lael-labs/linux

Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon+10−10

drivers/gpu/drm/xe/Kconfig+2−1

 config DRM_XE
 	tristate "Intel Xe Graphics"
 	depends on DRM && PCI && MMU && (m || (y && KUNIT=y))
+	depends on INTEL_VSEC || !INTEL_VSEC
+	depends on X86_PLATFORM_DEVICES || !(X86 && ACPI)
 	select INTERVAL_TREE
 	# we need shmfs for the swappable backing store, and in particular
 	# the shmem_readpage() which depends upon tmpfs
 	select BACKLIGHT_CLASS_DEVICE if ACPI
 	select INPUT if ACPI
 	select ACPI_VIDEO if X86 && ACPI
-	select X86_PLATFORM_DEVICES if X86 && ACPI
 	select ACPI_WMI if X86 && ACPI
 	select SYNC_FILE
 	select IOSF_MBI

drivers/gpu/drm/xe/regs/xe_mchbar_regs.h+5−5

@@ -38,10 +38,10 @@ · 37 unmodified lines
38	#define TEMP_MASK REG_GENMASK(7, 0)	38	#define TEMP_MASK REG_GENMASK(7, 0)
39		39
40	#define PCU_CR_PACKAGE_RAPL_LIMIT XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x59a0)	40	#define PCU_CR_PACKAGE_RAPL_LIMIT XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x59a0)
41	#define PKG_PWR_LIM_1 REG_GENMASK(14, 0)	41	#define PWR_LIM_VAL REG_GENMASK(14, 0)
42	#define PKG_PWR_LIM_1_EN REG_BIT(15)	42	#define PWR_LIM_EN REG_BIT(15)
43	#define PKG_PWR_LIM_1_TIME REG_GENMASK(23, 17)	43	#define PWR_LIM_TIME REG_GENMASK(23, 17)
44	#define PKG_PWR_LIM_1_TIME_X REG_GENMASK(23, 22)	44	#define PWR_LIM_TIME_X REG_GENMASK(23, 22)
45	#define PKG_PWR_LIM_1_TIME_Y REG_GENMASK(21, 17)	45	#define PWR_LIM_TIME_Y REG_GENMASK(21, 17)
46		46
47	#endif /* _XE_MCHBAR_REGS_H_ */	47	#endif /* _XE_MCHBAR_REGS_H_ */

drivers/gpu/drm/xe/regs/xe_pcode_regs.h+0−4

 #define PVC_GT0_PLATFORM_ENERGY_STATUS          XE_REG(0x28106c)
 #define PVC_GT0_PACKAGE_POWER_SKU               XE_REG(0x281080)
-#define BMG_PACKAGE_POWER_SKU			XE_REG(0x138098)
-#define BMG_PACKAGE_POWER_SKU_UNIT		XE_REG(0x1380dc)
 #define BMG_PACKAGE_ENERGY_STATUS		XE_REG(0x138120)
 #define BMG_FAN_1_SPEED				XE_REG(0x138140)
 #define BMG_FAN_2_SPEED				XE_REG(0x138170)
 #define BMG_FAN_3_SPEED				XE_REG(0x1381a0)
 #define BMG_VRAM_TEMPERATURE			XE_REG(0x1382c0)
 #define BMG_PACKAGE_TEMPERATURE			XE_REG(0x138434)
-#define BMG_PACKAGE_RAPL_LIMIT			XE_REG(0x138440)
 #define BMG_PLATFORM_ENERGY_STATUS		XE_REG(0x138458)
-#define BMG_PLATFORM_POWER_LIMIT		XE_REG(0x138460)
 #endif /* _XE_PCODE_REGS_H_ */

drivers/gpu/drm/xe/xe_bo.c+29−19

 		goto out;
 	}
-	/* Reject BO eviction if BO is bound to current VM. */
-	if (evict && ctx->resv) {
-		struct drm_gpuvm_bo *vm_bo;
-		drm_gem_for_each_gpuvm_bo(vm_bo, &bo->ttm.base) {
-			struct xe_vm *vm = gpuvm_to_vm(vm_bo->vm);
-			if (xe_vm_resv(vm) == ctx->resv &&
-			    xe_vm_in_preempt_fence_mode(vm)) {
-				ret = -EBUSY;
-				goto out;
-			}
-		}
-	}
 	/*
 	 * Failed multi-hop where the old_mem is still marked as
 	 * TTM_PL_FLAG_TEMPORARY, should just be a dummy move.
 	return lret;
 }
+static bool
+xe_bo_eviction_valuable(struct ttm_buffer_object *bo, const struct ttm_place *place)
+{
+	struct drm_gpuvm_bo *vm_bo;
+	if (!ttm_bo_eviction_valuable(bo, place))
+		return false;
+	if (!xe_bo_is_xe_bo(bo))
+		return true;
+	drm_gem_for_each_gpuvm_bo(vm_bo, &bo->base) {
+		if (xe_vm_is_validating(gpuvm_to_vm(vm_bo->vm)))
+			return false;
+	}
+	return true;
+}
 /**
  * xe_bo_shrink() - Try to shrink an xe bo.
  * @ctx: The struct ttm_operation_ctx used for shrinking.
 	    (flags.purge && !xe_tt->purgeable))
 		return -EBUSY;
-	if (!ttm_bo_eviction_valuable(bo, &place))
+	if (!xe_bo_eviction_valuable(bo, &place))
 		return -EBUSY;
 	if (!xe_bo_is_xe_bo(bo) || !xe_bo_get_unless_zero(xe_bo))
 	.io_mem_pfn = xe_ttm_io_mem_pfn,
 	.access_memory = xe_ttm_access_memory,
 	.release_notify = xe_ttm_bo_release_notify,
-	.eviction_valuable = ttm_bo_eviction_valuable,
+	.eviction_valuable = xe_bo_eviction_valuable,
 	.delete_mem_notify = xe_ttm_bo_delete_mem_notify,
 	.swap_notify = xe_ttm_bo_swap_notify,
 };
 		.no_wait_gpu = false,
 		.gfp_retry_mayfail = true,
 	};
+	struct pin_cookie cookie;
+	int ret;
 	if (vm) {
 		lockdep_assert_held(&vm->lock);
 		ctx.resv = xe_vm_resv(vm);
 	}
+	cookie = xe_vm_set_validating(vm, allow_res_evict);
 	trace_xe_bo_validate(bo);
-	return ttm_bo_validate(&bo->ttm, &bo->placement, &ctx);
+	ret = ttm_bo_validate(&bo->ttm, &bo->placement, &ctx);
+	xe_vm_clear_validating(vm, allow_res_evict, cookie);
+	return ret;
 }
 bool xe_bo_is_xe_bo(struct ttm_buffer_object *bo)
 					     u64 value);
 static const xe_gem_create_set_property_fn gem_create_set_property_funcs[] = {
-	[DRM_XE_GEM_CREATE_EXTENSION_SET_PROPERTY] = gem_create_set_pxp_type,
+	[DRM_XE_GEM_CREATE_SET_PROPERTY_PXP_TYPE] = gem_create_set_pxp_type,
 };
 static int gem_create_user_ext_set_property(struct xe_device *xe,

drivers/gpu/drm/xe/xe_device_sysfs.c+1−1

@@ -115,7 +115,7 @@ auto_link_downgrade_capable_show(struct device dev, struct device_attribute at · 114 unmodified lines
115	xe_pm_runtime_put(xe);	115	xe_pm_runtime_put(xe);
116		116
117	cap = REG_FIELD_GET(LINK_DOWNGRADE, val);	117	cap = REG_FIELD_GET(LINK_DOWNGRADE, val);
118	return sysfs_emit(buf, "%u\n", cap == DOWNGRADE_CAPABLE ? true : false);	118	return sysfs_emit(buf, "%u\n", cap == DOWNGRADE_CAPABLE);
119	}	119	}
120	static DEVICE_ATTR_ADMIN_RO(auto_link_downgrade_capable);	120	static DEVICE_ATTR_ADMIN_RO(auto_link_downgrade_capable);
121		121

drivers/gpu/drm/xe/xe_device_types.h+4−0

 		u8 has_heci_gscfi:1;
 		/** @info.has_llc: Device has a shared CPU+GPU last level cache */
 		u8 has_llc:1;
+		/** @info.has_mbx_power_limits: Device has support to manage power limits using
+		 * pcode mailbox commands.
+		 */
+		u8 has_mbx_power_limits:1;
 		/** @info.has_pxp: Device has PXP support */
 		u8 has_pxp:1;
 		/** @info.has_range_tlb_invalidation: Has range based TLB invalidations */

drivers/gpu/drm/xe/xe_exec_queue.c+1−14

 static int __xe_exec_queue_init(struct xe_exec_queue *q)
 {
-	struct xe_vm *vm = q->vm;
 	int i, err;
 	u32 flags = 0;
 			flags |= XE_LRC_CREATE_RUNALONE;
 	}
-	if (vm) {
-		err = xe_vm_lock(vm, true);
-		if (err)
-			return err;
-	}
 	for (i = 0; i < q->width; ++i) {
 		q->lrc[i] = xe_lrc_create(q->hwe, q->vm, SZ_16K, q->msix_vec, flags);
 		if (IS_ERR(q->lrc[i])) {
 			err = PTR_ERR(q->lrc[i]);
-			goto err_unlock;
+			goto err_lrc;
 		}
 	}
-	if (vm)
-		xe_vm_unlock(vm);
 	err = q->ops->init(q);
 	if (err)
 		goto err_lrc;
 	return 0;
-err_unlock:
-	if (vm)
-		xe_vm_unlock(vm);
 err_lrc:
 	for (i = i - 1; i >= 0; --i)
 		xe_lrc_put(q->lrc[i]);

drivers/gpu/drm/xe/xe_gpu_scheduler.h+9−1

@@ -51,7 +51,15 @@ static inline void xe_sched_tdr_queue_imm(struct xe_gpu_scheduler *sched) · 50 unmodified lines
51		51
52	static inline void xe_sched_resubmit_jobs(struct xe_gpu_scheduler *sched)	52	static inline void xe_sched_resubmit_jobs(struct xe_gpu_scheduler *sched)
53	{	53	{
54	drm_sched_resubmit_jobs(&sched->base);	54	struct drm_sched_job *s_job;
		55
		56	list_for_each_entry(s_job, &sched->base.pending_list, list) {
		57	struct drm_sched_fence *s_fence = s_job->s_fence;
		58	struct dma_fence *hw_fence = s_fence->parent;
		59
		60	if (hw_fence && !dma_fence_is_signaled(hw_fence))
		61	sched->base.ops->run_job(s_job);
		62	}
55	}	63	}
56		64
57	static inline bool	65	static inline bool

drivers/gpu/drm/xe/xe_guc_submit.c+11−0

@@ -229,6 +229,17 @@ static bool exec_queue_killed_or_banned_or_wedged(struct xe_exec_queue *q) · 228 unmodified lines
229	static void guc_submit_fini(struct drm_device drm, void arg)	229	static void guc_submit_fini(struct drm_device drm, void arg)
230	{	230	{
231	struct xe_guc *guc = arg;	231	struct xe_guc *guc = arg;
		232	struct xe_device *xe = guc_to_xe(guc);
		233	struct xe_gt *gt = guc_to_gt(guc);
		234	int ret;
		235
		236	ret = wait_event_timeout(guc->submission_state.fini_wq,
		237	xa_empty(&guc->submission_state.exec_queue_lookup),
		238	HZ * 5);
		239
		240	drain_workqueue(xe->destroy_wq);
		241
		242	xe_gt_assert(gt, ret);
232		243
233	xa_destroy(&guc->submission_state.exec_queue_lookup);	244	xa_destroy(&guc->submission_state.exec_queue_lookup);
234	}	245	}

drivers/gpu/drm/xe/xe_hwmon.c+285−99

@@ -51,6 +51,14 @@ enum xe_fan_channel { · 50 unmodified lines
51	FAN_MAX,	51	FAN_MAX,
52	};	52	};
53		53
		54	/*
		55	* For platforms that support mailbox commands for power limits, REG_PKG_POWER_SKU_UNIT is
		56	* not supported and below are SKU units to be used.
		57	*/
		58	#define PWR_UNIT 0x3
		59	#define ENERGY_UNIT 0xe
		60	#define TIME_UNIT 0xa
		61
54	/*	62	/*
55	* SF_* - scale factors for particular quantities according to hwmon spec.	63	* SF_* - scale factors for particular quantities according to hwmon spec.
56	*/	64	*/
@@ -60,6 +68,18 @@ enum xe_fan_channel { · 3 unmodified lines
60	#define SF_ENERGY 1000000 /* microjoules */	68	#define SF_ENERGY 1000000 /* microjoules */
61	#define SF_TIME 1000 /* milliseconds */	69	#define SF_TIME 1000 /* milliseconds */
62		70
		71	/*
		72	* PL*_HWMON_ATTR - mapping of hardware power limits to corresponding hwmon power attribute.
		73	*/
		74	#define PL1_HWMON_ATTR hwmon_power_max
		75
		76	#define PWR_ATTR_TO_STR(attr) (((attr) == hwmon_power_max) ? "PL1" : "Invalid")
		77
		78	/*
		79	* Timeout for power limit write mailbox command.
		80	*/
		81	#define PL_WRITE_MBX_TIMEOUT_MS (1)
		82
63	/**	83	/**
64	* struct xe_hwmon_energy_info - to accumulate energy	84	* struct xe_hwmon_energy_info - to accumulate energy
65	*/	85	*/
@@ -100,8 +120,80 @@ struct xe_hwmon { · 34 unmodified lines
100	struct xe_hwmon_energy_info ei[CHANNEL_MAX];	120	struct xe_hwmon_energy_info ei[CHANNEL_MAX];
101	/** @fi: Fan info for fanN_input */	121	/** @fi: Fan info for fanN_input */
102	struct xe_hwmon_fan_info fi[FAN_MAX];	122	struct xe_hwmon_fan_info fi[FAN_MAX];
		123	/** @boot_power_limit_read: is boot power limits read */
		124	bool boot_power_limit_read;
		125	/** @pl1_on_boot: power limit PL1 on boot */
		126	u32 pl1_on_boot[CHANNEL_MAX];
103	};	127	};
104		128
		129	static int xe_hwmon_pcode_read_power_limit(const struct xe_hwmon *hwmon, u32 attr, int channel,
		130	u32 *uval)
		131	{
		132	struct xe_tile *root_tile = xe_device_get_root_tile(hwmon->xe);
		133	u32 val0 = 0, val1 = 0;
		134	int ret = 0;
		135
		136	ret = xe_pcode_read(root_tile, PCODE_MBOX(PCODE_POWER_SETUP,
		137	(channel == CHANNEL_CARD) ?
		138	READ_PSYSGPU_POWER_LIMIT :
		139	READ_PACKAGE_POWER_LIMIT,
		140	hwmon->boot_power_limit_read ?
		141	READ_PL_FROM_PCODE : READ_PL_FROM_FW),
		142	&val0, &val1);
		143
		144	if (ret) {
		145	drm_dbg(&hwmon->xe->drm, "read failed ch %d val0 0x%08x, val1 0x%08x, ret %d\n",
		146	channel, val0, val1, ret);
		147	*uval = 0;
		148	return ret;
		149	}
		150
		151	/* return the value only if limit is enabled */
		152	if (attr == PL1_HWMON_ATTR)
		153	*uval = (val0 & PWR_LIM_EN) ? val0 : 0;
		154	else if (attr == hwmon_power_label)
		155	*uval = (val0 & PWR_LIM_EN) ? 1 : 0;
		156	else
		157	*uval = 0;
		158
		159	return ret;
		160	}
		161
		162	static int xe_hwmon_pcode_write_power_limit(const struct xe_hwmon *hwmon, u32 attr, u8 channel,
		163	u32 uval)
		164	{
		165	struct xe_tile *root_tile = xe_device_get_root_tile(hwmon->xe);
		166	u32 val0, val1;
		167	int ret = 0;
		168
		169	ret = xe_pcode_read(root_tile, PCODE_MBOX(PCODE_POWER_SETUP,
		170	(channel == CHANNEL_CARD) ?
		171	READ_PSYSGPU_POWER_LIMIT :
		172	READ_PACKAGE_POWER_LIMIT,
		173	hwmon->boot_power_limit_read ?
		174	READ_PL_FROM_PCODE : READ_PL_FROM_FW),
		175	&val0, &val1);
		176
		177	if (ret)
		178	drm_dbg(&hwmon->xe->drm, "read failed ch %d val0 0x%08x, val1 0x%08x, ret %d\n",
		179	channel, val0, val1, ret);
		180
		181	if (attr == PL1_HWMON_ATTR)
		182	val0 = uval;
		183	else
		184	return -EIO;
		185
		186	ret = xe_pcode_write64_timeout(root_tile, PCODE_MBOX(PCODE_POWER_SETUP,
		187	(channel == CHANNEL_CARD) ?
		188	WRITE_PSYSGPU_POWER_LIMIT :
		189	WRITE_PACKAGE_POWER_LIMIT, 0),
		190	val0, val1, PL_WRITE_MBX_TIMEOUT_MS);
		191	if (ret)
		192	drm_dbg(&hwmon->xe->drm, "write failed ch %d val0 0x%08x, val1 0x%08x, ret %d\n",
		193	channel, val0, val1, ret);
		194	return ret;
		195	}
		196
105	static struct xe_reg xe_hwmon_get_reg(struct xe_hwmon *hwmon, enum xe_hwmon_reg hwmon_reg,	197	static struct xe_reg xe_hwmon_get_reg(struct xe_hwmon *hwmon, enum xe_hwmon_reg hwmon_reg,
106	int channel)	198	int channel)
107	{	199	{
@@ -122,29 +214,19 @@ static struct xe_reg xe_hwmon_get_reg(struct xe_hwmon *hwmon, enum xe_hwmon_reg · 14 unmodified lines
122	}	214	}
123	break;	215	break;
124	case REG_PKG_RAPL_LIMIT:	216	case REG_PKG_RAPL_LIMIT:
125	if (xe->info.platform == XE_BATTLEMAGE) {	217	if (xe->info.platform == XE_PVC && channel == CHANNEL_PKG)
126	if (channel == CHANNEL_PKG)
127	return BMG_PACKAGE_RAPL_LIMIT;
128	else
129	return BMG_PLATFORM_POWER_LIMIT;
130	} else if (xe->info.platform == XE_PVC && channel == CHANNEL_PKG) {
131	return PVC_GT0_PACKAGE_RAPL_LIMIT;	218	return PVC_GT0_PACKAGE_RAPL_LIMIT;
132	} else if ((xe->info.platform == XE_DG2) && (channel == CHANNEL_PKG)) {	219	else if ((xe->info.platform == XE_DG2) && (channel == CHANNEL_PKG))
133	return PCU_CR_PACKAGE_RAPL_LIMIT;	220	return PCU_CR_PACKAGE_RAPL_LIMIT;
134	}
135	break;	221	break;
136	case REG_PKG_POWER_SKU:	222	case REG_PKG_POWER_SKU:
137	if (xe->info.platform == XE_BATTLEMAGE)	223	if (xe->info.platform == XE_PVC && channel == CHANNEL_PKG)
138	return BMG_PACKAGE_POWER_SKU;
139	else if (xe->info.platform == XE_PVC && channel == CHANNEL_PKG)
140	return PVC_GT0_PACKAGE_POWER_SKU;	224	return PVC_GT0_PACKAGE_POWER_SKU;
141	else if ((xe->info.platform == XE_DG2) && (channel == CHANNEL_PKG))	225	else if ((xe->info.platform == XE_DG2) && (channel == CHANNEL_PKG))
142	return PCU_CR_PACKAGE_POWER_SKU;	226	return PCU_CR_PACKAGE_POWER_SKU;
143	break;	227	break;
144	case REG_PKG_POWER_SKU_UNIT:	228	case REG_PKG_POWER_SKU_UNIT:
145	if (xe->info.platform == XE_BATTLEMAGE)	229	if (xe->info.platform == XE_PVC)
146	return BMG_PACKAGE_POWER_SKU_UNIT;
147	else if (xe->info.platform == XE_PVC)
148	return PVC_GT0_PACKAGE_POWER_SKU_UNIT;	230	return PVC_GT0_PACKAGE_POWER_SKU_UNIT;
149	else if (xe->info.platform == XE_DG2)	231	else if (xe->info.platform == XE_DG2)
150	return PCU_CR_PACKAGE_POWER_SKU_UNIT;	232	return PCU_CR_PACKAGE_POWER_SKU_UNIT;
@@ -181,7 +263,7 @@ static struct xe_reg xe_hwmon_get_reg(struct xe_hwmon *hwmon, enum xe_hwmon_reg · 30 unmodified lines
181	return XE_REG(0);	263	return XE_REG(0);
182	}	264	}
183		265
184	#define PL1_DISABLE 0	266	#define PL_DISABLE 0
185		267
186	/*	268	/*
187	* HW allows arbitrary PL1 limits to be set but silently clamps these values to	269	* HW allows arbitrary PL1 limits to be set but silently clamps these values to
@@ -189,67 +271,83 @@ static struct xe_reg xe_hwmon_get_reg(struct xe_hwmon *hwmon, enum xe_hwmon_reg · 1 unmodified line
189	* same pattern for sysfs, allow arbitrary PL1 limits to be set but display	271	* same pattern for sysfs, allow arbitrary PL1 limits to be set but display
190	* clamped values when read.	272	* clamped values when read.
191	*/	273	*/
192	static void xe_hwmon_power_max_read(struct xe_hwmon hwmon, int channel, long value)	274	static void xe_hwmon_power_max_read(struct xe_hwmon hwmon, u32 attr, int channel, long value)
193	{	275	{
194	u64 reg_val, min, max;	276	u64 reg_val, min, max;
195	struct xe_device *xe = hwmon->xe;	277	struct xe_device *xe = hwmon->xe;
196	struct xe_reg rapl_limit, pkg_power_sku;	278	struct xe_reg rapl_limit, pkg_power_sku;
197	struct xe_mmio *mmio = xe_root_tile_mmio(xe);	279	struct xe_mmio *mmio = xe_root_tile_mmio(xe);
198		280
199	rapl_limit = xe_hwmon_get_reg(hwmon, REG_PKG_RAPL_LIMIT, channel);	281	mutex_lock(&hwmon->hwmon_lock);
200	pkg_power_sku = xe_hwmon_get_reg(hwmon, REG_PKG_POWER_SKU, channel);
201		282
202	/*	283	if (hwmon->xe->info.has_mbx_power_limits) {
203	* Valid check of REG_PKG_RAPL_LIMIT is already done in xe_hwmon_power_is_visible.	284	xe_hwmon_pcode_read_power_limit(hwmon, attr, channel, (u32 *)&reg_val);
204	* So not checking it again here.	285	} else {
205	*/	286	rapl_limit = xe_hwmon_get_reg(hwmon, REG_PKG_RAPL_LIMIT, channel);
206	if (!xe_reg_is_valid(pkg_power_sku)) {	287	pkg_power_sku = xe_hwmon_get_reg(hwmon, REG_PKG_POWER_SKU, channel);
207	drm_warn(&xe->drm, "pkg_power_sku invalid\n");	288
208	*value = 0;	289	/*
209	return;	290	* Valid check of REG_PKG_RAPL_LIMIT is already done in xe_hwmon_power_is_visible.
		291	* So not checking it again here.
		292	*/
		293	if (!xe_reg_is_valid(pkg_power_sku)) {
		294	drm_warn(&xe->drm, "pkg_power_sku invalid\n");
		295	*value = 0;
		296	goto unlock;
		297	}
		298	reg_val = xe_mmio_read32(mmio, rapl_limit);
210	}	299	}
211		300
212	mutex_lock(&hwmon->hwmon_lock);	301	/* Check if PL limits are disabled. */
213		302	if (!(reg_val & PWR_LIM_EN)) {
214	reg_val = xe_mmio_read32(mmio, rapl_limit);	303	*value = PL_DISABLE;
215	/* Check if PL1 limit is disabled */	304	drm_info(&hwmon->xe->drm, "%s disabled for channel %d, val 0x%016llx\n",
216	if (!(reg_val & PKG_PWR_LIM_1_EN)) {	305	PWR_ATTR_TO_STR(attr), channel, reg_val);
217	*value = PL1_DISABLE;
218	goto unlock;	306	goto unlock;
219	}	307	}
220		308
221	reg_val = REG_FIELD_GET(PKG_PWR_LIM_1, reg_val);	309	reg_val = REG_FIELD_GET(PWR_LIM_VAL, reg_val);
222	*value = mul_u64_u32_shr(reg_val, SF_POWER, hwmon->scl_shift_power);	310	*value = mul_u64_u32_shr(reg_val, SF_POWER, hwmon->scl_shift_power);
223		311
224	reg_val = xe_mmio_read64_2x32(mmio, pkg_power_sku);	312	/* For platforms with mailbox power limit support clamping would be done by pcode. */
225	min = REG_FIELD_GET(PKG_MIN_PWR, reg_val);	313	if (!hwmon->xe->info.has_mbx_power_limits) {
226	min = mul_u64_u32_shr(min, SF_POWER, hwmon->scl_shift_power);	314	reg_val = xe_mmio_read64_2x32(mmio, pkg_power_sku);
227	max = REG_FIELD_GET(PKG_MAX_PWR, reg_val);	315	min = REG_FIELD_GET(PKG_MIN_PWR, reg_val);
228	max = mul_u64_u32_shr(max, SF_POWER, hwmon->scl_shift_power);	316	max = REG_FIELD_GET(PKG_MAX_PWR, reg_val);
229		317	min = mul_u64_u32_shr(min, SF_POWER, hwmon->scl_shift_power);
230	if (min && max)	318	max = mul_u64_u32_shr(max, SF_POWER, hwmon->scl_shift_power);
231	value = clamp_t(u64, value, min, max);	319	if (min && max)
		320	value = clamp_t(u64, value, min, max);
		321	}
232	unlock:	322	unlock:
233	mutex_unlock(&hwmon->hwmon_lock);	323	mutex_unlock(&hwmon->hwmon_lock);
234	}	324	}
235		325
236	static int xe_hwmon_power_max_write(struct xe_hwmon *hwmon, int channel, long value)	326	static int xe_hwmon_power_max_write(struct xe_hwmon *hwmon, u32 attr, int channel, long value)
237	{	327	{
238	struct xe_mmio *mmio = xe_root_tile_mmio(hwmon->xe);	328	struct xe_mmio *mmio = xe_root_tile_mmio(hwmon->xe);
239	int ret = 0;	329	int ret = 0;
240	u64 reg_val;	330	u32 reg_val;
241	struct xe_reg rapl_limit;	331	struct xe_reg rapl_limit;
242		332
		333	mutex_lock(&hwmon->hwmon_lock);
		334
243	rapl_limit = xe_hwmon_get_reg(hwmon, REG_PKG_RAPL_LIMIT, channel);	335	rapl_limit = xe_hwmon_get_reg(hwmon, REG_PKG_RAPL_LIMIT, channel);
244		336
245	mutex_lock(&hwmon->hwmon_lock);	337	/* Disable Power Limit and verify, as limit cannot be disabled on all platforms. */
		338	if (value == PL_DISABLE) {
		339	if (hwmon->xe->info.has_mbx_power_limits) {
		340	drm_dbg(&hwmon->xe->drm, "disabling %s on channel %d\n",
		341	PWR_ATTR_TO_STR(attr), channel);
		342	xe_hwmon_pcode_write_power_limit(hwmon, attr, channel, 0);
		343	xe_hwmon_pcode_read_power_limit(hwmon, attr, channel, &reg_val);
		344	} else {
		345	reg_val = xe_mmio_rmw32(mmio, rapl_limit, PWR_LIM_EN, 0);
		346	reg_val = xe_mmio_read32(mmio, rapl_limit);
		347	}
246		348
247	/* Disable PL1 limit and verify, as limit cannot be disabled on all platforms */	349	if (reg_val & PWR_LIM_EN) {
248	if (value == PL1_DISABLE) {	350	drm_warn(&hwmon->xe->drm, "Power limit disable is not supported!\n");
249	reg_val = xe_mmio_rmw32(mmio, rapl_limit, PKG_PWR_LIM_1_EN, 0);
250	reg_val = xe_mmio_read32(mmio, rapl_limit);
251	if (reg_val & PKG_PWR_LIM_1_EN) {
252	drm_warn(&hwmon->xe->drm, "PL1 disable is not supported!\n");
253	ret = -EOPNOTSUPP;	351	ret = -EOPNOTSUPP;
254	}	352	}
255	goto unlock;	353	goto unlock;
@@ -257,26 +355,50 @@ static int xe_hwmon_power_max_write(struct xe_hwmon *hwmon, int channel, long va · 1 unmodified line
257		355
258	/* Computation in 64-bits to avoid overflow. Round to nearest. */	356	/* Computation in 64-bits to avoid overflow. Round to nearest. */
259	reg_val = DIV_ROUND_CLOSEST_ULL((u64)value << hwmon->scl_shift_power, SF_POWER);	357	reg_val = DIV_ROUND_CLOSEST_ULL((u64)value << hwmon->scl_shift_power, SF_POWER);
260	reg_val = PKG_PWR_LIM_1_EN \| REG_FIELD_PREP(PKG_PWR_LIM_1, reg_val);	358	reg_val = PWR_LIM_EN \| REG_FIELD_PREP(PWR_LIM_VAL, reg_val);
261	reg_val = xe_mmio_rmw32(mmio, rapl_limit, PKG_PWR_LIM_1_EN \| PKG_PWR_LIM_1, reg_val);
262		359
		360	/*
		361	* Clamp power limit to card-firmware default as maximum, as an additional protection to
		362	* pcode clamp.
		363	*/
		364	if (hwmon->xe->info.has_mbx_power_limits) {
		365	if (reg_val > REG_FIELD_GET(PWR_LIM_VAL, hwmon->pl1_on_boot[channel])) {
		366	reg_val = REG_FIELD_GET(PWR_LIM_VAL, hwmon->pl1_on_boot[channel]);
		367	drm_dbg(&hwmon->xe->drm, "Clamping power limit to firmware default 0x%x\n",
		368	reg_val);
		369	}
		370	}
		371
		372	if (hwmon->xe->info.has_mbx_power_limits)
		373	ret = xe_hwmon_pcode_write_power_limit(hwmon, attr, channel, reg_val);
		374	else
		375	reg_val = xe_mmio_rmw32(mmio, rapl_limit, PWR_LIM_EN \| PWR_LIM_VAL,
		376	reg_val);
263	unlock:	377	unlock:
264	mutex_unlock(&hwmon->hwmon_lock);	378	mutex_unlock(&hwmon->hwmon_lock);
265	return ret;	379	return ret;
266	}	380	}
267		381
268	static void xe_hwmon_power_rated_max_read(struct xe_hwmon hwmon, int channel, long value)	382	static void xe_hwmon_power_rated_max_read(struct xe_hwmon *hwmon, u32 attr, int channel,
		383	long *value)
269	{	384	{
270	struct xe_mmio *mmio = xe_root_tile_mmio(hwmon->xe);	385	struct xe_mmio *mmio = xe_root_tile_mmio(hwmon->xe);
271	struct xe_reg reg = xe_hwmon_get_reg(hwmon, REG_PKG_POWER_SKU, channel);	386	u32 reg_val;
272	u64 reg_val;	387
		388	if (hwmon->xe->info.has_mbx_power_limits) {
		389	/* PL1 is rated max if supported. */
		390	xe_hwmon_pcode_read_power_limit(hwmon, PL1_HWMON_ATTR, channel, &reg_val);
		391	} else {
		392	/*
		393	* This sysfs file won't be visible if REG_PKG_POWER_SKU is invalid, so valid check
		394	* for this register can be skipped.
		395	* See xe_hwmon_power_is_visible.
		396	*/
		397	struct xe_reg reg = xe_hwmon_get_reg(hwmon, REG_PKG_POWER_SKU, channel);
		398
		399	reg_val = xe_mmio_read32(mmio, reg);
		400	}
273		401
274	/*
275	* This sysfs file won't be visible if REG_PKG_POWER_SKU is invalid, so valid check
276	* for this register can be skipped.
277	* See xe_hwmon_power_is_visible.
278	*/
279	reg_val = xe_mmio_read32(mmio, reg);
280	reg_val = REG_FIELD_GET(PKG_TDP, reg_val);	402	reg_val = REG_FIELD_GET(PKG_TDP, reg_val);
281	*value = mul_u64_u32_shr(reg_val, SF_POWER, hwmon->scl_shift_power);	403	*value = mul_u64_u32_shr(reg_val, SF_POWER, hwmon->scl_shift_power);
282	}	404	}
@@ -330,23 +452,35 @@ xe_hwmon_power_max_interval_show(struct device dev, struct device_attribute at · 47 unmodified lines
330	struct xe_mmio *mmio = xe_root_tile_mmio(hwmon->xe);	452	struct xe_mmio *mmio = xe_root_tile_mmio(hwmon->xe);
331	u32 x, y, x_w = 2; /* 2 bits */	453	u32 x, y, x_w = 2; /* 2 bits */
332	u64 r, tau4, out;	454	u64 r, tau4, out;
333	int sensor_index = to_sensor_dev_attr(attr)->index;	455	int channel = to_sensor_dev_attr(attr)->index;
		456	u32 power_attr = PL1_HWMON_ATTR;
		457	int ret = 0;
334		458
335	xe_pm_runtime_get(hwmon->xe);	459	xe_pm_runtime_get(hwmon->xe);
336		460
337	mutex_lock(&hwmon->hwmon_lock);	461	mutex_lock(&hwmon->hwmon_lock);
338		462
339	r = xe_mmio_read32(mmio, xe_hwmon_get_reg(hwmon, REG_PKG_RAPL_LIMIT, sensor_index));	463	if (hwmon->xe->info.has_mbx_power_limits) {
		464	ret = xe_hwmon_pcode_read_power_limit(hwmon, power_attr, channel, (u32 *)&r);
		465	if (ret) {
		466	drm_err(&hwmon->xe->drm,
		467	"power interval read fail, ch %d, attr %d, r 0%llx, ret %d\n",
		468	channel, power_attr, r, ret);
		469	r = 0;
		470	}
		471	} else {
		472	r = xe_mmio_read32(mmio, xe_hwmon_get_reg(hwmon, REG_PKG_RAPL_LIMIT, channel));
		473	}
340		474
341	mutex_unlock(&hwmon->hwmon_lock);	475	mutex_unlock(&hwmon->hwmon_lock);
342		476
343	xe_pm_runtime_put(hwmon->xe);	477	xe_pm_runtime_put(hwmon->xe);
344		478
345	x = REG_FIELD_GET(PKG_PWR_LIM_1_TIME_X, r);	479	x = REG_FIELD_GET(PWR_LIM_TIME_X, r);
346	y = REG_FIELD_GET(PKG_PWR_LIM_1_TIME_Y, r);	480	y = REG_FIELD_GET(PWR_LIM_TIME_Y, r);
347		481
348	/*	482	/*
349	* tau = 1.x * power(2,y), x = bits(23:22), y = bits(21:17)	483	* tau = (1 + (x / 4)) * power(2,y), x = bits(23:22), y = bits(21:17)
350	* = (4 \| x) << (y - 2)	484	* = (4 \| x) << (y - 2)
351	*	485	*
352	* Here (y - 2) ensures a 1.x fixed point representation of 1.x	486	* Here (y - 2) ensures a 1.x fixed point representation of 1.x
@@ -373,14 +507,15 @@ xe_hwmon_power_max_interval_store(struct device dev, struct device_attribute a · 20 unmodified lines
373	u64 tau4, r, max_win;	507	u64 tau4, r, max_win;
374	unsigned long val;	508	unsigned long val;
375	int ret;	509	int ret;
376	int sensor_index = to_sensor_dev_attr(attr)->index;	510	int channel = to_sensor_dev_attr(attr)->index;
		511	u32 power_attr = PL1_HWMON_ATTR;
377		512
378	ret = kstrtoul(buf, 0, &val);	513	ret = kstrtoul(buf, 0, &val);
379	if (ret)	514	if (ret)
380	return ret;	515	return ret;
381		516
382	/*	517	/*
383	* Max HW supported tau in '1.x * power(2,y)' format, x = 0, y = 0x12.	518	* Max HW supported tau in '(1 + (x / 4)) * power(2,y)' format, x = 0, y = 0x12.
384	* The hwmon->scl_shift_time default of 0xa results in a max tau of 256 seconds.	519	* The hwmon->scl_shift_time default of 0xa results in a max tau of 256 seconds.
385	*	520	*
386	* The ideal scenario is for PKG_MAX_WIN to be read from the PKG_PWR_SKU register.	521	* The ideal scenario is for PKG_MAX_WIN to be read from the PKG_PWR_SKU register.
@@ -400,11 +535,13 @@ xe_hwmon_power_max_interval_store(struct device dev, struct device_attribute a · 13 unmodified lines
400	tau4 = (u64)((1 << x_w) \| x) << y;	535	tau4 = (u64)((1 << x_w) \| x) << y;
401	max_win = mul_u64_u32_shr(tau4, SF_TIME, hwmon->scl_shift_time + x_w);	536	max_win = mul_u64_u32_shr(tau4, SF_TIME, hwmon->scl_shift_time + x_w);
402		537
403	if (val > max_win)	538	if (val > max_win) {
		539	drm_warn(&hwmon->xe->drm, "power_interval invalid val 0x%lx\n", val);
404	return -EINVAL;	540	return -EINVAL;
		541	}
405		542
406	/* val in hw units */	543	/* val in hw units */
407	val = DIV_ROUND_CLOSEST_ULL((u64)val << hwmon->scl_shift_time, SF_TIME);	544	val = DIV_ROUND_CLOSEST_ULL((u64)val << hwmon->scl_shift_time, SF_TIME) + 1;
408		545
409	/*	546	/*
410	* Convert val to 1.x * power(2,y)	547	* Convert val to 1.x * power(2,y)
@@ -419,14 +556,21 @@ xe_hwmon_power_max_interval_store(struct device dev, struct device_attribute a · 8 unmodified lines
419	x = (val - (1ul << y)) << x_w >> y;	556	x = (val - (1ul << y)) << x_w >> y;
420	}	557	}
421		558
422	rxy = REG_FIELD_PREP(PKG_PWR_LIM_1_TIME_X, x) \| REG_FIELD_PREP(PKG_PWR_LIM_1_TIME_Y, y);	559	rxy = REG_FIELD_PREP(PWR_LIM_TIME_X, x) \|
		560	REG_FIELD_PREP(PWR_LIM_TIME_Y, y);
423		561
424	xe_pm_runtime_get(hwmon->xe);	562	xe_pm_runtime_get(hwmon->xe);
425		563
426	mutex_lock(&hwmon->hwmon_lock);	564	mutex_lock(&hwmon->hwmon_lock);
427		565
428	r = xe_mmio_rmw32(mmio, xe_hwmon_get_reg(hwmon, REG_PKG_RAPL_LIMIT, sensor_index),	566	if (hwmon->xe->info.has_mbx_power_limits) {
429	PKG_PWR_LIM_1_TIME, rxy);	567	ret = xe_hwmon_pcode_read_power_limit(hwmon, power_attr, channel, (u32 *)&r);
		568	r = (r & ~PWR_LIM_TIME) \| rxy;
		569	xe_hwmon_pcode_write_power_limit(hwmon, power_attr, channel, r);
		570	} else {
		571	r = xe_mmio_rmw32(mmio, xe_hwmon_get_reg(hwmon, REG_PKG_RAPL_LIMIT, channel),
		572	PWR_LIM_TIME, rxy);
		573	}
430		574
431	mutex_unlock(&hwmon->hwmon_lock);	575	mutex_unlock(&hwmon->hwmon_lock);
432		576
@@ -435,6 +579,7 @@ xe_hwmon_power_max_interval_store(struct device dev, struct device_attribute a · 2 unmodified lines
435	return count;	579	return count;
436	}	580	}
437		581
		582	/* PSYS PL1 */
438	static SENSOR_DEVICE_ATTR(power1_max_interval, 0664,	583	static SENSOR_DEVICE_ATTR(power1_max_interval, 0664,
439	xe_hwmon_power_max_interval_show,	584	xe_hwmon_power_max_interval_show,
440	xe_hwmon_power_max_interval_store, CHANNEL_CARD);	585	xe_hwmon_power_max_interval_store, CHANNEL_CARD);
@@ -455,10 +600,19 @@ static umode_t xe_hwmon_attributes_visible(struct kobject *kobj, · 14 unmodified lines
455	struct device *dev = kobj_to_dev(kobj);	600	struct device *dev = kobj_to_dev(kobj);
456	struct xe_hwmon *hwmon = dev_get_drvdata(dev);	601	struct xe_hwmon *hwmon = dev_get_drvdata(dev);
457	int ret = 0;	602	int ret = 0;
		603	int channel = index ? CHANNEL_PKG : CHANNEL_CARD;
		604	u32 power_attr = PL1_HWMON_ATTR;
		605	u32 uval;
458		606
459	xe_pm_runtime_get(hwmon->xe);	607	xe_pm_runtime_get(hwmon->xe);
460		608
461	ret = xe_reg_is_valid(xe_hwmon_get_reg(hwmon, REG_PKG_RAPL_LIMIT, index)) ? attr->mode : 0;	609	if (hwmon->xe->info.has_mbx_power_limits) {
		610	xe_hwmon_pcode_read_power_limit(hwmon, power_attr, channel, &uval);
		611	ret = (uval & PWR_LIM_EN) ? attr->mode : 0;
		612	} else {
		613	ret = xe_reg_is_valid(xe_hwmon_get_reg(hwmon, REG_PKG_RAPL_LIMIT,
		614	channel)) ? attr->mode : 0;
		615	}
462		616
463	xe_pm_runtime_put(hwmon->xe);	617	xe_pm_runtime_put(hwmon->xe);
464		618
@@ -478,8 +632,8 @@ static const struct attribute_group *hwmon_groups[] = { · 13 unmodified lines
478	static const struct hwmon_channel_info * const hwmon_info[] = {	632	static const struct hwmon_channel_info * const hwmon_info[] = {
479	HWMON_CHANNEL_INFO(temp, HWMON_T_LABEL, HWMON_T_INPUT \| HWMON_T_LABEL,	633	HWMON_CHANNEL_INFO(temp, HWMON_T_LABEL, HWMON_T_INPUT \| HWMON_T_LABEL,
480	HWMON_T_INPUT \| HWMON_T_LABEL),	634	HWMON_T_INPUT \| HWMON_T_LABEL),
481	HWMON_CHANNEL_INFO(power, HWMON_P_MAX \| HWMON_P_RATED_MAX \| HWMON_P_LABEL,	635	HWMON_CHANNEL_INFO(power, HWMON_P_MAX \| HWMON_P_RATED_MAX \| HWMON_P_LABEL \| HWMON_P_CRIT,
482	HWMON_P_MAX \| HWMON_P_RATED_MAX \| HWMON_P_CRIT \| HWMON_P_LABEL),	636	HWMON_P_MAX \| HWMON_P_RATED_MAX \| HWMON_P_LABEL),
483	HWMON_CHANNEL_INFO(curr, HWMON_C_LABEL, HWMON_C_CRIT \| HWMON_C_LABEL),	637	HWMON_CHANNEL_INFO(curr, HWMON_C_LABEL, HWMON_C_CRIT \| HWMON_C_LABEL),
484	HWMON_CHANNEL_INFO(in, HWMON_I_INPUT \| HWMON_I_LABEL, HWMON_I_INPUT \| HWMON_I_LABEL),	638	HWMON_CHANNEL_INFO(in, HWMON_I_INPUT \| HWMON_I_LABEL, HWMON_I_INPUT \| HWMON_I_LABEL),
485	HWMON_CHANNEL_INFO(energy, HWMON_E_INPUT \| HWMON_E_LABEL, HWMON_E_INPUT \| HWMON_E_LABEL),	639	HWMON_CHANNEL_INFO(energy, HWMON_E_INPUT \| HWMON_E_LABEL, HWMON_E_INPUT \| HWMON_E_LABEL),
@@ -604,19 +758,27 @@ xe_hwmon_power_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel) · 118 unmodified lines
604		758
605	switch (attr) {	759	switch (attr) {
606	case hwmon_power_max:	760	case hwmon_power_max:
607	return xe_reg_is_valid(xe_hwmon_get_reg(hwmon, REG_PKG_RAPL_LIMIT,	761	if (hwmon->xe->info.has_mbx_power_limits) {
		762	xe_hwmon_pcode_read_power_limit(hwmon, attr, channel, &uval);
		763	return (uval) ? 0664 : 0;
		764	} else {
		765	return xe_reg_is_valid(xe_hwmon_get_reg(hwmon, REG_PKG_RAPL_LIMIT,
608	channel)) ? 0664 : 0;	766	channel)) ? 0664 : 0;
		767	}
609	case hwmon_power_rated_max:	768	case hwmon_power_rated_max:
610	return xe_reg_is_valid(xe_hwmon_get_reg(hwmon, REG_PKG_POWER_SKU,	769	if (hwmon->xe->info.has_mbx_power_limits)
611	channel)) ? 0444 : 0;	770	return 0;
		771	else
		772	return xe_reg_is_valid(xe_hwmon_get_reg(hwmon, REG_PKG_POWER_SKU,
		773	channel)) ? 0444 : 0;
612	case hwmon_power_crit:	774	case hwmon_power_crit:
613	if (channel == CHANNEL_PKG)
614	return (xe_hwmon_pcode_read_i1(hwmon, &uval) \|\|
615	!(uval & POWER_SETUP_I1_WATTS)) ? 0 : 0644;
616	break;
617	case hwmon_power_label:	775	case hwmon_power_label:
618	return xe_reg_is_valid(xe_hwmon_get_reg(hwmon, REG_PKG_POWER_SKU_UNIT,	776	if (channel == CHANNEL_CARD) {
619	channel)) ? 0444 : 0;	777	xe_hwmon_pcode_read_i1(hwmon, &uval);
		778	return (uval & POWER_SETUP_I1_WATTS) ? (attr == hwmon_power_label) ?
		779	0444 : 0644 : 0;
		780	}
		781	break;
620	default:	782	default:
621	return 0;	783	return 0;
622	}	784	}
@@ -628,10 +790,10 @@ xe_hwmon_power_read(struct xe_hwmon hwmon, u32 attr, int channel, long val) · 5 unmodified lines
628	{	790	{
629	switch (attr) {	791	switch (attr) {
630	case hwmon_power_max:	792	case hwmon_power_max:
631	xe_hwmon_power_max_read(hwmon, channel, val);	793	xe_hwmon_power_max_read(hwmon, attr, channel, val);
632	return 0;	794	return 0;
633	case hwmon_power_rated_max:	795	case hwmon_power_rated_max:
634	xe_hwmon_power_rated_max_read(hwmon, channel, val);	796	xe_hwmon_power_rated_max_read(hwmon, attr, channel, val);
635	return 0;	797	return 0;
636	case hwmon_power_crit:	798	case hwmon_power_crit:
637	return xe_hwmon_power_curr_crit_read(hwmon, channel, val, SF_POWER);	799	return xe_hwmon_power_curr_crit_read(hwmon, channel, val, SF_POWER);
@@ -645,7 +807,7 @@ xe_hwmon_power_write(struct xe_hwmon *hwmon, u32 attr, int channel, long val) · 7 unmodified lines
645	{	807	{
646	switch (attr) {	808	switch (attr) {
647	case hwmon_power_max:	809	case hwmon_power_max:
648	return xe_hwmon_power_max_write(hwmon, channel, val);	810	return xe_hwmon_power_max_write(hwmon, attr, channel, val);
649	case hwmon_power_crit:	811	case hwmon_power_crit:
650	return xe_hwmon_power_curr_crit_write(hwmon, channel, val, SF_POWER);	812	return xe_hwmon_power_curr_crit_write(hwmon, channel, val, SF_POWER);
651	default:	813	default:
@@ -965,18 +1127,42 @@ xe_hwmon_get_preregistration_info(struct xe_hwmon *hwmon) · 313 unmodified lines
965	int channel;	1127	int channel;
966	struct xe_reg pkg_power_sku_unit;	1128	struct xe_reg pkg_power_sku_unit;
967		1129
968	/*	1130	if (hwmon->xe->info.has_mbx_power_limits) {
969	* The contents of register PKG_POWER_SKU_UNIT do not change,	1131	/* Check if card firmware support mailbox power limits commands. */
970	* so read it once and store the shift values.	1132	if (xe_hwmon_pcode_read_power_limit(hwmon, PL1_HWMON_ATTR, CHANNEL_CARD,
971	*/	1133	&hwmon->pl1_on_boot[CHANNEL_CARD]) \|
972	pkg_power_sku_unit = xe_hwmon_get_reg(hwmon, REG_PKG_POWER_SKU_UNIT, 0);	1134	xe_hwmon_pcode_read_power_limit(hwmon, PL1_HWMON_ATTR, CHANNEL_PKG,
973	if (xe_reg_is_valid(pkg_power_sku_unit)) {	1135	&hwmon->pl1_on_boot[CHANNEL_PKG])) {
974	val_sku_unit = xe_mmio_read32(mmio, pkg_power_sku_unit);	1136	drm_warn(&hwmon->xe->drm,
975	hwmon->scl_shift_power = REG_FIELD_GET(PKG_PWR_UNIT, val_sku_unit);	1137	"Failed to read power limits, check card firmware !\n");
976	hwmon->scl_shift_energy = REG_FIELD_GET(PKG_ENERGY_UNIT, val_sku_unit);	1138	} else {
977	hwmon->scl_shift_time = REG_FIELD_GET(PKG_TIME_UNIT, val_sku_unit);	1139	drm_info(&hwmon->xe->drm, "Using mailbox commands for power limits\n");
		1140	/* Write default limits to read from pcode from now on. */
		1141	xe_hwmon_pcode_write_power_limit(hwmon, PL1_HWMON_ATTR,
		1142	CHANNEL_CARD,
		1143	hwmon->pl1_on_boot[CHANNEL_CARD]);
		1144	xe_hwmon_pcode_write_power_limit(hwmon, PL1_HWMON_ATTR,
		1145	CHANNEL_PKG,
		1146	hwmon->pl1_on_boot[CHANNEL_PKG]);
		1147	hwmon->scl_shift_power = PWR_UNIT;
		1148	hwmon->scl_shift_energy = ENERGY_UNIT;
		1149	hwmon->scl_shift_time = TIME_UNIT;
		1150	hwmon->boot_power_limit_read = true;
		1151	}
		1152	} else {
		1153	drm_info(&hwmon->xe->drm, "Using register for power limits\n");
		1154	/*
		1155	* The contents of register PKG_POWER_SKU_UNIT do not change,
		1156	* so read it once and store the shift values.
		1157	*/
		1158	pkg_power_sku_unit = xe_hwmon_get_reg(hwmon, REG_PKG_POWER_SKU_UNIT, 0);
		1159	if (xe_reg_is_valid(pkg_power_sku_unit)) {
		1160	val_sku_unit = xe_mmio_read32(mmio, pkg_power_sku_unit);
		1161	hwmon->scl_shift_power = REG_FIELD_GET(PKG_PWR_UNIT, val_sku_unit);
		1162	hwmon->scl_shift_energy = REG_FIELD_GET(PKG_ENERGY_UNIT, val_sku_unit);
		1163	hwmon->scl_shift_time = REG_FIELD_GET(PKG_TIME_UNIT, val_sku_unit);
		1164	}
978	}	1165	}
979
980	/*	1166	/*
981	* Initialize 'struct xe_hwmon_energy_info', i.e. set fields to the	1167	* Initialize 'struct xe_hwmon_energy_info', i.e. set fields to the
982	* first value of the energy register read	1168	* first value of the energy register read

drivers/gpu/drm/xe/xe_lrc.c+4−19

@@ -876,10 +876,7 @@ static void xe_lrc_set_ppgtt(struct xe_lrc lrc, struct xe_vm vm) · 875 unmodified lines
876	static void xe_lrc_finish(struct xe_lrc *lrc)	876	static void xe_lrc_finish(struct xe_lrc *lrc)
877	{	877	{
878	xe_hw_fence_ctx_finish(&lrc->fence_ctx);	878	xe_hw_fence_ctx_finish(&lrc->fence_ctx);
879	xe_bo_lock(lrc->bo, false);	879	xe_bo_unpin_map_no_vm(lrc->bo);
880	xe_bo_unpin(lrc->bo);
881	xe_bo_unlock(lrc->bo);
882	xe_bo_put(lrc->bo);
883	}	880	}
884		881
885	#define PVC_CTX_ASID (0x2e + 1)	882	#define PVC_CTX_ASID (0x2e + 1)
@@ -914,7 +911,7 @@ static int xe_lrc_init(struct xe_lrc lrc, struct xe_hw_engine hwe, · 28 unmodified lines
914	* FIXME: Perma-pinning LRC as we don't yet support moving GGTT address	911	* FIXME: Perma-pinning LRC as we don't yet support moving GGTT address
915	* via VM bind calls.	912	* via VM bind calls.
916	*/	913	*/
917	lrc->bo = xe_bo_create_pin_map(xe, tile, vm, lrc_size,	914	lrc->bo = xe_bo_create_pin_map(xe, tile, NULL, lrc_size,
918	ttm_bo_type_kernel,	915	ttm_bo_type_kernel,
919	bo_flags);	916	bo_flags);
920	if (IS_ERR(lrc->bo))	917	if (IS_ERR(lrc->bo))
@@ -1676,9 +1673,6 @@ struct xe_lrc_snapshot xe_lrc_snapshot_capture(struct xe_lrc lrc) · 755 unmodified lines
1676	if (!snapshot)	1673	if (!snapshot)
1677	return NULL;	1674	return NULL;
1678		1675
1679	if (lrc->bo->vm)
1680	xe_vm_get(lrc->bo->vm);
1681
1682	snapshot->context_desc = xe_lrc_ggtt_addr(lrc);	1676	snapshot->context_desc = xe_lrc_ggtt_addr(lrc);
1683	snapshot->ring_addr = __xe_lrc_ring_ggtt_addr(lrc);	1677	snapshot->ring_addr = __xe_lrc_ring_ggtt_addr(lrc);
1684	snapshot->indirect_context_desc = xe_lrc_indirect_ring_ggtt_addr(lrc);	1678	snapshot->indirect_context_desc = xe_lrc_indirect_ring_ggtt_addr(lrc);
@@ -1700,14 +1694,12 @@ struct xe_lrc_snapshot xe_lrc_snapshot_capture(struct xe_lrc lrc) · 15 unmodified lines
1700	void xe_lrc_snapshot_capture_delayed(struct xe_lrc_snapshot *snapshot)	1694	void xe_lrc_snapshot_capture_delayed(struct xe_lrc_snapshot *snapshot)
1701	{	1695	{
1702	struct xe_bo *bo;	1696	struct xe_bo *bo;
1703	struct xe_vm *vm;
1704	struct iosys_map src;	1697	struct iosys_map src;
1705		1698
1706	if (!snapshot)	1699	if (!snapshot)
1707	return;	1700	return;
1708		1701
1709	bo = snapshot->lrc_bo;	1702	bo = snapshot->lrc_bo;
1710	vm = bo->vm;
1711	snapshot->lrc_bo = NULL;	1703	snapshot->lrc_bo = NULL;
1712		1704
1713	snapshot->lrc_snapshot = kvmalloc(snapshot->lrc_size, GFP_KERNEL);	1705	snapshot->lrc_snapshot = kvmalloc(snapshot->lrc_size, GFP_KERNEL);
@@ -1727,8 +1719,6 @@ void xe_lrc_snapshot_capture_delayed(struct xe_lrc_snapshot *snapshot) · 13 unmodified lines
1727	xe_bo_unlock(bo);	1719	xe_bo_unlock(bo);
1728	put_bo:	1720	put_bo:
1729	xe_bo_put(bo);	1721	xe_bo_put(bo);
1730	if (vm)
1731	xe_vm_put(vm);
1732	}	1722	}
1733		1723
1734	void xe_lrc_snapshot_print(struct xe_lrc_snapshot snapshot, struct drm_printer p)	1724	void xe_lrc_snapshot_print(struct xe_lrc_snapshot snapshot, struct drm_printer p)
@@ -1781,14 +1771,9 @@ void xe_lrc_snapshot_free(struct xe_lrc_snapshot *snapshot) · 46 unmodified lines
1781	return;	1771	return;
1782		1772
1783	kvfree(snapshot->lrc_snapshot);	1773	kvfree(snapshot->lrc_snapshot);
1784	if (snapshot->lrc_bo) {	1774	if (snapshot->lrc_bo)
1785	struct xe_vm *vm;
1786
1787	vm = snapshot->lrc_bo->vm;
1788	xe_bo_put(snapshot->lrc_bo);	1775	xe_bo_put(snapshot->lrc_bo);
1789	if (vm)	1776
1790	xe_vm_put(vm);
1791	}
1792	kfree(snapshot);	1777	kfree(snapshot);
1793	}	1778	}
1794		1779

drivers/gpu/drm/xe/xe_pci.c+5−0

 	u8 has_heci_gscfi:1;
 	u8 has_heci_cscfi:1;
 	u8 has_llc:1;
+	u8 has_mbx_power_limits:1;
 	u8 has_pxp:1;
 	u8 has_sriov:1;
 	u8 needs_scratch:1;
 	DG2_FEATURES,
 	.has_display = true,
 	.has_fan_control = true,
+	.has_mbx_power_limits = false,
 };
 static const __maybe_unused struct xe_device_desc pvc_desc = {
 	.has_heci_gscfi = 1,
 	.max_remote_tiles = 1,
 	.require_force_probe = true,
+	.has_mbx_power_limits = false,
 };
 static const struct xe_device_desc mtl_desc = {
 	.dma_mask_size = 46,
 	.has_display = true,
 	.has_fan_control = true,
+	.has_mbx_power_limits = true,
 	.has_heci_cscfi = 1,
 	.needs_scratch = true,
 };
 	xe->info.dma_mask_size = desc->dma_mask_size;
 	xe->info.is_dgfx = desc->is_dgfx;
 	xe->info.has_fan_control = desc->has_fan_control;
+	xe->info.has_mbx_power_limits = desc->has_mbx_power_limits;
 	xe->info.has_heci_gscfi = desc->has_heci_gscfi;
 	xe->info.has_heci_cscfi = desc->has_heci_cscfi;
 	xe->info.has_llc = desc->has_llc;

drivers/gpu/drm/xe/xe_pcode.c+11−0

@@ -109,6 +109,17 @@ int xe_pcode_write_timeout(struct xe_tile *tile, u32 mbox, u32 data, int timeout · 108 unmodified lines
109	return err;	109	return err;
110	}	110	}
111		111
		112	int xe_pcode_write64_timeout(struct xe_tile *tile, u32 mbox, u32 data0, u32 data1, int timeout)
		113	{
		114	int err;
		115
		116	mutex_lock(&tile->pcode.lock);
		117	err = pcode_mailbox_rw(tile, mbox, &data0, &data1, timeout, false, false);
		118	mutex_unlock(&tile->pcode.lock);
		119
		120	return err;
		121	}
		122
112	int xe_pcode_read(struct xe_tile tile, u32 mbox, u32 val, u32 *val1)	123	int xe_pcode_read(struct xe_tile tile, u32 mbox, u32 val, u32 *val1)
113	{	124	{
114	int err;	125	int err;

drivers/gpu/drm/xe/xe_pcode.h+3−0

@@ -18,6 +18,9 @@ int xe_pcode_init_min_freq_table(struct xe_tile *tile, u32 min_gt_freq, · 17 unmodified lines
18	int xe_pcode_read(struct xe_tile tile, u32 mbox, u32 val, u32 *val1);	18	int xe_pcode_read(struct xe_tile tile, u32 mbox, u32 val, u32 *val1);
19	int xe_pcode_write_timeout(struct xe_tile *tile, u32 mbox, u32 val,	19	int xe_pcode_write_timeout(struct xe_tile *tile, u32 mbox, u32 val,
20	int timeout_ms);	20	int timeout_ms);
		21	int xe_pcode_write64_timeout(struct xe_tile *tile, u32 mbox, u32 data0,
		22	u32 data1, int timeout);
		23
21	#define xe_pcode_write(tile, mbox, val) \	24	#define xe_pcode_write(tile, mbox, val) \
22	xe_pcode_write_timeout(tile, mbox, val, 1)	25	xe_pcode_write_timeout(tile, mbox, val, 1)
23		26

drivers/gpu/drm/xe/xe_pcode_api.h+7−0

@@ -43,6 +43,13 @@ · 42 unmodified lines
43	#define POWER_SETUP_I1_SHIFT 6 /* 10.6 fixed point format */	43	#define POWER_SETUP_I1_SHIFT 6 /* 10.6 fixed point format */
44	#define POWER_SETUP_I1_DATA_MASK REG_GENMASK(15, 0)	44	#define POWER_SETUP_I1_DATA_MASK REG_GENMASK(15, 0)
45		45
		46	#define READ_PSYSGPU_POWER_LIMIT 0x6
		47	#define WRITE_PSYSGPU_POWER_LIMIT 0x7
		48	#define READ_PACKAGE_POWER_LIMIT 0x8
		49	#define WRITE_PACKAGE_POWER_LIMIT 0x9
		50	#define READ_PL_FROM_FW 0x1
		51	#define READ_PL_FROM_PCODE 0x0
		52
46	#define PCODE_FREQUENCY_CONFIG 0x6e	53	#define PCODE_FREQUENCY_CONFIG 0x6e
47	/* Frequency Config Sub Commands (param1) */	54	/* Frequency Config Sub Commands (param1) */
48	#define PCODE_MBOX_FC_SC_READ_FUSED_P0 0x0	55	#define PCODE_MBOX_FC_SC_READ_FUSED_P0 0x0

drivers/gpu/drm/xe/xe_pxp.c+6−2

 	 */
 	xe_pm_runtime_get(pxp->xe);
-	if (!pxp_prerequisites_done(pxp)) {
+	/* get_readiness_status() returns 0 for in-progress and 1 for done */
-		ret = -EBUSY;
+	ret = xe_pxp_get_readiness_status(pxp);
+	if (ret <= 0) {
+		if (!ret)
+			ret = -EBUSY;
 		goto out;
 	}
+	ret = 0;
 wait_for_idle:
 	/*

drivers/gpu/drm/xe/xe_vm.c+16−11

 	 * scheduler drops all the references of it, hence protecting the VM
 	 * for this case is necessary.
 	 */
-	if (flags & XE_VM_FLAG_LR_MODE)
+	if (flags & XE_VM_FLAG_LR_MODE) {
+		INIT_WORK(&vm->preempt.rebind_work, preempt_rebind_work_func);
 		xe_pm_runtime_get_noresume(xe);
+	}
+	if (flags & XE_VM_FLAG_FAULT_MODE) {
+		err = xe_svm_init(vm);
+		if (err)
+			goto err_no_resv;
+	}
 	vm_resv_obj = drm_gpuvm_resv_object_alloc(&xe->drm);
 	if (!vm_resv_obj) {
 		err = -ENOMEM;
-		goto err_no_resv;
+		goto err_svm_fini;
 	}
 	drm_gpuvm_init(&vm->gpuvm, "Xe VM", DRM_GPUVM_RESV_PROTECTED, &xe->drm,
 		vm->batch_invalidate_tlb = true;
 	}
-	if (vm->flags & XE_VM_FLAG_LR_MODE) {
+	if (vm->flags & XE_VM_FLAG_LR_MODE)
-		INIT_WORK(&vm->preempt.rebind_work, preempt_rebind_work_func);
 		vm->batch_invalidate_tlb = false;
-	}
 	/* Fill pt_root after allocating scratch tables */
 	for_each_tile(tile, xe, id) {
 		}
 	}
-	if (flags & XE_VM_FLAG_FAULT_MODE) {
-		err = xe_svm_init(vm);
-		if (err)
-			goto err_close;
-	}
 	if (number_tiles > 1)
 		vm->composite_fence_ctx = dma_fence_context_alloc(1);
 	xe_vm_close_and_put(vm);
 	return ERR_PTR(err);
+err_svm_fini:
+	if (flags & XE_VM_FLAG_FAULT_MODE) {
+		vm->size = 0; /* close the vm */
+		xe_svm_fini(vm);
+	}
 err_no_resv:
 	mutex_destroy(&vm->snap_mutex);
 	for_each_tile(tile, xe, id)

drivers/gpu/drm/xe/xe_vm.h+69−0

@@ -301,6 +301,75 @@ void xe_vm_snapshot_capture_delayed(struct xe_vm_snapshot *snap); · 300 unmodified lines
301	void xe_vm_snapshot_print(struct xe_vm_snapshot snap, struct drm_printer p);	301	void xe_vm_snapshot_print(struct xe_vm_snapshot snap, struct drm_printer p);
302	void xe_vm_snapshot_free(struct xe_vm_snapshot *snap);	302	void xe_vm_snapshot_free(struct xe_vm_snapshot *snap);
303		303
		304	/**
		305	* xe_vm_set_validating() - Register this task as currently making bos resident
		306	* @allow_res_evict: Allow eviction of buffer objects bound to @vm when
		307	* validating.
		308	* @vm: Pointer to the vm or NULL.
		309	*
		310	* Register this task as currently making bos resident for the vm. Intended
		311	* to avoid eviction by the same task of shared bos bound to the vm.
		312	* Call with the vm's resv lock held.
		313	*
		314	* Return: A pin cookie that should be used for xe_vm_clear_validating().
		315	*/
		316	static inline struct pin_cookie xe_vm_set_validating(struct xe_vm *vm,
		317	bool allow_res_evict)
		318	{
		319	struct pin_cookie cookie = {};
		320
		321	if (vm && !allow_res_evict) {
		322	xe_vm_assert_held(vm);
		323	cookie = lockdep_pin_lock(&xe_vm_resv(vm)->lock.base);
		324	/* Pairs with READ_ONCE in xe_vm_is_validating() */
		325	WRITE_ONCE(vm->validating, current);
		326	}
		327
		328	return cookie;
		329	}
		330
		331	/**
		332	* xe_vm_clear_validating() - Unregister this task as currently making bos resident
		333	* @vm: Pointer to the vm or NULL
		334	* @allow_res_evict: Eviction from @vm was allowed. Must be set to the same
		335	* value as for xe_vm_set_validation().
		336	* @cookie: Cookie obtained from xe_vm_set_validating().
		337	*
		338	* Register this task as currently making bos resident for the vm. Intended
		339	* to avoid eviction by the same task of shared bos bound to the vm.
		340	* Call with the vm's resv lock held.
		341	*/
		342	static inline void xe_vm_clear_validating(struct xe_vm *vm, bool allow_res_evict,
		343	struct pin_cookie cookie)
		344	{
		345	if (vm && !allow_res_evict) {
		346	lockdep_unpin_lock(&xe_vm_resv(vm)->lock.base, cookie);
		347	/* Pairs with READ_ONCE in xe_vm_is_validating() */
		348	WRITE_ONCE(vm->validating, NULL);
		349	}
		350	}
		351
		352	/**
		353	* xe_vm_is_validating() - Whether bos bound to the vm are currently being made resident
		354	* by the current task.
		355	* @vm: Pointer to the vm.
		356	*
		357	* If this function returns %true, we should be in a vm resv locked region, since
		358	* the current process is the same task that called xe_vm_set_validating().
		359	* The function asserts that that's indeed the case.
		360	*
		361	* Return: %true if the task is currently making bos resident, %false otherwise.
		362	*/
		363	static inline bool xe_vm_is_validating(struct xe_vm *vm)
		364	{
		365	/* Pairs with WRITE_ONCE in xe_vm_is_validating() */
		366	if (READ_ONCE(vm->validating) == current) {
		367	xe_vm_assert_held(vm);
		368	return true;
		369	}
		370	return false;
		371	}
		372
304	#if IS_ENABLED(CONFIG_DRM_XE_USERPTR_INVAL_INJECT)	373	#if IS_ENABLED(CONFIG_DRM_XE_USERPTR_INVAL_INJECT)
305	void xe_vma_userptr_force_invalidate(struct xe_userptr_vma *uvma);	374	void xe_vma_userptr_force_invalidate(struct xe_userptr_vma *uvma);
306	#else	375	#else

drivers/gpu/drm/xe/xe_vm_types.h+8−0

@@ -310,6 +310,14 @@ struct xe_vm { · 309 unmodified lines
310	* protected by the vm resv.	310	* protected by the vm resv.
311	*/	311	*/
312	u64 tlb_flush_seqno;	312	u64 tlb_flush_seqno;
		313	/**
		314	* @validating: The task that is currently making bos resident for this vm.
		315	* Protected by the VM's resv for writing. Opportunistic reading can be done
		316	* using READ_ONCE. Note: This is a workaround for the
		317	* TTM eviction_valuable() callback not being passed a struct
		318	* ttm_operation_context(). Future work might want to address this.
		319	*/
		320	struct task_struct *validating;
313	/** @batch_invalidate_tlb: Always invalidate TLB before batch start */	321	/** @batch_invalidate_tlb: Always invalidate TLB before batch start */
314	bool batch_invalidate_tlb;	322	bool batch_invalidate_tlb;
315	/** @xef: XE file handle for tracking this VM's drm client */	323	/** @xef: XE file handle for tracking this VM's drm client */

include/uapi/drm/xe_drm.h+5−0

  *    there is no need to explicitly set that. When a queue of type
  *    %DRM_XE_PXP_TYPE_HWDRM is created, the PXP default HWDRM session
  *    (%XE_PXP_HWDRM_DEFAULT_SESSION) will be started, if isn't already running.
+ *    The user is expected to query the PXP status via the query ioctl (see
+ *    %DRM_XE_DEVICE_QUERY_PXP_STATUS) and to wait for PXP to be ready before
+ *    attempting to create a queue with this property. When a queue is created
+ *    before PXP is ready, the ioctl will return -EBUSY if init is still in
+ *    progress or -EIO if init failed.
  *    Given that going into a power-saving state kills PXP HWDRM sessions,
  *    runtime PM will be blocked while queues of this type are alive.
  *    All PXP queues will be killed if a PXP invalidation event occurs.

@@ -60,26 +60,26 @@ Description: RO. Package default power limit (default TDP setting). · 59 unmodified lines
60		60
61	Only supported for particular Intel Xe graphics platforms.	61	Only supported for particular Intel Xe graphics platforms.
62		62
63	What: /sys/bus/pci/drivers/xe/.../hwmon/hwmon<i>/power2_crit	63	What: /sys/bus/pci/drivers/xe/.../hwmon/hwmon<i>/power1_crit
64	Date: February 2024	64	Date: May 2025
65	KernelVersion: 6.8	65	KernelVersion: 6.15
66	Contact: intel-xe@lists.freedesktop.org	66	Contact: intel-xe@lists.freedesktop.org
67	Description: RW. Package reactive critical (I1) power limit in microwatts.	67	Description: RW. Card reactive critical (I1) power limit in microwatts.
68		68
69	Package reactive critical (I1) power limit in microwatts is exposed	69	Card reactive critical (I1) power limit in microwatts is exposed
70	for client products. The power controller will throttle the	70	for client products. The power controller will throttle the
71	operating frequency if the power averaged over a window exceeds	71	operating frequency if the power averaged over a window exceeds
72	this limit.	72	this limit.
73		73
74	Only supported for particular Intel Xe graphics platforms.	74	Only supported for particular Intel Xe graphics platforms.
75		75
76	What: /sys/bus/pci/drivers/xe/.../hwmon/hwmon<i>/curr2_crit	76	What: /sys/bus/pci/drivers/xe/.../hwmon/hwmon<i>/curr1_crit
77	Date: February 2024	77	Date: May 2025
78	KernelVersion: 6.8	78	KernelVersion: 6.15
79	Contact: intel-xe@lists.freedesktop.org	79	Contact: intel-xe@lists.freedesktop.org
80	Description: RW. Package reactive critical (I1) power limit in milliamperes.	80	Description: RW. Card reactive critical (I1) power limit in milliamperes.
81		81
82	Package reactive critical (I1) power limit in milliamperes is	82	Card reactive critical (I1) power limit in milliamperes is
83	exposed for server products. The power controller will throttle	83	exposed for server products. The power controller will throttle
84	the operating frequency if the power averaged over a window	84	the operating frequency if the power averaged over a window
85	exceeds this limit.	85	exceeds this limit.