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Merge tag 'iommu-updates-v5.6' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu

Pull iommu updates from Joerg Roedel: - Allow compiling the ARM-SMMU drivers as modules. - Fixes and cleanups for the ARM-SMMU drivers and io-pgtable code collected by Will Deacon. The merge-commit (6855d1ba7537) has all the details. - Cleanup of the iommu_put_resv_regions() call-backs in various drivers. - AMD IOMMU driver cleanups. - Update for the x2APIC support in the AMD IOMMU driver. - Preparation patches for Intel VT-d nested mode support. - RMRR and identity domain handling fixes for the Intel VT-d driver. - More small fixes and cleanups. * tag 'iommu-updates-v5.6' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu: (87 commits) iommu/amd: Remove the unnecessary assignment iommu/vt-d: Remove unnecessary WARN_ON_ONCE() iommu/vt-d: Unnecessary to handle default identity domain iommu/vt-d: Allow devices with RMRRs to use identity domain iommu/vt-d: Add RMRR base and end addresses sanity check iommu/vt-d: Mark firmware tainted if RMRR fails sanity check iommu/amd: Remove unused struct member iommu/amd: Replace two consecutive readl calls with one readq iommu/vt-d: Don't reject Host Bridge due to scope mismatch PCI/ATS: Add PASID stubs iommu/arm-smmu-v3: Return -EBUSY when trying to re-add a device iommu/arm-smmu-v3: Improve add_device() error handling iommu/arm-smmu-v3: Use WRITE_ONCE() when changing validity of an STE iommu/arm-smmu-v3: Add second level of context descriptor table iommu/arm-smmu-v3: Prepare for handling arm_smmu_write_ctx_desc() failure iommu/arm-smmu-v3: Propagate ssid_bits iommu/arm-smmu-v3: Add support for Substream IDs iommu/arm-smmu-v3: Add context descriptor tables allocators iommu/arm-smmu-v3: Prepare arm_smmu_s1_cfg for SSID support ACPI/IORT: Parse SSID property of named component node ...

Linus Torvalds committed 6 years ago

Commit 4fc2ea62 parents d271ab2 e3b5ee036 files · +1686 −822Browse files

Showing the changes to include/linux (4 of 36 files). Show all

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4 files
  1. include/linux/intel-iommu.h +18 −7
  2. include/linux/io-pgtable.h +23 −4
  3. include/linux/iommu.h +16 −3
  4. include/linux/pci-ats.h +3 −0
include/linux/intel-iommu.h+18−7
@@ -34,10 +34,13 @@ · 33 unmodified lines
34#define VTD_STRIDE_SHIFT (9)34#define VTD_STRIDE_SHIFT (9)
35#define VTD_STRIDE_MASK (((u64)-1) << VTD_STRIDE_SHIFT)35#define VTD_STRIDE_MASK (((u64)-1) << VTD_STRIDE_SHIFT)
36 36
37#define DMA_PTE_READ (1)37#define DMA_PTE_READ BIT_ULL(0)
38#define DMA_PTE_WRITE (2)38#define DMA_PTE_WRITE BIT_ULL(1)
39#define DMA_PTE_LARGE_PAGE (1 << 7)39#define DMA_PTE_LARGE_PAGE BIT_ULL(7)
40#define DMA_PTE_SNP (1 << 11)40#define DMA_PTE_SNP BIT_ULL(11)
41
42#define DMA_FL_PTE_PRESENT BIT_ULL(0)
43#define DMA_FL_PTE_XD BIT_ULL(63)
41 44
42#define CONTEXT_TT_MULTI_LEVEL 045#define CONTEXT_TT_MULTI_LEVEL 0
43#define CONTEXT_TT_DEV_IOTLB 146#define CONTEXT_TT_DEV_IOTLB 1
@@ -435,8 +438,10 @@ enum { · 391 unmodified lines
435 438
436#define VTD_FLAG_TRANS_PRE_ENABLED (1 << 0)439#define VTD_FLAG_TRANS_PRE_ENABLED (1 << 0)
437#define VTD_FLAG_IRQ_REMAP_PRE_ENABLED (1 << 1)440#define VTD_FLAG_IRQ_REMAP_PRE_ENABLED (1 << 1)
441#define VTD_FLAG_SVM_CAPABLE (1 << 2)
438 442
439extern int intel_iommu_sm;443extern int intel_iommu_sm;
444extern spinlock_t device_domain_lock;
440 445
441#define sm_supported(iommu) (intel_iommu_sm && ecap_smts((iommu)->ecap))446#define sm_supported(iommu) (intel_iommu_sm && ecap_smts((iommu)->ecap))
442#define pasid_supported(iommu) (sm_supported(iommu) && \447#define pasid_supported(iommu) (sm_supported(iommu) && \
@@ -609,10 +614,11 @@ static inline void dma_clear_pte(struct dma_pte *pte) · 166 unmodified lines
609static inline u64 dma_pte_addr(struct dma_pte *pte)614static inline u64 dma_pte_addr(struct dma_pte *pte)
610{615{
611#ifdef CONFIG_64BIT616#ifdef CONFIG_64BIT
612 return pte->val & VTD_PAGE_MASK;617 return pte->val & VTD_PAGE_MASK & (~DMA_FL_PTE_XD);
613#else618#else
614 /* Must have a full atomic 64-bit read */619 /* Must have a full atomic 64-bit read */
615 return __cmpxchg64(&pte->val, 0ULL, 0ULL) & VTD_PAGE_MASK;620 return __cmpxchg64(&pte->val, 0ULL, 0ULL) &
621 VTD_PAGE_MASK & (~DMA_FL_PTE_XD);
616#endif622#endif
617}623}
618 624
@@ -645,6 +651,8 @@ extern void qi_flush_iotlb(struct intel_iommu *iommu, u16 did, u64 addr, · 26 unmodified lines
645 unsigned int size_order, u64 type);651 unsigned int size_order, u64 type);
646extern void qi_flush_dev_iotlb(struct intel_iommu *iommu, u16 sid, u16 pfsid,652extern void qi_flush_dev_iotlb(struct intel_iommu *iommu, u16 sid, u16 pfsid,
647 u16 qdep, u64 addr, unsigned mask);653 u16 qdep, u64 addr, unsigned mask);
654void qi_flush_piotlb(struct intel_iommu *iommu, u16 did, u32 pasid, u64 addr,
655 unsigned long npages, bool ih);
648extern int qi_submit_sync(struct qi_desc *desc, struct intel_iommu *iommu);656extern int qi_submit_sync(struct qi_desc *desc, struct intel_iommu *iommu);
649 657
650extern int dmar_ir_support(void);658extern int dmar_ir_support(void);
@@ -656,9 +664,10 @@ int for_each_device_domain(int (*fn)(struct device_domain_info *info, · 5 unmodified lines
656 void *data), void *data);664 void *data), void *data);
657void iommu_flush_write_buffer(struct intel_iommu *iommu);665void iommu_flush_write_buffer(struct intel_iommu *iommu);
658int intel_iommu_enable_pasid(struct intel_iommu *iommu, struct device *dev);666int intel_iommu_enable_pasid(struct intel_iommu *iommu, struct device *dev);
667struct dmar_domain *find_domain(struct device *dev);
659 668
660#ifdef CONFIG_INTEL_IOMMU_SVM669#ifdef CONFIG_INTEL_IOMMU_SVM
661int intel_svm_init(struct intel_iommu *iommu);670extern void intel_svm_check(struct intel_iommu *iommu);
662extern int intel_svm_enable_prq(struct intel_iommu *iommu);671extern int intel_svm_enable_prq(struct intel_iommu *iommu);
663extern int intel_svm_finish_prq(struct intel_iommu *iommu);672extern int intel_svm_finish_prq(struct intel_iommu *iommu);
664 673
@@ -686,6 +695,8 @@ struct intel_svm { · 21 unmodified lines
686};695};
687 696
688extern struct intel_iommu *intel_svm_device_to_iommu(struct device *dev);697extern struct intel_iommu *intel_svm_device_to_iommu(struct device *dev);
698#else
699static inline void intel_svm_check(struct intel_iommu *iommu) {}
689#endif700#endif
690 701
691#ifdef CONFIG_INTEL_IOMMU_DEBUGFS702#ifdef CONFIG_INTEL_IOMMU_DEBUGFS
include/linux/io-pgtable.h+23−4
@@ -83,12 +83,16 @@ struct io_pgtable_cfg { · 82 unmodified lines
83 * IO_PGTABLE_QUIRK_NON_STRICT: Skip issuing synchronous leaf TLBIs83 * IO_PGTABLE_QUIRK_NON_STRICT: Skip issuing synchronous leaf TLBIs
84 * on unmap, for DMA domains using the flush queue mechanism for84 * on unmap, for DMA domains using the flush queue mechanism for
85 * delayed invalidation.85 * delayed invalidation.
86 *
87 * IO_PGTABLE_QUIRK_ARM_TTBR1: (ARM LPAE format) Configure the table
88 * for use in the upper half of a split address space.
86 */89 */
87 #define IO_PGTABLE_QUIRK_ARM_NS BIT(0)90 #define IO_PGTABLE_QUIRK_ARM_NS BIT(0)
88 #define IO_PGTABLE_QUIRK_NO_PERMS BIT(1)91 #define IO_PGTABLE_QUIRK_NO_PERMS BIT(1)
89 #define IO_PGTABLE_QUIRK_TLBI_ON_MAP BIT(2)92 #define IO_PGTABLE_QUIRK_TLBI_ON_MAP BIT(2)
90 #define IO_PGTABLE_QUIRK_ARM_MTK_EXT BIT(3)93 #define IO_PGTABLE_QUIRK_ARM_MTK_EXT BIT(3)
91 #define IO_PGTABLE_QUIRK_NON_STRICT BIT(4)94 #define IO_PGTABLE_QUIRK_NON_STRICT BIT(4)
95 #define IO_PGTABLE_QUIRK_ARM_TTBR1 BIT(5)
92 unsigned long quirks;96 unsigned long quirks;
93 unsigned long pgsize_bitmap;97 unsigned long pgsize_bitmap;
94 unsigned int ias;98 unsigned int ias;
@@ -100,18 +104,33 @@ struct io_pgtable_cfg { · 5 unmodified lines
100 /* Low-level data specific to the table format */104 /* Low-level data specific to the table format */
101 union {105 union {
102 struct {106 struct {
103 u64 ttbr[2];107 u64 ttbr;
104 u64 tcr;108 struct {
109 u32 ips:3;
110 u32 tg:2;
111 u32 sh:2;
112 u32 orgn:2;
113 u32 irgn:2;
114 u32 tsz:6;
115 } tcr;
105 u64 mair;116 u64 mair;
106 } arm_lpae_s1_cfg;117 } arm_lpae_s1_cfg;
107 118
108 struct {119 struct {
109 u64 vttbr;120 u64 vttbr;
110 u64 vtcr;121 struct {
122 u32 ps:3;
123 u32 tg:2;
124 u32 sh:2;
125 u32 orgn:2;
126 u32 irgn:2;
127 u32 sl:2;
128 u32 tsz:6;
129 } vtcr;
111 } arm_lpae_s2_cfg;130 } arm_lpae_s2_cfg;
112 131
113 struct {132 struct {
114 u32 ttbr[2];133 u32 ttbr;
115 u32 tcr;134 u32 tcr;
116 u32 nmrr;135 u32 nmrr;
117 u32 prrr;136 u32 prrr;
include/linux/iommu.h+16−3
@@ -246,9 +246,10 @@ struct iommu_iotlb_gather { · 245 unmodified lines
246 * @sva_get_pasid: Get PASID associated to a SVA handle246 * @sva_get_pasid: Get PASID associated to a SVA handle
247 * @page_response: handle page request response247 * @page_response: handle page request response
248 * @cache_invalidate: invalidate translation caches248 * @cache_invalidate: invalidate translation caches
249 * @pgsize_bitmap: bitmap of all possible supported page sizes
250 * @sva_bind_gpasid: bind guest pasid and mm249 * @sva_bind_gpasid: bind guest pasid and mm
251 * @sva_unbind_gpasid: unbind guest pasid and mm250 * @sva_unbind_gpasid: unbind guest pasid and mm
251 * @pgsize_bitmap: bitmap of all possible supported page sizes
252 * @owner: Driver module providing these ops
252 */253 */
253struct iommu_ops {254struct iommu_ops {
254 bool (*capable)(enum iommu_cap);255 bool (*capable)(enum iommu_cap);
@@ -318,6 +319,7 @@ struct iommu_ops { · 63 unmodified lines
318 int (*sva_unbind_gpasid)(struct device *dev, int pasid);319 int (*sva_unbind_gpasid)(struct device *dev, int pasid);
319 320
320 unsigned long pgsize_bitmap;321 unsigned long pgsize_bitmap;
322 struct module *owner;
321};323};
322 324
323/**325/**
@@ -386,12 +388,19 @@ void iommu_device_sysfs_remove(struct iommu_device *iommu); · 62 unmodified lines
386int iommu_device_link(struct iommu_device *iommu, struct device *link);388int iommu_device_link(struct iommu_device *iommu, struct device *link);
387void iommu_device_unlink(struct iommu_device *iommu, struct device *link);389void iommu_device_unlink(struct iommu_device *iommu, struct device *link);
388 390
389static inline void iommu_device_set_ops(struct iommu_device *iommu,391static inline void __iommu_device_set_ops(struct iommu_device *iommu,
390 const struct iommu_ops *ops)392 const struct iommu_ops *ops)
391{393{
392 iommu->ops = ops;394 iommu->ops = ops;
393}395}
394 396
397#define iommu_device_set_ops(iommu, ops) \
398do { \
399 struct iommu_ops *__ops = (struct iommu_ops *)(ops); \
400 __ops->owner = THIS_MODULE; \
401 __iommu_device_set_ops(iommu, __ops); \
402} while (0)
403
395static inline void iommu_device_set_fwnode(struct iommu_device *iommu,404static inline void iommu_device_set_fwnode(struct iommu_device *iommu,
396 struct fwnode_handle *fwnode)405 struct fwnode_handle *fwnode)
397{406{
@@ -456,6 +465,8 @@ extern void iommu_set_fault_handler(struct iommu_domain *domain, · 58 unmodified lines
456 465
457extern void iommu_get_resv_regions(struct device *dev, struct list_head *list);466extern void iommu_get_resv_regions(struct device *dev, struct list_head *list);
458extern void iommu_put_resv_regions(struct device *dev, struct list_head *list);467extern void iommu_put_resv_regions(struct device *dev, struct list_head *list);
468extern void generic_iommu_put_resv_regions(struct device *dev,
469 struct list_head *list);
459extern int iommu_request_dm_for_dev(struct device *dev);470extern int iommu_request_dm_for_dev(struct device *dev);
460extern int iommu_request_dma_domain_for_dev(struct device *dev);471extern int iommu_request_dma_domain_for_dev(struct device *dev);
461extern void iommu_set_default_passthrough(bool cmd_line);472extern void iommu_set_default_passthrough(bool cmd_line);
@@ -570,6 +581,7 @@ struct iommu_group *fsl_mc_device_group(struct device *dev); · 108 unmodified lines
570 * @ops: ops for this device's IOMMU581 * @ops: ops for this device's IOMMU
571 * @iommu_fwnode: firmware handle for this device's IOMMU582 * @iommu_fwnode: firmware handle for this device's IOMMU
572 * @iommu_priv: IOMMU driver private data for this device583 * @iommu_priv: IOMMU driver private data for this device
584 * @num_pasid_bits: number of PASID bits supported by this device
573 * @num_ids: number of associated device IDs585 * @num_ids: number of associated device IDs
574 * @ids: IDs which this device may present to the IOMMU586 * @ids: IDs which this device may present to the IOMMU
575 */587 */
@@ -578,6 +590,7 @@ struct iommu_fwspec { · 2 unmodified lines
578 struct fwnode_handle *iommu_fwnode;590 struct fwnode_handle *iommu_fwnode;
579 void *iommu_priv;591 void *iommu_priv;
580 u32 flags;592 u32 flags;
593 u32 num_pasid_bits;
581 unsigned int num_ids;594 unsigned int num_ids;
582 u32 ids[1];595 u32 ids[1];
583};596};
include/linux/pci-ats.h+3−0
@@ -33,6 +33,9 @@ void pci_disable_pasid(struct pci_dev *pdev); · 32 unmodified lines
33int pci_pasid_features(struct pci_dev *pdev);33int pci_pasid_features(struct pci_dev *pdev);
34int pci_max_pasids(struct pci_dev *pdev);34int pci_max_pasids(struct pci_dev *pdev);
35#else /* CONFIG_PCI_PASID */35#else /* CONFIG_PCI_PASID */
36static inline int pci_enable_pasid(struct pci_dev *pdev, int features)
37{ return -EINVAL; }
38static inline void pci_disable_pasid(struct pci_dev *pdev) { }
36static inline int pci_pasid_features(struct pci_dev *pdev)39static inline int pci_pasid_features(struct pci_dev *pdev)
37{ return -EINVAL; }40{ return -EINVAL; }
38static inline int pci_max_pasids(struct pci_dev *pdev)41static inline int pci_max_pasids(struct pci_dev *pdev)