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Merge tag 'iommu-updates-v5.6' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu

Pull iommu updates from Joerg Roedel: - Allow compiling the ARM-SMMU drivers as modules. - Fixes and cleanups for the ARM-SMMU drivers and io-pgtable code collected by Will Deacon. The merge-commit (6855d1ba7537) has all the details. - Cleanup of the iommu_put_resv_regions() call-backs in various drivers. - AMD IOMMU driver cleanups. - Update for the x2APIC support in the AMD IOMMU driver. - Preparation patches for Intel VT-d nested mode support. - RMRR and identity domain handling fixes for the Intel VT-d driver. - More small fixes and cleanups. * tag 'iommu-updates-v5.6' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu: (87 commits) iommu/amd: Remove the unnecessary assignment iommu/vt-d: Remove unnecessary WARN_ON_ONCE() iommu/vt-d: Unnecessary to handle default identity domain iommu/vt-d: Allow devices with RMRRs to use identity domain iommu/vt-d: Add RMRR base and end addresses sanity check iommu/vt-d: Mark firmware tainted if RMRR fails sanity check iommu/amd: Remove unused struct member iommu/amd: Replace two consecutive readl calls with one readq iommu/vt-d: Don't reject Host Bridge due to scope mismatch PCI/ATS: Add PASID stubs iommu/arm-smmu-v3: Return -EBUSY when trying to re-add a device iommu/arm-smmu-v3: Improve add_device() error handling iommu/arm-smmu-v3: Use WRITE_ONCE() when changing validity of an STE iommu/arm-smmu-v3: Add second level of context descriptor table iommu/arm-smmu-v3: Prepare for handling arm_smmu_write_ctx_desc() failure iommu/arm-smmu-v3: Propagate ssid_bits iommu/arm-smmu-v3: Add support for Substream IDs iommu/arm-smmu-v3: Add context descriptor tables allocators iommu/arm-smmu-v3: Prepare arm_smmu_s1_cfg for SSID support ACPI/IORT: Parse SSID property of named component node ...

Linus Torvalds committed 6 years ago

Commit 4fc2ea62 parents d271ab2 e3b5ee036 files · +1686 −822Browse files

Showing the changes to include/linux (4 of 36 files). Show all

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4 files
  1. include/linux/intel-iommu.h +18 −7
  2. include/linux/io-pgtable.h +23 −4
  3. include/linux/iommu.h +16 −3
  4. include/linux/pci-ats.h +3 −0
include/linux/intel-iommu.h+18−7
@@ -34,10 +34,13 @@ · 33 unmodified lines
3434 #define VTD_STRIDE_SHIFT (9)
3535 #define VTD_STRIDE_MASK (((u64)-1) << VTD_STRIDE_SHIFT)
3636
37−#define DMA_PTE_READ (1)
38−#define DMA_PTE_WRITE (2)
39−#define DMA_PTE_LARGE_PAGE (1 << 7)
40−#define DMA_PTE_SNP (1 << 11)
37+#define DMA_PTE_READ BIT_ULL(0)
38+#define DMA_PTE_WRITE BIT_ULL(1)
39+#define DMA_PTE_LARGE_PAGE BIT_ULL(7)
40+#define DMA_PTE_SNP BIT_ULL(11)
41+
42+#define DMA_FL_PTE_PRESENT BIT_ULL(0)
43+#define DMA_FL_PTE_XD BIT_ULL(63)
4144
4245 #define CONTEXT_TT_MULTI_LEVEL 0
4346 #define CONTEXT_TT_DEV_IOTLB 1
@@ -435,8 +438,10 @@ enum { · 391 unmodified lines
435438
436439 #define VTD_FLAG_TRANS_PRE_ENABLED (1 << 0)
437440 #define VTD_FLAG_IRQ_REMAP_PRE_ENABLED (1 << 1)
441+#define VTD_FLAG_SVM_CAPABLE (1 << 2)
438442
439443 extern int intel_iommu_sm;
444+extern spinlock_t device_domain_lock;
440445
441446 #define sm_supported(iommu) (intel_iommu_sm && ecap_smts((iommu)->ecap))
442447 #define pasid_supported(iommu) (sm_supported(iommu) && \
@@ -609,10 +614,11 @@ static inline void dma_clear_pte(struct dma_pte *pte) · 166 unmodified lines
609614 static inline u64 dma_pte_addr(struct dma_pte *pte)
610615 {
611616 #ifdef CONFIG_64BIT
612− return pte->val & VTD_PAGE_MASK;
617+ return pte->val & VTD_PAGE_MASK & (~DMA_FL_PTE_XD);
613618 #else
614619 /* Must have a full atomic 64-bit read */
615− return __cmpxchg64(&pte->val, 0ULL, 0ULL) & VTD_PAGE_MASK;
620+ return __cmpxchg64(&pte->val, 0ULL, 0ULL) &
621+ VTD_PAGE_MASK & (~DMA_FL_PTE_XD);
616622 #endif
617623 }
618624
@@ -645,6 +651,8 @@ extern void qi_flush_iotlb(struct intel_iommu *iommu, u16 did, u64 addr, · 26 unmodified lines
645651 unsigned int size_order, u64 type);
646652 extern void qi_flush_dev_iotlb(struct intel_iommu *iommu, u16 sid, u16 pfsid,
647653 u16 qdep, u64 addr, unsigned mask);
654+void qi_flush_piotlb(struct intel_iommu *iommu, u16 did, u32 pasid, u64 addr,
655+ unsigned long npages, bool ih);
648656 extern int qi_submit_sync(struct qi_desc *desc, struct intel_iommu *iommu);
649657
650658 extern int dmar_ir_support(void);
@@ -656,9 +664,10 @@ int for_each_device_domain(int (*fn)(struct device_domain_info *info, · 5 unmodified lines
656664 void *data), void *data);
657665 void iommu_flush_write_buffer(struct intel_iommu *iommu);
658666 int intel_iommu_enable_pasid(struct intel_iommu *iommu, struct device *dev);
667+struct dmar_domain *find_domain(struct device *dev);
659668
660669 #ifdef CONFIG_INTEL_IOMMU_SVM
661−int intel_svm_init(struct intel_iommu *iommu);
670+extern void intel_svm_check(struct intel_iommu *iommu);
662671 extern int intel_svm_enable_prq(struct intel_iommu *iommu);
663672 extern int intel_svm_finish_prq(struct intel_iommu *iommu);
664673
@@ -686,6 +695,8 @@ struct intel_svm { · 21 unmodified lines
686695 };
687696
688697 extern struct intel_iommu *intel_svm_device_to_iommu(struct device *dev);
698+#else
699+static inline void intel_svm_check(struct intel_iommu *iommu) {}
689700 #endif
690701
691702 #ifdef CONFIG_INTEL_IOMMU_DEBUGFS
include/linux/io-pgtable.h+23−4
@@ -83,12 +83,16 @@ struct io_pgtable_cfg { · 82 unmodified lines
8383 * IO_PGTABLE_QUIRK_NON_STRICT: Skip issuing synchronous leaf TLBIs
8484 * on unmap, for DMA domains using the flush queue mechanism for
8585 * delayed invalidation.
86+ *
87+ * IO_PGTABLE_QUIRK_ARM_TTBR1: (ARM LPAE format) Configure the table
88+ * for use in the upper half of a split address space.
8689 */
8790 #define IO_PGTABLE_QUIRK_ARM_NS BIT(0)
8891 #define IO_PGTABLE_QUIRK_NO_PERMS BIT(1)
8992 #define IO_PGTABLE_QUIRK_TLBI_ON_MAP BIT(2)
9093 #define IO_PGTABLE_QUIRK_ARM_MTK_EXT BIT(3)
9194 #define IO_PGTABLE_QUIRK_NON_STRICT BIT(4)
95+ #define IO_PGTABLE_QUIRK_ARM_TTBR1 BIT(5)
9296 unsigned long quirks;
9397 unsigned long pgsize_bitmap;
9498 unsigned int ias;
@@ -100,18 +104,33 @@ struct io_pgtable_cfg { · 5 unmodified lines
100104 /* Low-level data specific to the table format */
101105 union {
102106 struct {
103− u64 ttbr[2];
104− u64 tcr;
107+ u64 ttbr;
108+ struct {
109+ u32 ips:3;
110+ u32 tg:2;
111+ u32 sh:2;
112+ u32 orgn:2;
113+ u32 irgn:2;
114+ u32 tsz:6;
115+ } tcr;
105116 u64 mair;
106117 } arm_lpae_s1_cfg;
107118
108119 struct {
109120 u64 vttbr;
110− u64 vtcr;
121+ struct {
122+ u32 ps:3;
123+ u32 tg:2;
124+ u32 sh:2;
125+ u32 orgn:2;
126+ u32 irgn:2;
127+ u32 sl:2;
128+ u32 tsz:6;
129+ } vtcr;
111130 } arm_lpae_s2_cfg;
112131
113132 struct {
114− u32 ttbr[2];
133+ u32 ttbr;
115134 u32 tcr;
116135 u32 nmrr;
117136 u32 prrr;
include/linux/iommu.h+16−3
@@ -246,9 +246,10 @@ struct iommu_iotlb_gather { · 245 unmodified lines
246246 * @sva_get_pasid: Get PASID associated to a SVA handle
247247 * @page_response: handle page request response
248248 * @cache_invalidate: invalidate translation caches
249− * @pgsize_bitmap: bitmap of all possible supported page sizes
250249 * @sva_bind_gpasid: bind guest pasid and mm
251250 * @sva_unbind_gpasid: unbind guest pasid and mm
251+ * @pgsize_bitmap: bitmap of all possible supported page sizes
252+ * @owner: Driver module providing these ops
252253 */
253254 struct iommu_ops {
254255 bool (*capable)(enum iommu_cap);
@@ -318,6 +319,7 @@ struct iommu_ops { · 63 unmodified lines
318319 int (*sva_unbind_gpasid)(struct device *dev, int pasid);
319320
320321 unsigned long pgsize_bitmap;
322+ struct module *owner;
321323 };
322324
323325 /**
@@ -386,12 +388,19 @@ void iommu_device_sysfs_remove(struct iommu_device *iommu); · 62 unmodified lines
386388 int iommu_device_link(struct iommu_device *iommu, struct device *link);
387389 void iommu_device_unlink(struct iommu_device *iommu, struct device *link);
388390
389−static inline void iommu_device_set_ops(struct iommu_device *iommu,
390− const struct iommu_ops *ops)
391+static inline void __iommu_device_set_ops(struct iommu_device *iommu,
392+ const struct iommu_ops *ops)
391393 {
392394 iommu->ops = ops;
393395 }
394396
397+#define iommu_device_set_ops(iommu, ops) \
398+do { \
399+ struct iommu_ops *__ops = (struct iommu_ops *)(ops); \
400+ __ops->owner = THIS_MODULE; \
401+ __iommu_device_set_ops(iommu, __ops); \
402+} while (0)
403+
395404 static inline void iommu_device_set_fwnode(struct iommu_device *iommu,
396405 struct fwnode_handle *fwnode)
397406 {
@@ -456,6 +465,8 @@ extern void iommu_set_fault_handler(struct iommu_domain *domain, · 58 unmodified lines
456465
457466 extern void iommu_get_resv_regions(struct device *dev, struct list_head *list);
458467 extern void iommu_put_resv_regions(struct device *dev, struct list_head *list);
468+extern void generic_iommu_put_resv_regions(struct device *dev,
469+ struct list_head *list);
459470 extern int iommu_request_dm_for_dev(struct device *dev);
460471 extern int iommu_request_dma_domain_for_dev(struct device *dev);
461472 extern void iommu_set_default_passthrough(bool cmd_line);
@@ -570,6 +581,7 @@ struct iommu_group *fsl_mc_device_group(struct device *dev); · 108 unmodified lines
570581 * @ops: ops for this device's IOMMU
571582 * @iommu_fwnode: firmware handle for this device's IOMMU
572583 * @iommu_priv: IOMMU driver private data for this device
584+ * @num_pasid_bits: number of PASID bits supported by this device
573585 * @num_ids: number of associated device IDs
574586 * @ids: IDs which this device may present to the IOMMU
575587 */
@@ -578,6 +590,7 @@ struct iommu_fwspec { · 2 unmodified lines
578590 struct fwnode_handle *iommu_fwnode;
579591 void *iommu_priv;
580592 u32 flags;
593+ u32 num_pasid_bits;
581594 unsigned int num_ids;
582595 u32 ids[1];
583596 };
include/linux/pci-ats.h+3−0
@@ -33,6 +33,9 @@ void pci_disable_pasid(struct pci_dev *pdev); · 32 unmodified lines
3333 int pci_pasid_features(struct pci_dev *pdev);
3434 int pci_max_pasids(struct pci_dev *pdev);
3535 #else /* CONFIG_PCI_PASID */
36+static inline int pci_enable_pasid(struct pci_dev *pdev, int features)
37+{ return -EINVAL; }
38+static inline void pci_disable_pasid(struct pci_dev *pdev) { }
3639 static inline int pci_pasid_features(struct pci_dev *pdev)
3740 { return -EINVAL; }
3841 static inline int pci_max_pasids(struct pci_dev *pdev)