amd-drm-fixes-6.18-2025-11-26: amdgpu: - Unified MES fix - HDMI fix - Cursor fix - Bightness fix - EDID reading improvement - UserQ fix - Cyan Skillfish IP discovery fix Signed-off-by: Dave Airlie <airlied@redhat.com>
Unified · Split
| @@ -2638,6 +2638,8 @@ static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev) · 2637 unmodified lines | ||
| 2638 | 2638 | chip_name = "navi12"; |
| 2639 | 2639 | break; |
| 2640 | 2640 | case CHIP_CYAN_SKILLFISH: |
| 2641 | + if (adev->mman.discovery_bin) | |
| 2642 | + return 0; | |
| 2641 | 2643 | chip_name = "cyan_skillfish"; |
| 2642 | 2644 | break; |
| 2643 | 2645 | } |
| @@ -597,6 +597,9 @@ int amdgpu_gmc_allocate_vm_inv_eng(struct amdgpu_device *adev) · 596 unmodified lines | ||
| 597 | 597 | /* reserve engine 5 for firmware */ |
| 598 | 598 | if (adev->enable_mes) |
| 599 | 599 | vm_inv_engs[i] &= ~(1 << 5); |
| 600 | + /* reserve engine 6 for uni mes */ | |
| 601 | + if (adev->enable_uni_mes) | |
| 602 | + vm_inv_engs[i] &= ~(1 << 6); | |
| 600 | 603 | /* reserve mmhub engine 3 for firmware */ |
| 601 | 604 | if (adev->enable_umsch_mm) |
| 602 | 605 | vm_inv_engs[i] &= ~(1 << 3); |
| @@ -1066,7 +1066,7 @@ amdgpu_vm_tlb_flush(struct amdgpu_vm_update_params *params, · 1065 unmodified lines | ||
| 1066 | 1066 | } |
| 1067 | 1067 | |
| 1068 | 1068 | /* Prepare a TLB flush fence to be attached to PTs */ |
| 1069 | − if (!params->unlocked && vm->is_compute_context) { | |
| 1069 | + if (!params->unlocked) { | |
| 1070 | 1070 | amdgpu_vm_tlb_fence_create(params->adev, vm, fence); |
| 1071 | 1071 | |
| 1072 | 1072 | /* Makes sure no PD/PT is freed before the flush */ |
| @@ -5052,6 +5052,21 @@ static void amdgpu_dm_backlight_set_level(struct amdgpu_display_manager *dm, · 5051 unmodified lines | ||
| 5052 | 5052 | struct dc_link *link; |
| 5053 | 5053 | u32 brightness; |
| 5054 | 5054 | bool rc, reallow_idle = false; |
| 5055 | + struct drm_connector *connector; | |
| 5056 | + | |
| 5057 | + list_for_each_entry(connector, &dm->ddev->mode_config.connector_list, head) { | |
| 5058 | + struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); | |
| 5059 | + | |
| 5060 | + if (aconnector->bl_idx != bl_idx) | |
| 5061 | + continue; | |
| 5062 | + | |
| 5063 | + /* if connector is off, save the brightness for next time it's on */ | |
| 5064 | + if (!aconnector->base.encoder) { | |
| 5065 | + dm->brightness[bl_idx] = user_brightness; | |
| 5066 | + dm->actual_brightness[bl_idx] = 0; | |
| 5067 | + return; | |
| 5068 | + } | |
| 5069 | + } | |
| 5055 | 5070 | |
| 5056 | 5071 | amdgpu_dm_update_backlight_caps(dm, bl_idx); |
| 5057 | 5072 | caps = &dm->backlight_caps[bl_idx]; |
| @@ -997,8 +997,8 @@ enum dc_edid_status dm_helpers_read_local_edid( · 996 unmodified lines | ||
| 997 | 997 | struct amdgpu_dm_connector *aconnector = link->priv; |
| 998 | 998 | struct drm_connector *connector = &aconnector->base; |
| 999 | 999 | struct i2c_adapter *ddc; |
| 1000 | − int retry = 3; | |
| 1001 | − enum dc_edid_status edid_status; | |
| 1000 | + int retry = 25; | |
| 1001 | + enum dc_edid_status edid_status = EDID_NO_RESPONSE; | |
| 1002 | 1002 | const struct drm_edid *drm_edid; |
| 1003 | 1003 | const struct edid *edid; |
| 1004 | 1004 | |
| @@ -1028,7 +1028,7 @@ enum dc_edid_status dm_helpers_read_local_edid( · 23 unmodified lines | ||
| 1028 | 1028 | } |
| 1029 | 1029 | |
| 1030 | 1030 | if (!drm_edid) |
| 1031 | − return EDID_NO_RESPONSE; | |
| 1031 | + continue; | |
| 1032 | 1032 | |
| 1033 | 1033 | edid = drm_edid_raw(drm_edid); // FIXME: Get rid of drm_edid_raw() |
| 1034 | 1034 | if (!edid || |
| @@ -1046,7 +1046,7 @@ enum dc_edid_status dm_helpers_read_local_edid( · 11 unmodified lines | ||
| 1046 | 1046 | &sink->dc_edid, |
| 1047 | 1047 | &sink->edid_caps); |
| 1048 | 1048 | |
| 1049 | − } while (edid_status == EDID_BAD_CHECKSUM && --retry > 0); | |
| 1049 | + } while ((edid_status == EDID_BAD_CHECKSUM || edid_status == EDID_NO_RESPONSE) && --retry > 0); | |
| 1050 | 1050 | |
| 1051 | 1051 | if (edid_status != EDID_OK) |
| 1052 | 1052 | DRM_ERROR("EDID err: %d, on connector: %s", |
| @@ -705,9 +705,14 @@ bool dc_stream_get_scanoutpos(const struct dc_stream_state *stream, · 704 unmodified lines | ||
| 705 | 705 | { |
| 706 | 706 | uint8_t i; |
| 707 | 707 | bool ret = false; |
| 708 | − struct dc *dc = stream->ctx->dc; | |
| 709 | − struct resource_context *res_ctx = | |
| 710 | − &dc->current_state->res_ctx; | |
| 708 | + struct dc *dc; | |
| 709 | + struct resource_context *res_ctx; | |
| 710 | + | |
| 711 | + if (!stream->ctx) | |
| 712 | + return false; | |
| 713 | + | |
| 714 | + dc = stream->ctx->dc; | |
| 715 | + res_ctx = &dc->current_state->res_ctx; | |
| 711 | 716 | |
| 712 | 717 | dc_exit_ips_for_hw_access(dc); |
| 713 | 718 | |
| @@ -671,7 +671,6 @@ void dce110_enable_stream(struct pipe_ctx *pipe_ctx) · 670 unmodified lines | ||
| 671 | 671 | uint32_t early_control = 0; |
| 672 | 672 | struct timing_generator *tg = pipe_ctx->stream_res.tg; |
| 673 | 673 | |
| 674 | − link_hwss->setup_stream_attribute(pipe_ctx); | |
| 675 | 674 | link_hwss->setup_stream_encoder(pipe_ctx); |
| 676 | 675 | |
| 677 | 676 | dc->hwss.update_info_frame(pipe_ctx); |
| @@ -3060,8 +3060,6 @@ void dcn20_enable_stream(struct pipe_ctx *pipe_ctx) · 3059 unmodified lines | ||
| 3060 | 3060 | link_enc->transmitter - TRANSMITTER_UNIPHY_A); |
| 3061 | 3061 | } |
| 3062 | 3062 | |
| 3063 | − link_hwss->setup_stream_attribute(pipe_ctx); | |
| 3064 | − | |
| 3065 | 3063 | if (dc->res_pool->dccg->funcs->set_pixel_rate_div) |
| 3066 | 3064 | dc->res_pool->dccg->funcs->set_pixel_rate_div( |
| 3067 | 3065 | dc->res_pool->dccg, |
| @@ -971,8 +971,6 @@ void dcn401_enable_stream(struct pipe_ctx *pipe_ctx) · 970 unmodified lines | ||
| 971 | 971 | } |
| 972 | 972 | } |
| 973 | 973 | |
| 974 | − link_hwss->setup_stream_attribute(pipe_ctx); | |
| 975 | − | |
| 976 | 974 | if (dc->res_pool->dccg->funcs->set_pixel_rate_div) { |
| 977 | 975 | dc->res_pool->dccg->funcs->set_pixel_rate_div( |
| 978 | 976 | dc->res_pool->dccg, |
| @@ -2458,6 +2458,7 @@ void link_set_dpms_on( · 2457 unmodified lines | ||
| 2458 | 2458 | struct link_encoder *link_enc = pipe_ctx->link_res.dio_link_enc; |
| 2459 | 2459 | enum otg_out_mux_dest otg_out_dest = OUT_MUX_DIO; |
| 2460 | 2460 | struct vpg *vpg = pipe_ctx->stream_res.stream_enc->vpg; |
| 2461 | + const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); | |
| 2461 | 2462 | bool apply_edp_fast_boot_optimization = |
| 2462 | 2463 | pipe_ctx->stream->apply_edp_fast_boot_optimization; |
| 2463 | 2464 | |
| @@ -2502,6 +2503,8 @@ void link_set_dpms_on( · 38 unmodified lines | ||
| 2502 | 2503 | pipe_ctx->stream_res.tg->funcs->set_out_mux(pipe_ctx->stream_res.tg, otg_out_dest); |
| 2503 | 2504 | } |
| 2504 | 2505 | |
| 2506 | + link_hwss->setup_stream_attribute(pipe_ctx); | |
| 2507 | + | |
| 2505 | 2508 | pipe_ctx->stream->apply_edp_fast_boot_optimization = false; |
| 2506 | 2509 | |
| 2507 | 2510 | // Enable VPG before building infoframe |
| @@ -44,11 +44,6 @@ static void virtual_stream_encoder_dvi_set_stream_attribute( · 43 unmodified lines | ||
| 44 | 44 | struct dc_crtc_timing *crtc_timing, |
| 45 | 45 | bool is_dual_link) {} |
| 46 | 46 | |
| 47 | −static void virtual_stream_encoder_lvds_set_stream_attribute( | |
| 48 | − struct stream_encoder *enc, | |
| 49 | − struct dc_crtc_timing *crtc_timing) | |
| 50 | −{} | |
| 51 | − | |
| 52 | 47 | static void virtual_stream_encoder_set_throttled_vcp_size( |
| 53 | 48 | struct stream_encoder *enc, |
| 54 | 49 | struct fixed31_32 avg_time_slots_per_mtp) |
| @@ -120,8 +115,6 @@ static const struct stream_encoder_funcs virtual_str_enc_funcs = { · 65 unmodified lines | ||
| 120 | 115 | virtual_stream_encoder_hdmi_set_stream_attribute, |
| 121 | 116 | .dvi_set_stream_attribute = |
| 122 | 117 | virtual_stream_encoder_dvi_set_stream_attribute, |
| 123 | − .lvds_set_stream_attribute = | |
| 124 | − virtual_stream_encoder_lvds_set_stream_attribute, | |
| 125 | 118 | .set_throttled_vcp_size = |
| 126 | 119 | virtual_stream_encoder_set_throttled_vcp_size, |
| 127 | 120 | .update_hdmi_info_packets = |