| @@ -3403,7 +3403,7 @@ static int goya_validate_dma_pkt_host(struct hl_device *hdev, · 3402 unmodified lines |
| 3403 | 3403 | { |
| 3404 | 3404 | u64 device_memory_addr, addr; |
| 3405 | 3405 | enum dma_data_direction dir; |
| 3406 | | − enum goya_dma_direction user_dir; |
| 3406 | + enum hl_goya_dma_direction user_dir; |
| 3407 | 3407 | bool sram_addr = true; |
| 3408 | 3408 | bool skip_host_mem_pin = false; |
| 3409 | 3409 | bool user_memset; |
| @@ -3419,7 +3419,7 @@ static int goya_validate_dma_pkt_host(struct hl_device *hdev, · 9 unmodified lines |
| 3419 | 3419 | GOYA_PKT_LIN_DMA_CTL_MEMSET_SHIFT; |
| 3420 | 3420 | |
| 3421 | 3421 | switch (user_dir) { |
| 3422 | | − case DMA_HOST_TO_DRAM: |
| 3422 | + case HL_DMA_HOST_TO_DRAM: |
| 3423 | 3423 | dev_dbg(hdev->dev, "DMA direction is HOST --> DRAM\n"); |
| 3424 | 3424 | dir = DMA_TO_DEVICE; |
| 3425 | 3425 | sram_addr = false; |
| @@ -3429,7 +3429,7 @@ static int goya_validate_dma_pkt_host(struct hl_device *hdev, · 3 unmodified lines |
| 3429 | 3429 | skip_host_mem_pin = true; |
| 3430 | 3430 | break; |
| 3431 | 3431 | |
| 3432 | | − case DMA_DRAM_TO_HOST: |
| 3432 | + case HL_DMA_DRAM_TO_HOST: |
| 3433 | 3433 | dev_dbg(hdev->dev, "DMA direction is DRAM --> HOST\n"); |
| 3434 | 3434 | dir = DMA_FROM_DEVICE; |
| 3435 | 3435 | sram_addr = false; |
| @@ -3437,7 +3437,7 @@ static int goya_validate_dma_pkt_host(struct hl_device *hdev, · 1 unmodified line |
| 3437 | 3437 | device_memory_addr = le64_to_cpu(user_dma_pkt->src_addr); |
| 3438 | 3438 | break; |
| 3439 | 3439 | |
| 3440 | | − case DMA_HOST_TO_SRAM: |
| 3440 | + case HL_DMA_HOST_TO_SRAM: |
| 3441 | 3441 | dev_dbg(hdev->dev, "DMA direction is HOST --> SRAM\n"); |
| 3442 | 3442 | dir = DMA_TO_DEVICE; |
| 3443 | 3443 | addr = le64_to_cpu(user_dma_pkt->src_addr); |
| @@ -3446,14 +3446,14 @@ static int goya_validate_dma_pkt_host(struct hl_device *hdev, · 2 unmodified lines |
| 3446 | 3446 | skip_host_mem_pin = true; |
| 3447 | 3447 | break; |
| 3448 | 3448 | |
| 3449 | | − case DMA_SRAM_TO_HOST: |
| 3449 | + case HL_DMA_SRAM_TO_HOST: |
| 3450 | 3450 | dev_dbg(hdev->dev, "DMA direction is SRAM --> HOST\n"); |
| 3451 | 3451 | dir = DMA_FROM_DEVICE; |
| 3452 | 3452 | addr = le64_to_cpu(user_dma_pkt->dst_addr); |
| 3453 | 3453 | device_memory_addr = le64_to_cpu(user_dma_pkt->src_addr); |
| 3454 | 3454 | break; |
| 3455 | 3455 | default: |
| 3456 | | − dev_err(hdev->dev, "DMA direction is undefined\n"); |
| 3456 | + dev_err(hdev->dev, "DMA direction %d is unsupported/undefined\n", user_dir); |
| 3457 | 3457 | return -EFAULT; |
| 3458 | 3458 | } |
| 3459 | 3459 | |
| @@ -3505,14 +3505,14 @@ static int goya_validate_dma_pkt_no_host(struct hl_device *hdev, · 45 unmodified lines |
| 3505 | 3505 | struct packet_lin_dma *user_dma_pkt) |
| 3506 | 3506 | { |
| 3507 | 3507 | u64 sram_memory_addr, dram_memory_addr; |
| 3508 | | − enum goya_dma_direction user_dir; |
| 3508 | + enum hl_goya_dma_direction user_dir; |
| 3509 | 3509 | u32 ctl; |
| 3510 | 3510 | |
| 3511 | 3511 | ctl = le32_to_cpu(user_dma_pkt->ctl); |
| 3512 | 3512 | user_dir = (ctl & GOYA_PKT_LIN_DMA_CTL_DMA_DIR_MASK) >> |
| 3513 | 3513 | GOYA_PKT_LIN_DMA_CTL_DMA_DIR_SHIFT; |
| 3514 | 3514 | |
| 3515 | | − if (user_dir == DMA_DRAM_TO_SRAM) { |
| 3515 | + if (user_dir == HL_DMA_DRAM_TO_SRAM) { |
| 3516 | 3516 | dev_dbg(hdev->dev, "DMA direction is DRAM --> SRAM\n"); |
| 3517 | 3517 | dram_memory_addr = le64_to_cpu(user_dma_pkt->src_addr); |
| 3518 | 3518 | sram_memory_addr = le64_to_cpu(user_dma_pkt->dst_addr); |
| @@ -3549,7 +3549,7 @@ static int goya_validate_dma_pkt_no_mmu(struct hl_device *hdev, · 30 unmodified lines |
| 3549 | 3549 | struct hl_cs_parser *parser, |
| 3550 | 3550 | struct packet_lin_dma *user_dma_pkt) |
| 3551 | 3551 | { |
| 3552 | | − enum goya_dma_direction user_dir; |
| 3552 | + enum hl_goya_dma_direction user_dir; |
| 3553 | 3553 | u32 ctl; |
| 3554 | 3554 | int rc; |
| 3555 | 3555 | |
| @@ -3574,7 +3574,7 @@ static int goya_validate_dma_pkt_no_mmu(struct hl_device *hdev, · 18 unmodified lines |
| 3574 | 3574 | return -EINVAL; |
| 3575 | 3575 | } |
| 3576 | 3576 | |
| 3577 | | − if ((user_dir == DMA_DRAM_TO_SRAM) || (user_dir == DMA_SRAM_TO_DRAM)) |
| 3577 | + if ((user_dir == HL_DMA_DRAM_TO_SRAM) || (user_dir == HL_DMA_SRAM_TO_DRAM)) |
| 3578 | 3578 | rc = goya_validate_dma_pkt_no_host(hdev, parser, user_dma_pkt); |
| 3579 | 3579 | else |
| 3580 | 3580 | rc = goya_validate_dma_pkt_host(hdev, parser, user_dma_pkt); |
| @@ -3781,7 +3781,7 @@ static int goya_patch_dma_packet(struct hl_device *hdev, · 200 unmodified lines |
| 3781 | 3781 | u32 count, dma_desc_cnt; |
| 3782 | 3782 | u64 len, len_next; |
| 3783 | 3783 | dma_addr_t dma_addr, dma_addr_next; |
| 3784 | | − enum goya_dma_direction user_dir; |
| 3784 | + enum hl_goya_dma_direction user_dir; |
| 3785 | 3785 | u64 device_memory_addr, addr; |
| 3786 | 3786 | enum dma_data_direction dir; |
| 3787 | 3787 | struct sg_table *sgt; |
| @@ -3797,14 +3797,14 @@ static int goya_patch_dma_packet(struct hl_device *hdev, · 9 unmodified lines |
| 3797 | 3797 | user_memset = (ctl & GOYA_PKT_LIN_DMA_CTL_MEMSET_MASK) >> |
| 3798 | 3798 | GOYA_PKT_LIN_DMA_CTL_MEMSET_SHIFT; |
| 3799 | 3799 | |
| 3800 | | − if ((user_dir == DMA_DRAM_TO_SRAM) || (user_dir == DMA_SRAM_TO_DRAM) || |
| 3800 | + if ((user_dir == HL_DMA_DRAM_TO_SRAM) || (user_dir == HL_DMA_SRAM_TO_DRAM) || |
| 3801 | 3801 | (user_dma_pkt->tsize == 0)) { |
| 3802 | 3802 | memcpy(new_dma_pkt, user_dma_pkt, sizeof(*new_dma_pkt)); |
| 3803 | 3803 | *new_dma_pkt_size = sizeof(*new_dma_pkt); |
| 3804 | 3804 | return 0; |
| 3805 | 3805 | } |
| 3806 | 3806 | |
| 3807 | | − if ((user_dir == DMA_HOST_TO_DRAM) || (user_dir == DMA_HOST_TO_SRAM)) { |
| 3807 | + if ((user_dir == HL_DMA_HOST_TO_DRAM) || (user_dir == HL_DMA_HOST_TO_SRAM)) { |
| 3808 | 3808 | addr = le64_to_cpu(user_dma_pkt->src_addr); |
| 3809 | 3809 | device_memory_addr = le64_to_cpu(user_dma_pkt->dst_addr); |
| 3810 | 3810 | dir = DMA_TO_DEVICE; |
| @@ -4804,7 +4804,7 @@ static int goya_memset_device_memory(struct hl_device *hdev, u64 addr, u64 size, · 993 unmodified lines |
| 4804 | 4804 | (1 << GOYA_PKT_LIN_DMA_CTL_WO_SHIFT) | |
| 4805 | 4805 | (1 << GOYA_PKT_CTL_RB_SHIFT) | |
| 4806 | 4806 | (1 << GOYA_PKT_CTL_MB_SHIFT)); |
| 4807 | | − ctl |= (is_dram ? DMA_HOST_TO_DRAM : DMA_HOST_TO_SRAM) << |
| 4807 | + ctl |= (is_dram ? HL_DMA_HOST_TO_DRAM : HL_DMA_HOST_TO_SRAM) << |
| 4808 | 4808 | GOYA_PKT_LIN_DMA_CTL_DMA_DIR_SHIFT; |
| 4809 | 4809 | lin_dma_pkt->ctl = cpu_to_le32(ctl); |
| 4810 | 4810 | |