Merge tag 'mfd-next-5.8' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd

Pull MFD updates from Lee Jones: "Core Frameworks: - Constify 'properties' attribute in core header file New Drivers: - Add support for Gateworks System Controller - Add support for MediaTek MT6358 PMIC - Add support for Mediatek MT6360 PMIC - Add support for Monolithic Power Systems MP2629 ADC and Battery charger Fix-ups: - Use new I2C API in htc-i2cpld - Remove superfluous code in sprd-sc27xx-spi - Improve error handling in stm32-timers - Device Tree additions/fixes in mt6397 - Defer probe betterment in wm8994-core - Improve module handling in wm8994-core - Staticify in stpmic1 - Trivial (spelling, formatting) in tqmx86 Bug Fixes: - Fix incorrect register/PCI IDs in intel-lpss-pci - Fix unbalanced Regulator API calls in wm8994-core - Fix double free() in wcd934x - Remove IRQ domain on failure in stmfx - Reset chip on resume in stmfx - Disable/enable IRQs on suspend/resume in stmfx - Do not use bulk writes on H/W which does not support them in max77620" * tag 'mfd-next-5.8' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd: (29 commits) mfd: mt6360: Remove duplicate REGMAP_IRQ_REG_LINE() entry mfd: Add support for PMIC MT6360 mfd: max77620: Use single-byte writes on MAX77620 mfd: wcd934x: Drop kfree for memory allocated with devm_kzalloc mfd: stmfx: Disable IRQ in suspend to avoid spurious interrupt mfd: stmfx: Fix stmfx_irq_init error path mfd: stmfx: Reset chip on resume as supply was disabled mfd: wm8994: Silence warning about supplies during deferred probe mfd: wm8994: Fix unbalanced calls to regulator_bulk_disable() mfd: wm8994: Fix driver operation if loaded as modules dt-bindings: mfd: mediatek: Add MT6397 Pin Controller mfd: Constify properties in mfd_cell mfd: stm32-timers: Use dma_request_chan() instead dma_request_slave_channel() mfd: sprd: Remove unnecessary spi_bus_type setting mfd: intel-lpss: Update LPSS UART #2 PCI ID for Jasper Lake mfd: tqmx86: Fix a typo in MODULE_DESCRIPTION mfd: stpmic1: Make stpmic1_regmap_config static mfd: htc-i2cpld: Convert to use i2c_new_client_device() MAINTAINERS: Add entry for mp2629 Battery Charger driver power: supply: mp2629: Add impedance compensation config ...

Linus Torvalds committed 6 years ago

Commit 512b7d32 parents acf25aa 098c4ad37 files · +2630 −83Browse files

Showing the changes to include/linux (8 of 37 files). Show all

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8 files

include/linux/mfd/core.h +1 −1
include/linux/mfd/mp2629.h +26 −0
include/linux/mfd/mt6358/core.h +158 −0
include/linux/mfd/mt6358/registers.h +282 −0
include/linux/mfd/mt6360.h +240 −0
include/linux/mfd/mt6397/core.h +5 −0
include/linux/mfd/mt6397/rtc.h +8 −1
include/linux/mfd/stmfx.h +1 −0

include/linux/mfd/core.h+1−1

@@ -70,7 +70,7 @@ struct mfd_cell { · 69 unmodified lines
70	70	size_t pdata_size;
71	71
72	72	/* device properties passed to the sub devices drivers */
73		− struct property_entry *properties;
	73	+ const struct property_entry *properties;
74	74
75	75	/*
76	76	* Device Tree compatible string

include/linux/mfd/mp2629.h+26−0

@@ -0,0 +1,26 @@
	1	+/* SPDX-License-Identifier: GPL-2.0+ */
	2	+/*
	3	+ * Copyright 2020 Monolithic Power Systems, Inc
	4	+ */
	5	+
	6	+#ifndef __MP2629_H__
	7	+#define __MP2629_H__
	8	+
	9	+#include <linux/device.h>
	10	+#include <linux/regmap.h>
	11	+
	12	+struct mp2629_data {
	13	+ struct device *dev;
	14	+ struct regmap *regmap;
	15	+};
	16	+
	17	+enum mp2629_adc_chan {
	18	+ MP2629_BATT_VOLT,
	19	+ MP2629_SYSTEM_VOLT,
	20	+ MP2629_INPUT_VOLT,
	21	+ MP2629_BATT_CURRENT,
	22	+ MP2629_INPUT_CURRENT,
	23	+ MP2629_ADC_CHAN_END
	24	+};
	25	+
	26	+#endif

include/linux/mfd/mt6358/core.h+158−0

@@ -0,0 +1,158 @@
	1	+/* SPDX-License-Identifier: GPL-2.0 */
	2	+/*
	3	+ * Copyright (c) 2020 MediaTek Inc.
	4	+ */
	5	+
	6	+#ifndef __MFD_MT6358_CORE_H__
	7	+#define __MFD_MT6358_CORE_H__
	8	+
	9	+#define MT6358_REG_WIDTH 16
	10	+
	11	+struct irq_top_t {
	12	+ int hwirq_base;
	13	+ unsigned int num_int_regs;
	14	+ unsigned int num_int_bits;
	15	+ unsigned int en_reg;
	16	+ unsigned int en_reg_shift;
	17	+ unsigned int sta_reg;
	18	+ unsigned int sta_reg_shift;
	19	+ unsigned int top_offset;
	20	+};
	21	+
	22	+struct pmic_irq_data {
	23	+ unsigned int num_top;
	24	+ unsigned int num_pmic_irqs;
	25	+ unsigned short top_int_status_reg;
	26	+ bool *enable_hwirq;
	27	+ bool *cache_hwirq;
	28	+};
	29	+
	30	+enum mt6358_irq_top_status_shift {
	31	+ MT6358_BUCK_TOP = 0,
	32	+ MT6358_LDO_TOP,
	33	+ MT6358_PSC_TOP,
	34	+ MT6358_SCK_TOP,
	35	+ MT6358_BM_TOP,
	36	+ MT6358_HK_TOP,
	37	+ MT6358_AUD_TOP,
	38	+ MT6358_MISC_TOP,
	39	+};
	40	+
	41	+enum mt6358_irq_numbers {
	42	+ MT6358_IRQ_VPROC11_OC = 0,
	43	+ MT6358_IRQ_VPROC12_OC,
	44	+ MT6358_IRQ_VCORE_OC,
	45	+ MT6358_IRQ_VGPU_OC,
	46	+ MT6358_IRQ_VMODEM_OC,
	47	+ MT6358_IRQ_VDRAM1_OC,
	48	+ MT6358_IRQ_VS1_OC,
	49	+ MT6358_IRQ_VS2_OC,
	50	+ MT6358_IRQ_VPA_OC,
	51	+ MT6358_IRQ_VCORE_PREOC,
	52	+ MT6358_IRQ_VFE28_OC = 16,
	53	+ MT6358_IRQ_VXO22_OC,
	54	+ MT6358_IRQ_VRF18_OC,
	55	+ MT6358_IRQ_VRF12_OC,
	56	+ MT6358_IRQ_VEFUSE_OC,
	57	+ MT6358_IRQ_VCN33_OC,
	58	+ MT6358_IRQ_VCN28_OC,
	59	+ MT6358_IRQ_VCN18_OC,
	60	+ MT6358_IRQ_VCAMA1_OC,
	61	+ MT6358_IRQ_VCAMA2_OC,
	62	+ MT6358_IRQ_VCAMD_OC,
	63	+ MT6358_IRQ_VCAMIO_OC,
	64	+ MT6358_IRQ_VLDO28_OC,
	65	+ MT6358_IRQ_VA12_OC,
	66	+ MT6358_IRQ_VAUX18_OC,
	67	+ MT6358_IRQ_VAUD28_OC,
	68	+ MT6358_IRQ_VIO28_OC,
	69	+ MT6358_IRQ_VIO18_OC,
	70	+ MT6358_IRQ_VSRAM_PROC11_OC,
	71	+ MT6358_IRQ_VSRAM_PROC12_OC,
	72	+ MT6358_IRQ_VSRAM_OTHERS_OC,
	73	+ MT6358_IRQ_VSRAM_GPU_OC,
	74	+ MT6358_IRQ_VDRAM2_OC,
	75	+ MT6358_IRQ_VMC_OC,
	76	+ MT6358_IRQ_VMCH_OC,
	77	+ MT6358_IRQ_VEMC_OC,
	78	+ MT6358_IRQ_VSIM1_OC,
	79	+ MT6358_IRQ_VSIM2_OC,
	80	+ MT6358_IRQ_VIBR_OC,
	81	+ MT6358_IRQ_VUSB_OC,
	82	+ MT6358_IRQ_VBIF28_OC,
	83	+ MT6358_IRQ_PWRKEY = 48,
	84	+ MT6358_IRQ_HOMEKEY,
	85	+ MT6358_IRQ_PWRKEY_R,
	86	+ MT6358_IRQ_HOMEKEY_R,
	87	+ MT6358_IRQ_NI_LBAT_INT,
	88	+ MT6358_IRQ_CHRDET,
	89	+ MT6358_IRQ_CHRDET_EDGE,
	90	+ MT6358_IRQ_VCDT_HV_DET,
	91	+ MT6358_IRQ_RTC = 64,
	92	+ MT6358_IRQ_FG_BAT0_H = 80,
	93	+ MT6358_IRQ_FG_BAT0_L,
	94	+ MT6358_IRQ_FG_CUR_H,
	95	+ MT6358_IRQ_FG_CUR_L,
	96	+ MT6358_IRQ_FG_ZCV,
	97	+ MT6358_IRQ_FG_BAT1_H,
	98	+ MT6358_IRQ_FG_BAT1_L,
	99	+ MT6358_IRQ_FG_N_CHARGE_L,
	100	+ MT6358_IRQ_FG_IAVG_H,
	101	+ MT6358_IRQ_FG_IAVG_L,
	102	+ MT6358_IRQ_FG_TIME_H,
	103	+ MT6358_IRQ_FG_DISCHARGE,
	104	+ MT6358_IRQ_FG_CHARGE,
	105	+ MT6358_IRQ_BATON_LV = 96,
	106	+ MT6358_IRQ_BATON_HT,
	107	+ MT6358_IRQ_BATON_BAT_IN,
	108	+ MT6358_IRQ_BATON_BAT_OUT,
	109	+ MT6358_IRQ_BIF,
	110	+ MT6358_IRQ_BAT_H = 112,
	111	+ MT6358_IRQ_BAT_L,
	112	+ MT6358_IRQ_BAT2_H,
	113	+ MT6358_IRQ_BAT2_L,
	114	+ MT6358_IRQ_BAT_TEMP_H,
	115	+ MT6358_IRQ_BAT_TEMP_L,
	116	+ MT6358_IRQ_AUXADC_IMP,
	117	+ MT6358_IRQ_NAG_C_DLTV,
	118	+ MT6358_IRQ_AUDIO = 128,
	119	+ MT6358_IRQ_ACCDET = 133,
	120	+ MT6358_IRQ_ACCDET_EINT0,
	121	+ MT6358_IRQ_ACCDET_EINT1,
	122	+ MT6358_IRQ_SPI_CMD_ALERT = 144,
	123	+ MT6358_IRQ_NR,
	124	+};
	125	+
	126	+#define MT6358_IRQ_BUCK_BASE MT6358_IRQ_VPROC11_OC
	127	+#define MT6358_IRQ_LDO_BASE MT6358_IRQ_VFE28_OC
	128	+#define MT6358_IRQ_PSC_BASE MT6358_IRQ_PWRKEY
	129	+#define MT6358_IRQ_SCK_BASE MT6358_IRQ_RTC
	130	+#define MT6358_IRQ_BM_BASE MT6358_IRQ_FG_BAT0_H
	131	+#define MT6358_IRQ_HK_BASE MT6358_IRQ_BAT_H
	132	+#define MT6358_IRQ_AUD_BASE MT6358_IRQ_AUDIO
	133	+#define MT6358_IRQ_MISC_BASE MT6358_IRQ_SPI_CMD_ALERT
	134	+
	135	+#define MT6358_IRQ_BUCK_BITS (MT6358_IRQ_VCORE_PREOC - MT6358_IRQ_BUCK_BASE + 1)
	136	+#define MT6358_IRQ_LDO_BITS (MT6358_IRQ_VBIF28_OC - MT6358_IRQ_LDO_BASE + 1)
	137	+#define MT6358_IRQ_PSC_BITS (MT6358_IRQ_VCDT_HV_DET - MT6358_IRQ_PSC_BASE + 1)
	138	+#define MT6358_IRQ_SCK_BITS (MT6358_IRQ_RTC - MT6358_IRQ_SCK_BASE + 1)
	139	+#define MT6358_IRQ_BM_BITS (MT6358_IRQ_BIF - MT6358_IRQ_BM_BASE + 1)
	140	+#define MT6358_IRQ_HK_BITS (MT6358_IRQ_NAG_C_DLTV - MT6358_IRQ_HK_BASE + 1)
	141	+#define MT6358_IRQ_AUD_BITS (MT6358_IRQ_ACCDET_EINT1 - MT6358_IRQ_AUD_BASE + 1)
	142	+#define MT6358_IRQ_MISC_BITS \
	143	+ (MT6358_IRQ_SPI_CMD_ALERT - MT6358_IRQ_MISC_BASE + 1)
	144	+
	145	+#define MT6358_TOP_GEN(sp) \
	146	+{ \
	147	+ .hwirq_base = MT6358_IRQ_##sp##_BASE, \
	148	+ .num_int_regs = \
	149	+ ((MT6358_IRQ_##sp##_BITS - 1) / MT6358_REG_WIDTH) + 1, \
	150	+ .num_int_bits = MT6358_IRQ_##sp##_BITS, \
	151	+ .en_reg = MT6358_##sp##_TOP_INT_CON0, \
	152	+ .en_reg_shift = 0x6, \
	153	+ .sta_reg = MT6358_##sp##_TOP_INT_STATUS0, \
	154	+ .sta_reg_shift = 0x2, \
	155	+ .top_offset = MT6358_##sp##_TOP, \
	156	+}
	157	+
	158	+#endif /* __MFD_MT6358_CORE_H__ */

include/linux/mfd/mt6358/registers.h+282−0

@@ -0,0 +1,282 @@
	1	+/* SPDX-License-Identifier: GPL-2.0 */
	2	+/*
	3	+ * Copyright (c) 2020 MediaTek Inc.
	4	+ */
	5	+
	6	+#ifndef __MFD_MT6358_REGISTERS_H__
	7	+#define __MFD_MT6358_REGISTERS_H__
	8	+
	9	+/* PMIC Registers */
	10	+#define MT6358_SWCID 0xa
	11	+#define MT6358_MISC_TOP_INT_CON0 0x188
	12	+#define MT6358_MISC_TOP_INT_STATUS0 0x194
	13	+#define MT6358_TOP_INT_STATUS0 0x19e
	14	+#define MT6358_SCK_TOP_INT_CON0 0x52e
	15	+#define MT6358_SCK_TOP_INT_STATUS0 0x53a
	16	+#define MT6358_EOSC_CALI_CON0 0x540
	17	+#define MT6358_EOSC_CALI_CON1 0x542
	18	+#define MT6358_RTC_MIX_CON0 0x544
	19	+#define MT6358_RTC_MIX_CON1 0x546
	20	+#define MT6358_RTC_MIX_CON2 0x548
	21	+#define MT6358_RTC_DSN_ID 0x580
	22	+#define MT6358_RTC_DSN_REV0 0x582
	23	+#define MT6358_RTC_DBI 0x584
	24	+#define MT6358_RTC_DXI 0x586
	25	+#define MT6358_RTC_BBPU 0x588
	26	+#define MT6358_RTC_IRQ_STA 0x58a
	27	+#define MT6358_RTC_IRQ_EN 0x58c
	28	+#define MT6358_RTC_CII_EN 0x58e
	29	+#define MT6358_RTC_AL_MASK 0x590
	30	+#define MT6358_RTC_TC_SEC 0x592
	31	+#define MT6358_RTC_TC_MIN 0x594
	32	+#define MT6358_RTC_TC_HOU 0x596
	33	+#define MT6358_RTC_TC_DOM 0x598
	34	+#define MT6358_RTC_TC_DOW 0x59a
	35	+#define MT6358_RTC_TC_MTH 0x59c
	36	+#define MT6358_RTC_TC_YEA 0x59e
	37	+#define MT6358_RTC_AL_SEC 0x5a0
	38	+#define MT6358_RTC_AL_MIN 0x5a2
	39	+#define MT6358_RTC_AL_HOU 0x5a4
	40	+#define MT6358_RTC_AL_DOM 0x5a6
	41	+#define MT6358_RTC_AL_DOW 0x5a8
	42	+#define MT6358_RTC_AL_MTH 0x5aa
	43	+#define MT6358_RTC_AL_YEA 0x5ac
	44	+#define MT6358_RTC_OSC32CON 0x5ae
	45	+#define MT6358_RTC_POWERKEY1 0x5b0
	46	+#define MT6358_RTC_POWERKEY2 0x5b2
	47	+#define MT6358_RTC_PDN1 0x5b4
	48	+#define MT6358_RTC_PDN2 0x5b6
	49	+#define MT6358_RTC_SPAR0 0x5b8
	50	+#define MT6358_RTC_SPAR1 0x5ba
	51	+#define MT6358_RTC_PROT 0x5bc
	52	+#define MT6358_RTC_DIFF 0x5be
	53	+#define MT6358_RTC_CALI 0x5c0
	54	+#define MT6358_RTC_WRTGR 0x5c2
	55	+#define MT6358_RTC_CON 0x5c4
	56	+#define MT6358_RTC_SEC_CTRL 0x5c6
	57	+#define MT6358_RTC_INT_CNT 0x5c8
	58	+#define MT6358_RTC_SEC_DAT0 0x5ca
	59	+#define MT6358_RTC_SEC_DAT1 0x5cc
	60	+#define MT6358_RTC_SEC_DAT2 0x5ce
	61	+#define MT6358_RTC_SEC_DSN_ID 0x600
	62	+#define MT6358_RTC_SEC_DSN_REV0 0x602
	63	+#define MT6358_RTC_SEC_DBI 0x604
	64	+#define MT6358_RTC_SEC_DXI 0x606
	65	+#define MT6358_RTC_TC_SEC_SEC 0x608
	66	+#define MT6358_RTC_TC_MIN_SEC 0x60a
	67	+#define MT6358_RTC_TC_HOU_SEC 0x60c
	68	+#define MT6358_RTC_TC_DOM_SEC 0x60e
	69	+#define MT6358_RTC_TC_DOW_SEC 0x610
	70	+#define MT6358_RTC_TC_MTH_SEC 0x612
	71	+#define MT6358_RTC_TC_YEA_SEC 0x614
	72	+#define MT6358_RTC_SEC_CK_PDN 0x616
	73	+#define MT6358_RTC_SEC_WRTGR 0x618
	74	+#define MT6358_PSC_TOP_INT_CON0 0x910
	75	+#define MT6358_PSC_TOP_INT_STATUS0 0x91c
	76	+#define MT6358_BM_TOP_INT_CON0 0xc32
	77	+#define MT6358_BM_TOP_INT_CON1 0xc38
	78	+#define MT6358_BM_TOP_INT_STATUS0 0xc4a
	79	+#define MT6358_BM_TOP_INT_STATUS1 0xc4c
	80	+#define MT6358_HK_TOP_INT_CON0 0xf92
	81	+#define MT6358_HK_TOP_INT_STATUS0 0xf9e
	82	+#define MT6358_BUCK_TOP_INT_CON0 0x1318
	83	+#define MT6358_BUCK_TOP_INT_STATUS0 0x1324
	84	+#define MT6358_BUCK_VPROC11_CON0 0x1388
	85	+#define MT6358_BUCK_VPROC11_DBG0 0x139e
	86	+#define MT6358_BUCK_VPROC11_DBG1 0x13a0
	87	+#define MT6358_BUCK_VPROC11_ELR0 0x13a6
	88	+#define MT6358_BUCK_VPROC12_CON0 0x1408
	89	+#define MT6358_BUCK_VPROC12_DBG0 0x141e
	90	+#define MT6358_BUCK_VPROC12_DBG1 0x1420
	91	+#define MT6358_BUCK_VPROC12_ELR0 0x1426
	92	+#define MT6358_BUCK_VCORE_CON0 0x1488
	93	+#define MT6358_BUCK_VCORE_DBG0 0x149e
	94	+#define MT6358_BUCK_VCORE_DBG1 0x14a0
	95	+#define MT6358_BUCK_VCORE_ELR0 0x14aa
	96	+#define MT6358_BUCK_VGPU_CON0 0x1508
	97	+#define MT6358_BUCK_VGPU_DBG0 0x151e
	98	+#define MT6358_BUCK_VGPU_DBG1 0x1520
	99	+#define MT6358_BUCK_VGPU_ELR0 0x1526
	100	+#define MT6358_BUCK_VMODEM_CON0 0x1588
	101	+#define MT6358_BUCK_VMODEM_DBG0 0x159e
	102	+#define MT6358_BUCK_VMODEM_DBG1 0x15a0
	103	+#define MT6358_BUCK_VMODEM_ELR0 0x15a6
	104	+#define MT6358_BUCK_VDRAM1_CON0 0x1608
	105	+#define MT6358_BUCK_VDRAM1_DBG0 0x161e
	106	+#define MT6358_BUCK_VDRAM1_DBG1 0x1620
	107	+#define MT6358_BUCK_VDRAM1_ELR0 0x1626
	108	+#define MT6358_BUCK_VS1_CON0 0x1688
	109	+#define MT6358_BUCK_VS1_DBG0 0x169e
	110	+#define MT6358_BUCK_VS1_DBG1 0x16a0
	111	+#define MT6358_BUCK_VS1_ELR0 0x16ae
	112	+#define MT6358_BUCK_VS2_CON0 0x1708
	113	+#define MT6358_BUCK_VS2_DBG0 0x171e
	114	+#define MT6358_BUCK_VS2_DBG1 0x1720
	115	+#define MT6358_BUCK_VS2_ELR0 0x172e
	116	+#define MT6358_BUCK_VPA_CON0 0x1788
	117	+#define MT6358_BUCK_VPA_CON1 0x178a
	118	+#define MT6358_BUCK_VPA_ELR0 MT6358_BUCK_VPA_CON1
	119	+#define MT6358_BUCK_VPA_DBG0 0x1792
	120	+#define MT6358_BUCK_VPA_DBG1 0x1794
	121	+#define MT6358_VPROC_ANA_CON0 0x180c
	122	+#define MT6358_VCORE_VGPU_ANA_CON0 0x1828
	123	+#define MT6358_VMODEM_ANA_CON0 0x1888
	124	+#define MT6358_VDRAM1_ANA_CON0 0x1896
	125	+#define MT6358_VS1_ANA_CON0 0x18a2
	126	+#define MT6358_VS2_ANA_CON0 0x18ae
	127	+#define MT6358_VPA_ANA_CON0 0x18ba
	128	+#define MT6358_LDO_TOP_INT_CON0 0x1a50
	129	+#define MT6358_LDO_TOP_INT_CON1 0x1a56
	130	+#define MT6358_LDO_TOP_INT_STATUS0 0x1a68
	131	+#define MT6358_LDO_TOP_INT_STATUS1 0x1a6a
	132	+#define MT6358_LDO_VXO22_CON0 0x1a88
	133	+#define MT6358_LDO_VXO22_CON1 0x1a96
	134	+#define MT6358_LDO_VA12_CON0 0x1a9c
	135	+#define MT6358_LDO_VA12_CON1 0x1aaa
	136	+#define MT6358_LDO_VAUX18_CON0 0x1ab0
	137	+#define MT6358_LDO_VAUX18_CON1 0x1abe
	138	+#define MT6358_LDO_VAUD28_CON0 0x1ac4
	139	+#define MT6358_LDO_VAUD28_CON1 0x1ad2
	140	+#define MT6358_LDO_VIO28_CON0 0x1ad8
	141	+#define MT6358_LDO_VIO28_CON1 0x1ae6
	142	+#define MT6358_LDO_VIO18_CON0 0x1aec
	143	+#define MT6358_LDO_VIO18_CON1 0x1afa
	144	+#define MT6358_LDO_VDRAM2_CON0 0x1b08
	145	+#define MT6358_LDO_VDRAM2_CON1 0x1b16
	146	+#define MT6358_LDO_VEMC_CON0 0x1b1c
	147	+#define MT6358_LDO_VEMC_CON1 0x1b2a
	148	+#define MT6358_LDO_VUSB_CON0_0 0x1b30
	149	+#define MT6358_LDO_VUSB_CON1 0x1b40
	150	+#define MT6358_LDO_VSRAM_PROC11_CON0 0x1b46
	151	+#define MT6358_LDO_VSRAM_PROC11_DBG0 0x1b60
	152	+#define MT6358_LDO_VSRAM_PROC11_DBG1 0x1b62
	153	+#define MT6358_LDO_VSRAM_PROC11_TRACKING_CON0 0x1b64
	154	+#define MT6358_LDO_VSRAM_PROC11_TRACKING_CON1 0x1b66
	155	+#define MT6358_LDO_VSRAM_PROC11_TRACKING_CON2 0x1b68
	156	+#define MT6358_LDO_VSRAM_PROC11_TRACKING_CON3 0x1b6a
	157	+#define MT6358_LDO_VSRAM_PROC12_TRACKING_CON0 0x1b6c
	158	+#define MT6358_LDO_VSRAM_PROC12_TRACKING_CON1 0x1b6e
	159	+#define MT6358_LDO_VSRAM_PROC12_TRACKING_CON2 0x1b70
	160	+#define MT6358_LDO_VSRAM_PROC12_TRACKING_CON3 0x1b72
	161	+#define MT6358_LDO_VSRAM_WAKEUP_CON0 0x1b74
	162	+#define MT6358_LDO_GON1_ELR_NUM 0x1b76
	163	+#define MT6358_LDO_VDRAM2_ELR0 0x1b78
	164	+#define MT6358_LDO_VSRAM_PROC12_CON0 0x1b88
	165	+#define MT6358_LDO_VSRAM_PROC12_DBG0 0x1ba2
	166	+#define MT6358_LDO_VSRAM_PROC12_DBG1 0x1ba4
	167	+#define MT6358_LDO_VSRAM_OTHERS_CON0 0x1ba6
	168	+#define MT6358_LDO_VSRAM_OTHERS_DBG0 0x1bc0
	169	+#define MT6358_LDO_VSRAM_OTHERS_DBG1 0x1bc2
	170	+#define MT6358_LDO_VSRAM_GPU_CON0 0x1bc8
	171	+#define MT6358_LDO_VSRAM_GPU_DBG0 0x1be2
	172	+#define MT6358_LDO_VSRAM_GPU_DBG1 0x1be4
	173	+#define MT6358_LDO_VSRAM_CON0 0x1bee
	174	+#define MT6358_LDO_VSRAM_CON1 0x1bf0
	175	+#define MT6358_LDO_VSRAM_CON2 0x1bf2
	176	+#define MT6358_LDO_VSRAM_CON3 0x1bf4
	177	+#define MT6358_LDO_VFE28_CON0 0x1c08
	178	+#define MT6358_LDO_VFE28_CON1 0x1c16
	179	+#define MT6358_LDO_VFE28_CON2 0x1c18
	180	+#define MT6358_LDO_VFE28_CON3 0x1c1a
	181	+#define MT6358_LDO_VRF18_CON0 0x1c1c
	182	+#define MT6358_LDO_VRF18_CON1 0x1c2a
	183	+#define MT6358_LDO_VRF18_CON2 0x1c2c
	184	+#define MT6358_LDO_VRF18_CON3 0x1c2e
	185	+#define MT6358_LDO_VRF12_CON0 0x1c30
	186	+#define MT6358_LDO_VRF12_CON1 0x1c3e
	187	+#define MT6358_LDO_VRF12_CON2 0x1c40
	188	+#define MT6358_LDO_VRF12_CON3 0x1c42
	189	+#define MT6358_LDO_VEFUSE_CON0 0x1c44
	190	+#define MT6358_LDO_VEFUSE_CON1 0x1c52
	191	+#define MT6358_LDO_VEFUSE_CON2 0x1c54
	192	+#define MT6358_LDO_VEFUSE_CON3 0x1c56
	193	+#define MT6358_LDO_VCN18_CON0 0x1c58
	194	+#define MT6358_LDO_VCN18_CON1 0x1c66
	195	+#define MT6358_LDO_VCN18_CON2 0x1c68
	196	+#define MT6358_LDO_VCN18_CON3 0x1c6a
	197	+#define MT6358_LDO_VCAMA1_CON0 0x1c6c
	198	+#define MT6358_LDO_VCAMA1_CON1 0x1c7a
	199	+#define MT6358_LDO_VCAMA1_CON2 0x1c7c
	200	+#define MT6358_LDO_VCAMA1_CON3 0x1c7e
	201	+#define MT6358_LDO_VCAMA2_CON0 0x1c88
	202	+#define MT6358_LDO_VCAMA2_CON1 0x1c96
	203	+#define MT6358_LDO_VCAMA2_CON2 0x1c98
	204	+#define MT6358_LDO_VCAMA2_CON3 0x1c9a
	205	+#define MT6358_LDO_VCAMD_CON0 0x1c9c
	206	+#define MT6358_LDO_VCAMD_CON1 0x1caa
	207	+#define MT6358_LDO_VCAMD_CON2 0x1cac
	208	+#define MT6358_LDO_VCAMD_CON3 0x1cae
	209	+#define MT6358_LDO_VCAMIO_CON0 0x1cb0
	210	+#define MT6358_LDO_VCAMIO_CON1 0x1cbe
	211	+#define MT6358_LDO_VCAMIO_CON2 0x1cc0
	212	+#define MT6358_LDO_VCAMIO_CON3 0x1cc2
	213	+#define MT6358_LDO_VMC_CON0 0x1cc4
	214	+#define MT6358_LDO_VMC_CON1 0x1cd2
	215	+#define MT6358_LDO_VMC_CON2 0x1cd4
	216	+#define MT6358_LDO_VMC_CON3 0x1cd6
	217	+#define MT6358_LDO_VMCH_CON0 0x1cd8
	218	+#define MT6358_LDO_VMCH_CON1 0x1ce6
	219	+#define MT6358_LDO_VMCH_CON2 0x1ce8
	220	+#define MT6358_LDO_VMCH_CON3 0x1cea
	221	+#define MT6358_LDO_VIBR_CON0 0x1d08
	222	+#define MT6358_LDO_VIBR_CON1 0x1d16
	223	+#define MT6358_LDO_VIBR_CON2 0x1d18
	224	+#define MT6358_LDO_VIBR_CON3 0x1d1a
	225	+#define MT6358_LDO_VCN33_CON0_0 0x1d1c
	226	+#define MT6358_LDO_VCN33_CON0_1 0x1d2a
	227	+#define MT6358_LDO_VCN33_CON1 0x1d2c
	228	+#define MT6358_LDO_VCN33_BT_CON1 MT6358_LDO_VCN33_CON1
	229	+#define MT6358_LDO_VCN33_WIFI_CON1 MT6358_LDO_VCN33_CON1
	230	+#define MT6358_LDO_VCN33_CON2 0x1d2e
	231	+#define MT6358_LDO_VCN33_CON3 0x1d30
	232	+#define MT6358_LDO_VLDO28_CON0_0 0x1d32
	233	+#define MT6358_LDO_VLDO28_CON0_1 0x1d40
	234	+#define MT6358_LDO_VLDO28_CON1 0x1d42
	235	+#define MT6358_LDO_VLDO28_CON2 0x1d44
	236	+#define MT6358_LDO_VLDO28_CON3 0x1d46
	237	+#define MT6358_LDO_VSIM1_CON0 0x1d48
	238	+#define MT6358_LDO_VSIM1_CON1 0x1d56
	239	+#define MT6358_LDO_VSIM1_CON2 0x1d58
	240	+#define MT6358_LDO_VSIM1_CON3 0x1d5a
	241	+#define MT6358_LDO_VSIM2_CON0 0x1d5c
	242	+#define MT6358_LDO_VSIM2_CON1 0x1d6a
	243	+#define MT6358_LDO_VSIM2_CON2 0x1d6c
	244	+#define MT6358_LDO_VSIM2_CON3 0x1d6e
	245	+#define MT6358_LDO_VCN28_CON0 0x1d88
	246	+#define MT6358_LDO_VCN28_CON1 0x1d96
	247	+#define MT6358_LDO_VCN28_CON2 0x1d98
	248	+#define MT6358_LDO_VCN28_CON3 0x1d9a
	249	+#define MT6358_VRTC28_CON0 0x1d9c
	250	+#define MT6358_LDO_VBIF28_CON0 0x1d9e
	251	+#define MT6358_LDO_VBIF28_CON1 0x1dac
	252	+#define MT6358_LDO_VBIF28_CON2 0x1dae
	253	+#define MT6358_LDO_VBIF28_CON3 0x1db0
	254	+#define MT6358_VCAMA1_ANA_CON0 0x1e08
	255	+#define MT6358_VCAMA2_ANA_CON0 0x1e0c
	256	+#define MT6358_VCN33_ANA_CON0 0x1e28
	257	+#define MT6358_VSIM1_ANA_CON0 0x1e2c
	258	+#define MT6358_VSIM2_ANA_CON0 0x1e30
	259	+#define MT6358_VUSB_ANA_CON0 0x1e34
	260	+#define MT6358_VEMC_ANA_CON0 0x1e38
	261	+#define MT6358_VLDO28_ANA_CON0 0x1e3c
	262	+#define MT6358_VIO28_ANA_CON0 0x1e40
	263	+#define MT6358_VIBR_ANA_CON0 0x1e44
	264	+#define MT6358_VMCH_ANA_CON0 0x1e48
	265	+#define MT6358_VMC_ANA_CON0 0x1e4c
	266	+#define MT6358_VRF18_ANA_CON0 0x1e88
	267	+#define MT6358_VCN18_ANA_CON0 0x1e8c
	268	+#define MT6358_VCAMIO_ANA_CON0 0x1e90
	269	+#define MT6358_VIO18_ANA_CON0 0x1e94
	270	+#define MT6358_VEFUSE_ANA_CON0 0x1e98
	271	+#define MT6358_VRF12_ANA_CON0 0x1e9c
	272	+#define MT6358_VSRAM_PROC11_ANA_CON0 0x1ea0
	273	+#define MT6358_VSRAM_PROC12_ANA_CON0 0x1ea4
	274	+#define MT6358_VSRAM_OTHERS_ANA_CON0 0x1ea6
	275	+#define MT6358_VSRAM_GPU_ANA_CON0 0x1ea8
	276	+#define MT6358_VDRAM2_ANA_CON0 0x1eaa
	277	+#define MT6358_VCAMD_ANA_CON0 0x1eae
	278	+#define MT6358_VA12_ANA_CON0 0x1eb2
	279	+#define MT6358_AUD_TOP_INT_CON0 0x2228
	280	+#define MT6358_AUD_TOP_INT_STATUS0 0x2234
	281	+
	282	+#endif /* __MFD_MT6358_REGISTERS_H__ */

include/linux/mfd/mt6360.h+240−0

@@ -0,0 +1,240 @@
	1	+/* SPDX-License-Identifier: GPL-2.0 */
	2	+/*
	3	+ * Copyright (c) 2020 MediaTek Inc.
	4	+ */
	5	+
	6	+#ifndef __MT6360_H__
	7	+#define __MT6360_H__
	8	+
	9	+#include <linux/regmap.h>
	10	+
	11	+enum {
	12	+ MT6360_SLAVE_PMU = 0,
	13	+ MT6360_SLAVE_PMIC,
	14	+ MT6360_SLAVE_LDO,
	15	+ MT6360_SLAVE_TCPC,
	16	+ MT6360_SLAVE_MAX,
	17	+};
	18	+
	19	+#define MT6360_PMU_SLAVEID (0x34)
	20	+#define MT6360_PMIC_SLAVEID (0x1A)
	21	+#define MT6360_LDO_SLAVEID (0x64)
	22	+#define MT6360_TCPC_SLAVEID (0x4E)
	23	+
	24	+struct mt6360_pmu_data {
	25	+ struct i2c_client *i2c[MT6360_SLAVE_MAX];
	26	+ struct device *dev;
	27	+ struct regmap *regmap;
	28	+ struct regmap_irq_chip_data *irq_data;
	29	+ unsigned int chip_rev;
	30	+};
	31	+
	32	+/* PMU register defininition */
	33	+#define MT6360_PMU_DEV_INFO (0x00)
	34	+#define MT6360_PMU_CORE_CTRL1 (0x01)
	35	+#define MT6360_PMU_RST1 (0x02)
	36	+#define MT6360_PMU_CRCEN (0x03)
	37	+#define MT6360_PMU_RST_PAS_CODE1 (0x04)
	38	+#define MT6360_PMU_RST_PAS_CODE2 (0x05)
	39	+#define MT6360_PMU_CORE_CTRL2 (0x06)
	40	+#define MT6360_PMU_TM_PAS_CODE1 (0x07)
	41	+#define MT6360_PMU_TM_PAS_CODE2 (0x08)
	42	+#define MT6360_PMU_TM_PAS_CODE3 (0x09)
	43	+#define MT6360_PMU_TM_PAS_CODE4 (0x0A)
	44	+#define MT6360_PMU_IRQ_IND (0x0B)
	45	+#define MT6360_PMU_IRQ_MASK (0x0C)
	46	+#define MT6360_PMU_IRQ_SET (0x0D)
	47	+#define MT6360_PMU_SHDN_CTRL (0x0E)
	48	+#define MT6360_PMU_TM_INF (0x0F)
	49	+#define MT6360_PMU_I2C_CTRL (0x10)
	50	+#define MT6360_PMU_CHG_CTRL1 (0x11)
	51	+#define MT6360_PMU_CHG_CTRL2 (0x12)
	52	+#define MT6360_PMU_CHG_CTRL3 (0x13)
	53	+#define MT6360_PMU_CHG_CTRL4 (0x14)
	54	+#define MT6360_PMU_CHG_CTRL5 (0x15)
	55	+#define MT6360_PMU_CHG_CTRL6 (0x16)
	56	+#define MT6360_PMU_CHG_CTRL7 (0x17)
	57	+#define MT6360_PMU_CHG_CTRL8 (0x18)
	58	+#define MT6360_PMU_CHG_CTRL9 (0x19)
	59	+#define MT6360_PMU_CHG_CTRL10 (0x1A)
	60	+#define MT6360_PMU_CHG_CTRL11 (0x1B)
	61	+#define MT6360_PMU_CHG_CTRL12 (0x1C)
	62	+#define MT6360_PMU_CHG_CTRL13 (0x1D)
	63	+#define MT6360_PMU_CHG_CTRL14 (0x1E)
	64	+#define MT6360_PMU_CHG_CTRL15 (0x1F)
	65	+#define MT6360_PMU_CHG_CTRL16 (0x20)
	66	+#define MT6360_PMU_CHG_AICC_RESULT (0x21)
	67	+#define MT6360_PMU_DEVICE_TYPE (0x22)
	68	+#define MT6360_PMU_QC_CONTROL1 (0x23)
	69	+#define MT6360_PMU_QC_CONTROL2 (0x24)
	70	+#define MT6360_PMU_QC30_CONTROL1 (0x25)
	71	+#define MT6360_PMU_QC30_CONTROL2 (0x26)
	72	+#define MT6360_PMU_USB_STATUS1 (0x27)
	73	+#define MT6360_PMU_QC_STATUS1 (0x28)
	74	+#define MT6360_PMU_QC_STATUS2 (0x29)
	75	+#define MT6360_PMU_CHG_PUMP (0x2A)
	76	+#define MT6360_PMU_CHG_CTRL17 (0x2B)
	77	+#define MT6360_PMU_CHG_CTRL18 (0x2C)
	78	+#define MT6360_PMU_CHRDET_CTRL1 (0x2D)
	79	+#define MT6360_PMU_CHRDET_CTRL2 (0x2E)
	80	+#define MT6360_PMU_DPDN_CTRL (0x2F)
	81	+#define MT6360_PMU_CHG_HIDDEN_CTRL1 (0x30)
	82	+#define MT6360_PMU_CHG_HIDDEN_CTRL2 (0x31)
	83	+#define MT6360_PMU_CHG_HIDDEN_CTRL3 (0x32)
	84	+#define MT6360_PMU_CHG_HIDDEN_CTRL4 (0x33)
	85	+#define MT6360_PMU_CHG_HIDDEN_CTRL5 (0x34)
	86	+#define MT6360_PMU_CHG_HIDDEN_CTRL6 (0x35)
	87	+#define MT6360_PMU_CHG_HIDDEN_CTRL7 (0x36)
	88	+#define MT6360_PMU_CHG_HIDDEN_CTRL8 (0x37)
	89	+#define MT6360_PMU_CHG_HIDDEN_CTRL9 (0x38)
	90	+#define MT6360_PMU_CHG_HIDDEN_CTRL10 (0x39)
	91	+#define MT6360_PMU_CHG_HIDDEN_CTRL11 (0x3A)
	92	+#define MT6360_PMU_CHG_HIDDEN_CTRL12 (0x3B)
	93	+#define MT6360_PMU_CHG_HIDDEN_CTRL13 (0x3C)
	94	+#define MT6360_PMU_CHG_HIDDEN_CTRL14 (0x3D)
	95	+#define MT6360_PMU_CHG_HIDDEN_CTRL15 (0x3E)
	96	+#define MT6360_PMU_CHG_HIDDEN_CTRL16 (0x3F)
	97	+#define MT6360_PMU_CHG_HIDDEN_CTRL17 (0x40)
	98	+#define MT6360_PMU_CHG_HIDDEN_CTRL18 (0x41)
	99	+#define MT6360_PMU_CHG_HIDDEN_CTRL19 (0x42)
	100	+#define MT6360_PMU_CHG_HIDDEN_CTRL20 (0x43)
	101	+#define MT6360_PMU_CHG_HIDDEN_CTRL21 (0x44)
	102	+#define MT6360_PMU_CHG_HIDDEN_CTRL22 (0x45)
	103	+#define MT6360_PMU_CHG_HIDDEN_CTRL23 (0x46)
	104	+#define MT6360_PMU_CHG_HIDDEN_CTRL24 (0x47)
	105	+#define MT6360_PMU_CHG_HIDDEN_CTRL25 (0x48)
	106	+#define MT6360_PMU_BC12_CTRL (0x49)
	107	+#define MT6360_PMU_CHG_STAT (0x4A)
	108	+#define MT6360_PMU_RESV1 (0x4B)
	109	+#define MT6360_PMU_TYPEC_OTP_TH_SEL_CODEH (0x4E)
	110	+#define MT6360_PMU_TYPEC_OTP_TH_SEL_CODEL (0x4F)
	111	+#define MT6360_PMU_TYPEC_OTP_HYST_TH (0x50)
	112	+#define MT6360_PMU_TYPEC_OTP_CTRL (0x51)
	113	+#define MT6360_PMU_ADC_BAT_DATA_H (0x52)
	114	+#define MT6360_PMU_ADC_BAT_DATA_L (0x53)
	115	+#define MT6360_PMU_IMID_BACKBST_ON (0x54)
	116	+#define MT6360_PMU_IMID_BACKBST_OFF (0x55)
	117	+#define MT6360_PMU_ADC_CONFIG (0x56)
	118	+#define MT6360_PMU_ADC_EN2 (0x57)
	119	+#define MT6360_PMU_ADC_IDLE_T (0x58)
	120	+#define MT6360_PMU_ADC_RPT_1 (0x5A)
	121	+#define MT6360_PMU_ADC_RPT_2 (0x5B)
	122	+#define MT6360_PMU_ADC_RPT_3 (0x5C)
	123	+#define MT6360_PMU_ADC_RPT_ORG1 (0x5D)
	124	+#define MT6360_PMU_ADC_RPT_ORG2 (0x5E)
	125	+#define MT6360_PMU_BAT_OVP_TH_SEL_CODEH (0x5F)
	126	+#define MT6360_PMU_BAT_OVP_TH_SEL_CODEL (0x60)
	127	+#define MT6360_PMU_CHG_CTRL19 (0x61)
	128	+#define MT6360_PMU_VDDASUPPLY (0x62)
	129	+#define MT6360_PMU_BC12_MANUAL (0x63)
	130	+#define MT6360_PMU_CHGDET_FUNC (0x64)
	131	+#define MT6360_PMU_FOD_CTRL (0x65)
	132	+#define MT6360_PMU_CHG_CTRL20 (0x66)
	133	+#define MT6360_PMU_CHG_HIDDEN_CTRL26 (0x67)
	134	+#define MT6360_PMU_CHG_HIDDEN_CTRL27 (0x68)
	135	+#define MT6360_PMU_RESV2 (0x69)
	136	+#define MT6360_PMU_USBID_CTRL1 (0x6D)
	137	+#define MT6360_PMU_USBID_CTRL2 (0x6E)
	138	+#define MT6360_PMU_USBID_CTRL3 (0x6F)
	139	+#define MT6360_PMU_FLED_CFG (0x70)
	140	+#define MT6360_PMU_RESV3 (0x71)
	141	+#define MT6360_PMU_FLED1_CTRL (0x72)
	142	+#define MT6360_PMU_FLED_STRB_CTRL (0x73)
	143	+#define MT6360_PMU_FLED1_STRB_CTRL2 (0x74)
	144	+#define MT6360_PMU_FLED1_TOR_CTRL (0x75)
	145	+#define MT6360_PMU_FLED2_CTRL (0x76)
	146	+#define MT6360_PMU_RESV4 (0x77)
	147	+#define MT6360_PMU_FLED2_STRB_CTRL2 (0x78)
	148	+#define MT6360_PMU_FLED2_TOR_CTRL (0x79)
	149	+#define MT6360_PMU_FLED_VMIDTRK_CTRL1 (0x7A)
	150	+#define MT6360_PMU_FLED_VMID_RTM (0x7B)
	151	+#define MT6360_PMU_FLED_VMIDTRK_CTRL2 (0x7C)
	152	+#define MT6360_PMU_FLED_PWSEL (0x7D)
	153	+#define MT6360_PMU_FLED_EN (0x7E)
	154	+#define MT6360_PMU_FLED_Hidden1 (0x7F)
	155	+#define MT6360_PMU_RGB_EN (0x80)
	156	+#define MT6360_PMU_RGB1_ISNK (0x81)
	157	+#define MT6360_PMU_RGB2_ISNK (0x82)
	158	+#define MT6360_PMU_RGB3_ISNK (0x83)
	159	+#define MT6360_PMU_RGB_ML_ISNK (0x84)
	160	+#define MT6360_PMU_RGB1_DIM (0x85)
	161	+#define MT6360_PMU_RGB2_DIM (0x86)
	162	+#define MT6360_PMU_RGB3_DIM (0x87)
	163	+#define MT6360_PMU_RESV5 (0x88)
	164	+#define MT6360_PMU_RGB12_Freq (0x89)
	165	+#define MT6360_PMU_RGB34_Freq (0x8A)
	166	+#define MT6360_PMU_RGB1_Tr (0x8B)
	167	+#define MT6360_PMU_RGB1_Tf (0x8C)
	168	+#define MT6360_PMU_RGB1_TON_TOFF (0x8D)
	169	+#define MT6360_PMU_RGB2_Tr (0x8E)
	170	+#define MT6360_PMU_RGB2_Tf (0x8F)
	171	+#define MT6360_PMU_RGB2_TON_TOFF (0x90)
	172	+#define MT6360_PMU_RGB3_Tr (0x91)
	173	+#define MT6360_PMU_RGB3_Tf (0x92)
	174	+#define MT6360_PMU_RGB3_TON_TOFF (0x93)
	175	+#define MT6360_PMU_RGB_Hidden_CTRL1 (0x94)
	176	+#define MT6360_PMU_RGB_Hidden_CTRL2 (0x95)
	177	+#define MT6360_PMU_RESV6 (0x97)
	178	+#define MT6360_PMU_SPARE1 (0x9A)
	179	+#define MT6360_PMU_SPARE2 (0xA0)
	180	+#define MT6360_PMU_SPARE3 (0xB0)
	181	+#define MT6360_PMU_SPARE4 (0xC0)
	182	+#define MT6360_PMU_CHG_IRQ1 (0xD0)
	183	+#define MT6360_PMU_CHG_IRQ2 (0xD1)
	184	+#define MT6360_PMU_CHG_IRQ3 (0xD2)
	185	+#define MT6360_PMU_CHG_IRQ4 (0xD3)
	186	+#define MT6360_PMU_CHG_IRQ5 (0xD4)
	187	+#define MT6360_PMU_CHG_IRQ6 (0xD5)
	188	+#define MT6360_PMU_QC_IRQ (0xD6)
	189	+#define MT6360_PMU_FOD_IRQ (0xD7)
	190	+#define MT6360_PMU_BASE_IRQ (0xD8)
	191	+#define MT6360_PMU_FLED_IRQ1 (0xD9)
	192	+#define MT6360_PMU_FLED_IRQ2 (0xDA)
	193	+#define MT6360_PMU_RGB_IRQ (0xDB)
	194	+#define MT6360_PMU_BUCK1_IRQ (0xDC)
	195	+#define MT6360_PMU_BUCK2_IRQ (0xDD)
	196	+#define MT6360_PMU_LDO_IRQ1 (0xDE)
	197	+#define MT6360_PMU_LDO_IRQ2 (0xDF)
	198	+#define MT6360_PMU_CHG_STAT1 (0xE0)
	199	+#define MT6360_PMU_CHG_STAT2 (0xE1)
	200	+#define MT6360_PMU_CHG_STAT3 (0xE2)
	201	+#define MT6360_PMU_CHG_STAT4 (0xE3)
	202	+#define MT6360_PMU_CHG_STAT5 (0xE4)
	203	+#define MT6360_PMU_CHG_STAT6 (0xE5)
	204	+#define MT6360_PMU_QC_STAT (0xE6)
	205	+#define MT6360_PMU_FOD_STAT (0xE7)
	206	+#define MT6360_PMU_BASE_STAT (0xE8)
	207	+#define MT6360_PMU_FLED_STAT1 (0xE9)
	208	+#define MT6360_PMU_FLED_STAT2 (0xEA)
	209	+#define MT6360_PMU_RGB_STAT (0xEB)
	210	+#define MT6360_PMU_BUCK1_STAT (0xEC)
	211	+#define MT6360_PMU_BUCK2_STAT (0xED)
	212	+#define MT6360_PMU_LDO_STAT1 (0xEE)
	213	+#define MT6360_PMU_LDO_STAT2 (0xEF)
	214	+#define MT6360_PMU_CHG_MASK1 (0xF0)
	215	+#define MT6360_PMU_CHG_MASK2 (0xF1)
	216	+#define MT6360_PMU_CHG_MASK3 (0xF2)
	217	+#define MT6360_PMU_CHG_MASK4 (0xF3)
	218	+#define MT6360_PMU_CHG_MASK5 (0xF4)
	219	+#define MT6360_PMU_CHG_MASK6 (0xF5)
	220	+#define MT6360_PMU_QC_MASK (0xF6)
	221	+#define MT6360_PMU_FOD_MASK (0xF7)
	222	+#define MT6360_PMU_BASE_MASK (0xF8)
	223	+#define MT6360_PMU_FLED_MASK1 (0xF9)
	224	+#define MT6360_PMU_FLED_MASK2 (0xFA)
	225	+#define MT6360_PMU_FAULTB_MASK (0xFB)
	226	+#define MT6360_PMU_BUCK1_MASK (0xFC)
	227	+#define MT6360_PMU_BUCK2_MASK (0xFD)
	228	+#define MT6360_PMU_LDO_MASK1 (0xFE)
	229	+#define MT6360_PMU_LDO_MASK2 (0xFF)
	230	+#define MT6360_PMU_MAXREG (MT6360_PMU_LDO_MASK2)
	231	+
	232	+/* MT6360_PMU_IRQ_SET */
	233	+#define MT6360_PMU_IRQ_REGNUM (MT6360_PMU_LDO_IRQ2 - MT6360_PMU_CHG_IRQ1 + 1)
	234	+#define MT6360_IRQ_RETRIG BIT(2)
	235	+
	236	+#define CHIP_VEN_MASK (0xF0)
	237	+#define CHIP_VEN_MT6360 (0x50)
	238	+#define CHIP_REV_MASK (0x0F)
	239	+
	240	+#endif /* __MT6360_H__ */

include/linux/mfd/mt6397/core.h+5−0

@@ -8,9 +8,11 @@ · 7 unmodified lines
8	8	#define __MFD_MT6397_CORE_H__
9	9
10	10	#include <linux/mutex.h>
	11	+#include <linux/notifier.h>
11	12
12	13	enum chip_id {
13	14	MT6323_CHIP_ID = 0x23,
	15	+ MT6358_CHIP_ID = 0x58,
14	16	MT6391_CHIP_ID = 0x91,
15	17	MT6397_CHIP_ID = 0x97,
16	18	};
@@ -54,6 +56,7 @@ enum mt6397_irq_numbers { · 37 unmodified lines
54	56	struct mt6397_chip {
55	57	struct device *dev;
56	58	struct regmap *regmap;
	59	+ struct notifier_block pm_nb;
57	60	int irq;
58	61	struct irq_domain *irq_domain;
59	62	struct mutex irqlock;
@@ -63,8 +66,10 @@ struct mt6397_chip { · 3 unmodified lines
63	66	u16 int_con[2];
64	67	u16 int_status[2];
65	68	u16 chip_id;
	69	+ void *irq_data;
66	70	};
67	71
	72	+int mt6358_irq_init(struct mt6397_chip *chip);
68	73	int mt6397_irq_init(struct mt6397_chip *chip);
69	74
70	75	#endif /* __MFD_MT6397_CORE_H__ */

include/linux/mfd/mt6397/rtc.h+8−1

@@ -18,7 +18,9 @@ · 17 unmodified lines
18	18	#define RTC_BBPU_CBUSY BIT(6)
19	19	#define RTC_BBPU_KEY (0x43 << 8)
20	20
21		−#define RTC_WRTGR 0x003c
	21	+#define RTC_WRTGR_MT6358 0x003a
	22	+#define RTC_WRTGR_MT6397 0x003c
	23	+#define RTC_WRTGR_MT6323 RTC_WRTGR_MT6397
22	24
23	25	#define RTC_IRQ_STA 0x0002
24	26	#define RTC_IRQ_STA_AL BIT(0)
@@ -65,6 +67,10 @@ · 40 unmodified lines
65	67	#define MTK_RTC_POLL_DELAY_US 10
66	68	#define MTK_RTC_POLL_TIMEOUT (jiffies_to_usecs(HZ))
67	69
	70	+struct mtk_rtc_data {
	71	+ u32 wrtgr;
	72	+};
	73	+
68	74	struct mt6397_rtc {
69	75	struct device *dev;
70	76	struct rtc_device *rtc_dev;
@@ -74,6 +80,7 @@ struct mt6397_rtc { · 3 unmodified lines
74	80	struct regmap *regmap;
75	81	int irq;
76	82	u32 addr_base;
	83	+ const struct mtk_rtc_data *data;
77	84	};
78	85
79	86	#endif /* _LINUX_MFD_MT6397_RTC_H_ */

include/linux/mfd/stmfx.h+1−0

@@ -109,6 +109,7 @@ struct stmfx { · 108 unmodified lines
109	109	struct device *dev;
110	110	struct regmap *map;
111	111	struct regulator *vdd;
	112	+ int irq;
112	113	struct irq_domain *irq_domain;
113	114	struct mutex lock; /* IRQ bus lock */
114	115	u8 irq_src;

Merge tag 'mfd-next-5.8' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd

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