History

Merge tag 'mmc-v4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc

Pull MMC updates from Ulf Hansson: "It's been an busy period for mmc. Quite some changes in the mmc core, two new mmc host drivers, some existing drivers being extended to support new IP versions and lots of other updates. MMC core: - Delete eMMC packed command support - Introduce mmc_abort_tuning() to enable eMMC tuning to fail gracefully - Introduce mmc_can_retune() to see if a host can be retuned - Re-work and improve the sequence when sending a CMD6 for mmc - Enable CDM13 polling when switching to HS and HS DDR mode for mmc - Relax checking for CMD6 errors after switch to HS200 - Re-factoring the code dealing with the mmc block queue - Recognize whether the eMMC card supports CMDQ - Fix 4K native sector check - Don't power off the card when starting the host - Increase MMC_IOC_MAX_BYTES to support bigger firmware binaries - Improve error handling and drop meaningless BUG_ONs() - Lots of clean-ups and changes to improve the quality of the code MMC host: - sdhci: Fix tuning sequence and clean-up the related code - sdhci: Add support to via DT override broken SDHCI cap register bits - sdhci-cadence: Add new driver for Cadence SD4HC SDHCI variant - sdhci-msm: Update clock management - sdhci-msm: Add support for eMMC HS400 mode - sdhci-msm: Deploy runtime/system PM support - sdhci-iproc: Extend driver support to newer IP versions - sdhci-pci: Add support for Intel GLK - sdhci-pci: Add support for Intel NI byt sdio - sdhci-acpi: Add support for 80860F14 UID 2 SDIO bus - sdhci: Lots of various small improvements and clean-ups - tmio: Add support for tuning - sh_mobile_sdhi: Add support for tuning - sh_mobile_sdhi: Extend driver to support SDHI IP on R7S72100 SoC - sh_mobile_sdhi: remove support for sh7372 - davinci: Use mmc_of_parse() to enable generic mmc DT bindings - meson: Add new driver to support GX platforms - dw_mmc: Deploy generic runtime/system PM support - dw_mmc: Lots of various small improvements As a part of the mmc changes this time, I have also pulled in an immutable branch/tag (soc-device-match-tag1) hosted by Geert Uytterhoeven, to share the implementation of the new soc_device_match() interface. This is needed by these mmc related changes: - mmc: sdhci-of-esdhc: Get correct IP version for T4240-R1.0-R2.0 - soc: fsl: add GUTS driver for QorIQ platforms" * tag 'mmc-v4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc: (136 commits) mmc: sdhci-cadence: add Cadence SD4HC support mmc: sdhci: export sdhci_execute_tuning() mmc: sdhci: Tidy tuning loop mmc: sdhci: Simplify tuning block size logic mmc: sdhci: Factor out tuning helper functions mmc: sdhci: Use mmc_abort_tuning() mmc: mmc: Introduce mmc_abort_tuning() mmc: sdhci: Always allow tuning to fall back to fixed sampling mmc: sdhci: Fix tuning reset after exhausting the maximum number of loops mmc: sdhci: Fix recovery from tuning timeout Revert "mmc: sdhci: Reset cmd and data circuits after tuning failure" mmc: mmc: Relax checking for switch errors after HS200 switch mmc: sdhci-acpi: support 80860F14 UID 2 SDIO bus mmc: sdhci-of-at91: remove bogus MMC_SDHCI_IO_ACCESSORS select mmc: sdhci-pci: Use ACPI to get max frequency for Intel NI byt sdio mmc: sdhci-pci: Add PCI ID for Intel NI byt sdio mmc: sdhci-s3c: add spin_unlock_irq() before calling clk_round_rate mmc: dw_mmc: display the clock message only one time when card is polling mmc: dw_mmc: add the debug message for polling and non-removable mmc: dw_mmc: check the "present" variable before checking flags ...

Linus Torvalds committed 9 years ago

Commit 5233c332 parents 58f253d ff6af2879 files · +4092 −1574Browse files

Unified · Split

79 files
  1. Documentation/devicetree/bindings/mmc/amlogic,meson-gx.txt +32 −0
  2. Documentation/devicetree/bindings/mmc/brcm,sdhci-iproc.txt +9 −0
  3. Documentation/devicetree/bindings/mmc/renesas,mmcif.txt +3 −0
  4. Documentation/devicetree/bindings/mmc/sdhci-cadence.txt +30 −0
  5. Documentation/devicetree/bindings/mmc/sdhci-msm.txt +1 −0
  6. Documentation/devicetree/bindings/mmc/sdhci.txt +13 −0
  7. Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt +2 −6
  8. Documentation/devicetree/bindings/mmc/tmio_mmc.txt +1 −1
  9. Documentation/devicetree/bindings/soc/fsl/guts.txt +3 −0
  10. MAINTAINERS +11 −1
  11. arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +6 −0
  12. drivers/base/Kconfig +1 −0
  13. drivers/base/soc.c +79 −0
  14. drivers/mmc/card/block.c +45 −454
  15. drivers/mmc/card/mmc_test.c +43 −15
  16. drivers/mmc/card/queue.c +123 −189
  17. drivers/mmc/card/queue.h +5 −24
  18. drivers/mmc/card/sdio_uart.c +0 −2
  19. drivers/mmc/core/core.c +36 −61
  20. drivers/mmc/core/debugfs.c +5 −1
  21. drivers/mmc/core/mmc.c +58 −55
  22. drivers/mmc/core/mmc_ops.c +131 −89
  23. drivers/mmc/core/mmc_ops.h +4 −3
  24. drivers/mmc/core/sd.c +0 −14
  25. drivers/mmc/core/sd_ops.c +4 −23
  26. drivers/mmc/core/sdio.c +2 −15
  27. drivers/mmc/core/sdio_cis.c +2 −1
  28. drivers/mmc/core/sdio_irq.c +7 −5
  29. drivers/mmc/core/slot-gpio.c +8 −0
  30. drivers/mmc/host/Kconfig +22 −1
  31. drivers/mmc/host/Makefile +2 −0
  32. drivers/mmc/host/davinci_mmc.c +66 −64
  33. drivers/mmc/host/dw_mmc-exynos.c +36 −16
  34. drivers/mmc/host/dw_mmc-k3.c +9 −30
  35. drivers/mmc/host/dw_mmc-pci.c +9 −20
  36. drivers/mmc/host/dw_mmc-pltfm.c +8 −20
  37. drivers/mmc/host/dw_mmc-rockchip.c +39 −3
  38. drivers/mmc/host/dw_mmc.c +115 −66
  39. drivers/mmc/host/dw_mmc.h +4 −3
  40. drivers/mmc/host/jz4740_mmc.c +1 −2
  41. drivers/mmc/host/meson-gx-mmc.c +851 −0
  42. drivers/mmc/host/mmci.c +91 −37
  43. drivers/mmc/host/mmci.h +39 −32
  44. drivers/mmc/host/mtk-sd.c +2 −2
  45. drivers/mmc/host/omap_hsmmc.c +1 −2
  46. drivers/mmc/host/rtsx_pci_sdmmc.c +1 −2
  47. drivers/mmc/host/rtsx_usb_sdmmc.c +3 −0
  48. drivers/mmc/host/s3cmci.c +4 −11
  49. drivers/mmc/host/sdhci-acpi.c +1 −0
  50. drivers/mmc/host/sdhci-cadence.c +283 −0
  51. drivers/mmc/host/sdhci-iproc.c +33 −2
  52. drivers/mmc/host/sdhci-msm.c +651 −43
  53. drivers/mmc/host/sdhci-of-at91.c +1 −0
  54. drivers/mmc/host/sdhci-of-esdhc.c +20 −0
  55. drivers/mmc/host/sdhci-pci-core.c +92 −6
  56. drivers/mmc/host/sdhci-pci.h +3 −0
  57. drivers/mmc/host/sdhci-pltfm.h +1 −1
  58. drivers/mmc/host/sdhci-s3c.c +2 −0
  59. drivers/mmc/host/sdhci.c +204 −158
  60. drivers/mmc/host/sdhci.h +3 −1
  61. drivers/mmc/host/sh_mobile_sdhi.c +273 −1
  62. drivers/mmc/host/sunxi-mmc.c +10 −5
  63. drivers/mmc/host/tmio_mmc.h +31 −1
  64. drivers/mmc/host/tmio_mmc_pio.c +111 −8
  65. drivers/mmc/host/wbsd.c +7 −4
  66. drivers/soc/Kconfig +1 −2
  67. drivers/soc/fsl/Kconfig +18 −0
  68. drivers/soc/fsl/Makefile +1 −0
  69. drivers/soc/fsl/guts.c +239 −0
  70. include/linux/fsl/guts.h +77 −48
  71. include/linux/mfd/tmio.h +5 −0
  72. include/linux/mmc/card.h +2 −12
  73. include/linux/mmc/core.h +15 −1
  74. include/linux/mmc/dw_mmc.h +6 −0
  75. include/linux/mmc/host.h +7 −10
  76. include/linux/mmc/mmc.h +17 −0
  77. include/linux/mmc/slot-gpio.h +1 −0
  78. include/linux/sys_soc.h +9 −0
  79. include/uapi/linux/mmc/ioctl.h +1 −1
Documentation/devicetree/bindings/mmc/amlogic,meson-gx.txt+32−0
@@ -0,0 +1,32 @@
1+Amlogic SD / eMMC controller for S905/GXBB family SoCs
2+
3+The MMC 5.1 compliant host controller on Amlogic provides the
4+interface for SD, eMMC and SDIO devices.
5+
6+This file documents the properties in addition to those available in
7+the MMC core bindings, documented by mmc.txt.
8+
9+Required properties:
10+- compatible : contains one of:
11+ - "amlogic,meson-gx-mmc"
12+ - "amlogic,meson-gxbb-mmc"
13+ - "amlogic,meson-gxl-mmc"
14+ - "amlogic,meson-gxm-mmc"
15+- clocks : A list of phandle + clock-specifier pairs for the clocks listed in clock-names.
16+- clock-names: Should contain the following:
17+ "core" - Main peripheral bus clock
18+ "clkin0" - Parent clock of internal mux
19+ "clkin1" - Other parent clock of internal mux
20+ The driver has an interal mux clock which switches between clkin0 and clkin1 depending on the
21+ clock rate requested by the MMC core.
22+
23+Example:
24+
25+ sd_emmc_a: mmc@70000 {
26+ compatible = "amlogic,meson-gxbb-mmc";
27+ reg = <0x0 0x70000 0x0 0x2000>;
28+ interrupts = < GIC_SPI 216 IRQ_TYPE_EDGE_RISING>;
29+ clocks = <&clkc CLKID_SD_EMMC_A>, <&xtal>, <&clkc CLKID_FCLK_DIV2>;
30+ clock-names = "core", "clkin0", "clkin1";
31+ pinctrl-0 = <&emmc_pins>;
32+ };
Documentation/devicetree/bindings/mmc/brcm,sdhci-iproc.txt+9−0
@@ -7,6 +7,15 @@ Required properties: · 6 unmodified lines
77 - compatible : Should be one of the following
88 "brcm,bcm2835-sdhci"
99 "brcm,sdhci-iproc-cygnus"
10+ "brcm,sdhci-iproc"
11+
12+Use brcm2835-sdhci for Rasperry PI.
13+
14+Use sdhci-iproc-cygnus for Broadcom SDHCI Controllers
15+restricted to 32bit host accesses to SDHCI registers.
16+
17+Use sdhci-iproc for Broadcom SDHCI Controllers that allow standard
18+8, 16, 32-bit host access to SDHCI register.
1019
1120 - clocks : The clock feeding the SDHCI controller.
1221
Documentation/devicetree/bindings/mmc/renesas,mmcif.txt+3−0
@@ -8,11 +8,14 @@ Required properties: · 7 unmodified lines
88
99 - compatible: should be "renesas,mmcif-<soctype>", "renesas,sh-mmcif" as a
1010 fallback. Examples with <soctype> are:
11+ - "renesas,mmcif-r8a73a4" for the MMCIF found in r8a73a4 SoCs
1112 - "renesas,mmcif-r8a7740" for the MMCIF found in r8a7740 SoCs
13+ - "renesas,mmcif-r8a7778" for the MMCIF found in r8a7778 SoCs
1214 - "renesas,mmcif-r8a7790" for the MMCIF found in r8a7790 SoCs
1315 - "renesas,mmcif-r8a7791" for the MMCIF found in r8a7791 SoCs
1416 - "renesas,mmcif-r8a7793" for the MMCIF found in r8a7793 SoCs
1517 - "renesas,mmcif-r8a7794" for the MMCIF found in r8a7794 SoCs
18+ - "renesas,mmcif-sh73a0" for the MMCIF found in sh73a0 SoCs
1619
1720 - clocks: reference to the functional clock
1821
Documentation/devicetree/bindings/mmc/sdhci-cadence.txt+30−0
@@ -0,0 +1,30 @@
1+* Cadence SD/SDIO/eMMC Host Controller
2+
3+Required properties:
4+- compatible: should be "cdns,sd4hc".
5+- reg: offset and length of the register set for the device.
6+- interrupts: a single interrupt specifier.
7+- clocks: phandle to the input clock.
8+
9+Optional properties:
10+For eMMC configuration, supported speed modes are not indicated by the SDHCI
11+Capabilities Register. Instead, the following properties should be specified
12+if supported. See mmc.txt for details.
13+- mmc-ddr-1_8v
14+- mmc-ddr-1_2v
15+- mmc-hs200-1_8v
16+- mmc-hs200-1_2v
17+- mmc-hs400-1_8v
18+- mmc-hs400-1_2v
19+
20+Example:
21+ emmc: sdhci@5a000000 {
22+ compatible = "cdns,sd4hc";
23+ reg = <0x5a000000 0x400>;
24+ interrupts = <0 78 4>;
25+ clocks = <&clk 4>;
26+ bus-width = <8>;
27+ mmc-ddr-1_8v;
28+ mmc-hs200-1_8v;
29+ mmc-hs400-1_8v;
30+ };
Documentation/devicetree/bindings/mmc/sdhci-msm.txt+1−0
@@ -17,6 +17,7 @@ Required properties: · 16 unmodified lines
1717 "iface" - Main peripheral bus clock (PCLK/HCLK - AHB Bus clock) (required)
1818 "core" - SDC MMC clock (MCLK) (required)
1919 "bus" - SDCC bus voter clock (optional)
20+ "xo" - TCXO clock (optional)
2021
2122 Example:
2223
Documentation/devicetree/bindings/mmc/sdhci.txt+13−0
@@ -0,0 +1,13 @@
1+The properties specific for SD host controllers. For properties shared by MMC
2+host controllers refer to the mmc[1] bindings.
3+
4+ [1] Documentation/devicetree/bindings/mmc/mmc.txt
5+
6+Optional properties:
7+- sdhci-caps-mask: The sdhci capabilities register is incorrect. This 64bit
8+ property corresponds to the bits in the sdhci capabilty register. If the bit
9+ is on in the mask then the bit is incorrect in the register and should be
10+ turned off, before applying sdhci-caps.
11+- sdhci-caps: The sdhci capabilities register is incorrect. This 64bit
12+ property corresponds to the bits in the sdhci capability register. If the
13+ bit is on in the property then the bit should be turned on.
Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt+2−6
@@ -59,8 +59,9 @@ Optional properties: · 58 unmodified lines
5959 is specified and the ciu clock is specified then we'll try to set the ciu
6060 clock to this at probe time.
6161
62−* clock-freq-min-max: Minimum and Maximum clock frequency for card output
62+* clock-freq-min-max (DEPRECATED): Minimum and Maximum clock frequency for card output
6363 clock(cclk_out). If it's not specified, max is 200MHZ and min is 400KHz by default.
64+ (Use the "max-frequency" instead of "clock-freq-min-max".)
6465
6566 * num-slots: specifies the number of slots supported by the controller.
6667 The number of physical slots actually used could be equal or less than the
@@ -74,11 +75,6 @@ Optional properties: · 7 unmodified lines
7475 * card-detect-delay: Delay in milli-seconds before detecting card after card
7576 insert event. The default value is 0.
7677
77−* supports-highspeed (DEPRECATED): Enables support for high speed cards (up to 50MHz)
78− (use "cap-mmc-highspeed" or "cap-sd-highspeed" instead)
79−
80−* broken-cd: as documented in mmc core bindings.
81−
8278 * vmmc-supply: The phandle to the regulator to use for vmmc. If this is
8379 specified we'll defer probe until we can find this regulator.
8480
Documentation/devicetree/bindings/mmc/tmio_mmc.txt+1−1
@@ -11,8 +11,8 @@ optional bindings can be used. · 10 unmodified lines
1111
1212 Required properties:
1313 - compatible: "renesas,sdhi-shmobile" - a generic sh-mobile SDHI unit
14− "renesas,sdhi-sh7372" - SDHI IP on SH7372 SoC
1514 "renesas,sdhi-sh73a0" - SDHI IP on SH73A0 SoC
15+ "renesas,sdhi-r7s72100" - SDHI IP on R7S72100 SoC
1616 "renesas,sdhi-r8a73a4" - SDHI IP on R8A73A4 SoC
1717 "renesas,sdhi-r8a7740" - SDHI IP on R8A7740 SoC
1818 "renesas,sdhi-r8a7778" - SDHI IP on R8A7778 SoC
Documentation/devicetree/bindings/soc/fsl/guts.txtrenamed from Documentation/devicetree/bindings/powerpc/fsl/guts.txt+3−0
@@ -25,6 +25,9 @@ Recommended properties: · 24 unmodified lines
2525 - fsl,liodn-bits : Indicates the number of defined bits in the LIODN
2626 registers, for those SOCs that have a PAMU device.
2727
28+ - little-endian : Indicates that the global utilities block is little
29+ endian. The default is big endian.
30+
2831 Examples:
2932 global-utilities@e0000 { /* global utilities block */
3033 compatible = "fsl,mpc8548-guts";
MAINTAINERS+11−1
@@ -1052,6 +1052,7 @@ F: arch/arm/mach-meson/ · 1051 unmodified lines
10521052 F: arch/arm/boot/dts/meson*
10531053 F: arch/arm64/boot/dts/amlogic/
10541054 F: drivers/pinctrl/meson/
1055+F: drivers/mmc/host/meson*
10551056 N: meson
10561057
10571058 ARM/Annapurna Labs ALPINE ARCHITECTURE
@@ -5068,9 +5069,18 @@ S: Maintained · 4010 unmodified lines
50685069 F: drivers/net/ethernet/freescale/fman
50695070 F: Documentation/devicetree/bindings/powerpc/fsl/fman.txt
50705071
5072+FREESCALE SOC DRIVERS
5073+M: Scott Wood <oss@buserror.net>
5074+L: linuxppc-dev@lists.ozlabs.org
5075+L: linux-arm-kernel@lists.infradead.org
5076+S: Maintained
5077+F: drivers/soc/fsl/
5078+F: include/linux/fsl/
5079+
50715080 FREESCALE QUICC ENGINE LIBRARY
5081+M: Qiang Zhao <qiang.zhao@nxp.com>
50725082 L: linuxppc-dev@lists.ozlabs.org
5073−S: Orphan
5083+S: Maintained
50745084 F: drivers/soc/fsl/qe/
50755085 F: include/soc/fsl/*qe*.h
50765086 F: include/soc/fsl/*ucc*.h
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi+6−0
@@ -216,6 +216,12 @@ · 215 unmodified lines
216216 clocks = <&sysclk>;
217217 };
218218
219+ dcfg: dcfg@1e00000 {
220+ compatible = "fsl,ls2080a-dcfg", "syscon";
221+ reg = <0x0 0x1e00000 0x0 0x10000>;
222+ little-endian;
223+ };
224+
219225 serial0: serial@21c0500 {
220226 compatible = "fsl,ns16550", "ns16550a";
221227 reg = <0x0 0x21c0500 0x0 0x100>;
drivers/base/Kconfig+1−0
@@ -237,6 +237,7 @@ config GENERIC_CPU_AUTOPROBE · 236 unmodified lines
237237
238238 config SOC_BUS
239239 bool
240+ select GLOB
240241
241242 source "drivers/base/regmap/Kconfig"
242243
drivers/base/soc.c+79−0
@@ -13,6 +13,7 @@ · 12 unmodified lines
1313 #include <linux/spinlock.h>
1414 #include <linux/sys_soc.h>
1515 #include <linux/err.h>
16+#include <linux/glob.h>
1617
1718 static DEFINE_IDA(soc_ida);
1819
@@ -113,6 +114,12 @@ struct soc_device *soc_device_register(struct soc_device_attribute *soc_dev_attr · 94 unmodified lines
113114 struct soc_device *soc_dev;
114115 int ret;
115116
117+ if (!soc_bus_type.p) {
118+ ret = bus_register(&soc_bus_type);
119+ if (ret)
120+ goto out1;
121+ }
122+
116123 soc_dev = kzalloc(sizeof(*soc_dev), GFP_KERNEL);
117124 if (!soc_dev) {
118125 ret = -ENOMEM;
@@ -156,6 +163,78 @@ void soc_device_unregister(struct soc_device *soc_dev) · 37 unmodified lines
156163
157164 static int __init soc_bus_register(void)
158165 {
166+ if (soc_bus_type.p)
167+ return 0;
168+
159169 return bus_register(&soc_bus_type);
160170 }
161171 core_initcall(soc_bus_register);
172+
173+static int soc_device_match_one(struct device *dev, void *arg)
174+{
175+ struct soc_device *soc_dev = container_of(dev, struct soc_device, dev);
176+ const struct soc_device_attribute *match = arg;
177+
178+ if (match->machine &&
179+ (!soc_dev->attr->machine ||
180+ !glob_match(match->machine, soc_dev->attr->machine)))
181+ return 0;
182+
183+ if (match->family &&
184+ (!soc_dev->attr->family ||
185+ !glob_match(match->family, soc_dev->attr->family)))
186+ return 0;
187+
188+ if (match->revision &&
189+ (!soc_dev->attr->revision ||
190+ !glob_match(match->revision, soc_dev->attr->revision)))
191+ return 0;
192+
193+ if (match->soc_id &&
194+ (!soc_dev->attr->soc_id ||
195+ !glob_match(match->soc_id, soc_dev->attr->soc_id)))
196+ return 0;
197+
198+ return 1;
199+}
200+
201+/*
202+ * soc_device_match - identify the SoC in the machine
203+ * @matches: zero-terminated array of possible matches
204+ *
205+ * returns the first matching entry of the argument array, or NULL
206+ * if none of them match.
207+ *
208+ * This function is meant as a helper in place of of_match_node()
209+ * in cases where either no device tree is available or the information
210+ * in a device node is insufficient to identify a particular variant
211+ * by its compatible strings or other properties. For new devices,
212+ * the DT binding should always provide unique compatible strings
213+ * that allow the use of of_match_node() instead.
214+ *
215+ * The calling function can use the .data entry of the
216+ * soc_device_attribute to pass a structure or function pointer for
217+ * each entry.
218+ */
219+const struct soc_device_attribute *soc_device_match(
220+ const struct soc_device_attribute *matches)
221+{
222+ int ret = 0;
223+
224+ if (!matches)
225+ return NULL;
226+
227+ while (!ret) {
228+ if (!(matches->machine || matches->family ||
229+ matches->revision || matches->soc_id))
230+ break;
231+ ret = bus_for_each_dev(&soc_bus_type, NULL, (void *)matches,
232+ soc_device_match_one);
233+ if (!ret)
234+ matches++;
235+ else
236+ return matches;
237+ }
238+ return NULL;
239+}
240+EXPORT_SYMBOL_GPL(soc_device_match);
drivers/mmc/card/block.c+45−454
@@ -66,9 +66,6 @@ MODULE_ALIAS("mmc:block"); · 65 unmodified lines
6666
6767 #define mmc_req_rel_wr(req) ((req->cmd_flags & REQ_FUA) && \
6868 (rq_data_dir(req) == WRITE))
69−#define PACKED_CMD_VER 0x01
70−#define PACKED_CMD_WR 0x02
71−
7269 static DEFINE_MUTEX(block_mutex);
7370
7471 /*
@@ -102,7 +99,6 @@ struct mmc_blk_data { · 27 unmodified lines
10299 unsigned int flags;
103100 #define MMC_BLK_CMD23 (1 << 0) /* Can do SET_BLOCK_COUNT for multiblock */
104101 #define MMC_BLK_REL_WR (1 << 1) /* MMC Reliable write support */
105−#define MMC_BLK_PACKED_CMD (1 << 2) /* MMC packed command support */
106102
107103 unsigned int usage;
108104 unsigned int read_only;
@@ -126,12 +122,6 @@ struct mmc_blk_data { · 17 unmodified lines
126122
127123 static DEFINE_MUTEX(open_lock);
128124
129−enum {
130− MMC_PACKED_NR_IDX = -1,
131− MMC_PACKED_NR_ZERO,
132− MMC_PACKED_NR_SINGLE,
133−};
134−
135125 module_param(perdev_minors, int, 0444);
136126 MODULE_PARM_DESC(perdev_minors, "Minors numbers to allocate per device");
137127
@@ -139,17 +129,6 @@ static inline int mmc_blk_part_switch(struct mmc_card *card, · 1 unmodified line
139129 struct mmc_blk_data *md);
140130 static int get_card_status(struct mmc_card *card, u32 *status, int retries);
141131
142−static inline void mmc_blk_clear_packed(struct mmc_queue_req *mqrq)
143−{
144− struct mmc_packed *packed = mqrq->packed;
145−
146− mqrq->cmd_type = MMC_PACKED_NONE;
147− packed->nr_entries = MMC_PACKED_NR_ZERO;
148− packed->idx_failure = MMC_PACKED_NR_IDX;
149− packed->retries = 0;
150− packed->blocks = 0;
151−}
152−
153132 static struct mmc_blk_data *mmc_blk_get(struct gendisk *disk)
154133 {
155134 struct mmc_blk_data *md;
@@ -854,7 +833,7 @@ static int get_card_status(struct mmc_card *card, u32 *status, int retries) · 698 unmodified lines
854833 }
855834
856835 static int card_busy_detect(struct mmc_card *card, unsigned int timeout_ms,
857− bool hw_busy_detect, struct request *req, int *gen_err)
836+ bool hw_busy_detect, struct request *req, bool *gen_err)
858837 {
859838 unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms);
860839 int err = 0;
@@ -871,7 +850,7 @@ static int card_busy_detect(struct mmc_card *card, unsigned int timeout_ms, · 10 unmodified lines
871850 if (status & R1_ERROR) {
872851 pr_err("%s: %s: error sending status cmd, status %#x\n",
873852 req->rq_disk->disk_name, __func__, status);
874− *gen_err = 1;
853+ *gen_err = true;
875854 }
876855
877856 /* We may rely on the host hw to handle busy detection.*/
@@ -902,7 +881,7 @@ static int card_busy_detect(struct mmc_card *card, unsigned int timeout_ms, · 24 unmodified lines
902881 }
903882
904883 static int send_stop(struct mmc_card *card, unsigned int timeout_ms,
905− struct request *req, int *gen_err, u32 *stop_status)
884+ struct request *req, bool *gen_err, u32 *stop_status)
906885 {
907886 struct mmc_host *host = card->host;
908887 struct mmc_command cmd = {0};
@@ -940,7 +919,7 @@ static int send_stop(struct mmc_card *card, unsigned int timeout_ms, · 31 unmodified lines
940919 (*stop_status & R1_ERROR)) {
941920 pr_err("%s: %s: general error sending stop command, resp %#x\n",
942921 req->rq_disk->disk_name, __func__, *stop_status);
943− *gen_err = 1;
922+ *gen_err = true;
944923 }
945924
946925 return card_busy_detect(card, timeout_ms, use_r1b_resp, req, gen_err);
@@ -1014,7 +993,7 @@ static int mmc_blk_cmd_error(struct request *req, const char *name, int error, · 67 unmodified lines
1014993 * Otherwise we don't understand what happened, so abort.
1015994 */
1016995 static int mmc_blk_cmd_recovery(struct mmc_card *card, struct request *req,
1017− struct mmc_blk_request *brq, int *ecc_err, int *gen_err)
996+ struct mmc_blk_request *brq, bool *ecc_err, bool *gen_err)
1018997 {
1019998 bool prev_cmd_status_valid = true;
1020999 u32 status, stop_status = 0;
@@ -1053,7 +1032,7 @@ static int mmc_blk_cmd_recovery(struct mmc_card *card, struct request *req, · 32 unmodified lines
10531032 if ((status & R1_CARD_ECC_FAILED) ||
10541033 (brq->stop.resp[0] & R1_CARD_ECC_FAILED) ||
10551034 (brq->cmd.resp[0] & R1_CARD_ECC_FAILED))
1056− *ecc_err = 1;
1035+ *ecc_err = true;
10571036
10581037 /* Flag General errors */
10591038 if (!mmc_host_is_spi(card->host) && rq_data_dir(req) != READ)
@@ -1062,7 +1041,7 @@ static int mmc_blk_cmd_recovery(struct mmc_card *card, struct request *req, · 2 unmodified lines
10621041 pr_err("%s: %s: general error sending stop or status command, stop cmd response %#x, card status %#x\n",
10631042 req->rq_disk->disk_name, __func__,
10641043 brq->stop.resp[0], status);
1065− *gen_err = 1;
1044+ *gen_err = true;
10661045 }
10671046
10681047 /*
@@ -1085,7 +1064,7 @@ static int mmc_blk_cmd_recovery(struct mmc_card *card, struct request *req, · 16 unmodified lines
10851064 }
10861065
10871066 if (stop_status & R1_CARD_ECC_FAILED)
1088− *ecc_err = 1;
1067+ *ecc_err = true;
10891068 }
10901069
10911070 /* Check for set block count errors */
@@ -1154,7 +1133,7 @@ static inline void mmc_blk_reset_success(struct mmc_blk_data *md, int type) · 62 unmodified lines
11541133
11551134 int mmc_access_rpmb(struct mmc_queue *mq)
11561135 {
1157− struct mmc_blk_data *md = mq->data;
1136+ struct mmc_blk_data *md = mq->blkdata;
11581137 /*
11591138 * If this is a RPMB partition access, return ture
11601139 */
@@ -1166,7 +1145,7 @@ int mmc_access_rpmb(struct mmc_queue *mq) · 5 unmodified lines
11661145
11671146 static int mmc_blk_issue_discard_rq(struct mmc_queue *mq, struct request *req)
11681147 {
1169− struct mmc_blk_data *md = mq->data;
1148+ struct mmc_blk_data *md = mq->blkdata;
11701149 struct mmc_card *card = md->queue.card;
11711150 unsigned int from, nr, arg;
11721151 int err = 0, type = MMC_BLK_DISCARD;
@@ -1210,7 +1189,7 @@ out: · 37 unmodified lines
12101189 static int mmc_blk_issue_secdiscard_rq(struct mmc_queue *mq,
12111190 struct request *req)
12121191 {
1213− struct mmc_blk_data *md = mq->data;
1192+ struct mmc_blk_data *md = mq->blkdata;
12141193 struct mmc_card *card = md->queue.card;
12151194 unsigned int from, nr, arg;
12161195 int err = 0, type = MMC_BLK_SECDISCARD;
@@ -1276,7 +1255,7 @@ out: · 59 unmodified lines
12761255
12771256 static int mmc_blk_issue_flush(struct mmc_queue *mq, struct request *req)
12781257 {
1279− struct mmc_blk_data *md = mq->data;
1258+ struct mmc_blk_data *md = mq->blkdata;
12801259 struct mmc_card *card = md->queue.card;
12811260 int ret = 0;
12821261
@@ -1320,15 +1299,16 @@ static inline void mmc_apply_rel_rw(struct mmc_blk_request *brq, · 37 unmodified lines
13201299 R1_CC_ERROR | /* Card controller error */ \
13211300 R1_ERROR) /* General/unknown error */
13221301
1323−static int mmc_blk_err_check(struct mmc_card *card,
1324− struct mmc_async_req *areq)
1302+static enum mmc_blk_status mmc_blk_err_check(struct mmc_card *card,
1303+ struct mmc_async_req *areq)
13251304 {
13261305 struct mmc_queue_req *mq_mrq = container_of(areq, struct mmc_queue_req,
13271306 mmc_active);
13281307 struct mmc_blk_request *brq = &mq_mrq->brq;
13291308 struct request *req = mq_mrq->req;
13301309 int need_retune = card->host->need_retune;
1331− int ecc_err = 0, gen_err = 0;
1310+ bool ecc_err = false;
1311+ bool gen_err = false;
13321312
13331313 /*
13341314 * sbc.error indicates a problem with the set block count
@@ -1378,7 +1358,7 @@ static int mmc_blk_err_check(struct mmc_card *card, · 43 unmodified lines
13781358 pr_err("%s: %s: general error sending stop command, stop cmd response %#x\n",
13791359 req->rq_disk->disk_name, __func__,
13801360 brq->stop.resp[0]);
1381− gen_err = 1;
1361+ gen_err = true;
13821362 }
13831363
13841364 err = card_busy_detect(card, MMC_BLK_TIMEOUT_MS, false, req,
@@ -1419,67 +1399,12 @@ static int mmc_blk_err_check(struct mmc_card *card, · 34 unmodified lines
14191399 if (!brq->data.bytes_xfered)
14201400 return MMC_BLK_RETRY;
14211401
1422− if (mmc_packed_cmd(mq_mrq->cmd_type)) {
1423− if (unlikely(brq->data.blocks << 9 != brq->data.bytes_xfered))
1424− return MMC_BLK_PARTIAL;
1425− else
1426− return MMC_BLK_SUCCESS;
1427− }
1428−
14291402 if (blk_rq_bytes(req) != brq->data.bytes_xfered)
14301403 return MMC_BLK_PARTIAL;
14311404
14321405 return MMC_BLK_SUCCESS;
14331406 }
14341407
1435−static int mmc_blk_packed_err_check(struct mmc_card *card,
1436− struct mmc_async_req *areq)
1437−{
1438− struct mmc_queue_req *mq_rq = container_of(areq, struct mmc_queue_req,
1439− mmc_active);
1440− struct request *req = mq_rq->req;
1441− struct mmc_packed *packed = mq_rq->packed;
1442− int err, check, status;
1443− u8 *ext_csd;
1444−
1445− packed->retries--;
1446− check = mmc_blk_err_check(card, areq);
1447− err = get_card_status(card, &status, 0);
1448− if (err) {
1449− pr_err("%s: error %d sending status command\n",
1450− req->rq_disk->disk_name, err);
1451− return MMC_BLK_ABORT;
1452− }
1453−
1454− if (status & R1_EXCEPTION_EVENT) {
1455− err = mmc_get_ext_csd(card, &ext_csd);
1456− if (err) {
1457− pr_err("%s: error %d sending ext_csd\n",
1458− req->rq_disk->disk_name, err);
1459− return MMC_BLK_ABORT;
1460− }
1461−
1462− if ((ext_csd[EXT_CSD_EXP_EVENTS_STATUS] &
1463− EXT_CSD_PACKED_FAILURE) &&
1464− (ext_csd[EXT_CSD_PACKED_CMD_STATUS] &
1465− EXT_CSD_PACKED_GENERIC_ERROR)) {
1466− if (ext_csd[EXT_CSD_PACKED_CMD_STATUS] &
1467− EXT_CSD_PACKED_INDEXED_ERROR) {
1468− packed->idx_failure =
1469− ext_csd[EXT_CSD_PACKED_FAILURE_INDEX] - 1;
1470− check = MMC_BLK_PARTIAL;
1471− }
1472− pr_err("%s: packed cmd failed, nr %u, sectors %u, "
1473− "failure index: %d\n",
1474− req->rq_disk->disk_name, packed->nr_entries,
1475− packed->blocks, packed->idx_failure);
1476− }
1477− kfree(ext_csd);
1478− }
1479−
1480− return check;
1481−}
1482−
14831408 static void mmc_blk_rw_rq_prep(struct mmc_queue_req *mqrq,
14841409 struct mmc_card *card,
14851410 int disable_multi,
@@ -1488,7 +1413,7 @@ static void mmc_blk_rw_rq_prep(struct mmc_queue_req *mqrq, · 2 unmodified lines
14881413 u32 readcmd, writecmd;
14891414 struct mmc_blk_request *brq = &mqrq->brq;
14901415 struct request *req = mqrq->req;
1491− struct mmc_blk_data *md = mq->data;
1416+ struct mmc_blk_data *md = mq->blkdata;
14921417 bool do_data_tag;
14931418
14941419 /*
@@ -1640,224 +1565,6 @@ static void mmc_blk_rw_rq_prep(struct mmc_queue_req *mqrq, · 145 unmodified lines
16401565 mmc_queue_bounce_pre(mqrq);
16411566 }
16421567
1643−static inline u8 mmc_calc_packed_hdr_segs(struct request_queue *q,
1644− struct mmc_card *card)
1645−{
1646− unsigned int hdr_sz = mmc_large_sector(card) ? 4096 : 512;
1647− unsigned int max_seg_sz = queue_max_segment_size(q);
1648− unsigned int len, nr_segs = 0;
1649−
1650− do {
1651− len = min(hdr_sz, max_seg_sz);
1652− hdr_sz -= len;
1653− nr_segs++;
1654− } while (hdr_sz);
1655−
1656− return nr_segs;
1657−}
1658−
1659−static u8 mmc_blk_prep_packed_list(struct mmc_queue *mq, struct request *req)
1660−{
1661− struct request_queue *q = mq->queue;
1662− struct mmc_card *card = mq->card;
1663− struct request *cur = req, *next = NULL;
1664− struct mmc_blk_data *md = mq->data;
1665− struct mmc_queue_req *mqrq = mq->mqrq_cur;
1666− bool en_rel_wr = card->ext_csd.rel_param & EXT_CSD_WR_REL_PARAM_EN;
1667− unsigned int req_sectors = 0, phys_segments = 0;
1668− unsigned int max_blk_count, max_phys_segs;
1669− bool put_back = true;
1670− u8 max_packed_rw = 0;
1671− u8 reqs = 0;
1672−
1673− /*
1674− * We don't need to check packed for any further
1675− * operation of packed stuff as we set MMC_PACKED_NONE
1676− * and return zero for reqs if geting null packed. Also
1677− * we clean the flag of MMC_BLK_PACKED_CMD to avoid doing
1678− * it again when removing blk req.
1679− */
1680− if (!mqrq->packed) {
1681− md->flags &= (~MMC_BLK_PACKED_CMD);
1682− goto no_packed;
1683− }
1684−
1685− if (!(md->flags & MMC_BLK_PACKED_CMD))
1686− goto no_packed;
1687−
1688− if ((rq_data_dir(cur) == WRITE) &&
1689− mmc_host_packed_wr(card->host))
1690− max_packed_rw = card->ext_csd.max_packed_writes;
1691−
1692− if (max_packed_rw == 0)
1693− goto no_packed;
1694−
1695− if (mmc_req_rel_wr(cur) &&
1696− (md->flags & MMC_BLK_REL_WR) && !en_rel_wr)
1697− goto no_packed;
1698−
1699− if (mmc_large_sector(card) &&
1700− !IS_ALIGNED(blk_rq_sectors(cur), 8))
1701− goto no_packed;
1702−
1703− mmc_blk_clear_packed(mqrq);
1704−
1705− max_blk_count = min(card->host->max_blk_count,
1706− card->host->max_req_size >> 9);
1707− if (unlikely(max_blk_count > 0xffff))
1708− max_blk_count = 0xffff;
1709−
1710− max_phys_segs = queue_max_segments(q);
1711− req_sectors += blk_rq_sectors(cur);
1712− phys_segments += cur->nr_phys_segments;
1713−
1714− if (rq_data_dir(cur) == WRITE) {
1715− req_sectors += mmc_large_sector(card) ? 8 : 1;
1716− phys_segments += mmc_calc_packed_hdr_segs(q, card);
1717− }
1718−
1719− do {
1720− if (reqs >= max_packed_rw - 1) {
1721− put_back = false;
1722− break;
1723− }
1724−
1725− spin_lock_irq(q->queue_lock);
1726− next = blk_fetch_request(q);
1727− spin_unlock_irq(q->queue_lock);
1728− if (!next) {
1729− put_back = false;
1730− break;
1731− }
1732−
1733− if (mmc_large_sector(card) &&
1734− !IS_ALIGNED(blk_rq_sectors(next), 8))
1735− break;
1736−
1737− if (req_op(next) == REQ_OP_DISCARD ||
1738− req_op(next) == REQ_OP_SECURE_ERASE ||
1739− req_op(next) == REQ_OP_FLUSH)
1740− break;
1741−
1742− if (rq_data_dir(cur) != rq_data_dir(next))
1743− break;
1744−
1745− if (mmc_req_rel_wr(next) &&
1746− (md->flags & MMC_BLK_REL_WR) && !en_rel_wr)
1747− break;
1748−
1749− req_sectors += blk_rq_sectors(next);
1750− if (req_sectors > max_blk_count)
1751− break;
1752−
1753− phys_segments += next->nr_phys_segments;
1754− if (phys_segments > max_phys_segs)
1755− break;
1756−
1757− list_add_tail(&next->queuelist, &mqrq->packed->list);
1758− cur = next;
1759− reqs++;
1760− } while (1);
1761−
1762− if (put_back) {
1763− spin_lock_irq(q->queue_lock);
1764− blk_requeue_request(q, next);
1765− spin_unlock_irq(q->queue_lock);
1766− }
1767−
1768− if (reqs > 0) {
1769− list_add(&req->queuelist, &mqrq->packed->list);
1770− mqrq->packed->nr_entries = ++reqs;
1771− mqrq->packed->retries = reqs;
1772− return reqs;
1773− }
1774−
1775−no_packed:
1776− mqrq->cmd_type = MMC_PACKED_NONE;
1777− return 0;
1778−}
1779−
1780−static void mmc_blk_packed_hdr_wrq_prep(struct mmc_queue_req *mqrq,
1781− struct mmc_card *card,
1782− struct mmc_queue *mq)
1783−{
1784− struct mmc_blk_request *brq = &mqrq->brq;
1785− struct request *req = mqrq->req;
1786− struct request *prq;
1787− struct mmc_blk_data *md = mq->data;
1788− struct mmc_packed *packed = mqrq->packed;
1789− bool do_rel_wr, do_data_tag;
1790− __le32 *packed_cmd_hdr;
1791− u8 hdr_blocks;
1792− u8 i = 1;
1793−
1794− mqrq->cmd_type = MMC_PACKED_WRITE;
1795− packed->blocks = 0;
1796− packed->idx_failure = MMC_PACKED_NR_IDX;
1797−
1798− packed_cmd_hdr = packed->cmd_hdr;
1799− memset(packed_cmd_hdr, 0, sizeof(packed->cmd_hdr));
1800− packed_cmd_hdr[0] = cpu_to_le32((packed->nr_entries << 16) |
1801− (PACKED_CMD_WR << 8) | PACKED_CMD_VER);
1802− hdr_blocks = mmc_large_sector(card) ? 8 : 1;
1803−
1804− /*
1805− * Argument for each entry of packed group
1806− */
1807− list_for_each_entry(prq, &packed->list, queuelist) {
1808− do_rel_wr = mmc_req_rel_wr(prq) && (md->flags & MMC_BLK_REL_WR);
1809− do_data_tag = (card->ext_csd.data_tag_unit_size) &&
1810− (prq->cmd_flags & REQ_META) &&
1811− (rq_data_dir(prq) == WRITE) &&
1812− blk_rq_bytes(prq) >= card->ext_csd.data_tag_unit_size;
1813− /* Argument of CMD23 */
1814− packed_cmd_hdr[(i * 2)] = cpu_to_le32(
1815− (do_rel_wr ? MMC_CMD23_ARG_REL_WR : 0) |
1816− (do_data_tag ? MMC_CMD23_ARG_TAG_REQ : 0) |
1817− blk_rq_sectors(prq));
1818− /* Argument of CMD18 or CMD25 */
1819− packed_cmd_hdr[((i * 2)) + 1] = cpu_to_le32(
1820− mmc_card_blockaddr(card) ?
1821− blk_rq_pos(prq) : blk_rq_pos(prq) << 9);
1822− packed->blocks += blk_rq_sectors(prq);
1823− i++;
1824− }
1825−
1826− memset(brq, 0, sizeof(struct mmc_blk_request));
1827− brq->mrq.cmd = &brq->cmd;
1828− brq->mrq.data = &brq->data;
1829− brq->mrq.sbc = &brq->sbc;
1830− brq->mrq.stop = &brq->stop;
1831−
1832− brq->sbc.opcode = MMC_SET_BLOCK_COUNT;
1833− brq->sbc.arg = MMC_CMD23_ARG_PACKED | (packed->blocks + hdr_blocks);
1834− brq->sbc.flags = MMC_RSP_R1 | MMC_CMD_AC;
1835−
1836− brq->cmd.opcode = MMC_WRITE_MULTIPLE_BLOCK;
1837− brq->cmd.arg = blk_rq_pos(req);
1838− if (!mmc_card_blockaddr(card))
1839− brq->cmd.arg <<= 9;
1840− brq->cmd.flags = MMC_RSP_SPI_R1 | MMC_RSP_R1 | MMC_CMD_ADTC;
1841−
1842− brq->data.blksz = 512;
1843− brq->data.blocks = packed->blocks + hdr_blocks;
1844− brq->data.flags = MMC_DATA_WRITE;
1845−
1846− brq->stop.opcode = MMC_STOP_TRANSMISSION;
1847− brq->stop.arg = 0;
1848− brq->stop.flags = MMC_RSP_SPI_R1B | MMC_RSP_R1B | MMC_CMD_AC;
1849−
1850− mmc_set_data_timeout(&brq->data, card);
1851−
1852− brq->data.sg = mqrq->sg;
1853− brq->data.sg_len = mmc_queue_map_sg(mq, mqrq);
1854−
1855− mqrq->mmc_active.mrq = &brq->mrq;
1856− mqrq->mmc_active.err_check = mmc_blk_packed_err_check;
1857−
1858− mmc_queue_bounce_pre(mqrq);
1859−}
1860−
18611568 static int mmc_blk_cmd_err(struct mmc_blk_data *md, struct mmc_card *card,
18621569 struct mmc_blk_request *brq, struct request *req,
18631570 int ret)
@@ -1881,97 +1588,25 @@ static int mmc_blk_cmd_err(struct mmc_blk_data *md, struct mmc_card *card, · 17 unmodified lines
18811588 ret = blk_end_request(req, 0, blocks << 9);
18821589 }
18831590 } else {
1884− if (!mmc_packed_cmd(mq_rq->cmd_type))
1885− ret = blk_end_request(req, 0, brq->data.bytes_xfered);
1591+ ret = blk_end_request(req, 0, brq->data.bytes_xfered);
18861592 }
18871593 return ret;
18881594 }
18891595
1890−static int mmc_blk_end_packed_req(struct mmc_queue_req *mq_rq)
1891−{
1892− struct request *prq;
1893− struct mmc_packed *packed = mq_rq->packed;
1894− int idx = packed->idx_failure, i = 0;
1895− int ret = 0;
1896−
1897− while (!list_empty(&packed->list)) {
1898− prq = list_entry_rq(packed->list.next);
1899− if (idx == i) {
1900− /* retry from error index */
1901− packed->nr_entries -= idx;
1902− mq_rq->req = prq;
1903− ret = 1;
1904−
1905− if (packed->nr_entries == MMC_PACKED_NR_SINGLE) {
1906− list_del_init(&prq->queuelist);
1907− mmc_blk_clear_packed(mq_rq);
1908− }
1909− return ret;
1910− }
1911− list_del_init(&prq->queuelist);
1912− blk_end_request(prq, 0, blk_rq_bytes(prq));
1913− i++;
1914− }
1915−
1916− mmc_blk_clear_packed(mq_rq);
1917− return ret;
1918−}
1919−
1920−static void mmc_blk_abort_packed_req(struct mmc_queue_req *mq_rq)
1921−{
1922− struct request *prq;
1923− struct mmc_packed *packed = mq_rq->packed;
1924−
1925− while (!list_empty(&packed->list)) {
1926− prq = list_entry_rq(packed->list.next);
1927− list_del_init(&prq->queuelist);
1928− blk_end_request(prq, -EIO, blk_rq_bytes(prq));
1929− }
1930−
1931− mmc_blk_clear_packed(mq_rq);
1932−}
1933−
1934−static void mmc_blk_revert_packed_req(struct mmc_queue *mq,
1935− struct mmc_queue_req *mq_rq)
1936−{
1937− struct request *prq;
1938− struct request_queue *q = mq->queue;
1939− struct mmc_packed *packed = mq_rq->packed;
1940−
1941− while (!list_empty(&packed->list)) {
1942− prq = list_entry_rq(packed->list.prev);
1943− if (prq->queuelist.prev != &packed->list) {
1944− list_del_init(&prq->queuelist);
1945− spin_lock_irq(q->queue_lock);
1946− blk_requeue_request(mq->queue, prq);
1947− spin_unlock_irq(q->queue_lock);
1948− } else {
1949− list_del_init(&prq->queuelist);
1950− }
1951− }
1952−
1953− mmc_blk_clear_packed(mq_rq);
1954−}
1955−
19561596 static int mmc_blk_issue_rw_rq(struct mmc_queue *mq, struct request *rqc)
19571597 {
1958− struct mmc_blk_data *md = mq->data;
1598+ struct mmc_blk_data *md = mq->blkdata;
19591599 struct mmc_card *card = md->queue.card;
1960− struct mmc_blk_request *brq = &mq->mqrq_cur->brq;
1600+ struct mmc_blk_request *brq;
19611601 int ret = 1, disable_multi = 0, retry = 0, type, retune_retry_done = 0;
19621602 enum mmc_blk_status status;
19631603 struct mmc_queue_req *mq_rq;
1964− struct request *req = rqc;
1604+ struct request *req;
19651605 struct mmc_async_req *areq;
1966− const u8 packed_nr = 2;
1967− u8 reqs = 0;
19681606
19691607 if (!rqc && !mq->mqrq_prev->req)
19701608 return 0;
19711609
1972− if (rqc)
1973− reqs = mmc_blk_prep_packed_list(mq, rqc);
1974−
19751610 do {
19761611 if (rqc) {
19771612 /*
@@ -1981,20 +1616,18 @@ static int mmc_blk_issue_rw_rq(struct mmc_queue *mq, struct request *rqc) · 3 unmodified lines
19811616 if (mmc_large_sector(card) &&
19821617 !IS_ALIGNED(blk_rq_sectors(rqc), 8)) {
19831618 pr_err("%s: Transfer size is not 4KB sector size aligned\n",
1984− req->rq_disk->disk_name);
1619+ rqc->rq_disk->disk_name);
19851620 mq_rq = mq->mqrq_cur;
1621+ req = rqc;
1622+ rqc = NULL;
19861623 goto cmd_abort;
19871624 }
19881625
1989− if (reqs >= packed_nr)
1990− mmc_blk_packed_hdr_wrq_prep(mq->mqrq_cur,
1991− card, mq);
1992− else
1993− mmc_blk_rw_rq_prep(mq->mqrq_cur, card, 0, mq);
1626+ mmc_blk_rw_rq_prep(mq->mqrq_cur, card, 0, mq);
19941627 areq = &mq->mqrq_cur->mmc_active;
19951628 } else
19961629 areq = NULL;
1997− areq = mmc_start_req(card->host, areq, (int *) &status);
1630+ areq = mmc_start_req(card->host, areq, &status);
19981631 if (!areq) {
19991632 if (status == MMC_BLK_NEW_REQUEST)
20001633 mq->flags |= MMC_QUEUE_NEW_REQUEST;
@@ -2015,13 +1648,8 @@ static int mmc_blk_issue_rw_rq(struct mmc_queue *mq, struct request *rqc) · 14 unmodified lines
20151648 */
20161649 mmc_blk_reset_success(md, type);
20171650
2018− if (mmc_packed_cmd(mq_rq->cmd_type)) {
2019− ret = mmc_blk_end_packed_req(mq_rq);
2020− break;
2021− } else {
2022− ret = blk_end_request(req, 0,
2023− brq->data.bytes_xfered);
2024− }
1651+ ret = blk_end_request(req, 0,
1652+ brq->data.bytes_xfered);
20251653
20261654 /*
20271655 * If the blk_end_request function returns non-zero even
@@ -2058,8 +1686,7 @@ static int mmc_blk_issue_rw_rq(struct mmc_queue *mq, struct request *rqc) · 30 unmodified lines
20581686 err = mmc_blk_reset(md, card->host, type);
20591687 if (!err)
20601688 break;
2061− if (err == -ENODEV ||
2062− mmc_packed_cmd(mq_rq->cmd_type))
1689+ if (err == -ENODEV)
20631690 goto cmd_abort;
20641691 /* Fall through */
20651692 }
@@ -2090,23 +1717,14 @@ static int mmc_blk_issue_rw_rq(struct mmc_queue *mq, struct request *rqc) · 24 unmodified lines
20901717 }
20911718
20921719 if (ret) {
2093− if (mmc_packed_cmd(mq_rq->cmd_type)) {
2094− if (!mq_rq->packed->retries)
2095− goto cmd_abort;
2096− mmc_blk_packed_hdr_wrq_prep(mq_rq, card, mq);
2097− mmc_start_req(card->host,
2098− &mq_rq->mmc_active, NULL);
2099− } else {
2100−
2101− /*
2102− * In case of a incomplete request
2103− * prepare it again and resend.
2104− */
2105− mmc_blk_rw_rq_prep(mq_rq, card,
2106− disable_multi, mq);
2107− mmc_start_req(card->host,
2108− &mq_rq->mmc_active, NULL);
2109− }
1720+ /*
1721+ * In case of a incomplete request
1722+ * prepare it again and resend.
1723+ */
1724+ mmc_blk_rw_rq_prep(mq_rq, card,
1725+ disable_multi, mq);
1726+ mmc_start_req(card->host,
1727+ &mq_rq->mmc_active, NULL);
21101728 mq_rq->brq.retune_retry_done = retune_retry_done;
21111729 }
21121730 } while (ret);
@@ -2114,15 +1732,11 @@ static int mmc_blk_issue_rw_rq(struct mmc_queue *mq, struct request *rqc) · 1 unmodified line
21141732 return 1;
21151733
21161734 cmd_abort:
2117− if (mmc_packed_cmd(mq_rq->cmd_type)) {
2118− mmc_blk_abort_packed_req(mq_rq);
2119− } else {
2120− if (mmc_card_removed(card))
2121− req->cmd_flags |= REQ_QUIET;
2122− while (ret)
2123− ret = blk_end_request(req, -EIO,
2124− blk_rq_cur_bytes(req));
2125− }
1735+ if (mmc_card_removed(card))
1736+ req->cmd_flags |= REQ_QUIET;
1737+ while (ret)
1738+ ret = blk_end_request(req, -EIO,
1739+ blk_rq_cur_bytes(req));
21261740
21271741 start_new_req:
21281742 if (rqc) {
@@ -2130,12 +1744,6 @@ static int mmc_blk_issue_rw_rq(struct mmc_queue *mq, struct request *rqc) · 1 unmodified line
21301744 rqc->cmd_flags |= REQ_QUIET;
21311745 blk_end_request_all(rqc, -EIO);
21321746 } else {
2133− /*
2134− * If current request is packed, it needs to put back.
2135− */
2136− if (mmc_packed_cmd(mq->mqrq_cur->cmd_type))
2137− mmc_blk_revert_packed_req(mq, mq->mqrq_cur);
2138−
21391747 mmc_blk_rw_rq_prep(mq->mqrq_cur, card, 0, mq);
21401748 mmc_start_req(card->host,
21411749 &mq->mqrq_cur->mmc_active, NULL);
@@ -2148,10 +1756,8 @@ static int mmc_blk_issue_rw_rq(struct mmc_queue *mq, struct request *rqc) · 6 unmodified lines
21481756 int mmc_blk_issue_rq(struct mmc_queue *mq, struct request *req)
21491757 {
21501758 int ret;
2151− struct mmc_blk_data *md = mq->data;
1759+ struct mmc_blk_data *md = mq->blkdata;
21521760 struct mmc_card *card = md->queue.card;
2153− struct mmc_host *host = card->host;
2154− unsigned long flags;
21551761 bool req_is_special = mmc_req_is_special(req);
21561762
21571763 if (req && !mq->mqrq_prev->req)
@@ -2184,11 +1790,6 @@ int mmc_blk_issue_rq(struct mmc_queue *mq, struct request *req) · 26 unmodified lines
21841790 mmc_blk_issue_rw_rq(mq, NULL);
21851791 ret = mmc_blk_issue_flush(mq, req);
21861792 } else {
2187− if (!req && host->areq) {
2188− spin_lock_irqsave(&host->context_info.lock, flags);
2189− host->context_info.is_waiting_last_req = true;
2190− spin_unlock_irqrestore(&host->context_info.lock, flags);
2191− }
21921793 ret = mmc_blk_issue_rw_rq(mq, req);
21931794 }
21941795
@@ -2266,7 +1867,7 @@ again: · 71 unmodified lines
22661867 if (ret)
22671868 goto err_putdisk;
22681869
2269− md->queue.data = md;
1870+ md->queue.blkdata = md;
22701871
22711872 md->disk->major = MMC_BLOCK_MAJOR;
22721873 md->disk->first_minor = devidx * perdev_minors;
@@ -2318,14 +1919,6 @@ again: · 45 unmodified lines
23181919 blk_queue_write_cache(md->queue.queue, true, true);
23191920 }
23201921
2321− if (mmc_card_mmc(card) &&
2322− (area_type == MMC_BLK_DATA_AREA_MAIN) &&
2323− (md->flags & MMC_BLK_CMD23) &&
2324− card->ext_csd.packed_event_en) {
2325− if (!mmc_packed_init(&md->queue, card))
2326− md->flags |= MMC_BLK_PACKED_CMD;
2327− }
2328−
23291922 return md;
23301923
23311924 err_putdisk:
@@ -2429,8 +2022,6 @@ static void mmc_blk_remove_req(struct mmc_blk_data *md) · 97 unmodified lines
24292022 */
24302023 card = md->queue.card;
24312024 mmc_cleanup_queue(&md->queue);
2432− if (md->flags & MMC_BLK_PACKED_CMD)
2433− mmc_packed_clean(&md->queue);
24342025 if (md->disk->flags & GENHD_FL_UP) {
24352026 device_remove_file(disk_to_dev(md->disk), &md->force_ro);
24362027 if ((md->area_type & MMC_BLK_DATA_AREA_BOOT) &&
drivers/mmc/card/mmc_test.c+43−15
@@ -214,7 +214,8 @@ static void mmc_test_prepare_mrq(struct mmc_test_card *test, · 213 unmodified lines
214214 struct mmc_request *mrq, struct scatterlist *sg, unsigned sg_len,
215215 unsigned dev_addr, unsigned blocks, unsigned blksz, int write)
216216 {
217− BUG_ON(!mrq || !mrq->cmd || !mrq->data || !mrq->stop);
217+ if (WARN_ON(!mrq || !mrq->cmd || !mrq->data || !mrq->stop))
218+ return;
218219
219220 if (blocks > 1) {
220221 mrq->cmd->opcode = write ?
@@ -694,7 +695,8 @@ static int mmc_test_cleanup(struct mmc_test_card *test) · 473 unmodified lines
694695 static void mmc_test_prepare_broken_mrq(struct mmc_test_card *test,
695696 struct mmc_request *mrq, int write)
696697 {
697− BUG_ON(!mrq || !mrq->cmd || !mrq->data);
698+ if (WARN_ON(!mrq || !mrq->cmd || !mrq->data))
699+ return;
698700
699701 if (mrq->data->blocks > 1) {
700702 mrq->cmd->opcode = write ?
@@ -714,7 +716,8 @@ static int mmc_test_check_result(struct mmc_test_card *test, · 13 unmodified lines
714716 {
715717 int ret;
716718
717− BUG_ON(!mrq || !mrq->cmd || !mrq->data);
719+ if (WARN_ON(!mrq || !mrq->cmd || !mrq->data))
720+ return -EINVAL;
718721
719722 ret = 0;
720723
@@ -736,15 +739,28 @@ static int mmc_test_check_result(struct mmc_test_card *test, · 15 unmodified lines
736739 return ret;
737740 }
738741
739−static int mmc_test_check_result_async(struct mmc_card *card,
742+static enum mmc_blk_status mmc_test_check_result_async(struct mmc_card *card,
740743 struct mmc_async_req *areq)
741744 {
742745 struct mmc_test_async_req *test_async =
743746 container_of(areq, struct mmc_test_async_req, areq);
747+ int ret;
744748
745749 mmc_test_wait_busy(test_async->test);
746750
747− return mmc_test_check_result(test_async->test, areq->mrq);
751+ /*
752+ * FIXME: this would earlier just casts a regular error code,
753+ * either of the kernel type -ERRORCODE or the local test framework
754+ * RESULT_* errorcode, into an enum mmc_blk_status and return as
755+ * result check. Instead, convert it to some reasonable type by just
756+ * returning either MMC_BLK_SUCCESS or MMC_BLK_CMD_ERR.
757+ * If possible, a reasonable error code should be returned.
758+ */
759+ ret = mmc_test_check_result(test_async->test, areq->mrq);
760+ if (ret)
761+ return MMC_BLK_CMD_ERR;
762+
763+ return MMC_BLK_SUCCESS;
748764 }
749765
750766 /*
@@ -755,7 +771,8 @@ static int mmc_test_check_broken_result(struct mmc_test_card *test, · 4 unmodified lines
755771 {
756772 int ret;
757773
758− BUG_ON(!mrq || !mrq->cmd || !mrq->data);
774+ if (WARN_ON(!mrq || !mrq->cmd || !mrq->data))
775+ return -EINVAL;
759776
760777 ret = 0;
761778
@@ -817,8 +834,9 @@ static int mmc_test_nonblock_transfer(struct mmc_test_card *test, · 55 unmodified lines
817834 struct mmc_async_req *done_areq;
818835 struct mmc_async_req *cur_areq = &test_areq[0].areq;
819836 struct mmc_async_req *other_areq = &test_areq[1].areq;
837+ enum mmc_blk_status status;
820838 int i;
821− int ret;
839+ int ret = RESULT_OK;
822840
823841 test_areq[0].test = test;
824842 test_areq[1].test = test;
@@ -834,10 +852,12 @@ static int mmc_test_nonblock_transfer(struct mmc_test_card *test, · 9 unmodified lines
834852 for (i = 0; i < count; i++) {
835853 mmc_test_prepare_mrq(test, cur_areq->mrq, sg, sg_len, dev_addr,
836854 blocks, blksz, write);
837− done_areq = mmc_start_req(test->card->host, cur_areq, &ret);
855+ done_areq = mmc_start_req(test->card->host, cur_areq, &status);
838856
839− if (ret || (!done_areq && i > 0))
857+ if (status != MMC_BLK_SUCCESS || (!done_areq && i > 0)) {
858+ ret = RESULT_FAIL;
840859 goto err;
860+ }
841861
842862 if (done_areq) {
843863 if (done_areq->mrq == &mrq2)
@@ -851,7 +871,9 @@ static int mmc_test_nonblock_transfer(struct mmc_test_card *test, · 7 unmodified lines
851871 dev_addr += blocks;
852872 }
853873
854− done_areq = mmc_start_req(test->card->host, NULL, &ret);
874+ done_areq = mmc_start_req(test->card->host, NULL, &status);
875+ if (status != MMC_BLK_SUCCESS)
876+ ret = RESULT_FAIL;
855877
856878 return ret;
857879 err:
@@ -2351,6 +2373,7 @@ static int mmc_test_ongoing_transfer(struct mmc_test_card *test, · 1493 unmodified lines
23512373 struct mmc_request *mrq;
23522374 unsigned long timeout;
23532375 bool expired = false;
2376+ enum mmc_blk_status blkstat = MMC_BLK_SUCCESS;
23542377 int ret = 0, cmd_ret;
23552378 u32 status = 0;
23562379 int count = 0;
@@ -2378,9 +2401,11 @@ static int mmc_test_ongoing_transfer(struct mmc_test_card *test, · 21 unmodified lines
23782401
23792402 /* Start ongoing data request */
23802403 if (use_areq) {
2381− mmc_start_req(host, &test_areq.areq, &ret);
2382− if (ret)
2404+ mmc_start_req(host, &test_areq.areq, &blkstat);
2405+ if (blkstat != MMC_BLK_SUCCESS) {
2406+ ret = RESULT_FAIL;
23832407 goto out_free;
2408+ }
23842409 } else {
23852410 mmc_wait_for_req(host, mrq);
23862411 }
@@ -2413,10 +2438,13 @@ static int mmc_test_ongoing_transfer(struct mmc_test_card *test, · 26 unmodified lines
24132438 } while (repeat_cmd && R1_CURRENT_STATE(status) != R1_STATE_TRAN);
24142439
24152440 /* Wait for data request to complete */
2416− if (use_areq)
2417− mmc_start_req(host, NULL, &ret);
2418− else
2441+ if (use_areq) {
2442+ mmc_start_req(host, NULL, &blkstat);
2443+ if (blkstat != MMC_BLK_SUCCESS)
2444+ ret = RESULT_FAIL;
2445+ } else {
24192446 mmc_wait_for_req_done(test->card->host, mrq);
2447+ }
24202448
24212449 /*
24222450 * For cap_cmd_during_tfr request, upper layer must send stop if
drivers/mmc/card/queue.c+123−189
@@ -53,6 +53,7 @@ static int mmc_queue_thread(void *d) · 52 unmodified lines
5353 {
5454 struct mmc_queue *mq = d;
5555 struct request_queue *q = mq->queue;
56+ struct mmc_context_info *cntx = &mq->card->host->context_info;
5657
5758 current->flags |= PF_MEMALLOC;
5859
@@ -63,6 +64,19 @@ static int mmc_queue_thread(void *d) · 4 unmodified lines
6364 spin_lock_irq(q->queue_lock);
6465 set_current_state(TASK_INTERRUPTIBLE);
6566 req = blk_fetch_request(q);
67+ mq->asleep = false;
68+ cntx->is_waiting_last_req = false;
69+ cntx->is_new_req = false;
70+ if (!req) {
71+ /*
72+ * Dispatch queue is empty so set flags for
73+ * mmc_request_fn() to wake us up.
74+ */
75+ if (mq->mqrq_prev->req)
76+ cntx->is_waiting_last_req = true;
77+ else
78+ mq->asleep = true;
79+ }
6680 mq->mqrq_cur->req = req;
6781 spin_unlock_irq(q->queue_lock);
6882
@@ -115,7 +129,6 @@ static void mmc_request_fn(struct request_queue *q) · 46 unmodified lines
115129 {
116130 struct mmc_queue *mq = q->queuedata;
117131 struct request *req;
118− unsigned long flags;
119132 struct mmc_context_info *cntx;
120133
121134 if (!mq) {
@@ -127,19 +140,13 @@ static void mmc_request_fn(struct request_queue *q) · 5 unmodified lines
127140 }
128141
129142 cntx = &mq->card->host->context_info;
130− if (!mq->mqrq_cur->req && mq->mqrq_prev->req) {
131− /*
132− * New MMC request arrived when MMC thread may be
133− * blocked on the previous request to be complete
134− * with no current request fetched
135− */
136− spin_lock_irqsave(&cntx->lock, flags);
137− if (cntx->is_waiting_last_req) {
138− cntx->is_new_req = true;
139− wake_up_interruptible(&cntx->wait);
140− }
141− spin_unlock_irqrestore(&cntx->lock, flags);
142− } else if (!mq->mqrq_cur->req && !mq->mqrq_prev->req)
143+
144+ if (cntx->is_waiting_last_req) {
145+ cntx->is_new_req = true;
146+ wake_up_interruptible(&cntx->wait);
147+ }
148+
149+ if (mq->asleep)
143150 wake_up_process(mq->thread);
144151 }
145152
@@ -179,6 +186,82 @@ static void mmc_queue_setup_discard(struct request_queue *q, · 33 unmodified lines
179186 queue_flag_set_unlocked(QUEUE_FLAG_SECERASE, q);
180187 }
181188
189+#ifdef CONFIG_MMC_BLOCK_BOUNCE
190+static bool mmc_queue_alloc_bounce_bufs(struct mmc_queue *mq,
191+ unsigned int bouncesz)
192+{
193+ int i;
194+
195+ for (i = 0; i < mq->qdepth; i++) {
196+ mq->mqrq[i].bounce_buf = kmalloc(bouncesz, GFP_KERNEL);
197+ if (!mq->mqrq[i].bounce_buf)
198+ goto out_err;
199+ }
200+
201+ return true;
202+
203+out_err:
204+ while (--i >= 0) {
205+ kfree(mq->mqrq[i].bounce_buf);
206+ mq->mqrq[i].bounce_buf = NULL;
207+ }
208+ pr_warn("%s: unable to allocate bounce buffers\n",
209+ mmc_card_name(mq->card));
210+ return false;
211+}
212+
213+static int mmc_queue_alloc_bounce_sgs(struct mmc_queue *mq,
214+ unsigned int bouncesz)
215+{
216+ int i, ret;
217+
218+ for (i = 0; i < mq->qdepth; i++) {
219+ mq->mqrq[i].sg = mmc_alloc_sg(1, &ret);
220+ if (ret)
221+ return ret;
222+
223+ mq->mqrq[i].bounce_sg = mmc_alloc_sg(bouncesz / 512, &ret);
224+ if (ret)
225+ return ret;
226+ }
227+
228+ return 0;
229+}
230+#endif
231+
232+static int mmc_queue_alloc_sgs(struct mmc_queue *mq, int max_segs)
233+{
234+ int i, ret;
235+
236+ for (i = 0; i < mq->qdepth; i++) {
237+ mq->mqrq[i].sg = mmc_alloc_sg(max_segs, &ret);
238+ if (ret)
239+ return ret;
240+ }
241+
242+ return 0;
243+}
244+
245+static void mmc_queue_req_free_bufs(struct mmc_queue_req *mqrq)
246+{
247+ kfree(mqrq->bounce_sg);
248+ mqrq->bounce_sg = NULL;
249+
250+ kfree(mqrq->sg);
251+ mqrq->sg = NULL;
252+
253+ kfree(mqrq->bounce_buf);
254+ mqrq->bounce_buf = NULL;
255+}
256+
257+static void mmc_queue_reqs_free_bufs(struct mmc_queue *mq)
258+{
259+ int i;
260+
261+ for (i = 0; i < mq->qdepth; i++)
262+ mmc_queue_req_free_bufs(&mq->mqrq[i]);
263+}
264+
182265 /**
183266 * mmc_init_queue - initialise a queue structure.
184267 * @mq: mmc queue
@@ -193,9 +276,8 @@ int mmc_init_queue(struct mmc_queue *mq, struct mmc_card *card, · 8 unmodified lines
193276 {
194277 struct mmc_host *host = card->host;
195278 u64 limit = BLK_BOUNCE_HIGH;
196− int ret;
197− struct mmc_queue_req *mqrq_cur = &mq->mqrq[0];
198− struct mmc_queue_req *mqrq_prev = &mq->mqrq[1];
279+ bool bounce = false;
280+ int ret = -ENOMEM;
199281
200282 if (mmc_dev(host)->dma_mask && *mmc_dev(host)->dma_mask)
201283 limit = (u64)dma_max_pfn(mmc_dev(host)) << PAGE_SHIFT;
@@ -205,8 +287,13 @@ int mmc_init_queue(struct mmc_queue *mq, struct mmc_card *card, · 3 unmodified lines
205287 if (!mq->queue)
206288 return -ENOMEM;
207289
208− mq->mqrq_cur = mqrq_cur;
209− mq->mqrq_prev = mqrq_prev;
290+ mq->qdepth = 2;
291+ mq->mqrq = kcalloc(mq->qdepth, sizeof(struct mmc_queue_req),
292+ GFP_KERNEL);
293+ if (!mq->mqrq)
294+ goto blk_cleanup;
295+ mq->mqrq_cur = &mq->mqrq[0];
296+ mq->mqrq_prev = &mq->mqrq[1];
210297 mq->queue->queuedata = mq;
211298
212299 blk_queue_prep_rq(mq->queue, mmc_prep_request);
@@ -228,63 +315,29 @@ int mmc_init_queue(struct mmc_queue *mq, struct mmc_card *card, · 15 unmodified lines
228315 if (bouncesz > (host->max_blk_count * 512))
229316 bouncesz = host->max_blk_count * 512;
230317
231− if (bouncesz > 512) {
232− mqrq_cur->bounce_buf = kmalloc(bouncesz, GFP_KERNEL);
233− if (!mqrq_cur->bounce_buf) {
234− pr_warn("%s: unable to allocate bounce cur buffer\n",
235− mmc_card_name(card));
236− } else {
237− mqrq_prev->bounce_buf =
238− kmalloc(bouncesz, GFP_KERNEL);
239− if (!mqrq_prev->bounce_buf) {
240− pr_warn("%s: unable to allocate bounce prev buffer\n",
241− mmc_card_name(card));
242− kfree(mqrq_cur->bounce_buf);
243− mqrq_cur->bounce_buf = NULL;
244− }
245− }
246− }
247−
248− if (mqrq_cur->bounce_buf && mqrq_prev->bounce_buf) {
318+ if (bouncesz > 512 &&
319+ mmc_queue_alloc_bounce_bufs(mq, bouncesz)) {
249320 blk_queue_bounce_limit(mq->queue, BLK_BOUNCE_ANY);
250321 blk_queue_max_hw_sectors(mq->queue, bouncesz / 512);
251322 blk_queue_max_segments(mq->queue, bouncesz / 512);
252323 blk_queue_max_segment_size(mq->queue, bouncesz);
253324
254− mqrq_cur->sg = mmc_alloc_sg(1, &ret);
255− if (ret)
256− goto cleanup_queue;
257−
258− mqrq_cur->bounce_sg =
259− mmc_alloc_sg(bouncesz / 512, &ret);
260− if (ret)
261− goto cleanup_queue;
262−
263− mqrq_prev->sg = mmc_alloc_sg(1, &ret);
264− if (ret)
265− goto cleanup_queue;
266−
267− mqrq_prev->bounce_sg =
268− mmc_alloc_sg(bouncesz / 512, &ret);
325+ ret = mmc_queue_alloc_bounce_sgs(mq, bouncesz);
269326 if (ret)
270327 goto cleanup_queue;
328+ bounce = true;
271329 }
272330 }
273331 #endif
274332
275− if (!mqrq_cur->bounce_buf && !mqrq_prev->bounce_buf) {
333+ if (!bounce) {
276334 blk_queue_bounce_limit(mq->queue, limit);
277335 blk_queue_max_hw_sectors(mq->queue,
278336 min(host->max_blk_count, host->max_req_size / 512));
279337 blk_queue_max_segments(mq->queue, host->max_segs);
280338 blk_queue_max_segment_size(mq->queue, host->max_seg_size);
281339
282− mqrq_cur->sg = mmc_alloc_sg(host->max_segs, &ret);
283− if (ret)
284− goto cleanup_queue;
285−
286−
287− mqrq_prev->sg = mmc_alloc_sg(host->max_segs, &ret);
340+ ret = mmc_queue_alloc_sgs(mq, host->max_segs);
288341 if (ret)
289342 goto cleanup_queue;
290343 }
@@ -296,27 +349,16 @@ int mmc_init_queue(struct mmc_queue *mq, struct mmc_card *card, · 5 unmodified lines
296349
297350 if (IS_ERR(mq->thread)) {
298351 ret = PTR_ERR(mq->thread);
299− goto free_bounce_sg;
352+ goto cleanup_queue;
300353 }
301354
302355 return 0;
303− free_bounce_sg:
304− kfree(mqrq_cur->bounce_sg);
305− mqrq_cur->bounce_sg = NULL;
306− kfree(mqrq_prev->bounce_sg);
307− mqrq_prev->bounce_sg = NULL;
308356
309357 cleanup_queue:
310− kfree(mqrq_cur->sg);
311− mqrq_cur->sg = NULL;
312− kfree(mqrq_cur->bounce_buf);
313− mqrq_cur->bounce_buf = NULL;
314−
315− kfree(mqrq_prev->sg);
316− mqrq_prev->sg = NULL;
317− kfree(mqrq_prev->bounce_buf);
318− mqrq_prev->bounce_buf = NULL;
319−
358+ mmc_queue_reqs_free_bufs(mq);
359+ kfree(mq->mqrq);
360+ mq->mqrq = NULL;
361+blk_cleanup:
320362 blk_cleanup_queue(mq->queue);
321363 return ret;
322364 }
@@ -325,8 +367,6 @@ void mmc_cleanup_queue(struct mmc_queue *mq) · 2 unmodified lines
325367 {
326368 struct request_queue *q = mq->queue;
327369 unsigned long flags;
328− struct mmc_queue_req *mqrq_cur = mq->mqrq_cur;
329− struct mmc_queue_req *mqrq_prev = mq->mqrq_prev;
330370
331371 /* Make sure the queue isn't suspended, as that will deadlock */
332372 mmc_queue_resume(mq);
@@ -340,71 +380,14 @@ void mmc_cleanup_queue(struct mmc_queue *mq) · 7 unmodified lines
340380 blk_start_queue(q);
341381 spin_unlock_irqrestore(q->queue_lock, flags);
342382
343− kfree(mqrq_cur->bounce_sg);
344− mqrq_cur->bounce_sg = NULL;
345−
346− kfree(mqrq_cur->sg);
347− mqrq_cur->sg = NULL;
348−
349− kfree(mqrq_cur->bounce_buf);
350− mqrq_cur->bounce_buf = NULL;
351−
352− kfree(mqrq_prev->bounce_sg);
353− mqrq_prev->bounce_sg = NULL;
354−
355− kfree(mqrq_prev->sg);
356− mqrq_prev->sg = NULL;
357−
358− kfree(mqrq_prev->bounce_buf);
359− mqrq_prev->bounce_buf = NULL;
383+ mmc_queue_reqs_free_bufs(mq);
384+ kfree(mq->mqrq);
385+ mq->mqrq = NULL;
360386
361387 mq->card = NULL;
362388 }
363389 EXPORT_SYMBOL(mmc_cleanup_queue);
364390
365−int mmc_packed_init(struct mmc_queue *mq, struct mmc_card *card)
366−{
367− struct mmc_queue_req *mqrq_cur = &mq->mqrq[0];
368− struct mmc_queue_req *mqrq_prev = &mq->mqrq[1];
369− int ret = 0;
370−
371−
372− mqrq_cur->packed = kzalloc(sizeof(struct mmc_packed), GFP_KERNEL);
373− if (!mqrq_cur->packed) {
374− pr_warn("%s: unable to allocate packed cmd for mqrq_cur\n",
375− mmc_card_name(card));
376− ret = -ENOMEM;
377− goto out;
378− }
379−
380− mqrq_prev->packed = kzalloc(sizeof(struct mmc_packed), GFP_KERNEL);
381− if (!mqrq_prev->packed) {
382− pr_warn("%s: unable to allocate packed cmd for mqrq_prev\n",
383− mmc_card_name(card));
384− kfree(mqrq_cur->packed);
385− mqrq_cur->packed = NULL;
386− ret = -ENOMEM;
387− goto out;
388− }
389−
390− INIT_LIST_HEAD(&mqrq_cur->packed->list);
391− INIT_LIST_HEAD(&mqrq_prev->packed->list);
392−
393−out:
394− return ret;
395−}
396−
397−void mmc_packed_clean(struct mmc_queue *mq)
398−{
399− struct mmc_queue_req *mqrq_cur = &mq->mqrq[0];
400− struct mmc_queue_req *mqrq_prev = &mq->mqrq[1];
401−
402− kfree(mqrq_cur->packed);
403− mqrq_cur->packed = NULL;
404− kfree(mqrq_prev->packed);
405− mqrq_prev->packed = NULL;
406−}
407−
408391 /**
409392 * mmc_queue_suspend - suspend a MMC request queue
410393 * @mq: MMC queue to suspend
@@ -449,41 +432,6 @@ void mmc_queue_resume(struct mmc_queue *mq) · 38 unmodified lines
449432 }
450433 }
451434
452−static unsigned int mmc_queue_packed_map_sg(struct mmc_queue *mq,
453− struct mmc_packed *packed,
454− struct scatterlist *sg,
455− enum mmc_packed_type cmd_type)
456−{
457− struct scatterlist *__sg = sg;
458− unsigned int sg_len = 0;
459− struct request *req;
460−
461− if (mmc_packed_wr(cmd_type)) {
462− unsigned int hdr_sz = mmc_large_sector(mq->card) ? 4096 : 512;
463− unsigned int max_seg_sz = queue_max_segment_size(mq->queue);
464− unsigned int len, remain, offset = 0;
465− u8 *buf = (u8 *)packed->cmd_hdr;
466−
467− remain = hdr_sz;
468− do {
469− len = min(remain, max_seg_sz);
470− sg_set_buf(__sg, buf + offset, len);
471− offset += len;
472− remain -= len;
473− sg_unmark_end(__sg++);
474− sg_len++;
475− } while (remain);
476− }
477−
478− list_for_each_entry(req, &packed->list, queuelist) {
479− sg_len += blk_rq_map_sg(mq->queue, req, __sg);
480− __sg = sg + (sg_len - 1);
481− sg_unmark_end(__sg++);
482− }
483− sg_mark_end(sg + (sg_len - 1));
484− return sg_len;
485−}
486−
487435 /*
488436 * Prepare the sg list(s) to be handed of to the host driver
489437 */
@@ -492,26 +440,12 @@ unsigned int mmc_queue_map_sg(struct mmc_queue *mq, struct mmc_queue_req *mqrq) · 2 unmodified lines
492440 unsigned int sg_len;
493441 size_t buflen;
494442 struct scatterlist *sg;
495− enum mmc_packed_type cmd_type;
496443 int i;
497444
498− cmd_type = mqrq->cmd_type;
499−
500− if (!mqrq->bounce_buf) {
501− if (mmc_packed_cmd(cmd_type))
502− return mmc_queue_packed_map_sg(mq, mqrq->packed,
503− mqrq->sg, cmd_type);
504− else
505− return blk_rq_map_sg(mq->queue, mqrq->req, mqrq->sg);
506− }
507−
508− BUG_ON(!mqrq->bounce_sg);
445+ if (!mqrq->bounce_buf)
446+ return blk_rq_map_sg(mq->queue, mqrq->req, mqrq->sg);
509447
510− if (mmc_packed_cmd(cmd_type))
511− sg_len = mmc_queue_packed_map_sg(mq, mqrq->packed,
512− mqrq->bounce_sg, cmd_type);
513− else
514− sg_len = blk_rq_map_sg(mq->queue, mqrq->req, mqrq->bounce_sg);
448+ sg_len = blk_rq_map_sg(mq->queue, mqrq->req, mqrq->bounce_sg);
515449
516450 mqrq->bounce_sg_len = sg_len;
517451
drivers/mmc/card/queue.h+5−24
@@ -11,6 +11,7 @@ static inline bool mmc_req_is_special(struct request *req) · 10 unmodified lines
1111
1212 struct request;
1313 struct task_struct;
14+struct mmc_blk_data;
1415
1516 struct mmc_blk_request {
1617 struct mmc_request mrq;
@@ -21,23 +22,6 @@ struct mmc_blk_request { · 4 unmodified lines
2122 int retune_retry_done;
2223 };
2324
24−enum mmc_packed_type {
25− MMC_PACKED_NONE = 0,
26− MMC_PACKED_WRITE,
27−};
28−
29−#define mmc_packed_cmd(type) ((type) != MMC_PACKED_NONE)
30−#define mmc_packed_wr(type) ((type) == MMC_PACKED_WRITE)
31−
32−struct mmc_packed {
33− struct list_head list;
34− __le32 cmd_hdr[1024];
35− unsigned int blocks;
36− u8 nr_entries;
37− u8 retries;
38− s16 idx_failure;
39−};
40−
4125 struct mmc_queue_req {
4226 struct request *req;
4327 struct mmc_blk_request brq;
@@ -46,8 +30,6 @@ struct mmc_queue_req { · 2 unmodified lines
4630 struct scatterlist *bounce_sg;
4731 unsigned int bounce_sg_len;
4832 struct mmc_async_req mmc_active;
49− enum mmc_packed_type cmd_type;
50− struct mmc_packed *packed;
5133 };
5234
5335 struct mmc_queue {
@@ -57,11 +39,13 @@ struct mmc_queue { · 3 unmodified lines
5739 unsigned int flags;
5840 #define MMC_QUEUE_SUSPENDED (1 << 0)
5941 #define MMC_QUEUE_NEW_REQUEST (1 << 1)
60− void *data;
42+ bool asleep;
43+ struct mmc_blk_data *blkdata;
6144 struct request_queue *queue;
62− struct mmc_queue_req mqrq[2];
45+ struct mmc_queue_req *mqrq;
6346 struct mmc_queue_req *mqrq_cur;
6447 struct mmc_queue_req *mqrq_prev;
48+ int qdepth;
6549 };
6650
6751 extern int mmc_init_queue(struct mmc_queue *, struct mmc_card *, spinlock_t *,
@@ -75,9 +59,6 @@ extern unsigned int mmc_queue_map_sg(struct mmc_queue *, · 7 unmodified lines
7559 extern void mmc_queue_bounce_pre(struct mmc_queue_req *);
7660 extern void mmc_queue_bounce_post(struct mmc_queue_req *);
7761
78−extern int mmc_packed_init(struct mmc_queue *, struct mmc_card *);
79−extern void mmc_packed_clean(struct mmc_queue *);
80−
8162 extern int mmc_access_rpmb(struct mmc_queue *);
8263
8364 #endif
drivers/mmc/card/sdio_uart.c+0−2
@@ -135,8 +135,6 @@ static void sdio_uart_port_remove(struct sdio_uart_port *port) · 134 unmodified lines
135135 {
136136 struct sdio_func *func;
137137
138− BUG_ON(sdio_uart_table[port->index] != port);
139−
140138 spin_lock(&sdio_uart_table_lock);
141139 sdio_uart_table[port->index] = NULL;
142140 spin_unlock(&sdio_uart_table_lock);
drivers/mmc/core/core.c+36−61
@@ -306,16 +306,16 @@ static int mmc_start_request(struct mmc_host *host, struct mmc_request *mrq) · 305 unmodified lines
306306 mrq->sbc->mrq = mrq;
307307 }
308308 if (mrq->data) {
309− BUG_ON(mrq->data->blksz > host->max_blk_size);
310− BUG_ON(mrq->data->blocks > host->max_blk_count);
311− BUG_ON(mrq->data->blocks * mrq->data->blksz >
312− host->max_req_size);
313−
309+ if (mrq->data->blksz > host->max_blk_size ||
310+ mrq->data->blocks > host->max_blk_count ||
311+ mrq->data->blocks * mrq->data->blksz > host->max_req_size)
312+ return -EINVAL;
314313 #ifdef CONFIG_MMC_DEBUG
315314 sz = 0;
316315 for_each_sg(mrq->data->sg, sg, mrq->data->sg_len, i)
317316 sz += sg->length;
318− BUG_ON(sz != mrq->data->blocks * mrq->data->blksz);
317+ if (sz != mrq->data->blocks * mrq->data->blksz)
318+ return -EINVAL;
319319 #endif
320320
321321 mrq->cmd->data = mrq->data;
@@ -349,8 +349,6 @@ void mmc_start_bkops(struct mmc_card *card, bool from_exception) · 27 unmodified lines
349349 int timeout;
350350 bool use_busy_signal;
351351
352− BUG_ON(!card);
353−
354352 if (!card->ext_csd.man_bkops_en || mmc_card_doing_bkops(card))
355353 return;
356354
@@ -380,7 +378,7 @@ void mmc_start_bkops(struct mmc_card *card, bool from_exception) · 23 unmodified lines
380378 mmc_retune_hold(card->host);
381379
382380 err = __mmc_switch(card, EXT_CSD_CMD_SET_NORMAL,
383− EXT_CSD_BKOPS_START, 1, timeout,
381+ EXT_CSD_BKOPS_START, 1, timeout, 0,
384382 use_busy_signal, true, false);
385383 if (err) {
386384 pr_warn("%s: Error %d starting bkops\n",
@@ -497,32 +495,28 @@ static int __mmc_start_req(struct mmc_host *host, struct mmc_request *mrq) · 110 unmodified lines
497495 *
498496 * Returns enum mmc_blk_status after checking errors.
499497 */
500−static int mmc_wait_for_data_req_done(struct mmc_host *host,
498+static enum mmc_blk_status mmc_wait_for_data_req_done(struct mmc_host *host,
501499 struct mmc_request *mrq,
502500 struct mmc_async_req *next_req)
503501 {
504502 struct mmc_command *cmd;
505503 struct mmc_context_info *context_info = &host->context_info;
506− int err;
507− unsigned long flags;
504+ enum mmc_blk_status status;
508505
509506 while (1) {
510507 wait_event_interruptible(context_info->wait,
511508 (context_info->is_done_rcv ||
512509 context_info->is_new_req));
513− spin_lock_irqsave(&context_info->lock, flags);
514510 context_info->is_waiting_last_req = false;
515− spin_unlock_irqrestore(&context_info->lock, flags);
516511 if (context_info->is_done_rcv) {
517512 context_info->is_done_rcv = false;
518− context_info->is_new_req = false;
519513 cmd = mrq->cmd;
520514
521515 if (!cmd->error || !cmd->retries ||
522516 mmc_card_removed(host->card)) {
523− err = host->areq->err_check(host->card,
524− host->areq);
525− break; /* return err */
517+ status = host->areq->err_check(host->card,
518+ host->areq);
519+ break; /* return status */
526520 } else {
527521 mmc_retune_recheck(host);
528522 pr_info("%s: req failed (CMD%u): %d, retrying...\n",
@@ -534,13 +528,12 @@ static int mmc_wait_for_data_req_done(struct mmc_host *host, · 5 unmodified lines
534528 continue; /* wait for done/new event again */
535529 }
536530 } else if (context_info->is_new_req) {
537− context_info->is_new_req = false;
538531 if (!next_req)
539532 return MMC_BLK_NEW_REQUEST;
540533 }
541534 }
542535 mmc_retune_release(host);
543− return err;
536+ return status;
544537 }
545538
546539 void mmc_wait_for_req_done(struct mmc_host *host, struct mmc_request *mrq)
@@ -611,18 +604,15 @@ EXPORT_SYMBOL(mmc_is_req_done); · 64 unmodified lines
611604 * mmc_pre_req - Prepare for a new request
612605 * @host: MMC host to prepare command
613606 * @mrq: MMC request to prepare for
614− * @is_first_req: true if there is no previous started request
615− * that may run in parellel to this call, otherwise false
616607 *
617608 * mmc_pre_req() is called in prior to mmc_start_req() to let
618609 * host prepare for the new request. Preparation of a request may be
619610 * performed while another request is running on the host.
620611 */
621−static void mmc_pre_req(struct mmc_host *host, struct mmc_request *mrq,
622− bool is_first_req)
612+static void mmc_pre_req(struct mmc_host *host, struct mmc_request *mrq)
623613 {
624614 if (host->ops->pre_req)
625− host->ops->pre_req(host, mrq, is_first_req);
615+ host->ops->pre_req(host, mrq);
626616 }
627617
628618 /**
@@ -658,21 +648,22 @@ static void mmc_post_req(struct mmc_host *host, struct mmc_request *mrq, · 29 unmodified lines
658648 * is returned without waiting. NULL is not an error condition.
659649 */
660650 struct mmc_async_req *mmc_start_req(struct mmc_host *host,
661− struct mmc_async_req *areq, int *error)
651+ struct mmc_async_req *areq,
652+ enum mmc_blk_status *ret_stat)
662653 {
663− int err = 0;
654+ enum mmc_blk_status status = MMC_BLK_SUCCESS;
664655 int start_err = 0;
665656 struct mmc_async_req *data = host->areq;
666657
667658 /* Prepare a new request */
668659 if (areq)
669− mmc_pre_req(host, areq->mrq, !host->areq);
660+ mmc_pre_req(host, areq->mrq);
670661
671662 if (host->areq) {
672− err = mmc_wait_for_data_req_done(host, host->areq->mrq, areq);
673− if (err == MMC_BLK_NEW_REQUEST) {
674− if (error)
675− *error = err;
663+ status = mmc_wait_for_data_req_done(host, host->areq->mrq, areq);
664+ if (status == MMC_BLK_NEW_REQUEST) {
665+ if (ret_stat)
666+ *ret_stat = status;
676667 /*
677668 * The previous request was not completed,
678669 * nothing to return
@@ -695,27 +686,27 @@ struct mmc_async_req *mmc_start_req(struct mmc_host *host, · 16 unmodified lines
695686
696687 /* prepare the request again */
697688 if (areq)
698− mmc_pre_req(host, areq->mrq, !host->areq);
689+ mmc_pre_req(host, areq->mrq);
699690 }
700691 }
701692
702− if (!err && areq)
693+ if (status == MMC_BLK_SUCCESS && areq)
703694 start_err = __mmc_start_data_req(host, areq->mrq);
704695
705696 if (host->areq)
706697 mmc_post_req(host, host->areq->mrq, 0);
707698
708699 /* Cancel a prepared request if it was not started. */
709− if ((err || start_err) && areq)
700+ if ((status != MMC_BLK_SUCCESS || start_err) && areq)
710701 mmc_post_req(host, areq->mrq, -EINVAL);
711702
712− if (err)
703+ if (status != MMC_BLK_SUCCESS)
713704 host->areq = NULL;
714705 else
715706 host->areq = areq;
716707
717− if (error)
718− *error = err;
708+ if (ret_stat)
709+ *ret_stat = status;
719710 return data;
720711 }
721712 EXPORT_SYMBOL(mmc_start_req);
@@ -754,8 +745,6 @@ int mmc_interrupt_hpi(struct mmc_card *card) · 32 unmodified lines
754745 u32 status;
755746 unsigned long prg_wait;
756747
757− BUG_ON(!card);
758−
759748 if (!card->ext_csd.hpi_en) {
760749 pr_info("%s: HPI enable bit unset\n", mmc_hostname(card->host));
761750 return 1;
@@ -850,7 +839,6 @@ int mmc_stop_bkops(struct mmc_card *card) · 88 unmodified lines
850839 {
851840 int err = 0;
852841
853− BUG_ON(!card);
854842 err = mmc_interrupt_hpi(card);
855843
856844 /*
@@ -1666,8 +1654,6 @@ int mmc_set_signal_voltage(struct mmc_host *host, int signal_voltage, u32 ocr) · 809 unmodified lines
16661654 int err = 0;
16671655 u32 clock;
16681656
1669− BUG_ON(!host);
1670−
16711657 /*
16721658 * Send CMD11 only if the request is to switch the card to
16731659 * 1.8V signalling.
@@ -1884,9 +1870,7 @@ void mmc_power_cycle(struct mmc_host *host, u32 ocr) · 210 unmodified lines
18841870 */
18851871 static void __mmc_release_bus(struct mmc_host *host)
18861872 {
1887− BUG_ON(!host);
1888− BUG_ON(host->bus_refs);
1889− BUG_ON(!host->bus_dead);
1873+ WARN_ON(!host->bus_dead);
18901874
18911875 host->bus_ops = NULL;
18921876 }
@@ -1926,15 +1910,12 @@ void mmc_attach_bus(struct mmc_host *host, const struct mmc_bus_ops *ops) · 33 unmodified lines
19261910 {
19271911 unsigned long flags;
19281912
1929− BUG_ON(!host);
1930− BUG_ON(!ops);
1931−
19321913 WARN_ON(!host->claimed);
19331914
19341915 spin_lock_irqsave(&host->lock, flags);
19351916
1936− BUG_ON(host->bus_ops);
1937− BUG_ON(host->bus_refs);
1917+ WARN_ON(host->bus_ops);
1918+ WARN_ON(host->bus_refs);
19381919
19391920 host->bus_ops = ops;
19401921 host->bus_refs = 1;
@@ -1950,8 +1931,6 @@ void mmc_detach_bus(struct mmc_host *host) · 9 unmodified lines
19501931 {
19511932 unsigned long flags;
19521933
1953− BUG_ON(!host);
1954−
19551934 WARN_ON(!host->claimed);
19561935 WARN_ON(!host->bus_ops);
19571936
@@ -2824,12 +2803,11 @@ void mmc_start_host(struct mmc_host *host) · 866 unmodified lines
28242803 host->rescan_disable = 0;
28252804 host->ios.power_mode = MMC_POWER_UNDEFINED;
28262805
2827− mmc_claim_host(host);
2828− if (host->caps2 & MMC_CAP2_NO_PRESCAN_POWERUP)
2829− mmc_power_off(host);
2830− else
2806+ if (!(host->caps2 & MMC_CAP2_NO_PRESCAN_POWERUP)) {
2807+ mmc_claim_host(host);
28312808 mmc_power_up(host, host->ocr_avail);
2832− mmc_release_host(host);
2809+ mmc_release_host(host);
2810+ }
28332811
28342812 mmc_gpiod_request_cd_irq(host);
28352813 _mmc_detect_change(host, 0, false);
@@ -2865,8 +2843,6 @@ void mmc_stop_host(struct mmc_host *host) · 29 unmodified lines
28652843 }
28662844 mmc_bus_put(host);
28672845
2868− BUG_ON(host->card);
2869−
28702846 mmc_claim_host(host);
28712847 mmc_power_off(host);
28722848 mmc_release_host(host);
@@ -3019,7 +2995,6 @@ void mmc_unregister_pm_notifier(struct mmc_host *host) · 146 unmodified lines
30192995 */
30202996 void mmc_init_context_info(struct mmc_host *host)
30212997 {
3022− spin_lock_init(&host->context_info.lock);
30232998 host->context_info.is_new_req = false;
30242999 host->context_info.is_done_rcv = false;
30253000 host->context_info.is_waiting_last_req = false;
drivers/mmc/core/debugfs.c+5−1
@@ -321,7 +321,11 @@ static int mmc_ext_csd_open(struct inode *inode, struct file *filp) · 320 unmodified lines
321321 for (i = 0; i < 512; i++)
322322 n += sprintf(buf + n, "%02x", ext_csd[i]);
323323 n += sprintf(buf + n, "\n");
324− BUG_ON(n != EXT_CSD_STR_LEN);
324+
325+ if (n != EXT_CSD_STR_LEN) {
326+ err = -EINVAL;
327+ goto out_free;
328+ }
325329
326330 filp->private_data = buf;
327331 kfree(ext_csd);
drivers/mmc/core/mmc.c+58−55
@@ -618,6 +618,24 @@ static int mmc_decode_ext_csd(struct mmc_card *card, u8 *ext_csd) · 617 unmodified lines
618618 (ext_csd[EXT_CSD_SUPPORTED_MODE] & 0x1) &&
619619 !(ext_csd[EXT_CSD_FW_CONFIG] & 0x1);
620620 }
621+
622+ /* eMMC v5.1 or later */
623+ if (card->ext_csd.rev >= 8) {
624+ card->ext_csd.cmdq_support = ext_csd[EXT_CSD_CMDQ_SUPPORT] &
625+ EXT_CSD_CMDQ_SUPPORTED;
626+ card->ext_csd.cmdq_depth = (ext_csd[EXT_CSD_CMDQ_DEPTH] &
627+ EXT_CSD_CMDQ_DEPTH_MASK) + 1;
628+ /* Exclude inefficiently small queue depths */
629+ if (card->ext_csd.cmdq_depth <= 2) {
630+ card->ext_csd.cmdq_support = false;
631+ card->ext_csd.cmdq_depth = 0;
632+ }
633+ if (card->ext_csd.cmdq_support) {
634+ pr_debug("%s: Command Queue supported depth %u\n",
635+ mmc_hostname(card->host),
636+ card->ext_csd.cmdq_depth);
637+ }
638+ }
621639 out:
622640 return err;
623641 }
@@ -1003,19 +1021,6 @@ static int mmc_select_bus_width(struct mmc_card *card) · 379 unmodified lines
10031021 return err;
10041022 }
10051023
1006−/* Caller must hold re-tuning */
1007−static int mmc_switch_status(struct mmc_card *card)
1008−{
1009− u32 status;
1010− int err;
1011−
1012− err = mmc_send_status(card, &status);
1013− if (err)
1014− return err;
1015−
1016− return mmc_switch_status_error(card->host, status);
1017−}
1018−
10191024 /*
10201025 * Switch to the high-speed mode
10211026 */
@@ -1025,13 +1030,8 @@ static int mmc_select_hs(struct mmc_card *card) · 3 unmodified lines
10251030
10261031 err = __mmc_switch(card, EXT_CSD_CMD_SET_NORMAL,
10271032 EXT_CSD_HS_TIMING, EXT_CSD_TIMING_HS,
1028− card->ext_csd.generic_cmd6_time,
1029− true, false, true);
1030− if (!err) {
1031− mmc_set_timing(card->host, MMC_TIMING_MMC_HS);
1032− err = mmc_switch_status(card);
1033− }
1034−
1033+ card->ext_csd.generic_cmd6_time, MMC_TIMING_MMC_HS,
1034+ true, true, true);
10351035 if (err)
10361036 pr_warn("%s: switch to high-speed failed, err:%d\n",
10371037 mmc_hostname(card->host), err);
@@ -1058,10 +1058,12 @@ static int mmc_select_hs_ddr(struct mmc_card *card) · 20 unmodified lines
10581058 ext_csd_bits = (bus_width == MMC_BUS_WIDTH_8) ?
10591059 EXT_CSD_DDR_BUS_WIDTH_8 : EXT_CSD_DDR_BUS_WIDTH_4;
10601060
1061− err = mmc_switch(card, EXT_CSD_CMD_SET_NORMAL,
1062− EXT_CSD_BUS_WIDTH,
1063− ext_csd_bits,
1064− card->ext_csd.generic_cmd6_time);
1061+ err = __mmc_switch(card, EXT_CSD_CMD_SET_NORMAL,
1062+ EXT_CSD_BUS_WIDTH,
1063+ ext_csd_bits,
1064+ card->ext_csd.generic_cmd6_time,
1065+ MMC_TIMING_MMC_DDR52,
1066+ true, true, true);
10651067 if (err) {
10661068 pr_err("%s: switch to bus width %d ddr failed\n",
10671069 mmc_hostname(host), 1 << bus_width);
@@ -1104,9 +1106,6 @@ static int mmc_select_hs_ddr(struct mmc_card *card) · 36 unmodified lines
11041106 if (err)
11051107 err = __mmc_set_signal_voltage(host, MMC_SIGNAL_VOLTAGE_330);
11061108
1107− if (!err)
1108− mmc_set_timing(host, MMC_TIMING_MMC_DDR52);
1109−
11101109 return err;
11111110 }
11121111
@@ -1128,7 +1127,7 @@ static int mmc_select_hs400(struct mmc_card *card) · 15 unmodified lines
11281127 val = EXT_CSD_TIMING_HS;
11291128 err = __mmc_switch(card, EXT_CSD_CMD_SET_NORMAL,
11301129 EXT_CSD_HS_TIMING, val,
1131− card->ext_csd.generic_cmd6_time,
1130+ card->ext_csd.generic_cmd6_time, 0,
11321131 true, false, true);
11331132 if (err) {
11341133 pr_err("%s: switch to high-speed from hs200 failed, err:%d\n",
@@ -1163,7 +1162,7 @@ static int mmc_select_hs400(struct mmc_card *card) · 28 unmodified lines
11631162 card->drive_strength << EXT_CSD_DRV_STR_SHIFT;
11641163 err = __mmc_switch(card, EXT_CSD_CMD_SET_NORMAL,
11651164 EXT_CSD_HS_TIMING, val,
1166− card->ext_csd.generic_cmd6_time,
1165+ card->ext_csd.generic_cmd6_time, 0,
11671166 true, false, true);
11681167 if (err) {
11691168 pr_err("%s: switch to hs400 failed, err:%d\n",
@@ -1206,7 +1205,7 @@ int mmc_hs400_to_hs200(struct mmc_card *card) · 36 unmodified lines
12061205 /* Switch HS400 to HS DDR */
12071206 val = EXT_CSD_TIMING_HS;
12081207 err = __mmc_switch(card, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING,
1209− val, card->ext_csd.generic_cmd6_time,
1208+ val, card->ext_csd.generic_cmd6_time, 0,
12101209 true, false, true);
12111210 if (err)
12121211 goto out_err;
@@ -1220,7 +1219,7 @@ int mmc_hs400_to_hs200(struct mmc_card *card) · 7 unmodified lines
12201219 /* Switch HS DDR to HS */
12211220 err = __mmc_switch(card, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BUS_WIDTH,
12221221 EXT_CSD_BUS_WIDTH_8, card->ext_csd.generic_cmd6_time,
1223− true, false, true);
1222+ 0, true, false, true);
12241223 if (err)
12251224 goto out_err;
12261225
@@ -1234,14 +1233,19 @@ int mmc_hs400_to_hs200(struct mmc_card *card) · 7 unmodified lines
12341233 val = EXT_CSD_TIMING_HS200 |
12351234 card->drive_strength << EXT_CSD_DRV_STR_SHIFT;
12361235 err = __mmc_switch(card, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING,
1237− val, card->ext_csd.generic_cmd6_time,
1236+ val, card->ext_csd.generic_cmd6_time, 0,
12381237 true, false, true);
12391238 if (err)
12401239 goto out_err;
12411240
12421241 mmc_set_timing(host, MMC_TIMING_MMC_HS200);
12431242
1244− err = mmc_switch_status(card);
1243+ /*
1244+ * For HS200, CRC errors are not a reliable way to know the switch
1245+ * failed. If there really is a problem, we would expect tuning will
1246+ * fail and the result ends up the same.
1247+ */
1248+ err = __mmc_switch_status(card, false);
12451249 if (err)
12461250 goto out_err;
12471251
@@ -1281,16 +1285,23 @@ static int mmc_select_hs400es(struct mmc_card *card) · 33 unmodified lines
12811285 goto out_err;
12821286
12831287 /* Switch card to HS mode */
1284− err = mmc_select_hs(card);
1285− if (err)
1288+ err = __mmc_switch(card, EXT_CSD_CMD_SET_NORMAL,
1289+ EXT_CSD_HS_TIMING, EXT_CSD_TIMING_HS,
1290+ card->ext_csd.generic_cmd6_time, 0,
1291+ true, false, true);
1292+ if (err) {
1293+ pr_err("%s: switch to hs for hs400es failed, err:%d\n",
1294+ mmc_hostname(host), err);
12861295 goto out_err;
1296+ }
12871297
1288− mmc_set_clock(host, card->ext_csd.hs_max_dtr);
1289−
1298+ mmc_set_timing(host, MMC_TIMING_MMC_HS);
12901299 err = mmc_switch_status(card);
12911300 if (err)
12921301 goto out_err;
12931302
1303+ mmc_set_clock(host, card->ext_csd.hs_max_dtr);
1304+
12941305 /* Switch card to DDR with strobe bit */
12951306 val = EXT_CSD_DDR_BUS_WIDTH_8 | EXT_CSD_BUS_WIDTH_STROBE;
12961307 err = mmc_switch(card, EXT_CSD_CMD_SET_NORMAL,
@@ -1308,7 +1319,7 @@ static int mmc_select_hs400es(struct mmc_card *card) · 11 unmodified lines
13081319 card->drive_strength << EXT_CSD_DRV_STR_SHIFT;
13091320 err = __mmc_switch(card, EXT_CSD_CMD_SET_NORMAL,
13101321 EXT_CSD_HS_TIMING, val,
1311− card->ext_csd.generic_cmd6_time,
1322+ card->ext_csd.generic_cmd6_time, 0,
13121323 true, false, true);
13131324 if (err) {
13141325 pr_err("%s: switch to hs400es failed, err:%d\n",
@@ -1390,14 +1401,20 @@ static int mmc_select_hs200(struct mmc_card *card) · 75 unmodified lines
13901401 card->drive_strength << EXT_CSD_DRV_STR_SHIFT;
13911402 err = __mmc_switch(card, EXT_CSD_CMD_SET_NORMAL,
13921403 EXT_CSD_HS_TIMING, val,
1393− card->ext_csd.generic_cmd6_time,
1404+ card->ext_csd.generic_cmd6_time, 0,
13941405 true, false, true);
13951406 if (err)
13961407 goto err;
13971408 old_timing = host->ios.timing;
13981409 mmc_set_timing(host, MMC_TIMING_MMC_HS200);
13991410
1400− err = mmc_switch_status(card);
1411+ /*
1412+ * For HS200, CRC errors are not a reliable way to know the
1413+ * switch failed. If there really is a problem, we would expect
1414+ * tuning will fail and the result ends up the same.
1415+ */
1416+ err = __mmc_switch_status(card, false);
1417+
14011418 /*
14021419 * mmc_select_timing() assumes timing has not changed if
14031420 * it is a switch error.
@@ -1480,7 +1497,6 @@ static int mmc_init_card(struct mmc_host *host, u32 ocr, · 76 unmodified lines
14801497 u32 cid[4];
14811498 u32 rocr;
14821499
1483− BUG_ON(!host);
14841500 WARN_ON(!host->claimed);
14851501
14861502 /* Set correct bus mode for MMC before attempting init */
@@ -1854,7 +1870,7 @@ static int mmc_poweroff_notify(struct mmc_card *card, unsigned int notify_type) · 367 unmodified lines
18541870
18551871 err = __mmc_switch(card, EXT_CSD_CMD_SET_NORMAL,
18561872 EXT_CSD_POWER_OFF_NOTIFICATION,
1857− notify_type, timeout, true, false, false);
1873+ notify_type, timeout, 0, true, false, false);
18581874 if (err)
18591875 pr_err("%s: Power Off Notification timed out, %u\n",
18601876 mmc_hostname(card->host), timeout);
@@ -1870,9 +1886,6 @@ static int mmc_poweroff_notify(struct mmc_card *card, unsigned int notify_type) · 9 unmodified lines
18701886 */
18711887 static void mmc_remove(struct mmc_host *host)
18721888 {
1873− BUG_ON(!host);
1874− BUG_ON(!host->card);
1875−
18761889 mmc_remove_card(host->card);
18771890 host->card = NULL;
18781891 }
@@ -1892,9 +1905,6 @@ static void mmc_detect(struct mmc_host *host) · 13 unmodified lines
18921905 {
18931906 int err;
18941907
1895− BUG_ON(!host);
1896− BUG_ON(!host->card);
1897−
18981908 mmc_get_card(host->card);
18991909
19001910 /*
@@ -1920,9 +1930,6 @@ static int _mmc_suspend(struct mmc_host *host, bool is_suspend) · 19 unmodified lines
19201930 unsigned int notify_type = is_suspend ? EXT_CSD_POWER_OFF_SHORT :
19211931 EXT_CSD_POWER_OFF_LONG;
19221932
1923− BUG_ON(!host);
1924− BUG_ON(!host->card);
1925−
19261933 mmc_claim_host(host);
19271934
19281935 if (mmc_card_suspended(host->card))
@@ -1979,9 +1986,6 @@ static int _mmc_resume(struct mmc_host *host) · 50 unmodified lines
19791986 {
19801987 int err = 0;
19811988
1982− BUG_ON(!host);
1983− BUG_ON(!host->card);
1984−
19851989 mmc_claim_host(host);
19861990
19871991 if (!mmc_card_suspended(host->card))
@@ -2114,7 +2118,6 @@ int mmc_attach_mmc(struct mmc_host *host) · 126 unmodified lines
21142118 int err;
21152119 u32 ocr, rocr;
21162120
2117− BUG_ON(!host);
21182121 WARN_ON(!host->claimed);
21192122
21202123 /* Set correct bus mode for MMC before attempting attach */
drivers/mmc/core/mmc_ops.c+131−89
@@ -54,21 +54,15 @@ static const u8 tuning_blk_pattern_8bit[] = { · 53 unmodified lines
5454 0xff, 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee,
5555 };
5656
57−static inline int __mmc_send_status(struct mmc_card *card, u32 *status,
58− bool ignore_crc)
57+int mmc_send_status(struct mmc_card *card, u32 *status)
5958 {
6059 int err;
6160 struct mmc_command cmd = {0};
6261
63− BUG_ON(!card);
64− BUG_ON(!card->host);
65−
6662 cmd.opcode = MMC_SEND_STATUS;
6763 if (!mmc_host_is_spi(card->host))
6864 cmd.arg = card->rca << 16;
6965 cmd.flags = MMC_RSP_SPI_R2 | MMC_RSP_R1 | MMC_CMD_AC;
70− if (ignore_crc)
71− cmd.flags &= ~MMC_RSP_CRC;
7266
7367 err = mmc_wait_for_cmd(card->host, &cmd, MMC_CMD_RETRIES);
7468 if (err)
@@ -83,17 +77,10 @@ static inline int __mmc_send_status(struct mmc_card *card, u32 *status, · 8 unmodified lines
8377 return 0;
8478 }
8579
86−int mmc_send_status(struct mmc_card *card, u32 *status)
87−{
88− return __mmc_send_status(card, status, false);
89−}
90−
9180 static int _mmc_select_card(struct mmc_host *host, struct mmc_card *card)
9281 {
9382 struct mmc_command cmd = {0};
9483
95− BUG_ON(!host);
96−
9784 cmd.opcode = MMC_SELECT_CARD;
9885
9986 if (card) {
@@ -109,7 +96,6 @@ static int _mmc_select_card(struct mmc_host *host, struct mmc_card *card) · 9 unmodified lines
10996
11097 int mmc_select_card(struct mmc_card *card)
11198 {
112− BUG_ON(!card);
11399
114100 return _mmc_select_card(card->host, card);
115101 }
@@ -181,8 +167,6 @@ int mmc_send_op_cond(struct mmc_host *host, u32 ocr, u32 *rocr) · 65 unmodified lines
181167 struct mmc_command cmd = {0};
182168 int i, err = 0;
183169
184− BUG_ON(!host);
185−
186170 cmd.opcode = MMC_SEND_OP_COND;
187171 cmd.arg = mmc_host_is_spi(host) ? 0 : ocr;
188172 cmd.flags = MMC_RSP_SPI_R1 | MMC_RSP_R3 | MMC_CMD_BCR;
@@ -221,9 +205,6 @@ int mmc_all_send_cid(struct mmc_host *host, u32 *cid) · 32 unmodified lines
221205 int err;
222206 struct mmc_command cmd = {0};
223207
224− BUG_ON(!host);
225− BUG_ON(!cid);
226−
227208 cmd.opcode = MMC_ALL_SEND_CID;
228209 cmd.arg = 0;
229210 cmd.flags = MMC_RSP_R2 | MMC_CMD_BCR;
@@ -241,9 +222,6 @@ int mmc_set_relative_addr(struct mmc_card *card) · 11 unmodified lines
241222 {
242223 struct mmc_command cmd = {0};
243224
244− BUG_ON(!card);
245− BUG_ON(!card->host);
246−
247225 cmd.opcode = MMC_SET_RELATIVE_ADDR;
248226 cmd.arg = card->rca << 16;
249227 cmd.flags = MMC_RSP_R1 | MMC_CMD_AC;
@@ -257,9 +235,6 @@ mmc_send_cxd_native(struct mmc_host *host, u32 arg, u32 *cxd, int opcode) · 7 unmodified lines
257235 int err;
258236 struct mmc_command cmd = {0};
259237
260− BUG_ON(!host);
261− BUG_ON(!cxd);
262−
263238 cmd.opcode = opcode;
264239 cmd.arg = arg;
265240 cmd.flags = MMC_RSP_R2 | MMC_CMD_AC;
@@ -440,7 +415,7 @@ int mmc_spi_set_crc(struct mmc_host *host, int use_crc) · 174 unmodified lines
440415 return err;
441416 }
442417
443−int mmc_switch_status_error(struct mmc_host *host, u32 status)
418+static int mmc_switch_status_error(struct mmc_host *host, u32 status)
444419 {
445420 if (mmc_host_is_spi(host)) {
446421 if (status & R1_SPI_ILLEGAL_COMMAND)
@@ -455,6 +430,88 @@ int mmc_switch_status_error(struct mmc_host *host, u32 status) · 8 unmodified lines
455430 return 0;
456431 }
457432
433+/* Caller must hold re-tuning */
434+int __mmc_switch_status(struct mmc_card *card, bool crc_err_fatal)
435+{
436+ u32 status;
437+ int err;
438+
439+ err = mmc_send_status(card, &status);
440+ if (!crc_err_fatal && err == -EILSEQ)
441+ return 0;
442+ if (err)
443+ return err;
444+
445+ return mmc_switch_status_error(card->host, status);
446+}
447+
448+int mmc_switch_status(struct mmc_card *card)
449+{
450+ return __mmc_switch_status(card, true);
451+}
452+
453+static int mmc_poll_for_busy(struct mmc_card *card, unsigned int timeout_ms,
454+ bool send_status, bool retry_crc_err)
455+{
456+ struct mmc_host *host = card->host;
457+ int err;
458+ unsigned long timeout;
459+ u32 status = 0;
460+ bool expired = false;
461+ bool busy = false;
462+
463+ /* We have an unspecified cmd timeout, use the fallback value. */
464+ if (!timeout_ms)
465+ timeout_ms = MMC_OPS_TIMEOUT_MS;
466+
467+ /*
468+ * In cases when not allowed to poll by using CMD13 or because we aren't
469+ * capable of polling by using ->card_busy(), then rely on waiting the
470+ * stated timeout to be sufficient.
471+ */
472+ if (!send_status && !host->ops->card_busy) {
473+ mmc_delay(timeout_ms);
474+ return 0;
475+ }
476+
477+ timeout = jiffies + msecs_to_jiffies(timeout_ms) + 1;
478+ do {
479+ /*
480+ * Due to the possibility of being preempted while polling,
481+ * check the expiration time first.
482+ */
483+ expired = time_after(jiffies, timeout);
484+
485+ if (host->ops->card_busy) {
486+ busy = host->ops->card_busy(host);
487+ } else {
488+ err = mmc_send_status(card, &status);
489+ if (retry_crc_err && err == -EILSEQ) {
490+ busy = true;
491+ } else if (err) {
492+ return err;
493+ } else {
494+ err = mmc_switch_status_error(host, status);
495+ if (err)
496+ return err;
497+ busy = R1_CURRENT_STATE(status) == R1_STATE_PRG;
498+ }
499+ }
500+
501+ /* Timeout if the device still remains busy. */
502+ if (expired && busy) {
503+ pr_err("%s: Card stuck being busy! %s\n",
504+ mmc_hostname(host), __func__);
505+ return -ETIMEDOUT;
506+ }
507+ } while (busy);
508+
509+ if (host->ops->card_busy && send_status)
510+ return mmc_switch_status(card);
511+
512+ return 0;
513+}
514+
458515 /**
459516 * __mmc_switch - modify EXT_CSD register
460517 * @card: the MMC card associated with the data transfer
@@ -463,24 +520,22 @@ int mmc_switch_status_error(struct mmc_host *host, u32 status) · 2 unmodified lines
463520 * @value: value to program into EXT_CSD register
464521 * @timeout_ms: timeout (ms) for operation performed by register write,
465522 * timeout of zero implies maximum possible timeout
523+ * @timing: new timing to change to
466524 * @use_busy_signal: use the busy signal as response type
467525 * @send_status: send status cmd to poll for busy
468− * @ignore_crc: ignore CRC errors when sending status cmd to poll for busy
526+ * @retry_crc_err: retry when CRC errors when polling with CMD13 for busy
469527 *
470528 * Modifies the EXT_CSD register for selected card.
471529 */
472530 int __mmc_switch(struct mmc_card *card, u8 set, u8 index, u8 value,
473− unsigned int timeout_ms, bool use_busy_signal, bool send_status,
474− bool ignore_crc)
531+ unsigned int timeout_ms, unsigned char timing,
532+ bool use_busy_signal, bool send_status, bool retry_crc_err)
475533 {
476534 struct mmc_host *host = card->host;
477535 int err;
478536 struct mmc_command cmd = {0};
479− unsigned long timeout;
480− u32 status = 0;
481537 bool use_r1b_resp = use_busy_signal;
482− bool expired = false;
483− bool busy = false;
538+ unsigned char old_timing = host->ios.timing;
484539
485540 mmc_retune_hold(host);
486541
@@ -522,62 +577,24 @@ int __mmc_switch(struct mmc_card *card, u8 set, u8 index, u8 value, · 35 unmodified lines
522577 if (!use_busy_signal)
523578 goto out;
524579
525− /*
526− * CRC errors shall only be ignored in cases were CMD13 is used to poll
527− * to detect busy completion.
528− */
529− if ((host->caps & MMC_CAP_WAIT_WHILE_BUSY) && use_r1b_resp)
530− ignore_crc = false;
531−
532− /* We have an unspecified cmd timeout, use the fallback value. */
533− if (!timeout_ms)
534− timeout_ms = MMC_OPS_TIMEOUT_MS;
535−
536− /* Must check status to be sure of no errors. */
537− timeout = jiffies + msecs_to_jiffies(timeout_ms) + 1;
538− do {
539− /*
540− * Due to the possibility of being preempted after
541− * sending the status command, check the expiration
542− * time first.
543− */
544− expired = time_after(jiffies, timeout);
545− if (send_status) {
546− err = __mmc_send_status(card, &status, ignore_crc);
547− if (err)
548− goto out;
549− }
550− if ((host->caps & MMC_CAP_WAIT_WHILE_BUSY) && use_r1b_resp)
551− break;
552− if (host->ops->card_busy) {
553− if (!host->ops->card_busy(host))
554− break;
555− busy = true;
556− }
557− if (mmc_host_is_spi(host))
558− break;
580+ /* Switch to new timing before poll and check switch status. */
581+ if (timing)
582+ mmc_set_timing(host, timing);
559583
560− /*
561− * We are not allowed to issue a status command and the host
562− * does'nt support MMC_CAP_WAIT_WHILE_BUSY, then we can only
563− * rely on waiting for the stated timeout to be sufficient.
564− */
565− if (!send_status && !host->ops->card_busy) {
566− mmc_delay(timeout_ms);
567− goto out;
568− }
584+ /*If SPI or used HW busy detection above, then we don't need to poll. */
585+ if (((host->caps & MMC_CAP_WAIT_WHILE_BUSY) && use_r1b_resp) ||
586+ mmc_host_is_spi(host)) {
587+ if (send_status)
588+ err = mmc_switch_status(card);
589+ goto out_tim;
590+ }
569591
570− /* Timeout if the device never leaves the program state. */
571− if (expired &&
572− (R1_CURRENT_STATE(status) == R1_STATE_PRG || busy)) {
573− pr_err("%s: Card stuck in programming state! %s\n",
574− mmc_hostname(host), __func__);
575− err = -ETIMEDOUT;
576− goto out;
577− }
578− } while (R1_CURRENT_STATE(status) == R1_STATE_PRG || busy);
592+ /* Let's try to poll to find out when the command is completed. */
593+ err = mmc_poll_for_busy(card, timeout_ms, send_status, retry_crc_err);
579594
580− err = mmc_switch_status_error(host, status);
595+out_tim:
596+ if (err && timing)
597+ mmc_set_timing(host, old_timing);
581598 out:
582599 mmc_retune_release(host);
583600
@@ -587,8 +604,8 @@ out: · 3 unmodified lines
587604 int mmc_switch(struct mmc_card *card, u8 set, u8 index, u8 value,
588605 unsigned int timeout_ms)
589606 {
590− return __mmc_switch(card, set, index, value, timeout_ms, true, true,
591− false);
607+ return __mmc_switch(card, set, index, value, timeout_ms, 0,
608+ true, true, false);
592609 }
593610 EXPORT_SYMBOL_GPL(mmc_switch);
594611
@@ -661,6 +678,31 @@ out: · 66 unmodified lines
661678 }
662679 EXPORT_SYMBOL_GPL(mmc_send_tuning);
663680
681+int mmc_abort_tuning(struct mmc_host *host, u32 opcode)
682+{
683+ struct mmc_command cmd = {0};
684+
685+ /*
686+ * eMMC specification specifies that CMD12 can be used to stop a tuning
687+ * command, but SD specification does not, so do nothing unless it is
688+ * eMMC.
689+ */
690+ if (opcode != MMC_SEND_TUNING_BLOCK_HS200)
691+ return 0;
692+
693+ cmd.opcode = MMC_STOP_TRANSMISSION;
694+ cmd.flags = MMC_RSP_SPI_R1 | MMC_RSP_R1 | MMC_CMD_AC;
695+
696+ /*
697+ * For drivers that override R1 to R1b, set an arbitrary timeout based
698+ * on the tuning timeout i.e. 150ms.
699+ */
700+ cmd.busy_timeout = 150;
701+
702+ return mmc_wait_for_cmd(host, &cmd, 0);
703+}
704+EXPORT_SYMBOL_GPL(mmc_abort_tuning);
705+
664706 static int
665707 mmc_send_bus_test(struct mmc_card *card, struct mmc_host *host, u8 opcode,
666708 u8 len)
drivers/mmc/core/mmc_ops.h+4−3
@@ -27,10 +27,11 @@ int mmc_spi_set_crc(struct mmc_host *host, int use_crc); · 26 unmodified lines
2727 int mmc_bus_test(struct mmc_card *card, u8 bus_width);
2828 int mmc_send_hpi_cmd(struct mmc_card *card, u32 *status);
2929 int mmc_can_ext_csd(struct mmc_card *card);
30−int mmc_switch_status_error(struct mmc_host *host, u32 status);
30+int mmc_switch_status(struct mmc_card *card);
31+int __mmc_switch_status(struct mmc_card *card, bool crc_err_fatal);
3132 int __mmc_switch(struct mmc_card *card, u8 set, u8 index, u8 value,
32− unsigned int timeout_ms, bool use_busy_signal, bool send_status,
33− bool ignore_crc);
33+ unsigned int timeout_ms, unsigned char timing,
34+ bool use_busy_signal, bool send_status, bool retry_crc_err);
3435
3536 #endif
3637
drivers/mmc/core/sd.c+0−14
@@ -927,7 +927,6 @@ static int mmc_sd_init_card(struct mmc_host *host, u32 ocr, · 926 unmodified lines
927927 u32 cid[4];
928928 u32 rocr = 0;
929929
930− BUG_ON(!host);
931930 WARN_ON(!host->claimed);
932931
933932 err = mmc_sd_get_cid(host, ocr, cid, &rocr);
@@ -1043,9 +1042,6 @@ free_card: · 109 unmodified lines
10431042 */
10441043 static void mmc_sd_remove(struct mmc_host *host)
10451044 {
1046− BUG_ON(!host);
1047− BUG_ON(!host->card);
1048−
10491045 mmc_remove_card(host->card);
10501046 host->card = NULL;
10511047 }
@@ -1065,9 +1061,6 @@ static void mmc_sd_detect(struct mmc_host *host) · 13 unmodified lines
10651061 {
10661062 int err;
10671063
1068− BUG_ON(!host);
1069− BUG_ON(!host->card);
1070−
10711064 mmc_get_card(host->card);
10721065
10731066 /*
@@ -1091,9 +1084,6 @@ static int _mmc_sd_suspend(struct mmc_host *host) · 17 unmodified lines
10911084 {
10921085 int err = 0;
10931086
1094− BUG_ON(!host);
1095− BUG_ON(!host->card);
1096−
10971087 mmc_claim_host(host);
10981088
10991089 if (mmc_card_suspended(host->card))
@@ -1136,9 +1126,6 @@ static int _mmc_sd_resume(struct mmc_host *host) · 36 unmodified lines
11361126 {
11371127 int err = 0;
11381128
1139− BUG_ON(!host);
1140− BUG_ON(!host->card);
1141−
11421129 mmc_claim_host(host);
11431130
11441131 if (!mmc_card_suspended(host->card))
@@ -1221,7 +1208,6 @@ int mmc_attach_sd(struct mmc_host *host) · 76 unmodified lines
12211208 int err;
12221209 u32 ocr, rocr;
12231210
1224− BUG_ON(!host);
12251211 WARN_ON(!host->claimed);
12261212
12271213 err = mmc_send_app_op_cond(host, 0, &ocr);
drivers/mmc/core/sd_ops.c+4−23
@@ -27,8 +27,8 @@ int mmc_app_cmd(struct mmc_host *host, struct mmc_card *card) · 26 unmodified lines
2727 int err;
2828 struct mmc_command cmd = {0};
2929
30− BUG_ON(!host);
31− BUG_ON(card && (card->host != host));
30+ if (WARN_ON(card && card->host != host))
31+ return -EINVAL;
3232
3333 cmd.opcode = MMC_APP_CMD;
3434
@@ -72,8 +72,8 @@ int mmc_wait_for_app_cmd(struct mmc_host *host, struct mmc_card *card, · 37 unmodified lines
7272
7373 int i, err;
7474
75− BUG_ON(!cmd);
76− BUG_ON(retries < 0);
75+ if (retries < 0)
76+ retries = MMC_CMD_RETRIES;
7777
7878 err = -EIO;
7979
@@ -122,9 +122,6 @@ int mmc_app_set_bus_width(struct mmc_card *card, int width) · 42 unmodified lines
122122 {
123123 struct mmc_command cmd = {0};
124124
125− BUG_ON(!card);
126− BUG_ON(!card->host);
127−
128125 cmd.opcode = SD_APP_SET_BUS_WIDTH;
129126 cmd.flags = MMC_RSP_R1 | MMC_CMD_AC;
130127
@@ -147,8 +144,6 @@ int mmc_send_app_op_cond(struct mmc_host *host, u32 ocr, u32 *rocr) · 16 unmodified lines
147144 struct mmc_command cmd = {0};
148145 int i, err = 0;
149146
150− BUG_ON(!host);
151−
152147 cmd.opcode = SD_APP_OP_COND;
153148 if (mmc_host_is_spi(host))
154149 cmd.arg = ocr & (1 << 30); /* SPI only defines one bit */
@@ -224,9 +219,6 @@ int mmc_send_relative_addr(struct mmc_host *host, unsigned int *rca) · 69 unmodified lines
224219 int err;
225220 struct mmc_command cmd = {0};
226221
227− BUG_ON(!host);
228− BUG_ON(!rca);
229−
230222 cmd.opcode = SD_SEND_RELATIVE_ADDR;
231223 cmd.arg = 0;
232224 cmd.flags = MMC_RSP_R6 | MMC_CMD_BCR;
@@ -249,10 +241,6 @@ int mmc_app_send_scr(struct mmc_card *card, u32 *scr) · 16 unmodified lines
249241 struct scatterlist sg;
250242 void *data_buf;
251243
252− BUG_ON(!card);
253− BUG_ON(!card->host);
254− BUG_ON(!scr);
255−
256244 /* NOTE: caller guarantees scr is heap-allocated */
257245
258246 err = mmc_app_cmd(card->host, card);
@@ -307,9 +295,6 @@ int mmc_sd_switch(struct mmc_card *card, int mode, int group, · 48 unmodified lines
307295 struct mmc_data data = {0};
308296 struct scatterlist sg;
309297
310− BUG_ON(!card);
311− BUG_ON(!card->host);
312−
313298 /* NOTE: caller guarantees resp is heap-allocated */
314299
315300 mode = !!mode;
@@ -352,10 +337,6 @@ int mmc_app_sd_status(struct mmc_card *card, void *ssr) · 36 unmodified lines
352337 struct mmc_data data = {0};
353338 struct scatterlist sg;
354339
355− BUG_ON(!card);
356− BUG_ON(!card->host);
357− BUG_ON(!ssr);
358−
359340 /* NOTE: caller guarantees ssr is heap-allocated */
360341
361342 err = mmc_app_cmd(card->host, card);
drivers/mmc/core/sdio.c+2−15
@@ -63,7 +63,8 @@ static int sdio_init_func(struct mmc_card *card, unsigned int fn) · 62 unmodified lines
6363 int ret;
6464 struct sdio_func *func;
6565
66− BUG_ON(fn > SDIO_MAX_FUNCS);
66+ if (WARN_ON(fn > SDIO_MAX_FUNCS))
67+ return -EINVAL;
6768
6869 func = sdio_alloc_func(card);
6970 if (IS_ERR(func))
@@ -555,7 +556,6 @@ static int mmc_sdio_init_card(struct mmc_host *host, u32 ocr, · 485 unmodified lines
555556 u32 rocr = 0;
556557 u32 ocr_card = ocr;
557558
558− BUG_ON(!host);
559559 WARN_ON(!host->claimed);
560560
561561 /* to query card if 1.8V signalling is supported */
@@ -791,9 +791,6 @@ static void mmc_sdio_remove(struct mmc_host *host) · 229 unmodified lines
791791 {
792792 int i;
793793
794− BUG_ON(!host);
795− BUG_ON(!host->card);
796−
797794 for (i = 0;i < host->card->sdio_funcs;i++) {
798795 if (host->card->sdio_func[i]) {
799796 sdio_remove_func(host->card->sdio_func[i]);
@@ -820,9 +817,6 @@ static void mmc_sdio_detect(struct mmc_host *host) · 20 unmodified lines
820817 {
821818 int err;
822819
823− BUG_ON(!host);
824− BUG_ON(!host->card);
825−
826820 /* Make sure card is powered before detecting it */
827821 if (host->caps & MMC_CAP_POWER_OFF_CARD) {
828822 err = pm_runtime_get_sync(&host->card->dev);
@@ -916,9 +910,6 @@ static int mmc_sdio_resume(struct mmc_host *host) · 87 unmodified lines
916910 {
917911 int err = 0;
918912
919− BUG_ON(!host);
920− BUG_ON(!host->card);
921−
922913 /* Basic card reinitialization. */
923914 mmc_claim_host(host);
924915
@@ -970,9 +961,6 @@ static int mmc_sdio_power_restore(struct mmc_host *host) · 45 unmodified lines
970961 {
971962 int ret;
972963
973− BUG_ON(!host);
974− BUG_ON(!host->card);
975−
976964 mmc_claim_host(host);
977965
978966 /*
@@ -1063,7 +1051,6 @@ int mmc_attach_sdio(struct mmc_host *host) · 84 unmodified lines
10631051 u32 ocr, rocr;
10641052 struct mmc_card *card;
10651053
1066− BUG_ON(!host);
10671054 WARN_ON(!host->claimed);
10681055
10691056 err = mmc_send_io_op_cond(host, 0, &ocr);
drivers/mmc/core/sdio_cis.c+2−1
@@ -262,7 +262,8 @@ static int sdio_read_cis(struct mmc_card *card, struct sdio_func *func) · 261 unmodified lines
262262 else
263263 prev = &card->tuples;
264264
265− BUG_ON(*prev);
265+ if (*prev)
266+ return -EINVAL;
266267
267268 do {
268269 unsigned char tpl_code, tpl_link;
drivers/mmc/core/sdio_irq.c+7−5
@@ -214,7 +214,9 @@ static int sdio_card_irq_put(struct mmc_card *card) · 213 unmodified lines
214214 struct mmc_host *host = card->host;
215215
216216 WARN_ON(!host->claimed);
217− BUG_ON(host->sdio_irqs < 1);
217+
218+ if (host->sdio_irqs < 1)
219+ return -EINVAL;
218220
219221 if (!--host->sdio_irqs) {
220222 if (!(host->caps2 & MMC_CAP2_SDIO_IRQ_NOTHREAD)) {
@@ -261,8 +263,8 @@ int sdio_claim_irq(struct sdio_func *func, sdio_irq_handler_t *handler) · 40 unmodified lines
261263 int ret;
262264 unsigned char reg;
263265
264− BUG_ON(!func);
265− BUG_ON(!func->card);
266+ if (!func)
267+ return -EINVAL;
266268
267269 pr_debug("SDIO: Enabling IRQ for %s...\n", sdio_func_id(func));
268270
@@ -304,8 +306,8 @@ int sdio_release_irq(struct sdio_func *func) · 35 unmodified lines
304306 int ret;
305307 unsigned char reg;
306308
307− BUG_ON(!func);
308− BUG_ON(!func->card);
309+ if (!func)
310+ return -EINVAL;
309311
310312 pr_debug("SDIO: Disabling IRQ for %s...\n", sdio_func_id(func));
311313
drivers/mmc/core/slot-gpio.c+8−0
@@ -258,6 +258,14 @@ int mmc_gpiod_request_cd(struct mmc_host *host, const char *con_id, · 257 unmodified lines
258258 }
259259 EXPORT_SYMBOL(mmc_gpiod_request_cd);
260260
261+bool mmc_can_gpio_cd(struct mmc_host *host)
262+{
263+ struct mmc_gpio *ctx = host->slot.handler_priv;
264+
265+ return ctx->cd_gpio ? true : false;
266+}
267+EXPORT_SYMBOL(mmc_can_gpio_cd);
268+
261269 /**
262270 * mmc_gpiod_request_ro - request a gpio descriptor for write protection
263271 * @host: mmc host
drivers/mmc/host/Kconfig+22−1
@@ -135,7 +135,6 @@ config MMC_SDHCI_OF_AT91 · 134 unmodified lines
135135 tristate "SDHCI OF support for the Atmel SDMMC controller"
136136 depends on MMC_SDHCI_PLTFM
137137 depends on OF
138− select MMC_SDHCI_IO_ACCESSORS
139138 help
140139 This selects the Atmel SDMMC driver
141140
@@ -144,6 +143,7 @@ config MMC_SDHCI_OF_ESDHC · 2 unmodified lines
144143 depends on MMC_SDHCI_PLTFM
145144 depends on PPC || ARCH_MXC || ARCH_LAYERSCAPE
146145 select MMC_SDHCI_IO_ACCESSORS
146+ select FSL_GUTS
147147 help
148148 This selects the Freescale eSDHC controller support.
149149
@@ -165,6 +165,17 @@ config MMC_SDHCI_OF_HLWD · 15 unmodified lines
165165
166166 If unsure, say N.
167167
168+config MMC_SDHCI_CADENCE
169+ tristate "SDHCI support for the Cadence SD/SDIO/eMMC controller"
170+ depends on MMC_SDHCI_PLTFM
171+ depends on OF
172+ help
173+ This selects the Cadence SD/SDIO/eMMC driver.
174+
175+ If you have a controller with this interface, say Y or M here.
176+
177+ If unsure, say N.
178+
168179 config MMC_SDHCI_CNS3XXX
169180 tristate "SDHCI support on the Cavium Networks CNS3xxx SoC"
170181 depends on ARCH_CNS3XXX
@@ -322,6 +333,16 @@ config MMC_SDHCI_IPROC · 151 unmodified lines
322333
323334 If unsure, say N.
324335
336+config MMC_MESON_GX
337+ tristate "Amlogic S905/GX* SD/MMC Host Controller support"
338+ depends on ARCH_MESON && MMC
339+ help
340+ This selects support for the Amlogic SD/MMC Host Controller
341+ found on the S905/GX* family of SoCs. This controller is
342+ MMC 5.1 compliant and supports SD, eMMC and SDIO interfaces.
343+
344+ If you have a controller with this interface, say Y here.
345+
325346 config MMC_MOXART
326347 tristate "MOXART SD/MMC Host Controller support"
327348 depends on ARCH_MOXART && MMC
drivers/mmc/host/Makefile+2−0
@@ -53,6 +53,7 @@ obj-$(CONFIG_MMC_JZ4740) += jz4740_mmc.o · 52 unmodified lines
5353 obj-$(CONFIG_MMC_VUB300) += vub300.o
5454 obj-$(CONFIG_MMC_USHC) += ushc.o
5555 obj-$(CONFIG_MMC_WMT) += wmt-sdmmc.o
56+obj-$(CONFIG_MMC_MESON_GX) += meson-gx-mmc.o
5657 obj-$(CONFIG_MMC_MOXART) += moxart-mmc.o
5758 obj-$(CONFIG_MMC_SUNXI) += sunxi-mmc.o
5859 obj-$(CONFIG_MMC_USDHI6ROL0) += usdhi6rol0.o
@@ -62,6 +63,7 @@ obj-$(CONFIG_MMC_REALTEK_PCI) += rtsx_pci_sdmmc.o · 3 unmodified lines
6263 obj-$(CONFIG_MMC_REALTEK_USB) += rtsx_usb_sdmmc.o
6364
6465 obj-$(CONFIG_MMC_SDHCI_PLTFM) += sdhci-pltfm.o
66+obj-$(CONFIG_MMC_SDHCI_CADENCE) += sdhci-cadence.o
6567 obj-$(CONFIG_MMC_SDHCI_CNS3XXX) += sdhci-cns3xxx.o
6668 obj-$(CONFIG_MMC_SDHCI_ESDHC_IMX) += sdhci-esdhc-imx.o
6769 obj-$(CONFIG_MMC_SDHCI_DOVE) += sdhci-dove.o
drivers/mmc/host/davinci_mmc.c+66−64
@@ -35,6 +35,7 @@ · 34 unmodified lines
3535 #include <linux/mmc/mmc.h>
3636 #include <linux/of.h>
3737 #include <linux/of_device.h>
38+#include <linux/mmc/slot-gpio.h>
3839
3940 #include <linux/platform_data/mmc-davinci.h>
4041
@@ -1029,9 +1030,10 @@ static int mmc_davinci_get_cd(struct mmc_host *mmc) · 988 unmodified lines
10291030 struct platform_device *pdev = to_platform_device(mmc->parent);
10301031 struct davinci_mmc_config *config = pdev->dev.platform_data;
10311032
1032− if (!config || !config->get_cd)
1033− return -ENOSYS;
1034− return config->get_cd(pdev->id);
1033+ if (config && config->get_cd)
1034+ return config->get_cd(pdev->id);
1035+
1036+ return mmc_gpio_get_cd(mmc);
10351037 }
10361038
10371039 static int mmc_davinci_get_ro(struct mmc_host *mmc)
@@ -1039,9 +1041,10 @@ static int mmc_davinci_get_ro(struct mmc_host *mmc) · 1 unmodified line
10391041 struct platform_device *pdev = to_platform_device(mmc->parent);
10401042 struct davinci_mmc_config *config = pdev->dev.platform_data;
10411043
1042− if (!config || !config->get_ro)
1043− return -ENOSYS;
1044− return config->get_ro(pdev->id);
1044+ if (config && config->get_ro)
1045+ return config->get_ro(pdev->id);
1046+
1047+ return mmc_gpio_get_ro(mmc);
10451048 }
10461049
10471050 static void mmc_davinci_enable_sdio_irq(struct mmc_host *mmc, int enable)
@@ -1159,49 +1162,53 @@ static const struct of_device_id davinci_mmc_dt_ids[] = { · 111 unmodified lines
11591162 };
11601163 MODULE_DEVICE_TABLE(of, davinci_mmc_dt_ids);
11611164
1162−static struct davinci_mmc_config
1163− *mmc_parse_pdata(struct platform_device *pdev)
1165+static int mmc_davinci_parse_pdata(struct mmc_host *mmc)
11641166 {
1165− struct device_node *np;
1167+ struct platform_device *pdev = to_platform_device(mmc->parent);
11661168 struct davinci_mmc_config *pdata = pdev->dev.platform_data;
1167− const struct of_device_id *match =
1168− of_match_device(davinci_mmc_dt_ids, &pdev->dev);
1169− u32 data;
1170−
1171− np = pdev->dev.of_node;
1172− if (!np)
1173− return pdata;
1174−
1175− pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1176− if (!pdata) {
1177− dev_err(&pdev->dev, "Failed to allocate memory for struct davinci_mmc_config\n");
1178− goto nodata;
1179− }
1169+ struct mmc_davinci_host *host;
1170+ int ret;
11801171
1181− if (match)
1182− pdev->id_entry = match->data;
1172+ if (!pdata)
1173+ return -EINVAL;
11831174
1184− if (of_property_read_u32(np, "max-frequency", &pdata->max_freq))
1185− dev_info(&pdev->dev, "'max-frequency' property not specified, defaulting to 25MHz\n");
1175+ host = mmc_priv(mmc);
1176+ if (!host)
1177+ return -EINVAL;
11861178
1187− of_property_read_u32(np, "bus-width", &data);
1188− switch (data) {
1189− case 1:
1190− case 4:
1191− case 8:
1192− pdata->wires = data;
1193− break;
1194− default:
1195− pdata->wires = 1;
1196− dev_info(&pdev->dev, "Unsupported buswidth, defaulting to 1 bit\n");
1197− }
1198−nodata:
1199− return pdata;
1179+ if (pdata && pdata->nr_sg)
1180+ host->nr_sg = pdata->nr_sg - 1;
1181+
1182+ if (pdata && (pdata->wires == 4 || pdata->wires == 0))
1183+ mmc->caps |= MMC_CAP_4_BIT_DATA;
1184+
1185+ if (pdata && (pdata->wires == 8))
1186+ mmc->caps |= (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA);
1187+
1188+ mmc->f_min = 312500;
1189+ mmc->f_max = 25000000;
1190+ if (pdata && pdata->max_freq)
1191+ mmc->f_max = pdata->max_freq;
1192+ if (pdata && pdata->caps)
1193+ mmc->caps |= pdata->caps;
1194+
1195+ /* Register a cd gpio, if there is not one, enable polling */
1196+ ret = mmc_gpiod_request_cd(mmc, "cd", 0, false, 0, NULL);
1197+ if (ret == -EPROBE_DEFER)
1198+ return ret;
1199+ else if (ret)
1200+ mmc->caps |= MMC_CAP_NEEDS_POLL;
1201+
1202+ ret = mmc_gpiod_request_ro(mmc, "wp", 0, false, 0, NULL);
1203+ if (ret == -EPROBE_DEFER)
1204+ return ret;
1205+
1206+ return 0;
12001207 }
12011208
12021209 static int __init davinci_mmcsd_probe(struct platform_device *pdev)
12031210 {
1204− struct davinci_mmc_config *pdata = NULL;
1211+ const struct of_device_id *match;
12051212 struct mmc_davinci_host *host = NULL;
12061213 struct mmc_host *mmc = NULL;
12071214 struct resource *r, *mem = NULL;
@@ -1209,12 +1216,6 @@ static int __init davinci_mmcsd_probe(struct platform_device *pdev) · 1 unmodified line
12091216 size_t mem_size;
12101217 const struct platform_device_id *id_entry;
12111218
1212− pdata = mmc_parse_pdata(pdev);
1213− if (pdata == NULL) {
1214− dev_err(&pdev->dev, "Couldn't get platform data\n");
1215− return -ENOENT;
1216− }
1217−
12181219 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
12191220 if (!r)
12201221 return -ENODEV;
@@ -1253,14 +1254,28 @@ static int __init davinci_mmcsd_probe(struct platform_device *pdev) · 32 unmodified lines
12531254
12541255 host->mmc_input_clk = clk_get_rate(host->clk);
12551256
1256− init_mmcsd_host(host);
1257−
1258− if (pdata->nr_sg)
1259− host->nr_sg = pdata->nr_sg - 1;
1257+ match = of_match_device(davinci_mmc_dt_ids, &pdev->dev);
1258+ if (match) {
1259+ pdev->id_entry = match->data;
1260+ ret = mmc_of_parse(mmc);
1261+ if (ret) {
1262+ dev_err(&pdev->dev,
1263+ "could not parse of data: %d\n", ret);
1264+ goto parse_fail;
1265+ }
1266+ } else {
1267+ ret = mmc_davinci_parse_pdata(mmc);
1268+ if (ret) {
1269+ dev_err(&pdev->dev,
1270+ "could not parse platform data: %d\n", ret);
1271+ goto parse_fail;
1272+ } }
12601273
12611274 if (host->nr_sg > MAX_NR_SG || !host->nr_sg)
12621275 host->nr_sg = MAX_NR_SG;
12631276
1277+ init_mmcsd_host(host);
1278+
12641279 host->use_dma = use_dma;
12651280 host->mmc_irq = irq;
12661281 host->sdio_irq = platform_get_irq(pdev, 1);
@@ -1273,27 +1288,13 @@ static int __init davinci_mmcsd_probe(struct platform_device *pdev) · 6 unmodified lines
12731288 host->use_dma = 0;
12741289 }
12751290
1276− /* REVISIT: someday, support IRQ-driven card detection. */
1277− mmc->caps |= MMC_CAP_NEEDS_POLL;
12781291 mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY;
12791292
1280− if (pdata && (pdata->wires == 4 || pdata->wires == 0))
1281− mmc->caps |= MMC_CAP_4_BIT_DATA;
1282−
1283− if (pdata && (pdata->wires == 8))
1284− mmc->caps |= (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA);
1285−
12861293 id_entry = platform_get_device_id(pdev);
12871294 if (id_entry)
12881295 host->version = id_entry->driver_data;
12891296
12901297 mmc->ops = &mmc_davinci_ops;
1291− mmc->f_min = 312500;
1292− mmc->f_max = 25000000;
1293− if (pdata && pdata->max_freq)
1294− mmc->f_max = pdata->max_freq;
1295− if (pdata && pdata->caps)
1296− mmc->caps |= pdata->caps;
12971298 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
12981299
12991300 /* With no iommu coalescing pages, each phys_seg is a hw_seg.
@@ -1354,6 +1355,7 @@ mmc_add_host_fail: · 54 unmodified lines
13541355 mmc_davinci_cpufreq_deregister(host);
13551356 cpu_freq_fail:
13561357 davinci_release_dma_channels(host);
1358+parse_fail:
13571359 dma_probe_defer:
13581360 clk_disable_unprepare(host->clk);
13591361 clk_prepare_enable_fail:
drivers/mmc/host/dw_mmc-exynos.c+36−16
@@ -17,6 +17,7 @@ · 16 unmodified lines
1717 #include <linux/mmc/mmc.h>
1818 #include <linux/of.h>
1919 #include <linux/of_gpio.h>
20+#include <linux/pm_runtime.h>
2021 #include <linux/slab.h>
2122
2223 #include "dw_mmc.h"
@@ -161,20 +162,13 @@ static void dw_mci_exynos_set_clksel_timing(struct dw_mci *host, u32 timing) · 138 unmodified lines
161162 set_bit(DW_MMC_CARD_NO_USE_HOLD, &host->cur_slot->flags);
162163 }
163164
164−#ifdef CONFIG_PM_SLEEP
165−static int dw_mci_exynos_suspend(struct device *dev)
166−{
167− struct dw_mci *host = dev_get_drvdata(dev);
168−
169− return dw_mci_suspend(host);
170−}
171−
172−static int dw_mci_exynos_resume(struct device *dev)
165+#ifdef CONFIG_PM
166+static int dw_mci_exynos_runtime_resume(struct device *dev)
173167 {
174168 struct dw_mci *host = dev_get_drvdata(dev);
175169
176170 dw_mci_exynos_config_smu(host);
177− return dw_mci_resume(host);
171+ return dw_mci_runtime_resume(dev);
178172 }
179173
180174 /**
@@ -211,10 +205,8 @@ static int dw_mci_exynos_resume_noirq(struct device *dev) · 30 unmodified lines
211205 return 0;
212206 }
213207 #else
214−#define dw_mci_exynos_suspend NULL
215−#define dw_mci_exynos_resume NULL
216208 #define dw_mci_exynos_resume_noirq NULL
217−#endif /* CONFIG_PM_SLEEP */
209+#endif /* CONFIG_PM */
218210
219211 static void dw_mci_exynos_config_hs400(struct dw_mci *host, u32 timing)
220212 {
@@ -524,14 +516,42 @@ static int dw_mci_exynos_probe(struct platform_device *pdev) · 303 unmodified lines
524516 {
525517 const struct dw_mci_drv_data *drv_data;
526518 const struct of_device_id *match;
519+ int ret;
527520
528521 match = of_match_node(dw_mci_exynos_match, pdev->dev.of_node);
529522 drv_data = match->data;
530− return dw_mci_pltfm_register(pdev, drv_data);
523+
524+ pm_runtime_get_noresume(&pdev->dev);
525+ pm_runtime_set_active(&pdev->dev);
526+ pm_runtime_enable(&pdev->dev);
527+
528+ ret = dw_mci_pltfm_register(pdev, drv_data);
529+ if (ret) {
530+ pm_runtime_disable(&pdev->dev);
531+ pm_runtime_set_suspended(&pdev->dev);
532+ pm_runtime_put_noidle(&pdev->dev);
533+
534+ return ret;
535+ }
536+
537+ return 0;
538+}
539+
540+static int dw_mci_exynos_remove(struct platform_device *pdev)
541+{
542+ pm_runtime_disable(&pdev->dev);
543+ pm_runtime_set_suspended(&pdev->dev);
544+ pm_runtime_put_noidle(&pdev->dev);
545+
546+ return dw_mci_pltfm_remove(pdev);
531547 }
532548
533549 static const struct dev_pm_ops dw_mci_exynos_pmops = {
534− SET_SYSTEM_SLEEP_PM_OPS(dw_mci_exynos_suspend, dw_mci_exynos_resume)
550+ SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
551+ pm_runtime_force_resume)
552+ SET_RUNTIME_PM_OPS(dw_mci_runtime_suspend,
553+ dw_mci_exynos_runtime_resume,
554+ NULL)
535555 .resume_noirq = dw_mci_exynos_resume_noirq,
536556 .thaw_noirq = dw_mci_exynos_resume_noirq,
537557 .restore_noirq = dw_mci_exynos_resume_noirq,
@@ -539,7 +559,7 @@ static const struct dev_pm_ops dw_mci_exynos_pmops = { · 1 unmodified line
539559
540560 static struct platform_driver dw_mci_exynos_pltfm_driver = {
541561 .probe = dw_mci_exynos_probe,
542− .remove = dw_mci_pltfm_remove,
562+ .remove = dw_mci_exynos_remove,
543563 .driver = {
544564 .name = "dwmmc_exynos",
545565 .of_match_table = dw_mci_exynos_match,
drivers/mmc/host/dw_mmc-k3.c+9−30
@@ -15,6 +15,7 @@ · 14 unmodified lines
1515 #include <linux/module.h>
1616 #include <linux/of_address.h>
1717 #include <linux/platform_device.h>
18+#include <linux/pm_runtime.h>
1819 #include <linux/regmap.h>
1920 #include <linux/regulator/consumer.h>
2021
@@ -162,35 +163,13 @@ static int dw_mci_k3_probe(struct platform_device *pdev) · 141 unmodified lines
162163 return dw_mci_pltfm_register(pdev, drv_data);
163164 }
164165
165−#ifdef CONFIG_PM_SLEEP
166−static int dw_mci_k3_suspend(struct device *dev)
167−{
168− struct dw_mci *host = dev_get_drvdata(dev);
169− int ret;
170−
171− ret = dw_mci_suspend(host);
172− if (!ret)
173− clk_disable_unprepare(host->ciu_clk);
174−
175− return ret;
176−}
177−
178−static int dw_mci_k3_resume(struct device *dev)
179−{
180− struct dw_mci *host = dev_get_drvdata(dev);
181− int ret;
182−
183− ret = clk_prepare_enable(host->ciu_clk);
184− if (ret) {
185− dev_err(host->dev, "failed to enable ciu clock\n");
186− return ret;
187− }
188−
189− return dw_mci_resume(host);
190−}
191−#endif /* CONFIG_PM_SLEEP */
192−
193−static SIMPLE_DEV_PM_OPS(dw_mci_k3_pmops, dw_mci_k3_suspend, dw_mci_k3_resume);
166+static const struct dev_pm_ops dw_mci_k3_dev_pm_ops = {
167+ SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
168+ pm_runtime_force_resume)
169+ SET_RUNTIME_PM_OPS(dw_mci_runtime_suspend,
170+ dw_mci_runtime_resume,
171+ NULL)
172+};
194173
195174 static struct platform_driver dw_mci_k3_pltfm_driver = {
196175 .probe = dw_mci_k3_probe,
@@ -198,7 +177,7 @@ static struct platform_driver dw_mci_k3_pltfm_driver = { · 1 unmodified line
198177 .driver = {
199178 .name = "dwmmc_k3",
200179 .of_match_table = dw_mci_k3_match,
201− .pm = &dw_mci_k3_pmops,
180+ .pm = &dw_mci_k3_dev_pm_ops,
202181 },
203182 };
204183
drivers/mmc/host/dw_mmc-pci.c+9−20
@@ -14,6 +14,7 @@ · 13 unmodified lines
1414 #include <linux/io.h>
1515 #include <linux/irq.h>
1616 #include <linux/pci.h>
17+#include <linux/pm_runtime.h>
1718 #include <linux/slab.h>
1819 #include <linux/mmc/host.h>
1920 #include <linux/mmc/mmc.h>
@@ -79,25 +80,13 @@ static void dw_mci_pci_remove(struct pci_dev *pdev) · 59 unmodified lines
7980 dw_mci_remove(host);
8081 }
8182
82−#ifdef CONFIG_PM_SLEEP
83−static int dw_mci_pci_suspend(struct device *dev)
84−{
85− struct pci_dev *pdev = to_pci_dev(dev);
86− struct dw_mci *host = pci_get_drvdata(pdev);
87−
88− return dw_mci_suspend(host);
89−}
90−
91−static int dw_mci_pci_resume(struct device *dev)
92−{
93− struct pci_dev *pdev = to_pci_dev(dev);
94− struct dw_mci *host = pci_get_drvdata(pdev);
95−
96− return dw_mci_resume(host);
97−}
98−#endif /* CONFIG_PM_SLEEP */
99−
100−static SIMPLE_DEV_PM_OPS(dw_mci_pci_pmops, dw_mci_pci_suspend, dw_mci_pci_resume);
83+static const struct dev_pm_ops dw_mci_pci_dev_pm_ops = {
84+ SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
85+ pm_runtime_force_resume)
86+ SET_RUNTIME_PM_OPS(dw_mci_runtime_suspend,
87+ dw_mci_runtime_resume,
88+ NULL)
89+};
10190
10291 static const struct pci_device_id dw_mci_pci_id[] = {
10392 { PCI_DEVICE(SYNOPSYS_DW_MCI_VENDOR_ID, SYNOPSYS_DW_MCI_DEVICE_ID) },
@@ -111,7 +100,7 @@ static struct pci_driver dw_mci_pci_driver = { · 7 unmodified lines
111100 .probe = dw_mci_pci_probe,
112101 .remove = dw_mci_pci_remove,
113102 .driver = {
114− .pm = &dw_mci_pci_pmops
103+ .pm = &dw_mci_pci_dev_pm_ops,
115104 },
116105 };
117106
drivers/mmc/host/dw_mmc-pltfm.c+8−20
@@ -16,6 +16,7 @@ · 15 unmodified lines
1616 #include <linux/io.h>
1717 #include <linux/irq.h>
1818 #include <linux/platform_device.h>
19+#include <linux/pm_runtime.h>
1920 #include <linux/slab.h>
2021 #include <linux/mmc/host.h>
2122 #include <linux/mmc/mmc.h>
@@ -58,26 +59,13 @@ int dw_mci_pltfm_register(struct platform_device *pdev, · 36 unmodified lines
5859 }
5960 EXPORT_SYMBOL_GPL(dw_mci_pltfm_register);
6061
61−#ifdef CONFIG_PM_SLEEP
62−/*
63− * TODO: we should probably disable the clock to the card in the suspend path.
64− */
65−static int dw_mci_pltfm_suspend(struct device *dev)
66−{
67− struct dw_mci *host = dev_get_drvdata(dev);
68−
69− return dw_mci_suspend(host);
70−}
71−
72−static int dw_mci_pltfm_resume(struct device *dev)
73−{
74− struct dw_mci *host = dev_get_drvdata(dev);
75−
76− return dw_mci_resume(host);
77−}
78−#endif /* CONFIG_PM_SLEEP */
79−
80−SIMPLE_DEV_PM_OPS(dw_mci_pltfm_pmops, dw_mci_pltfm_suspend, dw_mci_pltfm_resume);
62+const struct dev_pm_ops dw_mci_pltfm_pmops = {
63+ SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
64+ pm_runtime_force_resume)
65+ SET_RUNTIME_PM_OPS(dw_mci_runtime_suspend,
66+ dw_mci_runtime_resume,
67+ NULL)
68+};
8169 EXPORT_SYMBOL_GPL(dw_mci_pltfm_pmops);
8270
8371 static const struct of_device_id dw_mci_pltfm_match[] = {
drivers/mmc/host/dw_mmc-rockchip.c+39−3
@@ -13,6 +13,8 @@ · 12 unmodified lines
1313 #include <linux/mmc/host.h>
1414 #include <linux/mmc/dw_mmc.h>
1515 #include <linux/of_address.h>
16+#include <linux/mmc/slot-gpio.h>
17+#include <linux/pm_runtime.h>
1618 #include <linux/slab.h>
1719
1820 #include "dw_mmc.h"
@@ -325,6 +327,7 @@ static int dw_mci_rockchip_probe(struct platform_device *pdev) · 306 unmodified lines
325327 {
326328 const struct dw_mci_drv_data *drv_data;
327329 const struct of_device_id *match;
330+ int ret;
328331
329332 if (!pdev->dev.of_node)
330333 return -ENODEV;
@@ -332,16 +335,49 @@ static int dw_mci_rockchip_probe(struct platform_device *pdev) · 1 unmodified line
332335 match = of_match_node(dw_mci_rockchip_match, pdev->dev.of_node);
333336 drv_data = match->data;
334337
335− return dw_mci_pltfm_register(pdev, drv_data);
338+ pm_runtime_get_noresume(&pdev->dev);
339+ pm_runtime_set_active(&pdev->dev);
340+ pm_runtime_enable(&pdev->dev);
341+ pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
342+ pm_runtime_use_autosuspend(&pdev->dev);
343+
344+ ret = dw_mci_pltfm_register(pdev, drv_data);
345+ if (ret) {
346+ pm_runtime_disable(&pdev->dev);
347+ pm_runtime_set_suspended(&pdev->dev);
348+ pm_runtime_put_noidle(&pdev->dev);
349+ return ret;
350+ }
351+
352+ pm_runtime_put_autosuspend(&pdev->dev);
353+
354+ return 0;
336355 }
337356
357+static int dw_mci_rockchip_remove(struct platform_device *pdev)
358+{
359+ pm_runtime_get_sync(&pdev->dev);
360+ pm_runtime_disable(&pdev->dev);
361+ pm_runtime_put_noidle(&pdev->dev);
362+
363+ return dw_mci_pltfm_remove(pdev);
364+}
365+
366+static const struct dev_pm_ops dw_mci_rockchip_dev_pm_ops = {
367+ SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
368+ pm_runtime_force_resume)
369+ SET_RUNTIME_PM_OPS(dw_mci_runtime_suspend,
370+ dw_mci_runtime_resume,
371+ NULL)
372+};
373+
338374 static struct platform_driver dw_mci_rockchip_pltfm_driver = {
339375 .probe = dw_mci_rockchip_probe,
340− .remove = dw_mci_pltfm_remove,
376+ .remove = dw_mci_rockchip_remove,
341377 .driver = {
342378 .name = "dwmmc_rockchip",
343379 .of_match_table = dw_mci_rockchip_match,
344− .pm = &dw_mci_pltfm_pmops,
380+ .pm = &dw_mci_rockchip_dev_pm_ops,
345381 },
346382 };
347383
drivers/mmc/host/dw_mmc.c+115−66
@@ -54,7 +54,7 @@ · 53 unmodified lines
5454 #define DW_MCI_DMA_THRESHOLD 16
5555
5656 #define DW_MCI_FREQ_MAX 200000000 /* unit: HZ */
57−#define DW_MCI_FREQ_MIN 400000 /* unit: HZ */
57+#define DW_MCI_FREQ_MIN 100000 /* unit: HZ */
5858
5959 #define IDMAC_INT_CLR (SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \
6060 SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \
@@ -165,12 +165,14 @@ static const struct file_operations dw_mci_req_fops = { · 104 unmodified lines
165165
166166 static int dw_mci_regs_show(struct seq_file *s, void *v)
167167 {
168− seq_printf(s, "STATUS:\t0x%08x\n", SDMMC_STATUS);
169− seq_printf(s, "RINTSTS:\t0x%08x\n", SDMMC_RINTSTS);
170− seq_printf(s, "CMD:\t0x%08x\n", SDMMC_CMD);
171− seq_printf(s, "CTRL:\t0x%08x\n", SDMMC_CTRL);
172− seq_printf(s, "INTMASK:\t0x%08x\n", SDMMC_INTMASK);
173− seq_printf(s, "CLKENA:\t0x%08x\n", SDMMC_CLKENA);
168+ struct dw_mci *host = s->private;
169+
170+ seq_printf(s, "STATUS:\t0x%08x\n", mci_readl(host, STATUS));
171+ seq_printf(s, "RINTSTS:\t0x%08x\n", mci_readl(host, RINTSTS));
172+ seq_printf(s, "CMD:\t0x%08x\n", mci_readl(host, CMD));
173+ seq_printf(s, "CTRL:\t0x%08x\n", mci_readl(host, CTRL));
174+ seq_printf(s, "INTMASK:\t0x%08x\n", mci_readl(host, INTMASK));
175+ seq_printf(s, "CLKENA:\t0x%08x\n", mci_readl(host, CLKENA));
174176
175177 return 0;
176178 }
@@ -234,7 +236,6 @@ static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg); · 57 unmodified lines
234236
235237 static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd)
236238 {
237− struct mmc_data *data;
238239 struct dw_mci_slot *slot = mmc_priv(mmc);
239240 struct dw_mci *host = slot->host;
240241 u32 cmdr;
@@ -289,10 +290,9 @@ static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd) · 48 unmodified lines
289290 if (cmd->flags & MMC_RSP_CRC)
290291 cmdr |= SDMMC_CMD_RESP_CRC;
291292
292− data = cmd->data;
293− if (data) {
293+ if (cmd->data) {
294294 cmdr |= SDMMC_CMD_DAT_EXP;
295− if (data->flags & MMC_DATA_WRITE)
295+ if (cmd->data->flags & MMC_DATA_WRITE)
296296 cmdr |= SDMMC_CMD_DAT_WR;
297297 }
298298
@@ -335,6 +335,9 @@ static u32 dw_mci_prep_stop_abort(struct dw_mci *host, struct mmc_command *cmd) · 36 unmodified lines
335335 cmdr = stop->opcode | SDMMC_CMD_STOP |
336336 SDMMC_CMD_RESP_CRC | SDMMC_CMD_RESP_EXP;
337337
338+ if (!test_bit(DW_MMC_CARD_NO_USE_HOLD, &host->cur_slot->flags))
339+ cmdr |= SDMMC_CMD_USE_HOLD_REG;
340+
338341 return cmdr;
339342 }
340343
@@ -380,7 +383,7 @@ static void dw_mci_start_command(struct dw_mci *host, · 39 unmodified lines
380383
381384 static inline void send_stop_abort(struct dw_mci *host, struct mmc_data *data)
382385 {
383− struct mmc_command *stop = data->stop ? data->stop : &host->stop_abort;
386+ struct mmc_command *stop = &host->stop_abort;
384387
385388 dw_mci_start_command(host, stop, host->stop_cmdr);
386389 }
@@ -409,12 +412,13 @@ static void dw_mci_dma_cleanup(struct dw_mci *host) · 22 unmodified lines
409412 {
410413 struct mmc_data *data = host->data;
411414
412− if (data)
413− if (!data->host_cookie)
414− dma_unmap_sg(host->dev,
415− data->sg,
416− data->sg_len,
417− dw_mci_get_dma_dir(data));
415+ if (data && data->host_cookie == COOKIE_MAPPED) {
416+ dma_unmap_sg(host->dev,
417+ data->sg,
418+ data->sg_len,
419+ dw_mci_get_dma_dir(data));
420+ data->host_cookie = COOKIE_UNMAPPED;
421+ }
418422 }
419423
420424 static void dw_mci_idmac_reset(struct dw_mci *host)
@@ -612,7 +616,7 @@ static inline int dw_mci_prepare_desc64(struct dw_mci *host, · 191 unmodified lines
612616 return 0;
613617 err_own_bit:
614618 /* restore the descriptor chain as it's polluted */
615− dev_dbg(host->dev, "desciptor is still owned by IDMAC.\n");
619+ dev_dbg(host->dev, "descriptor is still owned by IDMAC.\n");
616620 memset(host->sg_cpu, 0, DESC_RING_BUF_SZ);
617621 dw_mci_idmac_init(host);
618622 return -EINVAL;
@@ -688,7 +692,7 @@ static inline int dw_mci_prepare_desc32(struct dw_mci *host, · 69 unmodified lines
688692 return 0;
689693 err_own_bit:
690694 /* restore the descriptor chain as it's polluted */
691− dev_dbg(host->dev, "desciptor is still owned by IDMAC.\n");
695+ dev_dbg(host->dev, "descriptor is still owned by IDMAC.\n");
692696 memset(host->sg_cpu, 0, DESC_RING_BUF_SZ);
693697 dw_mci_idmac_init(host);
694698 return -EINVAL;
@@ -845,13 +849,13 @@ static const struct dw_mci_dma_ops dw_mci_edmac_ops = { · 150 unmodified lines
845849
846850 static int dw_mci_pre_dma_transfer(struct dw_mci *host,
847851 struct mmc_data *data,
848− bool next)
852+ int cookie)
849853 {
850854 struct scatterlist *sg;
851855 unsigned int i, sg_len;
852856
853− if (!next && data->host_cookie)
854− return data->host_cookie;
857+ if (data->host_cookie == COOKIE_PRE_MAPPED)
858+ return data->sg_len;
855859
856860 /*
857861 * We don't do DMA on "complex" transfers, i.e. with
@@ -876,15 +880,13 @@ static int dw_mci_pre_dma_transfer(struct dw_mci *host, · 18 unmodified lines
876880 if (sg_len == 0)
877881 return -EINVAL;
878882
879− if (next)
880− data->host_cookie = sg_len;
883+ data->host_cookie = cookie;
881884
882885 return sg_len;
883886 }
884887
885888 static void dw_mci_pre_req(struct mmc_host *mmc,
886− struct mmc_request *mrq,
887− bool is_first_req)
889+ struct mmc_request *mrq)
888890 {
889891 struct dw_mci_slot *slot = mmc_priv(mmc);
890892 struct mmc_data *data = mrq->data;
@@ -892,13 +894,12 @@ static void dw_mci_pre_req(struct mmc_host *mmc, · 1 unmodified line
892894 if (!slot->host->use_dma || !data)
893895 return;
894896
895− if (data->host_cookie) {
896− data->host_cookie = 0;
897− return;
898− }
897+ /* This data might be unmapped at this time */
898+ data->host_cookie = COOKIE_UNMAPPED;
899899
900− if (dw_mci_pre_dma_transfer(slot->host, mrq->data, 1) < 0)
901− data->host_cookie = 0;
900+ if (dw_mci_pre_dma_transfer(slot->host, mrq->data,
901+ COOKIE_PRE_MAPPED) < 0)
902+ data->host_cookie = COOKIE_UNMAPPED;
902903 }
903904
904905 static void dw_mci_post_req(struct mmc_host *mmc,
@@ -911,12 +912,12 @@ static void dw_mci_post_req(struct mmc_host *mmc, · 6 unmodified lines
911912 if (!slot->host->use_dma || !data)
912913 return;
913914
914− if (data->host_cookie)
915+ if (data->host_cookie != COOKIE_UNMAPPED)
915916 dma_unmap_sg(slot->host->dev,
916917 data->sg,
917918 data->sg_len,
918919 dw_mci_get_dma_dir(data));
919− data->host_cookie = 0;
920+ data->host_cookie = COOKIE_UNMAPPED;
920921 }
921922
922923 static void dw_mci_adjust_fifoth(struct dw_mci *host, struct mmc_data *data)
@@ -1022,7 +1023,7 @@ static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data) · 99 unmodified lines
10221023 if (!host->use_dma)
10231024 return -ENODEV;
10241025
1025− sg_len = dw_mci_pre_dma_transfer(host, data, 0);
1026+ sg_len = dw_mci_pre_dma_transfer(host, data, COOKIE_MAPPED);
10261027 if (sg_len < 0) {
10271028 host->dma_ops->stop(host);
10281029 return sg_len;
@@ -1175,13 +1176,24 @@ static void dw_mci_setup_bus(struct dw_mci_slot *slot, bool force_clkinit) · 146 unmodified lines
11751176
11761177 div = (host->bus_hz != clock) ? DIV_ROUND_UP(div, 2) : 0;
11771178
1178− if (clock != slot->__clk_old || force_clkinit)
1179+ if ((clock != slot->__clk_old &&
1180+ !test_bit(DW_MMC_CARD_NEEDS_POLL, &slot->flags)) ||
1181+ force_clkinit) {
11791182 dev_info(&slot->mmc->class_dev,
11801183 "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ div = %d)\n",
11811184 slot->id, host->bus_hz, clock,
11821185 div ? ((host->bus_hz / div) >> 1) :
11831186 host->bus_hz, div);
11841187
1188+ /*
1189+ * If card is polling, display the message only
1190+ * one time at boot time.
1191+ */
1192+ if (slot->mmc->caps & MMC_CAP_NEEDS_POLL &&
1193+ slot->mmc->f_min == clock)
1194+ set_bit(DW_MMC_CARD_NEEDS_POLL, &slot->flags);
1195+ }
1196+
11851197 /* disable clock */
11861198 mci_writel(host, CLKENA, 0);
11871199 mci_writel(host, CLKSRC, 0);
@@ -1273,10 +1285,7 @@ static void __dw_mci_start_request(struct dw_mci *host, · 85 unmodified lines
12731285 spin_unlock_irqrestore(&host->irq_lock, irqflags);
12741286 }
12751287
1276− if (mrq->stop)
1277− host->stop_cmdr = dw_mci_prepare_command(slot->mmc, mrq->stop);
1278− else
1279− host->stop_cmdr = dw_mci_prep_stop_abort(host, cmd);
1288+ host->stop_cmdr = dw_mci_prep_stop_abort(host, cmd);
12801289 }
12811290
12821291 static void dw_mci_start_request(struct dw_mci *host,
@@ -1527,22 +1536,34 @@ static int dw_mci_get_cd(struct mmc_host *mmc) · 244 unmodified lines
15271536 int gpio_cd = mmc_gpio_get_cd(mmc);
15281537
15291538 /* Use platform get_cd function, else try onboard card detect */
1530− if ((mmc->caps & MMC_CAP_NEEDS_POLL) || !mmc_card_is_removable(mmc))
1539+ if (((mmc->caps & MMC_CAP_NEEDS_POLL)
1540+ || !mmc_card_is_removable(mmc))) {
15311541 present = 1;
1532− else if (gpio_cd >= 0)
1542+
1543+ if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) {
1544+ if (mmc->caps & MMC_CAP_NEEDS_POLL) {
1545+ dev_info(&mmc->class_dev,
1546+ "card is polling.\n");
1547+ } else {
1548+ dev_info(&mmc->class_dev,
1549+ "card is non-removable.\n");
1550+ }
1551+ set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1552+ }
1553+
1554+ return present;
1555+ } else if (gpio_cd >= 0)
15331556 present = gpio_cd;
15341557 else
15351558 present = (mci_readl(slot->host, CDETECT) & (1 << slot->id))
15361559 == 0 ? 1 : 0;
15371560
15381561 spin_lock_bh(&host->lock);
1539− if (present) {
1540− set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1562+ if (present && !test_and_set_bit(DW_MMC_CARD_PRESENT, &slot->flags))
15411563 dev_dbg(&mmc->class_dev, "card is present\n");
1542− } else {
1543− clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1564+ else if (!present &&
1565+ !test_and_clear_bit(DW_MMC_CARD_PRESENT, &slot->flags))
15441566 dev_dbg(&mmc->class_dev, "card is not present\n");
1545− }
15461567 spin_unlock_bh(&host->lock);
15471568
15481569 return present;
@@ -1889,8 +1910,7 @@ static void dw_mci_tasklet_func(unsigned long priv) · 340 unmodified lines
18891910 if (test_and_clear_bit(EVENT_DATA_ERROR,
18901911 &host->pending_events)) {
18911912 dw_mci_stop_dma(host);
1892− if (data->stop ||
1893− !(host->data_status & (SDMMC_INT_DRTO |
1913+ if (!(host->data_status & (SDMMC_INT_DRTO |
18941914 SDMMC_INT_EBE)))
18951915 send_stop_abort(host, data);
18961916 state = STATE_DATA_ERROR;
@@ -1926,8 +1946,7 @@ static void dw_mci_tasklet_func(unsigned long priv) · 29 unmodified lines
19261946 if (test_and_clear_bit(EVENT_DATA_ERROR,
19271947 &host->pending_events)) {
19281948 dw_mci_stop_dma(host);
1929− if (data->stop ||
1930− !(host->data_status & (SDMMC_INT_DRTO |
1949+ if (!(host->data_status & (SDMMC_INT_DRTO |
19311950 SDMMC_INT_EBE)))
19321951 send_stop_abort(host, data);
19331952 state = STATE_DATA_ERROR;
@@ -2003,7 +2022,7 @@ static void dw_mci_tasklet_func(unsigned long priv) · 69 unmodified lines
20032022 host->cmd = NULL;
20042023 host->data = NULL;
20052024
2006− if (mrq->stop)
2025+ if (!mrq->sbc && mrq->stop)
20072026 dw_mci_command_complete(host, mrq->stop);
20082027 else
20092028 host->cmd_status = 0;
@@ -2615,6 +2634,8 @@ static int dw_mci_init_slot(struct dw_mci *host, unsigned int id) · 605 unmodified lines
26152634 mmc->f_min = DW_MCI_FREQ_MIN;
26162635 mmc->f_max = DW_MCI_FREQ_MAX;
26172636 } else {
2637+ dev_info(host->dev,
2638+ "'clock-freq-min-max' property was deprecated.\n");
26182639 mmc->f_min = freq[0];
26192640 mmc->f_max = freq[1];
26202641 }
@@ -3267,26 +3288,46 @@ EXPORT_SYMBOL(dw_mci_remove); · 646 unmodified lines
32673288
32683289
32693290
3270−#ifdef CONFIG_PM_SLEEP
3271−/*
3272− * TODO: we should probably disable the clock to the card in the suspend path.
3273− */
3274−int dw_mci_suspend(struct dw_mci *host)
3291+#ifdef CONFIG_PM
3292+int dw_mci_runtime_suspend(struct device *dev)
32753293 {
3294+ struct dw_mci *host = dev_get_drvdata(dev);
3295+
32763296 if (host->use_dma && host->dma_ops->exit)
32773297 host->dma_ops->exit(host);
32783298
3299+ clk_disable_unprepare(host->ciu_clk);
3300+
3301+ if (host->cur_slot &&
3302+ (mmc_can_gpio_cd(host->cur_slot->mmc) ||
3303+ !mmc_card_is_removable(host->cur_slot->mmc)))
3304+ clk_disable_unprepare(host->biu_clk);
3305+
32793306 return 0;
32803307 }
3281−EXPORT_SYMBOL(dw_mci_suspend);
3308+EXPORT_SYMBOL(dw_mci_runtime_suspend);
32823309
3283−int dw_mci_resume(struct dw_mci *host)
3310+int dw_mci_runtime_resume(struct device *dev)
32843311 {
3285− int i, ret;
3312+ int i, ret = 0;
3313+ struct dw_mci *host = dev_get_drvdata(dev);
3314+
3315+ if (host->cur_slot &&
3316+ (mmc_can_gpio_cd(host->cur_slot->mmc) ||
3317+ !mmc_card_is_removable(host->cur_slot->mmc))) {
3318+ ret = clk_prepare_enable(host->biu_clk);
3319+ if (ret)
3320+ return ret;
3321+ }
3322+
3323+ ret = clk_prepare_enable(host->ciu_clk);
3324+ if (ret)
3325+ goto err;
32863326
32873327 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) {
3328+ clk_disable_unprepare(host->ciu_clk);
32883329 ret = -ENODEV;
3289− return ret;
3330+ goto err;
32903331 }
32913332
32923333 if (host->use_dma && host->dma_ops->init)
@@ -3296,8 +3337,8 @@ int dw_mci_resume(struct dw_mci *host) · 3 unmodified lines
32963337 * Restore the initial value at FIFOTH register
32973338 * And Invalidate the prev_blksz with zero
32983339 */
3299− mci_writel(host, FIFOTH, host->fifoth_val);
3300− host->prev_blksz = 0;
3340+ mci_writel(host, FIFOTH, host->fifoth_val);
3341+ host->prev_blksz = 0;
33013342
33023343 /* Put in max timeout */
33033344 mci_writel(host, TMOUT, 0xFFFFFFFF);
@@ -3323,9 +3364,17 @@ int dw_mci_resume(struct dw_mci *host) · 19 unmodified lines
33233364 dw_mci_enable_cd(host);
33243365
33253366 return 0;
3367+
3368+err:
3369+ if (host->cur_slot &&
3370+ (mmc_can_gpio_cd(host->cur_slot->mmc) ||
3371+ !mmc_card_is_removable(host->cur_slot->mmc)))
3372+ clk_disable_unprepare(host->biu_clk);
3373+
3374+ return ret;
33263375 }
3327−EXPORT_SYMBOL(dw_mci_resume);
3328−#endif /* CONFIG_PM_SLEEP */
3376+EXPORT_SYMBOL(dw_mci_runtime_resume);
3377+#endif /* CONFIG_PM */
33293378
33303379 static int __init dw_mci_init(void)
33313380 {
drivers/mmc/host/dw_mmc.h+4−3
@@ -234,9 +234,9 @@ · 233 unmodified lines
234234
235235 extern int dw_mci_probe(struct dw_mci *host);
236236 extern void dw_mci_remove(struct dw_mci *host);
237−#ifdef CONFIG_PM_SLEEP
238−extern int dw_mci_suspend(struct dw_mci *host);
239−extern int dw_mci_resume(struct dw_mci *host);
237+#ifdef CONFIG_PM
238+extern int dw_mci_runtime_suspend(struct device *device);
239+extern int dw_mci_runtime_resume(struct device *device);
240240 #endif
241241
242242 /**
@@ -272,6 +272,7 @@ struct dw_mci_slot { · 29 unmodified lines
272272 #define DW_MMC_CARD_NEED_INIT 1
273273 #define DW_MMC_CARD_NO_LOW_PWR 2
274274 #define DW_MMC_CARD_NO_USE_HOLD 3
275+#define DW_MMC_CARD_NEEDS_POLL 4
275276 int id;
276277 int sdio_id;
277278 };
drivers/mmc/host/jz4740_mmc.c+1−2
@@ -320,8 +320,7 @@ dma_unmap: · 319 unmodified lines
320320 }
321321
322322 static void jz4740_mmc_pre_request(struct mmc_host *mmc,
323− struct mmc_request *mrq,
324− bool is_first_req)
323+ struct mmc_request *mrq)
325324 {
326325 struct jz4740_mmc_host *host = mmc_priv(mmc);
327326 struct mmc_data *data = mrq->data;
drivers/mmc/host/meson-gx-mmc.c+851−0
@@ -0,0 +1,851 @@
1+/*
2+ * Amlogic SD/eMMC driver for the GX/S905 family SoCs
3+ *
4+ * Copyright (c) 2016 BayLibre, SAS.
5+ * Author: Kevin Hilman <khilman@baylibre.com>
6+ *
7+ * This program is free software; you can redistribute it and/or modify
8+ * it under the terms of version 2 of the GNU General Public License as
9+ * published by the Free Software Foundation.
10+ *
11+ * This program is distributed in the hope that it will be useful, but
12+ * WITHOUT ANY WARRANTY; without even the implied warranty of
13+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14+ * General Public License for more details.
15+ *
16+ * You should have received a copy of the GNU General Public License
17+ * along with this program; if not, see <http://www.gnu.org/licenses/>.
18+ * The full GNU General Public License is included in this distribution
19+ * in the file called COPYING.
20+ */
21+#include <linux/kernel.h>
22+#include <linux/module.h>
23+#include <linux/init.h>
24+#include <linux/device.h>
25+#include <linux/of_device.h>
26+#include <linux/platform_device.h>
27+#include <linux/ioport.h>
28+#include <linux/spinlock.h>
29+#include <linux/dma-mapping.h>
30+#include <linux/mmc/host.h>
31+#include <linux/mmc/mmc.h>
32+#include <linux/mmc/sdio.h>
33+#include <linux/mmc/slot-gpio.h>
34+#include <linux/io.h>
35+#include <linux/clk.h>
36+#include <linux/clk-provider.h>
37+#include <linux/regulator/consumer.h>
38+
39+#define DRIVER_NAME "meson-gx-mmc"
40+
41+#define SD_EMMC_CLOCK 0x0
42+#define CLK_DIV_SHIFT 0
43+#define CLK_DIV_WIDTH 6
44+#define CLK_DIV_MASK 0x3f
45+#define CLK_DIV_MAX 63
46+#define CLK_SRC_SHIFT 6
47+#define CLK_SRC_WIDTH 2
48+#define CLK_SRC_MASK 0x3
49+#define CLK_SRC_XTAL 0 /* external crystal */
50+#define CLK_SRC_XTAL_RATE 24000000
51+#define CLK_SRC_PLL 1 /* FCLK_DIV2 */
52+#define CLK_SRC_PLL_RATE 1000000000
53+#define CLK_PHASE_SHIFT 8
54+#define CLK_PHASE_MASK 0x3
55+#define CLK_PHASE_0 0
56+#define CLK_PHASE_90 1
57+#define CLK_PHASE_180 2
58+#define CLK_PHASE_270 3
59+#define CLK_ALWAYS_ON BIT(24)
60+
61+#define SD_EMMC_DElAY 0x4
62+#define SD_EMMC_ADJUST 0x8
63+#define SD_EMMC_CALOUT 0x10
64+#define SD_EMMC_START 0x40
65+#define START_DESC_INIT BIT(0)
66+#define START_DESC_BUSY BIT(1)
67+#define START_DESC_ADDR_SHIFT 2
68+#define START_DESC_ADDR_MASK (~0x3)
69+
70+#define SD_EMMC_CFG 0x44
71+#define CFG_BUS_WIDTH_SHIFT 0
72+#define CFG_BUS_WIDTH_MASK 0x3
73+#define CFG_BUS_WIDTH_1 0x0
74+#define CFG_BUS_WIDTH_4 0x1
75+#define CFG_BUS_WIDTH_8 0x2
76+#define CFG_DDR BIT(2)
77+#define CFG_BLK_LEN_SHIFT 4
78+#define CFG_BLK_LEN_MASK 0xf
79+#define CFG_RESP_TIMEOUT_SHIFT 8
80+#define CFG_RESP_TIMEOUT_MASK 0xf
81+#define CFG_RC_CC_SHIFT 12
82+#define CFG_RC_CC_MASK 0xf
83+#define CFG_STOP_CLOCK BIT(22)
84+#define CFG_CLK_ALWAYS_ON BIT(18)
85+#define CFG_AUTO_CLK BIT(23)
86+
87+#define SD_EMMC_STATUS 0x48
88+#define STATUS_BUSY BIT(31)
89+
90+#define SD_EMMC_IRQ_EN 0x4c
91+#define IRQ_EN_MASK 0x3fff
92+#define IRQ_RXD_ERR_SHIFT 0
93+#define IRQ_RXD_ERR_MASK 0xff
94+#define IRQ_TXD_ERR BIT(8)
95+#define IRQ_DESC_ERR BIT(9)
96+#define IRQ_RESP_ERR BIT(10)
97+#define IRQ_RESP_TIMEOUT BIT(11)
98+#define IRQ_DESC_TIMEOUT BIT(12)
99+#define IRQ_END_OF_CHAIN BIT(13)
100+#define IRQ_RESP_STATUS BIT(14)
101+#define IRQ_SDIO BIT(15)
102+
103+#define SD_EMMC_CMD_CFG 0x50
104+#define SD_EMMC_CMD_ARG 0x54
105+#define SD_EMMC_CMD_DAT 0x58
106+#define SD_EMMC_CMD_RSP 0x5c
107+#define SD_EMMC_CMD_RSP1 0x60
108+#define SD_EMMC_CMD_RSP2 0x64
109+#define SD_EMMC_CMD_RSP3 0x68
110+
111+#define SD_EMMC_RXD 0x94
112+#define SD_EMMC_TXD 0x94
113+#define SD_EMMC_LAST_REG SD_EMMC_TXD
114+
115+#define SD_EMMC_CFG_BLK_SIZE 512 /* internal buffer max: 512 bytes */
116+#define SD_EMMC_CFG_RESP_TIMEOUT 256 /* in clock cycles */
117+#define SD_EMMC_CFG_CMD_GAP 16 /* in clock cycles */
118+#define MUX_CLK_NUM_PARENTS 2
119+
120+struct meson_host {
121+ struct device *dev;
122+ struct mmc_host *mmc;
123+ struct mmc_request *mrq;
124+ struct mmc_command *cmd;
125+
126+ spinlock_t lock;
127+ void __iomem *regs;
128+ int irq;
129+ u32 ocr_mask;
130+ struct clk *core_clk;
131+ struct clk_mux mux;
132+ struct clk *mux_clk;
133+ struct clk *mux_parent[MUX_CLK_NUM_PARENTS];
134+ unsigned long mux_parent_rate[MUX_CLK_NUM_PARENTS];
135+
136+ struct clk_divider cfg_div;
137+ struct clk *cfg_div_clk;
138+
139+ unsigned int bounce_buf_size;
140+ void *bounce_buf;
141+ dma_addr_t bounce_dma_addr;
142+
143+ bool vqmmc_enabled;
144+};
145+
146+struct sd_emmc_desc {
147+ u32 cmd_cfg;
148+ u32 cmd_arg;
149+ u32 cmd_data;
150+ u32 cmd_resp;
151+};
152+#define CMD_CFG_LENGTH_SHIFT 0
153+#define CMD_CFG_LENGTH_MASK 0x1ff
154+#define CMD_CFG_BLOCK_MODE BIT(9)
155+#define CMD_CFG_R1B BIT(10)
156+#define CMD_CFG_END_OF_CHAIN BIT(11)
157+#define CMD_CFG_TIMEOUT_SHIFT 12
158+#define CMD_CFG_TIMEOUT_MASK 0xf
159+#define CMD_CFG_NO_RESP BIT(16)
160+#define CMD_CFG_NO_CMD BIT(17)
161+#define CMD_CFG_DATA_IO BIT(18)
162+#define CMD_CFG_DATA_WR BIT(19)
163+#define CMD_CFG_RESP_NOCRC BIT(20)
164+#define CMD_CFG_RESP_128 BIT(21)
165+#define CMD_CFG_RESP_NUM BIT(22)
166+#define CMD_CFG_DATA_NUM BIT(23)
167+#define CMD_CFG_CMD_INDEX_SHIFT 24
168+#define CMD_CFG_CMD_INDEX_MASK 0x3f
169+#define CMD_CFG_ERROR BIT(30)
170+#define CMD_CFG_OWNER BIT(31)
171+
172+#define CMD_DATA_MASK (~0x3)
173+#define CMD_DATA_BIG_ENDIAN BIT(1)
174+#define CMD_DATA_SRAM BIT(0)
175+#define CMD_RESP_MASK (~0x1)
176+#define CMD_RESP_SRAM BIT(0)
177+
178+static int meson_mmc_clk_set(struct meson_host *host, unsigned long clk_rate)
179+{
180+ struct mmc_host *mmc = host->mmc;
181+ int ret = 0;
182+ u32 cfg;
183+
184+ if (clk_rate) {
185+ if (WARN_ON(clk_rate > mmc->f_max))
186+ clk_rate = mmc->f_max;
187+ else if (WARN_ON(clk_rate < mmc->f_min))
188+ clk_rate = mmc->f_min;
189+ }
190+
191+ if (clk_rate == mmc->actual_clock)
192+ return 0;
193+
194+ /* stop clock */
195+ cfg = readl(host->regs + SD_EMMC_CFG);
196+ if (!(cfg & CFG_STOP_CLOCK)) {
197+ cfg |= CFG_STOP_CLOCK;
198+ writel(cfg, host->regs + SD_EMMC_CFG);
199+ }
200+
201+ dev_dbg(host->dev, "change clock rate %u -> %lu\n",
202+ mmc->actual_clock, clk_rate);
203+
204+ if (clk_rate == 0) {
205+ mmc->actual_clock = 0;
206+ return 0;
207+ }
208+
209+ ret = clk_set_rate(host->cfg_div_clk, clk_rate);
210+ if (ret)
211+ dev_warn(host->dev, "Unable to set cfg_div_clk to %lu. ret=%d\n",
212+ clk_rate, ret);
213+ else if (clk_rate && clk_rate != clk_get_rate(host->cfg_div_clk))
214+ dev_warn(host->dev, "divider requested rate %lu != actual rate %lu: ret=%d\n",
215+ clk_rate, clk_get_rate(host->cfg_div_clk), ret);
216+ else
217+ mmc->actual_clock = clk_rate;
218+
219+ /* (re)start clock, if non-zero */
220+ if (!ret && clk_rate) {
221+ cfg = readl(host->regs + SD_EMMC_CFG);
222+ cfg &= ~CFG_STOP_CLOCK;
223+ writel(cfg, host->regs + SD_EMMC_CFG);
224+ }
225+
226+ return ret;
227+}
228+
229+/*
230+ * The SD/eMMC IP block has an internal mux and divider used for
231+ * generating the MMC clock. Use the clock framework to create and
232+ * manage these clocks.
233+ */
234+static int meson_mmc_clk_init(struct meson_host *host)
235+{
236+ struct clk_init_data init;
237+ char clk_name[32];
238+ int i, ret = 0;
239+ const char *mux_parent_names[MUX_CLK_NUM_PARENTS];
240+ unsigned int mux_parent_count = 0;
241+ const char *clk_div_parents[1];
242+ unsigned int f_min = UINT_MAX;
243+ u32 clk_reg, cfg;
244+
245+ /* get the mux parents */
246+ for (i = 0; i < MUX_CLK_NUM_PARENTS; i++) {
247+ char name[16];
248+
249+ snprintf(name, sizeof(name), "clkin%d", i);
250+ host->mux_parent[i] = devm_clk_get(host->dev, name);
251+ if (IS_ERR(host->mux_parent[i])) {
252+ ret = PTR_ERR(host->mux_parent[i]);
253+ if (PTR_ERR(host->mux_parent[i]) != -EPROBE_DEFER)
254+ dev_err(host->dev, "Missing clock %s\n", name);
255+ host->mux_parent[i] = NULL;
256+ return ret;
257+ }
258+
259+ host->mux_parent_rate[i] = clk_get_rate(host->mux_parent[i]);
260+ mux_parent_names[i] = __clk_get_name(host->mux_parent[i]);
261+ mux_parent_count++;
262+ if (host->mux_parent_rate[i] < f_min)
263+ f_min = host->mux_parent_rate[i];
264+ }
265+
266+ /* cacluate f_min based on input clocks, and max divider value */
267+ if (f_min != UINT_MAX)
268+ f_min = DIV_ROUND_UP(CLK_SRC_XTAL_RATE, CLK_DIV_MAX);
269+ else
270+ f_min = 4000000; /* default min: 400 MHz */
271+ host->mmc->f_min = f_min;
272+
273+ /* create the mux */
274+ snprintf(clk_name, sizeof(clk_name), "%s#mux", dev_name(host->dev));
275+ init.name = clk_name;
276+ init.ops = &clk_mux_ops;
277+ init.flags = 0;
278+ init.parent_names = mux_parent_names;
279+ init.num_parents = mux_parent_count;
280+
281+ host->mux.reg = host->regs + SD_EMMC_CLOCK;
282+ host->mux.shift = CLK_SRC_SHIFT;
283+ host->mux.mask = CLK_SRC_MASK;
284+ host->mux.flags = 0;
285+ host->mux.table = NULL;
286+ host->mux.hw.init = &init;
287+
288+ host->mux_clk = devm_clk_register(host->dev, &host->mux.hw);
289+ if (WARN_ON(IS_ERR(host->mux_clk)))
290+ return PTR_ERR(host->mux_clk);
291+
292+ /* create the divider */
293+ snprintf(clk_name, sizeof(clk_name), "%s#div", dev_name(host->dev));
294+ init.name = devm_kstrdup(host->dev, clk_name, GFP_KERNEL);
295+ init.ops = &clk_divider_ops;
296+ init.flags = CLK_SET_RATE_PARENT;
297+ clk_div_parents[0] = __clk_get_name(host->mux_clk);
298+ init.parent_names = clk_div_parents;
299+ init.num_parents = ARRAY_SIZE(clk_div_parents);
300+
301+ host->cfg_div.reg = host->regs + SD_EMMC_CLOCK;
302+ host->cfg_div.shift = CLK_DIV_SHIFT;
303+ host->cfg_div.width = CLK_DIV_WIDTH;
304+ host->cfg_div.hw.init = &init;
305+ host->cfg_div.flags = CLK_DIVIDER_ONE_BASED |
306+ CLK_DIVIDER_ROUND_CLOSEST | CLK_DIVIDER_ALLOW_ZERO;
307+
308+ host->cfg_div_clk = devm_clk_register(host->dev, &host->cfg_div.hw);
309+ if (WARN_ON(PTR_ERR_OR_ZERO(host->cfg_div_clk)))
310+ return PTR_ERR(host->cfg_div_clk);
311+
312+ /* init SD_EMMC_CLOCK to sane defaults w/min clock rate */
313+ clk_reg = 0;
314+ clk_reg |= CLK_PHASE_180 << CLK_PHASE_SHIFT;
315+ clk_reg |= CLK_SRC_XTAL << CLK_SRC_SHIFT;
316+ clk_reg |= CLK_DIV_MAX << CLK_DIV_SHIFT;
317+ clk_reg &= ~CLK_ALWAYS_ON;
318+ writel(clk_reg, host->regs + SD_EMMC_CLOCK);
319+
320+ /* Ensure clock starts in "auto" mode, not "always on" */
321+ cfg = readl(host->regs + SD_EMMC_CFG);
322+ cfg &= ~CFG_CLK_ALWAYS_ON;
323+ cfg |= CFG_AUTO_CLK;
324+ writel(cfg, host->regs + SD_EMMC_CFG);
325+
326+ ret = clk_prepare_enable(host->cfg_div_clk);
327+ if (!ret)
328+ ret = meson_mmc_clk_set(host, f_min);
329+
330+ if (!ret)
331+ clk_disable_unprepare(host->cfg_div_clk);
332+
333+ return ret;
334+}
335+
336+static void meson_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
337+{
338+ struct meson_host *host = mmc_priv(mmc);
339+ u32 bus_width;
340+ u32 val, orig;
341+
342+ /*
343+ * GPIO regulator, only controls switching between 1v8 and
344+ * 3v3, doesn't support MMC_POWER_OFF, MMC_POWER_ON.
345+ */
346+ switch (ios->power_mode) {
347+ case MMC_POWER_OFF:
348+ if (!IS_ERR(mmc->supply.vmmc))
349+ mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
350+
351+ if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) {
352+ regulator_disable(mmc->supply.vqmmc);
353+ host->vqmmc_enabled = false;
354+ }
355+
356+ break;
357+
358+ case MMC_POWER_UP:
359+ if (!IS_ERR(mmc->supply.vmmc))
360+ mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd);
361+ break;
362+
363+ case MMC_POWER_ON:
364+ if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) {
365+ int ret = regulator_enable(mmc->supply.vqmmc);
366+
367+ if (ret < 0)
368+ dev_err(mmc_dev(mmc),
369+ "failed to enable vqmmc regulator\n");
370+ else
371+ host->vqmmc_enabled = true;
372+ }
373+
374+ break;
375+ }
376+
377+
378+ meson_mmc_clk_set(host, ios->clock);
379+
380+ /* Bus width */
381+ val = readl(host->regs + SD_EMMC_CFG);
382+ switch (ios->bus_width) {
383+ case MMC_BUS_WIDTH_1:
384+ bus_width = CFG_BUS_WIDTH_1;
385+ break;
386+ case MMC_BUS_WIDTH_4:
387+ bus_width = CFG_BUS_WIDTH_4;
388+ break;
389+ case MMC_BUS_WIDTH_8:
390+ bus_width = CFG_BUS_WIDTH_8;
391+ break;
392+ default:
393+ dev_err(host->dev, "Invalid ios->bus_width: %u. Setting to 4.\n",
394+ ios->bus_width);
395+ bus_width = CFG_BUS_WIDTH_4;
396+ return;
397+ }
398+
399+ val = readl(host->regs + SD_EMMC_CFG);
400+ orig = val;
401+
402+ val &= ~(CFG_BUS_WIDTH_MASK << CFG_BUS_WIDTH_SHIFT);
403+ val |= bus_width << CFG_BUS_WIDTH_SHIFT;
404+
405+ val &= ~(CFG_BLK_LEN_MASK << CFG_BLK_LEN_SHIFT);
406+ val |= ilog2(SD_EMMC_CFG_BLK_SIZE) << CFG_BLK_LEN_SHIFT;
407+
408+ val &= ~(CFG_RESP_TIMEOUT_MASK << CFG_RESP_TIMEOUT_SHIFT);
409+ val |= ilog2(SD_EMMC_CFG_RESP_TIMEOUT) << CFG_RESP_TIMEOUT_SHIFT;
410+
411+ val &= ~(CFG_RC_CC_MASK << CFG_RC_CC_SHIFT);
412+ val |= ilog2(SD_EMMC_CFG_CMD_GAP) << CFG_RC_CC_SHIFT;
413+
414+ writel(val, host->regs + SD_EMMC_CFG);
415+
416+ if (val != orig)
417+ dev_dbg(host->dev, "%s: SD_EMMC_CFG: 0x%08x -> 0x%08x\n",
418+ __func__, orig, val);
419+}
420+
421+static int meson_mmc_request_done(struct mmc_host *mmc, struct mmc_request *mrq)
422+{
423+ struct meson_host *host = mmc_priv(mmc);
424+
425+ WARN_ON(host->mrq != mrq);
426+
427+ host->mrq = NULL;
428+ host->cmd = NULL;
429+ mmc_request_done(host->mmc, mrq);
430+
431+ return 0;
432+}
433+
434+static void meson_mmc_start_cmd(struct mmc_host *mmc, struct mmc_command *cmd)
435+{
436+ struct meson_host *host = mmc_priv(mmc);
437+ struct sd_emmc_desc *desc, desc_tmp;
438+ u32 cfg;
439+ u8 blk_len, cmd_cfg_timeout;
440+ unsigned int xfer_bytes = 0;
441+
442+ /* Setup descriptors */
443+ dma_rmb();
444+ desc = &desc_tmp;
445+ memset(desc, 0, sizeof(struct sd_emmc_desc));
446+
447+ desc->cmd_cfg |= (cmd->opcode & CMD_CFG_CMD_INDEX_MASK) <<
448+ CMD_CFG_CMD_INDEX_SHIFT;
449+ desc->cmd_cfg |= CMD_CFG_OWNER; /* owned by CPU */
450+ desc->cmd_arg = cmd->arg;
451+
452+ /* Response */
453+ if (cmd->flags & MMC_RSP_PRESENT) {
454+ desc->cmd_cfg &= ~CMD_CFG_NO_RESP;
455+ if (cmd->flags & MMC_RSP_136)
456+ desc->cmd_cfg |= CMD_CFG_RESP_128;
457+ desc->cmd_cfg |= CMD_CFG_RESP_NUM;
458+ desc->cmd_resp = 0;
459+
460+ if (!(cmd->flags & MMC_RSP_CRC))
461+ desc->cmd_cfg |= CMD_CFG_RESP_NOCRC;
462+
463+ if (cmd->flags & MMC_RSP_BUSY)
464+ desc->cmd_cfg |= CMD_CFG_R1B;
465+ } else {
466+ desc->cmd_cfg |= CMD_CFG_NO_RESP;
467+ }
468+
469+ /* data? */
470+ if (cmd->data) {
471+ desc->cmd_cfg |= CMD_CFG_DATA_IO;
472+ if (cmd->data->blocks > 1) {
473+ desc->cmd_cfg |= CMD_CFG_BLOCK_MODE;
474+ desc->cmd_cfg |=
475+ (cmd->data->blocks & CMD_CFG_LENGTH_MASK) <<
476+ CMD_CFG_LENGTH_SHIFT;
477+
478+ /* check if block-size matches, if not update */
479+ cfg = readl(host->regs + SD_EMMC_CFG);
480+ blk_len = cfg & (CFG_BLK_LEN_MASK << CFG_BLK_LEN_SHIFT);
481+ blk_len >>= CFG_BLK_LEN_SHIFT;
482+ if (blk_len != ilog2(cmd->data->blksz)) {
483+ dev_warn(host->dev, "%s: update blk_len %d -> %d\n",
484+ __func__, blk_len,
485+ ilog2(cmd->data->blksz));
486+ blk_len = ilog2(cmd->data->blksz);
487+ cfg &= ~(CFG_BLK_LEN_MASK << CFG_BLK_LEN_SHIFT);
488+ cfg |= blk_len << CFG_BLK_LEN_SHIFT;
489+ writel(cfg, host->regs + SD_EMMC_CFG);
490+ }
491+ } else {
492+ desc->cmd_cfg &= ~CMD_CFG_BLOCK_MODE;
493+ desc->cmd_cfg |=
494+ (cmd->data->blksz & CMD_CFG_LENGTH_MASK) <<
495+ CMD_CFG_LENGTH_SHIFT;
496+ }
497+
498+ cmd->data->bytes_xfered = 0;
499+ xfer_bytes = cmd->data->blksz * cmd->data->blocks;
500+ if (cmd->data->flags & MMC_DATA_WRITE) {
501+ desc->cmd_cfg |= CMD_CFG_DATA_WR;
502+ WARN_ON(xfer_bytes > host->bounce_buf_size);
503+ sg_copy_to_buffer(cmd->data->sg, cmd->data->sg_len,
504+ host->bounce_buf, xfer_bytes);
505+ cmd->data->bytes_xfered = xfer_bytes;
506+ dma_wmb();
507+ } else {
508+ desc->cmd_cfg &= ~CMD_CFG_DATA_WR;
509+ }
510+
511+ if (xfer_bytes > 0) {
512+ desc->cmd_cfg &= ~CMD_CFG_DATA_NUM;
513+ desc->cmd_data = host->bounce_dma_addr & CMD_DATA_MASK;
514+ } else {
515+ /* write data to data_addr */
516+ desc->cmd_cfg |= CMD_CFG_DATA_NUM;
517+ desc->cmd_data = 0;
518+ }
519+
520+ cmd_cfg_timeout = 12;
521+ } else {
522+ desc->cmd_cfg &= ~CMD_CFG_DATA_IO;
523+ cmd_cfg_timeout = 10;
524+ }
525+ desc->cmd_cfg |= (cmd_cfg_timeout & CMD_CFG_TIMEOUT_MASK) <<
526+ CMD_CFG_TIMEOUT_SHIFT;
527+
528+ host->cmd = cmd;
529+
530+ /* Last descriptor */
531+ desc->cmd_cfg |= CMD_CFG_END_OF_CHAIN;
532+ writel(desc->cmd_cfg, host->regs + SD_EMMC_CMD_CFG);
533+ writel(desc->cmd_data, host->regs + SD_EMMC_CMD_DAT);
534+ writel(desc->cmd_resp, host->regs + SD_EMMC_CMD_RSP);
535+ wmb(); /* ensure descriptor is written before kicked */
536+ writel(desc->cmd_arg, host->regs + SD_EMMC_CMD_ARG);
537+}
538+
539+static void meson_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
540+{
541+ struct meson_host *host = mmc_priv(mmc);
542+
543+ WARN_ON(host->mrq != NULL);
544+
545+ /* Stop execution */
546+ writel(0, host->regs + SD_EMMC_START);
547+
548+ /* clear, ack, enable all interrupts */
549+ writel(0, host->regs + SD_EMMC_IRQ_EN);
550+ writel(IRQ_EN_MASK, host->regs + SD_EMMC_STATUS);
551+ writel(IRQ_EN_MASK, host->regs + SD_EMMC_IRQ_EN);
552+
553+ host->mrq = mrq;
554+
555+ if (mrq->sbc)
556+ meson_mmc_start_cmd(mmc, mrq->sbc);
557+ else
558+ meson_mmc_start_cmd(mmc, mrq->cmd);
559+}
560+
561+static int meson_mmc_read_resp(struct mmc_host *mmc, struct mmc_command *cmd)
562+{
563+ struct meson_host *host = mmc_priv(mmc);
564+
565+ if (cmd->flags & MMC_RSP_136) {
566+ cmd->resp[0] = readl(host->regs + SD_EMMC_CMD_RSP3);
567+ cmd->resp[1] = readl(host->regs + SD_EMMC_CMD_RSP2);
568+ cmd->resp[2] = readl(host->regs + SD_EMMC_CMD_RSP1);
569+ cmd->resp[3] = readl(host->regs + SD_EMMC_CMD_RSP);
570+ } else if (cmd->flags & MMC_RSP_PRESENT) {
571+ cmd->resp[0] = readl(host->regs + SD_EMMC_CMD_RSP);
572+ }
573+
574+ return 0;
575+}
576+
577+static irqreturn_t meson_mmc_irq(int irq, void *dev_id)
578+{
579+ struct meson_host *host = dev_id;
580+ struct mmc_request *mrq;
581+ struct mmc_command *cmd = host->cmd;
582+ u32 irq_en, status, raw_status;
583+ irqreturn_t ret = IRQ_HANDLED;
584+
585+ if (WARN_ON(!host))
586+ return IRQ_NONE;
587+
588+ mrq = host->mrq;
589+
590+ if (WARN_ON(!mrq))
591+ return IRQ_NONE;
592+
593+ if (WARN_ON(!cmd))
594+ return IRQ_NONE;
595+
596+ spin_lock(&host->lock);
597+ irq_en = readl(host->regs + SD_EMMC_IRQ_EN);
598+ raw_status = readl(host->regs + SD_EMMC_STATUS);
599+ status = raw_status & irq_en;
600+
601+ if (!status) {
602+ dev_warn(host->dev, "Spurious IRQ! status=0x%08x, irq_en=0x%08x\n",
603+ raw_status, irq_en);
604+ ret = IRQ_NONE;
605+ goto out;
606+ }
607+
608+ cmd->error = 0;
609+ if (status & IRQ_RXD_ERR_MASK) {
610+ dev_dbg(host->dev, "Unhandled IRQ: RXD error\n");
611+ cmd->error = -EILSEQ;
612+ }
613+ if (status & IRQ_TXD_ERR) {
614+ dev_dbg(host->dev, "Unhandled IRQ: TXD error\n");
615+ cmd->error = -EILSEQ;
616+ }
617+ if (status & IRQ_DESC_ERR)
618+ dev_dbg(host->dev, "Unhandled IRQ: Descriptor error\n");
619+ if (status & IRQ_RESP_ERR) {
620+ dev_dbg(host->dev, "Unhandled IRQ: Response error\n");
621+ cmd->error = -EILSEQ;
622+ }
623+ if (status & IRQ_RESP_TIMEOUT) {
624+ dev_dbg(host->dev, "Unhandled IRQ: Response timeout\n");
625+ cmd->error = -ETIMEDOUT;
626+ }
627+ if (status & IRQ_DESC_TIMEOUT) {
628+ dev_dbg(host->dev, "Unhandled IRQ: Descriptor timeout\n");
629+ cmd->error = -ETIMEDOUT;
630+ }
631+ if (status & IRQ_SDIO)
632+ dev_dbg(host->dev, "Unhandled IRQ: SDIO.\n");
633+
634+ if (status & (IRQ_END_OF_CHAIN | IRQ_RESP_STATUS))
635+ ret = IRQ_WAKE_THREAD;
636+ else {
637+ dev_warn(host->dev, "Unknown IRQ! status=0x%04x: MMC CMD%u arg=0x%08x flags=0x%08x stop=%d\n",
638+ status, cmd->opcode, cmd->arg,
639+ cmd->flags, mrq->stop ? 1 : 0);
640+ if (cmd->data) {
641+ struct mmc_data *data = cmd->data;
642+
643+ dev_warn(host->dev, "\tblksz %u blocks %u flags 0x%08x (%s%s)",
644+ data->blksz, data->blocks, data->flags,
645+ data->flags & MMC_DATA_WRITE ? "write" : "",
646+ data->flags & MMC_DATA_READ ? "read" : "");
647+ }
648+ }
649+
650+out:
651+ /* ack all (enabled) interrupts */
652+ writel(status, host->regs + SD_EMMC_STATUS);
653+
654+ if (ret == IRQ_HANDLED) {
655+ meson_mmc_read_resp(host->mmc, cmd);
656+ meson_mmc_request_done(host->mmc, cmd->mrq);
657+ }
658+
659+ spin_unlock(&host->lock);
660+ return ret;
661+}
662+
663+static irqreturn_t meson_mmc_irq_thread(int irq, void *dev_id)
664+{
665+ struct meson_host *host = dev_id;
666+ struct mmc_request *mrq = host->mrq;
667+ struct mmc_command *cmd = host->cmd;
668+ struct mmc_data *data;
669+ unsigned int xfer_bytes;
670+ int ret = IRQ_HANDLED;
671+
672+ if (WARN_ON(!mrq))
673+ ret = IRQ_NONE;
674+
675+ if (WARN_ON(!cmd))
676+ ret = IRQ_NONE;
677+
678+ data = cmd->data;
679+ if (data) {
680+ xfer_bytes = data->blksz * data->blocks;
681+ if (data->flags & MMC_DATA_READ) {
682+ WARN_ON(xfer_bytes > host->bounce_buf_size);
683+ sg_copy_from_buffer(data->sg, data->sg_len,
684+ host->bounce_buf, xfer_bytes);
685+ data->bytes_xfered = xfer_bytes;
686+ }
687+ }
688+
689+ meson_mmc_read_resp(host->mmc, cmd);
690+ if (!data || !data->stop || mrq->sbc)
691+ meson_mmc_request_done(host->mmc, mrq);
692+ else
693+ meson_mmc_start_cmd(host->mmc, data->stop);
694+
695+ return ret;
696+}
697+
698+/*
699+ * NOTE: we only need this until the GPIO/pinctrl driver can handle
700+ * interrupts. For now, the MMC core will use this for polling.
701+ */
702+static int meson_mmc_get_cd(struct mmc_host *mmc)
703+{
704+ int status = mmc_gpio_get_cd(mmc);
705+
706+ if (status == -ENOSYS)
707+ return 1; /* assume present */
708+
709+ return status;
710+}
711+
712+static const struct mmc_host_ops meson_mmc_ops = {
713+ .request = meson_mmc_request,
714+ .set_ios = meson_mmc_set_ios,
715+ .get_cd = meson_mmc_get_cd,
716+};
717+
718+static int meson_mmc_probe(struct platform_device *pdev)
719+{
720+ struct resource *res;
721+ struct meson_host *host;
722+ struct mmc_host *mmc;
723+ int ret;
724+
725+ mmc = mmc_alloc_host(sizeof(struct meson_host), &pdev->dev);
726+ if (!mmc)
727+ return -ENOMEM;
728+ host = mmc_priv(mmc);
729+ host->mmc = mmc;
730+ host->dev = &pdev->dev;
731+ dev_set_drvdata(&pdev->dev, host);
732+
733+ spin_lock_init(&host->lock);
734+
735+ /* Get regulators and the supported OCR mask */
736+ host->vqmmc_enabled = false;
737+ ret = mmc_regulator_get_supply(mmc);
738+ if (ret == -EPROBE_DEFER)
739+ goto free_host;
740+
741+ ret = mmc_of_parse(mmc);
742+ if (ret) {
743+ dev_warn(&pdev->dev, "error parsing DT: %d\n", ret);
744+ goto free_host;
745+ }
746+
747+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
748+ host->regs = devm_ioremap_resource(&pdev->dev, res);
749+ if (IS_ERR(host->regs)) {
750+ ret = PTR_ERR(host->regs);
751+ goto free_host;
752+ }
753+
754+ host->irq = platform_get_irq(pdev, 0);
755+ if (host->irq == 0) {
756+ dev_err(&pdev->dev, "failed to get interrupt resource.\n");
757+ ret = -EINVAL;
758+ goto free_host;
759+ }
760+
761+ host->core_clk = devm_clk_get(&pdev->dev, "core");
762+ if (IS_ERR(host->core_clk)) {
763+ ret = PTR_ERR(host->core_clk);
764+ goto free_host;
765+ }
766+
767+ ret = clk_prepare_enable(host->core_clk);
768+ if (ret)
769+ goto free_host;
770+
771+ ret = meson_mmc_clk_init(host);
772+ if (ret)
773+ goto free_host;
774+
775+ /* Stop execution */
776+ writel(0, host->regs + SD_EMMC_START);
777+
778+ /* clear, ack, enable all interrupts */
779+ writel(0, host->regs + SD_EMMC_IRQ_EN);
780+ writel(IRQ_EN_MASK, host->regs + SD_EMMC_STATUS);
781+
782+ ret = devm_request_threaded_irq(&pdev->dev, host->irq,
783+ meson_mmc_irq, meson_mmc_irq_thread,
784+ IRQF_SHARED, DRIVER_NAME, host);
785+ if (ret)
786+ goto free_host;
787+
788+ /* data bounce buffer */
789+ host->bounce_buf_size = SZ_512K;
790+ host->bounce_buf =
791+ dma_alloc_coherent(host->dev, host->bounce_buf_size,
792+ &host->bounce_dma_addr, GFP_KERNEL);
793+ if (host->bounce_buf == NULL) {
794+ dev_err(host->dev, "Unable to map allocate DMA bounce buffer.\n");
795+ ret = -ENOMEM;
796+ goto free_host;
797+ }
798+
799+ mmc->ops = &meson_mmc_ops;
800+ mmc_add_host(mmc);
801+
802+ return 0;
803+
804+free_host:
805+ clk_disable_unprepare(host->cfg_div_clk);
806+ clk_disable_unprepare(host->core_clk);
807+ mmc_free_host(mmc);
808+ return ret;
809+}
810+
811+static int meson_mmc_remove(struct platform_device *pdev)
812+{
813+ struct meson_host *host = dev_get_drvdata(&pdev->dev);
814+
815+ if (WARN_ON(!host))
816+ return 0;
817+
818+ if (host->bounce_buf)
819+ dma_free_coherent(host->dev, host->bounce_buf_size,
820+ host->bounce_buf, host->bounce_dma_addr);
821+
822+ clk_disable_unprepare(host->cfg_div_clk);
823+ clk_disable_unprepare(host->core_clk);
824+
825+ mmc_free_host(host->mmc);
826+ return 0;
827+}
828+
829+static const struct of_device_id meson_mmc_of_match[] = {
830+ { .compatible = "amlogic,meson-gx-mmc", },
831+ { .compatible = "amlogic,meson-gxbb-mmc", },
832+ { .compatible = "amlogic,meson-gxl-mmc", },
833+ { .compatible = "amlogic,meson-gxm-mmc", },
834+ {}
835+};
836+MODULE_DEVICE_TABLE(of, meson_mmc_of_match);
837+
838+static struct platform_driver meson_mmc_driver = {
839+ .probe = meson_mmc_probe,
840+ .remove = meson_mmc_remove,
841+ .driver = {
842+ .name = DRIVER_NAME,
843+ .of_match_table = of_match_ptr(meson_mmc_of_match),
844+ },
845+};
846+
847+module_platform_driver(meson_mmc_driver);
848+
849+MODULE_DESCRIPTION("Amlogic S905*/GX* SD/eMMC driver");
850+MODULE_AUTHOR("Kevin Hilman <khilman@baylibre.com>");
851+MODULE_LICENSE("GPL v2");
drivers/mmc/host/mmci.c+91−37
@@ -71,7 +71,12 @@ static unsigned int fmax = 515633; · 70 unmodified lines
7171 * @f_max: maximum clk frequency supported by the controller.
7272 * @signal_direction: input/out direction of bus signals can be indicated
7373 * @pwrreg_clkgate: MMCIPOWER register must be used to gate the clock
74− * @busy_detect: true if busy detection on dat0 is supported
74+ * @busy_detect: true if the variant supports busy detection on DAT0.
75+ * @busy_dpsm_flag: bitmask enabling busy detection in the DPSM
76+ * @busy_detect_flag: bitmask identifying the bit in the MMCISTATUS register
77+ * indicating that the card is busy
78+ * @busy_detect_mask: bitmask identifying the bit in the MMCIMASK0 to mask for
79+ * getting busy end detection interrupts
7580 * @pwrreg_nopower: bits in MMCIPOWER don't controls ext. power supply
7681 * @explicit_mclk_control: enable explicit mclk control in driver.
7782 * @qcom_fifo: enables qcom specific fifo pio read logic.
@@ -98,6 +103,9 @@ struct variant_data { · 20 unmodified lines
98103 bool signal_direction;
99104 bool pwrreg_clkgate;
100105 bool busy_detect;
106+ u32 busy_dpsm_flag;
107+ u32 busy_detect_flag;
108+ u32 busy_detect_mask;
101109 bool pwrreg_nopower;
102110 bool explicit_mclk_control;
103111 bool qcom_fifo;
@@ -137,7 +145,7 @@ static struct variant_data variant_u300 = { · 33 unmodified lines
137145 .clkreg_enable = MCI_ST_U300_HWFCEN,
138146 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,
139147 .datalength_bits = 16,
140− .datactrl_mask_sdio = MCI_ST_DPSM_SDIOEN,
148+ .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN,
141149 .st_sdio = true,
142150 .pwrreg_powerup = MCI_PWR_ON,
143151 .f_max = 100000000,
@@ -152,7 +160,7 @@ static struct variant_data variant_nomadik = { · 8 unmodified lines
152160 .clkreg = MCI_CLK_ENABLE,
153161 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,
154162 .datalength_bits = 24,
155− .datactrl_mask_sdio = MCI_ST_DPSM_SDIOEN,
163+ .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN,
156164 .st_sdio = true,
157165 .st_clkdiv = true,
158166 .pwrreg_powerup = MCI_PWR_ON,
@@ -170,7 +178,7 @@ static struct variant_data variant_ux500 = { · 11 unmodified lines
170178 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,
171179 .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE,
172180 .datalength_bits = 24,
173− .datactrl_mask_sdio = MCI_ST_DPSM_SDIOEN,
181+ .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN,
174182 .st_sdio = true,
175183 .st_clkdiv = true,
176184 .pwrreg_powerup = MCI_PWR_ON,
@@ -178,6 +186,9 @@ static struct variant_data variant_ux500 = { · 1 unmodified line
178186 .signal_direction = true,
179187 .pwrreg_clkgate = true,
180188 .busy_detect = true,
189+ .busy_dpsm_flag = MCI_DPSM_ST_BUSYMODE,
190+ .busy_detect_flag = MCI_ST_CARDBUSY,
191+ .busy_detect_mask = MCI_ST_BUSYENDMASK,
181192 .pwrreg_nopower = true,
182193 };
183194
@@ -188,9 +199,9 @@ static struct variant_data variant_ux500v2 = { · 4 unmodified lines
188199 .clkreg_enable = MCI_ST_UX500_HWFCEN,
189200 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,
190201 .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE,
191− .datactrl_mask_ddrmode = MCI_ST_DPSM_DDRMODE,
202+ .datactrl_mask_ddrmode = MCI_DPSM_ST_DDRMODE,
192203 .datalength_bits = 24,
193− .datactrl_mask_sdio = MCI_ST_DPSM_SDIOEN,
204+ .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN,
194205 .st_sdio = true,
195206 .st_clkdiv = true,
196207 .blksz_datactrl16 = true,
@@ -199,6 +210,9 @@ static struct variant_data variant_ux500v2 = { · 2 unmodified lines
199210 .signal_direction = true,
200211 .pwrreg_clkgate = true,
201212 .busy_detect = true,
213+ .busy_dpsm_flag = MCI_DPSM_ST_BUSYMODE,
214+ .busy_detect_flag = MCI_ST_CARDBUSY,
215+ .busy_detect_mask = MCI_ST_BUSYENDMASK,
202216 .pwrreg_nopower = true,
203217 };
204218
@@ -210,7 +224,7 @@ static struct variant_data variant_qcom = { · 5 unmodified lines
210224 MCI_QCOM_CLK_SELECT_IN_FBCLK,
211225 .clkreg_8bit_bus_enable = MCI_QCOM_CLK_WIDEBUS_8,
212226 .datactrl_mask_ddrmode = MCI_QCOM_CLK_SELECT_IN_DDR_MODE,
213− .data_cmd_enable = MCI_QCOM_CSPM_DATCMD,
227+ .data_cmd_enable = MCI_CPSM_QCOM_DATCMD,
214228 .blksz_datactrl4 = true,
215229 .datalength_bits = 24,
216230 .pwrreg_powerup = MCI_PWR_UP,
@@ -220,6 +234,7 @@ static struct variant_data variant_qcom = { · 3 unmodified lines
220234 .qcom_dml = true,
221235 };
222236
237+/* Busy detection for the ST Micro variant */
223238 static int mmci_card_busy(struct mmc_host *mmc)
224239 {
225240 struct mmci_host *host = mmc_priv(mmc);
@@ -227,7 +242,7 @@ static int mmci_card_busy(struct mmc_host *mmc) · 1 unmodified line
227242 int busy = 0;
228243
229244 spin_lock_irqsave(&host->lock, flags);
230− if (readl(host->base + MMCISTATUS) & MCI_ST_CARDBUSY)
245+ if (readl(host->base + MMCISTATUS) & host->variant->busy_detect_flag)
231246 busy = 1;
232247 spin_unlock_irqrestore(&host->lock, flags);
233248
@@ -294,8 +309,8 @@ static void mmci_write_pwrreg(struct mmci_host *host, u32 pwr) · 60 unmodified lines
294309 */
295310 static void mmci_write_datactrlreg(struct mmci_host *host, u32 datactrl)
296311 {
297− /* Keep ST Micro busy mode if enabled */
298− datactrl |= host->datactrl_reg & MCI_ST_DPSM_BUSYMODE;
312+ /* Keep busy mode in DPSM if enabled */
313+ datactrl |= host->datactrl_reg & host->variant->busy_dpsm_flag;
299314
300315 if (host->datactrl_reg != datactrl) {
301316 host->datactrl_reg = datactrl;
@@ -684,8 +699,7 @@ static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data) · 382 unmodified lines
684699 next->dma_chan = NULL;
685700 }
686701
687−static void mmci_pre_request(struct mmc_host *mmc, struct mmc_request *mrq,
688− bool is_first_req)
702+static void mmci_pre_request(struct mmc_host *mmc, struct mmc_request *mrq)
689703 {
690704 struct mmci_host *host = mmc_priv(mmc);
691705 struct mmc_data *data = mrq->data;
@@ -973,37 +987,66 @@ mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd, · 281 unmodified lines
973987 unsigned int status)
974988 {
975989 void __iomem *base = host->base;
976− bool sbc, busy_resp;
990+ bool sbc;
977991
978992 if (!cmd)
979993 return;
980994
981995 sbc = (cmd == host->mrq->sbc);
982− busy_resp = host->variant->busy_detect && (cmd->flags & MMC_RSP_BUSY);
983996
984− if (!((status|host->busy_status) & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT|
985− MCI_CMDSENT|MCI_CMDRESPEND)))
997+ /*
998+ * We need to be one of these interrupts to be considered worth
999+ * handling. Note that we tag on any latent IRQs postponed
1000+ * due to waiting for busy status.
1001+ */
1002+ if (!((status|host->busy_status) &
1003+ (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT|MCI_CMDSENT|MCI_CMDRESPEND)))
9861004 return;
9871005
988− /* Check if we need to wait for busy completion. */
989− if (host->busy_status && (status & MCI_ST_CARDBUSY))
990− return;
1006+ /*
1007+ * ST Micro variant: handle busy detection.
1008+ */
1009+ if (host->variant->busy_detect) {
1010+ bool busy_resp = !!(cmd->flags & MMC_RSP_BUSY);
9911011
992− /* Enable busy completion if needed and supported. */
993− if (!host->busy_status && busy_resp &&
994− !(status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT)) &&
995− (readl(base + MMCISTATUS) & MCI_ST_CARDBUSY)) {
996− writel(readl(base + MMCIMASK0) | MCI_ST_BUSYEND,
997− base + MMCIMASK0);
998− host->busy_status = status & (MCI_CMDSENT|MCI_CMDRESPEND);
999− return;
1000− }
1012+ /* We are busy with a command, return */
1013+ if (host->busy_status &&
1014+ (status & host->variant->busy_detect_flag))
1015+ return;
1016+
1017+ /*
1018+ * We were not busy, but we now got a busy response on
1019+ * something that was not an error, and we double-check
1020+ * that the special busy status bit is still set before
1021+ * proceeding.
1022+ */
1023+ if (!host->busy_status && busy_resp &&
1024+ !(status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT)) &&
1025+ (readl(base + MMCISTATUS) & host->variant->busy_detect_flag)) {
1026+ /* Unmask the busy IRQ */
1027+ writel(readl(base + MMCIMASK0) |
1028+ host->variant->busy_detect_mask,
1029+ base + MMCIMASK0);
1030+ /*
1031+ * Now cache the last response status code (until
1032+ * the busy bit goes low), and return.
1033+ */
1034+ host->busy_status =
1035+ status & (MCI_CMDSENT|MCI_CMDRESPEND);
1036+ return;
1037+ }
10011038
1002− /* At busy completion, mask the IRQ and complete the request. */
1003− if (host->busy_status) {
1004− writel(readl(base + MMCIMASK0) & ~MCI_ST_BUSYEND,
1005− base + MMCIMASK0);
1006− host->busy_status = 0;
1039+ /*
1040+ * At this point we are not busy with a command, we have
1041+ * not received a new busy request, mask the busy IRQ and
1042+ * fall through to process the IRQ.
1043+ */
1044+ if (host->busy_status) {
1045+ writel(readl(base + MMCIMASK0) &
1046+ ~host->variant->busy_detect_mask,
1047+ base + MMCIMASK0);
1048+ host->busy_status = 0;
1049+ }
10071050 }
10081051
10091052 host->cmd = NULL;
@@ -1257,9 +1300,11 @@ static irqreturn_t mmci_irq(int irq, void *dev_id) · 247 unmodified lines
12571300 mmci_data_irq(host, host->data, status);
12581301 }
12591302
1260− /* Don't poll for busy completion in irq context. */
1261− if (host->busy_status)
1262− status &= ~MCI_ST_CARDBUSY;
1303+ /*
1304+ * Don't poll for busy completion in irq context.
1305+ */
1306+ if (host->variant->busy_detect && host->busy_status)
1307+ status &= ~host->variant->busy_detect_flag;
12631308
12641309 ret = 1;
12651310 } while (status);
@@ -1612,9 +1657,18 @@ static int mmci_probe(struct amba_device *dev, · 346 unmodified lines
16121657 /* We support these capabilities. */
16131658 mmc->caps |= MMC_CAP_CMD23;
16141659
1660+ /*
1661+ * Enable busy detection.
1662+ */
16151663 if (variant->busy_detect) {
16161664 mmci_ops.card_busy = mmci_card_busy;
1617− mmci_write_datactrlreg(host, MCI_ST_DPSM_BUSYMODE);
1665+ /*
1666+ * Not all variants have a flag to enable busy detection
1667+ * in the DPSM, but if they do, set it here.
1668+ */
1669+ if (variant->busy_dpsm_flag)
1670+ mmci_write_datactrlreg(host,
1671+ host->variant->busy_dpsm_flag);
16181672 mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY;
16191673 mmc->max_busy_timeout = 0;
16201674 }
drivers/mmc/host/mmci.h+39−32
@@ -51,25 +51,27 @@ · 50 unmodified lines
5151 #define MCI_QCOM_CLK_SELECT_IN_DDR_MODE (BIT(14) | BIT(15))
5252
5353 #define MMCIARGUMENT 0x008
54−#define MMCICOMMAND 0x00c
55−#define MCI_CPSM_RESPONSE (1 << 6)
56−#define MCI_CPSM_LONGRSP (1 << 7)
57−#define MCI_CPSM_INTERRUPT (1 << 8)
58−#define MCI_CPSM_PENDING (1 << 9)
59−#define MCI_CPSM_ENABLE (1 << 10)
60−/* Argument flag extenstions in the ST Micro versions */
61−#define MCI_ST_SDIO_SUSP (1 << 11)
62−#define MCI_ST_ENCMD_COMPL (1 << 12)
63−#define MCI_ST_NIEN (1 << 13)
64−#define MCI_ST_CE_ATACMD (1 << 14)
6554
66−/* Modified on Qualcomm Integrations */
67−#define MCI_QCOM_CSPM_DATCMD BIT(12)
68−#define MCI_QCOM_CSPM_MCIABORT BIT(13)
69−#define MCI_QCOM_CSPM_CCSENABLE BIT(14)
70−#define MCI_QCOM_CSPM_CCSDISABLE BIT(15)
71−#define MCI_QCOM_CSPM_AUTO_CMD19 BIT(16)
72−#define MCI_QCOM_CSPM_AUTO_CMD21 BIT(21)
55+/* The command register controls the Command Path State Machine (CPSM) */
56+#define MMCICOMMAND 0x00c
57+#define MCI_CPSM_RESPONSE BIT(6)
58+#define MCI_CPSM_LONGRSP BIT(7)
59+#define MCI_CPSM_INTERRUPT BIT(8)
60+#define MCI_CPSM_PENDING BIT(9)
61+#define MCI_CPSM_ENABLE BIT(10)
62+/* Command register flag extenstions in the ST Micro versions */
63+#define MCI_CPSM_ST_SDIO_SUSP BIT(11)
64+#define MCI_CPSM_ST_ENCMD_COMPL BIT(12)
65+#define MCI_CPSM_ST_NIEN BIT(13)
66+#define MCI_CPSM_ST_CE_ATACMD BIT(14)
67+/* Command register flag extensions in the Qualcomm versions */
68+#define MCI_CPSM_QCOM_PROGENA BIT(11)
69+#define MCI_CPSM_QCOM_DATCMD BIT(12)
70+#define MCI_CPSM_QCOM_MCIABORT BIT(13)
71+#define MCI_CPSM_QCOM_CCSENABLE BIT(14)
72+#define MCI_CPSM_QCOM_CCSDISABLE BIT(15)
73+#define MCI_CPSM_QCOM_AUTO_CMD19 BIT(16)
74+#define MCI_CPSM_QCOM_AUTO_CMD21 BIT(21)
7375
7476 #define MMCIRESPCMD 0x010
7577 #define MMCIRESPONSE0 0x014
@@ -78,22 +80,27 @@ · 2 unmodified lines
7880 #define MMCIRESPONSE3 0x020
7981 #define MMCIDATATIMER 0x024
8082 #define MMCIDATALENGTH 0x028
83+
84+/* The data control register controls the Data Path State Machine (DPSM) */
8185 #define MMCIDATACTRL 0x02c
82−#define MCI_DPSM_ENABLE (1 << 0)
83−#define MCI_DPSM_DIRECTION (1 << 1)
84−#define MCI_DPSM_MODE (1 << 2)
85−#define MCI_DPSM_DMAENABLE (1 << 3)
86−#define MCI_DPSM_BLOCKSIZE (1 << 4)
86+#define MCI_DPSM_ENABLE BIT(0)
87+#define MCI_DPSM_DIRECTION BIT(1)
88+#define MCI_DPSM_MODE BIT(2)
89+#define MCI_DPSM_DMAENABLE BIT(3)
90+#define MCI_DPSM_BLOCKSIZE BIT(4)
8791 /* Control register extensions in the ST Micro U300 and Ux500 versions */
88−#define MCI_ST_DPSM_RWSTART (1 << 8)
89−#define MCI_ST_DPSM_RWSTOP (1 << 9)
90−#define MCI_ST_DPSM_RWMOD (1 << 10)
91−#define MCI_ST_DPSM_SDIOEN (1 << 11)
92+#define MCI_DPSM_ST_RWSTART BIT(8)
93+#define MCI_DPSM_ST_RWSTOP BIT(9)
94+#define MCI_DPSM_ST_RWMOD BIT(10)
95+#define MCI_DPSM_ST_SDIOEN BIT(11)
9296 /* Control register extensions in the ST Micro Ux500 versions */
93−#define MCI_ST_DPSM_DMAREQCTL (1 << 12)
94−#define MCI_ST_DPSM_DBOOTMODEEN (1 << 13)
95−#define MCI_ST_DPSM_BUSYMODE (1 << 14)
96−#define MCI_ST_DPSM_DDRMODE (1 << 15)
97+#define MCI_DPSM_ST_DMAREQCTL BIT(12)
98+#define MCI_DPSM_ST_DBOOTMODEEN BIT(13)
99+#define MCI_DPSM_ST_BUSYMODE BIT(14)
100+#define MCI_DPSM_ST_DDRMODE BIT(15)
101+/* Control register extensions in the Qualcomm versions */
102+#define MCI_DPSM_QCOM_DATA_PEND BIT(17)
103+#define MCI_DPSM_QCOM_RX_DATA_PEND BIT(20)
97104
98105 #define MMCIDATACNT 0x030
99106 #define MMCISTATUS 0x034
@@ -167,7 +174,7 @@ · 67 unmodified lines
167174 /* Extended status bits for the ST Micro variants */
168175 #define MCI_ST_SDIOITMASK (1 << 22)
169176 #define MCI_ST_CEATAENDMASK (1 << 23)
170−#define MCI_ST_BUSYEND (1 << 24)
177+#define MCI_ST_BUSYENDMASK (1 << 24)
171178
172179 #define MMCIMASK1 0x040
173180 #define MMCIFIFOCNT 0x048
drivers/mmc/host/mtk-sd.c+2−2
@@ -927,8 +927,7 @@ static void msdc_ops_request(struct mmc_host *mmc, struct mmc_request *mrq) · 926 unmodified lines
927927 msdc_start_command(host, mrq, mrq->cmd);
928928 }
929929
930−static void msdc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
931− bool is_first_req)
930+static void msdc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq)
932931 {
933932 struct msdc_host *host = mmc_priv(mmc);
934933 struct mmc_data *data = mrq->data;
@@ -1713,6 +1712,7 @@ static const struct of_device_id msdc_of_ids[] = { · 778 unmodified lines
17131712 { .compatible = "mediatek,mt8135-mmc", },
17141713 {}
17151714 };
1715+MODULE_DEVICE_TABLE(of, msdc_of_ids);
17161716
17171717 static struct platform_driver mt_msdc_driver = {
17181718 .probe = msdc_drv_probe,
drivers/mmc/host/omap_hsmmc.c+1−2
@@ -1565,8 +1565,7 @@ static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq, · 1564 unmodified lines
15651565 }
15661566 }
15671567
1568−static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
1569− bool is_first_req)
1568+static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq)
15701569 {
15711570 struct omap_hsmmc_host *host = mmc_priv(mmc);
15721571
drivers/mmc/host/rtsx_pci_sdmmc.c+1−2
@@ -190,8 +190,7 @@ static int sd_pre_dma_transfer(struct realtek_pci_sdmmc *host, · 189 unmodified lines
190190 return using_cookie;
191191 }
192192
193−static void sdmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
194− bool is_first_req)
193+static void sdmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq)
195194 {
196195 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
197196 struct mmc_data *data = mrq->data;
drivers/mmc/host/rtsx_usb_sdmmc.c+3−0
@@ -1374,6 +1374,8 @@ static int rtsx_usb_sdmmc_drv_probe(struct platform_device *pdev) · 1373 unmodified lines
13741374
13751375 mutex_init(&host->host_mutex);
13761376 rtsx_usb_init_host(host);
1377+ pm_runtime_use_autosuspend(&pdev->dev);
1378+ pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
13771379 pm_runtime_enable(&pdev->dev);
13781380
13791381 #ifdef RTSX_USB_USE_LEDS_CLASS
@@ -1428,6 +1430,7 @@ static int rtsx_usb_sdmmc_drv_remove(struct platform_device *pdev) · 48 unmodified lines
14281430
14291431 mmc_free_host(mmc);
14301432 pm_runtime_disable(&pdev->dev);
1433+ pm_runtime_dont_use_autosuspend(&pdev->dev);
14311434 platform_set_drvdata(pdev, NULL);
14321435
14331436 dev_dbg(&(pdev->dev),
drivers/mmc/host/s3cmci.c+4−11
@@ -28,7 +28,6 @@ · 27 unmodified lines
2828 #include <mach/dma.h>
2929 #include <mach/gpio-samsung.h>
3030
31−#include <linux/platform_data/dma-s3c24xx.h>
3231 #include <linux/platform_data/mmc-s3cmci.h>
3332
3433 #include "s3cmci.h"
@@ -1682,19 +1681,13 @@ static int s3cmci_probe(struct platform_device *pdev) · 1647 unmodified lines
16821681 gpio_direction_input(host->pdata->gpio_wprotect);
16831682 }
16841683
1685− /* depending on the dma state, get a dma channel to use. */
1684+ /* Depending on the dma state, get a DMA channel to use. */
16861685
16871686 if (s3cmci_host_usedma(host)) {
1688− dma_cap_mask_t mask;
1689−
1690− dma_cap_zero(mask);
1691− dma_cap_set(DMA_SLAVE, mask);
1692−
1693− host->dma = dma_request_slave_channel_compat(mask,
1694− s3c24xx_dma_filter, (void *)DMACH_SDI, &pdev->dev, "rx-tx");
1695− if (!host->dma) {
1687+ host->dma = dma_request_chan(&pdev->dev, "rx-tx");
1688+ ret = PTR_ERR_OR_ZERO(host->dma);
1689+ if (ret) {
16961690 dev_err(&pdev->dev, "cannot get DMA channel.\n");
1697− ret = -EBUSY;
16981691 goto probe_free_gpio_wp;
16991692 }
17001693 }
drivers/mmc/host/sdhci-acpi.c+1−0
@@ -328,6 +328,7 @@ static const struct sdhci_acpi_uid_slot sdhci_acpi_uids[] = { · 327 unmodified lines
328328 { "80865ACC", NULL, &sdhci_acpi_slot_int_emmc },
329329 { "80865AD0", NULL, &sdhci_acpi_slot_int_sdio },
330330 { "80860F14" , "1" , &sdhci_acpi_slot_int_emmc },
331+ { "80860F14" , "2" , &sdhci_acpi_slot_int_sdio },
331332 { "80860F14" , "3" , &sdhci_acpi_slot_int_sd },
332333 { "80860F16" , NULL, &sdhci_acpi_slot_int_sd },
333334 { "INT33BB" , "2" , &sdhci_acpi_slot_int_sdio },
drivers/mmc/host/sdhci-cadence.c+283−0
@@ -0,0 +1,283 @@
1+/*
2+ * Copyright (C) 2016 Socionext Inc.
3+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
4+ *
5+ * This program is free software; you can redistribute it and/or modify
6+ * it under the terms of the GNU General Public License as published by
7+ * the Free Software Foundation; either version 2 of the License, or
8+ * (at your option) any later version.
9+ *
10+ * This program is distributed in the hope that it will be useful,
11+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
12+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13+ * GNU General Public License for more details.
14+ */
15+
16+#include <linux/bitops.h>
17+#include <linux/iopoll.h>
18+#include <linux/module.h>
19+#include <linux/mmc/host.h>
20+
21+#include "sdhci-pltfm.h"
22+
23+/* HRS - Host Register Set (specific to Cadence) */
24+#define SDHCI_CDNS_HRS04 0x10 /* PHY access port */
25+#define SDHCI_CDNS_HRS04_ACK BIT(26)
26+#define SDHCI_CDNS_HRS04_RD BIT(25)
27+#define SDHCI_CDNS_HRS04_WR BIT(24)
28+#define SDHCI_CDNS_HRS04_RDATA_SHIFT 12
29+#define SDHCI_CDNS_HRS04_WDATA_SHIFT 8
30+#define SDHCI_CDNS_HRS04_ADDR_SHIFT 0
31+
32+#define SDHCI_CDNS_HRS06 0x18 /* eMMC control */
33+#define SDHCI_CDNS_HRS06_TUNE_UP BIT(15)
34+#define SDHCI_CDNS_HRS06_TUNE_SHIFT 8
35+#define SDHCI_CDNS_HRS06_TUNE_MASK 0x3f
36+#define SDHCI_CDNS_HRS06_MODE_MASK 0x7
37+#define SDHCI_CDNS_HRS06_MODE_SD 0x0
38+#define SDHCI_CDNS_HRS06_MODE_MMC_SDR 0x2
39+#define SDHCI_CDNS_HRS06_MODE_MMC_DDR 0x3
40+#define SDHCI_CDNS_HRS06_MODE_MMC_HS200 0x4
41+#define SDHCI_CDNS_HRS06_MODE_MMC_HS400 0x5
42+
43+/* SRS - Slot Register Set (SDHCI-compatible) */
44+#define SDHCI_CDNS_SRS_BASE 0x200
45+
46+/* PHY */
47+#define SDHCI_CDNS_PHY_DLY_SD_HS 0x00
48+#define SDHCI_CDNS_PHY_DLY_SD_DEFAULT 0x01
49+#define SDHCI_CDNS_PHY_DLY_UHS_SDR12 0x02
50+#define SDHCI_CDNS_PHY_DLY_UHS_SDR25 0x03
51+#define SDHCI_CDNS_PHY_DLY_UHS_SDR50 0x04
52+#define SDHCI_CDNS_PHY_DLY_UHS_DDR50 0x05
53+#define SDHCI_CDNS_PHY_DLY_EMMC_LEGACY 0x06
54+#define SDHCI_CDNS_PHY_DLY_EMMC_SDR 0x07
55+#define SDHCI_CDNS_PHY_DLY_EMMC_DDR 0x08
56+
57+/*
58+ * The tuned val register is 6 bit-wide, but not the whole of the range is
59+ * available. The range 0-42 seems to be available (then 43 wraps around to 0)
60+ * but I am not quite sure if it is official. Use only 0 to 39 for safety.
61+ */
62+#define SDHCI_CDNS_MAX_TUNING_LOOP 40
63+
64+struct sdhci_cdns_priv {
65+ void __iomem *hrs_addr;
66+};
67+
68+static void sdhci_cdns_write_phy_reg(struct sdhci_cdns_priv *priv,
69+ u8 addr, u8 data)
70+{
71+ void __iomem *reg = priv->hrs_addr + SDHCI_CDNS_HRS04;
72+ u32 tmp;
73+
74+ tmp = (data << SDHCI_CDNS_HRS04_WDATA_SHIFT) |
75+ (addr << SDHCI_CDNS_HRS04_ADDR_SHIFT);
76+ writel(tmp, reg);
77+
78+ tmp |= SDHCI_CDNS_HRS04_WR;
79+ writel(tmp, reg);
80+
81+ tmp &= ~SDHCI_CDNS_HRS04_WR;
82+ writel(tmp, reg);
83+}
84+
85+static void sdhci_cdns_phy_init(struct sdhci_cdns_priv *priv)
86+{
87+ sdhci_cdns_write_phy_reg(priv, SDHCI_CDNS_PHY_DLY_SD_HS, 4);
88+ sdhci_cdns_write_phy_reg(priv, SDHCI_CDNS_PHY_DLY_SD_DEFAULT, 4);
89+ sdhci_cdns_write_phy_reg(priv, SDHCI_CDNS_PHY_DLY_EMMC_LEGACY, 9);
90+ sdhci_cdns_write_phy_reg(priv, SDHCI_CDNS_PHY_DLY_EMMC_SDR, 2);
91+ sdhci_cdns_write_phy_reg(priv, SDHCI_CDNS_PHY_DLY_EMMC_DDR, 3);
92+}
93+
94+static inline void *sdhci_cdns_priv(struct sdhci_host *host)
95+{
96+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
97+
98+ return sdhci_pltfm_priv(pltfm_host);
99+}
100+
101+static unsigned int sdhci_cdns_get_timeout_clock(struct sdhci_host *host)
102+{
103+ /*
104+ * Cadence's spec says the Timeout Clock Frequency is the same as the
105+ * Base Clock Frequency. Divide it by 1000 to return a value in kHz.
106+ */
107+ return host->max_clk / 1000;
108+}
109+
110+static void sdhci_cdns_set_uhs_signaling(struct sdhci_host *host,
111+ unsigned int timing)
112+{
113+ struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host);
114+ u32 mode, tmp;
115+
116+ switch (timing) {
117+ case MMC_TIMING_MMC_HS:
118+ mode = SDHCI_CDNS_HRS06_MODE_MMC_SDR;
119+ break;
120+ case MMC_TIMING_MMC_DDR52:
121+ mode = SDHCI_CDNS_HRS06_MODE_MMC_DDR;
122+ break;
123+ case MMC_TIMING_MMC_HS200:
124+ mode = SDHCI_CDNS_HRS06_MODE_MMC_HS200;
125+ break;
126+ case MMC_TIMING_MMC_HS400:
127+ mode = SDHCI_CDNS_HRS06_MODE_MMC_HS400;
128+ break;
129+ default:
130+ mode = SDHCI_CDNS_HRS06_MODE_SD;
131+ break;
132+ }
133+
134+ /* The speed mode for eMMC is selected by HRS06 register */
135+ tmp = readl(priv->hrs_addr + SDHCI_CDNS_HRS06);
136+ tmp &= ~SDHCI_CDNS_HRS06_MODE_MASK;
137+ tmp |= mode;
138+ writel(tmp, priv->hrs_addr + SDHCI_CDNS_HRS06);
139+
140+ /* For SD, fall back to the default handler */
141+ if (mode == SDHCI_CDNS_HRS06_MODE_SD)
142+ sdhci_set_uhs_signaling(host, timing);
143+}
144+
145+static const struct sdhci_ops sdhci_cdns_ops = {
146+ .set_clock = sdhci_set_clock,
147+ .get_timeout_clock = sdhci_cdns_get_timeout_clock,
148+ .set_bus_width = sdhci_set_bus_width,
149+ .reset = sdhci_reset,
150+ .set_uhs_signaling = sdhci_cdns_set_uhs_signaling,
151+};
152+
153+static const struct sdhci_pltfm_data sdhci_cdns_pltfm_data = {
154+ .ops = &sdhci_cdns_ops,
155+};
156+
157+static int sdhci_cdns_set_tune_val(struct sdhci_host *host, unsigned int val)
158+{
159+ struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host);
160+ void __iomem *reg = priv->hrs_addr + SDHCI_CDNS_HRS06;
161+ u32 tmp;
162+
163+ if (WARN_ON(val > SDHCI_CDNS_HRS06_TUNE_MASK))
164+ return -EINVAL;
165+
166+ tmp = readl(reg);
167+ tmp &= ~(SDHCI_CDNS_HRS06_TUNE_MASK << SDHCI_CDNS_HRS06_TUNE_SHIFT);
168+ tmp |= val << SDHCI_CDNS_HRS06_TUNE_SHIFT;
169+ tmp |= SDHCI_CDNS_HRS06_TUNE_UP;
170+ writel(tmp, reg);
171+
172+ return readl_poll_timeout(reg, tmp, !(tmp & SDHCI_CDNS_HRS06_TUNE_UP),
173+ 0, 1);
174+}
175+
176+static int sdhci_cdns_execute_tuning(struct mmc_host *mmc, u32 opcode)
177+{
178+ struct sdhci_host *host = mmc_priv(mmc);
179+ int cur_streak = 0;
180+ int max_streak = 0;
181+ int end_of_streak = 0;
182+ int i;
183+
184+ /*
185+ * This handler only implements the eMMC tuning that is specific to
186+ * this controller. Fall back to the standard method for SD timing.
187+ */
188+ if (host->timing != MMC_TIMING_MMC_HS200)
189+ return sdhci_execute_tuning(mmc, opcode);
190+
191+ if (WARN_ON(opcode != MMC_SEND_TUNING_BLOCK_HS200))
192+ return -EINVAL;
193+
194+ for (i = 0; i < SDHCI_CDNS_MAX_TUNING_LOOP; i++) {
195+ if (sdhci_cdns_set_tune_val(host, i) ||
196+ mmc_send_tuning(host->mmc, opcode, NULL)) { /* bad */
197+ cur_streak = 0;
198+ } else { /* good */
199+ cur_streak++;
200+ if (cur_streak > max_streak) {
201+ max_streak = cur_streak;
202+ end_of_streak = i;
203+ }
204+ }
205+ }
206+
207+ if (!max_streak) {
208+ dev_err(mmc_dev(host->mmc), "no tuning point found\n");
209+ return -EIO;
210+ }
211+
212+ return sdhci_cdns_set_tune_val(host, end_of_streak - max_streak / 2);
213+}
214+
215+static int sdhci_cdns_probe(struct platform_device *pdev)
216+{
217+ struct sdhci_host *host;
218+ struct sdhci_pltfm_host *pltfm_host;
219+ struct sdhci_cdns_priv *priv;
220+ struct clk *clk;
221+ int ret;
222+
223+ clk = devm_clk_get(&pdev->dev, NULL);
224+ if (IS_ERR(clk))
225+ return PTR_ERR(clk);
226+
227+ ret = clk_prepare_enable(clk);
228+ if (ret)
229+ return ret;
230+
231+ host = sdhci_pltfm_init(pdev, &sdhci_cdns_pltfm_data, sizeof(*priv));
232+ if (IS_ERR(host)) {
233+ ret = PTR_ERR(host);
234+ goto disable_clk;
235+ }
236+
237+ pltfm_host = sdhci_priv(host);
238+ pltfm_host->clk = clk;
239+
240+ priv = sdhci_cdns_priv(host);
241+ priv->hrs_addr = host->ioaddr;
242+ host->ioaddr += SDHCI_CDNS_SRS_BASE;
243+ host->mmc_host_ops.execute_tuning = sdhci_cdns_execute_tuning;
244+
245+ ret = mmc_of_parse(host->mmc);
246+ if (ret)
247+ goto free;
248+
249+ sdhci_cdns_phy_init(priv);
250+
251+ ret = sdhci_add_host(host);
252+ if (ret)
253+ goto free;
254+
255+ return 0;
256+free:
257+ sdhci_pltfm_free(pdev);
258+disable_clk:
259+ clk_disable_unprepare(clk);
260+
261+ return ret;
262+}
263+
264+static const struct of_device_id sdhci_cdns_match[] = {
265+ { .compatible = "cdns,sd4hc" },
266+ { /* sentinel */ }
267+};
268+MODULE_DEVICE_TABLE(of, sdhci_cdns_match);
269+
270+static struct platform_driver sdhci_cdns_driver = {
271+ .driver = {
272+ .name = "sdhci-cdns",
273+ .pm = &sdhci_pltfm_pmops,
274+ .of_match_table = sdhci_cdns_match,
275+ },
276+ .probe = sdhci_cdns_probe,
277+ .remove = sdhci_pltfm_unregister,
278+};
279+module_platform_driver(sdhci_cdns_driver);
280+
281+MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>");
282+MODULE_DESCRIPTION("Cadence SD/SDIO/eMMC Host Controller Driver");
283+MODULE_LICENSE("GPL");
drivers/mmc/host/sdhci-iproc.c+33−2
@@ -143,6 +143,14 @@ static void sdhci_iproc_writeb(struct sdhci_host *host, u8 val, int reg) · 142 unmodified lines
143143 }
144144
145145 static const struct sdhci_ops sdhci_iproc_ops = {
146+ .set_clock = sdhci_set_clock,
147+ .get_max_clock = sdhci_pltfm_clk_get_max_clock,
148+ .set_bus_width = sdhci_set_bus_width,
149+ .reset = sdhci_reset,
150+ .set_uhs_signaling = sdhci_set_uhs_signaling,
151+};
152+
153+static const struct sdhci_ops sdhci_iproc_32only_ops = {
146154 .read_l = sdhci_iproc_readl,
147155 .read_w = sdhci_iproc_readw,
148156 .read_b = sdhci_iproc_readb,
@@ -156,6 +164,28 @@ static const struct sdhci_ops sdhci_iproc_ops = { · 7 unmodified lines
156164 .set_uhs_signaling = sdhci_set_uhs_signaling,
157165 };
158166
167+static const struct sdhci_pltfm_data sdhci_iproc_cygnus_pltfm_data = {
168+ .quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK,
169+ .quirks2 = SDHCI_QUIRK2_ACMD23_BROKEN,
170+ .ops = &sdhci_iproc_32only_ops,
171+};
172+
173+static const struct sdhci_iproc_data iproc_cygnus_data = {
174+ .pdata = &sdhci_iproc_cygnus_pltfm_data,
175+ .caps = ((0x1 << SDHCI_MAX_BLOCK_SHIFT)
176+ & SDHCI_MAX_BLOCK_MASK) |
177+ SDHCI_CAN_VDD_330 |
178+ SDHCI_CAN_VDD_180 |
179+ SDHCI_CAN_DO_SUSPEND |
180+ SDHCI_CAN_DO_HISPD |
181+ SDHCI_CAN_DO_ADMA2 |
182+ SDHCI_CAN_DO_SDMA,
183+ .caps1 = SDHCI_DRIVER_TYPE_C |
184+ SDHCI_DRIVER_TYPE_D |
185+ SDHCI_SUPPORT_DDR50,
186+ .mmc_caps = MMC_CAP_1_8V_DDR,
187+};
188+
159189 static const struct sdhci_pltfm_data sdhci_iproc_pltfm_data = {
160190 .quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK,
161191 .quirks2 = SDHCI_QUIRK2_ACMD23_BROKEN,
@@ -182,7 +212,7 @@ static const struct sdhci_pltfm_data sdhci_bcm2835_pltfm_data = { · 20 unmodified lines
182212 .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION |
183213 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
184214 SDHCI_QUIRK_MISSING_CAPS,
185− .ops = &sdhci_iproc_ops,
215+ .ops = &sdhci_iproc_32only_ops,
186216 };
187217
188218 static const struct sdhci_iproc_data bcm2835_data = {
@@ -194,7 +224,8 @@ static const struct sdhci_iproc_data bcm2835_data = { · 5 unmodified lines
194224
195225 static const struct of_device_id sdhci_iproc_of_match[] = {
196226 { .compatible = "brcm,bcm2835-sdhci", .data = &bcm2835_data },
197− { .compatible = "brcm,sdhci-iproc-cygnus", .data = &iproc_data },
227+ { .compatible = "brcm,sdhci-iproc-cygnus", .data = &iproc_cygnus_data},
228+ { .compatible = "brcm,sdhci-iproc", .data = &iproc_data },
198229 { }
199230 };
200231 MODULE_DEVICE_TABLE(of, sdhci_iproc_of_match);
drivers/mmc/host/sdhci-msm.c+651−43
@@ -18,7 +18,9 @@ · 17 unmodified lines
1818 #include <linux/of_device.h>
1919 #include <linux/delay.h>
2020 #include <linux/mmc/mmc.h>
21+#include <linux/pm_runtime.h>
2122 #include <linux/slab.h>
23+#include <linux/iopoll.h>
2224
2325 #include "sdhci-pltfm.h"
2426
@@ -31,6 +33,7 @@ · 6 unmodified lines
3133 #define HC_MODE_EN 0x1
3234 #define CORE_POWER 0x0
3335 #define CORE_SW_RST BIT(7)
36+#define FF_CLK_SW_RST_DIS BIT(13)
3437
3538 #define CORE_PWRCTL_STATUS 0xdc
3639 #define CORE_PWRCTL_MASK 0xe0
@@ -49,6 +52,7 @@ · 12 unmodified lines
4952 #define INT_MASK 0xf
5053 #define MAX_PHASES 16
5154 #define CORE_DLL_LOCK BIT(7)
55+#define CORE_DDR_DLL_LOCK BIT(11)
5256 #define CORE_DLL_EN BIT(16)
5357 #define CORE_CDR_EN BIT(17)
5458 #define CORE_CK_OUT_EN BIT(18)
@@ -56,18 +60,67 @@ · 1 unmodified line
5660 #define CORE_DLL_PDN BIT(29)
5761 #define CORE_DLL_RST BIT(30)
5862 #define CORE_DLL_CONFIG 0x100
63+#define CORE_CMD_DAT_TRACK_SEL BIT(0)
5964 #define CORE_DLL_STATUS 0x108
6065
66+#define CORE_DLL_CONFIG_2 0x1b4
67+#define CORE_DDR_CAL_EN BIT(0)
68+#define CORE_FLL_CYCLE_CNT BIT(18)
69+#define CORE_DLL_CLOCK_DISABLE BIT(21)
70+
6171 #define CORE_VENDOR_SPEC 0x10c
6272 #define CORE_CLK_PWRSAVE BIT(1)
73+#define CORE_HC_MCLK_SEL_DFLT (2 << 8)
74+#define CORE_HC_MCLK_SEL_HS400 (3 << 8)
75+#define CORE_HC_MCLK_SEL_MASK (3 << 8)
76+#define CORE_HC_SELECT_IN_EN BIT(18)
77+#define CORE_HC_SELECT_IN_HS400 (6 << 19)
78+#define CORE_HC_SELECT_IN_MASK (7 << 19)
79+
80+#define CORE_CSR_CDC_CTLR_CFG0 0x130
81+#define CORE_SW_TRIG_FULL_CALIB BIT(16)
82+#define CORE_HW_AUTOCAL_ENA BIT(17)
83+
84+#define CORE_CSR_CDC_CTLR_CFG1 0x134
85+#define CORE_CSR_CDC_CAL_TIMER_CFG0 0x138
86+#define CORE_TIMER_ENA BIT(16)
87+
88+#define CORE_CSR_CDC_CAL_TIMER_CFG1 0x13C
89+#define CORE_CSR_CDC_REFCOUNT_CFG 0x140
90+#define CORE_CSR_CDC_COARSE_CAL_CFG 0x144
91+#define CORE_CDC_OFFSET_CFG 0x14C
92+#define CORE_CSR_CDC_DELAY_CFG 0x150
93+#define CORE_CDC_SLAVE_DDA_CFG 0x160
94+#define CORE_CSR_CDC_STATUS0 0x164
95+#define CORE_CALIBRATION_DONE BIT(0)
96+
97+#define CORE_CDC_ERROR_CODE_MASK 0x7000000
98+
99+#define CORE_CSR_CDC_GEN_CFG 0x178
100+#define CORE_CDC_SWITCH_BYPASS_OFF BIT(0)
101+#define CORE_CDC_SWITCH_RC_EN BIT(1)
102+
103+#define CORE_DDR_200_CFG 0x184
104+#define CORE_CDC_T4_DLY_SEL BIT(0)
105+#define CORE_START_CDC_TRAFFIC BIT(6)
106+#define CORE_VENDOR_SPEC3 0x1b0
107+#define CORE_PWRSAVE_DLL BIT(3)
108+
109+#define CORE_DDR_CONFIG 0x1b8
110+#define DDR_CONFIG_POR_VAL 0x80040853
63111
64112 #define CORE_VENDOR_SPEC_CAPABILITIES0 0x11c
65113
114+#define INVALID_TUNING_PHASE -1
115+#define SDHCI_MSM_MIN_CLOCK 400000
116+#define CORE_FREQ_100MHZ (100 * 1000 * 1000)
117+
66118 #define CDR_SELEXT_SHIFT 20
67119 #define CDR_SELEXT_MASK (0xf << CDR_SELEXT_SHIFT)
68120 #define CMUX_SHIFT_PHASE_SHIFT 24
69121 #define CMUX_SHIFT_PHASE_MASK (7 << CMUX_SHIFT_PHASE_SHIFT)
70122
123+#define MSM_MMC_AUTOSUSPEND_DELAY_MS 50
71124 struct sdhci_msm_host {
72125 struct platform_device *pdev;
73126 void __iomem *core_mem; /* MSM SDCC mapped address */
@@ -75,7 +128,14 @@ struct sdhci_msm_host { · 1 unmodified line
75128 struct clk *clk; /* main SD/MMC bus clock */
76129 struct clk *pclk; /* SDHC peripheral bus clock */
77130 struct clk *bus_clk; /* SDHC bus voter clock */
131+ struct clk *xo_clk; /* TCXO clk needed for FLL feature of cm_dll*/
132+ unsigned long clk_rate;
78133 struct mmc_host *mmc;
134+ bool use_14lpp_dll_reset;
135+ bool tuning_done;
136+ bool calibration_done;
137+ u8 saved_tuning_phase;
138+ bool use_cdclp533;
79139 };
80140
81141 /* Platform specific tuning */
@@ -115,6 +175,9 @@ static int msm_config_cm_dll_phase(struct sdhci_host *host, u8 phase) · 33 unmodified lines
115175 u32 config;
116176 struct mmc_host *mmc = host->mmc;
117177
178+ if (phase > 0xf)
179+ return -EINVAL;
180+
118181 spin_lock_irqsave(&host->lock, flags);
119182
120183 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
@@ -136,9 +199,9 @@ static int msm_config_cm_dll_phase(struct sdhci_host *host, u8 phase) · 15 unmodified lines
136199 config |= grey_coded_phase_table[phase] << CDR_SELEXT_SHIFT;
137200 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
138201
139− /* Set CK_OUT_EN bit of DLL_CONFIG register to 1. */
140− writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG)
141− | CORE_CK_OUT_EN), host->ioaddr + CORE_DLL_CONFIG);
202+ config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
203+ config |= CORE_CK_OUT_EN;
204+ writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
142205
143206 /* Wait until CK_OUT_EN bit of DLL_CONFIG register becomes '1' */
144207 rc = msm_dll_poll_ck_out_en(host, 1);
@@ -163,8 +226,8 @@ out: · 18 unmodified lines
163226 * Find out the greatest range of consecuitive selected
164227 * DLL clock output phases that can be used as sampling
165228 * setting for SD3.0 UHS-I card read operation (in SDR104
166− * timing mode) or for eMMC4.5 card read operation (in HS200
167− * timing mode).
229+ * timing mode) or for eMMC4.5 card read operation (in
230+ * HS400/HS200 timing mode).
168231 * Select the 3/4 of the range and configure the DLL with the
169232 * selected DLL clock output phase.
170233 */
@@ -303,8 +366,11 @@ static inline void msm_cm_dll_set_freq(struct sdhci_host *host) · 132 unmodified lines
303366 static int msm_init_cm_dll(struct sdhci_host *host)
304367 {
305368 struct mmc_host *mmc = host->mmc;
369+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
370+ struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
306371 int wait_cnt = 50;
307372 unsigned long flags;
373+ u32 config;
308374
309375 spin_lock_irqsave(&host->lock, flags);
310376
@@ -313,33 +379,73 @@ static int msm_init_cm_dll(struct sdhci_host *host) · 2 unmodified lines
313379 * tuning is in progress. Keeping PWRSAVE ON may
314380 * turn off the clock.
315381 */
316− writel_relaxed((readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC)
317− & ~CORE_CLK_PWRSAVE), host->ioaddr + CORE_VENDOR_SPEC);
382+ config = readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC);
383+ config &= ~CORE_CLK_PWRSAVE;
384+ writel_relaxed(config, host->ioaddr + CORE_VENDOR_SPEC);
385+
386+ if (msm_host->use_14lpp_dll_reset) {
387+ config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
388+ config &= ~CORE_CK_OUT_EN;
389+ writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
390+
391+ config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG_2);
392+ config |= CORE_DLL_CLOCK_DISABLE;
393+ writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG_2);
394+ }
318395
319− /* Write 1 to DLL_RST bit of DLL_CONFIG register */
320− writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG)
321− | CORE_DLL_RST), host->ioaddr + CORE_DLL_CONFIG);
396+ config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
397+ config |= CORE_DLL_RST;
398+ writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
322399
323− /* Write 1 to DLL_PDN bit of DLL_CONFIG register */
324− writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG)
325− | CORE_DLL_PDN), host->ioaddr + CORE_DLL_CONFIG);
400+ config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
401+ config |= CORE_DLL_PDN;
402+ writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
326403 msm_cm_dll_set_freq(host);
327404
328− /* Write 0 to DLL_RST bit of DLL_CONFIG register */
329− writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG)
330− & ~CORE_DLL_RST), host->ioaddr + CORE_DLL_CONFIG);
405+ if (msm_host->use_14lpp_dll_reset &&
406+ !IS_ERR_OR_NULL(msm_host->xo_clk)) {
407+ u32 mclk_freq = 0;
408+
409+ config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG_2);
410+ config &= CORE_FLL_CYCLE_CNT;
411+ if (config)
412+ mclk_freq = DIV_ROUND_CLOSEST_ULL((host->clock * 8),
413+ clk_get_rate(msm_host->xo_clk));
414+ else
415+ mclk_freq = DIV_ROUND_CLOSEST_ULL((host->clock * 4),
416+ clk_get_rate(msm_host->xo_clk));
417+
418+ config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG_2);
419+ config &= ~(0xFF << 10);
420+ config |= mclk_freq << 10;
331421
332− /* Write 0 to DLL_PDN bit of DLL_CONFIG register */
333− writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG)
334− & ~CORE_DLL_PDN), host->ioaddr + CORE_DLL_CONFIG);
422+ writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG_2);
423+ /* wait for 5us before enabling DLL clock */
424+ udelay(5);
425+ }
426+
427+ config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
428+ config &= ~CORE_DLL_RST;
429+ writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
430+
431+ config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
432+ config &= ~CORE_DLL_PDN;
433+ writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
434+
435+ if (msm_host->use_14lpp_dll_reset) {
436+ msm_cm_dll_set_freq(host);
437+ config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG_2);
438+ config &= ~CORE_DLL_CLOCK_DISABLE;
439+ writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG_2);
440+ }
335441
336− /* Set DLL_EN bit to 1. */
337− writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG)
338− | CORE_DLL_EN), host->ioaddr + CORE_DLL_CONFIG);
442+ config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
443+ config |= CORE_DLL_EN;
444+ writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
339445
340− /* Set CK_OUT_EN bit to 1. */
341− writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG)
342− | CORE_CK_OUT_EN), host->ioaddr + CORE_DLL_CONFIG);
446+ config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
447+ config |= CORE_CK_OUT_EN;
448+ writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
343449
344450 /* Wait until DLL_LOCK bit of DLL_STATUS register becomes '1' */
345451 while (!(readl_relaxed(host->ioaddr + CORE_DLL_STATUS) &
@@ -358,6 +464,200 @@ static int msm_init_cm_dll(struct sdhci_host *host) · 12 unmodified lines
358464 return 0;
359465 }
360466
467+static int sdhci_msm_cdclp533_calibration(struct sdhci_host *host)
468+{
469+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
470+ struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
471+ u32 config, calib_done;
472+ int ret;
473+
474+ pr_debug("%s: %s: Enter\n", mmc_hostname(host->mmc), __func__);
475+
476+ /*
477+ * Retuning in HS400 (DDR mode) will fail, just reset the
478+ * tuning block and restore the saved tuning phase.
479+ */
480+ ret = msm_init_cm_dll(host);
481+ if (ret)
482+ goto out;
483+
484+ /* Set the selected phase in delay line hw block */
485+ ret = msm_config_cm_dll_phase(host, msm_host->saved_tuning_phase);
486+ if (ret)
487+ goto out;
488+
489+ config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
490+ config |= CORE_CMD_DAT_TRACK_SEL;
491+ writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
492+
493+ config = readl_relaxed(host->ioaddr + CORE_DDR_200_CFG);
494+ config &= ~CORE_CDC_T4_DLY_SEL;
495+ writel_relaxed(config, host->ioaddr + CORE_DDR_200_CFG);
496+
497+ config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_GEN_CFG);
498+ config &= ~CORE_CDC_SWITCH_BYPASS_OFF;
499+ writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_GEN_CFG);
500+
501+ config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_GEN_CFG);
502+ config |= CORE_CDC_SWITCH_RC_EN;
503+ writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_GEN_CFG);
504+
505+ config = readl_relaxed(host->ioaddr + CORE_DDR_200_CFG);
506+ config &= ~CORE_START_CDC_TRAFFIC;
507+ writel_relaxed(config, host->ioaddr + CORE_DDR_200_CFG);
508+
509+ /*
510+ * Perform CDC Register Initialization Sequence
511+ *
512+ * CORE_CSR_CDC_CTLR_CFG0 0x11800EC
513+ * CORE_CSR_CDC_CTLR_CFG1 0x3011111
514+ * CORE_CSR_CDC_CAL_TIMER_CFG0 0x1201000
515+ * CORE_CSR_CDC_CAL_TIMER_CFG1 0x4
516+ * CORE_CSR_CDC_REFCOUNT_CFG 0xCB732020
517+ * CORE_CSR_CDC_COARSE_CAL_CFG 0xB19
518+ * CORE_CSR_CDC_DELAY_CFG 0x3AC
519+ * CORE_CDC_OFFSET_CFG 0x0
520+ * CORE_CDC_SLAVE_DDA_CFG 0x16334
521+ */
522+
523+ writel_relaxed(0x11800EC, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
524+ writel_relaxed(0x3011111, host->ioaddr + CORE_CSR_CDC_CTLR_CFG1);
525+ writel_relaxed(0x1201000, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0);
526+ writel_relaxed(0x4, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG1);
527+ writel_relaxed(0xCB732020, host->ioaddr + CORE_CSR_CDC_REFCOUNT_CFG);
528+ writel_relaxed(0xB19, host->ioaddr + CORE_CSR_CDC_COARSE_CAL_CFG);
529+ writel_relaxed(0x3AC, host->ioaddr + CORE_CSR_CDC_DELAY_CFG);
530+ writel_relaxed(0x0, host->ioaddr + CORE_CDC_OFFSET_CFG);
531+ writel_relaxed(0x16334, host->ioaddr + CORE_CDC_SLAVE_DDA_CFG);
532+
533+ /* CDC HW Calibration */
534+
535+ config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
536+ config |= CORE_SW_TRIG_FULL_CALIB;
537+ writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
538+
539+ config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
540+ config &= ~CORE_SW_TRIG_FULL_CALIB;
541+ writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
542+
543+ config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
544+ config |= CORE_HW_AUTOCAL_ENA;
545+ writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
546+
547+ config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0);
548+ config |= CORE_TIMER_ENA;
549+ writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0);
550+
551+ ret = readl_relaxed_poll_timeout(host->ioaddr + CORE_CSR_CDC_STATUS0,
552+ calib_done,
553+ (calib_done & CORE_CALIBRATION_DONE),
554+ 1, 50);
555+
556+ if (ret == -ETIMEDOUT) {
557+ pr_err("%s: %s: CDC calibration was not completed\n",
558+ mmc_hostname(host->mmc), __func__);
559+ goto out;
560+ }
561+
562+ ret = readl_relaxed(host->ioaddr + CORE_CSR_CDC_STATUS0)
563+ & CORE_CDC_ERROR_CODE_MASK;
564+ if (ret) {
565+ pr_err("%s: %s: CDC error code %d\n",
566+ mmc_hostname(host->mmc), __func__, ret);
567+ ret = -EINVAL;
568+ goto out;
569+ }
570+
571+ config = readl_relaxed(host->ioaddr + CORE_DDR_200_CFG);
572+ config |= CORE_START_CDC_TRAFFIC;
573+ writel_relaxed(config, host->ioaddr + CORE_DDR_200_CFG);
574+out:
575+ pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host->mmc),
576+ __func__, ret);
577+ return ret;
578+}
579+
580+static int sdhci_msm_cm_dll_sdc4_calibration(struct sdhci_host *host)
581+{
582+ u32 dll_status, config;
583+ int ret;
584+
585+ pr_debug("%s: %s: Enter\n", mmc_hostname(host->mmc), __func__);
586+
587+ /*
588+ * Currently the CORE_DDR_CONFIG register defaults to desired
589+ * configuration on reset. Currently reprogramming the power on
590+ * reset (POR) value in case it might have been modified by
591+ * bootloaders. In the future, if this changes, then the desired
592+ * values will need to be programmed appropriately.
593+ */
594+ writel_relaxed(DDR_CONFIG_POR_VAL, host->ioaddr + CORE_DDR_CONFIG);
595+
596+ config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG_2);
597+ config |= CORE_DDR_CAL_EN;
598+ writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG_2);
599+
600+ ret = readl_relaxed_poll_timeout(host->ioaddr + CORE_DLL_STATUS,
601+ dll_status,
602+ (dll_status & CORE_DDR_DLL_LOCK),
603+ 10, 1000);
604+
605+ if (ret == -ETIMEDOUT) {
606+ pr_err("%s: %s: CM_DLL_SDC4 calibration was not completed\n",
607+ mmc_hostname(host->mmc), __func__);
608+ goto out;
609+ }
610+
611+ config = readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC3);
612+ config |= CORE_PWRSAVE_DLL;
613+ writel_relaxed(config, host->ioaddr + CORE_VENDOR_SPEC3);
614+
615+ /*
616+ * Drain writebuffer to ensure above DLL calibration
617+ * and PWRSAVE DLL is enabled.
618+ */
619+ wmb();
620+out:
621+ pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host->mmc),
622+ __func__, ret);
623+ return ret;
624+}
625+
626+static int sdhci_msm_hs400_dll_calibration(struct sdhci_host *host)
627+{
628+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
629+ struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
630+ int ret;
631+ u32 config;
632+
633+ pr_debug("%s: %s: Enter\n", mmc_hostname(host->mmc), __func__);
634+
635+ /*
636+ * Retuning in HS400 (DDR mode) will fail, just reset the
637+ * tuning block and restore the saved tuning phase.
638+ */
639+ ret = msm_init_cm_dll(host);
640+ if (ret)
641+ goto out;
642+
643+ /* Set the selected phase in delay line hw block */
644+ ret = msm_config_cm_dll_phase(host, msm_host->saved_tuning_phase);
645+ if (ret)
646+ goto out;
647+
648+ config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
649+ config |= CORE_CMD_DAT_TRACK_SEL;
650+ writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
651+ if (msm_host->use_cdclp533)
652+ ret = sdhci_msm_cdclp533_calibration(host);
653+ else
654+ ret = sdhci_msm_cm_dll_sdc4_calibration(host);
655+out:
656+ pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host->mmc),
657+ __func__, ret);
658+ return ret;
659+}
660+
361661 static int sdhci_msm_execute_tuning(struct sdhci_host *host, u32 opcode)
362662 {
363663 int tuning_seq_cnt = 3;
@@ -365,14 +665,17 @@ static int sdhci_msm_execute_tuning(struct sdhci_host *host, u32 opcode) · 1 unmodified line
365665 int rc;
366666 struct mmc_host *mmc = host->mmc;
367667 struct mmc_ios ios = host->mmc->ios;
668+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
669+ struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
368670
369671 /*
370672 * Tuning is required for SDR104, HS200 and HS400 cards and
371673 * if clock frequency is greater than 100MHz in these modes.
372674 */
373− if (host->clock <= 100 * 1000 * 1000 ||
374− !((ios.timing == MMC_TIMING_MMC_HS200) ||
375− (ios.timing == MMC_TIMING_UHS_SDR104)))
675+ if (host->clock <= CORE_FREQ_100MHZ ||
676+ !(ios.timing == MMC_TIMING_MMC_HS400 ||
677+ ios.timing == MMC_TIMING_MMC_HS200 ||
678+ ios.timing == MMC_TIMING_UHS_SDR104))
376679 return 0;
377680
378681 retry:
@@ -388,6 +691,7 @@ retry: · 9 unmodified lines
388691 if (rc)
389692 return rc;
390693
694+ msm_host->saved_tuning_phase = phase;
391695 rc = mmc_send_tuning(mmc, opcode, NULL);
392696 if (!rc) {
393697 /* Tuning is successful at this tuning point */
@@ -423,6 +727,8 @@ retry: · 29 unmodified lines
423727 rc = -EIO;
424728 }
425729
730+ if (!rc)
731+ msm_host->tuning_done = true;
426732 return rc;
427733 }
428734
@@ -430,7 +736,10 @@ static void sdhci_msm_set_uhs_signaling(struct sdhci_host *host, · 1 unmodified line
430736 unsigned int uhs)
431737 {
432738 struct mmc_host *mmc = host->mmc;
739+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
740+ struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
433741 u16 ctrl_2;
742+ u32 config;
434743
435744 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
436745 /* Select Bus Speed Mode for host */
@@ -445,6 +754,7 @@ static void sdhci_msm_set_uhs_signaling(struct sdhci_host *host, · 8 unmodified lines
445754 case MMC_TIMING_UHS_SDR50:
446755 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
447756 break;
757+ case MMC_TIMING_MMC_HS400:
448758 case MMC_TIMING_MMC_HS200:
449759 case MMC_TIMING_UHS_SDR104:
450760 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
@@ -461,15 +771,42 @@ static void sdhci_msm_set_uhs_signaling(struct sdhci_host *host, · 10 unmodified lines
461771 * provide feedback clock, the mode selection can be any value less
462772 * than 3'b011 in bits [2:0] of HOST CONTROL2 register.
463773 */
464− if (host->clock <= 100000000 &&
465− (uhs == MMC_TIMING_MMC_HS400 ||
466− uhs == MMC_TIMING_MMC_HS200 ||
467− uhs == MMC_TIMING_UHS_SDR104))
468− ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
774+ if (host->clock <= CORE_FREQ_100MHZ) {
775+ if (uhs == MMC_TIMING_MMC_HS400 ||
776+ uhs == MMC_TIMING_MMC_HS200 ||
777+ uhs == MMC_TIMING_UHS_SDR104)
778+ ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
779+ /*
780+ * DLL is not required for clock <= 100MHz
781+ * Thus, make sure DLL it is disabled when not required
782+ */
783+ config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
784+ config |= CORE_DLL_RST;
785+ writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
786+
787+ config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
788+ config |= CORE_DLL_PDN;
789+ writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
790+
791+ /*
792+ * The DLL needs to be restored and CDCLP533 recalibrated
793+ * when the clock frequency is set back to 400MHz.
794+ */
795+ msm_host->calibration_done = false;
796+ }
469797
470798 dev_dbg(mmc_dev(mmc), "%s: clock=%u uhs=%u ctrl_2=0x%x\n",
471799 mmc_hostname(host->mmc), host->clock, uhs, ctrl_2);
472800 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
801+
802+ spin_unlock_irq(&host->lock);
803+ /* CDCLP533 HW calibration is only required for HS400 mode*/
804+ if (host->clock > CORE_FREQ_100MHZ &&
805+ msm_host->tuning_done && !msm_host->calibration_done &&
806+ mmc->ios.timing == MMC_TIMING_MMC_HS400)
807+ if (!sdhci_msm_hs400_dll_calibration(host))
808+ msm_host->calibration_done = true;
809+ spin_lock_irq(&host->lock);
473810 }
474811
475812 static void sdhci_msm_voltage_switch(struct sdhci_host *host)
@@ -505,6 +842,183 @@ static irqreturn_t sdhci_msm_pwr_irq(int irq, void *data) · 29 unmodified lines
505842 return IRQ_HANDLED;
506843 }
507844
845+static unsigned int sdhci_msm_get_max_clock(struct sdhci_host *host)
846+{
847+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
848+ struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
849+
850+ return clk_round_rate(msm_host->clk, ULONG_MAX);
851+}
852+
853+static unsigned int sdhci_msm_get_min_clock(struct sdhci_host *host)
854+{
855+ return SDHCI_MSM_MIN_CLOCK;
856+}
857+
858+/**
859+ * __sdhci_msm_set_clock - sdhci_msm clock control.
860+ *
861+ * Description:
862+ * MSM controller does not use internal divider and
863+ * instead directly control the GCC clock as per
864+ * HW recommendation.
865+ **/
866+void __sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
867+{
868+ u16 clk;
869+ /*
870+ * Keep actual_clock as zero -
871+ * - since there is no divider used so no need of having actual_clock.
872+ * - MSM controller uses SDCLK for data timeout calculation. If
873+ * actual_clock is zero, host->clock is taken for calculation.
874+ */
875+ host->mmc->actual_clock = 0;
876+
877+ sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
878+
879+ if (clock == 0)
880+ return;
881+
882+ /*
883+ * MSM controller do not use clock divider.
884+ * Thus read SDHCI_CLOCK_CONTROL and only enable
885+ * clock with no divider value programmed.
886+ */
887+ clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
888+ sdhci_enable_clk(host, clk);
889+}
890+
891+/* sdhci_msm_set_clock - Called with (host->lock) spinlock held. */
892+static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
893+{
894+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
895+ struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
896+ struct mmc_ios curr_ios = host->mmc->ios;
897+ u32 config, dll_lock;
898+ int rc;
899+
900+ if (!clock) {
901+ msm_host->clk_rate = clock;
902+ goto out;
903+ }
904+
905+ spin_unlock_irq(&host->lock);
906+ /*
907+ * The SDHC requires internal clock frequency to be double the
908+ * actual clock that will be set for DDR mode. The controller
909+ * uses the faster clock(100/400MHz) for some of its parts and
910+ * send the actual required clock (50/200MHz) to the card.
911+ */
912+ if (curr_ios.timing == MMC_TIMING_UHS_DDR50 ||
913+ curr_ios.timing == MMC_TIMING_MMC_DDR52 ||
914+ curr_ios.timing == MMC_TIMING_MMC_HS400)
915+ clock *= 2;
916+ /*
917+ * In general all timing modes are controlled via UHS mode select in
918+ * Host Control2 register. eMMC specific HS200/HS400 doesn't have
919+ * their respective modes defined here, hence we use these values.
920+ *
921+ * HS200 - SDR104 (Since they both are equivalent in functionality)
922+ * HS400 - This involves multiple configurations
923+ * Initially SDR104 - when tuning is required as HS200
924+ * Then when switching to DDR @ 400MHz (HS400) we use
925+ * the vendor specific HC_SELECT_IN to control the mode.
926+ *
927+ * In addition to controlling the modes we also need to select the
928+ * correct input clock for DLL depending on the mode.
929+ *
930+ * HS400 - divided clock (free running MCLK/2)
931+ * All other modes - default (free running MCLK)
932+ */
933+ if (curr_ios.timing == MMC_TIMING_MMC_HS400) {
934+ /* Select the divided clock (free running MCLK/2) */
935+ config = readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC);
936+ config &= ~CORE_HC_MCLK_SEL_MASK;
937+ config |= CORE_HC_MCLK_SEL_HS400;
938+
939+ writel_relaxed(config, host->ioaddr + CORE_VENDOR_SPEC);
940+ /*
941+ * Select HS400 mode using the HC_SELECT_IN from VENDOR SPEC
942+ * register
943+ */
944+ if (msm_host->tuning_done && !msm_host->calibration_done) {
945+ /*
946+ * Write 0x6 to HC_SELECT_IN and 1 to HC_SELECT_IN_EN
947+ * field in VENDOR_SPEC_FUNC
948+ */
949+ config = readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC);
950+ config |= CORE_HC_SELECT_IN_HS400;
951+ config |= CORE_HC_SELECT_IN_EN;
952+ writel_relaxed(config, host->ioaddr + CORE_VENDOR_SPEC);
953+ }
954+ if (!msm_host->clk_rate && !msm_host->use_cdclp533) {
955+ /*
956+ * Poll on DLL_LOCK or DDR_DLL_LOCK bits in
957+ * CORE_DLL_STATUS to be set. This should get set
958+ * within 15 us at 200 MHz.
959+ */
960+ rc = readl_relaxed_poll_timeout(host->ioaddr +
961+ CORE_DLL_STATUS,
962+ dll_lock,
963+ (dll_lock &
964+ (CORE_DLL_LOCK |
965+ CORE_DDR_DLL_LOCK)), 10,
966+ 1000);
967+ if (rc == -ETIMEDOUT)
968+ pr_err("%s: Unable to get DLL_LOCK/DDR_DLL_LOCK, dll_status: 0x%08x\n",
969+ mmc_hostname(host->mmc), dll_lock);
970+ }
971+ } else {
972+ if (!msm_host->use_cdclp533) {
973+ config = readl_relaxed(host->ioaddr +
974+ CORE_VENDOR_SPEC3);
975+ config &= ~CORE_PWRSAVE_DLL;
976+ writel_relaxed(config, host->ioaddr +
977+ CORE_VENDOR_SPEC3);
978+ }
979+
980+ config = readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC);
981+ config &= ~CORE_HC_MCLK_SEL_MASK;
982+ config |= CORE_HC_MCLK_SEL_DFLT;
983+ writel_relaxed(config, host->ioaddr + CORE_VENDOR_SPEC);
984+
985+ /*
986+ * Disable HC_SELECT_IN to be able to use the UHS mode select
987+ * configuration from Host Control2 register for all other
988+ * modes.
989+ * Write 0 to HC_SELECT_IN and HC_SELECT_IN_EN field
990+ * in VENDOR_SPEC_FUNC
991+ */
992+ config = readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC);
993+ config &= ~CORE_HC_SELECT_IN_EN;
994+ config &= ~CORE_HC_SELECT_IN_MASK;
995+ writel_relaxed(config, host->ioaddr + CORE_VENDOR_SPEC);
996+ }
997+
998+ /*
999+ * Make sure above writes impacting free running MCLK are completed
1000+ * before changing the clk_rate at GCC.
1001+ */
1002+ wmb();
1003+
1004+ rc = clk_set_rate(msm_host->clk, clock);
1005+ if (rc) {
1006+ pr_err("%s: Failed to set clock at rate %u at timing %d\n",
1007+ mmc_hostname(host->mmc), clock,
1008+ curr_ios.timing);
1009+ goto out_lock;
1010+ }
1011+ msm_host->clk_rate = clock;
1012+ pr_debug("%s: Setting clock at rate %lu at timing %d\n",
1013+ mmc_hostname(host->mmc), clk_get_rate(msm_host->clk),
1014+ curr_ios.timing);
1015+
1016+out_lock:
1017+ spin_lock_irq(&host->lock);
1018+out:
1019+ __sdhci_msm_set_clock(host, clock);
1020+}
1021+
5081022 static const struct of_device_id sdhci_msm_dt_match[] = {
5091023 { .compatible = "qcom,sdhci-msm-v4" },
5101024 {},
@@ -515,7 +1029,9 @@ MODULE_DEVICE_TABLE(of, sdhci_msm_dt_match); · 4 unmodified lines
5151029 static const struct sdhci_ops sdhci_msm_ops = {
5161030 .platform_execute_tuning = sdhci_msm_execute_tuning,
5171031 .reset = sdhci_reset,
518− .set_clock = sdhci_set_clock,
1032+ .set_clock = sdhci_msm_set_clock,
1033+ .get_min_clock = sdhci_msm_get_min_clock,
1034+ .get_max_clock = sdhci_msm_get_max_clock,
5191035 .set_bus_width = sdhci_set_bus_width,
5201036 .set_uhs_signaling = sdhci_msm_set_uhs_signaling,
5211037 .voltage_switch = sdhci_msm_voltage_switch,
@@ -524,7 +1040,9 @@ static const struct sdhci_ops sdhci_msm_ops = { · 2 unmodified lines
5241040 static const struct sdhci_pltfm_data sdhci_msm_pdata = {
5251041 .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION |
5261042 SDHCI_QUIRK_NO_CARD_NO_RESET |
527− SDHCI_QUIRK_SINGLE_POWER_WRITE,
1043+ SDHCI_QUIRK_SINGLE_POWER_WRITE |
1044+ SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
1045+ .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
5281046 .ops = &sdhci_msm_ops,
5291047 };
5301048
@@ -536,7 +1054,7 @@ static int sdhci_msm_probe(struct platform_device *pdev) · 5 unmodified lines
5361054 struct resource *core_memres;
5371055 int ret;
5381056 u16 host_version, core_minor;
539− u32 core_version, caps;
1057+ u32 core_version, config;
5401058 u8 core_major;
5411059
5421060 host = sdhci_pltfm_init(pdev, &sdhci_msm_pdata, sizeof(*msm_host));
@@ -554,6 +1072,8 @@ static int sdhci_msm_probe(struct platform_device *pdev) · 11 unmodified lines
5541072
5551073 sdhci_get_of_property(pdev);
5561074
1075+ msm_host->saved_tuning_phase = INVALID_TUNING_PHASE;
1076+
5571077 /* Setup SDCC bus voter clock. */
5581078 msm_host->bus_clk = devm_clk_get(&pdev->dev, "bus");
5591079 if (!IS_ERR(msm_host->bus_clk)) {
@@ -586,6 +1106,16 @@ static int sdhci_msm_probe(struct platform_device *pdev) · 26 unmodified lines
5861106 goto pclk_disable;
5871107 }
5881108
1109+ /*
1110+ * xo clock is needed for FLL feature of cm_dll.
1111+ * In case if xo clock is not mentioned in DT, warn and proceed.
1112+ */
1113+ msm_host->xo_clk = devm_clk_get(&pdev->dev, "xo");
1114+ if (IS_ERR(msm_host->xo_clk)) {
1115+ ret = PTR_ERR(msm_host->xo_clk);
1116+ dev_warn(&pdev->dev, "TCXO clk not present (%d)\n", ret);
1117+ }
1118+
5891119 /* Vote for maximum clock rate for maximum performance */
5901120 ret = clk_set_rate(msm_host->clk, INT_MAX);
5911121 if (ret)
@@ -604,9 +1134,9 @@ static int sdhci_msm_probe(struct platform_device *pdev) · 12 unmodified lines
6041134 goto clk_disable;
6051135 }
6061136
607− /* Reset the core and Enable SDHC mode */
608− writel_relaxed(readl_relaxed(msm_host->core_mem + CORE_POWER) |
609− CORE_SW_RST, msm_host->core_mem + CORE_POWER);
1137+ config = readl_relaxed(msm_host->core_mem + CORE_POWER);
1138+ config |= CORE_SW_RST;
1139+ writel_relaxed(config, msm_host->core_mem + CORE_POWER);
6101140
6111141 /* SW reset can take upto 10HCLK + 15MCLK cycles. (min 40us) */
6121142 usleep_range(1000, 5000);
@@ -619,6 +1149,10 @@ static int sdhci_msm_probe(struct platform_device *pdev) · 6 unmodified lines
6191149 /* Set HC_MODE_EN bit in HC_MODE register */
6201150 writel_relaxed(HC_MODE_EN, (msm_host->core_mem + CORE_HC_MODE));
6211151
1152+ config = readl_relaxed(msm_host->core_mem + CORE_HC_MODE);
1153+ config |= FF_CLK_SW_RST_DIS;
1154+ writel_relaxed(config, msm_host->core_mem + CORE_HC_MODE);
1155+
6221156 host_version = readw_relaxed((host->ioaddr + SDHCI_HOST_VERSION));
6231157 dev_dbg(&pdev->dev, "Host Version: 0x%x Vendor Version 0x%x\n",
6241158 host_version, ((host_version & SDHCI_VENDOR_VER_MASK) >>
@@ -631,14 +1165,24 @@ static int sdhci_msm_probe(struct platform_device *pdev) · 6 unmodified lines
6311165 dev_dbg(&pdev->dev, "MCI Version: 0x%08x, major: 0x%04x, minor: 0x%02x\n",
6321166 core_version, core_major, core_minor);
6331167
1168+ if (core_major == 1 && core_minor >= 0x42)
1169+ msm_host->use_14lpp_dll_reset = true;
1170+
1171+ /*
1172+ * SDCC 5 controller with major version 1, minor version 0x34 and later
1173+ * with HS 400 mode support will use CM DLL instead of CDC LP 533 DLL.
1174+ */
1175+ if (core_major == 1 && core_minor < 0x34)
1176+ msm_host->use_cdclp533 = true;
1177+
6341178 /*
6351179 * Support for some capabilities is not advertised by newer
6361180 * controller versions and must be explicitly enabled.
6371181 */
6381182 if (core_major >= 1 && core_minor != 0x11 && core_minor != 0x12) {
639− caps = readl_relaxed(host->ioaddr + SDHCI_CAPABILITIES);
640− caps |= SDHCI_CAN_VDD_300 | SDHCI_CAN_DO_8BIT;
641− writel_relaxed(caps, host->ioaddr +
1183+ config = readl_relaxed(host->ioaddr + SDHCI_CAPABILITIES);
1184+ config |= SDHCI_CAN_VDD_300 | SDHCI_CAN_DO_8BIT;
1185+ writel_relaxed(config, host->ioaddr +
6421186 CORE_VENDOR_SPEC_CAPABILITIES0);
6431187 }
6441188
@@ -659,12 +1203,26 @@ static int sdhci_msm_probe(struct platform_device *pdev) · 14 unmodified lines
6591203 goto clk_disable;
6601204 }
6611205
1206+ pm_runtime_get_noresume(&pdev->dev);
1207+ pm_runtime_set_active(&pdev->dev);
1208+ pm_runtime_enable(&pdev->dev);
1209+ pm_runtime_set_autosuspend_delay(&pdev->dev,
1210+ MSM_MMC_AUTOSUSPEND_DELAY_MS);
1211+ pm_runtime_use_autosuspend(&pdev->dev);
1212+
6621213 ret = sdhci_add_host(host);
6631214 if (ret)
664− goto clk_disable;
1215+ goto pm_runtime_disable;
1216+
1217+ pm_runtime_mark_last_busy(&pdev->dev);
1218+ pm_runtime_put_autosuspend(&pdev->dev);
6651219
6661220 return 0;
6671221
1222+pm_runtime_disable:
1223+ pm_runtime_disable(&pdev->dev);
1224+ pm_runtime_set_suspended(&pdev->dev);
1225+ pm_runtime_put_noidle(&pdev->dev);
6681226 clk_disable:
6691227 clk_disable_unprepare(msm_host->clk);
6701228 pclk_disable:
@@ -686,6 +1244,11 @@ static int sdhci_msm_remove(struct platform_device *pdev) · 15 unmodified lines
6861244 0xffffffff);
6871245
6881246 sdhci_remove_host(host, dead);
1247+
1248+ pm_runtime_get_sync(&pdev->dev);
1249+ pm_runtime_disable(&pdev->dev);
1250+ pm_runtime_put_noidle(&pdev->dev);
1251+
6891252 clk_disable_unprepare(msm_host->clk);
6901253 clk_disable_unprepare(msm_host->pclk);
6911254 if (!IS_ERR(msm_host->bus_clk))
@@ -694,12 +1257,57 @@ static int sdhci_msm_remove(struct platform_device *pdev) · 2 unmodified lines
6941257 return 0;
6951258 }
6961259
1260+#ifdef CONFIG_PM
1261+static int sdhci_msm_runtime_suspend(struct device *dev)
1262+{
1263+ struct sdhci_host *host = dev_get_drvdata(dev);
1264+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1265+ struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1266+
1267+ clk_disable_unprepare(msm_host->clk);
1268+ clk_disable_unprepare(msm_host->pclk);
1269+
1270+ return 0;
1271+}
1272+
1273+static int sdhci_msm_runtime_resume(struct device *dev)
1274+{
1275+ struct sdhci_host *host = dev_get_drvdata(dev);
1276+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1277+ struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1278+ int ret;
1279+
1280+ ret = clk_prepare_enable(msm_host->clk);
1281+ if (ret) {
1282+ dev_err(dev, "clk_enable failed for core_clk: %d\n", ret);
1283+ return ret;
1284+ }
1285+ ret = clk_prepare_enable(msm_host->pclk);
1286+ if (ret) {
1287+ dev_err(dev, "clk_enable failed for iface_clk: %d\n", ret);
1288+ clk_disable_unprepare(msm_host->clk);
1289+ return ret;
1290+ }
1291+
1292+ return 0;
1293+}
1294+#endif
1295+
1296+static const struct dev_pm_ops sdhci_msm_pm_ops = {
1297+ SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1298+ pm_runtime_force_resume)
1299+ SET_RUNTIME_PM_OPS(sdhci_msm_runtime_suspend,
1300+ sdhci_msm_runtime_resume,
1301+ NULL)
1302+};
1303+
6971304 static struct platform_driver sdhci_msm_driver = {
6981305 .probe = sdhci_msm_probe,
6991306 .remove = sdhci_msm_remove,
7001307 .driver = {
7011308 .name = "sdhci_msm",
7021309 .of_match_table = sdhci_msm_dt_match,
1310+ .pm = &sdhci_msm_pm_ops,
7031311 },
7041312 };
7051313
drivers/mmc/host/sdhci-of-at91.c+1−0
@@ -100,6 +100,7 @@ static const struct of_device_id sdhci_at91_dt_match[] = { · 99 unmodified lines
100100 { .compatible = "atmel,sama5d2-sdhci", .data = &soc_data_sama5d2 },
101101 {}
102102 };
103+MODULE_DEVICE_TABLE(of, sdhci_at91_dt_match);
103104
104105 #ifdef CONFIG_PM
105106 static int sdhci_at91_runtime_suspend(struct device *dev)
drivers/mmc/host/sdhci-of-esdhc.c+20−0
@@ -18,6 +18,7 @@ · 17 unmodified lines
1818 #include <linux/of.h>
1919 #include <linux/delay.h>
2020 #include <linux/module.h>
21+#include <linux/sys_soc.h>
2122 #include <linux/mmc/host.h>
2223 #include "sdhci-pltfm.h"
2324 #include "sdhci-esdhc.h"
@@ -28,6 +29,7 @@ · 4 unmodified lines
2829 struct sdhci_esdhc {
2930 u8 vendor_ver;
3031 u8 spec_ver;
32+ bool quirk_incorrect_hostver;
3133 };
3234
3335 /**
@@ -87,6 +89,8 @@ static u32 esdhc_readl_fixup(struct sdhci_host *host, · 53 unmodified lines
8789 static u16 esdhc_readw_fixup(struct sdhci_host *host,
8890 int spec_reg, u32 value)
8991 {
92+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
93+ struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
9094 u16 ret;
9195 int shift = (spec_reg & 0x2) * 8;
9296
@@ -94,6 +98,12 @@ static u16 esdhc_readw_fixup(struct sdhci_host *host, · 1 unmodified line
9498 ret = value & 0xffff;
9599 else
96100 ret = (value >> shift) & 0xffff;
101+ /* Workaround for T4240-R1.0-R2.0 eSDHC which has incorrect
102+ * vendor version and spec version information.
103+ */
104+ if ((spec_reg == SDHCI_HOST_VERSION) &&
105+ (esdhc->quirk_incorrect_hostver))
106+ ret = (VENDOR_V_23 << SDHCI_VENDOR_VER_SHIFT) | SDHCI_SPEC_200;
97107 return ret;
98108 }
99109
@@ -572,6 +582,12 @@ static const struct sdhci_pltfm_data sdhci_esdhc_le_pdata = { · 472 unmodified lines
572582 .ops = &sdhci_esdhc_le_ops,
573583 };
574584
585+static struct soc_device_attribute soc_incorrect_hostver[] = {
586+ { .family = "QorIQ T4240", .revision = "1.0", },
587+ { .family = "QorIQ T4240", .revision = "2.0", },
588+ { },
589+};
590+
575591 static void esdhc_init(struct platform_device *pdev, struct sdhci_host *host)
576592 {
577593 struct sdhci_pltfm_host *pltfm_host;
@@ -585,6 +601,10 @@ static void esdhc_init(struct platform_device *pdev, struct sdhci_host *host) · 7 unmodified lines
585601 esdhc->vendor_ver = (host_ver & SDHCI_VENDOR_VER_MASK) >>
586602 SDHCI_VENDOR_VER_SHIFT;
587603 esdhc->spec_ver = host_ver & SDHCI_SPEC_VER_MASK;
604+ if (soc_device_match(soc_incorrect_hostver))
605+ esdhc->quirk_incorrect_hostver = true;
606+ else
607+ esdhc->quirk_incorrect_hostver = false;
588608 }
589609
590610 static int sdhci_esdhc_probe(struct platform_device *pdev)
drivers/mmc/host/sdhci-pci-core.c+92−6
@@ -27,6 +27,7 @@ · 26 unmodified lines
2727 #include <linux/pm_runtime.h>
2828 #include <linux/mmc/slot-gpio.h>
2929 #include <linux/mmc/sdhci-pci-data.h>
30+#include <linux/acpi.h>
3031
3132 #include "sdhci.h"
3233 #include "sdhci-pci.h"
@@ -375,6 +376,44 @@ static int byt_emmc_probe_slot(struct sdhci_pci_slot *slot) · 342 unmodified lines
375376 return 0;
376377 }
377378
379+#ifdef CONFIG_ACPI
380+static int ni_set_max_freq(struct sdhci_pci_slot *slot)
381+{
382+ acpi_status status;
383+ unsigned long long max_freq;
384+
385+ status = acpi_evaluate_integer(ACPI_HANDLE(&slot->chip->pdev->dev),
386+ "MXFQ", NULL, &max_freq);
387+ if (ACPI_FAILURE(status)) {
388+ dev_err(&slot->chip->pdev->dev,
389+ "MXFQ not found in acpi table\n");
390+ return -EINVAL;
391+ }
392+
393+ slot->host->mmc->f_max = max_freq * 1000000;
394+
395+ return 0;
396+}
397+#else
398+static inline int ni_set_max_freq(struct sdhci_pci_slot *slot)
399+{
400+ return 0;
401+}
402+#endif
403+
404+static int ni_byt_sdio_probe_slot(struct sdhci_pci_slot *slot)
405+{
406+ int err;
407+
408+ err = ni_set_max_freq(slot);
409+ if (err)
410+ return err;
411+
412+ slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE |
413+ MMC_CAP_WAIT_WHILE_BUSY;
414+ return 0;
415+}
416+
378417 static int byt_sdio_probe_slot(struct sdhci_pci_slot *slot)
379418 {
380419 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE |
@@ -390,7 +429,8 @@ static int byt_sd_probe_slot(struct sdhci_pci_slot *slot) · 9 unmodified lines
390429 slot->cd_override_level = true;
391430 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXT_SD ||
392431 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXTM_SD ||
393− slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_APL_SD) {
432+ slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_APL_SD ||
433+ slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_SD) {
394434 slot->host->mmc_host_ops.get_cd = bxt_get_cd;
395435 slot->host->mmc->caps |= MMC_CAP_AGGRESSIVE_PM;
396436 }
@@ -447,6 +487,15 @@ static const struct sdhci_pci_fixes sdhci_intel_byt_emmc = { · 50 unmodified lines
447487 .ops = &sdhci_intel_byt_ops,
448488 };
449489
490+static const struct sdhci_pci_fixes sdhci_ni_byt_sdio = {
491+ .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
492+ .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON |
493+ SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
494+ .allow_runtime_pm = true,
495+ .probe_slot = ni_byt_sdio_probe_slot,
496+ .ops = &sdhci_intel_byt_ops,
497+};
498+
450499 static const struct sdhci_pci_fixes sdhci_intel_byt_sdio = {
451500 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
452501 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON |
@@ -1076,6 +1125,14 @@ static const struct pci_device_id pci_ids[] = { · 623 unmodified lines
10761125 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc,
10771126 },
10781127
1128+ {
1129+ .vendor = PCI_VENDOR_ID_INTEL,
1130+ .device = PCI_DEVICE_ID_INTEL_BYT_SDIO,
1131+ .subvendor = PCI_VENDOR_ID_NI,
1132+ .subdevice = 0x7884,
1133+ .driver_data = (kernel_ulong_t)&sdhci_ni_byt_sdio,
1134+ },
1135+
10791136 {
10801137 .vendor = PCI_VENDOR_ID_INTEL,
10811138 .device = PCI_DEVICE_ID_INTEL_BYT_SDIO,
@@ -1276,6 +1333,30 @@ static const struct pci_device_id pci_ids[] = { · 194 unmodified lines
12761333 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd,
12771334 },
12781335
1336+ {
1337+ .vendor = PCI_VENDOR_ID_INTEL,
1338+ .device = PCI_DEVICE_ID_INTEL_GLK_EMMC,
1339+ .subvendor = PCI_ANY_ID,
1340+ .subdevice = PCI_ANY_ID,
1341+ .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc,
1342+ },
1343+
1344+ {
1345+ .vendor = PCI_VENDOR_ID_INTEL,
1346+ .device = PCI_DEVICE_ID_INTEL_GLK_SDIO,
1347+ .subvendor = PCI_ANY_ID,
1348+ .subdevice = PCI_ANY_ID,
1349+ .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio,
1350+ },
1351+
1352+ {
1353+ .vendor = PCI_VENDOR_ID_INTEL,
1354+ .device = PCI_DEVICE_ID_INTEL_GLK_SD,
1355+ .subvendor = PCI_ANY_ID,
1356+ .subdevice = PCI_ANY_ID,
1357+ .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd,
1358+ },
1359+
12791360 {
12801361 .vendor = PCI_VENDOR_ID_O2,
12811362 .device = PCI_DEVICE_ID_O2_8120,
@@ -1735,11 +1816,16 @@ static struct sdhci_pci_slot *sdhci_pci_probe_slot( · 453 unmodified lines
17351816 host->mmc->slotno = slotno;
17361817 host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP;
17371818
1738− if (slot->cd_idx >= 0 &&
1739− mmc_gpiod_request_cd(host->mmc, slot->cd_con_id, slot->cd_idx,
1740− slot->cd_override_level, 0, NULL)) {
1741− dev_warn(&pdev->dev, "failed to setup card detect gpio\n");
1742− slot->cd_idx = -1;
1819+ if (slot->cd_idx >= 0) {
1820+ ret = mmc_gpiod_request_cd(host->mmc, slot->cd_con_id, slot->cd_idx,
1821+ slot->cd_override_level, 0, NULL);
1822+ if (ret == -EPROBE_DEFER)
1823+ goto remove;
1824+
1825+ if (ret) {
1826+ dev_warn(&pdev->dev, "failed to setup card detect gpio\n");
1827+ slot->cd_idx = -1;
1828+ }
17431829 }
17441830
17451831 ret = sdhci_add_host(host);
drivers/mmc/host/sdhci-pci.h+3−0
@@ -34,6 +34,9 @@ · 33 unmodified lines
3434 #define PCI_DEVICE_ID_INTEL_APL_SD 0x5aca
3535 #define PCI_DEVICE_ID_INTEL_APL_EMMC 0x5acc
3636 #define PCI_DEVICE_ID_INTEL_APL_SDIO 0x5ad0
37+#define PCI_DEVICE_ID_INTEL_GLK_SD 0x31ca
38+#define PCI_DEVICE_ID_INTEL_GLK_EMMC 0x31cc
39+#define PCI_DEVICE_ID_INTEL_GLK_SDIO 0x31d0
3740
3841 /*
3942 * PCI registers
drivers/mmc/host/sdhci-pltfm.h+1−1
@@ -106,7 +106,7 @@ extern unsigned int sdhci_pltfm_clk_get_max_clock(struct sdhci_host *host); · 105 unmodified lines
106106
107107 static inline void *sdhci_pltfm_priv(struct sdhci_pltfm_host *host)
108108 {
109− return (void *)host->private;
109+ return host->private;
110110 }
111111
112112 extern const struct dev_pm_ops sdhci_pltfm_pmops;
drivers/mmc/host/sdhci-s3c.c+2−0
@@ -121,7 +121,9 @@ static unsigned int sdhci_s3c_consider_clock(struct sdhci_s3c *ourhost, · 120 unmodified lines
121121 * speed possible with selected clock source and skip the division.
122122 */
123123 if (ourhost->no_divider) {
124+ spin_unlock_irq(&ourhost->host->lock);
124125 rate = clk_round_rate(clksrc, wanted);
126+ spin_lock_irq(&ourhost->host->lock);
125127 return wanted - rate;
126128 }
127129
drivers/mmc/host/sdhci.c+204−158
@@ -22,6 +22,7 @@ · 21 unmodified lines
2222 #include <linux/scatterlist.h>
2323 #include <linux/regulator/consumer.h>
2424 #include <linux/pm_runtime.h>
25+#include <linux/of.h>
2526
2627 #include <linux/leds.h>
2728
@@ -1343,20 +1344,10 @@ clock_set: · 1315 unmodified lines
13431344 }
13441345 EXPORT_SYMBOL_GPL(sdhci_calc_clk);
13451346
1346−void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1347+void sdhci_enable_clk(struct sdhci_host *host, u16 clk)
13471348 {
1348− u16 clk;
13491349 unsigned long timeout;
13501350
1351− host->mmc->actual_clock = 0;
1352−
1353− sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1354−
1355− if (clock == 0)
1356− return;
1357−
1358− clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
1359−
13601351 clk |= SDHCI_CLOCK_INT_EN;
13611352 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
13621353
@@ -1377,6 +1368,22 @@ void sdhci_set_clock(struct sdhci_host *host, unsigned int clock) · 14 unmodified lines
13771368 clk |= SDHCI_CLOCK_CARD_EN;
13781369 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
13791370 }
1371+EXPORT_SYMBOL_GPL(sdhci_enable_clk);
1372+
1373+void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1374+{
1375+ u16 clk;
1376+
1377+ host->mmc->actual_clock = 0;
1378+
1379+ sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1380+
1381+ if (clock == 0)
1382+ return;
1383+
1384+ clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
1385+ sdhci_enable_clk(host, clk);
1386+}
13801387 EXPORT_SYMBOL_GPL(sdhci_set_clock);
13811388
13821389 static void sdhci_set_power_reg(struct sdhci_host *host, unsigned char mode,
@@ -1623,7 +1630,14 @@ static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) · 240 unmodified lines
16231630 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
16241631
16251632 if ((ios->timing == MMC_TIMING_SD_HS ||
1626− ios->timing == MMC_TIMING_MMC_HS)
1633+ ios->timing == MMC_TIMING_MMC_HS ||
1634+ ios->timing == MMC_TIMING_MMC_HS400 ||
1635+ ios->timing == MMC_TIMING_MMC_HS200 ||
1636+ ios->timing == MMC_TIMING_MMC_DDR52 ||
1637+ ios->timing == MMC_TIMING_UHS_SDR50 ||
1638+ ios->timing == MMC_TIMING_UHS_SDR104 ||
1639+ ios->timing == MMC_TIMING_UHS_DDR50 ||
1640+ ios->timing == MMC_TIMING_UHS_SDR25)
16271641 && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
16281642 ctrl |= SDHCI_CTRL_HISPD;
16291643 else
@@ -1632,16 +1646,6 @@ static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) · 2 unmodified lines
16321646 if (host->version >= SDHCI_SPEC_300) {
16331647 u16 clk, ctrl_2;
16341648
1635− /* In case of UHS-I modes, set High Speed Enable */
1636− if ((ios->timing == MMC_TIMING_MMC_HS400) ||
1637− (ios->timing == MMC_TIMING_MMC_HS200) ||
1638− (ios->timing == MMC_TIMING_MMC_DDR52) ||
1639− (ios->timing == MMC_TIMING_UHS_SDR50) ||
1640− (ios->timing == MMC_TIMING_UHS_SDR104) ||
1641− (ios->timing == MMC_TIMING_UHS_DDR50) ||
1642− (ios->timing == MMC_TIMING_UHS_SDR25))
1643− ctrl |= SDHCI_CTRL_HISPD;
1644−
16451649 if (!host->preset_enabled) {
16461650 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
16471651 /*
@@ -1948,11 +1952,157 @@ static int sdhci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios) · 300 unmodified lines
19481952 return 0;
19491953 }
19501954
1951−static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1955+static void sdhci_start_tuning(struct sdhci_host *host)
19521956 {
1953− struct sdhci_host *host = mmc_priv(mmc);
19541957 u16 ctrl;
1955− int tuning_loop_counter = MAX_TUNING_LOOP;
1958+
1959+ ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1960+ ctrl |= SDHCI_CTRL_EXEC_TUNING;
1961+ if (host->quirks2 & SDHCI_QUIRK2_TUNING_WORK_AROUND)
1962+ ctrl |= SDHCI_CTRL_TUNED_CLK;
1963+ sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1964+
1965+ /*
1966+ * As per the Host Controller spec v3.00, tuning command
1967+ * generates Buffer Read Ready interrupt, so enable that.
1968+ *
1969+ * Note: The spec clearly says that when tuning sequence
1970+ * is being performed, the controller does not generate
1971+ * interrupts other than Buffer Read Ready interrupt. But
1972+ * to make sure we don't hit a controller bug, we _only_
1973+ * enable Buffer Read Ready interrupt here.
1974+ */
1975+ sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
1976+ sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
1977+}
1978+
1979+static void sdhci_end_tuning(struct sdhci_host *host)
1980+{
1981+ sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1982+ sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
1983+}
1984+
1985+static void sdhci_reset_tuning(struct sdhci_host *host)
1986+{
1987+ u16 ctrl;
1988+
1989+ ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1990+ ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1991+ ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
1992+ sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1993+}
1994+
1995+static void sdhci_abort_tuning(struct sdhci_host *host, u32 opcode,
1996+ unsigned long flags)
1997+{
1998+ sdhci_reset_tuning(host);
1999+
2000+ sdhci_do_reset(host, SDHCI_RESET_CMD);
2001+ sdhci_do_reset(host, SDHCI_RESET_DATA);
2002+
2003+ sdhci_end_tuning(host);
2004+
2005+ spin_unlock_irqrestore(&host->lock, flags);
2006+ mmc_abort_tuning(host->mmc, opcode);
2007+ spin_lock_irqsave(&host->lock, flags);
2008+}
2009+
2010+/*
2011+ * We use sdhci_send_tuning() because mmc_send_tuning() is not a good fit. SDHCI
2012+ * tuning command does not have a data payload (or rather the hardware does it
2013+ * automatically) so mmc_send_tuning() will return -EIO. Also the tuning command
2014+ * interrupt setup is different to other commands and there is no timeout
2015+ * interrupt so special handling is needed.
2016+ */
2017+static void sdhci_send_tuning(struct sdhci_host *host, u32 opcode,
2018+ unsigned long flags)
2019+{
2020+ struct mmc_host *mmc = host->mmc;
2021+ struct mmc_command cmd = {0};
2022+ struct mmc_request mrq = {NULL};
2023+
2024+ cmd.opcode = opcode;
2025+ cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
2026+ cmd.mrq = &mrq;
2027+
2028+ mrq.cmd = &cmd;
2029+ /*
2030+ * In response to CMD19, the card sends 64 bytes of tuning
2031+ * block to the Host Controller. So we set the block size
2032+ * to 64 here.
2033+ */
2034+ if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200 &&
2035+ mmc->ios.bus_width == MMC_BUS_WIDTH_8)
2036+ sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128), SDHCI_BLOCK_SIZE);
2037+ else
2038+ sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64), SDHCI_BLOCK_SIZE);
2039+
2040+ /*
2041+ * The tuning block is sent by the card to the host controller.
2042+ * So we set the TRNS_READ bit in the Transfer Mode register.
2043+ * This also takes care of setting DMA Enable and Multi Block
2044+ * Select in the same register to 0.
2045+ */
2046+ sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
2047+
2048+ sdhci_send_command(host, &cmd);
2049+
2050+ host->cmd = NULL;
2051+
2052+ sdhci_del_timer(host, &mrq);
2053+
2054+ host->tuning_done = 0;
2055+
2056+ spin_unlock_irqrestore(&host->lock, flags);
2057+
2058+ /* Wait for Buffer Read Ready interrupt */
2059+ wait_event_timeout(host->buf_ready_int, (host->tuning_done == 1),
2060+ msecs_to_jiffies(50));
2061+
2062+ spin_lock_irqsave(&host->lock, flags);
2063+}
2064+
2065+static void __sdhci_execute_tuning(struct sdhci_host *host, u32 opcode,
2066+ unsigned long flags)
2067+{
2068+ int i;
2069+
2070+ /*
2071+ * Issue opcode repeatedly till Execute Tuning is set to 0 or the number
2072+ * of loops reaches 40 times.
2073+ */
2074+ for (i = 0; i < MAX_TUNING_LOOP; i++) {
2075+ u16 ctrl;
2076+
2077+ sdhci_send_tuning(host, opcode, flags);
2078+
2079+ if (!host->tuning_done) {
2080+ pr_info("%s: Tuning timeout, falling back to fixed sampling clock\n",
2081+ mmc_hostname(host->mmc));
2082+ sdhci_abort_tuning(host, opcode, flags);
2083+ return;
2084+ }
2085+
2086+ ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2087+ if (!(ctrl & SDHCI_CTRL_EXEC_TUNING)) {
2088+ if (ctrl & SDHCI_CTRL_TUNED_CLK)
2089+ return; /* Success! */
2090+ break;
2091+ }
2092+
2093+ /* eMMC spec does not require a delay between tuning cycles */
2094+ if (opcode == MMC_SEND_TUNING_BLOCK)
2095+ mdelay(1);
2096+ }
2097+
2098+ pr_info("%s: Tuning failed, falling back to fixed sampling clock\n",
2099+ mmc_hostname(host->mmc));
2100+ sdhci_reset_tuning(host);
2101+}
2102+
2103+int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
2104+{
2105+ struct sdhci_host *host = mmc_priv(mmc);
19562106 int err = 0;
19572107 unsigned long flags;
19582108 unsigned int tuning_count = 0;
@@ -2003,144 +2153,22 @@ static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode) · 44 unmodified lines
20032153
20042154 if (host->ops->platform_execute_tuning) {
20052155 spin_unlock_irqrestore(&host->lock, flags);
2006− err = host->ops->platform_execute_tuning(host, opcode);
2007− return err;
2156+ return host->ops->platform_execute_tuning(host, opcode);
20082157 }
20092158
2010− ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2011− ctrl |= SDHCI_CTRL_EXEC_TUNING;
2012− if (host->quirks2 & SDHCI_QUIRK2_TUNING_WORK_AROUND)
2013− ctrl |= SDHCI_CTRL_TUNED_CLK;
2014− sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2015−
2016− /*
2017− * As per the Host Controller spec v3.00, tuning command
2018− * generates Buffer Read Ready interrupt, so enable that.
2019− *
2020− * Note: The spec clearly says that when tuning sequence
2021− * is being performed, the controller does not generate
2022− * interrupts other than Buffer Read Ready interrupt. But
2023− * to make sure we don't hit a controller bug, we _only_
2024− * enable Buffer Read Ready interrupt here.
2025− */
2026− sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
2027− sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
2028−
2029− /*
2030− * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
2031− * of loops reaches 40 times.
2032− */
2033− do {
2034− struct mmc_command cmd = {0};
2035− struct mmc_request mrq = {NULL};
2036−
2037− cmd.opcode = opcode;
2038− cmd.arg = 0;
2039− cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
2040− cmd.retries = 0;
2041− cmd.data = NULL;
2042− cmd.mrq = &mrq;
2043− cmd.error = 0;
2044−
2045− if (tuning_loop_counter-- == 0)
2046− break;
2047−
2048− mrq.cmd = &cmd;
2049−
2050− /*
2051− * In response to CMD19, the card sends 64 bytes of tuning
2052− * block to the Host Controller. So we set the block size
2053− * to 64 here.
2054− */
2055− if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) {
2056− if (mmc->ios.bus_width == MMC_BUS_WIDTH_8)
2057− sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128),
2058− SDHCI_BLOCK_SIZE);
2059− else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4)
2060− sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
2061− SDHCI_BLOCK_SIZE);
2062− } else {
2063− sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
2064− SDHCI_BLOCK_SIZE);
2065− }
2066−
2067− /*
2068− * The tuning block is sent by the card to the host controller.
2069− * So we set the TRNS_READ bit in the Transfer Mode register.
2070− * This also takes care of setting DMA Enable and Multi Block
2071− * Select in the same register to 0.
2072− */
2073− sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
2074−
2075− sdhci_send_command(host, &cmd);
2076−
2077− host->cmd = NULL;
2078− sdhci_del_timer(host, &mrq);
2079−
2080− spin_unlock_irqrestore(&host->lock, flags);
2081− /* Wait for Buffer Read Ready interrupt */
2082− wait_event_timeout(host->buf_ready_int,
2083− (host->tuning_done == 1),
2084− msecs_to_jiffies(50));
2085− spin_lock_irqsave(&host->lock, flags);
2086−
2087− if (!host->tuning_done) {
2088− pr_info(DRIVER_NAME ": Timeout waiting for Buffer Read Ready interrupt during tuning procedure, falling back to fixed sampling clock\n");
2089−
2090− sdhci_do_reset(host, SDHCI_RESET_CMD);
2091− sdhci_do_reset(host, SDHCI_RESET_DATA);
2092−
2093− ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2094− ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2095− ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
2096− sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2097−
2098− err = -EIO;
2099− goto out;
2100− }
2159+ host->mmc->retune_period = tuning_count;
21012160
2102− host->tuning_done = 0;
2161+ sdhci_start_tuning(host);
21032162
2104− ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2163+ __sdhci_execute_tuning(host, opcode, flags);
21052164
2106− /* eMMC spec does not require a delay between tuning cycles */
2107− if (opcode == MMC_SEND_TUNING_BLOCK)
2108− mdelay(1);
2109− } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
2110−
2111− /*
2112− * The Host Driver has exhausted the maximum number of loops allowed,
2113− * so use fixed sampling frequency.
2114− */
2115− if (tuning_loop_counter < 0) {
2116− ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2117− sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2118− }
2119− if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
2120− pr_info(DRIVER_NAME ": Tuning procedure failed, falling back to fixed sampling clock\n");
2121− err = -EIO;
2122− }
2123−
2124−out:
2125− if (tuning_count) {
2126− /*
2127− * In case tuning fails, host controllers which support
2128− * re-tuning can try tuning again at a later time, when the
2129− * re-tuning timer expires. So for these controllers, we
2130− * return 0. Since there might be other controllers who do not
2131− * have this capability, we return error for them.
2132− */
2133− err = 0;
2134− }
2135−
2136− host->mmc->retune_period = err ? 0 : tuning_count;
2137−
2138− sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2139− sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2165+ sdhci_end_tuning(host);
21402166 out_unlock:
21412167 spin_unlock_irqrestore(&host->lock, flags);
2168+
21422169 return err;
21432170 }
2171+EXPORT_SYMBOL_GPL(sdhci_execute_tuning);
21442172
21452173 static int sdhci_select_drive_strength(struct mmc_card *card,
21462174 unsigned int max_dtr, int host_drv,
@@ -2198,8 +2226,7 @@ static void sdhci_post_req(struct mmc_host *mmc, struct mmc_request *mrq, · 51 unmodified lines
21982226 data->host_cookie = COOKIE_UNMAPPED;
21992227 }
22002228
2201−static void sdhci_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
2202− bool is_first_req)
2229+static void sdhci_pre_req(struct mmc_host *mmc, struct mmc_request *mrq)
22032230 {
22042231 struct sdhci_host *host = mmc_priv(mmc);
22052232
@@ -3010,6 +3037,8 @@ static int sdhci_set_dma_mask(struct sdhci_host *host) · 804 unmodified lines
30103037 void __sdhci_read_caps(struct sdhci_host *host, u16 *ver, u32 *caps, u32 *caps1)
30113038 {
30123039 u16 v;
3040+ u64 dt_caps_mask = 0;
3041+ u64 dt_caps = 0;
30133042
30143043 if (host->read_caps)
30153044 return;
@@ -3024,18 +3053,35 @@ void __sdhci_read_caps(struct sdhci_host *host, u16 *ver, u32 *caps, u32 *caps1) · 8 unmodified lines
30243053
30253054 sdhci_do_reset(host, SDHCI_RESET_ALL);
30263055
3056+ of_property_read_u64(mmc_dev(host->mmc)->of_node,
3057+ "sdhci-caps-mask", &dt_caps_mask);
3058+ of_property_read_u64(mmc_dev(host->mmc)->of_node,
3059+ "sdhci-caps", &dt_caps);
3060+
30273061 v = ver ? *ver : sdhci_readw(host, SDHCI_HOST_VERSION);
30283062 host->version = (v & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT;
30293063
30303064 if (host->quirks & SDHCI_QUIRK_MISSING_CAPS)
30313065 return;
30323066
3033− host->caps = caps ? *caps : sdhci_readl(host, SDHCI_CAPABILITIES);
3067+ if (caps) {
3068+ host->caps = *caps;
3069+ } else {
3070+ host->caps = sdhci_readl(host, SDHCI_CAPABILITIES);
3071+ host->caps &= ~lower_32_bits(dt_caps_mask);
3072+ host->caps |= lower_32_bits(dt_caps);
3073+ }
30343074
30353075 if (host->version < SDHCI_SPEC_300)
30363076 return;
30373077
3038− host->caps1 = caps1 ? *caps1 : sdhci_readl(host, SDHCI_CAPABILITIES_1);
3078+ if (caps1) {
3079+ host->caps1 = *caps1;
3080+ } else {
3081+ host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
3082+ host->caps1 &= ~upper_32_bits(dt_caps_mask);
3083+ host->caps1 |= upper_32_bits(dt_caps);
3084+ }
30393085 }
30403086 EXPORT_SYMBOL_GPL(__sdhci_read_caps);
30413087
drivers/mmc/host/sdhci.h+3−1
@@ -656,7 +656,7 @@ extern void sdhci_free_host(struct sdhci_host *host); · 655 unmodified lines
656656
657657 static inline void *sdhci_priv(struct sdhci_host *host)
658658 {
659− return (void *)host->private;
659+ return host->private;
660660 }
661661
662662 extern void sdhci_card_detect(struct sdhci_host *host);
@@ -682,6 +682,7 @@ static inline bool sdhci_sdio_irq_enabled(struct sdhci_host *host) · 19 unmodified lines
682682 u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock,
683683 unsigned int *actual_clock);
684684 void sdhci_set_clock(struct sdhci_host *host, unsigned int clock);
685+void sdhci_enable_clk(struct sdhci_host *host, u16 clk);
685686 void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
686687 unsigned short vdd);
687688 void sdhci_set_power_noreg(struct sdhci_host *host, unsigned char mode,
@@ -689,6 +690,7 @@ void sdhci_set_power_noreg(struct sdhci_host *host, unsigned char mode, · 1 unmodified line
689690 void sdhci_set_bus_width(struct sdhci_host *host, int width);
690691 void sdhci_reset(struct sdhci_host *host, u8 mask);
691692 void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing);
693+int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
692694
693695 #ifdef CONFIG_PM
694696 extern int sdhci_suspend_host(struct sdhci_host *host);
drivers/mmc/host/sh_mobile_sdhi.c+273−1
@@ -47,31 +47,69 @@ · 46 unmodified lines
4747
4848 #define host_to_priv(host) container_of((host)->pdata, struct sh_mobile_sdhi, mmc_data)
4949
50+struct sh_mobile_sdhi_scc {
51+ unsigned long clk_rate; /* clock rate for SDR104 */
52+ u32 tap; /* sampling clock position for SDR104 */
53+};
54+
5055 struct sh_mobile_sdhi_of_data {
5156 unsigned long tmio_flags;
57+ u32 tmio_ocr_mask;
5258 unsigned long capabilities;
5359 unsigned long capabilities2;
5460 enum dma_slave_buswidth dma_buswidth;
5561 dma_addr_t dma_rx_offset;
5662 unsigned bus_shift;
63+ int scc_offset;
64+ struct sh_mobile_sdhi_scc *taps;
65+ int taps_num;
5766 };
5867
5968 static const struct sh_mobile_sdhi_of_data of_default_cfg = {
6069 .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT,
6170 };
6271
72+static const struct sh_mobile_sdhi_of_data of_rz_compatible = {
73+ .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_32BIT_DATA_PORT,
74+ .tmio_ocr_mask = MMC_VDD_32_33,
75+ .capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ,
76+};
77+
6378 static const struct sh_mobile_sdhi_of_data of_rcar_gen1_compatible = {
6479 .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_WRPROTECT_DISABLE |
6580 TMIO_MMC_CLK_ACTUAL,
6681 .capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ,
6782 };
6883
84+/* Definitions for sampling clocks */
85+static struct sh_mobile_sdhi_scc rcar_gen2_scc_taps[] = {
86+ {
87+ .clk_rate = 156000000,
88+ .tap = 0x00000703,
89+ },
90+ {
91+ .clk_rate = 0,
92+ .tap = 0x00000300,
93+ },
94+};
95+
6996 static const struct sh_mobile_sdhi_of_data of_rcar_gen2_compatible = {
7097 .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_WRPROTECT_DISABLE |
7198 TMIO_MMC_CLK_ACTUAL | TMIO_MMC_MIN_RCAR2,
7299 .capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ,
73100 .dma_buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES,
74101 .dma_rx_offset = 0x2000,
102+ .scc_offset = 0x0300,
103+ .taps = rcar_gen2_scc_taps,
104+ .taps_num = ARRAY_SIZE(rcar_gen2_scc_taps),
105+};
106+
107+/* Definitions for sampling clocks */
108+static struct sh_mobile_sdhi_scc rcar_gen3_scc_taps[] = {
109+ {
110+ .clk_rate = 0,
111+ .tap = 0x00000300,
112+ },
75113 };
76114
77115 static const struct sh_mobile_sdhi_of_data of_rcar_gen3_compatible = {
@@ -79,6 +117,9 @@ static const struct sh_mobile_sdhi_of_data of_rcar_gen3_compatible = { · 1 unmodified line
79117 TMIO_MMC_CLK_ACTUAL | TMIO_MMC_MIN_RCAR2,
80118 .capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ,
81119 .bus_shift = 2,
120+ .scc_offset = 0x1000,
121+ .taps = rcar_gen3_scc_taps,
122+ .taps_num = ARRAY_SIZE(rcar_gen3_scc_taps),
82123 };
83124
84125 static const struct of_device_id sh_mobile_sdhi_of_match[] = {
@@ -86,6 +127,7 @@ static const struct of_device_id sh_mobile_sdhi_of_match[] = { · 1 unmodified line
86127 { .compatible = "renesas,sdhi-sh73a0", .data = &of_default_cfg, },
87128 { .compatible = "renesas,sdhi-r8a73a4", .data = &of_default_cfg, },
88129 { .compatible = "renesas,sdhi-r8a7740", .data = &of_default_cfg, },
130+ { .compatible = "renesas,sdhi-r7s72100", .data = &of_rz_compatible, },
89131 { .compatible = "renesas,sdhi-r8a7778", .data = &of_rcar_gen1_compatible, },
90132 { .compatible = "renesas,sdhi-r8a7779", .data = &of_rcar_gen1_compatible, },
91133 { .compatible = "renesas,sdhi-r8a7790", .data = &of_rcar_gen2_compatible, },
@@ -105,6 +147,7 @@ struct sh_mobile_sdhi { · 13 unmodified lines
105147 struct tmio_mmc_dma dma_priv;
106148 struct pinctrl *pinctrl;
107149 struct pinctrl_state *pins_default, *pins_uhs;
150+ void __iomem *scc_ctl;
108151 };
109152
110153 static void sh_mobile_sdhi_sdbuf_width(struct tmio_mmc_host *host, int width)
@@ -255,6 +298,201 @@ static int sh_mobile_sdhi_start_signal_voltage_switch(struct mmc_host *mmc, · 144 unmodified lines
255298 return pinctrl_select_state(priv->pinctrl, pin_state);
256299 }
257300
301+/* SCC registers */
302+#define SH_MOBILE_SDHI_SCC_DTCNTL 0x000
303+#define SH_MOBILE_SDHI_SCC_TAPSET 0x002
304+#define SH_MOBILE_SDHI_SCC_DT2FF 0x004
305+#define SH_MOBILE_SDHI_SCC_CKSEL 0x006
306+#define SH_MOBILE_SDHI_SCC_RVSCNTL 0x008
307+#define SH_MOBILE_SDHI_SCC_RVSREQ 0x00A
308+
309+/* Definitions for values the SH_MOBILE_SDHI_SCC_DTCNTL register */
310+#define SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN BIT(0)
311+#define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT 16
312+#define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK 0xff
313+
314+/* Definitions for values the SH_MOBILE_SDHI_SCC_CKSEL register */
315+#define SH_MOBILE_SDHI_SCC_CKSEL_DTSEL BIT(0)
316+/* Definitions for values the SH_MOBILE_SDHI_SCC_RVSCNTL register */
317+#define SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN BIT(0)
318+/* Definitions for values the SH_MOBILE_SDHI_SCC_RVSREQ register */
319+#define SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR BIT(2)
320+
321+static inline u32 sd_scc_read32(struct tmio_mmc_host *host,
322+ struct sh_mobile_sdhi *priv, int addr)
323+{
324+ return readl(priv->scc_ctl + (addr << host->bus_shift));
325+}
326+
327+static inline void sd_scc_write32(struct tmio_mmc_host *host,
328+ struct sh_mobile_sdhi *priv,
329+ int addr, u32 val)
330+{
331+ writel(val, priv->scc_ctl + (addr << host->bus_shift));
332+}
333+
334+static unsigned int sh_mobile_sdhi_init_tuning(struct tmio_mmc_host *host)
335+{
336+ struct sh_mobile_sdhi *priv;
337+
338+ if (!(host->mmc->caps & MMC_CAP_UHS_SDR104))
339+ return 0;
340+
341+ priv = host_to_priv(host);
342+
343+ /* set sampling clock selection range */
344+ sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL,
345+ 0x8 << SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT);
346+
347+ /* Initialize SCC */
348+ sd_ctrl_write32_as_16_and_16(host, CTL_STATUS, 0x0);
349+
350+ sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL,
351+ SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN |
352+ sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL));
353+
354+ sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
355+ sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
356+
357+ sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL,
358+ SH_MOBILE_SDHI_SCC_CKSEL_DTSEL |
359+ sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL));
360+
361+ sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
362+ sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
363+
364+ sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
365+ ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN &
366+ sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
367+
368+ sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, host->scc_tappos);
369+
370+ /* Read TAPNUM */
371+ return (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL) >>
372+ SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) &
373+ SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK;
374+}
375+
376+static void sh_mobile_sdhi_prepare_tuning(struct tmio_mmc_host *host,
377+ unsigned long tap)
378+{
379+ struct sh_mobile_sdhi *priv = host_to_priv(host);
380+
381+ /* Set sampling clock position */
382+ sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, tap);
383+}
384+
385+#define SH_MOBILE_SDHI_MAX_TAP 3
386+
387+static int sh_mobile_sdhi_select_tuning(struct tmio_mmc_host *host)
388+{
389+ struct sh_mobile_sdhi *priv = host_to_priv(host);
390+ unsigned long tap_cnt; /* counter of tuning success */
391+ unsigned long tap_set; /* tap position */
392+ unsigned long tap_start;/* start position of tuning success */
393+ unsigned long tap_end; /* end position of tuning success */
394+ unsigned long ntap; /* temporary counter of tuning success */
395+ unsigned long i;
396+
397+ /* Clear SCC_RVSREQ */
398+ sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0);
399+
400+ /*
401+ * Find the longest consecutive run of successful probes. If that
402+ * is more than SH_MOBILE_SDHI_MAX_TAP probes long then use the
403+ * center index as the tap.
404+ */
405+ tap_cnt = 0;
406+ ntap = 0;
407+ tap_start = 0;
408+ tap_end = 0;
409+ for (i = 0; i < host->tap_num * 2; i++) {
410+ if (test_bit(i, host->taps))
411+ ntap++;
412+ else {
413+ if (ntap > tap_cnt) {
414+ tap_start = i - ntap;
415+ tap_end = i - 1;
416+ tap_cnt = ntap;
417+ }
418+ ntap = 0;
419+ }
420+ }
421+
422+ if (ntap > tap_cnt) {
423+ tap_start = i - ntap;
424+ tap_end = i - 1;
425+ tap_cnt = ntap;
426+ }
427+
428+ if (tap_cnt >= SH_MOBILE_SDHI_MAX_TAP)
429+ tap_set = (tap_start + tap_end) / 2 % host->tap_num;
430+ else
431+ return -EIO;
432+
433+ /* Set SCC */
434+ sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, tap_set);
435+
436+ /* Enable auto re-tuning */
437+ sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
438+ SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN |
439+ sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
440+
441+ return 0;
442+}
443+
444+
445+static bool sh_mobile_sdhi_check_scc_error(struct tmio_mmc_host *host)
446+{
447+ struct sh_mobile_sdhi *priv;
448+
449+ if (!(host->mmc->caps & MMC_CAP_UHS_SDR104))
450+ return 0;
451+
452+ priv = host_to_priv(host);
453+
454+ /* Check SCC error */
455+ if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL) &
456+ SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN &&
457+ sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ) &
458+ SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR) {
459+ /* Clear SCC error */
460+ sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0);
461+ return true;
462+ }
463+
464+ return false;
465+}
466+
467+static void sh_mobile_sdhi_hw_reset(struct tmio_mmc_host *host)
468+{
469+ struct sh_mobile_sdhi *priv;
470+
471+ if (!(host->mmc->caps & MMC_CAP_UHS_SDR104))
472+ return;
473+
474+ priv = host_to_priv(host);
475+
476+ /* Reset SCC */
477+ sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
478+ sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
479+
480+ sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL,
481+ ~SH_MOBILE_SDHI_SCC_CKSEL_DTSEL &
482+ sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL));
483+
484+ sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
485+ sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
486+
487+ sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
488+ ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN &
489+ sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
490+
491+ sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
492+ ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN &
493+ sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
494+}
495+
258496 static int sh_mobile_sdhi_wait_idle(struct tmio_mmc_host *host)
259497 {
260498 int timeout = 1000;
@@ -325,7 +563,7 @@ static int sh_mobile_sdhi_probe(struct platform_device *pdev) · 64 unmodified lines
325563 struct tmio_mmc_data *mmd = pdev->dev.platform_data;
326564 struct tmio_mmc_host *host;
327565 struct resource *res;
328− int irq, ret, i = 0;
566+ int irq, ret, i;
329567 struct tmio_mmc_dma *dma_priv;
330568
331569 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
@@ -364,6 +602,7 @@ static int sh_mobile_sdhi_probe(struct platform_device *pdev) · 32 unmodified lines
364602 const struct sh_mobile_sdhi_of_data *of_data = of_id->data;
365603
366604 mmc_data->flags |= of_data->tmio_flags;
605+ mmc_data->ocr_mask = of_data->tmio_ocr_mask;
367606 mmc_data->capabilities |= of_data->capabilities;
368607 mmc_data->capabilities2 |= of_data->capabilities2;
369608 mmc_data->dma_rx_offset = of_data->dma_rx_offset;
@@ -384,6 +623,11 @@ static int sh_mobile_sdhi_probe(struct platform_device *pdev) · 14 unmodified lines
384623 host->card_busy = sh_mobile_sdhi_card_busy;
385624 host->start_signal_voltage_switch =
386625 sh_mobile_sdhi_start_signal_voltage_switch;
626+ host->init_tuning = sh_mobile_sdhi_init_tuning;
627+ host->prepare_tuning = sh_mobile_sdhi_prepare_tuning;
628+ host->select_tuning = sh_mobile_sdhi_select_tuning;
629+ host->check_scc_error = sh_mobile_sdhi_check_scc_error;
630+ host->hw_reset = sh_mobile_sdhi_hw_reset;
387631 }
388632
389633 /* Orginally registers were 16 bit apart, could be 32 or 64 nowadays */
@@ -424,6 +668,34 @@ static int sh_mobile_sdhi_probe(struct platform_device *pdev) · 34 unmodified lines
424668 if (ret < 0)
425669 goto efree;
426670
671+ if (host->mmc->caps & MMC_CAP_UHS_SDR104) {
672+ host->mmc->caps |= MMC_CAP_HW_RESET;
673+
674+ if (of_id && of_id->data) {
675+ const struct sh_mobile_sdhi_of_data *of_data;
676+ const struct sh_mobile_sdhi_scc *taps;
677+ bool hit = false;
678+
679+ of_data = of_id->data;
680+ taps = of_data->taps;
681+
682+ for (i = 0; i < of_data->taps_num; i++) {
683+ if (taps[i].clk_rate == 0 ||
684+ taps[i].clk_rate == host->mmc->f_max) {
685+ host->scc_tappos = taps->tap;
686+ hit = true;
687+ break;
688+ }
689+ }
690+
691+ if (!hit)
692+ dev_warn(&host->pdev->dev, "Unknown clock rate for SDR104\n");
693+
694+ priv->scc_ctl = host->ctl + of_data->scc_offset;
695+ }
696+ }
697+
698+ i = 0;
427699 while (1) {
428700 irq = platform_get_irq(pdev, i);
429701 if (irq < 0)
drivers/mmc/host/sunxi-mmc.c+10−5
@@ -822,10 +822,13 @@ static void sunxi_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) · 821 unmodified lines
822822 break;
823823
824824 case MMC_POWER_UP:
825− host->ferror = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc,
826− ios->vdd);
827− if (host->ferror)
828− return;
825+ if (!IS_ERR(mmc->supply.vmmc)) {
826+ host->ferror = mmc_regulator_set_ocr(mmc,
827+ mmc->supply.vmmc,
828+ ios->vdd);
829+ if (host->ferror)
830+ return;
831+ }
829832
830833 if (!IS_ERR(mmc->supply.vqmmc)) {
831834 host->ferror = regulator_enable(mmc->supply.vqmmc);
@@ -847,7 +850,9 @@ static void sunxi_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) · 15 unmodified lines
847850 case MMC_POWER_OFF:
848851 dev_dbg(mmc_dev(mmc), "power off!\n");
849852 sunxi_mmc_reset_host(host);
850− mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
853+ if (!IS_ERR(mmc->supply.vmmc))
854+ mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
855+
851856 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled)
852857 regulator_disable(mmc->supply.vqmmc);
853858 host->vqmmc_enabled = false;
drivers/mmc/host/tmio_mmc.h+31−1
@@ -153,9 +153,12 @@ struct tmio_mmc_host { · 152 unmodified lines
153153 struct mutex ios_lock; /* protect set_ios() context */
154154 bool native_hotplug;
155155 bool sdio_irq_enabled;
156+ u32 scc_tappos;
156157
157− int (*write16_hook)(struct tmio_mmc_host *host, int addr);
158+ /* Mandatory callback */
158159 int (*clk_enable)(struct tmio_mmc_host *host);
160+
161+ /* Optional callbacks */
159162 unsigned int (*clk_update)(struct tmio_mmc_host *host,
160163 unsigned int new_clock);
161164 void (*clk_disable)(struct tmio_mmc_host *host);
@@ -164,6 +167,21 @@ struct tmio_mmc_host { · 2 unmodified lines
164167 int (*card_busy)(struct mmc_host *mmc);
165168 int (*start_signal_voltage_switch)(struct mmc_host *mmc,
166169 struct mmc_ios *ios);
170+ int (*write16_hook)(struct tmio_mmc_host *host, int addr);
171+ void (*hw_reset)(struct tmio_mmc_host *host);
172+ void (*prepare_tuning)(struct tmio_mmc_host *host, unsigned long tap);
173+ bool (*check_scc_error)(struct tmio_mmc_host *host);
174+
175+ /*
176+ * Mandatory callback for tuning to occur which is optional for SDR50
177+ * and mandatory for SDR104.
178+ */
179+ unsigned int (*init_tuning)(struct tmio_mmc_host *host);
180+ int (*select_tuning)(struct tmio_mmc_host *host);
181+
182+ /* Tuning values: 1 for success, 0 for failure */
183+ DECLARE_BITMAP(taps, BITS_PER_BYTE * sizeof(long));
184+ unsigned int tap_num;
167185 };
168186
169187 struct tmio_mmc_host *tmio_mmc_host_alloc(struct platform_device *pdev);
@@ -245,6 +263,12 @@ static inline u32 sd_ctrl_read16_and_16_as_32(struct tmio_mmc_host *host, int ad · 75 unmodified lines
245263 readw(host->ctl + ((addr + 2) << host->bus_shift)) << 16;
246264 }
247265
266+static inline void sd_ctrl_read32_rep(struct tmio_mmc_host *host, int addr,
267+ u32 *buf, int count)
268+{
269+ readsl(host->ctl + (addr << host->bus_shift), buf, count);
270+}
271+
248272 static inline void sd_ctrl_write16(struct tmio_mmc_host *host, int addr, u16 val)
249273 {
250274 /* If there is a hook and it returns non-zero then there
@@ -267,4 +291,10 @@ static inline void sd_ctrl_write32_as_16_and_16(struct tmio_mmc_host *host, int · 16 unmodified lines
267291 writew(val >> 16, host->ctl + ((addr + 2) << host->bus_shift));
268292 }
269293
294+static inline void sd_ctrl_write32_rep(struct tmio_mmc_host *host, int addr,
295+ const u32 *buf, int count)
296+{
297+ writesl(host->ctl + (addr << host->bus_shift), buf, count);
298+}
299+
270300 #endif
drivers/mmc/host/tmio_mmc_pio.c+111−8
@@ -22,7 +22,6 @@ · 21 unmodified lines
2222 * TODO:
2323 * Investigate using a workqueue for PIO transfers
2424 * Eliminate FIXMEs
25− * SDIO support
2625 * Better Power management
2726 * Handle MMC errors better
2827 * double buffer support
@@ -36,6 +35,7 @@ · 7 unmodified lines
3635 #include <linux/io.h>
3736 #include <linux/irq.h>
3837 #include <linux/mfd/tmio.h>
38+#include <linux/mmc/card.h>
3939 #include <linux/mmc/host.h>
4040 #include <linux/mmc/mmc.h>
4141 #include <linux/mmc/slot-gpio.h>
@@ -298,6 +298,9 @@ static void tmio_mmc_finish_request(struct tmio_mmc_host *host) · 256 unmodified lines
298298 if (mrq->cmd->error || (mrq->data && mrq->data->error))
299299 tmio_mmc_abort_dma(host);
300300
301+ if (host->check_scc_error)
302+ host->check_scc_error(host);
303+
301304 mmc_request_done(host->mmc, mrq);
302305 }
303306
@@ -393,6 +396,36 @@ static void tmio_mmc_transfer_data(struct tmio_mmc_host *host, · 89 unmodified lines
393396 /*
394397 * Transfer the data
395398 */
399+ if (host->pdata->flags & TMIO_MMC_32BIT_DATA_PORT) {
400+ u8 data[4] = { };
401+
402+ if (is_read)
403+ sd_ctrl_read32_rep(host, CTL_SD_DATA_PORT, (u32 *)buf,
404+ count >> 2);
405+ else
406+ sd_ctrl_write32_rep(host, CTL_SD_DATA_PORT, (u32 *)buf,
407+ count >> 2);
408+
409+ /* if count was multiple of 4 */
410+ if (!(count & 0x3))
411+ return;
412+
413+ buf8 = (u8 *)(buf + (count >> 2));
414+ count %= 4;
415+
416+ if (is_read) {
417+ sd_ctrl_read32_rep(host, CTL_SD_DATA_PORT,
418+ (u32 *)data, 1);
419+ memcpy(buf8, data, count);
420+ } else {
421+ memcpy(data, buf8, count);
422+ sd_ctrl_write32_rep(host, CTL_SD_DATA_PORT,
423+ (u32 *)data, 1);
424+ }
425+
426+ return;
427+ }
428+
396429 if (is_read)
397430 sd_ctrl_read16_rep(host, CTL_SD_DATA_PORT, buf, count >> 1);
398431 else
@@ -522,7 +555,7 @@ void tmio_mmc_do_data_irq(struct tmio_mmc_host *host) · 123 unmodified lines
522555 schedule_work(&host->done);
523556 }
524557
525−static void tmio_mmc_data_irq(struct tmio_mmc_host *host)
558+static void tmio_mmc_data_irq(struct tmio_mmc_host *host, unsigned int stat)
526559 {
527560 struct mmc_data *data;
528561 spin_lock(&host->lock);
@@ -531,6 +564,9 @@ static void tmio_mmc_data_irq(struct tmio_mmc_host *host) · 2 unmodified lines
531564 if (!data)
532565 goto out;
533566
567+ if (stat & TMIO_STAT_CRCFAIL || stat & TMIO_STAT_STOPBIT_ERR ||
568+ stat & TMIO_STAT_TXUNDERRUN)
569+ data->error = -EILSEQ;
534570 if (host->chan_tx && (data->flags & MMC_DATA_WRITE) && !host->force_pio) {
535571 u32 status = sd_ctrl_read16_and_16_as_32(host, CTL_STATUS);
536572 bool done = false;
@@ -579,8 +615,6 @@ static void tmio_mmc_cmd_irq(struct tmio_mmc_host *host, · 42 unmodified lines
579615 goto out;
580616 }
581617
582− host->cmd = NULL;
583−
584618 /* This controller is sicker than the PXA one. Not only do we need to
585619 * drop the top 8 bits of the first response word, we also need to
586620 * modify the order of the response for short response command types.
@@ -600,14 +634,16 @@ static void tmio_mmc_cmd_irq(struct tmio_mmc_host *host, · 13 unmodified lines
600634
601635 if (stat & TMIO_STAT_CMDTIMEOUT)
602636 cmd->error = -ETIMEDOUT;
603− else if (stat & TMIO_STAT_CRCFAIL && cmd->flags & MMC_RSP_CRC)
637+ else if ((stat & TMIO_STAT_CRCFAIL && cmd->flags & MMC_RSP_CRC) ||
638+ stat & TMIO_STAT_STOPBIT_ERR ||
639+ stat & TMIO_STAT_CMD_IDX_ERR)
604640 cmd->error = -EILSEQ;
605641
606642 /* If there is data to handle we enable data IRQs here, and
607643 * we will ultimatley finish the request in the data_end handler.
608644 * If theres no data or we encountered an error, finish now.
609645 */
610− if (host->data && !cmd->error) {
646+ if (host->data && (!cmd->error || cmd->error == -EILSEQ)) {
611647 if (host->data->flags & MMC_DATA_READ) {
612648 if (host->force_pio || !host->chan_rx)
613649 tmio_mmc_enable_mmc_irqs(host, TMIO_MASK_READOP);
@@ -668,7 +704,7 @@ static bool __tmio_mmc_sdcard_irq(struct tmio_mmc_host *host, · 54 unmodified lines
668704 /* Data transfer completion */
669705 if (ireg & TMIO_STAT_DATAEND) {
670706 tmio_mmc_ack_mmc_irqs(host, TMIO_STAT_DATAEND);
671− tmio_mmc_data_irq(host);
707+ tmio_mmc_data_irq(host, status);
672708 return true;
673709 }
674710
@@ -687,7 +723,7 @@ static void tmio_mmc_sdio_irq(int irq, void *devid) · 12 unmodified lines
687723 return;
688724
689725 status = sd_ctrl_read16(host, CTL_SDIO_STATUS);
690− ireg = status & TMIO_SDIO_MASK_ALL & ~host->sdcard_irq_mask;
726+ ireg = status & TMIO_SDIO_MASK_ALL & ~host->sdio_irq_mask;
691727
692728 sdio_status = status & ~TMIO_SDIO_MASK_ALL;
693729 if (pdata->flags & TMIO_MMC_SDIO_STATUS_QUIRK)
@@ -756,6 +792,63 @@ static int tmio_mmc_start_data(struct tmio_mmc_host *host, · 62 unmodified lines
756792 return 0;
757793 }
758794
795+static void tmio_mmc_hw_reset(struct mmc_host *mmc)
796+{
797+ struct tmio_mmc_host *host = mmc_priv(mmc);
798+
799+ if (host->hw_reset)
800+ host->hw_reset(host);
801+}
802+
803+static int tmio_mmc_execute_tuning(struct mmc_host *mmc, u32 opcode)
804+{
805+ struct tmio_mmc_host *host = mmc_priv(mmc);
806+ int i, ret = 0;
807+
808+ if (!host->tap_num) {
809+ if (!host->init_tuning || !host->select_tuning)
810+ /* Tuning is not supported */
811+ goto out;
812+
813+ host->tap_num = host->init_tuning(host);
814+ if (!host->tap_num)
815+ /* Tuning is not supported */
816+ goto out;
817+ }
818+
819+ if (host->tap_num * 2 >= sizeof(host->taps) * BITS_PER_BYTE) {
820+ dev_warn_once(&host->pdev->dev,
821+ "Too many taps, skipping tuning. Please consider updating size of taps field of tmio_mmc_host\n");
822+ goto out;
823+ }
824+
825+ bitmap_zero(host->taps, host->tap_num * 2);
826+
827+ /* Issue CMD19 twice for each tap */
828+ for (i = 0; i < 2 * host->tap_num; i++) {
829+ if (host->prepare_tuning)
830+ host->prepare_tuning(host, i % host->tap_num);
831+
832+ ret = mmc_send_tuning(mmc, opcode, NULL);
833+ if (ret && ret != -EILSEQ)
834+ goto out;
835+ if (ret == 0)
836+ set_bit(i, host->taps);
837+
838+ mdelay(1);
839+ }
840+
841+ ret = host->select_tuning(host);
842+
843+out:
844+ if (ret < 0) {
845+ dev_warn(&host->pdev->dev, "Tuning procedure failed\n");
846+ tmio_mmc_hw_reset(mmc);
847+ }
848+
849+ return ret;
850+}
851+
759852 /* Process requests from the MMC layer */
760853 static void tmio_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
761854 {
@@ -972,6 +1065,8 @@ static struct mmc_host_ops tmio_mmc_ops = { · 210 unmodified lines
9721065 .get_cd = mmc_gpio_get_cd,
9731066 .enable_sdio_irq = tmio_mmc_enable_sdio_irq,
9741067 .multi_io_quirk = tmio_multi_io_quirk,
1068+ .hw_reset = tmio_mmc_hw_reset,
1069+ .execute_tuning = tmio_mmc_execute_tuning,
9751070 };
9761071
9771072 static int tmio_mmc_init_ocr(struct tmio_mmc_host *host)
@@ -1218,6 +1313,11 @@ int tmio_mmc_host_runtime_suspend(struct device *dev) · 240 unmodified lines
12181313 }
12191314 EXPORT_SYMBOL(tmio_mmc_host_runtime_suspend);
12201315
1316+static bool tmio_mmc_can_retune(struct tmio_mmc_host *host)
1317+{
1318+ return host->tap_num && mmc_can_retune(host->mmc);
1319+}
1320+
12211321 int tmio_mmc_host_runtime_resume(struct device *dev)
12221322 {
12231323 struct mmc_host *mmc = dev_get_drvdata(dev);
@@ -1231,6 +1331,9 @@ int tmio_mmc_host_runtime_resume(struct device *dev) · 7 unmodified lines
12311331
12321332 tmio_mmc_enable_dma(host, true);
12331333
1334+ if (tmio_mmc_can_retune(host) && host->select_tuning(host))
1335+ dev_warn(&host->pdev->dev, "Tuning selection failed\n");
1336+
12341337 return 0;
12351338 }
12361339 EXPORT_SYMBOL(tmio_mmc_host_runtime_resume);
drivers/mmc/host/wbsd.c+7−4
@@ -1395,23 +1395,25 @@ static void wbsd_request_dma(struct wbsd_host *host, int dma) · 1394 unmodified lines
13951395 */
13961396 host->dma_addr = dma_map_single(mmc_dev(host->mmc), host->dma_buffer,
13971397 WBSD_DMA_SIZE, DMA_BIDIRECTIONAL);
1398+ if (dma_mapping_error(mmc_dev(host->mmc), host->dma_addr))
1399+ goto kfree;
13981400
13991401 /*
14001402 * ISA DMA must be aligned on a 64k basis.
14011403 */
14021404 if ((host->dma_addr & 0xffff) != 0)
1403− goto kfree;
1405+ goto unmap;
14041406 /*
14051407 * ISA cannot access memory above 16 MB.
14061408 */
14071409 else if (host->dma_addr >= 0x1000000)
1408− goto kfree;
1410+ goto unmap;
14091411
14101412 host->dma = dma;
14111413
14121414 return;
14131415
1414−kfree:
1416+unmap:
14151417 /*
14161418 * If we've gotten here then there is some kind of alignment bug
14171419 */
@@ -1421,6 +1423,7 @@ kfree: · 3 unmodified lines
14211423 WBSD_DMA_SIZE, DMA_BIDIRECTIONAL);
14221424 host->dma_addr = 0;
14231425
1426+kfree:
14241427 kfree(host->dma_buffer);
14251428 host->dma_buffer = NULL;
14261429
@@ -1434,7 +1437,7 @@ err: · 7 unmodified lines
14341437
14351438 static void wbsd_release_dma(struct wbsd_host *host)
14361439 {
1437− if (host->dma_addr) {
1440+ if (!dma_mapping_error(mmc_dev(host->mmc), host->dma_addr)) {
14381441 dma_unmap_single(mmc_dev(host->mmc), host->dma_addr,
14391442 WBSD_DMA_SIZE, DMA_BIDIRECTIONAL);
14401443 }
drivers/soc/Kconfig+1−2
@@ -1,8 +1,7 @@
11 menu "SOC (System On Chip) specific Drivers"
22
33 source "drivers/soc/bcm/Kconfig"
4−source "drivers/soc/fsl/qbman/Kconfig"
5−source "drivers/soc/fsl/qe/Kconfig"
4+source "drivers/soc/fsl/Kconfig"
65 source "drivers/soc/mediatek/Kconfig"
76 source "drivers/soc/qcom/Kconfig"
87 source "drivers/soc/rockchip/Kconfig"
drivers/soc/fsl/Kconfig+18−0
@@ -0,0 +1,18 @@
1+#
2+# Freescale SOC drivers
3+#
4+
5+source "drivers/soc/fsl/qbman/Kconfig"
6+source "drivers/soc/fsl/qe/Kconfig"
7+
8+config FSL_GUTS
9+ bool
10+ select SOC_BUS
11+ help
12+ The global utilities block controls power management, I/O device
13+ enabling, power-onreset(POR) configuration monitoring, alternate
14+ function selection for multiplexed signals,and clock control.
15+ This driver is to manage and access global utilities block.
16+ Initially only reading SVR and registering soc device are supported.
17+ Other guts accesses, such as reading RCW, should eventually be moved
18+ into this driver as well.
drivers/soc/fsl/Makefile+1−0
@@ -5,3 +5,4 @@ · 4 unmodified lines
55 obj-$(CONFIG_FSL_DPAA) += qbman/
66 obj-$(CONFIG_QUICC_ENGINE) += qe/
77 obj-$(CONFIG_CPM) += qe/
8+obj-$(CONFIG_FSL_GUTS) += guts.o
drivers/soc/fsl/guts.c+239−0
@@ -0,0 +1,239 @@
1+/*
2+ * Freescale QorIQ Platforms GUTS Driver
3+ *
4+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
5+ *
6+ * This program is free software; you can redistribute it and/or modify
7+ * it under the terms of the GNU General Public License as published by
8+ * the Free Software Foundation; either version 2 of the License, or
9+ * (at your option) any later version.
10+ */
11+
12+#include <linux/io.h>
13+#include <linux/slab.h>
14+#include <linux/module.h>
15+#include <linux/of_fdt.h>
16+#include <linux/sys_soc.h>
17+#include <linux/of_address.h>
18+#include <linux/platform_device.h>
19+#include <linux/fsl/guts.h>
20+
21+struct guts {
22+ struct ccsr_guts __iomem *regs;
23+ bool little_endian;
24+};
25+
26+struct fsl_soc_die_attr {
27+ char *die;
28+ u32 svr;
29+ u32 mask;
30+};
31+
32+static struct guts *guts;
33+static struct soc_device_attribute soc_dev_attr;
34+static struct soc_device *soc_dev;
35+
36+
37+/* SoC die attribute definition for QorIQ platform */
38+static const struct fsl_soc_die_attr fsl_soc_die[] = {
39+ /*
40+ * Power Architecture-based SoCs T Series
41+ */
42+
43+ /* Die: T4240, SoC: T4240/T4160/T4080 */
44+ { .die = "T4240",
45+ .svr = 0x82400000,
46+ .mask = 0xfff00000,
47+ },
48+ /* Die: T1040, SoC: T1040/T1020/T1042/T1022 */
49+ { .die = "T1040",
50+ .svr = 0x85200000,
51+ .mask = 0xfff00000,
52+ },
53+ /* Die: T2080, SoC: T2080/T2081 */
54+ { .die = "T2080",
55+ .svr = 0x85300000,
56+ .mask = 0xfff00000,
57+ },
58+ /* Die: T1024, SoC: T1024/T1014/T1023/T1013 */
59+ { .die = "T1024",
60+ .svr = 0x85400000,
61+ .mask = 0xfff00000,
62+ },
63+
64+ /*
65+ * ARM-based SoCs LS Series
66+ */
67+
68+ /* Die: LS1043A, SoC: LS1043A/LS1023A */
69+ { .die = "LS1043A",
70+ .svr = 0x87920000,
71+ .mask = 0xffff0000,
72+ },
73+ /* Die: LS2080A, SoC: LS2080A/LS2040A/LS2085A */
74+ { .die = "LS2080A",
75+ .svr = 0x87010000,
76+ .mask = 0xff3f0000,
77+ },
78+ /* Die: LS1088A, SoC: LS1088A/LS1048A/LS1084A/LS1044A */
79+ { .die = "LS1088A",
80+ .svr = 0x87030000,
81+ .mask = 0xff3f0000,
82+ },
83+ /* Die: LS1012A, SoC: LS1012A */
84+ { .die = "LS1012A",
85+ .svr = 0x87040000,
86+ .mask = 0xffff0000,
87+ },
88+ /* Die: LS1046A, SoC: LS1046A/LS1026A */
89+ { .die = "LS1046A",
90+ .svr = 0x87070000,
91+ .mask = 0xffff0000,
92+ },
93+ /* Die: LS2088A, SoC: LS2088A/LS2048A/LS2084A/LS2044A */
94+ { .die = "LS2088A",
95+ .svr = 0x87090000,
96+ .mask = 0xff3f0000,
97+ },
98+ /* Die: LS1021A, SoC: LS1021A/LS1020A/LS1022A */
99+ { .die = "LS1021A",
100+ .svr = 0x87000000,
101+ .mask = 0xfff70000,
102+ },
103+ { },
104+};
105+
106+static const struct fsl_soc_die_attr *fsl_soc_die_match(
107+ u32 svr, const struct fsl_soc_die_attr *matches)
108+{
109+ while (matches->svr) {
110+ if (matches->svr == (svr & matches->mask))
111+ return matches;
112+ matches++;
113+ };
114+ return NULL;
115+}
116+
117+u32 fsl_guts_get_svr(void)
118+{
119+ u32 svr = 0;
120+
121+ if (!guts || !guts->regs)
122+ return svr;
123+
124+ if (guts->little_endian)
125+ svr = ioread32(&guts->regs->svr);
126+ else
127+ svr = ioread32be(&guts->regs->svr);
128+
129+ return svr;
130+}
131+EXPORT_SYMBOL(fsl_guts_get_svr);
132+
133+static int fsl_guts_probe(struct platform_device *pdev)
134+{
135+ struct device_node *root, *np = pdev->dev.of_node;
136+ struct device *dev = &pdev->dev;
137+ struct resource *res;
138+ const struct fsl_soc_die_attr *soc_die;
139+ const char *machine;
140+ u32 svr;
141+
142+ /* Initialize guts */
143+ guts = devm_kzalloc(dev, sizeof(*guts), GFP_KERNEL);
144+ if (!guts)
145+ return -ENOMEM;
146+
147+ guts->little_endian = of_property_read_bool(np, "little-endian");
148+
149+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
150+ guts->regs = devm_ioremap_resource(dev, res);
151+ if (IS_ERR(guts->regs))
152+ return PTR_ERR(guts->regs);
153+
154+ /* Register soc device */
155+ root = of_find_node_by_path("/");
156+ if (of_property_read_string(root, "model", &machine))
157+ of_property_read_string_index(root, "compatible", 0, &machine);
158+ of_node_put(root);
159+ if (machine)
160+ soc_dev_attr.machine = devm_kstrdup(dev, machine, GFP_KERNEL);
161+
162+ svr = fsl_guts_get_svr();
163+ soc_die = fsl_soc_die_match(svr, fsl_soc_die);
164+ if (soc_die) {
165+ soc_dev_attr.family = devm_kasprintf(dev, GFP_KERNEL,
166+ "QorIQ %s", soc_die->die);
167+ } else {
168+ soc_dev_attr.family = devm_kasprintf(dev, GFP_KERNEL, "QorIQ");
169+ }
170+ soc_dev_attr.soc_id = devm_kasprintf(dev, GFP_KERNEL,
171+ "svr:0x%08x", svr);
172+ soc_dev_attr.revision = devm_kasprintf(dev, GFP_KERNEL, "%d.%d",
173+ (svr >> 4) & 0xf, svr & 0xf);
174+
175+ soc_dev = soc_device_register(&soc_dev_attr);
176+ if (IS_ERR(soc_dev))
177+ return PTR_ERR(soc_dev);
178+
179+ pr_info("Machine: %s\n", soc_dev_attr.machine);
180+ pr_info("SoC family: %s\n", soc_dev_attr.family);
181+ pr_info("SoC ID: %s, Revision: %s\n",
182+ soc_dev_attr.soc_id, soc_dev_attr.revision);
183+ return 0;
184+}
185+
186+static int fsl_guts_remove(struct platform_device *dev)
187+{
188+ soc_device_unregister(soc_dev);
189+ return 0;
190+}
191+
192+/*
193+ * Table for matching compatible strings, for device tree
194+ * guts node, for Freescale QorIQ SOCs.
195+ */
196+static const struct of_device_id fsl_guts_of_match[] = {
197+ { .compatible = "fsl,qoriq-device-config-1.0", },
198+ { .compatible = "fsl,qoriq-device-config-2.0", },
199+ { .compatible = "fsl,p1010-guts", },
200+ { .compatible = "fsl,p1020-guts", },
201+ { .compatible = "fsl,p1021-guts", },
202+ { .compatible = "fsl,p1022-guts", },
203+ { .compatible = "fsl,p1023-guts", },
204+ { .compatible = "fsl,p2020-guts", },
205+ { .compatible = "fsl,bsc9131-guts", },
206+ { .compatible = "fsl,bsc9132-guts", },
207+ { .compatible = "fsl,mpc8536-guts", },
208+ { .compatible = "fsl,mpc8544-guts", },
209+ { .compatible = "fsl,mpc8548-guts", },
210+ { .compatible = "fsl,mpc8568-guts", },
211+ { .compatible = "fsl,mpc8569-guts", },
212+ { .compatible = "fsl,mpc8572-guts", },
213+ { .compatible = "fsl,ls1021a-dcfg", },
214+ { .compatible = "fsl,ls1043a-dcfg", },
215+ { .compatible = "fsl,ls2080a-dcfg", },
216+ {}
217+};
218+MODULE_DEVICE_TABLE(of, fsl_guts_of_match);
219+
220+static struct platform_driver fsl_guts_driver = {
221+ .driver = {
222+ .name = "fsl-guts",
223+ .of_match_table = fsl_guts_of_match,
224+ },
225+ .probe = fsl_guts_probe,
226+ .remove = fsl_guts_remove,
227+};
228+
229+static int __init fsl_guts_init(void)
230+{
231+ return platform_driver_register(&fsl_guts_driver);
232+}
233+core_initcall(fsl_guts_init);
234+
235+static void __exit fsl_guts_exit(void)
236+{
237+ platform_driver_unregister(&fsl_guts_driver);
238+}
239+module_exit(fsl_guts_exit);
include/linux/fsl/guts.h+77−48
@@ -29,83 +29,112 @@ · 28 unmodified lines
2929 * #ifdefs.
3030 */
3131 struct ccsr_guts {
32− __be32 porpllsr; /* 0x.0000 - POR PLL Ratio Status Register */
33− __be32 porbmsr; /* 0x.0004 - POR Boot Mode Status Register */
34− __be32 porimpscr; /* 0x.0008 - POR I/O Impedance Status and Control Register */
35− __be32 pordevsr; /* 0x.000c - POR I/O Device Status Register */
36− __be32 pordbgmsr; /* 0x.0010 - POR Debug Mode Status Register */
37− __be32 pordevsr2; /* 0x.0014 - POR device status register 2 */
32+ u32 porpllsr; /* 0x.0000 - POR PLL Ratio Status Register */
33+ u32 porbmsr; /* 0x.0004 - POR Boot Mode Status Register */
34+ u32 porimpscr; /* 0x.0008 - POR I/O Impedance Status and
35+ * Control Register
36+ */
37+ u32 pordevsr; /* 0x.000c - POR I/O Device Status Register */
38+ u32 pordbgmsr; /* 0x.0010 - POR Debug Mode Status Register */
39+ u32 pordevsr2; /* 0x.0014 - POR device status register 2 */
3840 u8 res018[0x20 - 0x18];
39− __be32 porcir; /* 0x.0020 - POR Configuration Information Register */
41+ u32 porcir; /* 0x.0020 - POR Configuration Information
42+ * Register
43+ */
4044 u8 res024[0x30 - 0x24];
41− __be32 gpiocr; /* 0x.0030 - GPIO Control Register */
45+ u32 gpiocr; /* 0x.0030 - GPIO Control Register */
4246 u8 res034[0x40 - 0x34];
43− __be32 gpoutdr; /* 0x.0040 - General-Purpose Output Data Register */
47+ u32 gpoutdr; /* 0x.0040 - General-Purpose Output Data
48+ * Register
49+ */
4450 u8 res044[0x50 - 0x44];
45− __be32 gpindr; /* 0x.0050 - General-Purpose Input Data Register */
51+ u32 gpindr; /* 0x.0050 - General-Purpose Input Data
52+ * Register
53+ */
4654 u8 res054[0x60 - 0x54];
47− __be32 pmuxcr; /* 0x.0060 - Alternate Function Signal Multiplex Control */
48− __be32 pmuxcr2; /* 0x.0064 - Alternate function signal multiplex control 2 */
49− __be32 dmuxcr; /* 0x.0068 - DMA Mux Control Register */
55+ u32 pmuxcr; /* 0x.0060 - Alternate Function Signal
56+ * Multiplex Control
57+ */
58+ u32 pmuxcr2; /* 0x.0064 - Alternate function signal
59+ * multiplex control 2
60+ */
61+ u32 dmuxcr; /* 0x.0068 - DMA Mux Control Register */
5062 u8 res06c[0x70 - 0x6c];
51− __be32 devdisr; /* 0x.0070 - Device Disable Control */
63+ u32 devdisr; /* 0x.0070 - Device Disable Control */
5264 #define CCSR_GUTS_DEVDISR_TB1 0x00001000
5365 #define CCSR_GUTS_DEVDISR_TB0 0x00004000
54− __be32 devdisr2; /* 0x.0074 - Device Disable Control 2 */
66+ u32 devdisr2; /* 0x.0074 - Device Disable Control 2 */
5567 u8 res078[0x7c - 0x78];
56− __be32 pmjcr; /* 0x.007c - 4 Power Management Jog Control Register */
57− __be32 powmgtcsr; /* 0x.0080 - Power Management Status and Control Register */
58− __be32 pmrccr; /* 0x.0084 - Power Management Reset Counter Configuration Register */
59− __be32 pmpdccr; /* 0x.0088 - Power Management Power Down Counter Configuration Register */
60− __be32 pmcdr; /* 0x.008c - 4Power management clock disable register */
61− __be32 mcpsumr; /* 0x.0090 - Machine Check Summary Register */
62− __be32 rstrscr; /* 0x.0094 - Reset Request Status and Control Register */
63− __be32 ectrstcr; /* 0x.0098 - Exception reset control register */
64− __be32 autorstsr; /* 0x.009c - Automatic reset status register */
65− __be32 pvr; /* 0x.00a0 - Processor Version Register */
66− __be32 svr; /* 0x.00a4 - System Version Register */
68+ u32 pmjcr; /* 0x.007c - 4 Power Management Jog Control
69+ * Register
70+ */
71+ u32 powmgtcsr; /* 0x.0080 - Power Management Status and
72+ * Control Register
73+ */
74+ u32 pmrccr; /* 0x.0084 - Power Management Reset Counter
75+ * Configuration Register
76+ */
77+ u32 pmpdccr; /* 0x.0088 - Power Management Power Down Counter
78+ * Configuration Register
79+ */
80+ u32 pmcdr; /* 0x.008c - 4Power management clock disable
81+ * register
82+ */
83+ u32 mcpsumr; /* 0x.0090 - Machine Check Summary Register */
84+ u32 rstrscr; /* 0x.0094 - Reset Request Status and
85+ * Control Register
86+ */
87+ u32 ectrstcr; /* 0x.0098 - Exception reset control register */
88+ u32 autorstsr; /* 0x.009c - Automatic reset status register */
89+ u32 pvr; /* 0x.00a0 - Processor Version Register */
90+ u32 svr; /* 0x.00a4 - System Version Register */
6791 u8 res0a8[0xb0 - 0xa8];
68− __be32 rstcr; /* 0x.00b0 - Reset Control Register */
92+ u32 rstcr; /* 0x.00b0 - Reset Control Register */
6993 u8 res0b4[0xc0 - 0xb4];
70− __be32 iovselsr; /* 0x.00c0 - I/O voltage select status register
94+ u32 iovselsr; /* 0x.00c0 - I/O voltage select status register
7195 Called 'elbcvselcr' on 86xx SOCs */
7296 u8 res0c4[0x100 - 0xc4];
73− __be32 rcwsr[16]; /* 0x.0100 - Reset Control Word Status registers
97+ u32 rcwsr[16]; /* 0x.0100 - Reset Control Word Status registers
7498 There are 16 registers */
7599 u8 res140[0x224 - 0x140];
76− __be32 iodelay1; /* 0x.0224 - IO delay control register 1 */
77− __be32 iodelay2; /* 0x.0228 - IO delay control register 2 */
100+ u32 iodelay1; /* 0x.0224 - IO delay control register 1 */
101+ u32 iodelay2; /* 0x.0228 - IO delay control register 2 */
78102 u8 res22c[0x604 - 0x22c];
79− __be32 pamubypenr; /* 0x.604 - PAMU bypass enable register */
103+ u32 pamubypenr; /* 0x.604 - PAMU bypass enable register */
80104 u8 res608[0x800 - 0x608];
81− __be32 clkdvdr; /* 0x.0800 - Clock Divide Register */
105+ u32 clkdvdr; /* 0x.0800 - Clock Divide Register */
82106 u8 res804[0x900 - 0x804];
83− __be32 ircr; /* 0x.0900 - Infrared Control Register */
107+ u32 ircr; /* 0x.0900 - Infrared Control Register */
84108 u8 res904[0x908 - 0x904];
85− __be32 dmacr; /* 0x.0908 - DMA Control Register */
109+ u32 dmacr; /* 0x.0908 - DMA Control Register */
86110 u8 res90c[0x914 - 0x90c];
87− __be32 elbccr; /* 0x.0914 - eLBC Control Register */
111+ u32 elbccr; /* 0x.0914 - eLBC Control Register */
88112 u8 res918[0xb20 - 0x918];
89− __be32 ddr1clkdr; /* 0x.0b20 - DDR1 Clock Disable Register */
90− __be32 ddr2clkdr; /* 0x.0b24 - DDR2 Clock Disable Register */
91− __be32 ddrclkdr; /* 0x.0b28 - DDR Clock Disable Register */
113+ u32 ddr1clkdr; /* 0x.0b20 - DDR1 Clock Disable Register */
114+ u32 ddr2clkdr; /* 0x.0b24 - DDR2 Clock Disable Register */
115+ u32 ddrclkdr; /* 0x.0b28 - DDR Clock Disable Register */
92116 u8 resb2c[0xe00 - 0xb2c];
93− __be32 clkocr; /* 0x.0e00 - Clock Out Select Register */
117+ u32 clkocr; /* 0x.0e00 - Clock Out Select Register */
94118 u8 rese04[0xe10 - 0xe04];
95− __be32 ddrdllcr; /* 0x.0e10 - DDR DLL Control Register */
119+ u32 ddrdllcr; /* 0x.0e10 - DDR DLL Control Register */
96120 u8 rese14[0xe20 - 0xe14];
97− __be32 lbcdllcr; /* 0x.0e20 - LBC DLL Control Register */
98− __be32 cpfor; /* 0x.0e24 - L2 charge pump fuse override register */
121+ u32 lbcdllcr; /* 0x.0e20 - LBC DLL Control Register */
122+ u32 cpfor; /* 0x.0e24 - L2 charge pump fuse override
123+ * register
124+ */
99125 u8 rese28[0xf04 - 0xe28];
100− __be32 srds1cr0; /* 0x.0f04 - SerDes1 Control Register 0 */
101− __be32 srds1cr1; /* 0x.0f08 - SerDes1 Control Register 0 */
126+ u32 srds1cr0; /* 0x.0f04 - SerDes1 Control Register 0 */
127+ u32 srds1cr1; /* 0x.0f08 - SerDes1 Control Register 0 */
102128 u8 resf0c[0xf2c - 0xf0c];
103− __be32 itcr; /* 0x.0f2c - Internal transaction control register */
129+ u32 itcr; /* 0x.0f2c - Internal transaction control
130+ * register
131+ */
104132 u8 resf30[0xf40 - 0xf30];
105− __be32 srds2cr0; /* 0x.0f40 - SerDes2 Control Register 0 */
106− __be32 srds2cr1; /* 0x.0f44 - SerDes2 Control Register 0 */
133+ u32 srds2cr0; /* 0x.0f40 - SerDes2 Control Register 0 */
134+ u32 srds2cr1; /* 0x.0f44 - SerDes2 Control Register 0 */
107135 } __attribute__ ((packed));
108136
137+u32 fsl_guts_get_svr(void);
109138
110139 /* Alternate function signal multiplex control */
111140 #define MPC85xx_PMUXCR_QE(x) (0x8000 >> (x))
include/linux/mfd/tmio.h+5−0
@@ -99,6 +99,11 @@ · 98 unmodified lines
9999 */
100100 #define TMIO_MMC_SDIO_STATUS_QUIRK (1 << 8)
101101
102+/*
103+ * Some controllers have a 32-bit wide data port register
104+ */
105+#define TMIO_MMC_32BIT_DATA_PORT (1 << 9)
106+
102107 /*
103108 * Some controllers allows to set SDx actual clock
104109 */
include/linux/mmc/card.h+2−12
@@ -89,6 +89,8 @@ struct mmc_ext_csd { · 88 unmodified lines
8989 unsigned int boot_ro_lock; /* ro lock support */
9090 bool boot_ro_lockable;
9191 bool ffu_capable; /* Firmware upgrade support */
92+ bool cmdq_support; /* Command Queue supported */
93+ unsigned int cmdq_depth; /* Command Queue depth */
9294 #define MMC_FIRMWARE_LEN 8
9395 u8 fwrev[MMC_FIRMWARE_LEN]; /* FW version */
9496 u8 raw_exception_status; /* 54 */
@@ -207,18 +209,6 @@ struct sdio_func_tuple; · 112 unmodified lines
207209
208210 #define SDIO_MAX_FUNCS 7
209211
210−enum mmc_blk_status {
211− MMC_BLK_SUCCESS = 0,
212− MMC_BLK_PARTIAL,
213− MMC_BLK_CMD_ERR,
214− MMC_BLK_RETRY,
215− MMC_BLK_ABORT,
216− MMC_BLK_DATA_ERR,
217− MMC_BLK_ECC_ERR,
218− MMC_BLK_NOMEDIUM,
219− MMC_BLK_NEW_REQUEST,
220−};
221−
222212 /* The number of MMC physical partitions. These consist of:
223213 * boot partitions (2), general purpose partitions (4) and
224214 * RPMB partition (1) in MMC v4.4.
include/linux/mmc/core.h+15−1
@@ -15,6 +15,18 @@ struct request; · 14 unmodified lines
1515 struct mmc_data;
1616 struct mmc_request;
1717
18+enum mmc_blk_status {
19+ MMC_BLK_SUCCESS = 0,
20+ MMC_BLK_PARTIAL,
21+ MMC_BLK_CMD_ERR,
22+ MMC_BLK_RETRY,
23+ MMC_BLK_ABORT,
24+ MMC_BLK_DATA_ERR,
25+ MMC_BLK_ECC_ERR,
26+ MMC_BLK_NOMEDIUM,
27+ MMC_BLK_NEW_REQUEST,
28+};
29+
1830 struct mmc_command {
1931 u32 opcode;
2032 u32 arg;
@@ -150,7 +162,8 @@ struct mmc_async_req; · 129 unmodified lines
150162 extern int mmc_stop_bkops(struct mmc_card *);
151163 extern int mmc_read_bkops_status(struct mmc_card *);
152164 extern struct mmc_async_req *mmc_start_req(struct mmc_host *,
153− struct mmc_async_req *, int *);
165+ struct mmc_async_req *,
166+ enum mmc_blk_status *);
154167 extern int mmc_interrupt_hpi(struct mmc_card *);
155168 extern void mmc_wait_for_req(struct mmc_host *, struct mmc_request *);
156169 extern void mmc_wait_for_req_done(struct mmc_host *host,
@@ -163,6 +176,7 @@ extern int mmc_wait_for_app_cmd(struct mmc_host *, struct mmc_card *, · 6 unmodified lines
163176 extern void mmc_start_bkops(struct mmc_card *card, bool from_exception);
164177 extern int mmc_switch(struct mmc_card *, u8, u8, u8, unsigned int);
165178 extern int mmc_send_tuning(struct mmc_host *host, u32 opcode, int *cmd_error);
179+extern int mmc_abort_tuning(struct mmc_host *host, u32 opcode);
166180 extern int mmc_get_ext_csd(struct mmc_card *card, u8 **new_ext_csd);
167181
168182 #define MMC_ERASE_ARG 0x00000000
include/linux/mmc/dw_mmc.h+6−0
@@ -39,6 +39,12 @@ enum { · 38 unmodified lines
3939 EVENT_DATA_ERROR,
4040 };
4141
42+enum dw_mci_cookie {
43+ COOKIE_UNMAPPED,
44+ COOKIE_PRE_MAPPED, /* mapped by pre_req() of dwmmc */
45+ COOKIE_MAPPED, /* mapped by prepare_data() of dwmmc */
46+};
47+
4248 struct mmc_data;
4349
4450 enum {
include/linux/mmc/host.h+7−10
@@ -93,8 +93,7 @@ struct mmc_host_ops { · 92 unmodified lines
9393 */
9494 void (*post_req)(struct mmc_host *host, struct mmc_request *req,
9595 int err);
96− void (*pre_req)(struct mmc_host *host, struct mmc_request *req,
97− bool is_first_req);
96+ void (*pre_req)(struct mmc_host *host, struct mmc_request *req);
9897 void (*request)(struct mmc_host *host, struct mmc_request *req);
9998
10099 /*
@@ -173,7 +172,7 @@ struct mmc_async_req { · 72 unmodified lines
173172 * Check error status of completed mmc request.
174173 * Returns 0 if success otherwise non zero.
175174 */
176− int (*err_check) (struct mmc_card *, struct mmc_async_req *);
175+ enum mmc_blk_status (*err_check)(struct mmc_card *, struct mmc_async_req *);
177176 };
178177
179178 /**
@@ -198,14 +197,12 @@ struct mmc_slot { · 18 unmodified lines
198197 * @is_new_req wake up reason was new request
199198 * @is_waiting_last_req mmc context waiting for single running request
200199 * @wait wait queue
201− * @lock lock to protect data fields
202200 */
203201 struct mmc_context_info {
204202 bool is_done_rcv;
205203 bool is_new_req;
206204 bool is_waiting_last_req;
207205 wait_queue_head_t wait;
208− spinlock_t lock;
209206 };
210207
211208 struct regulator;
@@ -495,11 +492,6 @@ static inline int mmc_host_uhs(struct mmc_host *host) · 283 unmodified lines
495492 MMC_CAP_UHS_DDR50);
496493 }
497494
498−static inline int mmc_host_packed_wr(struct mmc_host *host)
499−{
500− return host->caps2 & MMC_CAP2_PACKED_WR;
501−}
502−
503495 static inline int mmc_card_hs(struct mmc_card *card)
504496 {
505497 return card->host->ios.timing == MMC_TIMING_SD_HS ||
@@ -546,6 +538,11 @@ static inline void mmc_retune_recheck(struct mmc_host *host) · 40 unmodified lines
546538 host->retune_now = 1;
547539 }
548540
541+static inline bool mmc_can_retune(struct mmc_host *host)
542+{
543+ return host->can_retune == 1;
544+}
545+
549546 void mmc_retune_pause(struct mmc_host *host);
550547 void mmc_retune_unpause(struct mmc_host *host);
551548
include/linux/mmc/mmc.h+17−0
@@ -84,6 +84,13 @@ · 83 unmodified lines
8484 #define MMC_APP_CMD 55 /* ac [31:16] RCA R1 */
8585 #define MMC_GEN_CMD 56 /* adtc [0] RD/WR R1 */
8686
87+ /* class 11 */
88+#define MMC_QUE_TASK_PARAMS 44 /* ac [20:16] task id R1 */
89+#define MMC_QUE_TASK_ADDR 45 /* ac [31:0] data addr R1 */
90+#define MMC_EXECUTE_READ_TASK 46 /* adtc [20:16] task id R1 */
91+#define MMC_EXECUTE_WRITE_TASK 47 /* adtc [20:16] task id R1 */
92+#define MMC_CMDQ_TASK_MGMT 48 /* ac [20:16] task id R1b */
93+
8794 static inline bool mmc_op_multi(u32 opcode)
8895 {
8996 return opcode == MMC_WRITE_MULTIPLE_BLOCK ||
@@ -272,6 +279,7 @@ struct _mmc_csd { · 182 unmodified lines
272279 * EXT_CSD fields
273280 */
274281
282+#define EXT_CSD_CMDQ_MODE_EN 15 /* R/W */
275283 #define EXT_CSD_FLUSH_CACHE 32 /* W */
276284 #define EXT_CSD_CACHE_CTRL 33 /* R/W */
277285 #define EXT_CSD_POWER_OFF_NOTIFICATION 34 /* R/W */
@@ -331,6 +339,8 @@ struct _mmc_csd { · 53 unmodified lines
331339 #define EXT_CSD_CACHE_SIZE 249 /* RO, 4 bytes */
332340 #define EXT_CSD_PWR_CL_DDR_200_360 253 /* RO */
333341 #define EXT_CSD_FIRMWARE_VERSION 254 /* RO, 8 bytes */
342+#define EXT_CSD_CMDQ_DEPTH 307 /* RO */
343+#define EXT_CSD_CMDQ_SUPPORT 308 /* RO */
334344 #define EXT_CSD_SUPPORTED_MODE 493 /* RO */
335345 #define EXT_CSD_TAG_UNIT_SIZE 498 /* RO */
336346 #define EXT_CSD_DATA_TAG_SUPPORT 499 /* RO */
@@ -437,6 +447,13 @@ struct _mmc_csd { · 100 unmodified lines
437447 */
438448 #define EXT_CSD_MANUAL_BKOPS_MASK 0x01
439449
450+/*
451+ * Command Queue
452+ */
453+#define EXT_CSD_CMDQ_MODE_ENABLED BIT(0)
454+#define EXT_CSD_CMDQ_DEPTH_MASK GENMASK(4, 0)
455+#define EXT_CSD_CMDQ_SUPPORTED BIT(0)
456+
440457 /*
441458 * MMC_SWITCH access modes
442459 */
include/linux/mmc/slot-gpio.h+1−0
@@ -29,5 +29,6 @@ int mmc_gpiod_request_ro(struct mmc_host *host, const char *con_id, · 28 unmodified lines
2929 void mmc_gpio_set_cd_isr(struct mmc_host *host,
3030 irqreturn_t (*isr)(int irq, void *dev_id));
3131 void mmc_gpiod_request_cd_irq(struct mmc_host *host);
32+bool mmc_can_gpio_cd(struct mmc_host *host);
3233
3334 #endif
include/linux/sys_soc.h+9−0
@@ -13,6 +13,7 @@ struct soc_device_attribute { · 12 unmodified lines
1313 const char *family;
1414 const char *revision;
1515 const char *soc_id;
16+ const void *data;
1617 };
1718
1819 /**
@@ -34,4 +35,12 @@ void soc_device_unregister(struct soc_device *soc_dev); · 15 unmodified lines
3435 */
3536 struct device *soc_device_to_device(struct soc_device *soc);
3637
38+#ifdef CONFIG_SOC_BUS
39+const struct soc_device_attribute *soc_device_match(
40+ const struct soc_device_attribute *matches);
41+#else
42+static inline const struct soc_device_attribute *soc_device_match(
43+ const struct soc_device_attribute *matches) { return NULL; }
44+#endif
45+
3746 #endif /* __SOC_BUS_H */
include/uapi/linux/mmc/ioctl.h+1−1
@@ -69,6 +69,6 @@ struct mmc_ioc_multi_cmd { · 68 unmodified lines
6969 * is enforced per ioctl call. For larger data transfers, use the normal
7070 * block device operations.
7171 */
72−#define MMC_IOC_MAX_BYTES (512L * 256)
72+#define MMC_IOC_MAX_BYTES (512L * 1024)
7373 #define MMC_IOC_MAX_CMDS 255
7474 #endif /* LINUX_MMC_IOCTL_H */