Tiger Lake is the followon to Ice Lake. From the perspective of Intel cstate residency counters, there is nothing changed compared with Ice Lake. Share icl_cstates with Ice Lake. Update the comments for Tiger Lake. The External Design Specification (EDS) is not published yet. It comes from an authoritative internal source. The patch has been tested on real hardware.
Unified · Split
| @@ -50,44 +50,44 @@ · 49 unmodified lines | ||
| 50 | 50 | * MSR_CORE_C6_RESIDENCY: CORE C6 Residency Counter |
| 51 | 51 | * perf code: 0x02 |
| 52 | 52 | * Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW, |
| 53 | − * SKL,KNL,GLM,CNL,KBL,CML,ICL | |
| 53 | + * SKL,KNL,GLM,CNL,KBL,CML,ICL,TGL | |
| 54 | 54 | * Scope: Core |
| 55 | 55 | * MSR_CORE_C7_RESIDENCY: CORE C7 Residency Counter |
| 56 | 56 | * perf code: 0x03 |
| 57 | 57 | * Available model: SNB,IVB,HSW,BDW,SKL,CNL,KBL,CML, |
| 58 | − * ICL | |
| 58 | + * ICL,TGL | |
| 59 | 59 | * Scope: Core |
| 60 | 60 | * MSR_PKG_C2_RESIDENCY: Package C2 Residency Counter. |
| 61 | 61 | * perf code: 0x00 |
| 62 | 62 | * Available model: SNB,IVB,HSW,BDW,SKL,KNL,GLM,CNL, |
| 63 | − * KBL,CML,ICL | |
| 63 | + * KBL,CML,ICL,TGL | |
| 64 | 64 | * Scope: Package (physical package) |
| 65 | 65 | * MSR_PKG_C3_RESIDENCY: Package C3 Residency Counter. |
| 66 | 66 | * perf code: 0x01 |
| 67 | 67 | * Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,KNL, |
| 68 | − * GLM,CNL,KBL,CML,ICL | |
| 68 | + * GLM,CNL,KBL,CML,ICL,TGL | |
| 69 | 69 | * Scope: Package (physical package) |
| 70 | 70 | * MSR_PKG_C6_RESIDENCY: Package C6 Residency Counter. |
| 71 | 71 | * perf code: 0x02 |
| 72 | 72 | * Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW |
| 73 | − * SKL,KNL,GLM,CNL,KBL,CML,ICL | |
| 73 | + * SKL,KNL,GLM,CNL,KBL,CML,ICL,TGL | |
| 74 | 74 | * Scope: Package (physical package) |
| 75 | 75 | * MSR_PKG_C7_RESIDENCY: Package C7 Residency Counter. |
| 76 | 76 | * perf code: 0x03 |
| 77 | 77 | * Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,CNL, |
| 78 | − * KBL,CML,ICL | |
| 78 | + * KBL,CML,ICL,TGL | |
| 79 | 79 | * Scope: Package (physical package) |
| 80 | 80 | * MSR_PKG_C8_RESIDENCY: Package C8 Residency Counter. |
| 81 | 81 | * perf code: 0x04 |
| 82 | − * Available model: HSW ULT,KBL,CNL,CML,ICL | |
| 82 | + * Available model: HSW ULT,KBL,CNL,CML,ICL,TGL | |
| 83 | 83 | * Scope: Package (physical package) |
| 84 | 84 | * MSR_PKG_C9_RESIDENCY: Package C9 Residency Counter. |
| 85 | 85 | * perf code: 0x05 |
| 86 | − * Available model: HSW ULT,KBL,CNL,CML,ICL | |
| 86 | + * Available model: HSW ULT,KBL,CNL,CML,ICL,TGL | |
| 87 | 87 | * Scope: Package (physical package) |
| 88 | 88 | * MSR_PKG_C10_RESIDENCY: Package C10 Residency Counter. |
| 89 | 89 | * perf code: 0x06 |
| 90 | − * Available model: HSW ULT,KBL,GLM,CNL,CML,ICL | |
| 90 | + * Available model: HSW ULT,KBL,GLM,CNL,CML,ICL,TGL | |
| 91 | 91 | * Scope: Package (physical package) |
| 92 | 92 | * |
| 93 | 93 | */ |
| @@ -645,6 +645,8 @@ static const struct x86_cpu_id intel_cstates_match[] __initconst = { · 551 unmodified lines | ||
| 645 | 645 | |
| 646 | 646 | X86_CSTATES_MODEL(INTEL_FAM6_ICELAKE_L, icl_cstates), |
| 647 | 647 | X86_CSTATES_MODEL(INTEL_FAM6_ICELAKE, icl_cstates), |
| 648 | + X86_CSTATES_MODEL(INTEL_FAM6_TIGERLAKE_L, icl_cstates), | |
| 649 | + X86_CSTATES_MODEL(INTEL_FAM6_TIGERLAKE, icl_cstates), | |
| 648 | 650 | { }, |
| 649 | 651 | }; |
| 650 | 652 | MODULE_DEVICE_TABLE(x86cpu, intel_cstates_match); |