_NR_CLKS which can be used to register clocks via nr_clk_ids. The clock IDs are started from 1. So, _NR_CLKS should be defined to "the last clock id + 1"
Unified · Split
| @@ -166,7 +166,7 @@ · 165 unmodified lines | ||
| 166 | 166 | #define GOUT_CLKCMU_PERIC1_IP 248 |
| 167 | 167 | #define GOUT_CLKCMU_PERIS_BUS 249 |
| 168 | 168 | |
| 169 | −#define TOP_NR_CLK 249 | |
| 169 | +#define TOP_NR_CLK 250 | |
| 170 | 170 | |
| 171 | 171 | /* CMU_BUSMC */ |
| 172 | 172 | #define CLK_MOUT_BUSMC_BUS_USER 1 |
| @@ -174,7 +174,7 @@ · 1 unmodified line | ||
| 174 | 174 | #define CLK_GOUT_BUSMC_PDMA0_PCLK 3 |
| 175 | 175 | #define CLK_GOUT_BUSMC_SPDMA_PCLK 4 |
| 176 | 176 | |
| 177 | −#define BUSMC_NR_CLK 4 | |
| 177 | +#define BUSMC_NR_CLK 5 | |
| 178 | 178 | |
| 179 | 179 | /* CMU_CORE */ |
| 180 | 180 | #define CLK_MOUT_CORE_BUS_USER 1 |
| @@ -183,7 +183,7 @@ · 2 unmodified lines | ||
| 183 | 183 | #define CLK_GOUT_CORE_CCI_PCLK 4 |
| 184 | 184 | #define CLK_GOUT_CORE_CMU_CORE_PCLK 5 |
| 185 | 185 | |
| 186 | −#define CORE_NR_CLK 5 | |
| 186 | +#define CORE_NR_CLK 6 | |
| 187 | 187 | |
| 188 | 188 | /* CMU_FSYS2 */ |
| 189 | 189 | #define CLK_MOUT_FSYS2_BUS_USER 1 |
| @@ -194,7 +194,7 @@ · 4 unmodified lines | ||
| 194 | 194 | #define CLK_GOUT_FSYS2_UFS_EMBD1_ACLK 6 |
| 195 | 195 | #define CLK_GOUT_FSYS2_UFS_EMBD1_UNIPRO 7 |
| 196 | 196 | |
| 197 | −#define FSYS2_NR_CLK 7 | |
| 197 | +#define FSYS2_NR_CLK 8 | |
| 198 | 198 | |
| 199 | 199 | /* CMU_PERIC0 */ |
| 200 | 200 | #define CLK_MOUT_PERIC0_BUS_USER 1 |
| @@ -240,7 +240,7 @@ · 39 unmodified lines | ||
| 240 | 240 | #define CLK_GOUT_PERIC0_PCLK_10 41 |
| 241 | 241 | #define CLK_GOUT_PERIC0_PCLK_11 42 |
| 242 | 242 | |
| 243 | −#define PERIC0_NR_CLK 42 | |
| 243 | +#define PERIC0_NR_CLK 43 | |
| 244 | 244 | |
| 245 | 245 | /* CMU_PERIC1 */ |
| 246 | 246 | #define CLK_MOUT_PERIC1_BUS_USER 1 |
| @@ -286,7 +286,7 @@ · 39 unmodified lines | ||
| 286 | 286 | #define CLK_GOUT_PERIC1_PCLK_10 41 |
| 287 | 287 | #define CLK_GOUT_PERIC1_PCLK_11 42 |
| 288 | 288 | |
| 289 | −#define PERIC1_NR_CLK 42 | |
| 289 | +#define PERIC1_NR_CLK 43 | |
| 290 | 290 | |
| 291 | 291 | /* CMU_PERIS */ |
| 292 | 292 | #define CLK_MOUT_PERIS_BUS_USER 1 |
| @@ -294,6 +294,6 @@ · 1 unmodified line | ||
| 294 | 294 | #define CLK_GOUT_WDT_CLUSTER0 3 |
| 295 | 295 | #define CLK_GOUT_WDT_CLUSTER1 4 |
| 296 | 296 | |
| 297 | −#define PERIS_NR_CLK 4 | |
| 297 | +#define PERIS_NR_CLK 5 | |
| 298 | 298 | |
| 299 | 299 | #endif /* _DT_BINDINGS_CLOCK_EXYNOSAUTOV9_H */ |