Pull drm updates from Dave Airlie: "This is going to rebuild more than drm as it adds a new helper to list.h for doing bulk updates. Seemed like a reasonable addition to me. Otherwise the usual merge window stuff lots of i915 and amdgpu, not so much nouveau, and piles of everything else. Core: - Adds a new list.h helper for doing bulk list updates for TTM. - Don't leak fb address in smem_start to userspace (comes with EXPORT workaround for people using mali out of tree hacks) - udmabuf device to turn memfd regions into dma-buf - Per-plane blend mode property - ref/unref replacements with get/put - fbdev conflicting framebuffers code cleaned up - host-endian format variants - panel orientation quirk for Acer One 10 bridge: - TI SN65DSI86 chip support vkms: - GEM support. - Cursor support amdgpu: - Merge amdkfd and amdgpu into one module - CEC over DP AUX support - Picasso APU support + VCN dynamic powergating - Raven2 APU support - Vega20 enablement + kfd support - ACP powergating improvements - ABGR/XBGR display support - VCN jpeg support - xGMI support - DC i2c/aux cleanup - Ycbcr 4:2:0 support - GPUVM improvements - Powerplay and powerplay endian fixes - Display underflow fixes vmwgfx: - Move vmwgfx specific TTM code to vmwgfx - Split out vmwgfx buffer/resource validation code - Atomic operation rework bochs: - use more helpers - format/byteorder improvements qxl: - use more helpers i915: - GGTT coherency getparam - Turn off resource streamer API - More Icelake enablement + DMC firmware - Full PPGTT for Ivybridge, Haswell and Valleyview - DDB distribution based on resolution - Limited range DP display support nouveau: - CEC over DP AUX support - Initial HDMI 2.0 support virtio-gpu: - vmap support for PRIME objects tegra: - Initial Tegra194 support - DMA/IOMMU integration fixes msm: - a6xx perf improvements + clock prefix - GPU preemption optimisations - a6xx devfreq support - cursor support rockchip: - PX30 support - rgb output interface support mediatek: - HDMI output support on mt2701 and mt7623 rcar-du: - Interlaced modes on Gen3 - LVDS on R8A77980 - D3 and E3 SoC support hisilicon: - misc fixes mxsfb: - runtime pm support sun4i: - R40 TCON support - Allwinner A64 support - R40 HDMI support omapdrm: - Driver rework changing display pipeline ordering to use common code - DMM memory barrier and irq fixes - Errata workarounds exynos: - out-bridge support for LVDS bridge driver - Samsung 16x16 tiled format support - Plane alpha and pixel blend mode support tilcdc: - suspend/resume update mali-dp: - misc updates" * tag 'drm-next-2018-10-24' of git://anongit.freedesktop.org/drm/drm: (1382 commits) firmware/dmc/icl: Add missing MODULE_FIRMWARE() for Icelake. drm/i915/icl: Fix signal_levels drm/i915/icl: Fix DDI/TC port clk_off bits drm/i915/icl: create function to identify combophy port drm/i915/gen9+: Fix initial readout for Y tiled framebuffers drm/i915: Large page offsets for pread/pwrite drm/i915/selftests: Disable shrinker across mmap-exhaustion drm/i915/dp: Link train Fallback on eDP only if fallback link BW can fit panel's native mode drm/i915: Fix intel_dp_mst_best_encoder() drm/i915: Skip vcpi allocation for MSTB ports that are gone drm/i915: Don't unset intel_connector->mst_port drm/i915: Only reset seqno if actually idle drm/i915: Use the correct crtc when sanitizing plane mapping drm/i915: Restore vblank interrupts earlier drm/i915: Check fb stride against plane max stride drm/amdgpu/vcn:Fix uninitialized symbol error drm: panel-orientation-quirks: Add quirk for Acer One 10 (S1003) drm/amd/amdgpu: Fix debugfs error handling drm/amdgpu: Update gc_9_0 golden settings. drm/amd/powerplay: update PPtable with DC BTC and Tvr SocLimit fields ...
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| @@ -665,6 +665,8 @@ struct drm_amdgpu_cs_chunk_data { · 664 unmodified lines | |||
| 665 | #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM 0x10 | 665 | #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM 0x10 |
| 666 | /* Subquery id: Query GFX RLC SRLS firmware version */ | 666 | /* Subquery id: Query GFX RLC SRLS firmware version */ |
| 667 | #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM 0x11 | 667 | #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM 0x11 |
| 668 | /* Subquery id: Query DMCU firmware version */ | ||
| 669 | #define AMDGPU_INFO_FW_DMCU 0x12 | ||
| 668 | /* number of bytes moved for TTM migration */ | 670 | /* number of bytes moved for TTM migration */ |
| 669 | #define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f | 671 | #define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f |
| 670 | /* the used VRAM size */ | 672 | /* the used VRAM size */ |
| @@ -30,11 +30,50 @@ · 29 unmodified lines | |||
| 30 | extern "C" { | 30 | extern "C" { |
| 31 | #endif | 31 | #endif |
| 32 | 32 | ||
| 33 | /** | ||
| 34 | * DOC: overview | ||
| 35 | * | ||
| 36 | * In the DRM subsystem, framebuffer pixel formats are described using the | ||
| 37 | * fourcc codes defined in `include/uapi/drm/drm_fourcc.h`. In addition to the | ||
| 38 | * fourcc code, a Format Modifier may optionally be provided, in order to | ||
| 39 | * further describe the buffer's format - for example tiling or compression. | ||
| 40 | * | ||
| 41 | * Format Modifiers | ||
| 42 | * ---------------- | ||
| 43 | * | ||
| 44 | * Format modifiers are used in conjunction with a fourcc code, forming a | ||
| 45 | * unique fourcc:modifier pair. This format:modifier pair must fully define the | ||
| 46 | * format and data layout of the buffer, and should be the only way to describe | ||
| 47 | * that particular buffer. | ||
| 48 | * | ||
| 49 | * Having multiple fourcc:modifier pairs which describe the same layout should | ||
| 50 | * be avoided, as such aliases run the risk of different drivers exposing | ||
| 51 | * different names for the same data format, forcing userspace to understand | ||
| 52 | * that they are aliases. | ||
| 53 | * | ||
| 54 | * Format modifiers may change any property of the buffer, including the number | ||
| 55 | * of planes and/or the required allocation size. Format modifiers are | ||
| 56 | * vendor-namespaced, and as such the relationship between a fourcc code and a | ||
| 57 | * modifier is specific to the modifer being used. For example, some modifiers | ||
| 58 | * may preserve meaning - such as number of planes - from the fourcc code, | ||
| 59 | * whereas others may not. | ||
| 60 | * | ||
| 61 | * Vendors should document their modifier usage in as much detail as | ||
| 62 | * possible, to ensure maximum compatibility across devices, drivers and | ||
| 63 | * applications. | ||
| 64 | * | ||
| 65 | * The authoritative list of format modifier codes is found in | ||
| 66 | * `include/uapi/drm/drm_fourcc.h` | ||
| 67 | */ | ||
| 68 | |||
| 33 | #define fourcc_code(a, b, c, d) ((__u32)(a) | ((__u32)(b) << 8) | \ | 69 | #define fourcc_code(a, b, c, d) ((__u32)(a) | ((__u32)(b) << 8) | \ |
| 34 | ((__u32)(c) << 16) | ((__u32)(d) << 24)) | 70 | ((__u32)(c) << 16) | ((__u32)(d) << 24)) |
| 35 | 71 | ||
| 36 | #define DRM_FORMAT_BIG_ENDIAN (1<<31) /* format is big endian instead of little endian */ | 72 | #define DRM_FORMAT_BIG_ENDIAN (1<<31) /* format is big endian instead of little endian */ |
| 37 | 73 | ||
| 74 | /* Reserve 0 for the invalid format specifier */ | ||
| 75 | #define DRM_FORMAT_INVALID 0 | ||
| 76 | |||
| 38 | /* color index */ | 77 | /* color index */ |
| 39 | #define DRM_FORMAT_C8 fourcc_code('C', '8', ' ', ' ') /* [7:0] C */ | 78 | #define DRM_FORMAT_C8 fourcc_code('C', '8', ' ', ' ') /* [7:0] C */ |
| 40 | 79 | ||
| @@ -299,6 +338,15 @@ extern "C" { · 258 unmodified lines | |||
| 299 | */ | 338 | */ |
| 300 | #define DRM_FORMAT_MOD_SAMSUNG_64_32_TILE fourcc_mod_code(SAMSUNG, 1) | 339 | #define DRM_FORMAT_MOD_SAMSUNG_64_32_TILE fourcc_mod_code(SAMSUNG, 1) |
| 301 | 340 | ||
| 341 | /* | ||
| 342 | * Tiled, 16 (pixels) x 16 (lines) - sized macroblocks | ||
| 343 | * | ||
| 344 | * This is a simple tiled layout using tiles of 16x16 pixels in a row-major | ||
| 345 | * layout. For YCbCr formats Cb/Cr components are taken in such a way that | ||
| 346 | * they correspond to their 16x16 luma block. | ||
| 347 | */ | ||
| 348 | #define DRM_FORMAT_MOD_SAMSUNG_16_16_TILE fourcc_mod_code(SAMSUNG, 2) | ||
| 349 | |||
| 302 | /* | 350 | /* |
| 303 | * Qualcomm Compressed Format | 351 | * Qualcomm Compressed Format |
| 304 | * | 352 | * |
| @@ -186,8 +186,9 @@ extern "C" { · 185 unmodified lines | |||
| 186 | /* | 186 | /* |
| 187 | * DRM_MODE_REFLECT_<axis> | 187 | * DRM_MODE_REFLECT_<axis> |
| 188 | * | 188 | * |
| 189 | * Signals that the contents of a drm plane is reflected in the <axis> axis, | 189 | * Signals that the contents of a drm plane is reflected along the <axis> axis, |
| 190 | * in the same way as mirroring. | 190 | * in the same way as mirroring. |
| 191 | * See kerneldoc chapter "Plane Composition Properties" for more details. | ||
| 191 | * | 192 | * |
| 192 | * This define is provided as a convenience, looking up the property id | 193 | * This define is provided as a convenience, looking up the property id |
| 193 | * using the name->prop id lookup is the preferred method. | 194 | * using the name->prop id lookup is the preferred method. |
| @@ -529,6 +529,28 @@ typedef struct drm_i915_irq_wait { · 528 unmodified lines | |||
| 529 | */ | 529 | */ |
| 530 | #define I915_PARAM_CS_TIMESTAMP_FREQUENCY 51 | 530 | #define I915_PARAM_CS_TIMESTAMP_FREQUENCY 51 |
| 531 | 531 | ||
| 532 | /* | ||
| 533 | * Once upon a time we supposed that writes through the GGTT would be | ||
| 534 | * immediately in physical memory (once flushed out of the CPU path). However, | ||
| 535 | * on a few different processors and chipsets, this is not necessarily the case | ||
| 536 | * as the writes appear to be buffered internally. Thus a read of the backing | ||
| 537 | * storage (physical memory) via a different path (with different physical tags | ||
| 538 | * to the indirect write via the GGTT) will see stale values from before | ||
| 539 | * the GGTT write. Inside the kernel, we can for the most part keep track of | ||
| 540 | * the different read/write domains in use (e.g. set-domain), but the assumption | ||
| 541 | * of coherency is baked into the ABI, hence reporting its true state in this | ||
| 542 | * parameter. | ||
| 543 | * | ||
| 544 | * Reports true when writes via mmap_gtt are immediately visible following an | ||
| 545 | * lfence to flush the WCB. | ||
| 546 | * | ||
| 547 | * Reports false when writes via mmap_gtt are indeterminately delayed in an in | ||
| 548 | * internal buffer and are _not_ immediately visible to third parties accessing | ||
| 549 | * directly via mmap_cpu/mmap_wc. Use of mmap_gtt as part of an IPC | ||
| 550 | * communications channel when reporting false is strongly disadvised. | ||
| 551 | */ | ||
| 552 | #define I915_PARAM_MMAP_GTT_COHERENT 52 | ||
| 553 | |||
| 532 | typedef struct drm_i915_getparam { | 554 | typedef struct drm_i915_getparam { |
| 533 | __s32 param; | 555 | __s32 param; |
| 534 | /* | 556 | /* |
| @@ -82,6 +82,14 @@ struct kfd_ioctl_set_cu_mask_args { · 81 unmodified lines | |||
| 82 | __u64 cu_mask_ptr; /* to KFD */ | 82 | __u64 cu_mask_ptr; /* to KFD */ |
| 83 | }; | 83 | }; |
| 84 | 84 | ||
| 85 | struct kfd_ioctl_get_queue_wave_state_args { | ||
| 86 | uint64_t ctl_stack_address; /* to KFD */ | ||
| 87 | uint32_t ctl_stack_used_size; /* from KFD */ | ||
| 88 | uint32_t save_area_used_size; /* from KFD */ | ||
| 89 | uint32_t queue_id; /* to KFD */ | ||
| 90 | uint32_t pad; | ||
| 91 | }; | ||
| 92 | |||
| 85 | /* For kfd_ioctl_set_memory_policy_args.default_policy and alternate_policy */ | 93 | /* For kfd_ioctl_set_memory_policy_args.default_policy and alternate_policy */ |
| 86 | #define KFD_IOC_CACHE_POLICY_COHERENT 0 | 94 | #define KFD_IOC_CACHE_POLICY_COHERENT 0 |
| 87 | #define KFD_IOC_CACHE_POLICY_NONCOHERENT 1 | 95 | #define KFD_IOC_CACHE_POLICY_NONCOHERENT 1 |
| @@ -475,7 +483,10 @@ struct kfd_ioctl_unmap_memory_from_gpu_args { · 387 unmodified lines | |||
| 475 | #define AMDKFD_IOC_SET_CU_MASK \ | 483 | #define AMDKFD_IOC_SET_CU_MASK \ |
| 476 | AMDKFD_IOW(0x1A, struct kfd_ioctl_set_cu_mask_args) | 484 | AMDKFD_IOW(0x1A, struct kfd_ioctl_set_cu_mask_args) |
| 477 | 485 | ||
| 486 | #define AMDKFD_IOC_GET_QUEUE_WAVE_STATE \ | ||
| 487 | AMDKFD_IOWR(0x1B, struct kfd_ioctl_get_queue_wave_state_args) | ||
| 488 | |||
| 478 | #define AMDKFD_COMMAND_START 0x01 | 489 | #define AMDKFD_COMMAND_START 0x01 |
| 479 | #define AMDKFD_COMMAND_END 0x1B | 490 | #define AMDKFD_COMMAND_END 0x1C |
| 480 | 491 | ||
| 481 | #endif | 492 | #endif |
| @@ -0,0 +1,33 @@ | |||
| 1 | /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ | ||
| 2 | #ifndef _UAPI_LINUX_UDMABUF_H | ||
| 3 | #define _UAPI_LINUX_UDMABUF_H | ||
| 4 | |||
| 5 | #include <linux/types.h> | ||
| 6 | #include <linux/ioctl.h> | ||
| 7 | |||
| 8 | #define UDMABUF_FLAGS_CLOEXEC 0x01 | ||
| 9 | |||
| 10 | struct udmabuf_create { | ||
| 11 | __u32 memfd; | ||
| 12 | __u32 flags; | ||
| 13 | __u64 offset; | ||
| 14 | __u64 size; | ||
| 15 | }; | ||
| 16 | |||
| 17 | struct udmabuf_create_item { | ||
| 18 | __u32 memfd; | ||
| 19 | __u32 __pad; | ||
| 20 | __u64 offset; | ||
| 21 | __u64 size; | ||
| 22 | }; | ||
| 23 | |||
| 24 | struct udmabuf_create_list { | ||
| 25 | __u32 flags; | ||
| 26 | __u32 count; | ||
| 27 | struct udmabuf_create_item list[]; | ||
| 28 | }; | ||
| 29 | |||
| 30 | #define UDMABUF_CREATE _IOW('u', 0x42, struct udmabuf_create) | ||
| 31 | #define UDMABUF_CREATE_LIST _IOW('u', 0x43, struct udmabuf_create_list) | ||
| 32 | |||
| 33 | #endif /* _UAPI_LINUX_UDMABUF_H */ | ||