History

Merge tag 'pinctrl-v7.2-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin control updates from Linus Walleij: "Core changes: - Add new generic callbacks to populate per-pin pin controllers creating groups and functions from the device tree building out pinctrl_generic_to_map() and move the Spacemit driver over to use this - Generic board-level pin control driver using the mux framework New pin controller drivers: - Amlogic (meson) A9 SoC - Aspeed AST2700 SoC0 and SoC1 - nVidia Tegra264 and Tegra238 - Qualcomm Nord TLMM, Shikra TLMM, SM6350 LPASS LPI, and IPQ9650 TLMM - Renesas RZ/G3L SoC - UltraRISC DP1000 Improvements: - Handle pull up/pull down properly in the Renesas RZG2L driver - Fix up nVidia Tegra 234 DT bindings - Fix up pin definitions in the Qualcomm Eliza driver - Qualcomm PM8010 GPIO support in the PM8010 - Qualcomm SM6115 EGPIO support in the SM6115 - Switch Qualcomm LPASS LPI drivers to use runtime PM for power management - Clean up the Qualcomm Kconfig business a bit to include the necessary drivers for each subarch - Fix output glitch in the Amlogic (meson) A4 pin controller - Move the Airoha driver from the Mediatek directory to its own directory. It is too different from other Mediatek hardware - A slew of fixes to the Airoha AN7581 and AN7583 drivers" * tag 'pinctrl-v7.2-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (151 commits) pinctrl: Export pinctrl_get_group_selector() pinctrl: Match DT helper types pinctrl: qcom: Register functions before enabling pinctrl pinctrl: meson: amlogic-a4: use nolock get range pinctrl: ultrarisc: Add UltraRISC DP1000 pinctrl driver dt-bindings: pinctrl: Add UltraRISC DP1000 pinctrl controller pinctrl: qcom: Remove unused macro definitions pinctrl: tegra: PINCTRL_TEGRA264 should depend on ARCH_TEGRA pinctrl: tegra: PINCTRL_TEGRA238 should depend on ARCH_TEGRA pinctrl: tegra238: add missing AON pin groups dt-bindings: pinctrl: tegra238: add missing AON pin groups pinctrl: airoha: an7583: remove undefined groups from pcm_spi pin function pinctrl: airoha: an7583: fix phy1_led1 pin function pinctrl: airoha: an7583: add missed gpio22 pin group pinctrl: airoha: an7583: fix gpio21 pin group pinctrl: airoha: fix pwm pin function for an7581 and an7583 pinctrl: airoha: an7583: fix incorrect led mapping in phy4_led1 pin function pinctrl: airoha: an7581: fix incorrect led mapping in phy4_led1 pin function pinctrl: airoha: an7583: fix misprint in gpio19 pinconf pinctrl: airoha: an7581: fix misprint in gpio19 pinconf ...

Linus Torvalds committed 4 months ago

Commit 53c7db52 parents 7c67425 8b2c4f8180 files · +16413 −1096Browse files

Unified · Split

180 files
  1. Documentation/devicetree/bindings/pinctrl/allwinner,sun55i-a523-pinctrl.yaml +4 −4
  2. Documentation/devicetree/bindings/pinctrl/amlogic,pinctrl-a4.yaml +1 −0
  3. Documentation/devicetree/bindings/pinctrl/aspeed,ast2700-soc0-pinctrl.yaml +188 −0
  4. Documentation/devicetree/bindings/pinctrl/aspeed,ast2700-soc1-pinctrl.yaml +760 −0
  5. Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml +1 −0
  6. Documentation/devicetree/bindings/pinctrl/mediatek,mt6795-pinctrl.yaml +8 −0
  7. Documentation/devicetree/bindings/pinctrl/mediatek,mt8188-pinctrl.yaml +5 −0
  8. Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux-aon.yaml +5 −1
  9. Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux.yaml +5 −1
  10. Documentation/devicetree/bindings/pinctrl/nvidia,tegra238-pinmux-aon.yaml +102 −0
  11. Documentation/devicetree/bindings/pinctrl/nvidia,tegra238-pinmux-common.yaml +73 −0
  12. Documentation/devicetree/bindings/pinctrl/nvidia,tegra238-pinmux.yaml +219 −0
  13. Documentation/devicetree/bindings/pinctrl/nvidia,tegra264-pinmux-aon.yaml +80 −0
  14. Documentation/devicetree/bindings/pinctrl/nvidia,tegra264-pinmux-common.yaml +84 −0
  15. Documentation/devicetree/bindings/pinctrl/nvidia,tegra264-pinmux-main.yaml +167 −0
  16. Documentation/devicetree/bindings/pinctrl/nvidia,tegra264-pinmux-uphy.yaml +78 −0
  17. Documentation/devicetree/bindings/pinctrl/pinctrl-multiplexer.yaml +57 −0
  18. Documentation/devicetree/bindings/pinctrl/pinctrl.yaml +1 −1
  19. Documentation/devicetree/bindings/pinctrl/qcom,eliza-tlmm.yaml +16 −10
  20. Documentation/devicetree/bindings/pinctrl/qcom,ipq4019-pinctrl.yaml +0 −5
  21. Documentation/devicetree/bindings/pinctrl/qcom,ipq9650-tlmm.yaml +118 −0
  22. Documentation/devicetree/bindings/pinctrl/qcom,nord-tlmm.yaml +141 −0
  23. Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml +3 −0
  24. Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.yaml +0 −5
  25. Documentation/devicetree/bindings/pinctrl/qcom,shikra-tlmm.yaml +123 −0
  26. Documentation/devicetree/bindings/pinctrl/qcom,sm6350-lpass-lpi-pinctrl.yaml +124 −0
  27. Documentation/devicetree/bindings/pinctrl/qcom,tlmm-common.yaml +6 −0
  28. Documentation/devicetree/bindings/pinctrl/realtek,rtd1625-pinctrl.yaml +1 −1
  29. Documentation/devicetree/bindings/pinctrl/ultrarisc,dp1000-pinctrl.yaml +130 −0
  30. MAINTAINERS +9 −1
  31. drivers/mux/core.c +27 −16
  32. drivers/pinctrl/Kconfig +13 −0
  33. drivers/pinctrl/Makefile +7 −4
  34. drivers/pinctrl/actions/pinctrl-owl.h +1 −1
  35. drivers/pinctrl/airoha/Kconfig +20 −0
  36. drivers/pinctrl/airoha/Makefile +3 −0
  37. drivers/pinctrl/airoha/pinctrl-airoha.c +99 −25
  38. drivers/pinctrl/aspeed/Kconfig +23 −0
  39. drivers/pinctrl/aspeed/Makefile +2 −0
  40. drivers/pinctrl/aspeed/pinctrl-aspeed-g7-soc0.c +749 −0
  41. drivers/pinctrl/aspeed/pinctrl-aspeed-g7-soc1.c +1756 −0
  42. drivers/pinctrl/bcm/pinctrl-bcm4908.c +1 −1
  43. drivers/pinctrl/bcm/pinctrl-bcm63xx.h +1 −1
  44. drivers/pinctrl/bcm/pinctrl-iproc-gpio.c +1 −1
  45. drivers/pinctrl/bcm/pinctrl-ns.c +1 −1
  46. drivers/pinctrl/cirrus/pinctrl-cs42l43.c +4 −6
  47. drivers/pinctrl/core.c +36 −5
  48. drivers/pinctrl/intel/pinctrl-broxton.c +2 −2
  49. drivers/pinctrl/intel/pinctrl-denverton.c +1 −1
  50. drivers/pinctrl/intel/pinctrl-intel.c +2 −1
  51. drivers/pinctrl/mediatek/Kconfig +1 −16
  52. drivers/pinctrl/mediatek/Makefile +0 −1
  53. drivers/pinctrl/mediatek/mtk-eint.c +3 −3
  54. drivers/pinctrl/mediatek/pinctrl-moore.c +2 −1
  55. drivers/pinctrl/mediatek/pinctrl-mt8167.c +1 −1
  56. drivers/pinctrl/mediatek/pinctrl-mt8516.c +1 −1
  57. drivers/pinctrl/mediatek/pinctrl-mtk-common.c +10 −3
  58. drivers/pinctrl/mediatek/pinctrl-mtk-mt8365.h +1 −1
  59. drivers/pinctrl/mediatek/pinctrl-paris.c +5 −3
  60. drivers/pinctrl/meson/pinctrl-amlogic-a4.c +68 −18
  61. drivers/pinctrl/nuvoton/pinctrl-ma35.c +2 −1
  62. drivers/pinctrl/nuvoton/pinctrl-ma35d1.c +261 −209
  63. drivers/pinctrl/nxp/pinctrl-s32cc.c +30 −34
  64. drivers/pinctrl/pinconf-generic.c +2 −5
  65. drivers/pinctrl/pinconf.c +7 −2
  66. drivers/pinctrl/pinconf.h +31 −1
  67. drivers/pinctrl/pinctrl-aw9523.c +1 −1
  68. drivers/pinctrl/pinctrl-cy8c95x0.c +3 −3
  69. drivers/pinctrl/pinctrl-equilibrium.c +2 −1
  70. drivers/pinctrl/pinctrl-generic-mux.c +184 −0
  71. drivers/pinctrl/pinctrl-generic.c +152 −59
  72. drivers/pinctrl/pinctrl-ingenic.c +2 −1
  73. drivers/pinctrl/pinctrl-max77620.c +3 −3
  74. drivers/pinctrl/pinctrl-mcp23s08_i2c.c +3 −3
  75. drivers/pinctrl/pinctrl-rockchip.c +1 −1
  76. drivers/pinctrl/pinctrl-single.c +2 −1
  77. drivers/pinctrl/pinctrl-sx150x.c +10 −10
  78. drivers/pinctrl/pinctrl-tps6594.c +2 −2
  79. drivers/pinctrl/pinmux.c +5 −0
  80. drivers/pinctrl/qcom/Kconfig +23 −12
  81. drivers/pinctrl/qcom/Kconfig.msm +131 −42
  82. drivers/pinctrl/qcom/Makefile +4 −0
  83. drivers/pinctrl/qcom/pinctrl-apq8064.c +1 −1
  84. drivers/pinctrl/qcom/pinctrl-apq8084.c +1 −1
  85. drivers/pinctrl/qcom/pinctrl-eliza.c +133 −55
  86. drivers/pinctrl/qcom/pinctrl-glymur.c +1 −1
  87. drivers/pinctrl/qcom/pinctrl-hawi.c +1 −1
  88. drivers/pinctrl/qcom/pinctrl-ipq4019.c +1 −1
  89. drivers/pinctrl/qcom/pinctrl-ipq6018.c +1 −1
  90. drivers/pinctrl/qcom/pinctrl-ipq8064.c +1 −1
  91. drivers/pinctrl/qcom/pinctrl-ipq8074.c +1 −1
  92. drivers/pinctrl/qcom/pinctrl-ipq9650.c +762 −0
  93. drivers/pinctrl/qcom/pinctrl-kaanapali.c +1 −1
  94. drivers/pinctrl/qcom/pinctrl-lpass-lpi.c +88 −48
  95. drivers/pinctrl/qcom/pinctrl-lpass-lpi.h +20 −0
  96. drivers/pinctrl/qcom/pinctrl-mdm9607.c +1 −1
  97. drivers/pinctrl/qcom/pinctrl-mdm9615.c +1 −1
  98. drivers/pinctrl/qcom/pinctrl-milos-lpass-lpi.c +7 −0
  99. drivers/pinctrl/qcom/pinctrl-milos.c +1 −1
  100. drivers/pinctrl/qcom/pinctrl-msm.c +12 −9
  101. drivers/pinctrl/qcom/pinctrl-msm8226.c +1 −1
  102. drivers/pinctrl/qcom/pinctrl-msm8660.c +1 −1
  103. drivers/pinctrl/qcom/pinctrl-msm8916.c +1 −1
  104. drivers/pinctrl/qcom/pinctrl-msm8953.c +1 −1
  105. drivers/pinctrl/qcom/pinctrl-msm8960.c +1 −1
  106. drivers/pinctrl/qcom/pinctrl-msm8976.c +1 −1
  107. drivers/pinctrl/qcom/pinctrl-msm8994.c +1 −1
  108. drivers/pinctrl/qcom/pinctrl-msm8996.c +1 −1
  109. drivers/pinctrl/qcom/pinctrl-msm8998.c +1 −1
  110. drivers/pinctrl/qcom/pinctrl-msm8x74.c +1 −1
  111. drivers/pinctrl/qcom/pinctrl-nord.c +1770 −0
  112. drivers/pinctrl/qcom/pinctrl-qcm2290.c +1 −24
  113. drivers/pinctrl/qcom/pinctrl-qcs404.c +1 −1
  114. drivers/pinctrl/qcom/pinctrl-qcs615.c +1 −1
  115. drivers/pinctrl/qcom/pinctrl-qcs8300.c +0 −6
  116. drivers/pinctrl/qcom/pinctrl-qdu1000.c +0 −30
  117. drivers/pinctrl/qcom/pinctrl-sa8775p.c +0 −6
  118. drivers/pinctrl/qcom/pinctrl-sc7180.c +1 −1
  119. drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c +13 −6
  120. drivers/pinctrl/qcom/pinctrl-sc7280.c +1 −1
  121. drivers/pinctrl/qcom/pinctrl-sc8280xp-lpass-lpi.c +11 −4
  122. drivers/pinctrl/qcom/pinctrl-sdm660-lpass-lpi.c +7 −0
  123. drivers/pinctrl/qcom/pinctrl-sdm660.c +1 −1
  124. drivers/pinctrl/qcom/pinctrl-sdm670-lpass-lpi.c +7 −0
  125. drivers/pinctrl/qcom/pinctrl-sdm845.c +1 −1
  126. drivers/pinctrl/qcom/pinctrl-sdx55.c +1 −1
  127. drivers/pinctrl/qcom/pinctrl-sdx65.c +1 −1
  128. drivers/pinctrl/qcom/pinctrl-shikra.c +1253 −0
  129. drivers/pinctrl/qcom/pinctrl-sm4250-lpass-lpi.c +7 −0
  130. drivers/pinctrl/qcom/pinctrl-sm4450.c +0 −7
  131. drivers/pinctrl/qcom/pinctrl-sm6115-lpass-lpi.c +7 −0
  132. drivers/pinctrl/qcom/pinctrl-sm6115.c +26 −16
  133. drivers/pinctrl/qcom/pinctrl-sm6125.c +1 −1
  134. drivers/pinctrl/qcom/pinctrl-sm6350-lpass-lpi.c +156 −0
  135. drivers/pinctrl/qcom/pinctrl-sm6350.c +1 −1
  136. drivers/pinctrl/qcom/pinctrl-sm6375.c +1 −1
  137. drivers/pinctrl/qcom/pinctrl-sm8150.c +1 −1
  138. drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c +11 −4
  139. drivers/pinctrl/qcom/pinctrl-sm8250.c +1 −1
  140. drivers/pinctrl/qcom/pinctrl-sm8350.c +1 −1
  141. drivers/pinctrl/qcom/pinctrl-sm8450-lpass-lpi.c +11 −4
  142. drivers/pinctrl/qcom/pinctrl-sm8450.c +1 −1
  143. drivers/pinctrl/qcom/pinctrl-sm8550-lpass-lpi.c +11 −4
  144. drivers/pinctrl/qcom/pinctrl-sm8550.c +1 −1
  145. drivers/pinctrl/qcom/pinctrl-sm8650-lpass-lpi.c +11 −4
  146. drivers/pinctrl/qcom/pinctrl-sm8650.c +1 −1
  147. drivers/pinctrl/qcom/pinctrl-sm8750.c +1 −1
  148. drivers/pinctrl/qcom/pinctrl-spmi-gpio.c +1 −0
  149. drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c +5 −5
  150. drivers/pinctrl/qcom/pinctrl-x1e80100.c +1 −1
  151. drivers/pinctrl/qcom/tlmm-test.c +10 −11
  152. drivers/pinctrl/realtek/Kconfig +6 −6
  153. drivers/pinctrl/realtek/pinctrl-rtd.c +6 −6
  154. drivers/pinctrl/renesas/core.c +12 −12
  155. drivers/pinctrl/renesas/pinctrl-rzg2l.c +562 −26
  156. drivers/pinctrl/renesas/pinctrl-rzt2h.c +8 −5
  157. drivers/pinctrl/renesas/pinctrl-rzv2m.c +4 −3
  158. drivers/pinctrl/renesas/pinctrl.c +25 −0
  159. drivers/pinctrl/sophgo/pinctrl-cv18xx.c +12 −20
  160. drivers/pinctrl/spacemit/Kconfig +1 −3
  161. drivers/pinctrl/spacemit/pinctrl-k1.c +13 −169
  162. drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c +5 −8
  163. drivers/pinctrl/starfive/pinctrl-starfive-jh7110.h +2 −1
  164. drivers/pinctrl/sunxi/pinctrl-sun55i-a523-r.c +0 −1
  165. drivers/pinctrl/sunxi/pinctrl-sun55i-a523.c +0 −1
  166. drivers/pinctrl/sunxi/pinctrl-sunxi.c +1 −1
  167. drivers/pinctrl/tegra/Kconfig +34 −10
  168. drivers/pinctrl/tegra/Makefile +2 −0
  169. drivers/pinctrl/tegra/pinctrl-tegra.c +2 −0
  170. drivers/pinctrl/tegra/pinctrl-tegra238.c +2080 −0
  171. drivers/pinctrl/tegra/pinctrl-tegra264.c +2216 −0
  172. drivers/pinctrl/ultrarisc/Kconfig +20 −0
  173. drivers/pinctrl/ultrarisc/Makefile +4 −0
  174. drivers/pinctrl/ultrarisc/pinctrl-dp1000.c +168 −0
  175. drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c +517 −0
  176. drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.h +63 −0
  177. drivers/pinctrl/vt8500/Kconfig +7 −6
  178. include/dt-bindings/pinctrl/mediatek,mt6392-pinfunc.h +39 −0
  179. include/linux/mux/consumer.h +7 −1
  180. include/linux/pinctrl/pinmux.h +5 −0
Documentation/devicetree/bindings/pinctrl/allwinner,sun55i-a523-pinctrl.yaml+4−4
@@ -34,7 +34,7 @@ properties: · 33 unmodified lines
34 34
35 interrupts:35 interrupts:
36 minItems: 236 minItems: 2
37 maxItems: 1037 maxItems: 11
38 description:38 description:
39 One interrupt per external interrupt bank supported on the39 One interrupt per external interrupt bank supported on the
40 controller, sorted by bank number ascending order.40 controller, sorted by bank number ascending order.
@@ -61,7 +61,7 @@ properties: · 20 unmodified lines
61 bank found in the controller61 bank found in the controller
62 $ref: /schemas/types.yaml#/definitions/uint32-array62 $ref: /schemas/types.yaml#/definitions/uint32-array
63 minItems: 263 minItems: 2
64 maxItems: 1064 maxItems: 11
65 65
66patternProperties:66patternProperties:
67 # It's pretty scary, but the basic idea is that:67 # It's pretty scary, but the basic idea is that:
@@ -130,8 +130,8 @@ allOf: · 62 unmodified lines
130 then:130 then:
131 properties:131 properties:
132 interrupts:132 interrupts:
133 minItems: 10133 minItems: 11
134 maxItems: 10134 maxItems: 11
135 135
136 - if:136 - if:
137 properties:137 properties:
Documentation/devicetree/bindings/pinctrl/amlogic,pinctrl-a4.yaml+1−0
@@ -17,6 +17,7 @@ properties: · 16 unmodified lines
17 oneOf:17 oneOf:
18 - enum:18 - enum:
19 - amlogic,pinctrl-a419 - amlogic,pinctrl-a4
20 - amlogic,pinctrl-a9
20 - amlogic,pinctrl-s621 - amlogic,pinctrl-s6
21 - amlogic,pinctrl-s722 - amlogic,pinctrl-s7
22 - items:23 - items:
Documentation/devicetree/bindings/pinctrl/aspeed,ast2700-soc0-pinctrl.yaml+188−0
@@ -0,0 +1,188 @@
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/aspeed,ast2700-soc0-pinctrl.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: ASPEED AST2700 SoC0 Pin Controller
8
9maintainers:
10 - Billy Tsai <billy_tsai@aspeedtech.com>
11
12description: >
13 The AST2700 features a dual-SoC architecture with two interconnected SoCs,
14 each having its own System Control Unit (SCU) for independent pin control.
15 This pin controller manages the pin multiplexing for SoC0.
16
17 The SoC0 pin controller manages pin functions including eMMC, VGA DDC,
18 dual USB3/USB2 ports (A and B), JTAG, and PCIe root complex interfaces.
19
20properties:
21 compatible:
22 const: aspeed,ast2700-soc0-pinctrl
23
24 reg:
25 maxItems: 1
26
27patternProperties:
28 '-state$':
29 description: |
30 Pin control state.
31
32 If 'function' is present, the node describes a pinmux state and must
33 specify 'groups'.
34
35 For pin configuration, exactly one of 'groups' or 'pins' must be
36 specified in each state node. Group-level configuration applies to all
37 pins in the group. Pin-level configuration may be supplied in a
38 separate state node for individual pins; when both group-level and
39 pin-level configuration apply to the same pin, the pin-level
40 configuration takes precedence.
41
42 type: object
43 allOf:
44 - $ref: pinmux-node.yaml#
45 - $ref: pincfg-node.yaml#
46 - if:
47 required:
48 - function
49 then:
50 required:
51 - groups
52 - oneOf:
53 - required:
54 - groups
55 - required:
56 - pins
57
58 additionalProperties: false
59
60 properties:
61 function:
62 enum:
63 - EMMC
64 - JTAGDDR
65 - JTAGM0
66 - JTAGPCIEA
67 - JTAGPCIEB
68 - JTAGPSP
69 - JTAGSSP
70 - JTAGTSP
71 - JTAGUSB3A
72 - JTAGUSB3B
73 - PCIERC0PERST
74 - PCIERC1PERST
75 - TSPRSTN
76 - UFSCLKI
77 - USB2AD0
78 - USB2AD1
79 - USB2AH
80 - USB2AHP
81 - USB2AHPD0
82 - USB2AXH
83 - USB2AXH2B
84 - USB2AXHD1
85 - USB2AXHP
86 - USB2AXHP2B
87 - USB2AXHPD1
88 - USB2BD0
89 - USB2BD1
90 - USB2BH
91 - USB2BHP
92 - USB2BHPD0
93 - USB2BXH
94 - USB2BXH2A
95 - USB2BXHD1
96 - USB2BXHP
97 - USB2BXHP2A
98 - USB2BXHPD1
99 - USB3AXH
100 - USB3AXH2B
101 - USB3AXHD
102 - USB3AXHP
103 - USB3AXHP2B
104 - USB3AXHPD
105 - USB3BXH
106 - USB3BXH2A
107 - USB3BXHD
108 - USB3BXHP
109 - USB3BXHP2A
110 - USB3BXHPD
111 - VB
112 - VGADDC
113
114 groups:
115 enum:
116 - EMMCCDN
117 - EMMCG1
118 - EMMCG4
119 - EMMCG8
120 - EMMCWPN
121 - JTAG0
122 - PCIERC0PERST
123 - PCIERC1PERST
124 - TSPRSTN
125 - UFSCLKI
126 - USB2A
127 - USB2AAP
128 - USB2ABP
129 - USB2ADAP
130 - USB2AH
131 - USB2AHAP
132 - USB2B
133 - USB2BAP
134 - USB2BBP
135 - USB2BDBP
136 - USB2BH
137 - USB2BHBP
138 - USB3A
139 - USB3AAP
140 - USB3ABP
141 - USB3B
142 - USB3BAP
143 - USB3BBP
144 - VB0
145 - VB1
146 - VGADDC
147
148 pins:
149 enum:
150 - AB13
151 - AB14
152 - AC13
153 - AC14
154 - AD13
155 - AD14
156 - AE13
157 - AE14
158 - AE15
159 - AF13
160 - AF14
161 - AF15
162
163 drive-strength:
164 enum: [3, 6, 8, 11, 16, 18, 20, 23, 30, 32, 33, 35, 37, 38, 39, 41]
165
166 bias-disable: true
167 bias-pull-up: true
168 bias-pull-down: true
169
170required:
171 - compatible
172 - reg
173
174allOf:
175 - $ref: pinctrl.yaml#
176
177additionalProperties: false
178
179examples:
180 - |
181 pinctrl@400 {
182 compatible = "aspeed,ast2700-soc0-pinctrl";
183 reg = <0x400 0x318>;
184 emmc-state {
185 function = "EMMC";
186 groups = "EMMCG1";
187 };
188 };
Documentation/devicetree/bindings/pinctrl/aspeed,ast2700-soc1-pinctrl.yaml+760−0
@@ -0,0 +1,760 @@
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/aspeed,ast2700-soc1-pinctrl.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: ASPEED AST2700 SoC1 Pin Controller
8
9maintainers:
10 - Billy Tsai <billy_tsai@aspeedtech.com>
11
12description:
13 The AST2700 features a dual-SoC architecture with two interconnected SoCs,
14 each having its own System Control Unit (SCU) for independent pin control.
15 This pin controller manages the pin multiplexing for SoC1.
16
17 The SoC1 pin controller manages pin functions including eSPI, LPC and I2C,
18 among others.
19
20properties:
21 compatible:
22 const: aspeed,ast2700-soc1-pinctrl
23 reg:
24 maxItems: 1
25
26patternProperties:
27 '-state$':
28 description: |
29 Pin control state.
30
31 If `function` is present, the node describes a pinmux state and must
32 specify `groups`.
33
34 For pin configuration, exactly one of `groups` or `pins` must be
35 specified in each state node. Group-level configuration applies to all
36 pins in the group. Pin-level configuration may be supplied in a
37 separate state node for individual pins; when both group-level and
38 pin-level configuration apply to the same pin, the pin-level
39 configuration takes precedence.
40
41 type: object
42 allOf:
43 - $ref: pinmux-node.yaml#
44 - $ref: pincfg-node.yaml#
45 - if:
46 required:
47 - function
48 then:
49 required:
50 - groups
51 - oneOf:
52 - required:
53 - groups
54 - required:
55 - pins
56 additionalProperties: false
57
58 properties:
59 function:
60 enum:
61 - ADC0
62 - ADC1
63 - ADC10
64 - ADC11
65 - ADC12
66 - ADC13
67 - ADC14
68 - ADC15
69 - ADC2
70 - ADC3
71 - ADC4
72 - ADC5
73 - ADC6
74 - ADC7
75 - ADC8
76 - ADC9
77 - AUXPWRGOOD0
78 - AUXPWRGOOD1
79 - CANBUS
80 - ESPI0
81 - ESPI1
82 - FSI0
83 - FSI1
84 - FSI2
85 - FSI3
86 - FWQSPI
87 - FWSPIABR
88 - FWWPN
89 - HBLED
90 - I2C0
91 - I2C1
92 - I2C10
93 - I2C11
94 - I2C12
95 - I2C13
96 - I2C14
97 - I2C15
98 - I2C2
99 - I2C3
100 - I2C4
101 - I2C5
102 - I2C6
103 - I2C7
104 - I2C8
105 - I2C9
106 - I2CF0
107 - I2CF1
108 - I2CF2
109 - I3C0
110 - I3C1
111 - I3C10
112 - I3C11
113 - I3C12
114 - I3C13
115 - I3C14
116 - I3C15
117 - I3C2
118 - I3C3
119 - I3C4
120 - I3C5
121 - I3C6
122 - I3C7
123 - I3C8
124 - I3C9
125 - JTAGM1
126 - LPC0
127 - LPC1
128 - LTPI
129 - MACLINK0
130 - MACLINK1
131 - MACLINK2
132 - MDIO0
133 - MDIO1
134 - MDIO2
135 - NCTS0
136 - NCTS1
137 - NCTS5
138 - NCTS6
139 - NDCD0
140 - NDCD1
141 - NDCD5
142 - NDCD6
143 - NDSR0
144 - NDSR1
145 - NDSR5
146 - NDSR6
147 - NDTR0
148 - NDTR1
149 - NDTR5
150 - NDTR6
151 - NRI0
152 - NRI1
153 - NRI5
154 - NRI6
155 - NRTS0
156 - NRTS1
157 - NRTS5
158 - NRTS6
159 - OSCCLK
160 - PCIERC
161 - PWM0
162 - PWM1
163 - PWM10
164 - PWM11
165 - PWM12
166 - PWM13
167 - PWM14
168 - PWM15
169 - PWM2
170 - PWM3
171 - PWM4
172 - PWM5
173 - PWM6
174 - PWM7
175 - PWM8
176 - PWM9
177 - QSPI0
178 - QSPI1
179 - QSPI2
180 - RGMII0
181 - RGMII1
182 - RMII0
183 - RMII0RCLKO
184 - RMII1
185 - RMII1RCLKO
186 - SALT0
187 - SALT1
188 - SALT10
189 - SALT11
190 - SALT12
191 - SALT13
192 - SALT14
193 - SALT15
194 - SALT2
195 - SALT3
196 - SALT4
197 - SALT5
198 - SALT6
199 - SALT7
200 - SALT8
201 - SALT9
202 - SD
203 - SGMII
204 - SGPM0
205 - SGPM1
206 - SGPS
207 - SIOONCTRLN0
208 - SIOONCTRLN1
209 - SIOPBIN0
210 - SIOPBIN1
211 - SIOPBON0
212 - SIOPBON1
213 - SIOPWREQN0
214 - SIOPWREQN1
215 - SIOPWRGD1
216 - SIOS3N0
217 - SIOS3N1
218 - SIOS5N0
219 - SIOS5N1
220 - SIOSCIN0
221 - SIOSCIN1
222 - SMON0
223 - SMON1
224 - SPI0
225 - SPI0ABR
226 - SPI0CS1
227 - SPI0WPN
228 - SPI1
229 - SPI1ABR
230 - SPI1CS1
231 - SPI1WPN
232 - SPI2
233 - SPI2CS1
234 - TACH0
235 - TACH1
236 - TACH10
237 - TACH11
238 - TACH12
239 - TACH13
240 - TACH14
241 - TACH15
242 - TACH2
243 - TACH3
244 - TACH4
245 - TACH5
246 - TACH6
247 - TACH7
248 - TACH8
249 - TACH9
250 - THRU0
251 - THRU1
252 - THRU2
253 - THRU3
254 - UART0
255 - UART1
256 - UART10
257 - UART11
258 - UART2
259 - UART3
260 - UART5
261 - UART6
262 - UART7
263 - UART8
264 - UART9
265 - USB2C
266 - USB2D
267 - USBUART
268 - VGA
269 - VPI
270 - WDTRST0N
271 - WDTRST1N
272 - WDTRST2N
273 - WDTRST3N
274 - WDTRST4N
275 - WDTRST5N
276 - WDTRST6N
277 - WDTRST7N
278
279 groups:
280 enum:
281 - ADC0
282 - ADC1
283 - ADC10
284 - ADC11
285 - ADC12
286 - ADC13
287 - ADC14
288 - ADC15
289 - ADC2
290 - ADC3
291 - ADC4
292 - ADC5
293 - ADC6
294 - ADC7
295 - ADC8
296 - ADC9
297 - AUXPWRGOOD0
298 - AUXPWRGOOD1
299 - CANBUS
300 - DI2C0
301 - DI2C1
302 - DI2C10
303 - DI2C11
304 - DI2C12
305 - DI2C13
306 - DI2C14
307 - DI2C15
308 - DI2C2
309 - DI2C3
310 - DI2C8
311 - DI2C9
312 - DSGPM0
313 - ESPI0
314 - ESPI1
315 - FSI0
316 - FSI1
317 - FSI2
318 - FSI3
319 - FWQSPI
320 - FWSPIABR
321 - FWWPN
322 - HBLED
323 - HVI3C0
324 - HVI3C1
325 - HVI3C12
326 - HVI3C13
327 - HVI3C14
328 - HVI3C15
329 - HVI3C2
330 - HVI3C3
331 - I2C0
332 - I2C1
333 - I2C10
334 - I2C11
335 - I2C12
336 - I2C13
337 - I2C14
338 - I2C15
339 - I2C2
340 - I2C3
341 - I2C4
342 - I2C5
343 - I2C6
344 - I2C7
345 - I2C8
346 - I2C9
347 - I2CF0
348 - I2CF1
349 - I2CF2
350 - I3C10
351 - I3C11
352 - I3C4
353 - I3C5
354 - I3C6
355 - I3C7
356 - I3C8
357 - I3C9
358 - JTAGM1
359 - LPC0
360 - LPC1
361 - LTPI
362 - LTPI_PS_I2C0
363 - LTPI_PS_I2C1
364 - LTPI_PS_I2C2
365 - LTPI_PS_I2C3
366 - MACLINK0
367 - MACLINK1
368 - MACLINK2
369 - MDIO0
370 - MDIO1
371 - MDIO2
372 - NCTS0
373 - NCTS1
374 - NCTS5
375 - NCTS6
376 - NDCD0
377 - NDCD1
378 - NDCD5
379 - NDCD6
380 - NDSR0
381 - NDSR1
382 - NDSR5
383 - NDSR6
384 - NDTR0
385 - NDTR1
386 - NDTR5
387 - NDTR6
388 - NRI0
389 - NRI1
390 - NRI5
391 - NRI6
392 - NRTS0
393 - NRTS1
394 - NRTS5
395 - NRTS6
396 - OSCCLK
397 - PE2SGRSTN
398 - PWM0
399 - PWM1
400 - PWM10
401 - PWM11
402 - PWM12
403 - PWM13
404 - PWM14
405 - PWM15
406 - PWM2
407 - PWM3
408 - PWM4
409 - PWM5
410 - PWM6
411 - PWM7
412 - PWM8
413 - PWM9
414 - QSPI0
415 - QSPI1
416 - QSPI2
417 - RGMII0
418 - RGMII1
419 - RMII0
420 - RMII0RCLKO
421 - RMII1
422 - RMII1RCLKO
423 - SALT0
424 - SALT1
425 - SALT10
426 - SALT11
427 - SALT12
428 - SALT13
429 - SALT14
430 - SALT15
431 - SALT2
432 - SALT3
433 - SALT4
434 - SALT5
435 - SALT6
436 - SALT7
437 - SALT8
438 - SALT9
439 - SD
440 - SGMII
441 - SGPM0
442 - SGPM1
443 - SGPS
444 - SIOONCTRLN0
445 - SIOONCTRLN1
446 - SIOPBIN0
447 - SIOPBIN1
448 - SIOPBON0
449 - SIOPBON1
450 - SIOPWREQN0
451 - SIOPWREQN1
452 - SIOPWRGD1
453 - SIOS3N0
454 - SIOS3N1
455 - SIOS5N0
456 - SIOS5N1
457 - SIOSCIN0
458 - SIOSCIN1
459 - SMON0
460 - SMON1
461 - SPI0
462 - SPI0ABR
463 - SPI0CS1
464 - SPI0WPN
465 - SPI1
466 - SPI1ABR
467 - SPI1CS1
468 - SPI1WPN
469 - SPI2
470 - SPI2CS1
471 - TACH0
472 - TACH1
473 - TACH10
474 - TACH11
475 - TACH12
476 - TACH13
477 - TACH14
478 - TACH15
479 - TACH2
480 - TACH3
481 - TACH4
482 - TACH5
483 - TACH6
484 - TACH7
485 - TACH8
486 - TACH9
487 - THRU0
488 - THRU1
489 - THRU2
490 - THRU3
491 - UART0
492 - UART1
493 - UART10
494 - UART11
495 - UART2
496 - UART3
497 - UART5
498 - UART6
499 - UART7
500 - UART8
501 - UART9
502 - USB2CD
503 - USB2CH
504 - USB2CU
505 - USB2CUD
506 - USB2DD
507 - USB2DH
508 - USBUART
509 - VGA
510 - VPI
511 - WDTRST0N
512 - WDTRST1N
513 - WDTRST2N
514 - WDTRST3N
515 - WDTRST4N
516 - WDTRST5N
517 - WDTRST6N
518 - WDTRST7N
519
520 pins:
521 enum:
522 - A14
523 - A15
524 - A18
525 - A19
526 - A21
527 - A22
528 - A23
529 - A24
530 - A25
531 - A26
532 - A6
533 - A7
534 - A8
535 - AA12
536 - AA13
537 - AA14
538 - AA15
539 - AA16
540 - AA17
541 - AA18
542 - AA20
543 - AA21
544 - AA22
545 - AA23
546 - AA24
547 - AA25
548 - AA26
549 - AB15
550 - AB16
551 - AB17
552 - AB18
553 - AB19
554 - AB20
555 - AB21
556 - AB22
557 - AB23
558 - AB24
559 - AB25
560 - AB26
561 - AC15
562 - AC16
563 - AC17
564 - AC18
565 - AC19
566 - AC20
567 - AC22
568 - AC24
569 - AC25
570 - AC26
571 - AD15
572 - AD16
573 - AD17
574 - AD18
575 - AD19
576 - AD20
577 - AD22
578 - AD25
579 - AD26
580 - AE16
581 - AE17
582 - AE18
583 - AE19
584 - AE20
585 - AE21
586 - AE23
587 - AE25
588 - AE26
589 - AF16
590 - AF17
591 - AF18
592 - AF19
593 - AF20
594 - AF21
595 - AF23
596 - AF25
597 - AF26
598 - B10
599 - B11
600 - B12
601 - B13
602 - B14
603 - B15
604 - B16
605 - B18
606 - B19
607 - B21
608 - B22
609 - B23
610 - B24
611 - B25
612 - B26
613 - B6
614 - B7
615 - B8
616 - B9
617 - C10
618 - C11
619 - C12
620 - C13
621 - C14
622 - C15
623 - C16
624 - C17
625 - C18
626 - C19
627 - C20
628 - C23
629 - C26
630 - C6
631 - C7
632 - C8
633 - C9
634 - D10
635 - D12
636 - D14
637 - D15
638 - D19
639 - D20
640 - D24
641 - D26
642 - D7
643 - D8
644 - D9
645 - E10
646 - E11
647 - E12
648 - E13
649 - E14
650 - E26
651 - E7
652 - E8
653 - E9
654 - F10
655 - F11
656 - F12
657 - F13
658 - F14
659 - F26
660 - F7
661 - F8
662 - F9
663 - G10
664 - G11
665 - G7
666 - G8
667 - G9
668 - H10
669 - H11
670 - H7
671 - H8
672 - H9
673 - J10
674 - J11
675 - J12
676 - J13
677 - J9
678 - K12
679 - K13
680 - L12
681 - M13
682 - M14
683 - M15
684 - M16
685 - N13
686 - N14
687 - N15
688 - N25
689 - N26
690 - P13
691 - P14
692 - P25
693 - P26
694 - R14
695 - R25
696 - R26
697 - T23
698 - T24
699 - U21
700 - U22
701 - U25
702 - U26
703 - V14
704 - V16
705 - V17
706 - V18
707 - V19
708 - V20
709 - V21
710 - V22
711 - V23
712 - V24
713 - W14
714 - W16
715 - W17
716 - W18
717 - W20
718 - W21
719 - W22
720 - W25
721 - W26
722 - Y11
723 - Y15
724 - Y16
725 - Y17
726 - Y18
727 - Y20
728 - Y21
729 - Y22
730 - Y23
731 - Y24
732 - Y25
733 - Y26
734
735 drive-strength:
736 enum: [4, 8, 12, 16]
737
738 bias-disable: true
739 bias-pull-up: true
740 bias-pull-down: true
741
742required:
743 - compatible
744 - reg
745
746allOf:
747 - $ref: pinctrl.yaml#
748
749additionalProperties: false
750
751examples:
752 - |
753 pinctrl@400 {
754 compatible = "aspeed,ast2700-soc1-pinctrl";
755 reg = <0x400 0x2A0>;
756 sgpm0-state {
757 function = "SGPM0";
758 groups = "SGPM0";
759 };
760 };
Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml+1−0
@@ -17,6 +17,7 @@ properties: · 16 unmodified lines
17 enum:17 enum:
18 - mediatek,mt2701-pinctrl18 - mediatek,mt2701-pinctrl
19 - mediatek,mt2712-pinctrl19 - mediatek,mt2712-pinctrl
20 - mediatek,mt6392-pinctrl
20 - mediatek,mt6397-pinctrl21 - mediatek,mt6397-pinctrl
21 - mediatek,mt7623-pinctrl22 - mediatek,mt7623-pinctrl
22 - mediatek,mt8127-pinctrl23 - mediatek,mt8127-pinctrl
Documentation/devicetree/bindings/pinctrl/mediatek,mt6795-pinctrl.yaml+8−0
@@ -152,6 +152,14 @@ patternProperties: · 151 unmodified lines
152 $ref: /schemas/types.yaml#/definitions/uint32152 $ref: /schemas/types.yaml#/definitions/uint32
153 enum: [0, 1, 2, 3]153 enum: [0, 1, 2, 3]
154 154
155 slew-rate:
156 description: |
157 Set the slew rate. Valid arguments are described as below:
158 0: Normal slew rate
159 1: Slower slew
160 $ref: /schemas/types.yaml#/definitions/uint32
161 enum: [0, 1]
162
155 required:163 required:
156 - pinmux164 - pinmux
157 165
Documentation/devicetree/bindings/pinctrl/mediatek,mt8188-pinctrl.yaml+5−0
@@ -67,6 +67,11 @@ properties: · 66 unmodified lines
67 67
68# PIN CONFIGURATION NODES68# PIN CONFIGURATION NODES
69patternProperties:69patternProperties:
70 "-hog(-[0-9]+)?$":
71 type: object
72 required:
73 - gpio-hog
74
70 '-pins$':75 '-pins$':
71 type: object76 type: object
72 additionalProperties: false77 additionalProperties: false
Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux-aon.yaml+5−1
@@ -58,7 +58,11 @@ patternProperties: · 57 unmodified lines
58 drive_soc_gpio27_pee6, drive_ao_retention_n_pee2,58 drive_soc_gpio27_pee6, drive_ao_retention_n_pee2,
59 drive_vcomp_alert_pee1, drive_hdmi_cec_pgg0 ]59 drive_vcomp_alert_pee1, drive_hdmi_cec_pgg0 ]
60 60
61unevaluatedProperties: false61required:
62 - compatible
63 - reg
64
65additionalProperties: false
62 66
63examples:67examples:
64 - |68 - |
Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux.yaml+5−1
@@ -115,7 +115,11 @@ patternProperties: · 114 unmodified lines
115 drive_sdmmc1_dat2_pj4, drive_sdmmc1_dat1_pj3,115 drive_sdmmc1_dat2_pj4, drive_sdmmc1_dat1_pj3,
116 drive_sdmmc1_dat0_pj2 ]116 drive_sdmmc1_dat0_pj2 ]
117 117
118unevaluatedProperties: false118required:
119 - compatible
120 - reg
121
122additionalProperties: false
119 123
120examples:124examples:
121 - |125 - |
Documentation/devicetree/bindings/pinctrl/nvidia,tegra238-pinmux-aon.yaml+102−0
@@ -0,0 +1,102 @@
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra238-pinmux-aon.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: NVIDIA Tegra238 AON Pinmux Controller
8
9maintainers:
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12
13properties:
14 compatible:
15 const: nvidia,tegra238-pinmux-aon
16
17 reg:
18 maxItems: 1
19
20patternProperties:
21 "^pinmux(-[a-z0-9-]+)?$":
22 type: object
23
24 # pin groups
25 additionalProperties:
26 $ref: nvidia,tegra238-pinmux-common.yaml
27
28 properties:
29 nvidia,pins:
30 items:
31 enum: [ bootv_ctl_n_paa0, soc_gpio00_paa1, vcomp_alert_paa2,
32 pwm1_paa3, batt_oc_paa4, soc_gpio04_paa5,
33 soc_gpio25_paa6, soc_gpio26_paa7,
34 hdmi_cec_pbb0,
35 spi2_sck_pcc0, spi2_miso_pcc1, spi2_mosi_pcc2,
36 spi2_cs0_pcc3, spi2_cs1_pcc4, uart3_tx_pcc5,
37 uart3_rx_pcc6, gen2_i2c_scl_pcc7,
38 gen2_i2c_sda_pdd0, gen8_i2c_scl_pdd1,
39 gen8_i2c_sda_pdd2, touch_clk_pdd3, dmic1_clk_pdd4,
40 dmic1_dat_pdd5, soc_gpio19_pdd6, pwm2_pdd7,
41 pwm3_pee0, pwm7_pee1, soc_gpio49_pee2,
42 soc_gpio82_pee3, soc_gpio50_pee4, soc_gpio83_pee5,
43 soc_gpio69_pff0, soc_gpio70_pff1, soc_gpio71_pff2,
44 soc_gpio72_pff3, soc_gpio73_pff4, soc_gpio74_pff5,
45 soc_gpio80_pff6, soc_gpio76_pff7, soc_gpio77_pgg0,
46 soc_gpio84_pgg1, uart2_tx_pgg2, uart2_rx_pgg3,
47 uart2_rts_pgg4, uart2_cts_pgg5, soc_gpio85_pgg6,
48 uart5_tx_pgg7, uart5_rx_phh0, uart5_rts_phh1,
49 uart5_cts_phh2, soc_gpio86_phh3,
50 # drive groups (ordered PAA, PBB, PCC, PDD, PEE, PFF, PGG, PHH)
51 drive_bootv_ctl_n_paa0, drive_soc_gpio00_paa1,
52 drive_vcomp_alert_paa2, drive_pwm1_paa3,
53 drive_batt_oc_paa4, drive_soc_gpio04_paa5,
54 drive_soc_gpio25_paa6, drive_soc_gpio26_paa7,
55 drive_hdmi_cec_pbb0,
56 drive_spi2_sck_pcc0, drive_spi2_miso_pcc1,
57 drive_spi2_mosi_pcc2, drive_spi2_cs0_pcc3,
58 drive_spi2_cs1_pcc4, drive_uart3_tx_pcc5,
59 drive_uart3_rx_pcc6, drive_gen2_i2c_scl_pcc7,
60 drive_gen2_i2c_sda_pdd0, drive_gen8_i2c_scl_pdd1,
61 drive_gen8_i2c_sda_pdd2, drive_touch_clk_pdd3,
62 drive_dmic1_clk_pdd4, drive_dmic1_dat_pdd5,
63 drive_soc_gpio19_pdd6, drive_pwm2_pdd7,
64 drive_pwm3_pee0, drive_pwm7_pee1,
65 drive_soc_gpio49_pee2, drive_soc_gpio50_pee4,
66 drive_soc_gpio82_pee3, drive_soc_gpio71_pff2,
67 drive_soc_gpio76_pff7, drive_soc_gpio74_pff5,
68 drive_soc_gpio86_phh3, drive_soc_gpio72_pff3,
69 drive_soc_gpio77_pgg0, drive_soc_gpio80_pff6,
70 drive_soc_gpio84_pgg1, drive_soc_gpio83_pee5,
71 drive_soc_gpio73_pff4, drive_soc_gpio70_pff1,
72 drive_soc_gpio85_pgg6, drive_soc_gpio69_pff0,
73 drive_uart5_tx_pgg7, drive_uart5_rx_phh0,
74 drive_uart2_tx_pgg2, drive_uart2_rx_pgg3,
75 drive_uart2_cts_pgg5, drive_uart2_rts_pgg4,
76 drive_uart5_cts_phh2, drive_uart5_rts_phh1 ]
77
78required:
79 - compatible
80 - reg
81
82additionalProperties: false
83
84examples:
85 - |
86 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
87
88 pinmux@c300000 {
89 compatible = "nvidia,tegra238-pinmux-aon";
90 reg = <0x0c300000 0x4000>;
91
92 pinctrl-names = "cec";
93 pinctrl-0 = <&cec_state>;
94
95 cec_state: pinmux-cec {
96 cec {
97 nvidia,pins = "hdmi_cec_pbb0";
98 nvidia,function = "hdmi_cec";
99 };
100 };
101 };
102...
Documentation/devicetree/bindings/pinctrl/nvidia,tegra238-pinmux-common.yaml+73−0
@@ -0,0 +1,73 @@
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra238-pinmux-common.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: NVIDIA Tegra238 Pinmux Controller
8
9maintainers:
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12
13$ref: nvidia,tegra-pinmux-common.yaml
14
15properties:
16 nvidia,function:
17 enum: [ dca_vsync, dca_hsync, displaya, rsvd0, i2c7_clk, i2c7_dat,
18 i2c4_dat, i2c4_clk, i2c9_dat, i2c9_clk, usb_vbus_en0,
19 usb_vbus_en1, spi3_din, spi1_cs0, spi3_cs0, spi1_din,
20 spi3_cs1, spi1_sck, spi3_sck, spi1_cs1, spi1_dout, spi3_dout,
21 gp_pwm5, gp_pwm6, extperiph2_clk, extperiph1_clk, i2c3_dat,
22 i2c3_clk, extperiph4_clk, extperiph3_clk, dmic2_dat,
23 dmic2_clk, uarta_cts, uarta_rts, uarta_rxd, uarta_txd,
24 i2c5_clk, i2c5_dat, uartd_cts, uartd_rts, uartd_rxd,
25 uartd_txd, i2c1_clk, i2c1_dat, sdmmc1_cd, i2s2_sclk,
26 i2s2_sdata_out, i2s2_sdata_in, i2s2_lrck, i2s4_sclk,
27 i2s4_sdata_out, i2s4_sdata_in, i2s4_lrck, i2s1_sclk,
28 i2s1_sdata_out, i2s1_sdata_in, i2s1_lrck, aud_mclk,
29 i2s3_lrck, i2s3_sclk, i2s3_sdata_in, i2s3_sdata_out,
30 pe2_clkreq_l, pe1_clkreq_l, pe1_rst_l, pe0_clkreq_l,
31 pe0_rst_l, pe2_rst_l, pe3_clkreq_l, pe3_rst_l,
32 dp_aux_ch0_hpd, qspi0_io0, qspi0_io1, qspi0_sck, qspi0_cs_n,
33 uartg_cts, uartg_rts, uartg_txd, uartg_rxd, sdmmc1_clk,
34 sdmmc1_cmd, sdmmc1_comp, sdmmc1_dat3, sdmmc1_dat2,
35 sdmmc1_dat1, sdmmc1_dat0, ufs0, soc_therm_oc1, hdmi_cec,
36 gp_pwm4, uartc_rxd, uartc_txd, i2c8_dat, i2c8_clk,
37 spi2_dout, i2c2_clk, spi2_cs0, i2c2_dat, spi2_sck, spi2_din,
38 ppc_mode_1, ppc_ready, ppc_mode_2, ppc_cc, ppc_mode_0,
39 ppc_int_n, uarte_txd, uarte_rxd, uartb_txd, uartb_rxd,
40 uartb_cts, uartb_rts, uarte_cts, uarte_rts, gp_pwm7,
41 gp_pwm2, gp_pwm3, gp_pwm1, spi2_cs1, dmic1_clk, dmic1_dat,
42 rsvd1, dcb_hsync, dcb_vsync, soc_therm_oc4, gp_pwm8,
43 nv_therm_fan_tach0, wdt_reset_outa, ccla_la_trigger_mux,
44 dspk1_dat, dspk1_clk, nv_therm_fan_tach1, dspk0_dat,
45 dspk0_clk, i2s5_sclk, i2s6_lrck, i2s6_sdata_in, i2s6_sclk,
46 i2s6_sdata_out, i2s5_lrck, i2s5_sdata_out, i2s5_sdata_in,
47 sdmmc1_pe3_rst_l, sdmmc1_pe3_clkreq_l, touch_clk,
48 ppc_i2c_dat, wdt_reset_outb, spi5_cs1, ppc_rst_n,
49 ppc_i2c_clk, spi4_cs1, soc_therm_oc3, spi5_sck, spi5_miso,
50 spi4_sck, spi4_miso, spi4_cs0, spi4_mosi, spi5_cs0,
51 spi5_mosi, led_blink, rsvd2, dmic3_clk, dmic3_dat,
52 dmic4_clk, dmic4_dat, tsc_edge_out0, tsc_edge_out3,
53 tsc_edge_out1, tsc_edge_out2, dmic5_clk, dmic5_dat, rsvd3,
54 sdmmc1_wp, tsc_edge_out0a, tsc_edge_out0d, tsc_edge_out0b,
55 tsc_edge_out0c, soc_therm_oc2 ]
56
57 # out of the common properties, only these are allowed for Tegra238
58 nvidia,pins: true
59 nvidia,pull: true
60 nvidia,tristate: true
61 nvidia,schmitt: true
62 nvidia,enable-input: true
63 nvidia,open-drain: true
64 nvidia,lock: true
65 nvidia,drive-type: true
66 nvidia,io-hv: true
67
68required:
69 - nvidia,pins
70
71additionalProperties: false
72
73...
Documentation/devicetree/bindings/pinctrl/nvidia,tegra238-pinmux.yaml+219−0
@@ -0,0 +1,219 @@
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra238-pinmux.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: NVIDIA Tegra238 Pinmux Controller
8
9maintainers:
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12
13properties:
14 compatible:
15 const: nvidia,tegra238-pinmux
16
17 reg:
18 maxItems: 1
19
20patternProperties:
21 "^pinmux(-[a-z0-9-]+)?$":
22 type: object
23
24 # pin groups
25 additionalProperties:
26 $ref: nvidia,tegra238-pinmux-common.yaml
27
28 properties:
29 nvidia,pins:
30 items:
31 enum: [ gpu_pwr_req_pa0, gp_pwm5_pa1, gp_pwm6_pa2, spi3_sck_pa3,
32 spi3_miso_pa4, spi3_mosi_pa5, spi3_cs0_pa6, spi3_cs1_pa7,
33 spi1_sck_pb0, spi1_miso_pb1, spi1_mosi_pb2, spi1_cs0_pb3,
34 spi1_cs1_pb4, pwr_i2c_scl_pc0, pwr_i2c_sda_pc1,
35 extperiph1_clk_pc2, extperiph2_clk_pc3, cam_i2c_scl_pc4,
36 cam_i2c_sda_pc5, soc_gpio23_pc6, soc_gpio24_pc7,
37 soc_gpio27_pd0, soc_gpio55_pd1, soc_gpio29_pd2,
38 soc_gpio33_pd3, soc_gpio32_pd4, soc_gpio35_pd5,
39 soc_gpio37_pd6, soc_gpio56_pd7, uart1_tx_pe0,
40 uart1_rx_pe1, uart1_rts_pe2, uart1_cts_pe3,
41 soc_gpio13_pf0, soc_gpio14_pf1, soc_gpio15_pf2,
42 soc_gpio16_pf3, soc_gpio17_pf4, soc_gpio18_pf5,
43 soc_gpio20_pf6, soc_gpio21_pf7, soc_gpio22_pg0,
44 soc_gpio06_pg1, uart4_tx_pg2, uart4_rx_pg3,
45 uart4_rts_pg4, uart4_cts_pg5, soc_gpio41_pg6,
46 soc_gpio42_pg7, soc_gpio43_ph0, soc_gpio44_ph1,
47 gen1_i2c_scl_ph2, gen1_i2c_sda_ph3, cpu_pwr_req_ph4,
48 soc_gpio07_ph5, dap3_clk_pj0, dap3_dout_pj1,
49 dap3_din_pj2, dap3_fs_pj3, soc_gpio57_pj4,
50 soc_gpio58_pj5, soc_gpio59_pj6, soc_gpio60_pj7,
51 soc_gpio45_pk0, soc_gpio46_pk1, soc_gpio47_pk2,
52 soc_gpio48_pk3, qspi0_sck_pl0, qspi0_io0_pl1,
53 qspi0_io1_pl2, qspi0_cs_n_pl3, soc_gpio152_pl4,
54 soc_gpio153_pl5, soc_gpio154_pl6, soc_gpio155_pl7,
55 soc_gpio156_pm0, soc_gpio157_pm1, soc_gpio158_pm2,
56 soc_gpio159_pm3, soc_gpio160_pm4, soc_gpio161_pm5,
57 soc_gpio162_pm6, uart7_tx_pm7, uart7_rx_pn0,
58 uart7_rts_pn1, uart7_cts_pn2, soc_gpio167_pp0,
59 soc_gpio168_pp1, soc_gpio169_pp2, soc_gpio170_pp3,
60 dap4_sclk_pp4, dap4_dout_pp5, dap4_din_pp6, dap4_fs_pp7,
61 soc_gpio171_pq0, soc_gpio172_pq1, soc_gpio173_pq2,
62 soc_gpio61_pr0, soc_gpio62_pr1, soc_gpio63_pr2,
63 soc_gpio64_pr3, soc_gpio65_pr4, soc_gpio66_pr5,
64 soc_gpio67_pr6, soc_gpio68_pr7, gen4_i2c_scl_ps0,
65 gen4_i2c_sda_ps1, soc_gpio75_ps2, gen7_i2c_scl_ps3,
66 gen7_i2c_sda_ps4, soc_gpio78_ps5, gen9_i2c_scl_ps6,
67 gen9_i2c_sda_ps7, soc_gpio81_pt0, soc_gpio36_pt1,
68 soc_gpio53_pt2, soc_gpio38_pt3, soc_gpio40_pt4,
69 soc_gpio34_pt5, usb_vbus_en0_pt6, usb_vbus_en1_pt7,
70 sdmmc1_clk_pu0, sdmmc1_cmd_pu1, sdmmc1_dat0_pu2,
71 sdmmc1_dat1_pu3, sdmmc1_dat2_pu4, sdmmc1_dat3_pu5,
72 ufs0_ref_clk_pv0, ufs0_rst_n_pv1, pex_l0_clkreq_n_pw0,
73 pex_l0_rst_n_pw1, pex_l1_clkreq_n_pw2,
74 pex_l1_rst_n_pw3, pex_l2_clkreq_n_pw4,
75 pex_l2_rst_n_pw5, pex_l3_clkreq_n_pw6,
76 pex_l3_rst_n_pw7, pex_wake_n_px0, dp_aux_ch0_hpd_px1,
77 bootv_ctl_n_paa0, soc_gpio00_paa1, vcomp_alert_paa2,
78 pwm1_paa3, batt_oc_paa4, soc_gpio04_paa5,
79 soc_gpio25_paa6, soc_gpio26_paa7, hdmi_cec_pbb0,
80 spi2_sck_pcc0, spi2_miso_pcc1, spi2_mosi_pcc2,
81 spi2_cs0_pcc3, spi2_cs1_pcc4, uart3_tx_pcc5,
82 uart3_rx_pcc6, gen2_i2c_scl_pcc7, gen2_i2c_sda_pdd0,
83 gen8_i2c_scl_pdd1, gen8_i2c_sda_pdd2, touch_clk_pdd3,
84 dmic1_clk_pdd4, dmic1_dat_pdd5, soc_gpio19_pdd6,
85 pwm2_pdd7, pwm3_pee0, pwm7_pee1, soc_gpio49_pee2,
86 soc_gpio82_pee3, soc_gpio50_pee4, soc_gpio83_pee5,
87 soc_gpio69_pff0, soc_gpio70_pff1, soc_gpio71_pff2,
88 soc_gpio72_pff3, soc_gpio73_pff4, soc_gpio74_pff5,
89 soc_gpio80_pff6, soc_gpio76_pff7, soc_gpio77_pgg0,
90 soc_gpio84_pgg1, uart2_tx_pgg2, uart2_rx_pgg3,
91 uart2_rts_pgg4, uart2_cts_pgg5, soc_gpio85_pgg6,
92 uart5_tx_pgg7, uart5_rx_phh0, uart5_rts_phh1,
93 uart5_cts_phh2, soc_gpio86_phh3, sdmmc1_comp,
94 # drive groups
95 drive_soc_gpio36_pt1, drive_soc_gpio53_pt2,
96 drive_soc_gpio38_pt3, drive_soc_gpio40_pt4,
97 drive_soc_gpio75_ps2, drive_soc_gpio81_pt0,
98 drive_soc_gpio78_ps5, drive_soc_gpio34_pt5,
99 drive_gen7_i2c_scl_ps3, drive_gen7_i2c_sda_ps4,
100 drive_gen4_i2c_sda_ps1, drive_gen4_i2c_scl_ps0,
101 drive_gen9_i2c_sda_ps7, drive_gen9_i2c_scl_ps6,
102 drive_usb_vbus_en0_pt6, drive_usb_vbus_en1_pt7,
103 drive_soc_gpio61_pr0, drive_soc_gpio62_pr1,
104 drive_soc_gpio63_pr2, drive_soc_gpio64_pr3,
105 drive_soc_gpio65_pr4, drive_soc_gpio66_pr5,
106 drive_soc_gpio67_pr6, drive_soc_gpio68_pr7,
107 drive_spi3_miso_pa4, drive_spi1_cs0_pb3,
108 drive_spi3_cs0_pa6, drive_spi1_miso_pb1,
109 drive_spi3_cs1_pa7, drive_spi1_sck_pb0,
110 drive_spi3_sck_pa3, drive_spi1_cs1_pb4,
111 drive_spi1_mosi_pb2, drive_spi3_mosi_pa5,
112 drive_gpu_pwr_req_pa0, drive_gp_pwm5_pa1,
113 drive_gp_pwm6_pa2, drive_extperiph2_clk_pc3,
114 drive_extperiph1_clk_pc2, drive_cam_i2c_sda_pc5,
115 drive_cam_i2c_scl_pc4, drive_soc_gpio23_pc6,
116 drive_soc_gpio24_pc7, drive_soc_gpio27_pd0,
117 drive_soc_gpio29_pd2, drive_soc_gpio32_pd4,
118 drive_soc_gpio33_pd3, drive_soc_gpio35_pd5,
119 drive_soc_gpio37_pd6, drive_soc_gpio56_pd7,
120 drive_soc_gpio55_pd1, drive_uart1_cts_pe3,
121 drive_uart1_rts_pe2, drive_uart1_rx_pe1,
122 drive_uart1_tx_pe0, drive_pwr_i2c_scl_pc0,
123 drive_pwr_i2c_sda_pc1, drive_cpu_pwr_req_ph4,
124 drive_uart4_cts_pg5, drive_uart4_rts_pg4,
125 drive_uart4_rx_pg3, drive_uart4_tx_pg2,
126 drive_gen1_i2c_scl_ph2, drive_gen1_i2c_sda_ph3,
127 drive_soc_gpio20_pf6, drive_soc_gpio21_pf7,
128 drive_soc_gpio22_pg0, drive_soc_gpio13_pf0,
129 drive_soc_gpio14_pf1, drive_soc_gpio15_pf2,
130 drive_soc_gpio16_pf3, drive_soc_gpio17_pf4,
131 drive_soc_gpio18_pf5, drive_soc_gpio41_pg6,
132 drive_soc_gpio42_pg7, drive_soc_gpio43_ph0,
133 drive_soc_gpio44_ph1, drive_soc_gpio06_pg1,
134 drive_soc_gpio07_ph5, drive_dap4_sclk_pp4,
135 drive_dap4_dout_pp5, drive_dap4_din_pp6,
136 drive_dap4_fs_pp7, drive_soc_gpio167_pp0,
137 drive_soc_gpio168_pp1, drive_soc_gpio169_pp2,
138 drive_soc_gpio170_pp3, drive_soc_gpio171_pq0,
139 drive_soc_gpio172_pq1, drive_soc_gpio173_pq2,
140 drive_soc_gpio45_pk0, drive_soc_gpio46_pk1,
141 drive_soc_gpio47_pk2, drive_soc_gpio48_pk3,
142 drive_soc_gpio57_pj4, drive_soc_gpio58_pj5,
143 drive_soc_gpio59_pj6, drive_soc_gpio60_pj7,
144 drive_dap3_fs_pj3, drive_dap3_clk_pj0,
145 drive_dap3_din_pj2, drive_dap3_dout_pj1,
146 drive_pex_l2_clkreq_n_pw4, drive_pex_wake_n_px0,
147 drive_pex_l1_clkreq_n_pw2, drive_pex_l1_rst_n_pw3,
148 drive_pex_l0_clkreq_n_pw0, drive_pex_l0_rst_n_pw1,
149 drive_pex_l2_rst_n_pw5, drive_pex_l3_clkreq_n_pw6,
150 drive_pex_l3_rst_n_pw7, drive_dp_aux_ch0_hpd_px1,
151 drive_qspi0_io0_pl1, drive_qspi0_io1_pl2,
152 drive_qspi0_sck_pl0, drive_qspi0_cs_n_pl3,
153 drive_soc_gpio156_pm0, drive_soc_gpio155_pl7,
154 drive_soc_gpio160_pm4, drive_soc_gpio154_pl6,
155 drive_soc_gpio152_pl4, drive_soc_gpio153_pl5,
156 drive_soc_gpio161_pm5, drive_soc_gpio162_pm6,
157 drive_soc_gpio159_pm3, drive_soc_gpio157_pm1,
158 drive_soc_gpio158_pm2, drive_uart7_cts_pn2,
159 drive_uart7_rts_pn1, drive_uart7_tx_pm7,
160 drive_uart7_rx_pn0, drive_sdmmc1_clk_pu0,
161 drive_sdmmc1_cmd_pu1, drive_sdmmc1_dat3_pu5,
162 drive_sdmmc1_dat2_pu4, drive_sdmmc1_dat1_pu3,
163 drive_sdmmc1_dat0_pu2, drive_ufs0_rst_n_pv1,
164 drive_ufs0_ref_clk_pv0, drive_batt_oc_paa4,
165 drive_bootv_ctl_n_paa0, drive_vcomp_alert_paa2,
166 drive_hdmi_cec_pbb0, drive_touch_clk_pdd3,
167 drive_uart3_rx_pcc6, drive_uart3_tx_pcc5,
168 drive_gen8_i2c_sda_pdd2, drive_gen8_i2c_scl_pdd1,
169 drive_spi2_mosi_pcc2, drive_gen2_i2c_scl_pcc7,
170 drive_spi2_cs0_pcc3, drive_gen2_i2c_sda_pdd0,
171 drive_spi2_sck_pcc0, drive_spi2_miso_pcc1,
172 drive_soc_gpio49_pee2, drive_soc_gpio50_pee4,
173 drive_soc_gpio82_pee3, drive_soc_gpio71_pff2,
174 drive_soc_gpio76_pff7, drive_soc_gpio74_pff5,
175 drive_soc_gpio00_paa1, drive_soc_gpio19_pdd6,
176 drive_soc_gpio86_phh3, drive_soc_gpio72_pff3,
177 drive_soc_gpio77_pgg0, drive_soc_gpio80_pff6,
178 drive_soc_gpio84_pgg1, drive_soc_gpio83_pee5,
179 drive_soc_gpio73_pff4, drive_soc_gpio70_pff1,
180 drive_soc_gpio04_paa5, drive_soc_gpio85_pgg6,
181 drive_soc_gpio69_pff0, drive_soc_gpio25_paa6,
182 drive_soc_gpio26_paa7, drive_uart5_tx_pgg7,
183 drive_uart5_rx_phh0, drive_uart2_tx_pgg2,
184 drive_uart2_rx_pgg3, drive_uart2_cts_pgg5,
185 drive_uart2_rts_pgg4, drive_uart5_cts_phh2,
186 drive_uart5_rts_phh1, drive_pwm7_pee1,
187 drive_pwm2_pdd7, drive_pwm3_pee0, drive_pwm1_paa3,
188 drive_spi2_cs1_pcc4, drive_dmic1_clk_pdd4,
189 drive_dmic1_dat_pdd5, drive_sdmmc1_comp ]
190
191required:
192 - compatible
193 - reg
194
195additionalProperties: false
196
197examples:
198 - |
199 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
200
201 pinmux@2430000 {
202 compatible = "nvidia,tegra238-pinmux";
203 reg = <0x2430000 0x17000>;
204
205 pinctrl-names = "pex_rst";
206 pinctrl-0 = <&pex_rst_c5_out_state>;
207
208 pex_rst_c5_out_state: pinmux-pex-rst-c5-out {
209 pexrst {
210 nvidia,pins = "pex_l3_rst_n_pw7";
211 nvidia,schmitt = <TEGRA_PIN_DISABLE>;
212 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
213 nvidia,io-hv = <TEGRA_PIN_ENABLE>;
214 nvidia,tristate = <TEGRA_PIN_DISABLE>;
215 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
216 };
217 };
218 };
219...
Documentation/devicetree/bindings/pinctrl/nvidia,tegra264-pinmux-aon.yaml+80−0
@@ -0,0 +1,80 @@
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra264-pinmux-aon.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: NVIDIA Tegra264 AON Pinmux Controller
8
9maintainers:
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12
13properties:
14 compatible:
15 const: nvidia,tegra264-pinmux-aon
16
17 reg:
18 maxItems: 1
19
20patternProperties:
21 "^pinmux(-[a-z0-9-]+)?$":
22 type: object
23
24 # pin groups
25 additionalProperties:
26 $ref: nvidia,tegra264-pinmux-common.yaml
27
28 properties:
29 nvidia,pins:
30 items:
31 enum: [ soc_gpio00_paa0, vcomp_alert_paa1, ao_retention_n_paa2,
32 batt_oc_paa3, bootv_ctl_n_paa4, power_on_paa5,
33 hdmi_cec_paa6, soc_gpio07_paa7, soc_gpio08_pbb0,
34 soc_gpio09_pbb1, gen2_i2c_scl_pcc0, gen2_i2c_sda_pcc1,
35 gen3_i2c_scl_pcc2, gen3_i2c_sda_pcc3, gp_pwm4_pcc4,
36 uart0_tx_pcc5, uart0_rx_pcc6, spi2_sck_pcc7,
37 spi2_miso_pdd0, spi2_mosi_pdd1, spi2_cs0_n_pdd2,
38 soc_gpio21_pdd3, soc_gpio22_pdd4, soc_gpio23_pdd5,
39 soc_gpio24_pdd6, soc_gpio25_pdd7, soc_gpio26_pee0,
40 soc_gpio27_pee1, soc_gpio28_pee2, soc_gpio29_pee3,
41 drive_ao_retention_n_paa2, drive_batt_oc_paa3,
42 drive_power_on_paa5, drive_vcomp_alert_paa1,
43 drive_bootv_ctl_n_paa4, drive_soc_gpio00_paa0,
44 drive_soc_gpio07_paa7, drive_soc_gpio08_pbb0,
45 drive_soc_gpio09_pbb1, drive_hdmi_cec_paa6,
46 drive_gen2_i2c_scl_pcc0, drive_gen2_i2c_sda_pcc1,
47 drive_gen3_i2c_scl_pcc2, drive_gen3_i2c_sda_pcc3,
48 drive_gp_pwm4_pcc4, drive_uart0_tx_pcc5,
49 drive_uart0_rx_pcc6, drive_spi2_sck_pcc7,
50 drive_spi2_miso_pdd0, drive_spi2_mosi_pdd1,
51 drive_spi2_cs0_n_pdd2, drive_soc_gpio21_pdd3,
52 drive_soc_gpio22_pdd4, drive_soc_gpio23_pdd5,
53 drive_soc_gpio24_pdd6, drive_soc_gpio25_pdd7,
54 drive_soc_gpio26_pee0, drive_soc_gpio27_pee1,
55 drive_soc_gpio28_pee2, drive_soc_gpio29_pee3 ]
56
57required:
58 - compatible
59 - reg
60
61additionalProperties: false
62
63examples:
64 - |
65 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
66
67 pinmux@c7a2000 {
68 compatible = "nvidia,tegra264-pinmux-aon";
69 reg = <0xc7a2000 0x2000>;
70
71 pinctrl-names = "default";
72 pinctrl-0 = <&state_default>;
73
74 state_default: pinmux-default {
75 uart0 {
76 nvidia,pins = "uart0_tx_pcc5";
77 nvidia,function = "uarta_txd";
78 };
79 };
80 };
Documentation/devicetree/bindings/pinctrl/nvidia,tegra264-pinmux-common.yaml+84−0
@@ -0,0 +1,84 @@
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra264-pinmux-common.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: NVIDIA Tegra264 Pinmux Common Properties
8
9maintainers:
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12
13$ref: nvidia,tegra-pinmux-common.yaml
14
15properties:
16 nvidia,function:
17 enum: [ dca_vsync, dca_hsync, rsvd0, dp_aux_ch0_hpd, dp_aux_ch1_hpd,
18 dp_aux_ch2_hpd, dp_aux_ch3_hpd, gp_pwm2, gp_pwm3, i2c7_clk,
19 i2c7_dat, i2c9_clk, i2c9_dat, uartk_cts, uartk_rts, uartk_rxd,
20 uartk_txd, spi3_cs0, spi3_cs3, spi3_din, spi3_dout, spi3_sck,
21 uartf_cts, uartf_rts, uartf_rxd, uartf_txd, spi1_cs0, spi1_cs1,
22 spi1_din, spi1_dout, spi1_sck, extperiph2_clk, extperiph1_clk,
23 i2c12_clk, i2c12_dat, nv_therm_fan_tach0, gp_pwm9, uartj_cts,
24 uartj_rts, uartj_rxd, uartj_txd, i2c0_clk, i2c0_dat, i2c1_clk,
25 i2c1_dat, i2s2_lrck, i2s2_sclk, i2s2_sdata_out, i2s2_sdata_in,
26 gp_pwm10, uarte_cts, uarte_rts, uarte_rxd, uarte_txd, i2c5_dat,
27 i2c5_clk, i2s6_sdata_in, i2s6_sdata_out, i2s6_lrck, i2s6_sclk,
28 i2s4_sdata_out, i2s4_sclk, i2s4_sdata_in, i2s4_lrck, spi5_cs0,
29 spi5_din, spi5_dout, spi5_sck, aud_mclk, i2s1_sclk, i2s1_sdata_in,
30 i2s1_sdata_out, i2s1_lrck, i2c11_clk, i2c11_dat, xhalt_trig,
31 gp_pwm1, gp_pwm6, gp_pwm7, gp_pwm8, ufs0, pe1_clkreq_l, pe1_rst_l,
32 pe2_rst_l, pe2_clkreq_l, pe3_clkreq_l, pe3_rst_l, sgmii0_sma_mdio,
33 sgmii0_sma_mdc, usb_vbus_en0, usb_vbus_en1, eth1_mdio, pe4_clkreq_l,
34 pe4_rst_l, pe5_clkreq_l, pe5_rst_l, eth0_mdio, eth0_mdc, eth1_mdc,
35 eth2_mdio, eth2_mdc, eth3_mdio, eth3_mdc, qspi0_cs_n, qspi0_io0,
36 qspi0_io1, qspi0_io2, qspi0_io3, qspi0_sck, sdmmc1_clk, sdmmc1_cmd,
37 sdmmc1_comp, sdmmc1_dat3, sdmmc1_dat2, sdmmc1_dat1, sdmmc1_dat0,
38 qspi3_sck, qspi3_cs0, qspi3_io0, qspi3_io1, dcb_vsync, dcb_hsync,
39 dsa_lspii, dce_vsync, dce_hsync, dch_vsync, dch_hsync, bl_en,
40 bl_pwm_dim0, rsvd1, soc_therm_oc3, i2s5_sclk, i2s5_sdata_in,
41 extperiph3_clk, extperiph4_clk, i2s5_sdata_out, i2s5_lrck,
42 sdmmc1_cd, i2s7_sdata_in, spi4_sck, spi4_din, spi4_dout, spi4_cs0,
43 spi4_cs1, gp_pwm5, i2c14_clk, i2c14_dat, i2s8_sclk, i2s8_sdata_out,
44 i2s8_lrck, i2s8_sdata_in, i2c16_clk, i2c16_dat, i2s3_sclk,
45 i2s3_sdata_out, i2s3_sdata_in, i2s3_lrck, pm_trig1, pm_trig0,
46 qspi2_sck, qspi2_cs0, qspi2_io0, qspi2_io1, dcc_vsync, dcc_hsync,
47 rsvd2, dcf_vsync, dcf_hsync, soundwire1_clk, soundwire1_dat0,
48 soundwire1_dat1, soundwire1_dat2, dmic2_clk, dmic2_dat,
49 nv_therm_fan_tach1, i2c15_clk, i2c15_dat, i2s7_lrck,
50 ccla_la_trigger_mux, i2s7_sclk, i2s7_sdata_out, dmic1_dat,
51 dmic1_clk, dcd_vsync, dcd_hsync, rsvd3, dcg_vsync, dcg_hsync,
52 dspk1_clk, dspk1_dat, soc_therm_oc2, istctrl_ist_done_n,
53 soc_therm_oc1, tsc_edge_out0c, tsc_edge_out0d, tsc_edge_out0a,
54 tsc_edge_out0b, touch_clk, hdmi_cec, i2c2_clk, i2c2_dat, i2c3_clk,
55 i2c3_dat, gp_pwm4, uarta_txd, uarta_rxd, spi2_sck, spi2_din,
56 spi2_dout, spi2_cs0, tsc_sync1, tsc_edge_out3, tsc_edge_out0,
57 tsc_edge_out1, tsc_sync0, soundwire0_clk, soundwire0_dat0,
58 l0l1_rst_out_n, l2_rst_out_n, uartl_txd, uartl_rxd, i2s9_sclk,
59 i2s9_sdata_out, i2s9_sdata_in, i2s9_lrck, dmic5_dat, dmic5_clk,
60 tsc_edge_out2 ]
61
62 # out of the common properties, only these are allowed for Tegra264
63 nvidia,pins: true
64 nvidia,pull: true
65 nvidia,tristate: true
66 nvidia,schmitt: true
67 nvidia,enable-input: true
68 nvidia,open-drain: true
69 nvidia,lock: true
70 nvidia,drive-type: true
71 nvidia,io-hv: true
72
73required:
74 - nvidia,pins
75
76# We would typically use unevaluatedProperties here but that has the
77# downside that all the properties in the common bindings become valid
78# for all chip generations. In this case, however, we want the per-SoC
79# bindings to be able to override which of the common properties are
80# allowed, since not all pinmux generations support the same sets of
81# properties. This way, the common bindings define the format of the
82# properties but the per-SoC bindings define which of them apply to a
83# given chip.
84additionalProperties: false
Documentation/devicetree/bindings/pinctrl/nvidia,tegra264-pinmux-main.yaml+167−0
@@ -0,0 +1,167 @@
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra264-pinmux-main.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: NVIDIA Tegra264 Main Pinmux Controller
8
9maintainers:
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12
13properties:
14 compatible:
15 const: nvidia,tegra264-pinmux-main
16
17 reg:
18 maxItems: 1
19
20patternProperties:
21 "^pinmux(-[a-z0-9-]+)?$":
22 type: object
23
24 # pin groups
25 additionalProperties:
26 $ref: nvidia,tegra264-pinmux-common.yaml
27
28 properties:
29 nvidia,pins:
30 items:
31 enum: [ pwm1_pa0, pwm6_pa1, pwm7_pa2, pwm8_pa3, ufs0_ref_clk_pa4,
32 ufs0_rst_n_pa5, soc_gpio250_pf0, soc_gpio251_pf1,
33 soc_gpio252_pf2, dp_aux_ch0_hpd_pf3, dp_aux_ch1_hpd_pf4,
34 dp_aux_ch2_hpd_pf5, dp_aux_ch3_hpd_pf6, pwm2_pf7, pwm3_pg0,
35 gen7_i2c_scl_pg1, gen7_i2c_sda_pg2, gen9_i2c_scl_pg3,
36 gen9_i2c_sda_pg4, sdmmc1_clk_px0, sdmmc1_cmd_px1,
37 sdmmc1_dat0_px2, sdmmc1_dat1_px3, sdmmc1_dat2_px4,
38 sdmmc1_dat3_px5, sdmmc1_comp, soc_gpio124_pl0,
39 soc_gpio125_pl1, fan_tach0_pl2, soc_gpio127_pl3,
40 soc_gpio128_pl4, soc_gpio129_pl5, soc_gpio130_pl6,
41 soc_gpio131_pl7, gp_pwm9_pm0, soc_gpio133_pm1, uart9_tx_pm2,
42 uart9_rx_pm3, uart9_rts_n_pm4, uart9_cts_n_pm5,
43 soc_gpio170_pu0, soc_gpio171_pu1, soc_gpio172_pu2,
44 soc_gpio173_pu3, soc_gpio174_pu4, soc_gpio175_pu5,
45 soc_gpio176_pu6, soc_gpio177_pu7, soc_gpio178_pv0,
46 pwm10_pv1, uart4_tx_pv2, uart4_rx_pv3, uart4_rts_n_pv4,
47 uart4_cts_n_pv5, dap2_clk_pv6, dap2_din_pv7, dap2_dout_pw0,
48 dap2_fs_pw1, gen1_i2c_scl_pw2, gen1_i2c_sda_pw3,
49 gen0_i2c_scl_pw4, gen0_i2c_sda_pw5, pwr_i2c_scl_pw6,
50 pwr_i2c_sda_pw7, soc_gpio138_pp0, soc_gpio139_pp1,
51 dap6_sclk_pp2, dap6_dout_pp3, dap6_din_pp4, dap6_fs_pp5,
52 dap4_sclk_pp6, dap4_dout_pp7, dap4_din_pq0, dap4_fs_pq1,
53 spi5_sck_pq2, spi5_miso_pq3, spi5_mosi_pq4, spi5_cs0_pq5,
54 soc_gpio152_pq6, soc_gpio153_pq7, aud_mclk_pr0,
55 soc_gpio155_pr1, dap1_sclk_pr2, dap1_out_pr3, dap1_in_pr4,
56 dap1_fs_pr5, gen11_i2c_scl_pr6, gen11_i2c_sda_pr7,
57 soc_gpio350_ps0, soc_gpio351_ps1, qspi0_sck_pt0,
58 qspi0_cs_n_pt1, qspi0_io0_pt2, qspi0_io1_pt3, qspi0_io2_pt4,
59 qspi0_io3_pt5, soc_gpio192_pt6, soc_gpio270_py0,
60 soc_gpio271_py1, soc_gpio272_py2, soc_gpio273_py3,
61 soc_gpio274_py4, soc_gpio275_py5, soc_gpio276_py6,
62 soc_gpio277_py7, soc_gpio278_pz0, soc_gpio279_pz1,
63 xhalt_trig_pz2, soc_gpio281_pz3, soc_gpio282_pz4,
64 soc_gpio283_pz5, soc_gpio284_pz6, soc_gpio285_pz7,
65 soc_gpio286_pal0, soc_gpio287_pal1, soc_gpio288_pal2,
66 cpu_pwr_req_ph0, gpu_pwr_req_ph1, uart10_tx_ph2,
67 uart10_rx_ph3, uart10_rts_n_ph4, uart10_cts_n_ph5,
68 spi3_sck_ph6, spi3_miso_ph7, spi3_mosi_pj0, spi3_cs0_pj1,
69 spi3_cs3_pj2, uart5_tx_pj3, uart5_rx_pj4, uart5_rts_n_pj5,
70 uart5_cts_n_pj6, spi1_sck_pj7, spi1_miso_pk0, spi1_mosi_pk1,
71 spi1_cs0_pk2, spi1_cs1_pk3, extperiph1_clk_pk4,
72 extperiph2_clk_pk5, gen12_i2c_scl_pk6, gen12_i2c_sda_pk7,
73 drive_cpu_pwr_req_ph0, drive_gpu_pwr_req_ph1,
74 drive_uart10_cts_n_ph5, drive_uart10_rts_n_ph4,
75 drive_uart10_rx_ph3, drive_uart10_tx_ph2,
76 drive_spi3_cs0_pj1, drive_spi3_cs3_pj2,
77 drive_spi3_miso_ph7, drive_spi3_mosi_pj0,
78 drive_spi3_sck_ph6, drive_uart5_cts_n_pj6,
79 drive_uart5_rts_n_pj5, drive_uart5_rx_pj4,
80 drive_uart5_tx_pj3, drive_spi1_cs0_pk2,
81 drive_spi1_cs1_pk3, drive_spi1_miso_pk0,
82 drive_spi1_mosi_pk1, drive_spi1_sck_pj7,
83 drive_extperiph2_clk_pk5, drive_extperiph1_clk_pk4,
84 drive_gen12_i2c_scl_pk6, drive_gen12_i2c_sda_pk7,
85 drive_soc_gpio124_pl0, drive_soc_gpio125_pl1,
86 drive_fan_tach0_pl2, drive_soc_gpio127_pl3,
87 drive_soc_gpio128_pl4, drive_soc_gpio129_pl5,
88 drive_soc_gpio130_pl6, drive_soc_gpio131_pl7,
89 drive_gp_pwm9_pm0, drive_soc_gpio133_pm1,
90 drive_uart9_cts_n_pm5, drive_uart9_rts_n_pm4,
91 drive_uart9_rx_pm3, drive_uart9_tx_pm2,
92 drive_sdmmc1_clk_px0, drive_sdmmc1_cmd_px1,
93 drive_sdmmc1_dat3_px5, drive_sdmmc1_dat2_px4,
94 drive_sdmmc1_dat1_px3, drive_sdmmc1_dat0_px2,
95 drive_qspi0_cs_n_pt1, drive_qspi0_io0_pt2,
96 drive_qspi0_io1_pt3, drive_qspi0_io2_pt4,
97 drive_qspi0_io3_pt5, drive_qspi0_sck_pt0,
98 drive_soc_gpio192_pt6, drive_soc_gpio138_pp0,
99 drive_soc_gpio139_pp1, drive_dap6_din_pp4,
100 drive_dap6_dout_pp3, drive_dap6_fs_pp5,
101 drive_dap6_sclk_pp2, drive_dap4_dout_pp7,
102 drive_dap4_sclk_pp6, drive_dap4_din_pq0,
103 drive_dap4_fs_pq1, drive_spi5_cs0_pq5,
104 drive_spi5_miso_pq3, drive_spi5_mosi_pq4,
105 drive_spi5_sck_pq2, drive_soc_gpio152_pq6,
106 drive_soc_gpio153_pq7, drive_soc_gpio155_pr1,
107 drive_aud_mclk_pr0, drive_dap1_sclk_pr2,
108 drive_dap1_in_pr4, drive_dap1_out_pr3,
109 drive_dap1_fs_pr5, drive_gen11_i2c_scl_pr6,
110 drive_gen11_i2c_sda_pr7, drive_soc_gpio350_ps0,
111 drive_soc_gpio351_ps1, drive_gen0_i2c_scl_pw4,
112 drive_gen0_i2c_sda_pw5, drive_gen1_i2c_scl_pw2,
113 drive_gen1_i2c_sda_pw3, drive_dap2_fs_pw1,
114 drive_dap2_clk_pv6, drive_dap2_din_pv7,
115 drive_dap2_dout_pw0, drive_pwm10_pv1,
116 drive_soc_gpio170_pu0, drive_soc_gpio171_pu1,
117 drive_soc_gpio172_pu2, drive_soc_gpio173_pu3,
118 drive_soc_gpio174_pu4, drive_soc_gpio175_pu5,
119 drive_soc_gpio176_pu6, drive_soc_gpio177_pu7,
120 drive_soc_gpio178_pv0, drive_uart4_cts_n_pv5,
121 drive_uart4_rts_n_pv4, drive_uart4_rx_pv3,
122 drive_uart4_tx_pv2, drive_pwr_i2c_sda_pw7,
123 drive_pwr_i2c_scl_pw6, drive_soc_gpio250_pf0,
124 drive_soc_gpio251_pf1, drive_soc_gpio252_pf2,
125 drive_dp_aux_ch0_hpd_pf3, drive_dp_aux_ch1_hpd_pf4,
126 drive_dp_aux_ch2_hpd_pf5, drive_dp_aux_ch3_hpd_pf6,
127 drive_pwm2_pf7, drive_pwm3_pg0,
128 drive_gen7_i2c_scl_pg1, drive_gen7_i2c_sda_pg2,
129 drive_gen9_i2c_scl_pg3, drive_gen9_i2c_sda_pg4,
130 drive_soc_gpio270_py0, drive_soc_gpio271_py1,
131 drive_soc_gpio272_py2, drive_soc_gpio273_py3,
132 drive_soc_gpio274_py4, drive_soc_gpio275_py5,
133 drive_soc_gpio276_py6, drive_soc_gpio277_py7,
134 drive_soc_gpio278_pz0, drive_soc_gpio279_pz1,
135 drive_soc_gpio282_pz4, drive_soc_gpio283_pz5,
136 drive_soc_gpio284_pz6, drive_soc_gpio285_pz7,
137 drive_soc_gpio286_pal0, drive_soc_gpio287_pal1,
138 drive_soc_gpio288_pal2, drive_xhalt_trig_pz2,
139 drive_soc_gpio281_pz3 ]
140
141required:
142 - compatible
143 - reg
144
145additionalProperties: false
146
147examples:
148 - |
149 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
150
151 pinmux@c281000 {
152 compatible = "nvidia,tegra264-pinmux-main";
153 reg = <0xc281000 0xc000>;
154
155 pinctrl-names = "default";
156 pinctrl-0 = <&state_default>;
157
158 state_default: pinmux-default {
159 sdmmc1 {
160 nvidia,pins = "sdmmc1_clk_px0";
161 nvidia,function = "sdmmc1_cd";
162 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
163 nvidia,tristate = <TEGRA_PIN_DISABLE>;
164 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
165 };
166 };
167 };
Documentation/devicetree/bindings/pinctrl/nvidia,tegra264-pinmux-uphy.yaml+78−0
@@ -0,0 +1,78 @@
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra264-pinmux-uphy.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: NVIDIA Tegra264 UPHY Pinmux Controller
8
9maintainers:
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12
13properties:
14 compatible:
15 const: nvidia,tegra264-pinmux-uphy
16
17 reg:
18 maxItems: 1
19
20patternProperties:
21 "^pinmux(-[a-z0-9-]+)?$":
22 type: object
23
24 # pin groups
25 additionalProperties:
26 $ref: nvidia,tegra264-pinmux-common.yaml
27
28 properties:
29 nvidia,pins:
30 items:
31 enum: [ eth1_mdio_pe0, pex_l4_clkreq_n_pd0, pex_l4_rst_n_pd1,
32 pex_l5_clkreq_n_pd2, pex_l5_rst_n_pd3, eth0_mdio_pd4,
33 eth0_mdc_pd5, eth1_mdc_pe1, eth2_mdio_pe2, eth2_mdc_pe3,
34 eth3_mdio_pd6, eth3_mdc_pd7, pex_l1_clkreq_n_pb0,
35 pex_l1_rst_n_pb1, pex_wake_n_pc2, pex_l2_rst_n_pb3,
36 pex_l2_clkreq_n_pb2, pex_l3_clkreq_n_pb4, pex_l3_rst_n_pb5,
37 sgmii0_sma_mdio_pc0, sgmii0_sma_mdc_pc1, soc_gpio113_pb6,
38 soc_gpio114_pb7, pwm1_pa0, pwm6_pa1, pwm7_pa2, pwm8_pa3,
39 ufs0_ref_clk_pa4, ufs0_rst_n_pa5, drive_eth1_mdio_pe0,
40 drive_pex_l4_clkreq_n_pd0, drive_pex_l4_rst_n_pd1,
41 drive_pex_l5_clkreq_n_pd2, drive_pex_l5_rst_n_pd3,
42 drive_eth0_mdio_pd4, drive_eth0_mdc_pd5, drive_eth1_mdc_pe1,
43 drive_eth2_mdio_pe2, drive_eth2_mdc_pe3, drive_eth3_mdio_pd6,
44 drive_eth3_mdc_pd7, drive_pex_l1_clkreq_n_pb0,
45 drive_pex_l1_rst_n_pb1, drive_pex_wake_n_pc2,
46 drive_pex_l2_rst_n_pb3, drive_pex_l2_clkreq_n_pb2,
47 drive_pex_l3_clkreq_n_pb4, drive_pex_l3_rst_n_pb5,
48 drive_sgmii0_sma_mdio_pc0, drive_sgmii0_sma_mdc_pc1,
49 drive_soc_gpio113_pb6, drive_soc_gpio114_pb7,
50 drive_pwm1_pa0, drive_pwm6_pa1, drive_pwm7_pa2,
51 drive_pwm8_pa3, drive_ufs0_ref_clk_pa4, drive_ufs0_rst_n_pa5 ]
52
53required:
54 - compatible
55 - reg
56
57additionalProperties: false
58
59examples:
60 - |
61 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
62
63 pinmux@82e0000 {
64 compatible = "nvidia,tegra264-pinmux-uphy";
65 reg = <0x82e0000 0x4000>;
66
67 pinctrl-names = "default";
68 pinctrl-0 = <&pinmux_default>;
69
70 pinmux_default: pinmux-default {
71 pex {
72 nvidia,pins = "pex_l1_rst_n_pb1";
73 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
74 nvidia,tristate = <TEGRA_PIN_DISABLE>;
75 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
76 };
77 };
78 };
Documentation/devicetree/bindings/pinctrl/pinctrl-multiplexer.yaml+57−0
@@ -0,0 +1,57 @@
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/pinctrl-multiplexer.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Generic pinctrl device for on-board MUX Chips
8
9maintainers:
10 - Frank Li <Frank.Li@nxp.com>
11
12description:
13 Generic pinctrl device for on-board MUX Chips, which switch SoC signals
14 between different peripherals (e.g. MMC and UART).
15
16 The MUX select lines are often driven by a I2C GPIO expander.
17
18properties:
19 compatible:
20 const: pinctrl-multiplexer
21
22patternProperties:
23 '-grp$':
24 type: object
25 additionalProperties: false
26 properties:
27 mux-states:
28 maxItems: 1
29
30 required:
31 - mux-states
32
33required:
34 - compatible
35
36allOf:
37 - $ref: pinctrl.yaml#
38
39unevaluatedProperties: false
40
41examples:
42 - |
43 pinctrl-mux {
44 compatible = "pinctrl-multiplexer";
45
46 uart-grp {
47 mux-states = <&mux 0>;
48 };
49
50 spi-grp {
51 mux-states = <&mux 1>;
52 };
53
54 i2c-grp {
55 mux-states = <&mux 2>;
56 };
57 };
Documentation/devicetree/bindings/pinctrl/pinctrl.yaml+1−1
@@ -27,7 +27,7 @@ description: | · 26 unmodified lines
27 27
28properties:28properties:
29 $nodename:29 $nodename:
30 pattern: "^(pinctrl|pinmux)(@[0-9a-f]+)?$"30 pattern: "^(pinctrl|pinmux)(@[0-9a-f]+|-[a-z0-9]+)?$"
31 31
32 "#pinctrl-cells":32 "#pinctrl-cells":
33 description: >33 description: >
Documentation/devicetree/bindings/pinctrl/qcom,eliza-tlmm.yaml+16−10
@@ -86,16 +86,22 @@ $defs: · 85 unmodified lines
86 qdss_gpio_tracectl, qdss_gpio_tracedata, qlink_big_enable,86 qdss_gpio_tracectl, qdss_gpio_tracedata, qlink_big_enable,
87 qlink_big_request, qlink_little_enable,87 qlink_big_request, qlink_little_enable,
88 qlink_little_request, qlink_wmss, qspi0, qspi_clk,88 qlink_little_request, qlink_wmss, qspi0, qspi_clk,
89 qspi_cs, qup1_se0, qup1_se1, qup1_se2, qup1_se3, qup1_se4,89 qspi_cs, qup1_se0, qup1_se1, qup1_se2, qup1_se2_l2_mira,
90 qup1_se5, qup1_se6, qup1_se7, qup2_se0, qup2_se1,90 qup1_se2_l2_mirb, qup1_se2_l3_mira, qup1_se2_l3_mirb,
91 qup2_se2, qup2_se3, qup2_se4, qup2_se5, qup2_se6,91 qup1_se3, qup1_se4_01, qup1_se4_23,
92 qup2_se7, resout_gpio, sd_write_protect, sdc1, sdc2,92 qup1_se5, qup1_se6, qup1_se6_l1_mira,
93 sdc2_fb_clk, tb_trig_sdc1, tb_trig_sdc2, tmess_prng0,93 qup1_se6_l1_mirb, qup1_se6_l3_mira, qup1_se6_l3_mirb,
94 tmess_prng1, tmess_prng2, tmess_prng3, tsense_pwm1,94 qup1_se7, qup1_se7_l0_mira, qup1_se7_l0_mirb,
95 tsense_pwm2, tsense_pwm3, tsense_pwm4, uim0_clk,95 qup1_se7_l1_mira, qup1_se7_l1_mirb, qup2_se0, qup2_se1,
96 uim0_data, uim0_present, uim0_reset, uim1_clk, uim1_data,96 qup2_se2, qup2_se3, qup2_se3_l0_mira, qup2_se3_l0_mirb,
97 uim1_present, uim1_reset, usb0_hs, usb_phy, vfr_0, vfr_1,97 qup2_se3_l1_mira, qup2_se3_l1_mirb, qup2_se4, qup2_se5,
98 vsense_trigger_mirnat, wcn_sw_ctrl ]98 qup2_se6, qup2_se7, resout_gpio, sd_write_protect, sdc1,
99 sdc2, sdc2_fb_clk, tb_trig_sdc1, tb_trig_sdc2,
100 tmess_prng0, tmess_prng1, tmess_prng2, tmess_prng3,
101 tsense_pwm1, tsense_pwm2, tsense_pwm3, tsense_pwm4,
102 uim0_clk, uim0_data, uim0_present, uim0_reset, uim1_clk,
103 uim1_data, uim1_present, uim1_reset, usb0_hs, usb_phy,
104 vfr_0, vfr_1, vsense_trigger_mirnat, wcn_sw_ctrl ]
99 required:105 required:
100 - pins106 - pins
101 107
Documentation/devicetree/bindings/pinctrl/qcom,ipq4019-pinctrl.yaml+0−5
@@ -36,11 +36,6 @@ patternProperties: · 35 unmodified lines
36 $ref: "#/$defs/qcom-ipq4019-tlmm-state"36 $ref: "#/$defs/qcom-ipq4019-tlmm-state"
37 additionalProperties: false37 additionalProperties: false
38 38
39 "-hog(-[0-9]+)?$":
40 type: object
41 required:
42 - gpio-hog
43
44$defs:39$defs:
45 qcom-ipq4019-tlmm-state:40 qcom-ipq4019-tlmm-state:
46 type: object41 type: object
Documentation/devicetree/bindings/pinctrl/qcom,ipq9650-tlmm.yaml+118−0
@@ -0,0 +1,118 @@
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/qcom,ipq9650-tlmm.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm IPQ9650 TLMM pin controller
8
9maintainers:
10 - Bjorn Andersson <andersson@kernel.org>
11 - Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
12
13description:
14 Top Level Mode Multiplexer pin controller in Qualcomm IPQ9650 SoC.
15
16allOf:
17 - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
18
19properties:
20 compatible:
21 const: qcom,ipq9650-tlmm
22
23 reg:
24 maxItems: 1
25
26 interrupts:
27 maxItems: 1
28
29 gpio-reserved-ranges:
30 minItems: 1
31 maxItems: 27
32
33 gpio-line-names:
34 maxItems: 54
35
36patternProperties:
37 "-state$":
38 oneOf:
39 - $ref: "#/$defs/qcom-ipq9650-tlmm-state"
40 - patternProperties:
41 "-pins$":
42 $ref: "#/$defs/qcom-ipq9650-tlmm-state"
43 additionalProperties: false
44
45$defs:
46 qcom-ipq9650-tlmm-state:
47 type: object
48 description:
49 Pinctrl node's client devices use subnodes for desired pin configuration.
50 Client device subnodes use below standard properties.
51 $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
52 unevaluatedProperties: false
53
54 properties:
55 pins:
56 description:
57 List of gpio pins affected by the properties specified in this
58 subnode.
59 items:
60 pattern: "^gpio([0-9]|[1-4][0-9]|5[0-3])$"
61 minItems: 1
62 maxItems: 36
63
64 function:
65 description:
66 Specify the alternative function to be configured for the specified
67 pins.
68
69 enum: [ atest_char_start, atest_char_status0, atest_char_status1,
70 atest_char_status2, atest_char_status3, atest_tic_en,
71 audio_pri_mclk_in0, audio_pri_mclk_out0, audio_pri_mclk_in1,
72 audio_pri_mclk_out1, audio_pri, audio_sec, audio_sec_mclk_in0,
73 audio_sec_mclk_out0, audio_sec_mclk_in1, audio_sec_mclk_out1,
74 core_voltage_0, core_voltage_1, core_voltage_2, core_voltage_3,
75 core_voltage_4, cri_rng0, cri_rng1, cri_rng2, dbg_out_clk,
76 gcc_plltest_bypassnl, gcc_plltest_resetn, gcc_tlmm, gpio,
77 mdc_mst, mdc_slv0, mdc_slv1, mdio_mst, mdio_slv, mdio_slv0,
78 mdio_slv1, pcie0_clk_req_n, pcie0_wake, pcie1_clk_req_n,
79 pcie1_wake, pcie2_clk_req_n, pcie2_wake, pcie3_clk_req_n,
80 pcie3_wake, pcie4_clk_req_n, pcie4_wake, pll_bist_sync,
81 pll_test, pwm, qdss_cti_trig_in_a0, qdss_cti_trig_in_a1,
82 qdss_cti_trig_in_b0, qdss_cti_trig_in_b1, qdss_cti_trig_out_a0,
83 qdss_cti_trig_out_a1, qdss_cti_trig_out_b0, qdss_cti_trig_out_b1,
84 qdss_traceclk_a, qdss_tracectl_a, qdss_tracedata_a, qspi_data,
85 qspi_clk, qspi_cs_n, qup_se0, qup_se1, qup_se2, qup_se3,
86 qup_se4, qup_se5, qup_se6, qup_se7, resout, rx_los0, rx_los1,
87 rx_los2, sdc_clk, sdc_cmd, sdc_data, tsens_max, tsn ]
88
89 required:
90 - pins
91
92required:
93 - compatible
94 - reg
95
96unevaluatedProperties: false
97
98examples:
99 - |
100 #include <dt-bindings/interrupt-controller/arm-gic.h>
101
102 tlmm: pinctrl@1000000 {
103 compatible = "qcom,ipq9650-tlmm";
104 reg = <0x01000000 0x300000>;
105 gpio-controller;
106 #gpio-cells = <2>;
107 gpio-ranges = <&tlmm 0 0 54>;
108 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
109 interrupt-controller;
110 #interrupt-cells = <2>;
111
112 qup-uart1-default-state {
113 pins = "gpio43", "gpio44";
114 function = "qup_se6";
115 drive-strength = <8>;
116 bias-pull-down;
117 };
118 };
Documentation/devicetree/bindings/pinctrl/qcom,nord-tlmm.yaml+141−0
@@ -0,0 +1,141 @@
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/qcom,nord-tlmm.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Technologies, Inc. SA8797P TLMM block
8
9maintainers:
10 - Bartosz Golaszewski <brgl@kernel.org>
11
12description:
13 Top Level Mode Multiplexer pin controller in Qualcomm SA8797P SoC.
14
15allOf:
16 - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
17
18properties:
19 compatible:
20 const: qcom,nord-tlmm
21
22 reg:
23 maxItems: 1
24
25 interrupts:
26 maxItems: 1
27
28 gpio-reserved-ranges:
29 minItems: 1
30 maxItems: 90
31
32 gpio-line-names:
33 maxItems: 181
34
35patternProperties:
36 "-state$":
37 oneOf:
38 - $ref: "#/$defs/qcom-nord-tlmm-state"
39 - patternProperties:
40 "-pins$":
41 $ref: "#/$defs/qcom-nord-tlmm-state"
42 additionalProperties: false
43
44$defs:
45 qcom-nord-tlmm-state:
46 type: object
47 description:
48 Pinctrl node's client devices use subnodes for desired pin configuration.
49 Client device subnodes use below standard properties.
50 $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
51 unevaluatedProperties: false
52
53 properties:
54 pins:
55 description:
56 List of gpio pins affected by the properties specified in this
57 subnode.
58 items:
59 oneOf:
60 - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-7][0-9]|180)$"
61 - enum: [ ufs_reset ]
62 minItems: 1
63 maxItems: 16
64
65 function:
66 description:
67 Specify the alternative function to be configured for the specified
68 pins.
69
70 enum: [ aoss_cti, atest_char, atest_usb20, atest_usb21,
71 aud_intfc0_clk, aud_intfc0_data, aud_intfc0_ws,
72 aud_intfc10_clk, aud_intfc10_data, aud_intfc10_ws,
73 aud_intfc1_clk, aud_intfc1_data, aud_intfc1_ws,
74 aud_intfc2_clk, aud_intfc2_data, aud_intfc2_ws,
75 aud_intfc3_clk, aud_intfc3_data, aud_intfc3_ws,
76 aud_intfc4_clk, aud_intfc4_data, aud_intfc4_ws,
77 aud_intfc5_clk, aud_intfc5_data, aud_intfc5_ws,
78 aud_intfc6_clk, aud_intfc6_data, aud_intfc6_ws,
79 aud_intfc7_clk, aud_intfc7_data, aud_intfc7_ws,
80 aud_intfc8_clk, aud_intfc8_data, aud_intfc8_ws,
81 aud_intfc9_clk, aud_intfc9_data, aud_intfc9_ws,
82 aud_mclk0_mira, aud_mclk0_mirb, aud_mclk1_mira, aud_mclk1_mirb,
83 aud_mclk2_mira, aud_mclk2_mirb, aud_refclk0, aud_refclk1,
84 bist_done, ccu_async_in, ccu_i2c_scl, ccu_i2c_sda, ccu_timer,
85 clink_debug, dbg_out, dbg_out_clk,
86 ddr_bist_complete, ddr_bist_fail, ddr_bist_start, ddr_bist_stop,
87 ddr_pxi, dp_rx0, dp_rx00, dp_rx01, dp_rx0_mute, dp_rx1, dp_rx10,
88 dp_rx11, dp_rx1_mute,
89 edp0_hot, edp0_lcd, edp1_hot, edp1_lcd, edp2_hot, edp2_lcd,
90 edp3_hot, edp3_lcd,
91 emac0_mcg, emac0_mdc, emac0_mdio, emac0_ptp, emac1_mcg,
92 emac1_mdc, emac1_mdio, emac1_ptp,
93 gcc_gp1_clk, gcc_gp2_clk, gcc_gp3_clk, gcc_gp4_clk, gcc_gp5_clk,
94 gcc_gp6_clk, gcc_gp7_clk, gcc_gp8_clk, jitter_bist, lbist_pass,
95 mbist_pass, mdp0_vsync_out, mdp1_vsync_out, mdp_vsync_e,
96 mdp_vsync_p, mdp_vsync_s,
97 pcie0_clk_req_n, pcie1_clk_req_n, pcie2_clk_req_n,
98 pcie3_clk_req_n, phase_flag, pll_bist_sync, pll_clk_aux,
99 prng_rosc0, prng_rosc1, pwrbrk_i_n, qdss, qdss_cti, qspi,
100 qup0_se0, qup0_se1, qup0_se2, qup0_se3, qup0_se4, qup0_se5,
101 qup1_se0, qup1_se1, qup1_se3, qup1_se2, qup1_se4, qup1_se5,
102 qup1_se6, qup2_se0, qup2_se1, qup2_se2, qup2_se3, qup2_se4,
103 qup2_se5, qup2_se6,
104 sailss_ospi, sdc4_clk, sdc4_cmd, sdc4_data, smb_alert,
105 smb_alert_n, smb_clk, smb_dat, tb_trig_sdc4, tmess_prng0,
106 tmess_prng1, tsc_timer, tsense_pwm, usb0_hs,
107 usb0_phy_ps, usb1_hs, usb1_phy_ps, usb2_hs, usxgmii0_phy,
108 usxgmii1_phy, vsense_trigger_mirnat, wcn_sw, wcn_sw_ctrl]
109
110 required:
111 - pins
112
113required:
114 - compatible
115 - reg
116
117unevaluatedProperties: false
118
119examples:
120 - |
121 #include <dt-bindings/interrupt-controller/arm-gic.h>
122
123 tlmm: pinctrl@f100000 {
124 compatible = "qcom,nord-tlmm";
125 reg = <0x0f100000 0xc0000>;
126 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
127 gpio-controller;
128 #gpio-cells = <2>;
129 interrupt-controller;
130 #interrupt-cells = <2>;
131 gpio-ranges = <&tlmm 0 0 181>;
132 wakeup-parent = <&pdc>;
133
134 qup_uart15_default: qup-uart15-default-state {
135 pins = "gpio147", "gpio148";
136 function = "qup2_se2";
137 drive-strength = <2>;
138 bias-disable;
139 };
140 };
141...
Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml+3−0
@@ -30,6 +30,7 @@ properties: · 29 unmodified lines
30 - qcom,pm7550-gpio30 - qcom,pm7550-gpio
31 - qcom,pm7550ba-gpio31 - qcom,pm7550ba-gpio
32 - qcom,pm8005-gpio32 - qcom,pm8005-gpio
33 - qcom,pm8010-gpio
33 - qcom,pm8018-gpio34 - qcom,pm8018-gpio
34 - qcom,pm8019-gpio35 - qcom,pm8019-gpio
35 - qcom,pm8038-gpio36 - qcom,pm8038-gpio
@@ -134,6 +135,7 @@ allOf: · 98 unmodified lines
134 compatible:135 compatible:
135 contains:136 contains:
136 enum:137 enum:
138 - qcom,pm8010-gpio
137 - qcom,pmi8950-gpio139 - qcom,pmi8950-gpio
138 - qcom,pmr735d-gpio140 - qcom,pmr735d-gpio
139 then:141 then:
@@ -465,6 +467,7 @@ $defs: · 325 unmodified lines
465 - gpio1-gpio10 for pm7325467 - gpio1-gpio10 for pm7325
466 - gpio1-gpio8 for pm7550ba468 - gpio1-gpio8 for pm7550ba
467 - gpio1-gpio4 for pm8005469 - gpio1-gpio4 for pm8005
470 - gpio1-gpio2 for pm8010
468 - gpio1-gpio6 for pm8018471 - gpio1-gpio6 for pm8018
469 - gpio1-gpio12 for pm8038472 - gpio1-gpio12 for pm8038
470 - gpio1-gpio40 for pm8058473 - gpio1-gpio40 for pm8058
Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.yaml+0−5
@@ -42,11 +42,6 @@ patternProperties: · 41 unmodified lines
42 $ref: "#/$defs/qcom-sdm845-tlmm-state"42 $ref: "#/$defs/qcom-sdm845-tlmm-state"
43 additionalProperties: false43 additionalProperties: false
44 44
45 "-hog(-[0-9]+)?$":
46 type: object
47 required:
48 - gpio-hog
49
50$defs:45$defs:
51 qcom-sdm845-tlmm-state:46 qcom-sdm845-tlmm-state:
52 type: object47 type: object
Documentation/devicetree/bindings/pinctrl/qcom,shikra-tlmm.yaml+123−0
@@ -0,0 +1,123 @@
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/qcom,shikra-tlmm.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Technologies, Inc. Shikra TLMM block
8
9maintainers:
10 - Komal Bajaj <komal.bajaj@oss.qualcomm.com>
11
12description: |
13 Top Level Mode Multiplexer pin controller in Qualcomm Shikra SoC.
14
15allOf:
16 - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
17
18properties:
19 compatible:
20 const: qcom,shikra-tlmm
21
22 reg:
23 maxItems: 1
24
25 interrupts:
26 maxItems: 1
27
28 gpio-reserved-ranges:
29 minItems: 1
30 maxItems: 83
31
32 gpio-line-names:
33 maxItems: 166
34
35patternProperties:
36 "-state$":
37 oneOf:
38 - $ref: "#/$defs/qcom-shikra-tlmm-state"
39 - patternProperties:
40 "-pins$":
41 $ref: "#/$defs/qcom-shikra-tlmm-state"
42 additionalProperties: false
43
44$defs:
45 qcom-shikra-tlmm-state:
46 type: object
47 description:
48 Pinctrl node's client devices use subnodes for desired pin configuration.
49 Client device subnodes use below standard properties.
50 $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
51 unevaluatedProperties: false
52
53 properties:
54 pins:
55 description:
56 List of gpio pins affected by the properties specified in this
57 subnode.
58 items:
59 oneOf:
60 - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-5][0-9]|16[0-5])$"
61 - enum: [ sdc1_rclk, sdc1_clk, sdc1_cmd, sdc1_data,
62 sdc2_clk, sdc2_cmd, sdc2_data ]
63 minItems: 1
64 maxItems: 36
65
66 function:
67 description:
68 Specify the alternative function to be configured for the specified
69 pins.
70
71 enum: [ gpio, agera_pll, atest_bbrx, atest_char, atest_gpsadc,
72 atest_tsens, atest_usb, cam_mclk, cci_async, cci_i2c0,
73 cci_i2c1, cci_timer, char_exec, cri_trng, dac_calib,
74 dbg_out_clk, ddr_bist, ddr_pxi, dmic, emac_dll, emac_mcg,
75 emac_phy, emac0_ptp_aux, emac0_ptp_pps, emac1_ptp_aux,
76 emac1_ptp_pps, ext_mclk, gcc_gp, gsm0_tx, i2s0, i2s1,
77 i2s2, i2s3, jitter_bist, m_voc, mdp_vsync_e, mdp_vsync_out0,
78 mdp_vsync_out1, mdp_vsync_p, mdp_vsync_s, mpm_pwr, mss_lte,
79 nav_gpio, pa_indicator_or, pbs_in, pbs_out, pcie0_clk_req_n,
80 phase_flag, pll, prng_rosc, pwm, qdss_cti, qup0_se0,
81 qup0_se1, qup0_se1_01, qup0_se1_23, qup0_se2, qup0_se3_01,
82 qup0_se3_23, qup0_se4_01, qup0_se4_23, qup0_se5, qup0_se6,
83 qup0_se7_01, qup0_se7_23, qup0_se8, qup0_se9, qup0_se9_01,
84 qup0_se9_23, rgmii, sd_write_protect, sdc_cdc, sdc_tb_trig,
85 ssbi_wtr, swr0_rx, swr0_tx, tgu_ch_trigout, tsc_async,
86 tsense_pwm, uim1, uim2, unused_adsp, unused_gsm1, usb0_phy_ps,
87 vfr, vsense_trigger_mirnat, wlan ]
88
89 required:
90 - pins
91
92required:
93 - compatible
94 - reg
95
96unevaluatedProperties: false
97
98examples:
99 - |
100 #include <dt-bindings/interrupt-controller/arm-gic.h>
101
102 tlmm: pinctrl@500000 {
103 compatible = "qcom,shikra-tlmm";
104 reg = <0x00500000 0x800000>;
105
106 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
107
108 gpio-controller;
109 #gpio-cells = <2>;
110
111 interrupt-controller;
112 #interrupt-cells = <2>;
113
114 gpio-ranges = <&tlmm 0 0 166>;
115
116 qup-uart0-default-state {
117 pins = "gpio0", "gpio1";
118 function = "qup0_se1";
119 drive-strength = <2>;
120 bias-disable;
121 };
122 };
123...
Documentation/devicetree/bindings/pinctrl/qcom,sm6350-lpass-lpi-pinctrl.yaml+124−0
@@ -0,0 +1,124 @@
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/qcom,sm6350-lpass-lpi-pinctrl.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm SM6350 SoC LPASS LPI TLMM
8
9maintainers:
10 - Luca Weiss <luca.weiss@fairphone.com>
11
12description:
13 Top Level Mode Multiplexer pin controller in the Low Power Audio SubSystem
14 (LPASS) Low Power Island (LPI) of Qualcomm SM6350 SoC.
15
16properties:
17 compatible:
18 const: qcom,sm6350-lpass-lpi-pinctrl
19
20 reg:
21 items:
22 - description: LPASS LPI TLMM Control and Status registers
23 - description: LPASS LPI MCC registers
24
25 clocks:
26 items:
27 - description: LPASS Core voting clock
28 - description: LPASS Audio voting clock
29
30 clock-names:
31 items:
32 - const: core
33 - const: audio
34
35patternProperties:
36 "-state$":
37 oneOf:
38 - $ref: "#/$defs/qcom-sm6350-lpass-state"
39 - patternProperties:
40 "-pins$":
41 $ref: "#/$defs/qcom-sm6350-lpass-state"
42 additionalProperties: false
43
44$defs:
45 qcom-sm6350-lpass-state:
46 type: object
47 description:
48 Pinctrl node's client devices use subnodes for desired pin configuration.
49 Client device subnodes use below standard properties.
50 $ref: qcom,lpass-lpi-common.yaml#/$defs/qcom-tlmm-state
51 unevaluatedProperties: false
52
53 properties:
54 pins:
55 description:
56 List of gpio pins affected by the properties specified in this
57 subnode.
58 items:
59 pattern: "^gpio([0-9]|1[0-4])$"
60
61 function:
62 enum: [ dmic1_clk, dmic1_data, dmic2_clk, dmic2_data, dmic3_clk,
63 dmic3_data, gpio, i2s1_clk, i2s1_data, i2s1_ws, i2s2_clk,
64 i2s2_data, i2s2_ws, qua_mi2s_data, qua_mi2s_sclk, qua_mi2s_ws,
65 swr_rx_clk, swr_rx_data, swr_tx_clk, swr_tx_data, wsa_swr_clk,
66 wsa_swr_data ]
67 description:
68 Specify the alternative function to be configured for the specified
69 pins.
70
71allOf:
72 - $ref: qcom,lpass-lpi-common.yaml#
73
74required:
75 - compatible
76 - reg
77 - clocks
78 - clock-names
79
80unevaluatedProperties: false
81
82examples:
83 - |
84 #include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
85
86 lpass_tlmm: pinctrl@33c0000 {
87 compatible = "qcom,sm6350-lpass-lpi-pinctrl";
88 reg = <0x033c0000 0x20000>,
89 <0x03550000 0x10000>;
90 gpio-controller;
91 #gpio-cells = <2>;
92 gpio-ranges = <&lpass_tlmm 0 0 15>;
93
94 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
95 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
96 clock-names = "core",
97 "audio";
98
99 i2s1_active: i2s1-active-state {
100 clk-pins {
101 pins = "gpio6";
102 function = "i2s1_clk";
103 drive-strength = <8>;
104 bias-disable;
105 output-high;
106 };
107
108 ws-pins {
109 pins = "gpio7";
110 function = "i2s1_ws";
111 drive-strength = <8>;
112 bias-disable;
113 output-high;
114 };
115
116 data-pins {
117 pins = "gpio8", "gpio9";
118 function = "i2s1_data";
119 drive-strength = <8>;
120 bias-disable;
121 output-high;
122 };
123 };
124 };
Documentation/devicetree/bindings/pinctrl/qcom,tlmm-common.yaml+6−0
@@ -51,6 +51,12 @@ properties: · 50 unmodified lines
51 should not be accessed by the OS. Please see the ../gpio/gpio.txt for more51 should not be accessed by the OS. Please see the ../gpio/gpio.txt for more
52 information.52 information.
53 53
54patternProperties:
55 "-hog(-[0-9]+)?$":
56 type: object
57 required:
58 - gpio-hog
59
54allOf:60allOf:
55 - $ref: pinctrl.yaml#61 - $ref: pinctrl.yaml#
56 62
Documentation/devicetree/bindings/pinctrl/realtek,rtd1625-pinctrl.yaml+1−1
@@ -110,7 +110,7 @@ patternProperties: · 109 unmodified lines
110 110
111 input-schmitt-disable: true111 input-schmitt-disable: true
112 112
113 input-voltage-microvolt:113 input-threshold-voltage-microvolt:
114 description: |114 description: |
115 Select the input receiver voltage domain for the pin.115 Select the input receiver voltage domain for the pin.
116 Valid arguments are:116 Valid arguments are:
Documentation/devicetree/bindings/pinctrl/ultrarisc,dp1000-pinctrl.yaml+130−0
@@ -0,0 +1,130 @@
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/ultrarisc,dp1000-pinctrl.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: UltraRISC DP1000 Pin Controller
8
9maintainers:
10 - Jia Wang <wangjia@ultrarisc.com>
11
12description: |
13 UltraRISC RISC-V SoC DP1000 pin controller.
14 The controller manages ports A, B, C, D and LPC. Ports A-D default to
15 GPIO and provide additional SPI, UART, I2C, and PWM mux functions.
16 LPC pins default to the LPC interface and can be muxed to eSPI.
17 All pins also support pin configuration, including drive strength,
18 pull-up, and pull-down settings.
19
20properties:
21 compatible:
22 const: ultrarisc,dp1000-pinctrl
23
24 reg:
25 items:
26 - description: pin controller registers
27
28required:
29 - compatible
30 - reg
31
32patternProperties:
33 '.*-pins$':
34 type: object
35 unevaluatedProperties: false
36 allOf:
37 - $ref: /schemas/pinctrl/pincfg-node.yaml#
38 - $ref: /schemas/pinctrl/pinmux-node.yaml#
39 - if:
40 properties:
41 pins:
42 items:
43 minimum: 40
44 maximum: 52
45 then:
46 properties:
47 function:
48 enum:
49 - lpc
50 - espi
51 else:
52 properties:
53 pins:
54 items:
55 maximum: 39
56 function:
57 enum:
58 - gpio
59 - i2c
60 - pwm
61 - spi
62 - uart
63
64 properties:
65 pins:
66 description: |
67 List of pins affected by this state node, using numeric pin IDs.
68 Pins 0-39 correspond to ports A-D, and pins 40-52 correspond
69 to LPC0-LPC12.
70 $ref: /schemas/types.yaml#/definitions/uint32-array
71 minItems: 1
72 uniqueItems: true
73 items:
74 minimum: 0
75 maximum: 52
76
77 function:
78 description: |
79 Mux function to select for the listed pins. Supported functions
80 depend on the selected pins and match the DP1000 hardware mux
81 table.
82 enum:
83 - gpio
84 - i2c
85 - pwm
86 - spi
87 - uart
88 - lpc
89 - espi
90
91 bias-disable: true
92 bias-high-impedance: true
93 bias-pull-up: true
94 bias-pull-down: true
95
96 drive-strength:
97 description: Output drive strength in mA.
98 enum: [20, 27, 33, 40]
99
100 required:
101 - pins
102 - function
103
104unevaluatedProperties: false
105
106examples:
107 - |
108 soc {
109 #address-cells = <2>;
110 #size-cells = <2>;
111
112 pinctrl@11081000 {
113 compatible = "ultrarisc,dp1000-pinctrl";
114 reg = <0x0 0x11081000 0x0 0x1000>;
115
116 i2c0-pins {
117 pins = <12 13>;
118 function = "i2c";
119 bias-pull-up;
120 drive-strength = <33>;
121 };
122
123 uart0-pins {
124 pins = <8 9>;
125 function = "uart";
126 bias-pull-up;
127 drive-strength = <33>;
128 };
129 };
130 };
MAINTAINERS+9−1
@@ -21154,7 +21154,7 @@ M: Lorenzo Bianconi <lorenzo@kernel.org> · 21153 unmodified lines
21154L: linux-mediatek@lists.infradead.org (moderated for non-subscribers)21154L: linux-mediatek@lists.infradead.org (moderated for non-subscribers)
21155S: Maintained21155S: Maintained
21156F: Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml21156F: Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml
21157F: drivers/pinctrl/mediatek/pinctrl-airoha.c21157F: drivers/pinctrl/airoha/pinctrl-airoha.c
21158 21158
21159PIN CONTROLLER - AMD21159PIN CONTROLLER - AMD
21160M: Basavaraj Natikar <Basavaraj.Natikar@amd.com>21160M: Basavaraj Natikar <Basavaraj.Natikar@amd.com>
@@ -21246,6 +21246,7 @@ F: drivers/pinctrl/renesas/ · 85 unmodified lines
21246PIN CONTROLLER - SAMSUNG21246PIN CONTROLLER - SAMSUNG
21247M: Krzysztof Kozlowski <krzk@kernel.org>21247M: Krzysztof Kozlowski <krzk@kernel.org>
21248M: Sylwester Nawrocki <s.nawrocki@samsung.com>21248M: Sylwester Nawrocki <s.nawrocki@samsung.com>
21249M: Peter Griffin <peter.griffin@linaro.org>
21249R: Alim Akhtar <alim.akhtar@samsung.com>21250R: Alim Akhtar <alim.akhtar@samsung.com>
21250L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)21251L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
21251L: linux-samsung-soc@vger.kernel.org21252L: linux-samsung-soc@vger.kernel.org
@@ -27524,6 +27525,13 @@ S: Maintained · 6272 unmodified lines
27524F: drivers/usb/common/ulpi.c27525F: drivers/usb/common/ulpi.c
27525F: include/linux/ulpi/27526F: include/linux/ulpi/
27526 27527
27528ULTRARISC DP1000 PINCTRL DRIVER
27529M: Jia Wang <wangjia@ultrarisc.com>
27530L: linux-gpio@vger.kernel.org
27531S: Maintained
27532F: Documentation/devicetree/bindings/pinctrl/ultrarisc,dp1000-pinctrl.yaml
27533F: drivers/pinctrl/ultrarisc/*
27534
27527ULTRATRONIK BOARD SUPPORT27535ULTRATRONIK BOARD SUPPORT
27528M: Goran Rađenović <goran.radni@gmail.com>27536M: Goran Rađenović <goran.radni@gmail.com>
27529M: Börge Strümpfel <boerge.struempfel@gmail.com>27537M: Börge Strümpfel <boerge.struempfel@gmail.com>
drivers/mux/core.c+27−16
@@ -533,14 +533,16 @@ static struct mux_chip *of_find_mux_chip_by_node(struct device_node *np) · 532 unmodified lines
533 * @state: Pointer to where the requested state is returned, or NULL when533 * @state: Pointer to where the requested state is returned, or NULL when
534 * the required multiplexer states are handled by other means.534 * the required multiplexer states are handled by other means.
535 * @optional: Whether to return NULL and silence errors when mux doesn't exist.535 * @optional: Whether to return NULL and silence errors when mux doesn't exist.
536 * @node: the device nodes, use dev->of_node if it is NULL.
536 *537 *
537 * Return: Pointer to the mux-control on success, an ERR_PTR with a negative538 * Return: Pointer to the mux-control on success, an ERR_PTR with a negative
538 * errno on error, or NULL if optional is true and mux doesn't exist.539 * errno on error, or NULL if optional is true and mux doesn't exist.
539 */540 */
540static struct mux_control *mux_get(struct device *dev, const char *mux_name,541static struct mux_control *mux_get(struct device *dev, const char *mux_name,
541 unsigned int *state, bool optional)542 unsigned int *state, bool optional,
543 struct device_node *node)
542{544{
543 struct device_node *np = dev->of_node;545 struct device_node *np = node ? node : dev->of_node;
544 struct of_phandle_args args;546 struct of_phandle_args args;
545 struct mux_chip *mux_chip;547 struct mux_chip *mux_chip;
546 unsigned int controller;548 unsigned int controller;
@@ -635,7 +637,7 @@ static struct mux_control *mux_get(struct device *dev, const char *mux_name, · 88 unmodified lines
635 */637 */
636struct mux_control *mux_control_get(struct device *dev, const char *mux_name)638struct mux_control *mux_control_get(struct device *dev, const char *mux_name)
637{639{
638 struct mux_control *mux = mux_get(dev, mux_name, NULL, false);640 struct mux_control *mux = mux_get(dev, mux_name, NULL, false, NULL);
639 641
640 if (!mux)642 if (!mux)
641 return ERR_PTR(-ENOENT);643 return ERR_PTR(-ENOENT);
@@ -654,7 +656,7 @@ EXPORT_SYMBOL_GPL(mux_control_get); · 12 unmodified lines
654 */656 */
655struct mux_control *mux_control_get_optional(struct device *dev, const char *mux_name)657struct mux_control *mux_control_get_optional(struct device *dev, const char *mux_name)
656{658{
657 return mux_get(dev, mux_name, NULL, true);659 return mux_get(dev, mux_name, NULL, true, NULL);
658}660}
659EXPORT_SYMBOL_GPL(mux_control_get_optional);661EXPORT_SYMBOL_GPL(mux_control_get_optional);
660 662
@@ -712,11 +714,14 @@ EXPORT_SYMBOL_GPL(devm_mux_control_get); · 51 unmodified lines
712 * @dev: The device that needs a mux-state.714 * @dev: The device that needs a mux-state.
713 * @mux_name: The name identifying the mux-state.715 * @mux_name: The name identifying the mux-state.
714 * @optional: Whether to return NULL and silence errors when mux doesn't exist.716 * @optional: Whether to return NULL and silence errors when mux doesn't exist.
717 * @np: the device nodes, use dev->of_node if it is NULL.
715 *718 *
716 * Return: Pointer to the mux-state on success, an ERR_PTR with a negative719 * Return: Pointer to the mux-state on success, an ERR_PTR with a negative
717 * errno on error, or NULL if optional is true and mux doesn't exist.720 * errno on error, or NULL if optional is true and mux doesn't exist.
718 */721 */
719static struct mux_state *mux_state_get(struct device *dev, const char *mux_name, bool optional)722static struct mux_state *
723mux_state_get(struct device *dev, const char *mux_name, bool optional,
724 struct device_node *np)
720{725{
721 struct mux_state *mstate;726 struct mux_state *mstate;
722 727
@@ -724,7 +729,7 @@ static struct mux_state *mux_state_get(struct device *dev, const char *mux_name, · 1 unmodified line
724 if (!mstate)729 if (!mstate)
725 return ERR_PTR(-ENOMEM);730 return ERR_PTR(-ENOMEM);
726 731
727 mstate->mux = mux_get(dev, mux_name, &mstate->state, optional);732 mstate->mux = mux_get(dev, mux_name, &mstate->state, optional, np);
728 if (IS_ERR(mstate->mux)) {733 if (IS_ERR(mstate->mux)) {
729 int err = PTR_ERR(mstate->mux);734 int err = PTR_ERR(mstate->mux);
730 735
@@ -766,6 +771,7 @@ static void devm_mux_state_release(struct device *dev, void *res) · 35 unmodified lines
766 * @dev: The device that needs a mux-state.771 * @dev: The device that needs a mux-state.
767 * @mux_name: The name identifying the mux-state.772 * @mux_name: The name identifying the mux-state.
768 * @optional: Whether to return NULL and silence errors when mux doesn't exist.773 * @optional: Whether to return NULL and silence errors when mux doesn't exist.
774 * @np: The device nodes, use dev->of_node if it is NULL.
769 * @init: Optional function pointer for mux-state object initialisation.775 * @init: Optional function pointer for mux-state object initialisation.
770 * @exit: Optional function pointer for mux-state object cleanup on release.776 * @exit: Optional function pointer for mux-state object cleanup on release.
771 *777 *
@@ -773,7 +779,7 @@ static void devm_mux_state_release(struct device *dev, void *res) · 1 unmodified line
773 * errno on error, or NULL if optional is true and mux doesn't exist.779 * errno on error, or NULL if optional is true and mux doesn't exist.
774 */780 */
775static struct mux_state *__devm_mux_state_get(struct device *dev, const char *mux_name,781static struct mux_state *__devm_mux_state_get(struct device *dev, const char *mux_name,
776 bool optional,782 bool optional, struct device_node *np,
777 int (*init)(struct mux_state *mstate),783 int (*init)(struct mux_state *mstate),
778 int (*exit)(struct mux_state *mstate))784 int (*exit)(struct mux_state *mstate))
779{785{
@@ -781,7 +787,7 @@ static struct mux_state *__devm_mux_state_get(struct device *dev, const char *mu · 1 unmodified line
781 struct mux_state *mstate;787 struct mux_state *mstate;
782 int ret;788 int ret;
783 789
784 mstate = mux_state_get(dev, mux_name, optional);790 mstate = mux_state_get(dev, mux_name, optional, np);
785 if (IS_ERR(mstate))791 if (IS_ERR(mstate))
786 return ERR_CAST(mstate);792 return ERR_CAST(mstate);
787 else if (optional && !mstate)793 else if (optional && !mstate)
@@ -815,20 +821,23 @@ err_devres_alloc: · 27 unmodified lines
815}821}
816 822
817/**823/**
818 * devm_mux_state_get() - Get the mux-state for a device, with resource824 * devm_mux_state_get_from_np() - Get the mux-state for a device, with resource
819 * management.825 * management.
820 * @dev: The device that needs a mux-control.826 * @dev: The device that needs a mux-control.
821 * @mux_name: The name identifying the mux-control.827 * @mux_name: The name identifying the mux-control.
828 * @np: the device nodes, use dev->of_node if it is NULL.
822 *829 *
823 * Return: Pointer to the mux-state, or an ERR_PTR with a negative errno.830 * Return: Pointer to the mux-state, or an ERR_PTR with a negative errno.
824 *831 *
825 * The mux-state will automatically be freed on release.832 * The mux-state will automatically be freed on release.
826 */833 */
827struct mux_state *devm_mux_state_get(struct device *dev, const char *mux_name)834struct mux_state *
835devm_mux_state_get_from_np(struct device *dev, const char *mux_name,
836 struct device_node *np)
828{837{
829 return __devm_mux_state_get(dev, mux_name, false, NULL, NULL);838 return __devm_mux_state_get(dev, mux_name, false, np, NULL, NULL);
830}839}
831EXPORT_SYMBOL_GPL(devm_mux_state_get);840EXPORT_SYMBOL_GPL(devm_mux_state_get_from_np);
832 841
833/**842/**
834 * devm_mux_state_get_optional() - Get the optional mux-state for a device,843 * devm_mux_state_get_optional() - Get the optional mux-state for a device,
@@ -843,7 +852,7 @@ EXPORT_SYMBOL_GPL(devm_mux_state_get); · 8 unmodified lines
843 */852 */
844struct mux_state *devm_mux_state_get_optional(struct device *dev, const char *mux_name)853struct mux_state *devm_mux_state_get_optional(struct device *dev, const char *mux_name)
845{854{
846 return __devm_mux_state_get(dev, mux_name, true, NULL, NULL);855 return __devm_mux_state_get(dev, mux_name, true, NULL, NULL, NULL);
847}856}
848EXPORT_SYMBOL_GPL(devm_mux_state_get_optional);857EXPORT_SYMBOL_GPL(devm_mux_state_get_optional);
849 858
@@ -861,7 +870,8 @@ EXPORT_SYMBOL_GPL(devm_mux_state_get_optional); · 11 unmodified lines
861 */870 */
862struct mux_state *devm_mux_state_get_selected(struct device *dev, const char *mux_name)871struct mux_state *devm_mux_state_get_selected(struct device *dev, const char *mux_name)
863{872{
864 return __devm_mux_state_get(dev, mux_name, false, mux_state_select, mux_state_deselect);873 return __devm_mux_state_get(dev, mux_name, false, NULL,
874 mux_state_select, mux_state_deselect);
865}875}
866EXPORT_SYMBOL_GPL(devm_mux_state_get_selected);876EXPORT_SYMBOL_GPL(devm_mux_state_get_selected);
867 877
@@ -881,7 +891,8 @@ EXPORT_SYMBOL_GPL(devm_mux_state_get_selected); · 13 unmodified lines
881struct mux_state *devm_mux_state_get_optional_selected(struct device *dev,891struct mux_state *devm_mux_state_get_optional_selected(struct device *dev,
882 const char *mux_name)892 const char *mux_name)
883{893{
884 return __devm_mux_state_get(dev, mux_name, true, mux_state_select, mux_state_deselect);894 return __devm_mux_state_get(dev, mux_name, true, NULL,
895 mux_state_select, mux_state_deselect);
885}896}
886EXPORT_SYMBOL_GPL(devm_mux_state_get_optional_selected);897EXPORT_SYMBOL_GPL(devm_mux_state_get_optional_selected);
887 898
drivers/pinctrl/Kconfig+13−0
@@ -272,6 +272,16 @@ config PINCTRL_GEMINI · 271 unmodified lines
272 select GENERIC_PINCONF272 select GENERIC_PINCONF
273 select MFD_SYSCON273 select MFD_SYSCON
274 274
275config PINCTRL_GENERIC_MUX
276 tristate "Generic Pinctrl driver by using multiplexer"
277 depends on MULTIPLEXER
278 depends on OF
279 select PINMUX
280 select GENERIC_PINCTRL
281 help
282 Generic pinctrl driver by MULTIPLEXER framework to control on
283 board pin selection.
284
275config PINCTRL_INGENIC285config PINCTRL_INGENIC
276 bool "Pinctrl driver for the Ingenic JZ47xx SoCs"286 bool "Pinctrl driver for the Ingenic JZ47xx SoCs"
277 default MACH_INGENIC287 default MACH_INGENIC
@@ -548,6 +558,7 @@ config PINCTRL_ST · 270 unmodified lines
548 558
549config PINCTRL_STMFX559config PINCTRL_STMFX
550 tristate "STMicroelectronics STMFX GPIO expander pinctrl driver"560 tristate "STMicroelectronics STMFX GPIO expander pinctrl driver"
561 depends on OF
551 depends on I2C562 depends on I2C
552 depends on HAS_IOMEM563 depends on HAS_IOMEM
553 select GENERIC_PINCONF564 select GENERIC_PINCONF
@@ -679,6 +690,7 @@ config PINCTRL_RP1 · 125 unmodified lines
679 multi function device.690 multi function device.
680 691
681source "drivers/pinctrl/actions/Kconfig"692source "drivers/pinctrl/actions/Kconfig"
693source "drivers/pinctrl/airoha/Kconfig"
682source "drivers/pinctrl/aspeed/Kconfig"694source "drivers/pinctrl/aspeed/Kconfig"
683source "drivers/pinctrl/bcm/Kconfig"695source "drivers/pinctrl/bcm/Kconfig"
684source "drivers/pinctrl/berlin/Kconfig"696source "drivers/pinctrl/berlin/Kconfig"
@@ -708,6 +720,7 @@ source "drivers/pinctrl/sunplus/Kconfig" · 23 unmodified lines
708source "drivers/pinctrl/sunxi/Kconfig"720source "drivers/pinctrl/sunxi/Kconfig"
709source "drivers/pinctrl/tegra/Kconfig"721source "drivers/pinctrl/tegra/Kconfig"
710source "drivers/pinctrl/ti/Kconfig"722source "drivers/pinctrl/ti/Kconfig"
723source "drivers/pinctrl/ultrarisc/Kconfig"
711source "drivers/pinctrl/uniphier/Kconfig"724source "drivers/pinctrl/uniphier/Kconfig"
712source "drivers/pinctrl/visconti/Kconfig"725source "drivers/pinctrl/visconti/Kconfig"
713source "drivers/pinctrl/vt8500/Kconfig"726source "drivers/pinctrl/vt8500/Kconfig"
drivers/pinctrl/Makefile+7−4
@@ -29,6 +29,7 @@ obj-$(CONFIG_PINCTRL_EQUILIBRIUM) += pinctrl-equilibrium.o · 28 unmodified lines
29obj-$(CONFIG_PINCTRL_EP93XX) += pinctrl-ep93xx.o29obj-$(CONFIG_PINCTRL_EP93XX) += pinctrl-ep93xx.o
30obj-$(CONFIG_PINCTRL_EYEQ5) += pinctrl-eyeq5.o30obj-$(CONFIG_PINCTRL_EYEQ5) += pinctrl-eyeq5.o
31obj-$(CONFIG_PINCTRL_GEMINI) += pinctrl-gemini.o31obj-$(CONFIG_PINCTRL_GEMINI) += pinctrl-gemini.o
32obj-$(CONFIG_PINCTRL_GENERIC_MUX) += pinctrl-generic-mux.o
32obj-$(CONFIG_PINCTRL_INGENIC) += pinctrl-ingenic.o33obj-$(CONFIG_PINCTRL_INGENIC) += pinctrl-ingenic.o
33obj-$(CONFIG_PINCTRL_K210) += pinctrl-k210.o34obj-$(CONFIG_PINCTRL_K210) += pinctrl-k210.o
34obj-$(CONFIG_PINCTRL_K230) += pinctrl-k230.o35obj-$(CONFIG_PINCTRL_K230) += pinctrl-k230.o
@@ -66,7 +67,8 @@ obj-$(CONFIG_PINCTRL_ZYNQMP) += pinctrl-zynqmp.o · 31 unmodified lines
66obj-$(CONFIG_PINCTRL_ZYNQ) += pinctrl-zynq.o67obj-$(CONFIG_PINCTRL_ZYNQ) += pinctrl-zynq.o
67 68
68obj-y += actions/69obj-y += actions/
69obj-$(CONFIG_ARCH_ASPEED) += aspeed/70obj-y += airoha/
71obj-$(CONFIG_PINCTRL_ASPEED) += aspeed/
70obj-y += bcm/72obj-y += bcm/
71obj-$(CONFIG_PINCTRL_BERLIN) += berlin/73obj-$(CONFIG_PINCTRL_BERLIN) += berlin/
72obj-y += cirrus/74obj-y += cirrus/
@@ -82,7 +84,7 @@ obj-y += nuvoton/ · 9 unmodified lines
82obj-y += nxp/84obj-y += nxp/
83obj-$(CONFIG_PINCTRL_PXA) += pxa/85obj-$(CONFIG_PINCTRL_PXA) += pxa/
84obj-y += qcom/86obj-y += qcom/
85obj-$(CONFIG_ARCH_REALTEK) += realtek/87obj-$(CONFIG_PINCTRL_RTD) += realtek/
86obj-$(CONFIG_PINCTRL_RENESAS) += renesas/88obj-$(CONFIG_PINCTRL_RENESAS) += renesas/
87obj-$(CONFIG_PINCTRL_SAMSUNG) += samsung/89obj-$(CONFIG_PINCTRL_SAMSUNG) += samsung/
88obj-y += sophgo/90obj-y += sophgo/
@@ -93,8 +95,9 @@ obj-y += starfive/ · 4 unmodified lines
93obj-$(CONFIG_PINCTRL_STM32) += stm32/95obj-$(CONFIG_PINCTRL_STM32) += stm32/
94obj-y += sunplus/96obj-y += sunplus/
95obj-$(CONFIG_PINCTRL_SUNXI) += sunxi/97obj-$(CONFIG_PINCTRL_SUNXI) += sunxi/
96obj-$(CONFIG_ARCH_TEGRA) += tegra/98obj-y += tegra/
97obj-y += ti/99obj-y += ti/
100obj-$(CONFIG_PINCTRL_ULTRARISC) += ultrarisc/
98obj-$(CONFIG_PINCTRL_UNIPHIER) += uniphier/101obj-$(CONFIG_PINCTRL_UNIPHIER) += uniphier/
99obj-$(CONFIG_PINCTRL_VISCONTI) += visconti/102obj-$(CONFIG_PINCTRL_VISCONTI) += visconti/
100obj-$(CONFIG_ARCH_VT8500) += vt8500/103obj-$(CONFIG_PINCTRL_WMT) += vt8500/
drivers/pinctrl/actions/pinctrl-owl.h+1−1
@@ -1,4 +1,4 @@
1// SPDX-License-Identifier: GPL-2.0+1/* SPDX-License-Identifier: GPL-2.0+ */
2/*2/*
3 * OWL SoC's Pinctrl definitions3 * OWL SoC's Pinctrl definitions
4 *4 *
drivers/pinctrl/airoha/Kconfig+20−0
@@ -0,0 +1,20 @@
1# SPDX-License-Identifier: GPL-2.0-only
2menu "Airoha pinctrl drivers"
3 depends on ARCH_AIROHA || COMPILE_TEST
4
5config PINCTRL_AIROHA
6 tristate "Airoha EN7581 pin control"
7 depends on OF
8 depends on ARM64 || COMPILE_TEST
9 select PINMUX
10 select GENERIC_PINCONF
11 select GENERIC_PINCTRL_GROUPS
12 select GENERIC_PINMUX_FUNCTIONS
13 select GPIOLIB
14 select GPIOLIB_IRQCHIP
15 select REGMAP_MMIO
16 help
17 Say yes here to support pin controller and gpio driver
18 on Airoha EN7581 SoC.
19
20endmenu
drivers/pinctrl/airoha/Makefile+3−0
@@ -0,0 +1,3 @@
1# SPDX-License-Identifier: GPL-2.0
2
3obj-$(CONFIG_PINCTRL_AIROHA) += pinctrl-airoha.o
drivers/pinctrl/airoha/pinctrl-airoha.crenamed from drivers/pinctrl/mediatek/pinctrl-airoha.c+99−25
@@ -539,6 +539,7 @@ static const int en7581_gpio28_pins[] = { 41 }; · 538 unmodified lines
539static const int en7581_gpio29_pins[] = { 42 };539static const int en7581_gpio29_pins[] = { 42 };
540static const int en7581_gpio30_pins[] = { 43 };540static const int en7581_gpio30_pins[] = { 43 };
541static const int en7581_gpio31_pins[] = { 44 };541static const int en7581_gpio31_pins[] = { 44 };
542static const int en7581_gpio32_pins[] = { 45 };
542static const int en7581_gpio33_pins[] = { 46 };543static const int en7581_gpio33_pins[] = { 46 };
543static const int en7581_gpio34_pins[] = { 47 };544static const int en7581_gpio34_pins[] = { 47 };
544static const int en7581_gpio35_pins[] = { 48 };545static const int en7581_gpio35_pins[] = { 48 };
@@ -623,6 +624,7 @@ static const struct pingroup en7581_pinctrl_groups[] = { · 78 unmodified lines
623 PINCTRL_PIN_GROUP("gpio29", en7581_gpio29),624 PINCTRL_PIN_GROUP("gpio29", en7581_gpio29),
624 PINCTRL_PIN_GROUP("gpio30", en7581_gpio30),625 PINCTRL_PIN_GROUP("gpio30", en7581_gpio30),
625 PINCTRL_PIN_GROUP("gpio31", en7581_gpio31),626 PINCTRL_PIN_GROUP("gpio31", en7581_gpio31),
627 PINCTRL_PIN_GROUP("gpio32", en7581_gpio32),
626 PINCTRL_PIN_GROUP("gpio33", en7581_gpio33),628 PINCTRL_PIN_GROUP("gpio33", en7581_gpio33),
627 PINCTRL_PIN_GROUP("gpio34", en7581_gpio34),629 PINCTRL_PIN_GROUP("gpio34", en7581_gpio34),
628 PINCTRL_PIN_GROUP("gpio35", en7581_gpio35),630 PINCTRL_PIN_GROUP("gpio35", en7581_gpio35),
@@ -746,7 +748,8 @@ static const int an7583_gpio17_pins[] = { 19 }; · 117 unmodified lines
746static const int an7583_gpio18_pins[] = { 20 };748static const int an7583_gpio18_pins[] = { 20 };
747static const int an7583_gpio19_pins[] = { 21 };749static const int an7583_gpio19_pins[] = { 21 };
748static const int an7583_gpio20_pins[] = { 22 };750static const int an7583_gpio20_pins[] = { 22 };
749static const int an7583_gpio21_pins[] = { 24 };751static const int an7583_gpio21_pins[] = { 23 };
752static const int an7583_gpio22_pins[] = { 24 };
750static const int an7583_gpio23_pins[] = { 25 };753static const int an7583_gpio23_pins[] = { 25 };
751static const int an7583_gpio24_pins[] = { 26 };754static const int an7583_gpio24_pins[] = { 26 };
752static const int an7583_gpio25_pins[] = { 27 };755static const int an7583_gpio25_pins[] = { 27 };
@@ -756,6 +759,7 @@ static const int an7583_gpio28_pins[] = { 30 }; · 3 unmodified lines
756static const int an7583_gpio29_pins[] = { 31 };759static const int an7583_gpio29_pins[] = { 31 };
757static const int an7583_gpio30_pins[] = { 32 };760static const int an7583_gpio30_pins[] = { 32 };
758static const int an7583_gpio31_pins[] = { 33 };761static const int an7583_gpio31_pins[] = { 33 };
762static const int an7583_gpio32_pins[] = { 34 };
759static const int an7583_gpio33_pins[] = { 35 };763static const int an7583_gpio33_pins[] = { 35 };
760static const int an7583_gpio34_pins[] = { 36 };764static const int an7583_gpio34_pins[] = { 36 };
761static const int an7583_gpio35_pins[] = { 37 };765static const int an7583_gpio35_pins[] = { 37 };
@@ -825,6 +829,7 @@ static const struct pingroup an7583_pinctrl_groups[] = { · 63 unmodified lines
825 PINCTRL_PIN_GROUP("gpio19", an7583_gpio19),829 PINCTRL_PIN_GROUP("gpio19", an7583_gpio19),
826 PINCTRL_PIN_GROUP("gpio20", an7583_gpio20),830 PINCTRL_PIN_GROUP("gpio20", an7583_gpio20),
827 PINCTRL_PIN_GROUP("gpio21", an7583_gpio21),831 PINCTRL_PIN_GROUP("gpio21", an7583_gpio21),
832 PINCTRL_PIN_GROUP("gpio22", an7583_gpio22),
828 PINCTRL_PIN_GROUP("gpio23", an7583_gpio23),833 PINCTRL_PIN_GROUP("gpio23", an7583_gpio23),
829 PINCTRL_PIN_GROUP("gpio24", an7583_gpio24),834 PINCTRL_PIN_GROUP("gpio24", an7583_gpio24),
830 PINCTRL_PIN_GROUP("gpio25", an7583_gpio25),835 PINCTRL_PIN_GROUP("gpio25", an7583_gpio25),
@@ -834,6 +839,7 @@ static const struct pingroup an7583_pinctrl_groups[] = { · 3 unmodified lines
834 PINCTRL_PIN_GROUP("gpio29", an7583_gpio29),839 PINCTRL_PIN_GROUP("gpio29", an7583_gpio29),
835 PINCTRL_PIN_GROUP("gpio30", an7583_gpio30),840 PINCTRL_PIN_GROUP("gpio30", an7583_gpio30),
836 PINCTRL_PIN_GROUP("gpio31", an7583_gpio31),841 PINCTRL_PIN_GROUP("gpio31", an7583_gpio31),
842 PINCTRL_PIN_GROUP("gpio32", an7583_gpio32),
837 PINCTRL_PIN_GROUP("gpio33", an7583_gpio33),843 PINCTRL_PIN_GROUP("gpio33", an7583_gpio33),
838 PINCTRL_PIN_GROUP("gpio34", an7583_gpio34),844 PINCTRL_PIN_GROUP("gpio34", an7583_gpio34),
839 PINCTRL_PIN_GROUP("gpio35", an7583_gpio35),845 PINCTRL_PIN_GROUP("gpio35", an7583_gpio35),
@@ -871,10 +877,8 @@ static const char *const pcm_spi_groups[] = { "pcm_spi", "pcm_spi_int", · 31 unmodified lines
871 "pcm_spi_cs2_p156",877 "pcm_spi_cs2_p156",
872 "pcm_spi_cs2_p128",878 "pcm_spi_cs2_p128",
873 "pcm_spi_cs3", "pcm_spi_cs4" };879 "pcm_spi_cs3", "pcm_spi_cs4" };
874static const char *const an7583_pcm_spi_groups[] = { "pcm_spi", "pcm_spi_int",880static const char *const an7583_pcm_spi_groups[] = { "pcm_spi",
875 "pcm_spi_rst", "pcm_spi_cs1",881 "pcm_spi_rst", "pcm_spi_cs1" };
876 "pcm_spi_cs2", "pcm_spi_cs3",
877 "pcm_spi_cs4" };
878static const char *const i2s_groups[] = { "i2s" };882static const char *const i2s_groups[] = { "i2s" };
879static const char *const emmc_groups[] = { "emmc" };883static const char *const emmc_groups[] = { "emmc" };
880static const char *const pnand_groups[] = { "pnand" };884static const char *const pnand_groups[] = { "pnand" };
@@ -902,7 +906,30 @@ static const char *const pwm_groups[] = { "gpio0", "gpio1", · 21 unmodified lines
902 "gpio40", "gpio41",906 "gpio40", "gpio41",
903 "gpio42", "gpio43",907 "gpio42", "gpio43",
904 "gpio44", "gpio45",908 "gpio44", "gpio45",
905 "gpio46", "gpio47" };909 "gpio46" };
910static const char *const an7583_pwm_groups[] = { "gpio0", "gpio1",
911 "gpio2", "gpio3",
912 "gpio4", "gpio5",
913 "gpio6", "gpio7",
914 "gpio8", "gpio9",
915 "gpio10", "gpio11",
916 "gpio12", "gpio13",
917 "gpio14", "gpio15",
918 "gpio16", "gpio17",
919 "gpio18", "gpio19",
920 "gpio20", "gpio21",
921 "gpio22", "gpio23",
922 "gpio24", "gpio25",
923 "gpio26", "gpio27",
924 "gpio28", "gpio29",
925 "gpio30", "gpio31",
926 "gpio36", "gpio37",
927 "gpio38", "gpio39",
928 "gpio40", "gpio41",
929 "gpio42", "gpio43",
930 "gpio44", "gpio45",
931 "gpio46", "gpio47",
932 "gpio48" };
906static const char *const phy1_led0_groups[] = { "gpio33", "gpio34",933static const char *const phy1_led0_groups[] = { "gpio33", "gpio34",
907 "gpio35", "gpio42" };934 "gpio35", "gpio42" };
908static const char *const phy2_led0_groups[] = { "gpio33", "gpio34",935static const char *const phy2_led0_groups[] = { "gpio33", "gpio34",
@@ -1500,7 +1527,54 @@ static const struct airoha_pinctrl_func_group pwm_func_group[] = { · 591 unmodified lines
1500 AIROHA_PINCTRL_PWM_EXT("gpio44", GPIO44_FLASH_MODE_CFG),1527 AIROHA_PINCTRL_PWM_EXT("gpio44", GPIO44_FLASH_MODE_CFG),
1501 AIROHA_PINCTRL_PWM_EXT("gpio45", GPIO45_FLASH_MODE_CFG),1528 AIROHA_PINCTRL_PWM_EXT("gpio45", GPIO45_FLASH_MODE_CFG),
1502 AIROHA_PINCTRL_PWM_EXT("gpio46", GPIO46_FLASH_MODE_CFG),1529 AIROHA_PINCTRL_PWM_EXT("gpio46", GPIO46_FLASH_MODE_CFG),
1530};
1531
1532static const struct airoha_pinctrl_func_group an7583_pwm_func_group[] = {
1533 AIROHA_PINCTRL_PWM("gpio0", GPIO0_FLASH_MODE_CFG),
1534 AIROHA_PINCTRL_PWM("gpio1", GPIO1_FLASH_MODE_CFG),
1535 AIROHA_PINCTRL_PWM("gpio2", GPIO2_FLASH_MODE_CFG),
1536 AIROHA_PINCTRL_PWM("gpio3", GPIO3_FLASH_MODE_CFG),
1537 AIROHA_PINCTRL_PWM("gpio4", GPIO4_FLASH_MODE_CFG),
1538 AIROHA_PINCTRL_PWM("gpio5", GPIO5_FLASH_MODE_CFG),
1539 AIROHA_PINCTRL_PWM("gpio6", GPIO6_FLASH_MODE_CFG),
1540 AIROHA_PINCTRL_PWM("gpio7", GPIO7_FLASH_MODE_CFG),
1541 AIROHA_PINCTRL_PWM("gpio8", GPIO8_FLASH_MODE_CFG),
1542 AIROHA_PINCTRL_PWM("gpio9", GPIO9_FLASH_MODE_CFG),
1543 AIROHA_PINCTRL_PWM("gpio10", GPIO10_FLASH_MODE_CFG),
1544 AIROHA_PINCTRL_PWM("gpio11", GPIO11_FLASH_MODE_CFG),
1545 AIROHA_PINCTRL_PWM("gpio12", GPIO12_FLASH_MODE_CFG),
1546 AIROHA_PINCTRL_PWM("gpio13", GPIO13_FLASH_MODE_CFG),
1547 AIROHA_PINCTRL_PWM("gpio14", GPIO14_FLASH_MODE_CFG),
1548 AIROHA_PINCTRL_PWM("gpio15", GPIO15_FLASH_MODE_CFG),
1549 AIROHA_PINCTRL_PWM_EXT("gpio16", GPIO16_FLASH_MODE_CFG),
1550 AIROHA_PINCTRL_PWM_EXT("gpio17", GPIO17_FLASH_MODE_CFG),
1551 AIROHA_PINCTRL_PWM_EXT("gpio18", GPIO18_FLASH_MODE_CFG),
1552 AIROHA_PINCTRL_PWM_EXT("gpio19", GPIO19_FLASH_MODE_CFG),
1553 AIROHA_PINCTRL_PWM_EXT("gpio20", GPIO20_FLASH_MODE_CFG),
1554 AIROHA_PINCTRL_PWM_EXT("gpio21", GPIO21_FLASH_MODE_CFG),
1555 AIROHA_PINCTRL_PWM_EXT("gpio22", GPIO22_FLASH_MODE_CFG),
1556 AIROHA_PINCTRL_PWM_EXT("gpio23", GPIO23_FLASH_MODE_CFG),
1557 AIROHA_PINCTRL_PWM_EXT("gpio24", GPIO24_FLASH_MODE_CFG),
1558 AIROHA_PINCTRL_PWM_EXT("gpio25", GPIO25_FLASH_MODE_CFG),
1559 AIROHA_PINCTRL_PWM_EXT("gpio26", GPIO26_FLASH_MODE_CFG),
1560 AIROHA_PINCTRL_PWM_EXT("gpio27", GPIO27_FLASH_MODE_CFG),
1561 AIROHA_PINCTRL_PWM_EXT("gpio28", GPIO28_FLASH_MODE_CFG),
1562 AIROHA_PINCTRL_PWM_EXT("gpio29", GPIO29_FLASH_MODE_CFG),
1563 AIROHA_PINCTRL_PWM_EXT("gpio30", GPIO30_FLASH_MODE_CFG),
1564 AIROHA_PINCTRL_PWM_EXT("gpio31", GPIO31_FLASH_MODE_CFG),
1565 AIROHA_PINCTRL_PWM_EXT("gpio36", GPIO36_FLASH_MODE_CFG),
1566 AIROHA_PINCTRL_PWM_EXT("gpio37", GPIO37_FLASH_MODE_CFG),
1567 AIROHA_PINCTRL_PWM_EXT("gpio38", GPIO38_FLASH_MODE_CFG),
1568 AIROHA_PINCTRL_PWM_EXT("gpio39", GPIO39_FLASH_MODE_CFG),
1569 AIROHA_PINCTRL_PWM_EXT("gpio40", GPIO40_FLASH_MODE_CFG),
1570 AIROHA_PINCTRL_PWM_EXT("gpio41", GPIO41_FLASH_MODE_CFG),
1571 AIROHA_PINCTRL_PWM_EXT("gpio42", GPIO42_FLASH_MODE_CFG),
1572 AIROHA_PINCTRL_PWM_EXT("gpio43", GPIO43_FLASH_MODE_CFG),
1573 AIROHA_PINCTRL_PWM_EXT("gpio44", GPIO44_FLASH_MODE_CFG),
1574 AIROHA_PINCTRL_PWM_EXT("gpio45", GPIO45_FLASH_MODE_CFG),
1575 AIROHA_PINCTRL_PWM_EXT("gpio46", GPIO46_FLASH_MODE_CFG),
1503 AIROHA_PINCTRL_PWM_EXT("gpio47", GPIO47_FLASH_MODE_CFG),1576 AIROHA_PINCTRL_PWM_EXT("gpio47", GPIO47_FLASH_MODE_CFG),
1577 AIROHA_PINCTRL_PWM_EXT("gpio48", GPIO48_FLASH_MODE_CFG),
1504};1578};
1505 1579
1506#define AIROHA_PINCTRL_PHY_LED0(gpio, mux_val, map_mask, map_val) \1580#define AIROHA_PINCTRL_PHY_LED0(gpio, mux_val, map_mask, map_val) \
@@ -1618,13 +1692,13 @@ static const struct airoha_pinctrl_func_group phy3_led1_func_group[] = { · 111 unmodified lines
1618 1692
1619static const struct airoha_pinctrl_func_group phy4_led1_func_group[] = {1693static const struct airoha_pinctrl_func_group phy4_led1_func_group[] = {
1620 AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK,1694 AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK,
1621 LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),1695 LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
1622 AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK,1696 AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK,
1623 LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),1697 LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)),
1624 AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK,1698 AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK,
1625 LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),1699 LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)),
1626 AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK,1700 AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK,
1627 LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),1701 LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
1628};1702};
1629 1703
1630static const struct airoha_pinctrl_func_group an7583_phy1_led0_func_group[] = {1704static const struct airoha_pinctrl_func_group an7583_phy1_led0_func_group[] = {
@@ -1678,7 +1752,7 @@ static const struct airoha_pinctrl_func_group an7583_phy1_led1_func_group[] = { · 47 unmodified lines
1678 LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),1752 LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
1679 AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK,1753 AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK,
1680 LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),1754 LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
1681 AIROHA_PINCTRL_PHY_LED1("gpio1", GPIO_LAN3_LED1_MODE_MASK,1755 AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK,
1682 LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),1756 LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
1683};1757};
1684 1758
@@ -1706,13 +1780,13 @@ static const struct airoha_pinctrl_func_group an7583_phy3_led1_func_group[] = { · 21 unmodified lines
1706 1780
1707static const struct airoha_pinctrl_func_group an7583_phy4_led1_func_group[] = {1781static const struct airoha_pinctrl_func_group an7583_phy4_led1_func_group[] = {
1708 AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK,1782 AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK,
1709 LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),1783 LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
1710 AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK,1784 AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK,
1711 LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),1785 LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)),
1712 AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK,1786 AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK,
1713 LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),1787 LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)),
1714 AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK,1788 AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK,
1715 LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),1789 LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
1716};1790};
1717 1791
1718static const struct airoha_pinctrl_func en7581_pinctrl_funcs[] = {1792static const struct airoha_pinctrl_func en7581_pinctrl_funcs[] = {
@@ -1755,7 +1829,7 @@ static const struct airoha_pinctrl_func an7583_pinctrl_funcs[] = { · 36 unmodified lines
1755 PINCTRL_FUNC_DESC("emmc", emmc),1829 PINCTRL_FUNC_DESC("emmc", emmc),
1756 PINCTRL_FUNC_DESC("pnand", pnand),1830 PINCTRL_FUNC_DESC("pnand", pnand),
1757 PINCTRL_FUNC_DESC("pcie_reset", an7583_pcie_reset),1831 PINCTRL_FUNC_DESC("pcie_reset", an7583_pcie_reset),
1758 PINCTRL_FUNC_DESC("pwm", pwm),1832 PINCTRL_FUNC_DESC("pwm", an7583_pwm),
1759 PINCTRL_FUNC_DESC("phy1_led0", an7583_phy1_led0),1833 PINCTRL_FUNC_DESC("phy1_led0", an7583_phy1_led0),
1760 PINCTRL_FUNC_DESC("phy2_led0", an7583_phy2_led0),1834 PINCTRL_FUNC_DESC("phy2_led0", an7583_phy2_led0),
1761 PINCTRL_FUNC_DESC("phy3_led0", an7583_phy3_led0),1835 PINCTRL_FUNC_DESC("phy3_led0", an7583_phy3_led0),
@@ -1794,7 +1868,7 @@ static const struct airoha_pinctrl_conf en7581_pinctrl_pullup_conf[] = { · 32 unmodified lines
1794 PINCTRL_CONF_DESC(29, REG_GPIO_L_PU, BIT(16)),1868 PINCTRL_CONF_DESC(29, REG_GPIO_L_PU, BIT(16)),
1795 PINCTRL_CONF_DESC(30, REG_GPIO_L_PU, BIT(17)),1869 PINCTRL_CONF_DESC(30, REG_GPIO_L_PU, BIT(17)),
1796 PINCTRL_CONF_DESC(31, REG_GPIO_L_PU, BIT(18)),1870 PINCTRL_CONF_DESC(31, REG_GPIO_L_PU, BIT(18)),
1797 PINCTRL_CONF_DESC(32, REG_GPIO_L_PU, BIT(18)),1871 PINCTRL_CONF_DESC(32, REG_GPIO_L_PU, BIT(19)),
1798 PINCTRL_CONF_DESC(33, REG_GPIO_L_PU, BIT(20)),1872 PINCTRL_CONF_DESC(33, REG_GPIO_L_PU, BIT(20)),
1799 PINCTRL_CONF_DESC(34, REG_GPIO_L_PU, BIT(21)),1873 PINCTRL_CONF_DESC(34, REG_GPIO_L_PU, BIT(21)),
1800 PINCTRL_CONF_DESC(35, REG_GPIO_L_PU, BIT(22)),1874 PINCTRL_CONF_DESC(35, REG_GPIO_L_PU, BIT(22)),
@@ -1847,7 +1921,7 @@ static const struct airoha_pinctrl_conf an7583_pinctrl_pullup_conf[] = { · 46 unmodified lines
1847 PINCTRL_CONF_DESC(18, REG_GPIO_L_PU, BIT(16)),1921 PINCTRL_CONF_DESC(18, REG_GPIO_L_PU, BIT(16)),
1848 PINCTRL_CONF_DESC(19, REG_GPIO_L_PU, BIT(17)),1922 PINCTRL_CONF_DESC(19, REG_GPIO_L_PU, BIT(17)),
1849 PINCTRL_CONF_DESC(20, REG_GPIO_L_PU, BIT(18)),1923 PINCTRL_CONF_DESC(20, REG_GPIO_L_PU, BIT(18)),
1850 PINCTRL_CONF_DESC(21, REG_GPIO_L_PU, BIT(18)),1924 PINCTRL_CONF_DESC(21, REG_GPIO_L_PU, BIT(19)),
1851 PINCTRL_CONF_DESC(22, REG_GPIO_L_PU, BIT(20)),1925 PINCTRL_CONF_DESC(22, REG_GPIO_L_PU, BIT(20)),
1852 PINCTRL_CONF_DESC(23, REG_GPIO_L_PU, BIT(21)),1926 PINCTRL_CONF_DESC(23, REG_GPIO_L_PU, BIT(21)),
1853 PINCTRL_CONF_DESC(24, REG_GPIO_L_PU, BIT(22)),1927 PINCTRL_CONF_DESC(24, REG_GPIO_L_PU, BIT(22)),
@@ -1911,7 +1985,7 @@ static const struct airoha_pinctrl_conf en7581_pinctrl_pulldown_conf[] = { · 57 unmodified lines
1911 PINCTRL_CONF_DESC(29, REG_GPIO_L_PD, BIT(16)),1985 PINCTRL_CONF_DESC(29, REG_GPIO_L_PD, BIT(16)),
1912 PINCTRL_CONF_DESC(30, REG_GPIO_L_PD, BIT(17)),1986 PINCTRL_CONF_DESC(30, REG_GPIO_L_PD, BIT(17)),
1913 PINCTRL_CONF_DESC(31, REG_GPIO_L_PD, BIT(18)),1987 PINCTRL_CONF_DESC(31, REG_GPIO_L_PD, BIT(18)),
1914 PINCTRL_CONF_DESC(32, REG_GPIO_L_PD, BIT(18)),1988 PINCTRL_CONF_DESC(32, REG_GPIO_L_PD, BIT(19)),
1915 PINCTRL_CONF_DESC(33, REG_GPIO_L_PD, BIT(20)),1989 PINCTRL_CONF_DESC(33, REG_GPIO_L_PD, BIT(20)),
1916 PINCTRL_CONF_DESC(34, REG_GPIO_L_PD, BIT(21)),1990 PINCTRL_CONF_DESC(34, REG_GPIO_L_PD, BIT(21)),
1917 PINCTRL_CONF_DESC(35, REG_GPIO_L_PD, BIT(22)),1991 PINCTRL_CONF_DESC(35, REG_GPIO_L_PD, BIT(22)),
@@ -1964,7 +2038,7 @@ static const struct airoha_pinctrl_conf an7583_pinctrl_pulldown_conf[] = { · 46 unmodified lines
1964 PINCTRL_CONF_DESC(18, REG_GPIO_L_PD, BIT(16)),2038 PINCTRL_CONF_DESC(18, REG_GPIO_L_PD, BIT(16)),
1965 PINCTRL_CONF_DESC(19, REG_GPIO_L_PD, BIT(17)),2039 PINCTRL_CONF_DESC(19, REG_GPIO_L_PD, BIT(17)),
1966 PINCTRL_CONF_DESC(20, REG_GPIO_L_PD, BIT(18)),2040 PINCTRL_CONF_DESC(20, REG_GPIO_L_PD, BIT(18)),
1967 PINCTRL_CONF_DESC(21, REG_GPIO_L_PD, BIT(18)),2041 PINCTRL_CONF_DESC(21, REG_GPIO_L_PD, BIT(19)),
1968 PINCTRL_CONF_DESC(22, REG_GPIO_L_PD, BIT(20)),2042 PINCTRL_CONF_DESC(22, REG_GPIO_L_PD, BIT(20)),
1969 PINCTRL_CONF_DESC(23, REG_GPIO_L_PD, BIT(21)),2043 PINCTRL_CONF_DESC(23, REG_GPIO_L_PD, BIT(21)),
1970 PINCTRL_CONF_DESC(24, REG_GPIO_L_PD, BIT(22)),2044 PINCTRL_CONF_DESC(24, REG_GPIO_L_PD, BIT(22)),
@@ -2028,7 +2102,7 @@ static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e2_conf[] = { · 57 unmodified lines
2028 PINCTRL_CONF_DESC(29, REG_GPIO_L_E2, BIT(16)),2102 PINCTRL_CONF_DESC(29, REG_GPIO_L_E2, BIT(16)),
2029 PINCTRL_CONF_DESC(30, REG_GPIO_L_E2, BIT(17)),2103 PINCTRL_CONF_DESC(30, REG_GPIO_L_E2, BIT(17)),
2030 PINCTRL_CONF_DESC(31, REG_GPIO_L_E2, BIT(18)),2104 PINCTRL_CONF_DESC(31, REG_GPIO_L_E2, BIT(18)),
2031 PINCTRL_CONF_DESC(32, REG_GPIO_L_E2, BIT(18)),2105 PINCTRL_CONF_DESC(32, REG_GPIO_L_E2, BIT(19)),
2032 PINCTRL_CONF_DESC(33, REG_GPIO_L_E2, BIT(20)),2106 PINCTRL_CONF_DESC(33, REG_GPIO_L_E2, BIT(20)),
2033 PINCTRL_CONF_DESC(34, REG_GPIO_L_E2, BIT(21)),2107 PINCTRL_CONF_DESC(34, REG_GPIO_L_E2, BIT(21)),
2034 PINCTRL_CONF_DESC(35, REG_GPIO_L_E2, BIT(22)),2108 PINCTRL_CONF_DESC(35, REG_GPIO_L_E2, BIT(22)),
@@ -2081,7 +2155,7 @@ static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e2_conf[] = { · 46 unmodified lines
2081 PINCTRL_CONF_DESC(18, REG_GPIO_L_E2, BIT(16)),2155 PINCTRL_CONF_DESC(18, REG_GPIO_L_E2, BIT(16)),
2082 PINCTRL_CONF_DESC(19, REG_GPIO_L_E2, BIT(17)),2156 PINCTRL_CONF_DESC(19, REG_GPIO_L_E2, BIT(17)),
2083 PINCTRL_CONF_DESC(20, REG_GPIO_L_E2, BIT(18)),2157 PINCTRL_CONF_DESC(20, REG_GPIO_L_E2, BIT(18)),
2084 PINCTRL_CONF_DESC(21, REG_GPIO_L_E2, BIT(18)),2158 PINCTRL_CONF_DESC(21, REG_GPIO_L_E2, BIT(19)),
2085 PINCTRL_CONF_DESC(22, REG_GPIO_L_E2, BIT(20)),2159 PINCTRL_CONF_DESC(22, REG_GPIO_L_E2, BIT(20)),
2086 PINCTRL_CONF_DESC(23, REG_GPIO_L_E2, BIT(21)),2160 PINCTRL_CONF_DESC(23, REG_GPIO_L_E2, BIT(21)),
2087 PINCTRL_CONF_DESC(24, REG_GPIO_L_E2, BIT(22)),2161 PINCTRL_CONF_DESC(24, REG_GPIO_L_E2, BIT(22)),
@@ -2145,7 +2219,7 @@ static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e4_conf[] = { · 57 unmodified lines
2145 PINCTRL_CONF_DESC(29, REG_GPIO_L_E4, BIT(16)),2219 PINCTRL_CONF_DESC(29, REG_GPIO_L_E4, BIT(16)),
2146 PINCTRL_CONF_DESC(30, REG_GPIO_L_E4, BIT(17)),2220 PINCTRL_CONF_DESC(30, REG_GPIO_L_E4, BIT(17)),
2147 PINCTRL_CONF_DESC(31, REG_GPIO_L_E4, BIT(18)),2221 PINCTRL_CONF_DESC(31, REG_GPIO_L_E4, BIT(18)),
2148 PINCTRL_CONF_DESC(32, REG_GPIO_L_E4, BIT(18)),2222 PINCTRL_CONF_DESC(32, REG_GPIO_L_E4, BIT(19)),
2149 PINCTRL_CONF_DESC(33, REG_GPIO_L_E4, BIT(20)),2223 PINCTRL_CONF_DESC(33, REG_GPIO_L_E4, BIT(20)),
2150 PINCTRL_CONF_DESC(34, REG_GPIO_L_E4, BIT(21)),2224 PINCTRL_CONF_DESC(34, REG_GPIO_L_E4, BIT(21)),
2151 PINCTRL_CONF_DESC(35, REG_GPIO_L_E4, BIT(22)),2225 PINCTRL_CONF_DESC(35, REG_GPIO_L_E4, BIT(22)),
@@ -2198,7 +2272,7 @@ static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e4_conf[] = { · 46 unmodified lines
2198 PINCTRL_CONF_DESC(18, REG_GPIO_L_E4, BIT(16)),2272 PINCTRL_CONF_DESC(18, REG_GPIO_L_E4, BIT(16)),
2199 PINCTRL_CONF_DESC(19, REG_GPIO_L_E4, BIT(17)),2273 PINCTRL_CONF_DESC(19, REG_GPIO_L_E4, BIT(17)),
2200 PINCTRL_CONF_DESC(20, REG_GPIO_L_E4, BIT(18)),2274 PINCTRL_CONF_DESC(20, REG_GPIO_L_E4, BIT(18)),
2201 PINCTRL_CONF_DESC(21, REG_GPIO_L_E4, BIT(18)),2275 PINCTRL_CONF_DESC(21, REG_GPIO_L_E4, BIT(19)),
2202 PINCTRL_CONF_DESC(22, REG_GPIO_L_E4, BIT(20)),2276 PINCTRL_CONF_DESC(22, REG_GPIO_L_E4, BIT(20)),
2203 PINCTRL_CONF_DESC(23, REG_GPIO_L_E4, BIT(21)),2277 PINCTRL_CONF_DESC(23, REG_GPIO_L_E4, BIT(21)),
2204 PINCTRL_CONF_DESC(24, REG_GPIO_L_E4, BIT(22)),2278 PINCTRL_CONF_DESC(24, REG_GPIO_L_E4, BIT(22)),
@@ -2811,7 +2885,7 @@ static int airoha_pinconf_group_get(struct pinctrl_dev *pctrl_dev, · 606 unmodified lines
2811 unsigned int group, unsigned long *config)2885 unsigned int group, unsigned long *config)
2812{2886{
2813 struct airoha_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);2887 struct airoha_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
2814 u32 cur_config = 0;2888 unsigned long cur_config = 0;
2815 int i;2889 int i;
2816 2890
2817 for (i = 0; i < pinctrl->grps[group].npins; i++) {2891 for (i = 0; i < pinctrl->grps[group].npins; i++) {
drivers/pinctrl/aspeed/Kconfig+23−0
@@ -31,3 +31,26 @@ config PINCTRL_ASPEED_G6 · 30 unmodified lines
31 help31 help
32 Say Y here to enable pin controller support for Aspeed's 6th32 Say Y here to enable pin controller support for Aspeed's 6th
33 generation SoCs. GPIO is provided by a separate GPIO driver.33 generation SoCs. GPIO is provided by a separate GPIO driver.
34
35config PINCTRL_ASPEED_G7_SOC0
36 bool "Aspeed G7 SoC pin control"
37 depends on (ARCH_ASPEED || COMPILE_TEST) && OF
38 select PINCTRL_ASPEED
39 help
40 Say Y here to enable pin controller support for the SoC0 instance
41 of Aspeed's 7th generation SoCs. GPIO is provided by a separate
42 GPIO driver.
43
44config PINCTRL_ASPEED_G7_SOC1
45 bool "Aspeed G7 SoC1 pin control"
46 depends on (ARCH_ASPEED || COMPILE_TEST) && OF
47 select MFD_SYSCON
48 select PINMUX
49 select GENERIC_PINCTRL_GROUPS
50 select GENERIC_PINMUX_FUNCTIONS
51 select GENERIC_PINCONF
52 select REGMAP_MMIO
53 help
54 Say Y here to enable pin controller support for the SoC1 instance
55 of Aspeed's 7th generation SoCs. GPIO is provided by a separate
56 GPIO driver.
drivers/pinctrl/aspeed/Makefile+2−0
@@ -6,3 +6,5 @@ obj-$(CONFIG_PINCTRL_ASPEED) += pinctrl-aspeed.o pinmux-aspeed.o · 5 unmodified lines
6obj-$(CONFIG_PINCTRL_ASPEED_G4) += pinctrl-aspeed-g4.o6obj-$(CONFIG_PINCTRL_ASPEED_G4) += pinctrl-aspeed-g4.o
7obj-$(CONFIG_PINCTRL_ASPEED_G5) += pinctrl-aspeed-g5.o7obj-$(CONFIG_PINCTRL_ASPEED_G5) += pinctrl-aspeed-g5.o
8obj-$(CONFIG_PINCTRL_ASPEED_G6) += pinctrl-aspeed-g6.o8obj-$(CONFIG_PINCTRL_ASPEED_G6) += pinctrl-aspeed-g6.o
9obj-$(CONFIG_PINCTRL_ASPEED_G7_SOC0) += pinctrl-aspeed-g7-soc0.o
10obj-$(CONFIG_PINCTRL_ASPEED_G7_SOC1) += pinctrl-aspeed-g7-soc1.o
drivers/pinctrl/aspeed/pinctrl-aspeed-g7-soc0.c+749−0
@@ -0,0 +1,749 @@
1// SPDX-License-Identifier: GPL-2.0
2
3#include <linux/bitops.h>
4#include <linux/bits.h>
5#include <linux/mfd/syscon.h>
6#include <linux/of.h>
7#include <linux/pinctrl/pinconf-generic.h>
8#include <linux/pinctrl/pinconf.h>
9#include <linux/pinctrl/pinctrl.h>
10#include <linux/pinctrl/pinmux.h>
11#include <linux/platform_device.h>
12#include <linux/regmap.h>
13
14#include "pinctrl-aspeed.h"
15#include "pinmux-aspeed.h"
16#include "../pinctrl-utils.h"
17
18#define SCU200 0x200 /* System Reset Control #1 */
19
20#define SCU010 0x010 /* Hardware Strap Register */
21#define SCU400 0x400 /* Multi-function Pin Control #1 */
22#define SCU404 0x404 /* Multi-function Pin Control #2 */
23#define SCU408 0x408 /* Multi-function Pin Control #3 */
24#define SCU40C 0x40C /* Multi-function Pin Control #3 */
25#define SCU410 0x410 /* USB Multi-function Control Register */
26#define SCU414 0x414 /* VGA Function Control Register */
27
28#define SCU480 0x480 /* GPIO18A0 IO Control Register */
29#define SCU484 0x484 /* GPIO18A1 IO Control Register */
30#define SCU488 0x488 /* GPIO18A2 IO Control Register */
31#define SCU48C 0x48c /* GPIO18A3 IO Control Register */
32#define SCU490 0x490 /* GPIO18A4 IO Control Register */
33#define SCU494 0x494 /* GPIO18A5 IO Control Register */
34#define SCU498 0x498 /* GPIO18A6 IO Control Register */
35#define SCU49C 0x49c /* GPIO18A7 IO Control Register */
36#define SCU4A0 0x4A0 /* GPIO18B0 IO Control Register */
37#define SCU4A4 0x4A4 /* GPIO18B1 IO Control Register */
38#define SCU4A8 0x4A8 /* GPIO18B2 IO Control Register */
39#define SCU4AC 0x4AC /* GPIO18B3 IO Control Register */
40
41enum {
42 AC14,
43 AE15,
44 AD14,
45 AE14,
46 AF14,
47 AB13,
48 AB14,
49 AF15,
50 AF13,
51 AC13,
52 AD13,
53 AE13,
54 JTAG_PORT,
55 PCIERC0_PERST,
56 PCIERC1_PERST,
57 PORTA_MODE,
58 PORTA_U2,
59 PORTB_MODE,
60 PORTB_U2,
61 PORTA_U2_PHY,
62 PORTB_U2_PHY,
63 PORTA_U3,
64 PORTB_U3,
65 PORTA_U3_PHY,
66 PORTB_U3_PHY,
67};
68
69SIG_EXPR_LIST_DECL_SEMG(AC14, EMMCCLK, EMMCG1, EMMC, SIG_DESC_SET(SCU400, 0));
70SIG_EXPR_LIST_DECL_SEMG(AC14, VB1CS, VB1, VB, SIG_DESC_SET(SCU404, 0));
71PIN_DECL_2(AC14, GPIO18A0, EMMCCLK, VB1CS);
72
73SIG_EXPR_LIST_DECL_SEMG(AE15, EMMCCMD, EMMCG1, EMMC, SIG_DESC_SET(SCU400, 1));
74SIG_EXPR_LIST_DECL_SEMG(AE15, VB1CK, VB1, VB, SIG_DESC_SET(SCU404, 1));
75PIN_DECL_2(AE15, GPIO18A1, EMMCCMD, VB1CK);
76
77SIG_EXPR_LIST_DECL_SEMG(AD14, EMMCDAT0, EMMCG1, EMMC, SIG_DESC_SET(SCU400, 2));
78SIG_EXPR_LIST_DECL_SEMG(AD14, VB1MOSI, VB1, VB, SIG_DESC_SET(SCU404, 2));
79PIN_DECL_2(AD14, GPIO18A2, EMMCDAT0, VB1MOSI);
80
81SIG_EXPR_LIST_DECL_SEMG(AE14, EMMCDAT1, EMMCG4, EMMC, SIG_DESC_SET(SCU400, 3));
82SIG_EXPR_LIST_DECL_SEMG(AE14, VB1MISO, VB1, VB, SIG_DESC_SET(SCU404, 3));
83PIN_DECL_2(AE14, GPIO18A3, EMMCDAT1, VB1MISO);
84
85SIG_EXPR_LIST_DECL_SEMG(AF14, EMMCDAT2, EMMCG4, EMMC, SIG_DESC_SET(SCU400, 4));
86PIN_DECL_1(AF14, GPIO18A4, EMMCDAT2);
87
88SIG_EXPR_LIST_DECL_SEMG(AB13, EMMCDAT3, EMMCG4, EMMC, SIG_DESC_SET(SCU400, 5));
89PIN_DECL_1(AB13, GPIO18A5, EMMCDAT3);
90
91SIG_EXPR_LIST_DECL_SEMG(AB14, EMMCCDN, EMMCG1, EMMC, SIG_DESC_SET(SCU400, 6));
92SIG_EXPR_LIST_DECL_SEMG(AB14, VB0CS, VB0, VB, SIG_DESC_SET(SCU010, 17));
93PIN_DECL_2(AB14, GPIO18A6, EMMCCDN, VB0CS);
94
95SIG_EXPR_LIST_DECL_SEMG(AF15, EMMCWPN, EMMCG1, EMMC, SIG_DESC_SET(SCU400, 7));
96SIG_EXPR_LIST_DECL_SEMG(AF15, VB0CK, VB0, VB, SIG_DESC_SET(SCU010, 17));
97PIN_DECL_2(AF15, GPIO18A7, EMMCWPN, VB0CK);
98
99SIG_EXPR_LIST_DECL_SESG(AF13, TSPRSTN, TSPRSTN, SIG_DESC_SET(SCU010, 9));
100SIG_EXPR_LIST_DECL_SEMG(AF13, EMMCDAT4, EMMCG8, EMMC, SIG_DESC_SET(SCU400, 8));
101SIG_EXPR_LIST_DECL_SEMG(AF13, VB0MOSI, VB0, VB, SIG_DESC_SET(SCU010, 17));
102PIN_DECL_3(AF13, GPIO18B0, TSPRSTN, EMMCDAT4, VB0MOSI);
103
104SIG_EXPR_LIST_DECL_SESG(AC13, UFSCLKI, UFSCLKI, SIG_DESC_SET(SCU010, 19));
105SIG_EXPR_LIST_DECL_SEMG(AC13, EMMCDAT5, EMMCG8, EMMC, SIG_DESC_SET(SCU400, 9));
106SIG_EXPR_LIST_DECL_SEMG(AC13, VB0MISO, VB0, VB, SIG_DESC_SET(SCU010, 17));
107PIN_DECL_3(AC13, GPIO18B1, UFSCLKI, EMMCDAT5, VB0MISO);
108
109SIG_EXPR_LIST_DECL_SEMG(AD13, EMMCDAT6, EMMCG8, EMMC, SIG_DESC_SET(SCU400, 10));
110SIG_EXPR_LIST_DECL_SESG(AD13, DDCCLK, VGADDC, SIG_DESC_SET(SCU404, 10));
111PIN_DECL_2(AD13, GPIO18B2, EMMCDAT6, DDCCLK);
112
113SIG_EXPR_LIST_DECL_SEMG(AE13, EMMCDAT7, EMMCG8, EMMC, SIG_DESC_SET(SCU400, 11));
114SIG_EXPR_LIST_DECL_SESG(AE13, DDCDAT, VGADDC, SIG_DESC_SET(SCU404, 11));
115PIN_DECL_2(AE13, GPIO18B3, EMMCDAT7, DDCDAT);
116
117GROUP_DECL(EMMCG1, AC14, AE15, AD14);
118GROUP_DECL(EMMCG4, AC14, AE15, AD14, AE14, AF14, AB13);
119GROUP_DECL(EMMCG8, AC14, AE15, AD14, AE14, AF14, AB13, AF13, AC13, AD13, AE13);
120GROUP_DECL(EMMCWPN, AF15);
121GROUP_DECL(EMMCCDN, AB14);
122FUNC_DECL_(EMMC, "EMMCG1", "EMMCG4", "EMMCG8", "EMMCWPN", "EMMCCDN");
123
124GROUP_DECL(VB1, AC14, AE15, AD14, AE14);
125GROUP_DECL(VB0, AF15, AB14, AF13, AC13);
126FUNC_DECL_2(VB, VB1, VB0);
127
128FUNC_GROUP_DECL(TSPRSTN, AF13);
129
130FUNC_GROUP_DECL(UFSCLKI, AC13);
131
132FUNC_GROUP_DECL(VGADDC, AD13, AE13);
133
134/* JTAG Port Selection */
135#define JTAG_PORT_PSP_DESC { ASPEED_IP_SCU, SCU408, GENMASK(12, 5), 0x0, 0 }
136#define JTAG_PORT_SSP_DESC { ASPEED_IP_SCU, SCU408, GENMASK(12, 5), 0x41, 0 }
137#define JTAG_PORT_TSP_DESC { ASPEED_IP_SCU, SCU408, GENMASK(12, 5), 0x42, 0 }
138#define JTAG_PORT_DDR_DESC { ASPEED_IP_SCU, SCU408, GENMASK(12, 5), 0x43, 0 }
139#define JTAG_PORT_USB3A_DESC { ASPEED_IP_SCU, SCU408, GENMASK(12, 5), 0x44, 0 }
140#define JTAG_PORT_USB3B_DESC { ASPEED_IP_SCU, SCU408, GENMASK(12, 5), 0x45, 0 }
141#define JTAG_PORT_PCIEA_DESC { ASPEED_IP_SCU, SCU408, GENMASK(12, 5), 0x46, 0 }
142#define JTAG_PORT_PCIEB_DESC { ASPEED_IP_SCU, SCU408, GENMASK(12, 5), 0x47, 0 }
143#define JTAG_PORT_JTAGM0_DESC { ASPEED_IP_SCU, SCU408, GENMASK(12, 5), 0x8, 0 }
144
145SIG_EXPR_LIST_DECL_SEMG(JTAG_PORT, JTAGPSP, JTAG0, JTAGPSP, JTAG_PORT_PSP_DESC);
146SIG_EXPR_LIST_DECL_SEMG(JTAG_PORT, JTAGSSP, JTAG0, JTAGSSP, JTAG_PORT_SSP_DESC);
147SIG_EXPR_LIST_DECL_SEMG(JTAG_PORT, JTAGTSP, JTAG0, JTAGTSP, JTAG_PORT_TSP_DESC);
148SIG_EXPR_LIST_DECL_SEMG(JTAG_PORT, JTAGDDR, JTAG0, JTAGDDR, JTAG_PORT_DDR_DESC);
149SIG_EXPR_LIST_DECL_SEMG(JTAG_PORT, JTAGUSB3A, JTAG0, JTAGUSB3A, JTAG_PORT_USB3A_DESC);
150SIG_EXPR_LIST_DECL_SEMG(JTAG_PORT, JTAGUSB3B, JTAG0, JTAGUSB3B, JTAG_PORT_USB3B_DESC);
151SIG_EXPR_LIST_DECL_SEMG(JTAG_PORT, JTAGPCIEA, JTAG0, JTAGPCIEA, JTAG_PORT_PCIEA_DESC);
152SIG_EXPR_LIST_DECL_SEMG(JTAG_PORT, JTAGPCIEB, JTAG0, JTAGPCIEB, JTAG_PORT_PCIEB_DESC);
153SIG_EXPR_LIST_DECL_SEMG(JTAG_PORT, JTAGM0, JTAG0, JTAGM0, JTAG_PORT_JTAGM0_DESC);
154PIN_DECL_(JTAG_PORT, SIG_EXPR_LIST_PTR(JTAG_PORT, JTAGPSP), SIG_EXPR_LIST_PTR(JTAG_PORT, JTAGSSP),
155 SIG_EXPR_LIST_PTR(JTAG_PORT, JTAGTSP), SIG_EXPR_LIST_PTR(JTAG_PORT, JTAGDDR),
156 SIG_EXPR_LIST_PTR(JTAG_PORT, JTAGUSB3A), SIG_EXPR_LIST_PTR(JTAG_PORT, JTAGUSB3B),
157 SIG_EXPR_LIST_PTR(JTAG_PORT, JTAGPCIEA), SIG_EXPR_LIST_PTR(JTAG_PORT, JTAGPCIEB),
158 SIG_EXPR_LIST_PTR(JTAG_PORT, JTAGM0));
159
160GROUP_DECL(JTAG0, JTAG_PORT);
161
162FUNC_DECL_1(JTAGPSP, JTAG0);
163FUNC_DECL_1(JTAGSSP, JTAG0);
164FUNC_DECL_1(JTAGTSP, JTAG0);
165FUNC_DECL_1(JTAGDDR, JTAG0);
166FUNC_DECL_1(JTAGUSB3A, JTAG0);
167FUNC_DECL_1(JTAGUSB3B, JTAG0);
168FUNC_DECL_1(JTAGPCIEA, JTAG0);
169FUNC_DECL_1(JTAGPCIEB, JTAG0);
170FUNC_DECL_1(JTAGM0, JTAG0);
171
172/* PCIe Reset Control */
173SIG_EXPR_LIST_DECL_SESG(PCIERC0_PERST, PCIERC0PERST, PCIERC0PERST, SIG_DESC_SET(SCU200, 21));
174PIN_DECL_(PCIERC0_PERST, SIG_EXPR_LIST_PTR(PCIERC0_PERST, PCIERC0PERST));
175FUNC_GROUP_DECL(PCIERC0PERST, PCIERC0_PERST);
176
177SIG_EXPR_LIST_DECL_SESG(PCIERC1_PERST, PCIERC1PERST, PCIERC1PERST, SIG_DESC_SET(SCU200, 19));
178PIN_DECL_(PCIERC1_PERST, SIG_EXPR_LIST_PTR(PCIERC1_PERST, PCIERC1PERST));
179FUNC_GROUP_DECL(PCIERC1PERST, PCIERC1_PERST);
180
181#define PORTA_MODE_HPD0_DESC { ASPEED_IP_SCU, SCU410, GENMASK(25, 24), 0, 0 }
182#define PORTA_MODE_D0_DESC { ASPEED_IP_SCU, SCU410, GENMASK(25, 24), 1, 0 }
183#define PORTA_MODE_H_DESC { ASPEED_IP_SCU, SCU410, GENMASK(25, 24), 2, 0 }
184#define PORTA_MODE_HP_DESC { ASPEED_IP_SCU, SCU410, GENMASK(25, 24), 3, 0 }
185
186SIG_EXPR_LIST_DECL_SEMG(PORTA_MODE, USB2AHPD0, USB2AH, USB2AHPD0, PORTA_MODE_HPD0_DESC);
187SIG_EXPR_LIST_DECL_SEMG(PORTA_MODE, USB2AH, USB2AHAP, USB2AH, PORTA_MODE_H_DESC);
188SIG_EXPR_LIST_DECL_SEMG(PORTA_MODE, USB2AHP, USB2AHAP, USB2AHP, PORTA_MODE_HP_DESC);
189SIG_EXPR_LIST_DECL_SEMG(PORTA_MODE, USB2AD0, USB2AHAP, USB2AD0, PORTA_MODE_D0_DESC);
190PIN_DECL_(PORTA_MODE, SIG_EXPR_LIST_PTR(PORTA_MODE, USB2AHPD0),
191 SIG_EXPR_LIST_PTR(PORTA_MODE, USB2AH), SIG_EXPR_LIST_PTR(PORTA_MODE, USB2AHP),
192 SIG_EXPR_LIST_PTR(PORTA_MODE, USB2AD0));
193
194#define PORTA_U2_XHD_DESC { ASPEED_IP_SCU, SCU410, GENMASK(3, 2), 0, 0 }
195#define PORTA_U2_D1_DESC { ASPEED_IP_SCU, SCU410, GENMASK(3, 2), 1, 0 }
196#define PORTA_U2_XH_DESC { ASPEED_IP_SCU, SCU410, GENMASK(3, 2), 2, 0 }
197#define PORTA_U2_XH2E_DESC { ASPEED_IP_SCU, SCU410, GENMASK(3, 2), 3, 0 }
198
199SIG_EXPR_LIST_DECL_SEMG(PORTA_U2, USB2AXHD1, USB2A, USB2AXHD1, PORTA_U2_XHD_DESC,
200 SIG_DESC_SET(SCU410, 9));
201SIG_EXPR_LIST_DECL_SEMG(PORTA_U2, USB2AXHPD1, USB2A, USB2AXHPD1, PORTA_U2_XHD_DESC,
202 SIG_DESC_CLEAR(SCU410, 9));
203SIG_EXPR_LIST_DECL_SEMG(PORTA_U2, USB2AXH, USB2AAP, USB2AXH, PORTA_U2_XH_DESC,
204 SIG_DESC_SET(SCU410, 9));
205SIG_EXPR_LIST_DECL_SEMG(PORTA_U2, USB2AXHP, USB2AAP, USB2AXHP, PORTA_U2_XH_DESC,
206 SIG_DESC_CLEAR(SCU410, 9));
207SIG_EXPR_LIST_DECL_SEMG(PORTA_U2, USB2AXH2B, USB2ABP, USB2AXH2B, PORTA_U2_XH2E_DESC,
208 SIG_DESC_SET(SCU410, 9));
209SIG_EXPR_LIST_DECL_SEMG(PORTA_U2, USB2AXHP2B, USB2ABP, USB2AXHP2B, PORTA_U2_XH2E_DESC,
210 SIG_DESC_CLEAR(SCU410, 9));
211SIG_EXPR_LIST_DECL_SEMG(PORTA_U2, USB2AD1, USB2ADAP, USB2AD1, PORTA_U2_D1_DESC);
212PIN_DECL_(PORTA_U2, SIG_EXPR_LIST_PTR(PORTA_U2, USB2AXHD1), SIG_EXPR_LIST_PTR(PORTA_U2, USB2AXHPD1),
213 SIG_EXPR_LIST_PTR(PORTA_U2, USB2AXH), SIG_EXPR_LIST_PTR(PORTA_U2, USB2AXHP),
214 SIG_EXPR_LIST_PTR(PORTA_U2, USB2AXH2B), SIG_EXPR_LIST_PTR(PORTA_U2, USB2AXHP2B),
215 SIG_EXPR_LIST_PTR(PORTA_U2, USB2AD1));
216
217#define PORTB_MODE_HPD0_DESC { ASPEED_IP_SCU, SCU410, GENMASK(29, 28), 0, 0 }
218#define PORTB_MODE_D0_DESC { ASPEED_IP_SCU, SCU410, GENMASK(29, 28), 1, 0 }
219#define PORTB_MODE_H_DESC { ASPEED_IP_SCU, SCU410, GENMASK(29, 28), 2, 0 }
220#define PORTB_MODE_HP_DESC { ASPEED_IP_SCU, SCU410, GENMASK(29, 28), 3, 0 }
221
222SIG_EXPR_LIST_DECL_SEMG(PORTB_MODE, USB2BHPD0, USB2BH, USB2BHPD0, PORTB_MODE_HPD0_DESC);
223SIG_EXPR_LIST_DECL_SEMG(PORTB_MODE, USB2BH, USB2BHBP, USB2BH, PORTB_MODE_H_DESC);
224SIG_EXPR_LIST_DECL_SEMG(PORTB_MODE, USB2BHP, USB2BHBP, USB2BHP, PORTB_MODE_HP_DESC);
225SIG_EXPR_LIST_DECL_SEMG(PORTB_MODE, USB2BD0, USB2BHBP, USB2BD0, PORTB_MODE_D0_DESC);
226PIN_DECL_(PORTB_MODE, SIG_EXPR_LIST_PTR(PORTB_MODE, USB2BHPD0),
227 SIG_EXPR_LIST_PTR(PORTB_MODE, USB2BH), SIG_EXPR_LIST_PTR(PORTB_MODE, USB2BHP),
228 SIG_EXPR_LIST_PTR(PORTB_MODE, USB2BD0));
229
230#define PORTB_U2_XHD_DESC { ASPEED_IP_SCU, SCU410, GENMASK(7, 6), 0, 0 }
231#define PORTB_U2_D1_DESC { ASPEED_IP_SCU, SCU410, GENMASK(7, 6), 1, 0 }
232#define PORTB_U2_XH_DESC { ASPEED_IP_SCU, SCU410, GENMASK(7, 6), 2, 0 }
233#define PORTB_U2_XH2E_DESC { ASPEED_IP_SCU, SCU410, GENMASK(7, 6), 3, 0 }
234
235SIG_EXPR_LIST_DECL_SEMG(PORTB_U2, USB2BXHD1, USB2B, USB2BXHD1, PORTB_U2_XHD_DESC,
236 SIG_DESC_SET(SCU410, 10));
237SIG_EXPR_LIST_DECL_SEMG(PORTB_U2, USB2BXHPD1, USB2B, USB2BXHPD1, PORTB_U2_XHD_DESC,
238 SIG_DESC_CLEAR(SCU410, 10));
239SIG_EXPR_LIST_DECL_SEMG(PORTB_U2, USB2BXH, USB2BBP, USB2BXH, PORTB_U2_XH_DESC,
240 SIG_DESC_SET(SCU410, 10));
241SIG_EXPR_LIST_DECL_SEMG(PORTB_U2, USB2BXHP, USB2BBP, USB2BXHP, PORTB_U2_XH_DESC,
242 SIG_DESC_CLEAR(SCU410, 10));
243SIG_EXPR_LIST_DECL_SEMG(PORTB_U2, USB2BXH2A, USB2BAP, USB2BXH2A, PORTB_U2_XH2E_DESC,
244 SIG_DESC_SET(SCU410, 10));
245SIG_EXPR_LIST_DECL_SEMG(PORTB_U2, USB2BXHP2A, USB2BAP, USB2BXHP2A, PORTB_U2_XH2E_DESC,
246 SIG_DESC_CLEAR(SCU410, 10));
247SIG_EXPR_LIST_DECL_SEMG(PORTB_U2, USB2BD1, USB2BDBP, USB2BD1, PORTB_U2_D1_DESC);
248PIN_DECL_(PORTB_U2, SIG_EXPR_LIST_PTR(PORTB_U2, USB2BXHD1), SIG_EXPR_LIST_PTR(PORTB_U2, USB2BXHPD1),
249 SIG_EXPR_LIST_PTR(PORTB_U2, USB2BXH), SIG_EXPR_LIST_PTR(PORTB_U2, USB2BXHP),
250 SIG_EXPR_LIST_PTR(PORTB_U2, USB2BXH2A), SIG_EXPR_LIST_PTR(PORTB_U2, USB2BXHP2A),
251 SIG_EXPR_LIST_PTR(PORTB_U2, USB2BD1));
252/*
253 * USB2 virtual PHY pins.
254 *
255 * PORTA_U2_PHY and PORTB_U2_PHY are logical endpoints, not package pins.
256 * They alias existing USB2 expressions so pin groups can model direct and
257 * cross-coupled routing for host and mode paths.
258 *
259 * - USB2AAP/USB2ADAP/USB2AHAP: use PORTA_U2_PHY
260 * - USB2ABP : use PORTB_U2_PHY
261 * - USB2BBP/USB2BDBP/USB2BHBP: use PORTB_U2_PHY
262 * - USB2BAP : use PORTA_U2_PHY
263 *
264 * They do not have any registers to configure this behaviour; the goal is
265 * simply for the driver to prevent conflicting selections. For example,
266 * selecting group USB2ABP and USB2BBP at the same time should not be
267 * allowed.
268 */
269SIG_EXPR_LIST_ALIAS(PORTA_U2_PHY, USB2AXH, USB2AAP);
270SIG_EXPR_LIST_ALIAS(PORTA_U2_PHY, USB2AXHP, USB2AAP);
271SIG_EXPR_LIST_ALIAS(PORTA_U2_PHY, USB2BXH2A, USB2BAP);
272SIG_EXPR_LIST_ALIAS(PORTA_U2_PHY, USB2BXHP2A, USB2BAP);
273SIG_EXPR_LIST_ALIAS(PORTA_U2_PHY, USB2AD1, USB2ADAP);
274SIG_EXPR_LIST_ALIAS(PORTA_U2_PHY, USB2AH, USB2AHAP);
275SIG_EXPR_LIST_ALIAS(PORTA_U2_PHY, USB2AHP, USB2AHAP);
276SIG_EXPR_LIST_ALIAS(PORTA_U2_PHY, USB2AD0, USB2AHAP);
277PIN_DECL_(PORTA_U2_PHY, SIG_EXPR_LIST_PTR(PORTA_U2_PHY, USB2AXH),
278 SIG_EXPR_LIST_PTR(PORTA_U2_PHY, USB2AXHP), SIG_EXPR_LIST_PTR(PORTA_U2_PHY, USB2BXH2A),
279 SIG_EXPR_LIST_PTR(PORTA_U2_PHY, USB2BXHP2A), SIG_EXPR_LIST_PTR(PORTA_U2_PHY, USB2AD1),
280 SIG_EXPR_LIST_PTR(PORTA_U2_PHY, USB2AH), SIG_EXPR_LIST_PTR(PORTA_U2_PHY, USB2AHP),
281 SIG_EXPR_LIST_PTR(PORTA_U2_PHY, USB2AD0));
282
283SIG_EXPR_LIST_ALIAS(PORTB_U2_PHY, USB2AXH2B, USB2ABP);
284SIG_EXPR_LIST_ALIAS(PORTB_U2_PHY, USB2AXHP2B, USB2ABP);
285SIG_EXPR_LIST_ALIAS(PORTB_U2_PHY, USB2BXH, USB2BBP);
286SIG_EXPR_LIST_ALIAS(PORTB_U2_PHY, USB2BXHP, USB2BBP);
287SIG_EXPR_LIST_ALIAS(PORTB_U2_PHY, USB2BD1, USB2BDBP);
288SIG_EXPR_LIST_ALIAS(PORTB_U2_PHY, USB2BH, USB2BHBP);
289SIG_EXPR_LIST_ALIAS(PORTB_U2_PHY, USB2BHP, USB2BHBP);
290SIG_EXPR_LIST_ALIAS(PORTB_U2_PHY, USB2BD0, USB2BHBP);
291PIN_DECL_(PORTB_U2_PHY, SIG_EXPR_LIST_PTR(PORTB_U2_PHY, USB2AXH2B),
292 SIG_EXPR_LIST_PTR(PORTB_U2_PHY, USB2AXHP2B), SIG_EXPR_LIST_PTR(PORTB_U2_PHY, USB2BXH),
293 SIG_EXPR_LIST_PTR(PORTB_U2_PHY, USB2BXHP), SIG_EXPR_LIST_PTR(PORTB_U2_PHY, USB2BD1),
294 SIG_EXPR_LIST_PTR(PORTB_U2_PHY, USB2BH), SIG_EXPR_LIST_PTR(PORTB_U2_PHY, USB2BHP),
295 SIG_EXPR_LIST_PTR(PORTB_U2_PHY, USB2BD0));
296
297GROUP_DECL(USB2A, PORTA_U2);
298GROUP_DECL(USB2AAP, PORTA_U2, PORTA_U2_PHY);
299GROUP_DECL(USB2ABP, PORTA_U2, PORTB_U2_PHY);
300GROUP_DECL(USB2ADAP, PORTA_U2, PORTA_U2_PHY);
301GROUP_DECL(USB2AH, PORTA_MODE);
302GROUP_DECL(USB2AHAP, PORTA_MODE, PORTA_U2_PHY);
303
304FUNC_DECL_1(USB2AXHD1, USB2A);
305FUNC_DECL_1(USB2AXHPD1, USB2A);
306FUNC_DECL_1(USB2AXH, USB2AAP);
307FUNC_DECL_1(USB2AXHP, USB2AAP);
308FUNC_DECL_1(USB2AXH2B, USB2ABP);
309FUNC_DECL_1(USB2AXHP2B, USB2ABP);
310FUNC_DECL_1(USB2AD1, USB2ADAP);
311FUNC_DECL_1(USB2AHPD0, USB2AH);
312FUNC_DECL_1(USB2AH, USB2AHAP);
313FUNC_DECL_1(USB2AHP, USB2AHAP);
314FUNC_DECL_1(USB2AD0, USB2AHAP);
315
316GROUP_DECL(USB2B, PORTB_U2);
317GROUP_DECL(USB2BBP, PORTB_U2, PORTB_U2_PHY);
318GROUP_DECL(USB2BAP, PORTB_U2, PORTA_U2_PHY);
319GROUP_DECL(USB2BDBP, PORTB_U2, PORTB_U2_PHY);
320GROUP_DECL(USB2BH, PORTB_MODE);
321GROUP_DECL(USB2BHBP, PORTB_MODE, PORTB_U2_PHY);
322
323FUNC_DECL_1(USB2BXHD1, USB2B);
324FUNC_DECL_1(USB2BXHPD1, USB2B);
325FUNC_DECL_1(USB2BXH, USB2BBP);
326FUNC_DECL_1(USB2BXHP, USB2BBP);
327FUNC_DECL_1(USB2BXH2A, USB2BAP);
328FUNC_DECL_1(USB2BXHP2A, USB2BAP);
329FUNC_DECL_1(USB2BD1, USB2BDBP);
330FUNC_DECL_1(USB2BHPD0, USB2BH);
331FUNC_DECL_1(USB2BH, USB2BHBP);
332FUNC_DECL_1(USB2BHP, USB2BHBP);
333FUNC_DECL_1(USB2BD0, USB2BHBP);
334
335#define PORTA_U3_XHD_DESC { ASPEED_IP_SCU, SCU410, GENMASK(1, 0), 0, 0 }
336#define PORTA_U3_XH_DESC { ASPEED_IP_SCU, SCU410, GENMASK(1, 0), 2, 0 }
337#define PORTA_U3_XH2E_DESC { ASPEED_IP_SCU, SCU410, GENMASK(1, 0), 3, 0 }
338
339SIG_EXPR_LIST_DECL_SEMG(PORTA_U3, USB3AXHD, USB3A, USB3AXHD, PORTA_U3_XHD_DESC,
340 SIG_DESC_SET(SCU410, 9));
341SIG_EXPR_LIST_DECL_SEMG(PORTA_U3, USB3AXHPD, USB3A, USB3AXHPD, PORTA_U3_XHD_DESC,
342 SIG_DESC_CLEAR(SCU410, 9));
343SIG_EXPR_LIST_DECL_SEMG(PORTA_U3, USB3AXH, USB3AAP, USB3AXH, PORTA_U3_XH_DESC,
344 SIG_DESC_SET(SCU410, 9));
345SIG_EXPR_LIST_DECL_SEMG(PORTA_U3, USB3AXHP, USB3AAP, USB3AXHP, PORTA_U3_XH_DESC,
346 SIG_DESC_CLEAR(SCU410, 9));
347SIG_EXPR_LIST_DECL_SEMG(PORTA_U3, USB3AXH2B, USB3ABP, USB3AXH2B, PORTA_U3_XH2E_DESC,
348 SIG_DESC_SET(SCU410, 9));
349SIG_EXPR_LIST_DECL_SEMG(PORTA_U3, USB3AXHP2B, USB3ABP, USB3AXHP2B, PORTA_U3_XH2E_DESC,
350 SIG_DESC_CLEAR(SCU410, 9));
351PIN_DECL_(PORTA_U3, SIG_EXPR_LIST_PTR(PORTA_U3, USB3AXHD), SIG_EXPR_LIST_PTR(PORTA_U3, USB3AXHPD),
352 SIG_EXPR_LIST_PTR(PORTA_U3, USB3AXH), SIG_EXPR_LIST_PTR(PORTA_U3, USB3AXHP),
353 SIG_EXPR_LIST_PTR(PORTA_U3, USB3AXH2B), SIG_EXPR_LIST_PTR(PORTA_U3, USB3AXHP2B));
354
355#define PORTB_U3_XHD_DESC { ASPEED_IP_SCU, SCU410, GENMASK(5, 4), 0, 0 }
356#define PORTB_U3_XH_DESC { ASPEED_IP_SCU, SCU410, GENMASK(5, 4), 2, 0 }
357#define PORTB_U3_XH2E_DESC { ASPEED_IP_SCU, SCU410, GENMASK(5, 4), 3, 0 }
358
359SIG_EXPR_LIST_DECL_SEMG(PORTB_U3, USB3BXHD, USB3B, USB3BXHD, PORTB_U3_XHD_DESC,
360 SIG_DESC_SET(SCU410, 10));
361SIG_EXPR_LIST_DECL_SEMG(PORTB_U3, USB3BXHPD, USB3B, USB3BXHPD, PORTB_U3_XHD_DESC,
362 SIG_DESC_CLEAR(SCU410, 10));
363SIG_EXPR_LIST_DECL_SEMG(PORTB_U3, USB3BXH, USB3BBP, USB3BXH, PORTB_U3_XH_DESC,
364 SIG_DESC_SET(SCU410, 10));
365SIG_EXPR_LIST_DECL_SEMG(PORTB_U3, USB3BXHP, USB3BBP, USB3BXHP, PORTB_U3_XH_DESC,
366 SIG_DESC_CLEAR(SCU410, 10));
367SIG_EXPR_LIST_DECL_SEMG(PORTB_U3, USB3BXH2A, USB3BAP, USB3BXH2A, PORTB_U3_XH2E_DESC,
368 SIG_DESC_SET(SCU410, 10));
369SIG_EXPR_LIST_DECL_SEMG(PORTB_U3, USB3BXHP2A, USB3BAP, USB3BXHP2A, PORTB_U3_XH2E_DESC,
370 SIG_DESC_CLEAR(SCU410, 10));
371PIN_DECL_(PORTB_U3, SIG_EXPR_LIST_PTR(PORTB_U3, USB3BXHD), SIG_EXPR_LIST_PTR(PORTB_U3, USB3BXHPD),
372 SIG_EXPR_LIST_PTR(PORTB_U3, USB3BXH), SIG_EXPR_LIST_PTR(PORTB_U3, USB3BXHP),
373 SIG_EXPR_LIST_PTR(PORTB_U3, USB3BXH2A), SIG_EXPR_LIST_PTR(PORTB_U3, USB3BXHP2A));
374
375/*
376 * USB3 virtual PHY pins.
377 *
378 * PORTA_U3_PHY and PORTB_U3_PHY are logical endpoints, not package pins.
379 * They alias existing USB3 expressions so pin groups can model both direct and
380 * cross-coupled routing to PHY A/B.
381 *
382 * - USB3AAP: PORTA_U3 + PORTA_U3_PHY (A -> PHY A)
383 * - USB3ABP: PORTA_U3 + PORTB_U3_PHY (A -> PHY B)
384 * - USB3BBP: PORTB_U3 + PORTB_U3_PHY (B -> PHY B)
385 * - USB3BAP: PORTB_U3 + PORTA_U3_PHY (B -> PHY A)
386 *
387 * They do not have any registers to configure this behavior; the goal is
388 * simply for the driver to prevent conflicting selections. For example,
389 * selecting group USB3ABP and USB3BBP at the same time should not be
390 * allowed.
391 */
392SIG_EXPR_LIST_ALIAS(PORTA_U3_PHY, USB3AXH, USB3AAP);
393SIG_EXPR_LIST_ALIAS(PORTA_U3_PHY, USB3AXHP, USB3AAP);
394SIG_EXPR_LIST_ALIAS(PORTA_U3_PHY, USB3BXH2A, USB3BAP);
395SIG_EXPR_LIST_ALIAS(PORTA_U3_PHY, USB3BXHP2A, USB3BAP);
396PIN_DECL_(PORTA_U3_PHY, SIG_EXPR_LIST_PTR(PORTA_U3_PHY, USB3AXH),
397 SIG_EXPR_LIST_PTR(PORTA_U3_PHY, USB3AXHP), SIG_EXPR_LIST_PTR(PORTA_U3_PHY, USB3BXH2A),
398 SIG_EXPR_LIST_PTR(PORTA_U3_PHY, USB3BXHP2A));
399
400SIG_EXPR_LIST_ALIAS(PORTB_U3_PHY, USB3AXH2B, USB3ABP);
401SIG_EXPR_LIST_ALIAS(PORTB_U3_PHY, USB3AXHP2B, USB3ABP);
402SIG_EXPR_LIST_ALIAS(PORTB_U3_PHY, USB3BXH, USB3BBP);
403SIG_EXPR_LIST_ALIAS(PORTB_U3_PHY, USB3BXHP, USB3BBP);
404PIN_DECL_(PORTB_U3_PHY, SIG_EXPR_LIST_PTR(PORTB_U3_PHY, USB3AXH2B),
405 SIG_EXPR_LIST_PTR(PORTB_U3_PHY, USB3AXHP2B), SIG_EXPR_LIST_PTR(PORTB_U3_PHY, USB3BXH),
406 SIG_EXPR_LIST_PTR(PORTB_U3_PHY, USB3BXHP));
407
408/* USB3A xHCI to vHUB */
409GROUP_DECL(USB3A, PORTA_U3);
410/* USB3A xHCI to USB3A PHY */
411GROUP_DECL(USB3AAP, PORTA_U3, PORTA_U3_PHY);
412/* USB3A xHCI to USB3B PHY */
413GROUP_DECL(USB3ABP, PORTA_U3, PORTB_U3_PHY);
414
415FUNC_DECL_1(USB3AXHD, USB3A);
416FUNC_DECL_1(USB3AXHPD, USB3A);
417FUNC_DECL_1(USB3AXH, USB3AAP);
418FUNC_DECL_1(USB3AXHP, USB3AAP);
419FUNC_DECL_1(USB3AXH2B, USB3ABP);
420FUNC_DECL_1(USB3AXHP2B, USB3ABP);
421
422/* USB3B xHCI to vHUB */
423GROUP_DECL(USB3B, PORTB_U3);
424/* USB3B xHCI to USB3A PHY */
425GROUP_DECL(USB3BAP, PORTB_U3, PORTA_U3_PHY);
426/* USB3B xHCI to USB3B PHY */
427GROUP_DECL(USB3BBP, PORTB_U3, PORTB_U3_PHY);
428
429FUNC_DECL_1(USB3BXHD, USB3B);
430FUNC_DECL_1(USB3BXHPD, USB3B);
431FUNC_DECL_1(USB3BXH, USB3BBP);
432FUNC_DECL_1(USB3BXHP, USB3BBP);
433FUNC_DECL_1(USB3BXH2A, USB3BAP);
434FUNC_DECL_1(USB3BXHP2A, USB3BAP);
435
436static const struct pinctrl_pin_desc aspeed_g7_soc0_pins[] = {
437 ASPEED_PINCTRL_PIN(AC14),
438 ASPEED_PINCTRL_PIN(AE15),
439 ASPEED_PINCTRL_PIN(AD14),
440 ASPEED_PINCTRL_PIN(AE14),
441 ASPEED_PINCTRL_PIN(AF14),
442 ASPEED_PINCTRL_PIN(AB13),
443 ASPEED_PINCTRL_PIN(AB14),
444 ASPEED_PINCTRL_PIN(AF15),
445 ASPEED_PINCTRL_PIN(AF13),
446 ASPEED_PINCTRL_PIN(AC13),
447 ASPEED_PINCTRL_PIN(AD13),
448 ASPEED_PINCTRL_PIN(AE13),
449 ASPEED_PINCTRL_PIN(JTAG_PORT),
450 ASPEED_PINCTRL_PIN(PCIERC0_PERST),
451 ASPEED_PINCTRL_PIN(PCIERC1_PERST),
452 ASPEED_PINCTRL_PIN(PORTA_MODE),
453 ASPEED_PINCTRL_PIN(PORTA_U2),
454 ASPEED_PINCTRL_PIN(PORTA_U3),
455 ASPEED_PINCTRL_PIN(PORTA_U2_PHY),
456 ASPEED_PINCTRL_PIN(PORTA_U3_PHY),
457 ASPEED_PINCTRL_PIN(PORTB_MODE),
458 ASPEED_PINCTRL_PIN(PORTB_U2),
459 ASPEED_PINCTRL_PIN(PORTB_U3),
460 ASPEED_PINCTRL_PIN(PORTB_U2_PHY),
461 ASPEED_PINCTRL_PIN(PORTB_U3_PHY),
462};
463
464static const struct aspeed_pin_group aspeed_g7_soc0_groups[] = {
465 ASPEED_PINCTRL_GROUP(EMMCCDN),
466 ASPEED_PINCTRL_GROUP(EMMCG1),
467 ASPEED_PINCTRL_GROUP(EMMCG4),
468 ASPEED_PINCTRL_GROUP(EMMCG8),
469 ASPEED_PINCTRL_GROUP(EMMCWPN),
470 ASPEED_PINCTRL_GROUP(TSPRSTN),
471 ASPEED_PINCTRL_GROUP(UFSCLKI),
472 ASPEED_PINCTRL_GROUP(VB0),
473 ASPEED_PINCTRL_GROUP(VB1),
474 ASPEED_PINCTRL_GROUP(VGADDC),
475 /* JTAG groups */
476 ASPEED_PINCTRL_GROUP(JTAG0),
477 /* PCIE RC groups */
478 ASPEED_PINCTRL_GROUP(PCIERC0PERST),
479 ASPEED_PINCTRL_GROUP(PCIERC1PERST),
480 /* USB3A groups */
481 ASPEED_PINCTRL_GROUP(USB3A),
482 ASPEED_PINCTRL_GROUP(USB3AAP),
483 ASPEED_PINCTRL_GROUP(USB3ABP),
484 /* USB3B groups */
485 ASPEED_PINCTRL_GROUP(USB3B),
486 ASPEED_PINCTRL_GROUP(USB3BAP),
487 ASPEED_PINCTRL_GROUP(USB3BBP),
488 /* USB2A groups */
489 ASPEED_PINCTRL_GROUP(USB2A),
490 ASPEED_PINCTRL_GROUP(USB2AAP),
491 ASPEED_PINCTRL_GROUP(USB2ABP),
492 ASPEED_PINCTRL_GROUP(USB2ADAP),
493 ASPEED_PINCTRL_GROUP(USB2AH),
494 ASPEED_PINCTRL_GROUP(USB2AHAP),
495 /* USB2B groups */
496 ASPEED_PINCTRL_GROUP(USB2B),
497 ASPEED_PINCTRL_GROUP(USB2BAP),
498 ASPEED_PINCTRL_GROUP(USB2BBP),
499 ASPEED_PINCTRL_GROUP(USB2BDBP),
500 ASPEED_PINCTRL_GROUP(USB2BH),
501 ASPEED_PINCTRL_GROUP(USB2BHBP),
502};
503
504static const struct aspeed_pin_function aspeed_g7_soc0_functions[] = {
505 ASPEED_PINCTRL_FUNC(EMMC),
506 ASPEED_PINCTRL_FUNC(TSPRSTN),
507 ASPEED_PINCTRL_FUNC(UFSCLKI),
508 ASPEED_PINCTRL_FUNC(VB),
509 ASPEED_PINCTRL_FUNC(VGADDC),
510 /* JTAG functions */
511 ASPEED_PINCTRL_FUNC(JTAGDDR),
512 ASPEED_PINCTRL_FUNC(JTAGM0),
513 ASPEED_PINCTRL_FUNC(JTAGPCIEA),
514 ASPEED_PINCTRL_FUNC(JTAGPCIEB),
515 ASPEED_PINCTRL_FUNC(JTAGPSP),
516 ASPEED_PINCTRL_FUNC(JTAGSSP),
517 ASPEED_PINCTRL_FUNC(JTAGTSP),
518 ASPEED_PINCTRL_FUNC(JTAGUSB3A),
519 ASPEED_PINCTRL_FUNC(JTAGUSB3B),
520 /* PCIE RC functions */
521 ASPEED_PINCTRL_FUNC(PCIERC0PERST),
522 ASPEED_PINCTRL_FUNC(PCIERC1PERST),
523 /* USB3A functions */
524 ASPEED_PINCTRL_FUNC(USB3AXH),
525 ASPEED_PINCTRL_FUNC(USB3AXH2B),
526 ASPEED_PINCTRL_FUNC(USB3AXHD),
527 ASPEED_PINCTRL_FUNC(USB3AXHP),
528 ASPEED_PINCTRL_FUNC(USB3AXHP2B),
529 ASPEED_PINCTRL_FUNC(USB3AXHPD),
530 /* USB3B functions */
531 ASPEED_PINCTRL_FUNC(USB3BXH),
532 ASPEED_PINCTRL_FUNC(USB3BXH2A),
533 ASPEED_PINCTRL_FUNC(USB3BXHD),
534 ASPEED_PINCTRL_FUNC(USB3BXHP),
535 ASPEED_PINCTRL_FUNC(USB3BXHP2A),
536 ASPEED_PINCTRL_FUNC(USB3BXHPD),
537 /* USB2A functions */
538 ASPEED_PINCTRL_FUNC(USB2AD0),
539 ASPEED_PINCTRL_FUNC(USB2AD1),
540 ASPEED_PINCTRL_FUNC(USB2AH),
541 ASPEED_PINCTRL_FUNC(USB2AHP),
542 ASPEED_PINCTRL_FUNC(USB2AHPD0),
543 ASPEED_PINCTRL_FUNC(USB2AXH),
544 ASPEED_PINCTRL_FUNC(USB2AXH2B),
545 ASPEED_PINCTRL_FUNC(USB2AXHD1),
546 ASPEED_PINCTRL_FUNC(USB2AXHP),
547 ASPEED_PINCTRL_FUNC(USB2AXHP2B),
548 ASPEED_PINCTRL_FUNC(USB2AXHPD1),
549 /* USB2B functions */
550 ASPEED_PINCTRL_FUNC(USB2BD0),
551 ASPEED_PINCTRL_FUNC(USB2BD1),
552 ASPEED_PINCTRL_FUNC(USB2BH),
553 ASPEED_PINCTRL_FUNC(USB2BHP),
554 ASPEED_PINCTRL_FUNC(USB2BHPD0),
555 ASPEED_PINCTRL_FUNC(USB2BXH),
556 ASPEED_PINCTRL_FUNC(USB2BXH2A),
557 ASPEED_PINCTRL_FUNC(USB2BXHD1),
558 ASPEED_PINCTRL_FUNC(USB2BXHP),
559 ASPEED_PINCTRL_FUNC(USB2BXHP2A),
560 ASPEED_PINCTRL_FUNC(USB2BXHPD1),
561};
562
563static const struct pinmux_ops aspeed_g7_soc0_pinmux_ops = {
564 .get_functions_count = aspeed_pinmux_get_fn_count,
565 .get_function_name = aspeed_pinmux_get_fn_name,
566 .get_function_groups = aspeed_pinmux_get_fn_groups,
567 .set_mux = aspeed_pinmux_set_mux,
568 .gpio_request_enable = aspeed_gpio_request_enable,
569 .strict = true,
570};
571
572static const struct pinctrl_ops aspeed_g7_soc0_pinctrl_ops = {
573 .get_groups_count = aspeed_pinctrl_get_groups_count,
574 .get_group_name = aspeed_pinctrl_get_group_name,
575 .get_group_pins = aspeed_pinctrl_get_group_pins,
576 .pin_dbg_show = aspeed_pinctrl_pin_dbg_show,
577 .dt_node_to_map = pinconf_generic_dt_node_to_map_all,
578 .dt_free_map = pinctrl_utils_free_map,
579};
580
581static const struct pinconf_ops aspeed_g7_soc0_pinconf_ops = {
582 .is_generic = true,
583 .pin_config_get = aspeed_pin_config_get,
584 .pin_config_set = aspeed_pin_config_set,
585 .pin_config_group_get = aspeed_pin_config_group_get,
586 .pin_config_group_set = aspeed_pin_config_group_set,
587};
588
589/* pinctrl_desc */
590static const struct pinctrl_desc aspeed_g7_soc0_pinctrl_desc = {
591 .name = "aspeed-g7-soc0-pinctrl",
592 .pins = aspeed_g7_soc0_pins,
593 .npins = ARRAY_SIZE(aspeed_g7_soc0_pins),
594 .pctlops = &aspeed_g7_soc0_pinctrl_ops,
595 .pmxops = &aspeed_g7_soc0_pinmux_ops,
596 .confops = &aspeed_g7_soc0_pinconf_ops,
597};
598
599static const struct aspeed_pin_config aspeed_g7_soc0_configs[] = {
600 /* GPIO18A */
601 { PIN_CONFIG_DRIVE_STRENGTH, { AC14, AC14 }, SCU480, GENMASK(3, 0) },
602 { PIN_CONFIG_BIAS_PULL_DOWN, { AC14, AC14 }, SCU480, GENMASK(5, 4) },
603 { PIN_CONFIG_BIAS_PULL_UP, { AC14, AC14 }, SCU480, GENMASK(5, 4) },
604 { PIN_CONFIG_BIAS_DISABLE, { AC14, AC14 }, SCU480, BIT(5) },
605 { PIN_CONFIG_DRIVE_STRENGTH, { AE15, AE15 }, SCU484, GENMASK(3, 0) },
606 { PIN_CONFIG_BIAS_PULL_DOWN, { AE15, AE15 }, SCU484, GENMASK(5, 4) },
607 { PIN_CONFIG_BIAS_PULL_UP, { AE15, AE15 }, SCU484, GENMASK(5, 4) },
608 { PIN_CONFIG_BIAS_DISABLE, { AE15, AE15 }, SCU484, BIT(5) },
609 { PIN_CONFIG_DRIVE_STRENGTH, { AD14, AD14 }, SCU488, GENMASK(3, 0) },
610 { PIN_CONFIG_BIAS_PULL_DOWN, { AD14, AD14 }, SCU488, GENMASK(5, 4) },
611 { PIN_CONFIG_BIAS_PULL_UP, { AD14, AD14 }, SCU488, GENMASK(5, 4) },
612 { PIN_CONFIG_BIAS_DISABLE, { AD14, AD14 }, SCU488, BIT(5) },
613 { PIN_CONFIG_DRIVE_STRENGTH, { AE14, AE14 }, SCU48C, GENMASK(3, 0) },
614 { PIN_CONFIG_BIAS_PULL_DOWN, { AE14, AE14 }, SCU48C, GENMASK(5, 4) },
615 { PIN_CONFIG_BIAS_PULL_UP, { AE14, AE14 }, SCU48C, GENMASK(5, 4) },
616 { PIN_CONFIG_BIAS_DISABLE, { AE14, AE14 }, SCU48C, BIT(5) },
617 { PIN_CONFIG_DRIVE_STRENGTH, { AF14, AF14 }, SCU490, GENMASK(3, 0) },
618 { PIN_CONFIG_BIAS_PULL_DOWN, { AF14, AF14 }, SCU490, GENMASK(5, 4) },
619 { PIN_CONFIG_BIAS_PULL_UP, { AF14, AF14 }, SCU490, GENMASK(5, 4) },
620 { PIN_CONFIG_BIAS_DISABLE, { AF14, AF14 }, SCU490, BIT(5) },
621 { PIN_CONFIG_DRIVE_STRENGTH, { AB13, AB13 }, SCU494, GENMASK(3, 0) },
622 { PIN_CONFIG_BIAS_PULL_DOWN, { AB13, AB13 }, SCU494, GENMASK(5, 4) },
623 { PIN_CONFIG_BIAS_PULL_UP, { AB13, AB13 }, SCU494, GENMASK(5, 4) },
624 { PIN_CONFIG_BIAS_DISABLE, { AB13, AB13 }, SCU494, BIT(5) },
625 { PIN_CONFIG_DRIVE_STRENGTH, { AB14, AB14 }, SCU498, GENMASK(3, 0) },
626 { PIN_CONFIG_BIAS_PULL_DOWN, { AB14, AB14 }, SCU498, GENMASK(5, 4) },
627 { PIN_CONFIG_BIAS_PULL_UP, { AB14, AB14 }, SCU498, GENMASK(5, 4) },
628 { PIN_CONFIG_BIAS_DISABLE, { AB14, AB14 }, SCU498, BIT(5) },
629 { PIN_CONFIG_DRIVE_STRENGTH, { AF15, AF15 }, SCU49C, GENMASK(3, 0) },
630 { PIN_CONFIG_BIAS_PULL_DOWN, { AF15, AF15 }, SCU49C, GENMASK(5, 4) },
631 { PIN_CONFIG_BIAS_PULL_UP, { AF15, AF15 }, SCU49C, GENMASK(5, 4) },
632 { PIN_CONFIG_BIAS_DISABLE, { AF15, AF15 }, SCU49C, BIT(5) },
633 /* GPIO18B */
634 { PIN_CONFIG_DRIVE_STRENGTH, { AF13, AF13 }, SCU4A0, GENMASK(3, 0) },
635 { PIN_CONFIG_BIAS_PULL_DOWN, { AF13, AF13 }, SCU4A0, GENMASK(5, 4) },
636 { PIN_CONFIG_BIAS_PULL_UP, { AF13, AF13 }, SCU4A0, GENMASK(5, 4) },
637 { PIN_CONFIG_BIAS_DISABLE, { AF13, AF13 }, SCU4A0, BIT(5) },
638 { PIN_CONFIG_DRIVE_STRENGTH, { AC13, AC13 }, SCU4A4, GENMASK(3, 0) },
639 { PIN_CONFIG_BIAS_PULL_DOWN, { AC13, AC13 }, SCU4A4, GENMASK(5, 4) },
640 { PIN_CONFIG_BIAS_PULL_UP, { AC13, AC13 }, SCU4A4, GENMASK(5, 4) },
641 { PIN_CONFIG_BIAS_DISABLE, { AC13, AC13 }, SCU4A4, BIT(5) },
642 { PIN_CONFIG_DRIVE_STRENGTH, { AD13, AD13 }, SCU4A8, GENMASK(3, 0) },
643 { PIN_CONFIG_BIAS_PULL_DOWN, { AD13, AD13 }, SCU4A8, GENMASK(5, 4) },
644 { PIN_CONFIG_BIAS_PULL_UP, { AD13, AD13 }, SCU4A8, GENMASK(5, 4) },
645 { PIN_CONFIG_BIAS_DISABLE, { AD13, AD13 }, SCU4A8, BIT(5) },
646 { PIN_CONFIG_DRIVE_STRENGTH, { AE13, AE13 }, SCU4AC, GENMASK(3, 0) },
647 { PIN_CONFIG_BIAS_PULL_DOWN, { AE13, AE13 }, SCU4AC, GENMASK(5, 4) },
648 { PIN_CONFIG_BIAS_PULL_UP, { AE13, AE13 }, SCU4AC, GENMASK(5, 4) },
649 { PIN_CONFIG_BIAS_DISABLE, { AE13, AE13 }, SCU4AC, BIT(5) },
650};
651
652static const struct aspeed_pin_config_map aspeed_g7_soc0_pin_config_map[] = {
653 { PIN_CONFIG_BIAS_PULL_DOWN, -1, 2, GENMASK(1, 0) },
654 { PIN_CONFIG_BIAS_PULL_UP, -1, 3, GENMASK(1, 0) },
655 { PIN_CONFIG_BIAS_DISABLE, -1, 0, BIT_MASK(0) },
656 { PIN_CONFIG_DRIVE_STRENGTH, 3, 0, GENMASK(3, 0) },
657 { PIN_CONFIG_DRIVE_STRENGTH, 6, 1, GENMASK(3, 0) },
658 { PIN_CONFIG_DRIVE_STRENGTH, 8, 2, GENMASK(3, 0) },
659 { PIN_CONFIG_DRIVE_STRENGTH, 11, 3, GENMASK(3, 0) },
660 { PIN_CONFIG_DRIVE_STRENGTH, 16, 4, GENMASK(3, 0) },
661 { PIN_CONFIG_DRIVE_STRENGTH, 18, 5, GENMASK(3, 0) },
662 { PIN_CONFIG_DRIVE_STRENGTH, 20, 6, GENMASK(3, 0) },
663 { PIN_CONFIG_DRIVE_STRENGTH, 23, 7, GENMASK(3, 0) },
664 { PIN_CONFIG_DRIVE_STRENGTH, 30, 8, GENMASK(3, 0) },
665 { PIN_CONFIG_DRIVE_STRENGTH, 32, 9, GENMASK(3, 0) },
666 { PIN_CONFIG_DRIVE_STRENGTH, 33, 10, GENMASK(3, 0) },
667 { PIN_CONFIG_DRIVE_STRENGTH, 35, 11, GENMASK(3, 0) },
668 { PIN_CONFIG_DRIVE_STRENGTH, 37, 12, GENMASK(3, 0) },
669 { PIN_CONFIG_DRIVE_STRENGTH, 38, 13, GENMASK(3, 0) },
670 { PIN_CONFIG_DRIVE_STRENGTH, 39, 14, GENMASK(3, 0) },
671 { PIN_CONFIG_DRIVE_STRENGTH, 41, 15, GENMASK(3, 0) },
672
673};
674
675static int aspeed_g7_soc0_sig_expr_set(struct aspeed_pinmux_data *ctx,
676 const struct aspeed_sig_expr *expr, bool enable)
677{
678 int ret;
679 int i;
680
681 for (i = 0; i < expr->ndescs; i++) {
682 const struct aspeed_sig_desc *desc = &expr->descs[i];
683 u32 pattern = enable ? desc->enable : desc->disable;
684 u32 val = (pattern << __ffs(desc->mask));
685
686 if (!ctx->maps[desc->ip])
687 return -ENODEV;
688
689 WARN_ON_ONCE(desc->ip != ASPEED_IP_SCU);
690
691 ret = regmap_update_bits(ctx->maps[desc->ip], desc->reg,
692 desc->mask, val);
693 if (ret)
694 return ret;
695 }
696
697 ret = aspeed_sig_expr_eval(ctx, expr, enable);
698 if (ret < 0)
699 return ret;
700
701 return ret ? 0 : -EPERM;
702}
703
704static const struct aspeed_pinmux_ops aspeed_g7_soc0_ops = {
705 .set = aspeed_g7_soc0_sig_expr_set,
706};
707
708static struct aspeed_pinctrl_data aspeed_g7_soc0_pinctrl_data = {
709 .pins = aspeed_g7_soc0_pins,
710 .npins = ARRAY_SIZE(aspeed_g7_soc0_pins),
711 .pinmux = {
712 .ops = &aspeed_g7_soc0_ops,
713 .groups = aspeed_g7_soc0_groups,
714 .ngroups = ARRAY_SIZE(aspeed_g7_soc0_groups),
715 .functions = aspeed_g7_soc0_functions,
716 .nfunctions = ARRAY_SIZE(aspeed_g7_soc0_functions),
717 },
718 .configs = aspeed_g7_soc0_configs,
719 .nconfigs = ARRAY_SIZE(aspeed_g7_soc0_configs),
720 .confmaps = aspeed_g7_soc0_pin_config_map,
721 .nconfmaps = ARRAY_SIZE(aspeed_g7_soc0_pin_config_map),
722};
723
724static int aspeed_g7_soc0_pinctrl_probe(struct platform_device *pdev)
725{
726 return aspeed_pinctrl_probe(pdev, &aspeed_g7_soc0_pinctrl_desc,
727 &aspeed_g7_soc0_pinctrl_data);
728}
729
730static const struct of_device_id aspeed_g7_soc0_pinctrl_match[] = {
731 { .compatible = "aspeed,ast2700-soc0-pinctrl" },
732 {}
733};
734MODULE_DEVICE_TABLE(of, aspeed_g7_soc0_pinctrl_match);
735
736static struct platform_driver aspeed_g7_soc0_pinctrl_driver = {
737 .probe = aspeed_g7_soc0_pinctrl_probe,
738 .driver = {
739 .name = "aspeed-g7-soc0-pinctrl",
740 .of_match_table = aspeed_g7_soc0_pinctrl_match,
741 .suppress_bind_attrs = true,
742 },
743};
744
745static int __init aspeed_g7_soc0_pinctrl_init(void)
746{
747 return platform_driver_register(&aspeed_g7_soc0_pinctrl_driver);
748}
749arch_initcall(aspeed_g7_soc0_pinctrl_init);
drivers/pinctrl/aspeed/pinctrl-aspeed-g7-soc1.c+1756−0
@@ -0,0 +1,1756 @@
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Pinctrl driver for Aspeed G7 SoC1
4 *
5 * Copyright (C) 2026 Aspeed Technology Inc.
6 */
7
8#include <linux/errno.h>
9#include <linux/mfd/syscon.h>
10#include <linux/module.h>
11#include <linux/of.h>
12#include <linux/pinctrl/pinconf-generic.h>
13#include <linux/pinctrl/pinconf.h>
14#include <linux/pinctrl/pinctrl.h>
15#include <linux/pinctrl/pinmux.h>
16#include <linux/platform_device.h>
17#include <linux/regmap.h>
18#include <linux/slab.h>
19
20#include "../core.h"
21#include "../pinconf.h"
22#include "../pinctrl-utils.h"
23#include "../pinmux.h"
24
25#define ASPEED_G7_SOC1_NR_PINS 220
26#define ASPEED_G7_SOC1_REG_WIDTH 32
27#define ASPEED_G7_SOC1_REG_STRIDE 4
28
29#define ASPEED_G7_SOC1_MUX_BASE 0x400
30#define ASPEED_G7_SOC1_BIAS_BASE 0x480
31#define ASPEED_G7_SOC1_DRV_BASE 0x4C0
32#define ASPEED_G7_SOC1_PCIE_REG 0x908
33#define ASPEED_G7_SOC1_USB_MODE_REG 0x3B0
34#define ASPEED_G7_SOC1_SGMII_REG 0x47C
35
36/*
37 * Each pin occupies a 4-bit slot in the MUX registers (MUX_BITS_PER_PIN),
38 * but only bits [2:0] select the mux function; bit 3 is reserved read-only
39 * and must not be written. MUX_FUNC_MASK therefore covers 3 bits, not 4.
40 */
41#define ASPEED_G7_SOC1_MUX_FUNC_MASK 0x7
42#define ASPEED_G7_SOC1_MUX_BITS_PER_PIN 4
43#define ASPEED_G7_SOC1_MUX_PINS_PER_REG \
44 (ASPEED_G7_SOC1_REG_WIDTH / ASPEED_G7_SOC1_MUX_BITS_PER_PIN)
45
46#define ASPEED_G7_SOC1_BIAS_FUNC_MASK 0x1
47#define ASPEED_G7_SOC1_BIAS_BITS_PER_PIN 1
48#define ASPEED_G7_SOC1_BIAS_PINS_PER_REG \
49 (ASPEED_G7_SOC1_REG_WIDTH / ASPEED_G7_SOC1_BIAS_BITS_PER_PIN)
50
51#define ASPEED_G7_SOC1_DRV_FUNC_MASK 0x3
52#define ASPEED_G7_SOC1_DRV_BITS_PER_PIN 2
53#define ASPEED_G7_SOC1_DRV_PINS_PER_REG \
54 (ASPEED_G7_SOC1_REG_WIDTH / ASPEED_G7_SOC1_DRV_BITS_PER_PIN)
55
56#define ASPEED_G7_SOC1_DRV_STRENGTH_STEP_MA 4
57#define ASPEED_G7_SOC1_DRV_STRENGTH_HW_BASE 1
58#define ASPEED_G7_SOC1_DRV_STRENGTH_MIN_MA \
59 (ASPEED_G7_SOC1_DRV_STRENGTH_HW_BASE * ASPEED_G7_SOC1_DRV_STRENGTH_STEP_MA)
60#define ASPEED_G7_SOC1_DRV_STRENGTH_MAX_MA \
61 ((ASPEED_G7_SOC1_DRV_FUNC_MASK + ASPEED_G7_SOC1_DRV_STRENGTH_HW_BASE) * \
62 ASPEED_G7_SOC1_DRV_STRENGTH_STEP_MA)
63
64/*
65 * NOTE: The numeric values of these enum entries are significant.
66 * They must match the SoC GPIO numbering / ball-to-GPIO ID mapping.
67 * Do not reorder alphabetically.
68 */
69enum {
70 C16,
71 C14,
72 C11,
73 D9,
74 F14,
75 D10,
76 C12,
77 C13,
78 AC26,
79 AA25,
80 AB23,
81 U22,
82 V21,
83 N26,
84 P25,
85 N25,
86 V23,
87 W22,
88 AB26,
89 AD26,
90 P26,
91 AE26,
92 AF26,
93 AF25,
94 AE25,
95 AD25,
96 AF23,
97 AF20,
98 AF21,
99 AE21,
100 AE23,
101 AD22,
102 AF17,
103 AA16,
104 Y16,
105 V17,
106 J13,
107 AB16,
108 AC16,
109 AF16,
110 AA15,
111 AB15,
112 AC15,
113 AD15,
114 Y15,
115 AA14,
116 W16,
117 V16,
118 AB18,
119 AC18,
120 K13,
121 AA17,
122 AB17,
123 AD16,
124 AC17,
125 AD17,
126 AE16,
127 AE17,
128 AB24,
129 W26,
130 HOLE0,
131 HOLE1,
132 HOLE2,
133 HOLE3,
134 W25,
135 Y23,
136 Y24,
137 W21,
138 AA23,
139 AC22,
140 AB22,
141 Y21,
142 AE20,
143 AF19,
144 Y22,
145 AA20,
146 AA22,
147 AB20,
148 AF18,
149 AE19,
150 AD20,
151 AC20,
152 AA21,
153 AB21,
154 AC19,
155 AE18,
156 AD19,
157 AD18,
158 U25,
159 U26,
160 Y26,
161 AA24,
162 R25,
163 AA26,
164 R26,
165 Y25,
166 B16,
167 D14,
168 B15,
169 B14,
170 C17,
171 B13,
172 E14,
173 C15,
174 D24,
175 B23,
176 B22,
177 C23,
178 B18,
179 B21,
180 M15,
181 B19,
182 B26,
183 A25,
184 A24,
185 B24,
186 E26,
187 A21,
188 A19,
189 A18,
190 D26,
191 C26,
192 A23,
193 A22,
194 B25,
195 F26,
196 A26,
197 A14,
198 E10,
199 E13,
200 D12,
201 F10,
202 E11,
203 F11,
204 F13,
205 N15,
206 C20,
207 C19,
208 A8,
209 R14,
210 A7,
211 P14,
212 D20,
213 A6,
214 B6,
215 N14,
216 B7,
217 B8,
218 B9,
219 M14,
220 J11,
221 E7,
222 D19,
223 B11,
224 D15,
225 B12,
226 B10,
227 P13,
228 C18,
229 C6,
230 C7,
231 D7,
232 N13,
233 C8,
234 C9,
235 C10,
236 M16,
237 A15,
238 G11,
239 H7,
240 H8,
241 H9,
242 H10,
243 H11,
244 J9,
245 J10,
246 E9,
247 F9,
248 F8,
249 M13,
250 F7,
251 D8,
252 E8,
253 L12,
254 F12,
255 E12,
256 J12,
257 G7,
258 G8,
259 G9,
260 G10,
261 K12,
262 W17,
263 V18,
264 W18,
265 Y17,
266 AA18,
267 AA13,
268 Y18,
269 AA12,
270 W20,
271 V20,
272 Y11,
273 V14,
274 V19,
275 W14,
276 Y20,
277 AB19,
278 U21,
279 T24,
280 V24,
281 V22,
282 T23,
283 AC25,
284 AB25,
285 AC24,
286 PCIERC2_PERST,
287 PORTC_MODE,
288 PORTD_MODE,
289 SGMII0,
290};
291
292struct aspeed_g7_soc1_pinctrl {
293 struct device *dev;
294 struct regmap *regmap;
295 struct pinctrl_dev *pctl;
296};
297
298struct aspeed_g7_field {
299 unsigned int reg;
300 unsigned int shift;
301 unsigned int mask;
302};
303
304static struct aspeed_g7_field
305aspeed_g7_soc1_pinmux_field_from_pin(unsigned int pin)
306{
307 return (struct aspeed_g7_field){
308 .reg = ASPEED_G7_SOC1_MUX_BASE +
309 (pin / ASPEED_G7_SOC1_MUX_PINS_PER_REG) *
310 ASPEED_G7_SOC1_REG_STRIDE,
311 .shift = (pin % ASPEED_G7_SOC1_MUX_PINS_PER_REG) *
312 ASPEED_G7_SOC1_MUX_BITS_PER_PIN,
313 .mask = ASPEED_G7_SOC1_MUX_FUNC_MASK,
314 };
315}
316
317static struct aspeed_g7_field
318aspeed_g7_soc1_bias_field_from_pin(unsigned int pin)
319{
320 return (struct aspeed_g7_field){
321 .reg = ASPEED_G7_SOC1_BIAS_BASE +
322 (pin / ASPEED_G7_SOC1_BIAS_PINS_PER_REG) *
323 ASPEED_G7_SOC1_REG_STRIDE,
324 .shift = pin % ASPEED_G7_SOC1_BIAS_PINS_PER_REG,
325 .mask = ASPEED_G7_SOC1_BIAS_FUNC_MASK,
326 };
327}
328
329static struct aspeed_g7_field
330aspeed_g7_soc1_drv_field_from_idx(unsigned int idx)
331{
332 return (struct aspeed_g7_field){
333 .reg = ASPEED_G7_SOC1_DRV_BASE +
334 (idx / ASPEED_G7_SOC1_DRV_PINS_PER_REG) *
335 ASPEED_G7_SOC1_REG_STRIDE,
336 .shift = (idx % ASPEED_G7_SOC1_DRV_PINS_PER_REG) *
337 ASPEED_G7_SOC1_DRV_BITS_PER_PIN,
338 .mask = ASPEED_G7_SOC1_DRV_FUNC_MASK,
339 };
340}
341
342#define PIN(n) PINCTRL_PIN(n, #n)
343
344static const struct pinctrl_pin_desc aspeed_g7_soc1_pins[] = {
345 PIN(C16),
346 PIN(C14),
347 PIN(C11),
348 PIN(D9),
349 PIN(F14),
350 PIN(D10),
351 PIN(C12),
352 PIN(C13),
353 PIN(AC26),
354 PIN(AA25),
355 PIN(AB23),
356 PIN(U22),
357 PIN(V21),
358 PIN(N26),
359 PIN(P25),
360 PIN(N25),
361 PIN(V23),
362 PIN(W22),
363 PIN(AB26),
364 PIN(AD26),
365 PIN(P26),
366 PIN(AE26),
367 PIN(AF26),
368 PIN(AF25),
369 PIN(AE25),
370 PIN(AD25),
371 PIN(AF23),
372 PIN(AF20),
373 PIN(AF21),
374 PIN(AE21),
375 PIN(AE23),
376 PIN(AD22),
377 PIN(AF17),
378 PIN(AA16),
379 PIN(Y16),
380 PIN(V17),
381 PIN(J13),
382 PIN(AB16),
383 PIN(AC16),
384 PIN(AF16),
385 PIN(AA15),
386 PIN(AB15),
387 PIN(AC15),
388 PIN(AD15),
389 PIN(Y15),
390 PIN(AA14),
391 PIN(W16),
392 PIN(V16),
393 PIN(AB18),
394 PIN(AC18),
395 PIN(K13),
396 PIN(AA17),
397 PIN(AB17),
398 PIN(AD16),
399 PIN(AC17),
400 PIN(AD17),
401 PIN(AE16),
402 PIN(AE17),
403 PIN(AB24),
404 PIN(W26),
405 PIN(HOLE0),
406 PIN(HOLE1),
407 PIN(HOLE2),
408 PIN(HOLE3),
409 PIN(W25),
410 PIN(Y23),
411 PIN(Y24),
412 PIN(W21),
413 PIN(AA23),
414 PIN(AC22),
415 PIN(AB22),
416 PIN(Y21),
417 PIN(AE20),
418 PIN(AF19),
419 PIN(Y22),
420 PIN(AA20),
421 PIN(AA22),
422 PIN(AB20),
423 PIN(AF18),
424 PIN(AE19),
425 PIN(AD20),
426 PIN(AC20),
427 PIN(AA21),
428 PIN(AB21),
429 PIN(AC19),
430 PIN(AE18),
431 PIN(AD19),
432 PIN(AD18),
433 PIN(U25),
434 PIN(U26),
435 PIN(Y26),
436 PIN(AA24),
437 PIN(R25),
438 PIN(AA26),
439 PIN(R26),
440 PIN(Y25),
441 PIN(B16),
442 PIN(D14),
443 PIN(B15),
444 PIN(B14),
445 PIN(C17),
446 PIN(B13),
447 PIN(E14),
448 PIN(C15),
449 PIN(D24),
450 PIN(B23),
451 PIN(B22),
452 PIN(C23),
453 PIN(B18),
454 PIN(B21),
455 PIN(M15),
456 PIN(B19),
457 PIN(B26),
458 PIN(A25),
459 PIN(A24),
460 PIN(B24),
461 PIN(E26),
462 PIN(A21),
463 PIN(A19),
464 PIN(A18),
465 PIN(D26),
466 PIN(C26),
467 PIN(A23),
468 PIN(A22),
469 PIN(B25),
470 PIN(F26),
471 PIN(A26),
472 PIN(A14),
473 PIN(E10),
474 PIN(E13),
475 PIN(D12),
476 PIN(F10),
477 PIN(E11),
478 PIN(F11),
479 PIN(F13),
480 PIN(N15),
481 PIN(C20),
482 PIN(C19),
483 PIN(A8),
484 PIN(R14),
485 PIN(A7),
486 PIN(P14),
487 PIN(D20),
488 PIN(A6),
489 PIN(B6),
490 PIN(N14),
491 PIN(B7),
492 PIN(B8),
493 PIN(B9),
494 PIN(M14),
495 PIN(J11),
496 PIN(E7),
497 PIN(D19),
498 PIN(B11),
499 PIN(D15),
500 PIN(B12),
501 PIN(B10),
502 PIN(P13),
503 PIN(C18),
504 PIN(C6),
505 PIN(C7),
506 PIN(D7),
507 PIN(N13),
508 PIN(C8),
509 PIN(C9),
510 PIN(C10),
511 PIN(M16),
512 PIN(A15),
513 PIN(G11),
514 PIN(H7),
515 PIN(H8),
516 PIN(H9),
517 PIN(H10),
518 PIN(H11),
519 PIN(J9),
520 PIN(J10),
521 PIN(E9),
522 PIN(F9),
523 PIN(F8),
524 PIN(M13),
525 PIN(F7),
526 PIN(D8),
527 PIN(E8),
528 PIN(L12),
529 PIN(F12),
530 PIN(E12),
531 PIN(J12),
532 PIN(G7),
533 PIN(G8),
534 PIN(G9),
535 PIN(G10),
536 PIN(K12),
537 PIN(W17),
538 PIN(V18),
539 PIN(W18),
540 PIN(Y17),
541 PIN(AA18),
542 PIN(AA13),
543 PIN(Y18),
544 PIN(AA12),
545 PIN(W20),
546 PIN(V20),
547 PIN(Y11),
548 PIN(V14),
549 PIN(V19),
550 PIN(W14),
551 PIN(Y20),
552 PIN(AB19),
553 PIN(U21),
554 PIN(T24),
555 PIN(V24),
556 PIN(V22),
557 PIN(T23),
558 PIN(AC25),
559 PIN(AB25),
560 PIN(AC24),
561 PIN(PCIERC2_PERST),
562 PIN(PORTC_MODE),
563 PIN(PORTD_MODE),
564 PIN(SGMII0),
565};
566
567static const struct pinctrl_ops aspeed_g7_soc1_pctl_ops = {
568 .get_groups_count = pinctrl_generic_get_group_count,
569 .get_group_name = pinctrl_generic_get_group_name,
570 .get_group_pins = pinctrl_generic_get_group_pins,
571 .dt_node_to_map = pinconf_generic_dt_node_to_map_all,
572 .dt_free_map = pinctrl_utils_free_map,
573};
574
575struct aspeed_g7_soc1_function {
576 struct pinfunction pinfunction;
577 const u8 *muxvals;
578};
579
580static int aspeed_g7_soc1_drive_strength_to_hw(u32 strength,
581 unsigned int *val)
582{
583 if (strength < ASPEED_G7_SOC1_DRV_STRENGTH_MIN_MA ||
584 strength > ASPEED_G7_SOC1_DRV_STRENGTH_MAX_MA ||
585 strength % ASPEED_G7_SOC1_DRV_STRENGTH_STEP_MA)
586 return -EINVAL;
587
588 *val = (strength / ASPEED_G7_SOC1_DRV_STRENGTH_STEP_MA) -
589 ASPEED_G7_SOC1_DRV_STRENGTH_HW_BASE;
590
591 return 0;
592}
593
594static int aspeed_g7_soc1_set_mux(struct pinctrl_dev *pctldev,
595 unsigned int fselector, unsigned int group)
596{
597 struct aspeed_g7_soc1_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
598 const struct aspeed_g7_soc1_function *soc1_func;
599 const struct function_desc *fd;
600 const struct pinfunction *func;
601 const struct pingroup *grp;
602 struct group_desc *gd;
603 const char *gname;
604 int i, g_idx = -1, ret;
605
606 gd = pinctrl_generic_get_group(pctldev, group);
607 if (!gd)
608 return -EINVAL;
609
610 grp = &gd->grp;
611
612 fd = pinmux_generic_get_function(pctldev, fselector);
613 if (!fd)
614 return -EINVAL;
615
616 soc1_func = fd->data;
617 if (!soc1_func)
618 return -EINVAL;
619
620 func = &soc1_func->pinfunction;
621 gname = grp->name;
622
623 for (i = 0; i < func->ngroups; i++) {
624 if (!strcmp(gname, func->groups[i])) {
625 g_idx = i;
626 break;
627 }
628 }
629
630 if (g_idx < 0)
631 return -EINVAL;
632
633 for (i = 0; i < grp->npins; i++) {
634 unsigned int val = soc1_func->muxvals[g_idx];
635 unsigned int pin = grp->pins[i];
636 struct aspeed_g7_field field;
637
638 if (pin == PCIERC2_PERST) {
639 /*
640 * PCIERC2_PERST is a special case: it is managed by a
641 * dedicated control register (0x908) instead of the
642 * standard 4-bit multi-function field.
643 */
644 field.reg = ASPEED_G7_SOC1_PCIE_REG;
645 field.shift = 0;
646 field.mask = 0x1;
647 val = 1;
648 } else if (pin == PORTC_MODE || pin == PORTD_MODE) {
649 /*
650 * PORTC_MODE and PORTD_MODE are virtual "pins" that
651 * control the USB 2.0 controller mode settings.
652 * These reside in a specific control register (0x3B0)
653 * with non-standard bit widths.
654 */
655 field.reg = ASPEED_G7_SOC1_USB_MODE_REG;
656 field.mask = 0x3;
657 field.shift = pin == PORTC_MODE ? 0 : 2;
658 } else if (pin == SGMII0) {
659 /*
660 * SGMII0 is a virtual pin whose mux control resides at
661 * SCU47C bit 0, outside the contiguous pin-indexed MUX
662 * register range starting at MUX_BASE. The field is
663 * 1 bit wide; use a 1-bit mask to avoid clobbering
664 * adjacent bits in SCU47C.
665 */
666 field.reg = ASPEED_G7_SOC1_SGMII_REG;
667 field.shift = 0;
668 field.mask = 0x1;
669 } else {
670 /* Standard 4-bit-per-pin multi-function configuration */
671 field = aspeed_g7_soc1_pinmux_field_from_pin(pin);
672 }
673
674 dev_dbg(pctl->dev,
675 "Setting pin %u reg 0x%x shift %u to function %s (muxval=0x%x)\n",
676 pin, field.reg, field.shift, func->name, val);
677
678 ret = regmap_update_bits(pctl->regmap, field.reg,
679 field.mask << field.shift,
680 val << field.shift);
681 if (ret)
682 return ret;
683 }
684
685 return 0;
686}
687
688static int aspeed_g7_soc1_gpio_request_enable(struct pinctrl_dev *pctldev,
689 struct pinctrl_gpio_range *range,
690 unsigned int pin)
691{
692 struct aspeed_g7_soc1_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
693 struct aspeed_g7_field field;
694 unsigned int val = 0;
695 int ret = -ENOTSUPP;
696
697 if (pin <= AC24) {
698 /*
699 * Balls W17 through AB19 are the ADC-capable pins: mux
700 * function 0 selects the ADC input and function 1 selects
701 * GPIO, unlike all other pins where function 0 is GPIO.
702 */
703 if (pin >= W17 && pin <= AB19)
704 val = 1;
705 field = aspeed_g7_soc1_pinmux_field_from_pin(pin);
706 ret = regmap_update_bits(pctl->regmap, field.reg,
707 field.mask << field.shift,
708 val << field.shift);
709 }
710
711 return ret;
712}
713
714static const struct pinmux_ops aspeed_g7_soc1_pmx_ops = {
715 .get_functions_count = pinmux_generic_get_function_count,
716 .get_function_name = pinmux_generic_get_function_name,
717 .get_function_groups = pinmux_generic_get_function_groups,
718 .set_mux = aspeed_g7_soc1_set_mux,
719 .gpio_request_enable = aspeed_g7_soc1_gpio_request_enable,
720 .strict = true,
721};
722
723/*
724 * aspeed_g7_soc1_drv_map - Mapping table for pin drive strength control.
725 *
726 * In AST2700 SOC1, drive strength configuration is architecturally decoupled
727 * from the main pin mux registers (0x400 range). It is managed by a separate
728 * set of registers starting at 0x4C0.
729 *
730 * This table is required because:
731 * 1. The mapping between physical pin IDs and drive strength control slots
732 * is non-linear and sparse.
733 * For example, W25 maps to field index 8 (stored as 9),
734 * meaning it occupies bits [17:16] of the first 0x4C0 register.
735 * 2. Only a subset of physical pins supports drive strength configuration.
736 *
737 * The table stores (drive strength field index + 1).
738 * The field index refers to the 2-bit drive strength field position within the
739 * 0x4C0 register range. A value of 0 indicates that the pin does not support
740 * drive strength configuration (returning -ENOTSUPP).
741 * This +1 offset allows us to rely on C's default zero-initialization for
742 * unsupported pins while avoiding compiler warnings regarding overridden
743 * initializers.
744 */
745static const int aspeed_g7_soc1_drv_map[ASPEED_G7_SOC1_NR_PINS] = {
746 [C16] = 1, [C14] = 2, [C11] = 3, [D9] = 4, [F14] = 5, [D10] = 6, [C12] = 7,
747 [C13] = 8, [W25] = 9, [Y23] = 10, [Y24] = 11, [W21] = 12, [AA23] = 13, [AC22] = 14,
748 [AB22] = 15, [Y21] = 16, [AE20] = 17, [AF19] = 18, [Y22] = 19, [AA20] = 20, [AA22] = 21,
749 [AB20] = 22, [AF18] = 23, [AE19] = 24, [AD20] = 25, [AC20] = 26, [AA21] = 27, [AB21] = 28,
750 [AC19] = 29, [AE18] = 30, [AD19] = 31, [AD18] = 32, [U25] = 33, [U26] = 34, [Y26] = 35,
751 [AA24] = 36, [R25] = 37, [AA26] = 38, [R26] = 39, [Y25] = 40, [B16] = 41, [D14] = 42,
752 [B15] = 43, [B14] = 44, [C17] = 45, [B13] = 46, [E14] = 47, [C15] = 48, [D24] = 49,
753 [B23] = 50, [B22] = 51, [C23] = 52, [B18] = 53, [B21] = 54, [M15] = 55, [B19] = 56,
754 [B26] = 57, [A25] = 58, [A24] = 59, [B24] = 60, [E26] = 61, [A21] = 62, [A19] = 63,
755 [A18] = 64, [D26] = 65, [C26] = 66, [A23] = 67, [A22] = 68, [B25] = 69, [F26] = 70,
756 [A26] = 71, [A14] = 72, [E10] = 73, [E13] = 74, [D12] = 75, [F10] = 76, [E11] = 77,
757 [F11] = 78, [F13] = 79, [N15] = 80, [C20] = 81, [C19] = 82, [A8] = 83, [R14] = 84,
758 [A7] = 85, [P14] = 86, [D20] = 87, [A6] = 88, [B6] = 89, [N14] = 90, [B7] = 91,
759 [B8] = 92, [B9] = 93, [M14] = 94, [J11] = 95, [E7] = 96, [D19] = 97, [B11] = 98,
760 [D15] = 99, [B12] = 100, [B10] = 101, [P13] = 102, [C18] = 103, [C6] = 104, [C7] = 105,
761 [D7] = 106, [N13] = 107, [C8] = 108, [C9] = 109, [C10] = 110, [M16] = 111, [A15] = 112,
762 [E9] = 113, [F9] = 114, [F8] = 115, [M13] = 116, [F7] = 117, [D8] = 118, [E8] = 119,
763 [L12] = 120,
764};
765
766static int aspeed_g7_soc1_pin_config_get(struct pinctrl_dev *pctldev,
767 unsigned int pin,
768 unsigned long *config)
769{
770 struct aspeed_g7_soc1_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
771 enum pin_config_param param = pinconf_to_config_param(*config);
772 struct aspeed_g7_field field;
773 unsigned int val, val_raw;
774 int ret, ds_idx;
775
776 if (pin > AC24)
777 return -EINVAL;
778
779 switch (param) {
780 case PIN_CONFIG_BIAS_DISABLE:
781 field = aspeed_g7_soc1_bias_field_from_pin(pin);
782 break;
783 case PIN_CONFIG_BIAS_PULL_DOWN:
784 case PIN_CONFIG_BIAS_PULL_UP:
785 /*
786 * The hardware has a single 1-bit enable/disable field per
787 * pin; pull direction is fixed in silicon and cannot be read
788 * back from the register. Reject readback requests for a
789 * specific pull direction.
790 */
791 return -ENOTSUPP;
792 case PIN_CONFIG_DRIVE_STRENGTH:
793 ds_idx = aspeed_g7_soc1_drv_map[pin];
794 if (!ds_idx)
795 return -ENOTSUPP;
796 ds_idx--; /* Adjust back to 0-based hardware index */
797 field = aspeed_g7_soc1_drv_field_from_idx(ds_idx);
798 break;
799 default:
800 return -ENOTSUPP;
801 }
802
803 ret = regmap_read(pctl->regmap, field.reg, &val_raw);
804 if (ret)
805 return ret;
806
807 val = (val_raw & (field.mask << field.shift)) >> field.shift;
808 if (param == PIN_CONFIG_DRIVE_STRENGTH)
809 val = (val + ASPEED_G7_SOC1_DRV_STRENGTH_HW_BASE) *
810 ASPEED_G7_SOC1_DRV_STRENGTH_STEP_MA;
811
812 if (!val)
813 return -EINVAL;
814
815 *config = pinconf_to_config_packed(param, val);
816
817 return 0;
818}
819
820static int aspeed_g7_soc1_pin_config_set(struct pinctrl_dev *pctldev,
821 unsigned int pin,
822 unsigned long *configs,
823 unsigned int num_configs)
824{
825 struct aspeed_g7_soc1_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
826 struct aspeed_g7_field field;
827 enum pin_config_param param;
828 int i, ret, ds_idx;
829 unsigned int val;
830 u32 arg;
831
832 if (pin > AC24)
833 return -EINVAL;
834
835 for (i = 0; i < num_configs; i++) {
836 param = pinconf_to_config_param(configs[i]);
837 arg = pinconf_to_config_argument(configs[i]);
838
839 switch (param) {
840 case PIN_CONFIG_BIAS_PULL_DOWN:
841 case PIN_CONFIG_BIAS_PULL_UP:
842 /*
843 * The hardware has one enable/disable bit per pin;
844 * pull direction is fixed in silicon. Both PULL_UP
845 * and PULL_DOWN map to "enable bias"; the caller must
846 * request the direction that the hardware provides.
847 */
848 case PIN_CONFIG_BIAS_DISABLE:
849 field = aspeed_g7_soc1_bias_field_from_pin(pin);
850 val = (param == PIN_CONFIG_BIAS_DISABLE) ? 1 : 0;
851 break;
852 case PIN_CONFIG_DRIVE_STRENGTH:
853 ds_idx = aspeed_g7_soc1_drv_map[pin];
854 if (!ds_idx)
855 return -ENOTSUPP;
856 ds_idx--; /* Adjust back to 0-based hardware index */
857 field = aspeed_g7_soc1_drv_field_from_idx(ds_idx);
858 ret = aspeed_g7_soc1_drive_strength_to_hw(arg, &val);
859 if (ret)
860 return ret;
861 break;
862 default:
863 return -ENOTSUPP;
864 }
865
866 dev_dbg(pctl->dev,
867 "Configuring pin %u reg 0x%x shift %u param %d arg %u val 0x%x\n",
868 pin, field.reg, field.shift, param, arg, val);
869
870 ret = regmap_update_bits(pctl->regmap, field.reg,
871 field.mask << field.shift,
872 val << field.shift);
873
874 if (ret)
875 return ret;
876 }
877
878 return 0;
879}
880
881static int aspeed_g7_soc1_pin_config_group_get(struct pinctrl_dev *pctldev,
882 unsigned int selector,
883 unsigned long *config)
884{
885 const unsigned int *pins;
886 unsigned int npins;
887 int ret;
888
889 ret = pinctrl_generic_get_group_pins(pctldev, selector, &pins, &npins);
890 if (ret)
891 return ret;
892 if (!npins)
893 return -ENODEV;
894
895 return aspeed_g7_soc1_pin_config_get(pctldev, pins[0], config);
896}
897
898static int aspeed_g7_soc1_pin_config_group_set(struct pinctrl_dev *pctldev,
899 unsigned int selector,
900 unsigned long *configs,
901 unsigned int num_configs)
902{
903 const unsigned int *pins;
904 unsigned int npins;
905 int ret;
906 int i;
907
908 ret = pinctrl_generic_get_group_pins(pctldev, selector, &pins, &npins);
909 if (ret)
910 return ret;
911
912 for (i = 0; i < npins; i++) {
913 ret = aspeed_g7_soc1_pin_config_set(pctldev, pins[i], configs,
914 num_configs);
915 if (ret)
916 return ret;
917 }
918
919 return 0;
920}
921
922static const struct pinconf_ops aspeed_g7_soc1_conf_ops = {
923 .is_generic = true,
924 .pin_config_get = aspeed_g7_soc1_pin_config_get,
925 .pin_config_set = aspeed_g7_soc1_pin_config_set,
926 .pin_config_group_get = aspeed_g7_soc1_pin_config_group_get,
927 .pin_config_group_set = aspeed_g7_soc1_pin_config_group_set,
928 .pin_config_config_dbg_show = pinconf_generic_dump_config,
929};
930
931static const struct pinctrl_desc aspeed_g7_soc1_desc = {
932 .name = "aspeed-g7-soc1-pinctrl",
933 .pins = aspeed_g7_soc1_pins,
934 .npins = ARRAY_SIZE(aspeed_g7_soc1_pins),
935 .pctlops = &aspeed_g7_soc1_pctl_ops,
936 .pmxops = &aspeed_g7_soc1_pmx_ops,
937 .confops = &aspeed_g7_soc1_conf_ops,
938 .owner = THIS_MODULE,
939};
940
941 #define PIN_GROUP(name, ...) static const unsigned int name ## _pins[] = { __VA_ARGS__ }
942
943/* Pin Groups and Functions */
944PIN_GROUP(ADC0, W17);
945PIN_GROUP(ADC1, V18);
946PIN_GROUP(ADC10, Y11);
947PIN_GROUP(ADC11, V14);
948PIN_GROUP(ADC12, V19);
949PIN_GROUP(ADC13, W14);
950PIN_GROUP(ADC14, Y20);
951PIN_GROUP(ADC15, AB19);
952PIN_GROUP(ADC2, W18);
953PIN_GROUP(ADC3, Y17);
954PIN_GROUP(ADC4, AA18);
955PIN_GROUP(ADC5, AA13);
956PIN_GROUP(ADC6, Y18);
957PIN_GROUP(ADC7, AA12);
958PIN_GROUP(ADC8, W20);
959PIN_GROUP(ADC9, V20);
960PIN_GROUP(AUXPWRGOOD0, W14);
961PIN_GROUP(AUXPWRGOOD1, Y20);
962PIN_GROUP(CANBUS, G7, G8, G9);
963PIN_GROUP(DI2C0, C16, D9);
964PIN_GROUP(DI2C1, C14, F14);
965PIN_GROUP(DI2C10, R25, AA26);
966PIN_GROUP(DI2C11, R26, Y25);
967PIN_GROUP(DI2C12, W25, Y23);
968PIN_GROUP(DI2C13, Y24, W21);
969PIN_GROUP(DI2C14, AA23, AC22);
970PIN_GROUP(DI2C15, AB22, Y21);
971PIN_GROUP(DI2C2, D10, C12);
972PIN_GROUP(DI2C3, C11, C13);
973PIN_GROUP(DI2C8, U25, U26);
974PIN_GROUP(DI2C9, Y26, AA24);
975PIN_GROUP(DSGPM0, D19, B10, C7, D7);
976PIN_GROUP(ESPI0, B16, D14, B15, B14, C17, B13, E14, C15);
977PIN_GROUP(ESPI1, C16, C14, C11, D9, F14, D10, C12, C13);
978PIN_GROUP(FSI0, AD20, AC20);
979PIN_GROUP(FSI1, AA21, AB21);
980PIN_GROUP(FSI2, AC19, AE18);
981PIN_GROUP(FSI3, AD19, AD18);
982PIN_GROUP(FWQSPI, M16, A15);
983PIN_GROUP(FWSPIABR, A14);
984PIN_GROUP(FWWPN, N15);
985PIN_GROUP(HBLED, V24);
986PIN_GROUP(HVI3C0, U25, U26);
987PIN_GROUP(HVI3C1, Y26, AA24);
988PIN_GROUP(HVI3C12, W25, Y23);
989PIN_GROUP(HVI3C13, Y24, W21);
990PIN_GROUP(HVI3C14, AA23, AC22);
991PIN_GROUP(HVI3C15, AB22, Y21);
992PIN_GROUP(HVI3C2, R25, AA26);
993PIN_GROUP(HVI3C3, R26, Y25);
994PIN_GROUP(I2C0, G11, H7);
995PIN_GROUP(I2C1, H8, H9);
996PIN_GROUP(I2C10, G8, G9);
997PIN_GROUP(I2C11, G10, K12);
998PIN_GROUP(I2C12, AC18, AA17);
999PIN_GROUP(I2C13, AB17, AD16);
1000PIN_GROUP(I2C14, AC17, AD17);
1001PIN_GROUP(I2C15, AE16, AE17);
1002PIN_GROUP(I2C2, H10, H11);
1003PIN_GROUP(I2C3, J9, J10);
1004PIN_GROUP(I2C4, E9, F9);
1005PIN_GROUP(I2C5, F8, M13);
1006PIN_GROUP(I2C6, F7, D8);
1007PIN_GROUP(I2C7, E8, L12);
1008PIN_GROUP(I2C8, F12, E12);
1009PIN_GROUP(I2C9, J12, G7);
1010PIN_GROUP(I2CF0, F12, E12, J12, G7);
1011PIN_GROUP(I2CF1, E9, F9, F8, M13);
1012PIN_GROUP(I2CF2, F7, D8, E8, L12);
1013PIN_GROUP(I3C10, AC19, AE18);
1014PIN_GROUP(I3C11, AD19, AD18);
1015PIN_GROUP(I3C4, AE20, AF19);
1016PIN_GROUP(I3C5, Y22, AA20);
1017PIN_GROUP(I3C6, AA22, AB20);
1018PIN_GROUP(I3C7, AF18, AE19);
1019PIN_GROUP(I3C8, AD20, AC20);
1020PIN_GROUP(I3C9, AA21, AB21);
1021PIN_GROUP(JTAGM1, D12, F10, E11, F11, F13);
1022PIN_GROUP(LPC0, AF26, AF25, B16, D14, B15, B14, C17, B13, E14, C15);
1023PIN_GROUP(LPC1, C16, C14, C11, D9, F14, D10, C12, C13, AE16, AE17);
1024PIN_GROUP(LTPI, U25, U26, Y26, AA24);
1025PIN_GROUP(LTPI_PS_I2C0, G11, H7);
1026PIN_GROUP(LTPI_PS_I2C1, H8, H9);
1027PIN_GROUP(LTPI_PS_I2C2, H10, H11);
1028PIN_GROUP(LTPI_PS_I2C3, J9, J10);
1029PIN_GROUP(MACLINK0, U21);
1030PIN_GROUP(MACLINK1, AC24);
1031PIN_GROUP(MACLINK2, T24);
1032PIN_GROUP(MDIO0, B9, M14);
1033PIN_GROUP(MDIO1, C9, C10);
1034PIN_GROUP(MDIO2, E10, E13);
1035PIN_GROUP(NCTS0, AF17);
1036PIN_GROUP(NCTS1, AA15);
1037PIN_GROUP(NCTS5, V21);
1038PIN_GROUP(NCTS6, AB26);
1039PIN_GROUP(NDCD0, AA16);
1040PIN_GROUP(NDCD1, AB15);
1041PIN_GROUP(NDCD5, N26);
1042PIN_GROUP(NDCD6, AD26);
1043PIN_GROUP(NDSR0, Y16);
1044PIN_GROUP(NDSR1, AC15);
1045PIN_GROUP(NDSR5, P25);
1046PIN_GROUP(NDSR6, P26);
1047PIN_GROUP(NDTR0, J13);
1048PIN_GROUP(NDTR1, Y15);
1049PIN_GROUP(NDTR5, V23);
1050PIN_GROUP(NDTR6, AF26);
1051PIN_GROUP(NRI0, V17);
1052PIN_GROUP(NRI1, AD15);
1053PIN_GROUP(NRI5, N25);
1054PIN_GROUP(NRI6, AE26);
1055PIN_GROUP(NRTS0, AB16);
1056PIN_GROUP(NRTS1, AA14);
1057PIN_GROUP(NRTS5, W22);
1058PIN_GROUP(NRTS6, AF25);
1059PIN_GROUP(OSCCLK, C17);
1060PIN_GROUP(PE2SGRSTN, E10, PCIERC2_PERST);
1061PIN_GROUP(PWM0, AE25);
1062PIN_GROUP(PWM1, AD25);
1063PIN_GROUP(PWM10, AB17);
1064PIN_GROUP(PWM11, AD16);
1065PIN_GROUP(PWM12, AC17);
1066PIN_GROUP(PWM13, AD17);
1067PIN_GROUP(PWM14, AE16);
1068PIN_GROUP(PWM15, AE17);
1069PIN_GROUP(PWM2, AF23);
1070PIN_GROUP(PWM3, AF20);
1071PIN_GROUP(PWM4, AF21);
1072PIN_GROUP(PWM5, AE21);
1073PIN_GROUP(PWM6, AE23);
1074PIN_GROUP(PWM7, AD22);
1075PIN_GROUP(PWM8, K13);
1076PIN_GROUP(PWM9, AA17);
1077PIN_GROUP(QSPI0, C23, B18);
1078PIN_GROUP(QSPI1, B24, E26);
1079PIN_GROUP(QSPI2, B25, F26);
1080PIN_GROUP(RGMII0, C20, C19, A8, R14, A7, P14, D20, A6, B6, N14, B7, B8);
1081PIN_GROUP(RGMII1, D19, B11, D15, B12, B10, P13, C18, C6, C7, D7, N13, C8);
1082PIN_GROUP(RMII0, C20, A8, R14, A7, P14, A6, B6, N14);
1083PIN_GROUP(RMII0RCLKO, D20);
1084PIN_GROUP(RMII1, D19, D15, B12, B10, P13, C6, C7, D7);
1085PIN_GROUP(RMII1RCLKO, C18);
1086PIN_GROUP(SALT0, AC17);
1087PIN_GROUP(SALT1, AD17);
1088PIN_GROUP(SALT10, Y18);
1089PIN_GROUP(SALT11, AA12);
1090PIN_GROUP(SALT12, AB26);
1091PIN_GROUP(SALT13, AD26);
1092PIN_GROUP(SALT14, P26);
1093PIN_GROUP(SALT15, AE26);
1094PIN_GROUP(SALT2, AC15);
1095PIN_GROUP(SALT3, AD15);
1096PIN_GROUP(SALT4, W17);
1097PIN_GROUP(SALT5, V18);
1098PIN_GROUP(SALT6, W18);
1099PIN_GROUP(SALT7, Y17);
1100PIN_GROUP(SALT8, AA18);
1101PIN_GROUP(SALT9, AA13);
1102PIN_GROUP(SD, C16, C14, C11, D9, F14, D10, C12, C13);
1103PIN_GROUP(SGMII, SGMII0);
1104PIN_GROUP(SGPM0, U21, T24, V22, T23);
1105PIN_GROUP(SGPM1, AC25, AB25, AB24, W26);
1106PIN_GROUP(SGPS, B11, C18, N13, C8);
1107PIN_GROUP(SIOONCTRLN0, AE23);
1108PIN_GROUP(SIOONCTRLN1, AA15);
1109PIN_GROUP(SIOPBIN0, AD25);
1110PIN_GROUP(SIOPBIN1, AA16);
1111PIN_GROUP(SIOPBON0, AE25);
1112PIN_GROUP(SIOPBON1, AF17);
1113PIN_GROUP(SIOPWREQN0, AE21);
1114PIN_GROUP(SIOPWREQN1, AB16);
1115PIN_GROUP(SIOPWRGD1, AB15);
1116PIN_GROUP(SIOS3N0, AF20);
1117PIN_GROUP(SIOS3N1, V17);
1118PIN_GROUP(SIOS5N0, AF21);
1119PIN_GROUP(SIOS5N1, J13);
1120PIN_GROUP(SIOSCIN0, AF23);
1121PIN_GROUP(SIOSCIN1, Y16);
1122PIN_GROUP(SMON0, U21, T24, V22, T23);
1123PIN_GROUP(SMON1, W26, AC25, AB25);
1124PIN_GROUP(SPI0, D24, B23, B22);
1125PIN_GROUP(SPI0ABR, M15);
1126PIN_GROUP(SPI0CS1, B21);
1127PIN_GROUP(SPI0WPN, B19);
1128PIN_GROUP(SPI1, B26, A25, A24);
1129PIN_GROUP(SPI1ABR, A19);
1130PIN_GROUP(SPI1CS1, A21);
1131PIN_GROUP(SPI1WPN, A18);
1132PIN_GROUP(SPI2, D26, C26, A23, A22);
1133PIN_GROUP(SPI2CS1, A26);
1134PIN_GROUP(TACH0, AC26);
1135PIN_GROUP(TACH1, AA25);
1136PIN_GROUP(TACH10, AB26);
1137PIN_GROUP(TACH11, AD26);
1138PIN_GROUP(TACH12, P26);
1139PIN_GROUP(TACH13, AE26);
1140PIN_GROUP(TACH14, AF26);
1141PIN_GROUP(TACH15, AF25);
1142PIN_GROUP(TACH2, AB23);
1143PIN_GROUP(TACH3, U22);
1144PIN_GROUP(TACH4, V21);
1145PIN_GROUP(TACH5, N26);
1146PIN_GROUP(TACH6, P25);
1147PIN_GROUP(TACH7, N25);
1148PIN_GROUP(TACH8, V23);
1149PIN_GROUP(TACH9, W22);
1150PIN_GROUP(THRU0, AC26, AA25);
1151PIN_GROUP(THRU1, AB23, U22);
1152PIN_GROUP(THRU2, A19, A18);
1153PIN_GROUP(THRU3, B25, F26);
1154PIN_GROUP(UART0, AC16, AF16);
1155PIN_GROUP(UART1, W16, V16);
1156PIN_GROUP(UART2, AB18, AC18);
1157PIN_GROUP(UART3, K13, AA17);
1158PIN_GROUP(UART5, AB17, AD16);
1159PIN_GROUP(UART6, AC17, AD17);
1160PIN_GROUP(UART7, AE16, AE17);
1161PIN_GROUP(UART8, M15, B19);
1162PIN_GROUP(UART9, B26, A25);
1163PIN_GROUP(UART10, A24, B24);
1164PIN_GROUP(UART11, E26, A21);
1165PIN_GROUP(USB2CD, PORTC_MODE);
1166PIN_GROUP(USB2CH, PORTC_MODE);
1167PIN_GROUP(USB2CU, PORTC_MODE);
1168PIN_GROUP(USB2CUD, PORTC_MODE);
1169PIN_GROUP(USB2DD, PORTD_MODE);
1170PIN_GROUP(USB2DH, PORTD_MODE);
1171PIN_GROUP(USBUART, G10, K12);
1172PIN_GROUP(VGA, J11, E7);
1173PIN_GROUP(VPI, C16, C14, C11, D9, F14, D10, AC26, AA25, AB23, U22, V21, N26,
1174 P25, N25, V23, W22, AB26, AD26, P26, AE26, AF26, AF25, AE25, AD25,
1175 AF23, AF20, AF21, AE21);
1176PIN_GROUP(WDTRST0N, K13);
1177PIN_GROUP(WDTRST1N, AA17);
1178PIN_GROUP(WDTRST2N, AB17);
1179PIN_GROUP(WDTRST3N, AD16);
1180PIN_GROUP(WDTRST4N, AC25);
1181PIN_GROUP(WDTRST5N, AB25);
1182PIN_GROUP(WDTRST6N, AC24);
1183PIN_GROUP(WDTRST7N, AB24);
1184
1185#define GROUP(n) PINCTRL_PINGROUP(#n, n##_pins, ARRAY_SIZE(n##_pins))
1186
1187static const struct pingroup aspeed_g7_soc1_groups[] = {
1188 GROUP(ADC0),
1189 GROUP(ADC1),
1190 GROUP(ADC10),
1191 GROUP(ADC11),
1192 GROUP(ADC12),
1193 GROUP(ADC13),
1194 GROUP(ADC14),
1195 GROUP(ADC15),
1196 GROUP(ADC2),
1197 GROUP(ADC3),
1198 GROUP(ADC4),
1199 GROUP(ADC5),
1200 GROUP(ADC6),
1201 GROUP(ADC7),
1202 GROUP(ADC8),
1203 GROUP(ADC9),
1204 GROUP(AUXPWRGOOD0),
1205 GROUP(AUXPWRGOOD1),
1206 GROUP(CANBUS),
1207 GROUP(DI2C0),
1208 GROUP(DI2C1),
1209 GROUP(DI2C10),
1210 GROUP(DI2C11),
1211 GROUP(DI2C12),
1212 GROUP(DI2C13),
1213 GROUP(DI2C14),
1214 GROUP(DI2C15),
1215 GROUP(DI2C2),
1216 GROUP(DI2C3),
1217 GROUP(DI2C8),
1218 GROUP(DI2C9),
1219 GROUP(DSGPM0),
1220 GROUP(ESPI0),
1221 GROUP(ESPI1),
1222 GROUP(FSI0),
1223 GROUP(FSI1),
1224 GROUP(FSI2),
1225 GROUP(FSI3),
1226 GROUP(FWQSPI),
1227 GROUP(FWSPIABR),
1228 GROUP(FWWPN),
1229 GROUP(HBLED),
1230 GROUP(HVI3C0),
1231 GROUP(HVI3C1),
1232 GROUP(HVI3C12),
1233 GROUP(HVI3C13),
1234 GROUP(HVI3C14),
1235 GROUP(HVI3C15),
1236 GROUP(HVI3C2),
1237 GROUP(HVI3C3),
1238 GROUP(I2C0),
1239 GROUP(I2C1),
1240 GROUP(I2C10),
1241 GROUP(I2C11),
1242 GROUP(I2C12),
1243 GROUP(I2C13),
1244 GROUP(I2C14),
1245 GROUP(I2C15),
1246 GROUP(I2C2),
1247 GROUP(I2C3),
1248 GROUP(I2C4),
1249 GROUP(I2C5),
1250 GROUP(I2C6),
1251 GROUP(I2C7),
1252 GROUP(I2C8),
1253 GROUP(I2C9),
1254 GROUP(I2CF0),
1255 GROUP(I2CF1),
1256 GROUP(I2CF2),
1257 GROUP(I3C10),
1258 GROUP(I3C11),
1259 GROUP(I3C4),
1260 GROUP(I3C5),
1261 GROUP(I3C6),
1262 GROUP(I3C7),
1263 GROUP(I3C8),
1264 GROUP(I3C9),
1265 GROUP(JTAGM1),
1266 GROUP(LPC0),
1267 GROUP(LPC1),
1268 GROUP(LTPI),
1269 GROUP(LTPI_PS_I2C0),
1270 GROUP(LTPI_PS_I2C1),
1271 GROUP(LTPI_PS_I2C2),
1272 GROUP(LTPI_PS_I2C3),
1273 GROUP(MACLINK0),
1274 GROUP(MACLINK1),
1275 GROUP(MACLINK2),
1276 GROUP(MDIO0),
1277 GROUP(MDIO1),
1278 GROUP(MDIO2),
1279 GROUP(NCTS0),
1280 GROUP(NCTS1),
1281 GROUP(NCTS5),
1282 GROUP(NCTS6),
1283 GROUP(NDCD0),
1284 GROUP(NDCD1),
1285 GROUP(NDCD5),
1286 GROUP(NDCD6),
1287 GROUP(NDSR0),
1288 GROUP(NDSR1),
1289 GROUP(NDSR5),
1290 GROUP(NDSR6),
1291 GROUP(NDTR0),
1292 GROUP(NDTR1),
1293 GROUP(NDTR5),
1294 GROUP(NDTR6),
1295 GROUP(NRI0),
1296 GROUP(NRI1),
1297 GROUP(NRI5),
1298 GROUP(NRI6),
1299 GROUP(NRTS0),
1300 GROUP(NRTS1),
1301 GROUP(NRTS5),
1302 GROUP(NRTS6),
1303 GROUP(OSCCLK),
1304 GROUP(PE2SGRSTN),
1305 GROUP(PWM0),
1306 GROUP(PWM1),
1307 GROUP(PWM10),
1308 GROUP(PWM11),
1309 GROUP(PWM12),
1310 GROUP(PWM13),
1311 GROUP(PWM14),
1312 GROUP(PWM15),
1313 GROUP(PWM2),
1314 GROUP(PWM3),
1315 GROUP(PWM4),
1316 GROUP(PWM5),
1317 GROUP(PWM6),
1318 GROUP(PWM7),
1319 GROUP(PWM8),
1320 GROUP(PWM9),
1321 GROUP(QSPI0),
1322 GROUP(QSPI1),
1323 GROUP(QSPI2),
1324 GROUP(RGMII0),
1325 GROUP(RGMII1),
1326 GROUP(RMII0),
1327 GROUP(RMII0RCLKO),
1328 GROUP(RMII1),
1329 GROUP(RMII1RCLKO),
1330 GROUP(SALT0),
1331 GROUP(SALT1),
1332 GROUP(SALT10),
1333 GROUP(SALT11),
1334 GROUP(SALT12),
1335 GROUP(SALT13),
1336 GROUP(SALT14),
1337 GROUP(SALT15),
1338 GROUP(SALT2),
1339 GROUP(SALT3),
1340 GROUP(SALT4),
1341 GROUP(SALT5),
1342 GROUP(SALT6),
1343 GROUP(SALT7),
1344 GROUP(SALT8),
1345 GROUP(SALT9),
1346 GROUP(SD),
1347 GROUP(SGMII),
1348 GROUP(SGPM0),
1349 GROUP(SGPM1),
1350 GROUP(SGPS),
1351 GROUP(SIOONCTRLN0),
1352 GROUP(SIOONCTRLN1),
1353 GROUP(SIOPBIN0),
1354 GROUP(SIOPBIN1),
1355 GROUP(SIOPBON0),
1356 GROUP(SIOPBON1),
1357 GROUP(SIOPWREQN0),
1358 GROUP(SIOPWREQN1),
1359 GROUP(SIOPWRGD1),
1360 GROUP(SIOS3N0),
1361 GROUP(SIOS3N1),
1362 GROUP(SIOS5N0),
1363 GROUP(SIOS5N1),
1364 GROUP(SIOSCIN0),
1365 GROUP(SIOSCIN1),
1366 GROUP(SMON0),
1367 GROUP(SMON1),
1368 GROUP(SPI0),
1369 GROUP(SPI0ABR),
1370 GROUP(SPI0CS1),
1371 GROUP(SPI0WPN),
1372 GROUP(SPI1),
1373 GROUP(SPI1ABR),
1374 GROUP(SPI1CS1),
1375 GROUP(SPI1WPN),
1376 GROUP(SPI2),
1377 GROUP(SPI2CS1),
1378 GROUP(TACH0),
1379 GROUP(TACH1),
1380 GROUP(TACH10),
1381 GROUP(TACH11),
1382 GROUP(TACH12),
1383 GROUP(TACH13),
1384 GROUP(TACH14),
1385 GROUP(TACH15),
1386 GROUP(TACH2),
1387 GROUP(TACH3),
1388 GROUP(TACH4),
1389 GROUP(TACH5),
1390 GROUP(TACH6),
1391 GROUP(TACH7),
1392 GROUP(TACH8),
1393 GROUP(TACH9),
1394 GROUP(THRU0),
1395 GROUP(THRU1),
1396 GROUP(THRU2),
1397 GROUP(THRU3),
1398 GROUP(UART0),
1399 GROUP(UART1),
1400 GROUP(UART10),
1401 GROUP(UART11),
1402 GROUP(UART2),
1403 GROUP(UART3),
1404 GROUP(UART5),
1405 GROUP(UART6),
1406 GROUP(UART7),
1407 GROUP(UART8),
1408 GROUP(UART9),
1409 GROUP(USB2CD),
1410 GROUP(USB2CH),
1411 GROUP(USB2CU),
1412 GROUP(USB2CUD),
1413 GROUP(USB2DD),
1414 GROUP(USB2DH),
1415 GROUP(USBUART),
1416 GROUP(VGA),
1417 GROUP(VPI),
1418 GROUP(WDTRST0N),
1419 GROUP(WDTRST1N),
1420 GROUP(WDTRST2N),
1421 GROUP(WDTRST3N),
1422 GROUP(WDTRST4N),
1423 GROUP(WDTRST5N),
1424 GROUP(WDTRST6N),
1425 GROUP(WDTRST7N),
1426};
1427
1428/**
1429 * VM() - Helper macro to unwrap a parenthesized list of arguments.
1430 * @...: The parenthesized list to be unwrapped.
1431 *
1432 * Since the C preprocessor treats commas inside braces {} as argument
1433 * separators for macros, we wrap lists (like mux values) in parentheses ()
1434 * to protect them during macro expansion. This macro strips those
1435 * parentheses when the values are needed for array initialization.
1436 */
1437#define VM(...) __VA_ARGS__
1438
1439/**
1440 * FUNC() - Macro to initialize an aspeed_g7_soc1_function entry.
1441 * @n: Name of the pin function.
1442 * @m: Parenthesized list of mux values, mapped 1:1 to the groups list.
1443 * @...: Variable list of pin group names associated with this function.
1444 *
1445 * This macro solves complex static initialization by:
1446 * 1. Creating anonymous arrays for both group names and mux values
1447 * using C99 Compound Literals.
1448 * 2. Using VM(m) to unwrap mux values into the array initializer.
1449 * 3. Calculating the number of groups via sizeof() division, which
1450 * bypasses the __must_be_array() check performed by ARRAY_SIZE()
1451 * that often fails on compound literals in the kernel environment.
1452 *
1453 * Example: FUNC(i2c0, (1, 4), "i2c0", "di2c0")
1454 * Maps "i2c0" group to mux value 1 and "di2c0" group to mux value 4.
1455 */
1456#define FUNC(n, m, ...) \
1457 { \
1458 .pinfunction = { \
1459 .name = #n, \
1460 .groups = (const char *const[]){ __VA_ARGS__ }, \
1461 .ngroups = sizeof((const char *const[]){ __VA_ARGS__ }) / sizeof(char *), \
1462 }, \
1463 .muxvals = (const u8[]){ VM m } \
1464 }
1465
1466static const struct aspeed_g7_soc1_function aspeed_g7_soc1_functions[] = {
1467 FUNC(ADC0, (0), "ADC0"),
1468 FUNC(ADC1, (0), "ADC1"),
1469 FUNC(ADC10, (0), "ADC10"),
1470 FUNC(ADC11, (0), "ADC11"),
1471 FUNC(ADC12, (0), "ADC12"),
1472 FUNC(ADC13, (0), "ADC13"),
1473 FUNC(ADC14, (0), "ADC14"),
1474 FUNC(ADC15, (0), "ADC15"),
1475 FUNC(ADC2, (0), "ADC2"),
1476 FUNC(ADC3, (0), "ADC3"),
1477 FUNC(ADC4, (0), "ADC4"),
1478 FUNC(ADC5, (0), "ADC5"),
1479 FUNC(ADC6, (0), "ADC6"),
1480 FUNC(ADC7, (0), "ADC7"),
1481 FUNC(ADC8, (0), "ADC8"),
1482 FUNC(ADC9, (0), "ADC9"),
1483 FUNC(AUXPWRGOOD0, (2), "AUXPWRGOOD0"),
1484 FUNC(AUXPWRGOOD1, (2), "AUXPWRGOOD1"),
1485 FUNC(CANBUS, (2), "CANBUS"),
1486 FUNC(ESPI0, (1), "ESPI0"),
1487 FUNC(ESPI1, (1), "ESPI1"),
1488 FUNC(FSI0, (2), "FSI0"),
1489 FUNC(FSI1, (2), "FSI1"),
1490 FUNC(FSI2, (2), "FSI2"),
1491 FUNC(FSI3, (2), "FSI3"),
1492 FUNC(FWQSPI, (1), "FWQSPI"),
1493 FUNC(FWSPIABR, (1), "FWSPIABR"),
1494 FUNC(FWWPN, (1), "FWWPN"),
1495 FUNC(HBLED, (2), "HBLED"),
1496 FUNC(I2C0, (1, 2, 4), "I2C0", "LTPI_PS_I2C0", "DI2C0"),
1497 FUNC(I2C1, (1, 2, 4), "I2C1", "LTPI_PS_I2C1", "DI2C1"),
1498 FUNC(I2C10, (1, 2), "I2C10", "DI2C10"),
1499 FUNC(I2C11, (1, 2), "I2C11", "DI2C11"),
1500 FUNC(I2C12, (4, 2), "I2C12", "DI2C12"),
1501 FUNC(I2C13, (4, 2), "I2C13", "DI2C13"),
1502 FUNC(I2C14, (4, 2), "I2C14", "DI2C14"),
1503 FUNC(I2C15, (2, 2), "I2C15", "DI2C15"),
1504 FUNC(I2C2, (1, 2, 4), "I2C2", "LTPI_PS_I2C2", "DI2C2"),
1505 FUNC(I2C3, (1, 2, 4), "I2C3", "LTPI_PS_I2C3", "DI2C3"),
1506 FUNC(I2C4, (1), "I2C4"),
1507 FUNC(I2C5, (1), "I2C5"),
1508 FUNC(I2C6, (1), "I2C6"),
1509 FUNC(I2C7, (1), "I2C7"),
1510 FUNC(I2C8, (1, 2), "I2C8", "DI2C8"),
1511 FUNC(I2C9, (1, 2), "I2C9", "DI2C9"),
1512 FUNC(I2CF0, (5), "I2CF0"),
1513 FUNC(I2CF1, (5), "I2CF1"),
1514 FUNC(I2CF2, (5), "I2CF2"),
1515 FUNC(I3C0, (1), "HVI3C0"),
1516 FUNC(I3C1, (1), "HVI3C1"),
1517 FUNC(I3C10, (1), "I3C10"),
1518 FUNC(I3C11, (1), "I3C11"),
1519 FUNC(I3C12, (1), "HVI3C12"),
1520 FUNC(I3C13, (1), "HVI3C13"),
1521 FUNC(I3C14, (1), "HVI3C14"),
1522 FUNC(I3C15, (1), "HVI3C15"),
1523 FUNC(I3C2, (1), "HVI3C2"),
1524 FUNC(I3C3, (1), "HVI3C3"),
1525 FUNC(I3C4, (1), "I3C4"),
1526 FUNC(I3C5, (1), "I3C5"),
1527 FUNC(I3C6, (1), "I3C6"),
1528 FUNC(I3C7, (1), "I3C7"),
1529 FUNC(I3C8, (1), "I3C8"),
1530 FUNC(I3C9, (1), "I3C9"),
1531 FUNC(JTAGM1, (1), "JTAGM1"),
1532 FUNC(LPC0, (2), "LPC0"),
1533 FUNC(LPC1, (2), "LPC1"),
1534 FUNC(LTPI, (2), "LTPI"),
1535 FUNC(MACLINK0, (4), "MACLINK0"),
1536 FUNC(MACLINK1, (3), "MACLINK1"),
1537 FUNC(MACLINK2, (4), "MACLINK2"),
1538 FUNC(MDIO0, (1), "MDIO0"),
1539 FUNC(MDIO1, (1), "MDIO1"),
1540 FUNC(MDIO2, (1), "MDIO2"),
1541 FUNC(NCTS0, (1), "NCTS0"),
1542 FUNC(NCTS1, (1), "NCTS1"),
1543 FUNC(NCTS5, (4), "NCTS5"),
1544 FUNC(NCTS6, (4), "NCTS6"),
1545 FUNC(NDCD0, (1), "NDCD0"),
1546 FUNC(NDCD1, (1), "NDCD1"),
1547 FUNC(NDCD5, (4), "NDCD5"),
1548 FUNC(NDCD6, (4), "NDCD6"),
1549 FUNC(NDSR0, (1), "NDSR0"),
1550 FUNC(NDSR1, (1), "NDSR1"),
1551 FUNC(NDSR5, (4), "NDSR5"),
1552 FUNC(NDSR6, (4), "NDSR6"),
1553 FUNC(NDTR0, (1), "NDTR0"),
1554 FUNC(NDTR1, (1), "NDTR1"),
1555 FUNC(NDTR5, (4), "NDTR5"),
1556 FUNC(NDTR6, (4), "NDTR6"),
1557 FUNC(NRI0, (1), "NRI0"),
1558 FUNC(NRI1, (1), "NRI1"),
1559 FUNC(NRI5, (4), "NRI5"),
1560 FUNC(NRI6, (4), "NRI6"),
1561 FUNC(NRTS0, (1), "NRTS0"),
1562 FUNC(NRTS1, (1), "NRTS1"),
1563 FUNC(NRTS5, (4), "NRTS5"),
1564 FUNC(NRTS6, (4), "NRTS6"),
1565 FUNC(OSCCLK, (3), "OSCCLK"),
1566 FUNC(PCIERC, (2), "PE2SGRSTN"),
1567 FUNC(PWM0, (1), "PWM0"),
1568 FUNC(PWM1, (1), "PWM1"),
1569 FUNC(PWM10, (3), "PWM10"),
1570 FUNC(PWM11, (3), "PWM11"),
1571 FUNC(PWM12, (3), "PWM12"),
1572 FUNC(PWM13, (3), "PWM13"),
1573 FUNC(PWM14, (3), "PWM14"),
1574 FUNC(PWM15, (3), "PWM15"),
1575 FUNC(PWM2, (1), "PWM2"),
1576 FUNC(PWM3, (1), "PWM3"),
1577 FUNC(PWM4, (1), "PWM4"),
1578 FUNC(PWM5, (1), "PWM5"),
1579 FUNC(PWM6, (1), "PWM6"),
1580 FUNC(PWM7, (1), "PWM7"),
1581 FUNC(PWM8, (3), "PWM8"),
1582 FUNC(PWM9, (3), "PWM9"),
1583 FUNC(QSPI0, (1), "QSPI0"),
1584 FUNC(QSPI1, (1), "QSPI1"),
1585 FUNC(QSPI2, (1), "QSPI2"),
1586 FUNC(RGMII0, (1), "RGMII0"),
1587 FUNC(RGMII1, (1), "RGMII1"),
1588 FUNC(RMII0, (2), "RMII0"),
1589 FUNC(RMII0RCLKO, (2), "RMII0RCLKO"),
1590 FUNC(RMII1, (2), "RMII1"),
1591 FUNC(RMII1RCLKO, (2), "RMII1RCLKO"),
1592 FUNC(SALT0, (2), "SALT0"),
1593 FUNC(SALT1, (2), "SALT1"),
1594 FUNC(SALT10, (2), "SALT10"),
1595 FUNC(SALT11, (2), "SALT11"),
1596 FUNC(SALT12, (2), "SALT12"),
1597 FUNC(SALT13, (2), "SALT13"),
1598 FUNC(SALT14, (2), "SALT14"),
1599 FUNC(SALT15, (2), "SALT15"),
1600 FUNC(SALT2, (2), "SALT2"),
1601 FUNC(SALT3, (2), "SALT3"),
1602 FUNC(SALT4, (2), "SALT4"),
1603 FUNC(SALT5, (2), "SALT5"),
1604 FUNC(SALT6, (2), "SALT6"),
1605 FUNC(SALT7, (2), "SALT7"),
1606 FUNC(SALT8, (2), "SALT8"),
1607 FUNC(SALT9, (2), "SALT9"),
1608 FUNC(SD, (3), "SD"),
1609 FUNC(SGMII, (1), "SGMII"),
1610 FUNC(SGPM0, (1, 4), "SGPM0", "DSGPM0"),
1611 FUNC(SGPM1, (1), "SGPM1"),
1612 FUNC(SGPS, (5), "SGPS"),
1613 FUNC(SIOONCTRLN0, (2), "SIOONCTRLN0"),
1614 FUNC(SIOONCTRLN1, (2), "SIOONCTRLN1"),
1615 FUNC(SIOPBIN0, (2), "SIOPBIN0"),
1616 FUNC(SIOPBIN1, (2), "SIOPBIN1"),
1617 FUNC(SIOPBON0, (2), "SIOPBON0"),
1618 FUNC(SIOPBON1, (2), "SIOPBON1"),
1619 FUNC(SIOPWREQN0, (2), "SIOPWREQN0"),
1620 FUNC(SIOPWREQN1, (2), "SIOPWREQN1"),
1621 FUNC(SIOPWRGD1, (2), "SIOPWRGD1"),
1622 FUNC(SIOS3N0, (2), "SIOS3N0"),
1623 FUNC(SIOS3N1, (2), "SIOS3N1"),
1624 FUNC(SIOS5N0, (2), "SIOS5N0"),
1625 FUNC(SIOS5N1, (2), "SIOS5N1"),
1626 FUNC(SIOSCIN0, (2), "SIOSCIN0"),
1627 FUNC(SIOSCIN1, (2), "SIOSCIN1"),
1628 FUNC(SMON0, (2), "SMON0"),
1629 FUNC(SMON1, (4), "SMON1"),
1630 FUNC(SPI0, (1), "SPI0"),
1631 FUNC(SPI0ABR, (1), "SPI0ABR"),
1632 FUNC(SPI0CS1, (1), "SPI0CS1"),
1633 FUNC(SPI0WPN, (1), "SPI0WPN"),
1634 FUNC(SPI1, (1), "SPI1"),
1635 FUNC(SPI1ABR, (1), "SPI1ABR"),
1636 FUNC(SPI1CS1, (1), "SPI1CS1"),
1637 FUNC(SPI1WPN, (1), "SPI1WPN"),
1638 FUNC(SPI2, (1), "SPI2"),
1639 FUNC(SPI2CS1, (1), "SPI2CS1"),
1640 FUNC(TACH0, (1), "TACH0"),
1641 FUNC(TACH1, (1), "TACH1"),
1642 FUNC(TACH10, (1), "TACH10"),
1643 FUNC(TACH11, (1), "TACH11"),
1644 FUNC(TACH12, (1), "TACH12"),
1645 FUNC(TACH13, (1), "TACH13"),
1646 FUNC(TACH14, (1), "TACH14"),
1647 FUNC(TACH15, (1), "TACH15"),
1648 FUNC(TACH2, (1), "TACH2"),
1649 FUNC(TACH3, (1), "TACH3"),
1650 FUNC(TACH4, (1), "TACH4"),
1651 FUNC(TACH5, (1), "TACH5"),
1652 FUNC(TACH6, (1), "TACH6"),
1653 FUNC(TACH7, (1), "TACH7"),
1654 FUNC(TACH8, (1), "TACH8"),
1655 FUNC(TACH9, (1), "TACH9"),
1656 FUNC(THRU0, (2), "THRU0"),
1657 FUNC(THRU1, (2), "THRU1"),
1658 FUNC(THRU2, (4), "THRU2"),
1659 FUNC(THRU3, (4), "THRU3"),
1660 FUNC(UART0, (1), "UART0"),
1661 FUNC(UART1, (1), "UART1"),
1662 FUNC(UART10, (3), "UART10"),
1663 FUNC(UART11, (3), "UART11"),
1664 FUNC(UART2, (1), "UART2"),
1665 FUNC(UART3, (1), "UART3"),
1666 FUNC(UART5, (4), "UART5"),
1667 FUNC(UART6, (4), "UART6"),
1668 FUNC(UART7, (1), "UART7"),
1669 FUNC(UART8, (3), "UART8"),
1670 FUNC(UART9, (3), "UART9"),
1671 FUNC(USB2C, (0, 1, 2, 3), "USB2CUD", "USB2CD", "USB2CH", "USB2CU"),
1672 FUNC(USB2D, (1, 2), "USB2DD", "USB2DH"),
1673 FUNC(USBUART, (2), "USBUART"),
1674 FUNC(VGA, (1), "VGA"),
1675 FUNC(VPI, (5), "VPI"),
1676 FUNC(WDTRST0N, (2), "WDTRST0N"),
1677 FUNC(WDTRST1N, (2), "WDTRST1N"),
1678 FUNC(WDTRST2N, (2), "WDTRST2N"),
1679 FUNC(WDTRST3N, (2), "WDTRST3N"),
1680 FUNC(WDTRST4N, (2), "WDTRST4N"),
1681 FUNC(WDTRST5N, (2), "WDTRST5N"),
1682 FUNC(WDTRST6N, (2), "WDTRST6N"),
1683 FUNC(WDTRST7N, (2), "WDTRST7N"),
1684};
1685
1686static int aspeed_g7_soc1_pinctrl_probe(struct platform_device *pdev)
1687{
1688 struct aspeed_g7_soc1_pinctrl *pctl;
1689 struct device *dev = &pdev->dev;
1690 int i, ret;
1691
1692 pctl = devm_kzalloc(dev, sizeof(*pctl), GFP_KERNEL);
1693 if (!pctl)
1694 return -ENOMEM;
1695
1696 pctl->dev = dev;
1697 pctl->regmap = syscon_node_to_regmap(dev->parent->of_node);
1698 if (IS_ERR(pctl->regmap)) {
1699 dev_err(dev, "Failed to get regmap from parent\n");
1700 return PTR_ERR(pctl->regmap);
1701 }
1702
1703 ret = devm_pinctrl_register_and_init(dev, &aspeed_g7_soc1_desc, pctl,
1704 &pctl->pctl);
1705 if (ret) {
1706 dev_err(dev, "Failed to register pinctrl\n");
1707 return ret;
1708 }
1709
1710 for (i = 0; i < ARRAY_SIZE(aspeed_g7_soc1_groups); i++) {
1711 const struct pingroup *grp = &aspeed_g7_soc1_groups[i];
1712
1713 ret = pinctrl_generic_add_group(pctl->pctl, grp->name,
1714 (const unsigned int *)grp->pins,
1715 grp->npins, pctl);
1716 if (ret < 0) {
1717 dev_err(dev, "Failed to add group %s\n", grp->name);
1718 return ret;
1719 }
1720 }
1721
1722 for (i = 0; i < ARRAY_SIZE(aspeed_g7_soc1_functions); i++) {
1723 const struct aspeed_g7_soc1_function *func = &aspeed_g7_soc1_functions[i];
1724
1725 ret = pinmux_generic_add_function(pctl->pctl, func->pinfunction.name,
1726 func->pinfunction.groups,
1727 func->pinfunction.ngroups, (void *)func);
1728 if (ret < 0) {
1729 dev_err(dev, "Failed to add function %s\n", func->pinfunction.name);
1730 return ret;
1731 }
1732 }
1733
1734 return pinctrl_enable(pctl->pctl);
1735}
1736
1737static const struct of_device_id aspeed_g7_soc1_pinctrl_match[] = {
1738 { .compatible = "aspeed,ast2700-soc1-pinctrl" },
1739 {}
1740};
1741MODULE_DEVICE_TABLE(of, aspeed_g7_soc1_pinctrl_match);
1742
1743static struct platform_driver aspeed_g7_soc1_pinctrl_driver = {
1744 .probe = aspeed_g7_soc1_pinctrl_probe,
1745 .driver = {
1746 .name = "aspeed-g7-soc1-pinctrl",
1747 .of_match_table = aspeed_g7_soc1_pinctrl_match,
1748 .suppress_bind_attrs = true,
1749 },
1750};
1751
1752static int __init aspeed_g7_soc1_pinctrl_init(void)
1753{
1754 return platform_driver_register(&aspeed_g7_soc1_pinctrl_driver);
1755}
1756arch_initcall(aspeed_g7_soc1_pinctrl_init);
drivers/pinctrl/bcm/pinctrl-bcm4908.c+1−1
@@ -466,6 +466,7 @@ static const struct of_device_id bcm4908_pinctrl_of_match_table[] = { · 465 unmodified lines
466 { .compatible = "brcm,bcm4908-pinctrl", },466 { .compatible = "brcm,bcm4908-pinctrl", },
467 { }467 { }
468};468};
469MODULE_DEVICE_TABLE(of, bcm4908_pinctrl_of_match_table);
469 470
470static int bcm4908_pinctrl_probe(struct platform_device *pdev)471static int bcm4908_pinctrl_probe(struct platform_device *pdev)
471{472{
@@ -561,4 +562,3 @@ module_platform_driver(bcm4908_pinctrl_driver); · 89 unmodified lines
561MODULE_AUTHOR("Rafał Miłecki");562MODULE_AUTHOR("Rafał Miłecki");
562MODULE_DESCRIPTION("Broadcom BCM4908 pinmux driver");563MODULE_DESCRIPTION("Broadcom BCM4908 pinmux driver");
563MODULE_LICENSE("GPL v2");564MODULE_LICENSE("GPL v2");
564MODULE_DEVICE_TABLE(of, bcm4908_pinctrl_of_match_table);
drivers/pinctrl/bcm/pinctrl-bcm63xx.h+1−1
@@ -1,4 +1,4 @@
1// SPDX-License-Identifier: GPL-2.0+1/* SPDX-License-Identifier: GPL-2.0+ */
2/*2/*
3 * Copyright (C) 2021 Álvaro Fernández Rojas <noltari@gmail.com>3 * Copyright (C) 2021 Álvaro Fernández Rojas <noltari@gmail.com>
4 * Copyright (C) 2016 Jonas Gorski <jonas.gorski@gmail.com>4 * Copyright (C) 2016 Jonas Gorski <jonas.gorski@gmail.com>
drivers/pinctrl/bcm/pinctrl-iproc-gpio.c+1−1
@@ -868,7 +868,7 @@ static int iproc_gpio_probe(struct platform_device *pdev) · 867 unmodified lines
868 gc->set = iproc_gpio_set;868 gc->set = iproc_gpio_set;
869 gc->get = iproc_gpio_get;869 gc->get = iproc_gpio_get;
870 870
871 chip->pinmux_is_supported = of_property_read_bool(dev->of_node,871 chip->pinmux_is_supported = of_property_present(dev->of_node,
872 "gpio-ranges");872 "gpio-ranges");
873 873
874 /* optional GPIO interrupt support */874 /* optional GPIO interrupt support */
drivers/pinctrl/bcm/pinctrl-ns.c+1−1
@@ -204,6 +204,7 @@ static const struct of_device_id ns_pinctrl_of_match_table[] = { · 203 unmodified lines
204 { .compatible = "brcm,bcm53012-pinmux", .data = (void *)FLAG_BCM53012, },204 { .compatible = "brcm,bcm53012-pinmux", .data = (void *)FLAG_BCM53012, },
205 { }205 { }
206};206};
207MODULE_DEVICE_TABLE(of, ns_pinctrl_of_match_table);
207 208
208static int ns_pinctrl_probe(struct platform_device *pdev)209static int ns_pinctrl_probe(struct platform_device *pdev)
209{210{
@@ -295,4 +296,3 @@ static struct platform_driver ns_pinctrl_driver = { · 85 unmodified lines
295module_platform_driver(ns_pinctrl_driver);296module_platform_driver(ns_pinctrl_driver);
296 297
297MODULE_AUTHOR("Rafał Miłecki");298MODULE_AUTHOR("Rafał Miłecki");
298MODULE_DEVICE_TABLE(of, ns_pinctrl_of_match_table);
drivers/pinctrl/cirrus/pinctrl-cs42l43.c+4−6
@@ -343,7 +343,7 @@ static int cs42l43_pin_set_db(struct cs42l43_pin *priv, unsigned int pin, · 342 unmodified lines
343 343
344 return regmap_update_bits(priv->regmap, CS42L43_GPIO_CTRL2,344 return regmap_update_bits(priv->regmap, CS42L43_GPIO_CTRL2,
345 CS42L43_GPIO1_DEGLITCH_BYP_MASK << pin,345 CS42L43_GPIO1_DEGLITCH_BYP_MASK << pin,
346 !!us << pin);346 !us << pin);
347}347}
348 348
349static int cs42l43_pin_config_get(struct pinctrl_dev *pctldev,349static int cs42l43_pin_config_get(struct pinctrl_dev *pctldev,
@@ -499,12 +499,10 @@ static int cs42l43_gpio_set(struct gpio_chip *chip, unsigned int offset, · 149 unmodified lines
499 499
500 ret = regmap_update_bits(priv->regmap, CS42L43_GPIO_CTRL1,500 ret = regmap_update_bits(priv->regmap, CS42L43_GPIO_CTRL1,
501 BIT(shift), value << shift);501 BIT(shift), value << shift);
502 if (ret)
503 return ret;
504 502
505 pm_runtime_put(priv->dev);503 pm_runtime_put(priv->dev);
506 504
507 return 0;505 return ret;
508}506}
509 507
510static int cs42l43_gpio_direction_out(struct gpio_chip *chip,508static int cs42l43_gpio_direction_out(struct gpio_chip *chip,
@@ -604,8 +602,8 @@ static int cs42l43_pin_probe(struct platform_device *pdev) · 93 unmodified lines
604}602}
605 603
606static const struct platform_device_id cs42l43_pin_id_table[] = {604static const struct platform_device_id cs42l43_pin_id_table[] = {
607 { "cs42l43-pinctrl", },605 { .name = "cs42l43-pinctrl" },
608 {}606 { }
609};607};
610MODULE_DEVICE_TABLE(platform, cs42l43_pin_id_table);608MODULE_DEVICE_TABLE(platform, cs42l43_pin_id_table);
611 609
drivers/pinctrl/core.c+36−5
@@ -622,8 +622,13 @@ static int pinctrl_generic_group_name_to_selector(struct pinctrl_dev *pctldev, · 621 unmodified lines
622 const char *function)622 const char *function)
623{623{
624 const struct pinctrl_ops *ops = pctldev->desc->pctlops;624 const struct pinctrl_ops *ops = pctldev->desc->pctlops;
625 int ngroups = ops->get_groups_count(pctldev);
626 int selector = 0;625 int selector = 0;
626 int ngroups;
627
628 if (!ops->get_groups_count || !ops->get_group_name)
629 return -EINVAL;
630
631 ngroups = ops->get_groups_count(pctldev);
627 632
628 /* See if this pctldev has this group */633 /* See if this pctldev has this group */
629 while (selector < ngroups) {634 while (selector < ngroups) {
@@ -738,8 +743,15 @@ int pinctrl_get_group_selector(struct pinctrl_dev *pctldev, · 108 unmodified lines
738 const char *pin_group)743 const char *pin_group)
739{744{
740 const struct pinctrl_ops *pctlops = pctldev->desc->pctlops;745 const struct pinctrl_ops *pctlops = pctldev->desc->pctlops;
741 unsigned int ngroups = pctlops->get_groups_count(pctldev);
742 unsigned int group_selector = 0;746 unsigned int group_selector = 0;
747 unsigned int ngroups;
748
749 if (!pctlops->get_groups_count || !pctlops->get_group_name) {
750 dev_err(pctldev->dev, "does not support pin groups\n");
751 return -EINVAL;
752 }
753
754 ngroups = pctlops->get_groups_count(pctldev);
743 755
744 while (group_selector < ngroups) {756 while (group_selector < ngroups) {
745 const char *gname = pctlops->get_group_name(pctldev,757 const char *gname = pctlops->get_group_name(pctldev,
@@ -760,6 +772,7 @@ int pinctrl_get_group_selector(struct pinctrl_dev *pctldev, · 14 unmodified lines
760 772
761 return -EINVAL;773 return -EINVAL;
762}774}
775EXPORT_SYMBOL_GPL(pinctrl_get_group_selector);
763 776
764bool pinctrl_gpio_can_use_line(struct gpio_chip *gc, unsigned int offset)777bool pinctrl_gpio_can_use_line(struct gpio_chip *gc, unsigned int offset)
765{778{
@@ -1801,6 +1814,11 @@ static int pinctrl_groups_show(struct seq_file *s, void *what) · 1035 unmodified lines
1801 1814
1802 mutex_lock(&pctldev->mutex);1815 mutex_lock(&pctldev->mutex);
1803 1816
1817 if (!ops->get_groups_count || !ops->get_group_name) {
1818 mutex_unlock(&pctldev->mutex);
1819 return 0;
1820 }
1821
1804 ngroups = ops->get_groups_count(pctldev);1822 ngroups = ops->get_groups_count(pctldev);
1805 1823
1806 seq_puts(s, "registered pin groups:\n");1824 seq_puts(s, "registered pin groups:\n");
@@ -2081,12 +2099,25 @@ static void pinctrl_remove_device_debugfs(struct pinctrl_dev *pctldev) · 274 unmodified lines
2081static int pinctrl_check_ops(struct pinctrl_dev *pctldev)2099static int pinctrl_check_ops(struct pinctrl_dev *pctldev)
2082{2100{
2083 const struct pinctrl_ops *ops = pctldev->desc->pctlops;2101 const struct pinctrl_ops *ops = pctldev->desc->pctlops;
2102 const struct pinconf_ops *confops = pctldev->desc->confops;
2103 bool needs_groups = false;
2084 2104
2085 if (!ops ||2105 if (!ops)
2086 !ops->get_groups_count ||
2087 !ops->get_group_name)
2088 return -EINVAL;2106 return -EINVAL;
2089 2107
2108 if (pctldev->desc->pmxops)
2109 needs_groups = true;
2110
2111 if (confops && (confops->pin_config_group_get ||
2112 confops->pin_config_group_set))
2113 needs_groups = true;
2114
2115 if (needs_groups && (!ops->get_groups_count || !ops->get_group_name)) {
2116 dev_err(pctldev->dev,
2117 "driver needs group callbacks for mux or group config\n");
2118 return -EINVAL;
2119 }
2120
2090 return 0;2121 return 0;
2091}2122}
2092 2123
drivers/pinctrl/intel/pinctrl-broxton.c+2−2
@@ -995,8 +995,8 @@ static const struct acpi_device_id bxt_pinctrl_acpi_match[] = { · 994 unmodified lines
995MODULE_DEVICE_TABLE(acpi, bxt_pinctrl_acpi_match);995MODULE_DEVICE_TABLE(acpi, bxt_pinctrl_acpi_match);
996 996
997static const struct platform_device_id bxt_pinctrl_platform_ids[] = {997static const struct platform_device_id bxt_pinctrl_platform_ids[] = {
998 { "apollolake-pinctrl", (kernel_ulong_t)apl_pinctrl_soc_data },998 { .name = "apollolake-pinctrl", .driver_data = (kernel_ulong_t)apl_pinctrl_soc_data },
999 { "broxton-pinctrl", (kernel_ulong_t)bxt_pinctrl_soc_data },999 { .name = "broxton-pinctrl", .driver_data = (kernel_ulong_t)bxt_pinctrl_soc_data },
1000 { }1000 { }
1001};1001};
1002MODULE_DEVICE_TABLE(platform, bxt_pinctrl_platform_ids);1002MODULE_DEVICE_TABLE(platform, bxt_pinctrl_platform_ids);
drivers/pinctrl/intel/pinctrl-denverton.c+1−1
@@ -250,7 +250,7 @@ static const struct acpi_device_id dnv_pinctrl_acpi_match[] = { · 249 unmodified lines
250MODULE_DEVICE_TABLE(acpi, dnv_pinctrl_acpi_match);250MODULE_DEVICE_TABLE(acpi, dnv_pinctrl_acpi_match);
251 251
252static const struct platform_device_id dnv_pinctrl_platform_ids[] = {252static const struct platform_device_id dnv_pinctrl_platform_ids[] = {
253 { "denverton-pinctrl", (kernel_ulong_t)&dnv_soc_data },253 { .name = "denverton-pinctrl", .driver_data = (kernel_ulong_t)&dnv_soc_data },
254 { }254 { }
255};255};
256MODULE_DEVICE_TABLE(platform, dnv_pinctrl_platform_ids);256MODULE_DEVICE_TABLE(platform, dnv_pinctrl_platform_ids);
drivers/pinctrl/intel/pinctrl-intel.c+2−1
@@ -1556,13 +1556,13 @@ static int intel_pinctrl_probe_pwm(struct intel_pinctrl *pctrl, · 1555 unmodified lines
1556 struct intel_community *community,1556 struct intel_community *community,
1557 unsigned short capability_offset)1557 unsigned short capability_offset)
1558{1558{
1559 void __iomem *base = community->regs + capability_offset + 4;
1560 static const struct pwm_lpss_boardinfo info = {1559 static const struct pwm_lpss_boardinfo info = {
1561 .clk_rate = 19200000,1560 .clk_rate = 19200000,
1562 .npwm = 1,1561 .npwm = 1,
1563 .base_unit_bits = 22,1562 .base_unit_bits = 22,
1564 };1563 };
1565 struct pwm_chip *chip;1564 struct pwm_chip *chip;
1565 void __iomem *base;
1566 1566
1567 if (!(community->features & PINCTRL_FEATURE_PWM))1567 if (!(community->features & PINCTRL_FEATURE_PWM))
1568 return 0;1568 return 0;
@@ -1570,6 +1570,7 @@ static int intel_pinctrl_probe_pwm(struct intel_pinctrl *pctrl, · 1 unmodified line
1570 if (!IS_REACHABLE(CONFIG_PWM_LPSS))1570 if (!IS_REACHABLE(CONFIG_PWM_LPSS))
1571 return 0;1571 return 0;
1572 1572
1573 base = community->regs + capability_offset + 4;
1573 chip = devm_pwm_lpss_probe(pctrl->dev, base, &info);1574 chip = devm_pwm_lpss_probe(pctrl->dev, base, &info);
1574 return PTR_ERR_OR_ZERO(chip);1575 return PTR_ERR_OR_ZERO(chip);
1575}1576}
drivers/pinctrl/mediatek/Kconfig+1−16
@@ -1,6 +1,6 @@
1# SPDX-License-Identifier: GPL-2.0-only1# SPDX-License-Identifier: GPL-2.0-only
2menu "MediaTek pinctrl drivers"2menu "MediaTek pinctrl drivers"
3 depends on ARCH_MEDIATEK || ARCH_AIROHA || RALINK || COMPILE_TEST3 depends on ARCH_MEDIATEK || RALINK || COMPILE_TEST
4 4
5config EINT_MTK5config EINT_MTK
6 tristate "MediaTek External Interrupt Support"6 tristate "MediaTek External Interrupt Support"
@@ -126,21 +126,6 @@ config PINCTRL_MT8127 · 119 unmodified lines
126 select PINCTRL_MTK126 select PINCTRL_MTK
127 127
128# For ARMv8 SoCs128# For ARMv8 SoCs
129config PINCTRL_AIROHA
130 tristate "Airoha EN7581 pin control"
131 depends on OF
132 depends on ARM64 || COMPILE_TEST
133 select PINMUX
134 select GENERIC_PINCONF
135 select GENERIC_PINCTRL_GROUPS
136 select GENERIC_PINMUX_FUNCTIONS
137 select GPIOLIB
138 select GPIOLIB_IRQCHIP
139 select REGMAP_MMIO
140 help
141 Say yes here to support pin controller and gpio driver
142 on Airoha EN7581 SoC.
143
144config PINCTRL_MT2712129config PINCTRL_MT2712
145 bool "MediaTek MT2712 pin control"130 bool "MediaTek MT2712 pin control"
146 depends on OF131 depends on OF
drivers/pinctrl/mediatek/Makefile+0−1
@@ -8,7 +8,6 @@ obj-$(CONFIG_PINCTRL_MTK_MOORE) += pinctrl-moore.o · 7 unmodified lines
8obj-$(CONFIG_PINCTRL_MTK_PARIS) += pinctrl-paris.o8obj-$(CONFIG_PINCTRL_MTK_PARIS) += pinctrl-paris.o
9 9
10# SoC Drivers10# SoC Drivers
11obj-$(CONFIG_PINCTRL_AIROHA) += pinctrl-airoha.o
12obj-$(CONFIG_PINCTRL_MT7620) += pinctrl-mt7620.o11obj-$(CONFIG_PINCTRL_MT7620) += pinctrl-mt7620.o
13obj-$(CONFIG_PINCTRL_MT7621) += pinctrl-mt7621.o12obj-$(CONFIG_PINCTRL_MT7621) += pinctrl-mt7621.o
14obj-$(CONFIG_PINCTRL_MT76X8) += pinctrl-mt76x8.o13obj-$(CONFIG_PINCTRL_MT76X8) += pinctrl-mt76x8.o
drivers/pinctrl/mediatek/mtk-eint.c+3−3
@@ -246,7 +246,7 @@ static int mtk_eint_irq_set_wake(struct irq_data *d, unsigned int on) · 245 unmodified lines
246}246}
247 247
248static void mtk_eint_chip_write_mask(const struct mtk_eint *eint,248static void mtk_eint_chip_write_mask(const struct mtk_eint *eint,
249 void __iomem *base, unsigned int **buf)249 unsigned int **buf)
250{250{
251 int inst, port, port_num;251 int inst, port, port_num;
252 void __iomem *reg;252 void __iomem *reg;
@@ -425,7 +425,7 @@ static void mtk_eint_irq_handler(struct irq_desc *desc) · 172 unmodified lines
425 425
426int mtk_eint_do_suspend(struct mtk_eint *eint)426int mtk_eint_do_suspend(struct mtk_eint *eint)
427{427{
428 mtk_eint_chip_write_mask(eint, eint->base, eint->wake_mask);428 mtk_eint_chip_write_mask(eint, eint->wake_mask);
429 429
430 return 0;430 return 0;
431}431}
@@ -433,7 +433,7 @@ EXPORT_SYMBOL_GPL(mtk_eint_do_suspend); · 1 unmodified line
433 433
434int mtk_eint_do_resume(struct mtk_eint *eint)434int mtk_eint_do_resume(struct mtk_eint *eint)
435{435{
436 mtk_eint_chip_write_mask(eint, eint->base, eint->cur_mask);436 mtk_eint_chip_write_mask(eint, eint->cur_mask);
437 437
438 return 0;438 return 0;
439}439}
drivers/pinctrl/mediatek/pinctrl-moore.c+2−1
@@ -402,7 +402,8 @@ static int mtk_pinconf_group_get(struct pinctrl_dev *pctldev, · 401 unmodified lines
402 unsigned int group, unsigned long *config)402 unsigned int group, unsigned long *config)
403{403{
404 const unsigned int *pins;404 const unsigned int *pins;
405 unsigned int i, npins, old = 0;405 unsigned int i, npins;
406 unsigned long old = 0;
406 int ret;407 int ret;
407 408
408 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);409 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
drivers/pinctrl/mediatek/pinctrl-mt8167.c+1−1
@@ -244,7 +244,7 @@ static const struct mtk_pin_ies_smt_set mt8167_smt_set[] = { · 243 unmodified lines
244 MTK_PIN_IES_SMT_SPEC(24, 25, 0xA00, 12),244 MTK_PIN_IES_SMT_SPEC(24, 25, 0xA00, 12),
245 MTK_PIN_IES_SMT_SPEC(26, 30, 0xA00, 0),245 MTK_PIN_IES_SMT_SPEC(26, 30, 0xA00, 0),
246 MTK_PIN_IES_SMT_SPEC(31, 33, 0xA00, 1),246 MTK_PIN_IES_SMT_SPEC(31, 33, 0xA00, 1),
247 MTK_PIN_IES_SMT_SPEC(34, 39, 0xA900, 2),247 MTK_PIN_IES_SMT_SPEC(34, 39, 0xA00, 2),
248 MTK_PIN_IES_SMT_SPEC(40, 40, 0xA10, 11),248 MTK_PIN_IES_SMT_SPEC(40, 40, 0xA10, 11),
249 MTK_PIN_IES_SMT_SPEC(41, 43, 0xA00, 10),249 MTK_PIN_IES_SMT_SPEC(41, 43, 0xA00, 10),
250 MTK_PIN_IES_SMT_SPEC(44, 47, 0xA00, 11),250 MTK_PIN_IES_SMT_SPEC(44, 47, 0xA00, 11),
drivers/pinctrl/mediatek/pinctrl-mt8516.c+1−1
@@ -244,7 +244,7 @@ static const struct mtk_pin_ies_smt_set mt8516_smt_set[] = { · 243 unmodified lines
244 MTK_PIN_IES_SMT_SPEC(24, 25, 0xA00, 12),244 MTK_PIN_IES_SMT_SPEC(24, 25, 0xA00, 12),
245 MTK_PIN_IES_SMT_SPEC(26, 30, 0xA00, 0),245 MTK_PIN_IES_SMT_SPEC(26, 30, 0xA00, 0),
246 MTK_PIN_IES_SMT_SPEC(31, 33, 0xA00, 1),246 MTK_PIN_IES_SMT_SPEC(31, 33, 0xA00, 1),
247 MTK_PIN_IES_SMT_SPEC(34, 39, 0xA900, 2),247 MTK_PIN_IES_SMT_SPEC(34, 39, 0xA00, 2),
248 MTK_PIN_IES_SMT_SPEC(40, 40, 0xA10, 11),248 MTK_PIN_IES_SMT_SPEC(40, 40, 0xA10, 11),
249 MTK_PIN_IES_SMT_SPEC(41, 43, 0xA00, 10),249 MTK_PIN_IES_SMT_SPEC(41, 43, 0xA00, 10),
250 MTK_PIN_IES_SMT_SPEC(44, 47, 0xA00, 11),250 MTK_PIN_IES_SMT_SPEC(44, 47, 0xA00, 11),
drivers/pinctrl/mediatek/pinctrl-mtk-common.c+10−3
@@ -802,20 +802,27 @@ static const struct pinmux_ops mtk_pmx_ops = { · 801 unmodified lines
802 .get_function_name = mtk_pmx_get_func_name,802 .get_function_name = mtk_pmx_get_func_name,
803 .get_function_groups = mtk_pmx_get_func_groups,803 .get_function_groups = mtk_pmx_get_func_groups,
804 .set_mux = mtk_pmx_set_mux,804 .set_mux = mtk_pmx_set_mux,
805 .gpio_set_direction = mtk_pmx_gpio_set_direction,
806 .gpio_request_enable = mtk_pmx_gpio_request_enable,805 .gpio_request_enable = mtk_pmx_gpio_request_enable,
807};806};
808 807
808static int mtk_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
809{
810 struct mtk_pinctrl *pctl = gpiochip_get_data(chip);
811
812 return mtk_pmx_gpio_set_direction(pctl->pctl_dev, NULL, offset, true);
813}
814
809static int mtk_gpio_direction_output(struct gpio_chip *chip,815static int mtk_gpio_direction_output(struct gpio_chip *chip,
810 unsigned offset, int value)816 unsigned offset, int value)
811{817{
818 struct mtk_pinctrl *pctl = gpiochip_get_data(chip);
812 int ret;819 int ret;
813 820
814 ret = mtk_gpio_set(chip, offset, value);821 ret = mtk_gpio_set(chip, offset, value);
815 if (ret)822 if (ret)
816 return ret;823 return ret;
817 824
818 return pinctrl_gpio_direction_output(chip, offset);825 return mtk_pmx_gpio_set_direction(pctl->pctl_dev, NULL, offset, false);
819}826}
820 827
821static int mtk_gpio_get_direction(struct gpio_chip *chip, unsigned offset)828static int mtk_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
@@ -895,7 +902,7 @@ static const struct gpio_chip mtk_gpio_chip = { · 73 unmodified lines
895 .request = gpiochip_generic_request,902 .request = gpiochip_generic_request,
896 .free = gpiochip_generic_free,903 .free = gpiochip_generic_free,
897 .get_direction = mtk_gpio_get_direction,904 .get_direction = mtk_gpio_get_direction,
898 .direction_input = pinctrl_gpio_direction_input,905 .direction_input = mtk_gpio_direction_input,
899 .direction_output = mtk_gpio_direction_output,906 .direction_output = mtk_gpio_direction_output,
900 .get = mtk_gpio_get,907 .get = mtk_gpio_get,
901 .set = mtk_gpio_set,908 .set = mtk_gpio_set,
drivers/pinctrl/mediatek/pinctrl-mtk-mt8365.h+1−1
@@ -1,4 +1,4 @@
1// SPDX-License-Identifier: GPL-2.01/* SPDX-License-Identifier: GPL-2.0 */
2/*2/*
3 * Copyright (C) 2018 MediaTek Inc.3 * Copyright (C) 2018 MediaTek Inc.
4 * Author: Zhiyong Tao <zhiyong.tao@mediatek.com>4 * Author: Zhiyong Tao <zhiyong.tao@mediatek.com>
drivers/pinctrl/mediatek/pinctrl-paris.c+5−3
@@ -771,7 +771,6 @@ static const struct pinmux_ops mtk_pmxops = { · 770 unmodified lines
771 .get_function_name = mtk_pmx_get_func_name,771 .get_function_name = mtk_pmx_get_func_name,
772 .get_function_groups = mtk_pmx_get_func_groups,772 .get_function_groups = mtk_pmx_get_func_groups,
773 .set_mux = mtk_pmx_set_mux,773 .set_mux = mtk_pmx_set_mux,
774 .gpio_set_direction = mtk_pinmux_gpio_set_direction,
775 .gpio_request_enable = mtk_pinmux_gpio_request_enable,774 .gpio_request_enable = mtk_pinmux_gpio_request_enable,
776};775};
777 776
@@ -886,19 +885,22 @@ static int mtk_gpio_set(struct gpio_chip *chip, unsigned int gpio, int value) · 108 unmodified lines
886 885
887static int mtk_gpio_direction_input(struct gpio_chip *chip, unsigned int gpio)886static int mtk_gpio_direction_input(struct gpio_chip *chip, unsigned int gpio)
888{887{
889 return pinctrl_gpio_direction_input(chip, gpio);888 struct mtk_pinctrl *hw = gpiochip_get_data(chip);
889
890 return mtk_pinmux_gpio_set_direction(hw->pctrl, NULL, gpio, true);
890}891}
891 892
892static int mtk_gpio_direction_output(struct gpio_chip *chip, unsigned int gpio,893static int mtk_gpio_direction_output(struct gpio_chip *chip, unsigned int gpio,
893 int value)894 int value)
894{895{
896 struct mtk_pinctrl *hw = gpiochip_get_data(chip);
895 int ret;897 int ret;
896 898
897 ret = mtk_gpio_set(chip, gpio, value);899 ret = mtk_gpio_set(chip, gpio, value);
898 if (ret)900 if (ret)
899 return ret;901 return ret;
900 902
901 return pinctrl_gpio_direction_output(chip, gpio);903 return mtk_pinmux_gpio_set_direction(hw->pctrl, NULL, gpio, false);
902}904}
903 905
904static int mtk_gpio_to_irq(struct gpio_chip *chip, unsigned int offset)906static int mtk_gpio_to_irq(struct gpio_chip *chip, unsigned int offset)
drivers/pinctrl/meson/pinctrl-amlogic-a4.c+68−18
@@ -55,14 +55,18 @@ struct aml_pio_control { · 54 unmodified lines
55 * partial bank(subordinate) pins mux config use other bank(main) mux registgers55 * partial bank(subordinate) pins mux config use other bank(main) mux registgers
56 * m_bank_id: the main bank which pin_id from 0, but register bit not from bit 056 * m_bank_id: the main bank which pin_id from 0, but register bit not from bit 0
57 * m_bit_offs: bit offset the main bank mux register57 * m_bit_offs: bit offset the main bank mux register
58 * s_bit_offs: start bit that subordinate bank use mux register
58 * sid: start pin_id of subordinate bank59 * sid: start pin_id of subordinate bank
59 * eid: end pin_id of subordinate bank60 * eid: end pin_id of subordinate bank
61 * next: subordinate bank reused multiple other bank groups.
60 */62 */
61struct multi_mux {63struct multi_mux {
62 unsigned int m_bank_id;64 unsigned int m_bank_id;
63 unsigned int m_bit_offs;65 unsigned int m_bit_offs;
66 unsigned int s_bit_offs;
64 unsigned int sid;67 unsigned int sid;
65 unsigned int eid;68 unsigned int eid;
69 const struct multi_mux *next;
66};70};
67 71
68struct aml_pctl_data {72struct aml_pctl_data {
@@ -124,12 +128,51 @@ static const char *aml_bank_name[31] = { · 55 unmodified lines
124"GPIOCC", "TEST_N", "ANALOG"128"GPIOCC", "TEST_N", "ANALOG"
125};129};
126 130
131static const struct multi_mux multi_mux_a9[] = {
132 {
133 .m_bank_id = AMLOGIC_GPIO_C,
134 .m_bit_offs = 4,
135 .s_bit_offs = 0,
136 .sid = (AMLOGIC_GPIO_D << 8) + 16,
137 .eid = (AMLOGIC_GPIO_D << 8) + 16,
138 .next = &multi_mux_a9[1],
139 }, {
140 .m_bank_id = AMLOGIC_GPIO_AO,
141 .m_bit_offs = 0,
142 .s_bit_offs = 52,
143 .sid = (AMLOGIC_GPIO_D << 8) + 17,
144 .eid = (AMLOGIC_GPIO_D << 8) + 17,
145 .next = NULL,
146 }, {
147 .m_bank_id = AMLOGIC_GPIO_A,
148 .m_bit_offs = 0,
149 .s_bit_offs = 80,
150 .sid = (AMLOGIC_GPIO_Y << 8) + 8,
151 .eid = (AMLOGIC_GPIO_Y << 8) + 9,
152 .next = NULL,
153 }, {
154 .m_bank_id = AMLOGIC_GPIO_CC,
155 .m_bit_offs = 24,
156 .s_bit_offs = 0,
157 .sid = (AMLOGIC_GPIO_X << 8) + 16,
158 .eid = (AMLOGIC_GPIO_X << 8) + 17,
159 .next = NULL,
160 },
161};
162
163static const struct aml_pctl_data a9_priv_data = {
164 .number = ARRAY_SIZE(multi_mux_a9),
165 .p_mux = multi_mux_a9,
166};
167
127static const struct multi_mux multi_mux_s7[] = {168static const struct multi_mux multi_mux_s7[] = {
128 {169 {
129 .m_bank_id = AMLOGIC_GPIO_CC,170 .m_bank_id = AMLOGIC_GPIO_CC,
130 .m_bit_offs = 24,171 .m_bit_offs = 24,
172 .s_bit_offs = 0,
131 .sid = (AMLOGIC_GPIO_X << 8) + 16,173 .sid = (AMLOGIC_GPIO_X << 8) + 16,
132 .eid = (AMLOGIC_GPIO_X << 8) + 19,174 .eid = (AMLOGIC_GPIO_X << 8) + 19,
175 .next = NULL,
133 },176 },
134};177};
135 178
@@ -142,13 +185,17 @@ static const struct multi_mux multi_mux_s6[] = { · 6 unmodified lines
142 {185 {
143 .m_bank_id = AMLOGIC_GPIO_CC,186 .m_bank_id = AMLOGIC_GPIO_CC,
144 .m_bit_offs = 24,187 .m_bit_offs = 24,
188 .s_bit_offs = 0,
145 .sid = (AMLOGIC_GPIO_X << 8) + 16,189 .sid = (AMLOGIC_GPIO_X << 8) + 16,
146 .eid = (AMLOGIC_GPIO_X << 8) + 19,190 .eid = (AMLOGIC_GPIO_X << 8) + 19,
191 .next = NULL,
147 }, {192 }, {
148 .m_bank_id = AMLOGIC_GPIO_F,193 .m_bank_id = AMLOGIC_GPIO_F,
149 .m_bit_offs = 4,194 .m_bit_offs = 4,
195 .s_bit_offs = 0,
150 .sid = (AMLOGIC_GPIO_D << 8) + 6,196 .sid = (AMLOGIC_GPIO_D << 8) + 6,
151 .eid = (AMLOGIC_GPIO_D << 8) + 6,197 .eid = (AMLOGIC_GPIO_D << 8) + 6,
198 .next = NULL,
152 },199 },
153};200};
154 201
@@ -177,31 +224,34 @@ static int aml_pctl_set_function(struct aml_pinctrl *info, · 22 unmodified lines
177 struct aml_gpio_bank *bank = gpio_chip_to_bank(range->gc);224 struct aml_gpio_bank *bank = gpio_chip_to_bank(range->gc);
178 unsigned int shift;225 unsigned int shift;
179 int reg;226 int reg;
180 int i;227 int i, loop_count;
181 unsigned int offset = bank->mux_bit_offs;228 unsigned int offset = bank->mux_bit_offs;
182 const struct multi_mux *p_mux;229 const struct multi_mux *p_mux;
183 230
184 /* peculiar mux reg set */231 /* peculiar mux reg set */
185 if (bank->p_mux) {232 loop_count = 10;
186 p_mux = bank->p_mux;233 p_mux = bank->p_mux;
234 while (p_mux && loop_count) {
187 if (pin_id >= p_mux->sid && pin_id <= p_mux->eid) {235 if (pin_id >= p_mux->sid && pin_id <= p_mux->eid) {
188 bank = NULL;236 bank = NULL;
189 for (i = 0; i < info->nbanks; i++) {237 for (i = 0; i < info->nbanks; i++) {
190 if (info->banks[i].bank_id == p_mux->m_bank_id) {238 if (info->banks[i].bank_id == p_mux->m_bank_id) {
191 bank = &info->banks[i];239 bank = &info->banks[i];
192 break;240 break;
193 }241 }
194 }242 }
195 243
196 if (!bank || !bank->reg_mux)244 if (!bank || !bank->reg_mux)
197 return -EINVAL;245 return -EINVAL;
198 246
199 shift = (pin_id - p_mux->sid) << 2;247 shift = ((pin_id - p_mux->sid) << 2) + p_mux->s_bit_offs;
200 reg = (shift / 32) * 4;248 reg = (shift / 32) * 4;
201 offset = shift % 32;249 offset = shift % 32;
202 return regmap_update_bits(bank->reg_mux, reg,250 return regmap_update_bits(bank->reg_mux, reg,
203 0xf << offset, (func & 0xf) << offset);251 0xf << offset, (func & 0xf) << offset);
204 }252 }
253 p_mux = p_mux->next;
254 loop_count--;
205 }255 }
206 256
207 /* normal mux reg set */257 /* normal mux reg set */
@@ -250,7 +300,7 @@ static int aml_pmx_set_mux(struct pinctrl_dev *pctldev, unsigned int fselector, · 42 unmodified lines
250 int i;300 int i;
251 301
252 for (i = 0; i < group->npins; i++) {302 for (i = 0; i < group->npins; i++) {
253 range = pinctrl_find_gpio_range_from_pin(pctldev, group->pins[i]);303 range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, group->pins[i]);
254 aml_pctl_set_function(info, range, group->pins[i], group->func[i]);304 aml_pctl_set_function(info, range, group->pins[i], group->func[i]);
255 }305 }
256 306
@@ -449,7 +499,7 @@ static int aml_pinconf_disable_bias(struct aml_pinctrl *info, · 192 unmodified lines
449 unsigned int pin)499 unsigned int pin)
450{500{
451 struct pinctrl_gpio_range *range =501 struct pinctrl_gpio_range *range =
452 pinctrl_find_gpio_range_from_pin(info->pctl, pin);502 pinctrl_find_gpio_range_from_pin_nolock(info->pctl, pin);
453 struct aml_gpio_bank *bank = gpio_chip_to_bank(range->gc);503 struct aml_gpio_bank *bank = gpio_chip_to_bank(range->gc);
454 unsigned int reg, bit = 0;504 unsigned int reg, bit = 0;
455 505
@@ -462,7 +512,7 @@ static int aml_pinconf_enable_bias(struct aml_pinctrl *info, unsigned int pin, · 6 unmodified lines
462 bool pull_up)512 bool pull_up)
463{513{
464 struct pinctrl_gpio_range *range =514 struct pinctrl_gpio_range *range =
465 pinctrl_find_gpio_range_from_pin(info->pctl, pin);515 pinctrl_find_gpio_range_from_pin_nolock(info->pctl, pin);
466 struct aml_gpio_bank *bank = gpio_chip_to_bank(range->gc);516 struct aml_gpio_bank *bank = gpio_chip_to_bank(range->gc);
467 unsigned int reg, bit, val = 0;517 unsigned int reg, bit, val = 0;
468 int ret;518 int ret;
@@ -484,7 +534,7 @@ static int aml_pinconf_set_drive_strength(struct aml_pinctrl *info, · 15 unmodified lines
484 u16 drive_strength_ua)534 u16 drive_strength_ua)
485{535{
486 struct pinctrl_gpio_range *range =536 struct pinctrl_gpio_range *range =
487 pinctrl_find_gpio_range_from_pin(info->pctl, pin);537 pinctrl_find_gpio_range_from_pin_nolock(info->pctl, pin);
488 struct aml_gpio_bank *bank = gpio_chip_to_bank(range->gc);538 struct aml_gpio_bank *bank = gpio_chip_to_bank(range->gc);
489 unsigned int reg, bit, ds_val;539 unsigned int reg, bit, ds_val;
490 540
@@ -519,7 +569,7 @@ static int aml_pinconf_set_gpio_bit(struct aml_pinctrl *info, · 28 unmodified lines
519 bool arg)569 bool arg)
520{570{
521 struct pinctrl_gpio_range *range =571 struct pinctrl_gpio_range *range =
522 pinctrl_find_gpio_range_from_pin(info->pctl, pin);572 pinctrl_find_gpio_range_from_pin_nolock(info->pctl, pin);
523 struct aml_gpio_bank *bank = gpio_chip_to_bank(range->gc);573 struct aml_gpio_bank *bank = gpio_chip_to_bank(range->gc);
524 unsigned int reg, bit;574 unsigned int reg, bit;
525 575
@@ -548,11 +598,11 @@ static int aml_pinconf_set_output_drive(struct aml_pinctrl *info, · 22 unmodified lines
548{598{
549 int ret;599 int ret;
550 600
551 ret = aml_pinconf_set_output(info, pin, true);601 ret = aml_pinconf_set_drive(info, pin, high);
552 if (ret)602 if (ret)
553 return ret;603 return ret;
554 604
555 return aml_pinconf_set_drive(info, pin, high);605 return aml_pinconf_set_output(info, pin, true);
556}606}
557 607
558static int aml_pinconf_set(struct pinctrl_dev *pcdev, unsigned int pin,608static int aml_pinconf_set(struct pinctrl_dev *pcdev, unsigned int pin,
@@ -921,15 +971,14 @@ static int aml_gpio_direction_output(struct gpio_chip *chip, unsigned int gpio, · 362 unmodified lines
921 unsigned int bit, reg;971 unsigned int bit, reg;
922 int ret;972 int ret;
923 973
924 aml_gpio_calc_reg_and_bit(bank, AML_REG_DIR, gpio, &reg, &bit);974 aml_gpio_calc_reg_and_bit(bank, AML_REG_OUT, gpio, &reg, &bit);
925 ret = regmap_update_bits(bank->reg_gpio, reg, BIT(bit), 0);975 ret = regmap_update_bits(bank->reg_gpio, reg, BIT(bit),
976 value ? BIT(bit) : 0);
926 if (ret < 0)977 if (ret < 0)
927 return ret;978 return ret;
928 979
929 aml_gpio_calc_reg_and_bit(bank, AML_REG_OUT, gpio, &reg, &bit);980 aml_gpio_calc_reg_and_bit(bank, AML_REG_DIR, gpio, &reg, &bit);
930 981 return regmap_update_bits(bank->reg_gpio, reg, BIT(bit), 0);
931 return regmap_update_bits(bank->reg_gpio, reg, BIT(bit),
932 value ? BIT(bit) : 0);
933}982}
934 983
935static int aml_gpio_set(struct gpio_chip *chip, unsigned int gpio, int value)984static int aml_gpio_set(struct gpio_chip *chip, unsigned int gpio, int value)
@@ -1159,6 +1208,7 @@ static int aml_pctl_probe(struct platform_device *pdev) · 223 unmodified lines
1159 1208
1160static const struct of_device_id aml_pctl_of_match[] = {1209static const struct of_device_id aml_pctl_of_match[] = {
1161 { .compatible = "amlogic,pinctrl-a4", },1210 { .compatible = "amlogic,pinctrl-a4", },
1211 { .compatible = "amlogic,pinctrl-a9", .data = &a9_priv_data, },
1162 { .compatible = "amlogic,pinctrl-s7", .data = &s7_priv_data, },1212 { .compatible = "amlogic,pinctrl-s7", .data = &s7_priv_data, },
1163 { .compatible = "amlogic,pinctrl-s6", .data = &s6_priv_data, },1213 { .compatible = "amlogic,pinctrl-s6", .data = &s6_priv_data, },
1164 { /* sentinel */ }1214 { /* sentinel */ }
drivers/pinctrl/nuvoton/pinctrl-ma35.c+2−1
@@ -1014,7 +1014,8 @@ static int ma35_pinctrl_parse_groups(struct fwnode_handle *fwnode, struct group_ · 1013 unmodified lines
1014 grp->data = pin;1014 grp->data = pin;
1015 1015
1016 for (i = 0, j = 0; i < count; i += 3, j++) {1016 for (i = 0, j = 0; i < count; i += 3, j++) {
1017 pin->offset = elems[i] * MA35_MFP_REG_SZ_PER_BANK + MA35_MFP_REG_BASE;1017 pin->offset = elems[i] * MA35_MFP_REG_SZ_PER_BANK + MA35_MFP_REG_BASE +
1018 (elems[i + 1] >= 8 ? 4 : 0);
1018 pin->shift = (elems[i + 1] * MA35_MFP_BITS_PER_PORT) % 32;1019 pin->shift = (elems[i + 1] * MA35_MFP_BITS_PER_PORT) % 32;
1019 pin->muxval = elems[i + 2];1020 pin->muxval = elems[i + 2];
1020 pin->configs = configs;1021 pin->configs = configs;
drivers/pinctrl/nuvoton/pinctrl-ma35d1.c+261−209
@@ -113,6 +113,7 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { · 112 unmodified lines
113 MA35_MUX(0x0, "GPA14"),113 MA35_MUX(0x0, "GPA14"),
114 MA35_MUX(0x2, "UART7_RXD"),114 MA35_MUX(0x2, "UART7_RXD"),
115 MA35_MUX(0x3, "CAN3_RXD"),115 MA35_MUX(0x3, "CAN3_RXD"),
116 MA35_MUX(0x4, "USBHL3_DM"),
116 MA35_MUX(0x6, "NAND_nWP"),117 MA35_MUX(0x6, "NAND_nWP"),
117 MA35_MUX(0x7, "EBI_AD14"),118 MA35_MUX(0x7, "EBI_AD14"),
118 MA35_MUX(0x9, "EBI_ADR14")),119 MA35_MUX(0x9, "EBI_ADR14")),
@@ -123,6 +124,7 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { · 4 unmodified lines
123 MA35_MUX(0x3, "UART6_RXD"),124 MA35_MUX(0x3, "UART6_RXD"),
124 MA35_MUX(0x4, "I2C4_SDA"),125 MA35_MUX(0x4, "I2C4_SDA"),
125 MA35_MUX(0x5, "CAN2_RXD"),126 MA35_MUX(0x5, "CAN2_RXD"),
127 MA35_MUX(0x6, "USBHL0_DM"),
126 MA35_MUX(0x7, "EBI_ALE"),128 MA35_MUX(0x7, "EBI_ALE"),
127 MA35_MUX(0x9, "QEI0_A"),129 MA35_MUX(0x9, "QEI0_A"),
128 MA35_MUX(0xb, "TM1"),130 MA35_MUX(0xb, "TM1"),
@@ -187,6 +189,7 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { · 58 unmodified lines
187 MA35_MUX(0x1, "EPWM2_CH5"),189 MA35_MUX(0x1, "EPWM2_CH5"),
188 MA35_MUX(0x2, "UART2_RXD"),190 MA35_MUX(0x2, "UART2_RXD"),
189 MA35_MUX(0x3, "CAN0_RXD"),191 MA35_MUX(0x3, "CAN0_RXD"),
192 MA35_MUX(0x4, "USBHL2_DM"),
190 MA35_MUX(0x5, "SPI0_MOSI"),193 MA35_MUX(0x5, "SPI0_MOSI"),
191 MA35_MUX(0x6, "EBI_MCLK"),194 MA35_MUX(0x6, "EBI_MCLK"),
192 MA35_MUX(0x7, "CCAP1_VSYNC"),195 MA35_MUX(0x7, "CCAP1_VSYNC"),
@@ -202,6 +205,7 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { · 9 unmodified lines
202 MA35_MUX(0x1, "EPWM2_BRAKE1"),205 MA35_MUX(0x1, "EPWM2_BRAKE1"),
203 MA35_MUX(0x2, "UART2_TXD"),206 MA35_MUX(0x2, "UART2_TXD"),
204 MA35_MUX(0x3, "CAN0_TXD"),207 MA35_MUX(0x3, "CAN0_TXD"),
208 MA35_MUX(0x4, "USBHL2_DP"),
205 MA35_MUX(0x5, "SPI0_MISO"),209 MA35_MUX(0x5, "SPI0_MISO"),
206 MA35_MUX(0x6, "I2S1_MCLK"),210 MA35_MUX(0x6, "I2S1_MCLK"),
207 MA35_MUX(0x7, "CCAP1_SFIELD"),211 MA35_MUX(0x7, "CCAP1_SFIELD"),
@@ -220,6 +224,7 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { · 12 unmodified lines
220 MA35_MUX(0x4, "I2C3_SDA"),224 MA35_MUX(0x4, "I2C3_SDA"),
221 MA35_MUX(0x5, "CAN2_RXD"),225 MA35_MUX(0x5, "CAN2_RXD"),
222 MA35_MUX(0x6, "I2S1_LRCK"),226 MA35_MUX(0x6, "I2S1_LRCK"),
227 MA35_MUX(0x7, "USBHL1_DM"),
223 MA35_MUX(0x8, "ADC0_CH4"),228 MA35_MUX(0x8, "ADC0_CH4"),
224 MA35_MUX(0x9, "EBI_ADR16"),229 MA35_MUX(0x9, "EBI_ADR16"),
225 MA35_MUX(0xe, "ECAP2_IC0")),230 MA35_MUX(0xe, "ECAP2_IC0")),
@@ -231,6 +236,7 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { · 5 unmodified lines
231 MA35_MUX(0x4, "I2C3_SCL"),236 MA35_MUX(0x4, "I2C3_SCL"),
232 MA35_MUX(0x5, "CAN2_TXD"),237 MA35_MUX(0x5, "CAN2_TXD"),
233 MA35_MUX(0x6, "I2S1_BCLK"),238 MA35_MUX(0x6, "I2S1_BCLK"),
239 MA35_MUX(0x7, "USBHL1_DP"),
234 MA35_MUX(0x8, "ADC0_CH5"),240 MA35_MUX(0x8, "ADC0_CH5"),
235 MA35_MUX(0x9, "EBI_ADR17"),241 MA35_MUX(0x9, "EBI_ADR17"),
236 MA35_MUX(0xe, "ECAP2_IC1")),242 MA35_MUX(0xe, "ECAP2_IC1")),
@@ -239,6 +245,7 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { · 2 unmodified lines
239 MA35_MUX(0x1, "EPWM2_CH2"),245 MA35_MUX(0x1, "EPWM2_CH2"),
240 MA35_MUX(0x2, "UART4_RXD"),246 MA35_MUX(0x2, "UART4_RXD"),
241 MA35_MUX(0x3, "CAN1_RXD"),247 MA35_MUX(0x3, "CAN1_RXD"),
248 MA35_MUX(0x4, "USBHL3_DM"),
242 MA35_MUX(0x5, "I2C4_SDA"),249 MA35_MUX(0x5, "I2C4_SDA"),
243 MA35_MUX(0x6, "I2S1_DI"),250 MA35_MUX(0x6, "I2S1_DI"),
244 MA35_MUX(0x8, "ADC0_CH6"),251 MA35_MUX(0x8, "ADC0_CH6"),
@@ -249,6 +256,7 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { · 4 unmodified lines
249 MA35_MUX(0x1, "EPWM2_CH3"),256 MA35_MUX(0x1, "EPWM2_CH3"),
250 MA35_MUX(0x2, "UART4_TXD"),257 MA35_MUX(0x2, "UART4_TXD"),
251 MA35_MUX(0x3, "CAN1_TXD"),258 MA35_MUX(0x3, "CAN1_TXD"),
259 MA35_MUX(0x4, "USBHL3_DP"),
252 MA35_MUX(0x5, "I2C4_SCL"),260 MA35_MUX(0x5, "I2C4_SCL"),
253 MA35_MUX(0x6, "I2S1_DO"),261 MA35_MUX(0x6, "I2S1_DO"),
254 MA35_MUX(0x8, "ADC0_CH7"),262 MA35_MUX(0x8, "ADC0_CH7"),
@@ -264,10 +272,12 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { · 9 unmodified lines
264 MA35_PIN(34, PC2, 0x90, 0x8,272 MA35_PIN(34, PC2, 0x90, 0x8,
265 MA35_MUX(0x0, "GPC2"),273 MA35_MUX(0x0, "GPC2"),
266 MA35_MUX(0x3, "CAN0_RXD"),274 MA35_MUX(0x3, "CAN0_RXD"),
275 MA35_MUX(0x4, "USBHL4_DM"),
267 MA35_MUX(0x6, "SD0_DAT0/eMMC0_DAT0")),276 MA35_MUX(0x6, "SD0_DAT0/eMMC0_DAT0")),
268 MA35_PIN(35, PC3, 0x90, 0xc,277 MA35_PIN(35, PC3, 0x90, 0xc,
269 MA35_MUX(0x0, "GPC3"),278 MA35_MUX(0x0, "GPC3"),
270 MA35_MUX(0x3, "CAN0_TXD"),279 MA35_MUX(0x3, "CAN0_TXD"),
280 MA35_MUX(0x4, "USBHL4_DP"),
271 MA35_MUX(0x6, "SD0_DAT1/eMMC0_DAT1")),281 MA35_MUX(0x6, "SD0_DAT1/eMMC0_DAT1")),
272 MA35_PIN(36, PC4, 0x90, 0x10,282 MA35_PIN(36, PC4, 0x90, 0x10,
273 MA35_MUX(0x0, "GPC4"),283 MA35_MUX(0x0, "GPC4"),
@@ -280,65 +290,100 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { · 6 unmodified lines
280 MA35_PIN(38, PC6, 0x90, 0x18,290 MA35_PIN(38, PC6, 0x90, 0x18,
281 MA35_MUX(0x0, "GPC6"),291 MA35_MUX(0x0, "GPC6"),
282 MA35_MUX(0x3, "CAN1_RXD"),292 MA35_MUX(0x3, "CAN1_RXD"),
293 MA35_MUX(0x4, "USBHL5_DM"),
283 MA35_MUX(0x6, "SD0_nCD")),294 MA35_MUX(0x6, "SD0_nCD")),
284 MA35_PIN(39, PC7, 0x90, 0x1c,295 MA35_PIN(39, PC7, 0x90, 0x1c,
285 MA35_MUX(0x0, "GPC7"),296 MA35_MUX(0x0, "GPC7"),
286 MA35_MUX(0x3, "CAN1_TXD"),297 MA35_MUX(0x3, "CAN1_TXD"),
298 MA35_MUX(0x4, "USBHL5_DP"),
287 MA35_MUX(0x6, "SD0_WP")),299 MA35_MUX(0x6, "SD0_WP")),
288 MA35_PIN(40, PC12, 0x94, 0x10,300 MA35_PIN(40, PC8, 0x94, 0x0,
301 MA35_MUX(0x0, "GPC8"),
302 MA35_MUX(0x1, "EPWM2_CH0"),
303 MA35_MUX(0x2, "UART10_nCTS"),
304 MA35_MUX(0x3, "UART9_RXD"),
305 MA35_MUX(0x4, "I2C0_SDA"),
306 MA35_MUX(0x5, "SPI1_SS0"),
307 MA35_MUX(0x6, "SD0_DAT4/eMMC0_DAT4")),
308 MA35_PIN(41, PC9, 0x94, 0x4,
309 MA35_MUX(0x0, "GPC9"),
310 MA35_MUX(0x1, "EPWM2_CH1"),
311 MA35_MUX(0x2, "UART10_nRTS"),
312 MA35_MUX(0x3, "UART9_TXD"),
313 MA35_MUX(0x4, "I2C0_SCL"),
314 MA35_MUX(0x5, "SPI1_CLK"),
315 MA35_MUX(0x6, "SD0_DAT5/eMMC0_DAT5")),
316 MA35_PIN(42, PC10, 0x94, 0x8,
317 MA35_MUX(0x0, "GPC10"),
318 MA35_MUX(0x1, "EPWM2_CH2"),
319 MA35_MUX(0x2, "UART10_RXD"),
320 MA35_MUX(0x3, "CAN2_RXD"),
321 MA35_MUX(0x4, "USBHL0_DM"),
322 MA35_MUX(0x5, "SPI1_MOSI"),
323 MA35_MUX(0x6, "SD0_DAT6/eMMC0_DAT6")),
324 MA35_PIN(43, PC11, 0x94, 0xc,
325 MA35_MUX(0x0, "GPC11"),
326 MA35_MUX(0x1, "EPWM2_CH3"),
327 MA35_MUX(0x2, "UART10_TXD"),
328 MA35_MUX(0x3, "CAN2_TXD"),
329 MA35_MUX(0x4, "USBHL0_DP"),
330 MA35_MUX(0x5, "SPI1_MISO"),
331 MA35_MUX(0x6, "SD0_DAT7/eMMC0_DAT7")),
332 MA35_PIN(44, PC12, 0x94, 0x10,
289 MA35_MUX(0x0, "GPC12"),333 MA35_MUX(0x0, "GPC12"),
290 MA35_MUX(0x2, "UART12_nCTS"),334 MA35_MUX(0x2, "UART12_nCTS"),
291 MA35_MUX(0x3, "UART11_RXD"),335 MA35_MUX(0x3, "UART11_RXD"),
292 MA35_MUX(0x6, "LCM_DATA16")),336 MA35_MUX(0x6, "LCM_DATA16")),
293 MA35_PIN(41, PC13, 0x94, 0x14,337 MA35_PIN(45, PC13, 0x94, 0x14,
294 MA35_MUX(0x0, "GPC13"),338 MA35_MUX(0x0, "GPC13"),
295 MA35_MUX(0x2, "UART12_nRTS"),339 MA35_MUX(0x2, "UART12_nRTS"),
296 MA35_MUX(0x3, "UART11_TXD"),340 MA35_MUX(0x3, "UART11_TXD"),
297 MA35_MUX(0x6, "LCM_DATA17")),341 MA35_MUX(0x6, "LCM_DATA17")),
298 MA35_PIN(42, PC14, 0x94, 0x18,342 MA35_PIN(46, PC14, 0x94, 0x18,
299 MA35_MUX(0x0, "GPC14"),343 MA35_MUX(0x0, "GPC14"),
300 MA35_MUX(0x2, "UART12_RXD"),344 MA35_MUX(0x2, "UART12_RXD"),
301 MA35_MUX(0x6, "LCM_DATA18")),345 MA35_MUX(0x6, "LCM_DATA18")),
302 MA35_PIN(43, PC15, 0x94, 0x1c,346 MA35_PIN(47, PC15, 0x94, 0x1c,
303 MA35_MUX(0x0, "GPC15"),347 MA35_MUX(0x0, "GPC15"),
304 MA35_MUX(0x2, "UART12_TXD"),348 MA35_MUX(0x2, "UART12_TXD"),
305 MA35_MUX(0x6, "LCM_DATA19"),349 MA35_MUX(0x6, "LCM_DATA19"),
306 MA35_MUX(0x7, "LCM_MPU_TE"),350 MA35_MUX(0x7, "LCM_MPU_TE"),
307 MA35_MUX(0x8, "LCM_MPU_VSYNC")),351 MA35_MUX(0x8, "LCM_MPU_VSYNC")),
308 MA35_PIN(44, PD0, 0x98, 0x0,352 MA35_PIN(48, PD0, 0x98, 0x0,
309 MA35_MUX(0x0, "GPD0"),353 MA35_MUX(0x0, "GPD0"),
310 MA35_MUX(0x2, "UART3_nCTS"),354 MA35_MUX(0x2, "UART3_nCTS"),
311 MA35_MUX(0x3, "UART4_RXD"),355 MA35_MUX(0x3, "UART4_RXD"),
312 MA35_MUX(0x5, "QSPI0_SS0")),356 MA35_MUX(0x5, "QSPI0_SS0")),
313 MA35_PIN(45, PD1, 0x98, 0x4,357 MA35_PIN(49, PD1, 0x98, 0x4,
314 MA35_MUX(0x0, "GPD1"),358 MA35_MUX(0x0, "GPD1"),
315 MA35_MUX(0x2, "UART3_nRTS"),359 MA35_MUX(0x2, "UART3_nRTS"),
316 MA35_MUX(0x3, "UART4_TXD"),360 MA35_MUX(0x3, "UART4_TXD"),
317 MA35_MUX(0x5, "QSPI0_CLK")),361 MA35_MUX(0x5, "QSPI0_CLK")),
318 MA35_PIN(46, PD2, 0x98, 0x8,362 MA35_PIN(50, PD2, 0x98, 0x8,
319 MA35_MUX(0x0, "GPD2"),363 MA35_MUX(0x0, "GPD2"),
320 MA35_MUX(0x2, "UART3_RXD"),364 MA35_MUX(0x2, "UART3_RXD"),
321 MA35_MUX(0x5, "QSPI0_MOSI0")),365 MA35_MUX(0x5, "QSPI0_MOSI0")),
322 MA35_PIN(47, PD3, 0x98, 0xc,366 MA35_PIN(51, PD3, 0x98, 0xc,
323 MA35_MUX(0x0, "GPD3"),367 MA35_MUX(0x0, "GPD3"),
324 MA35_MUX(0x2, "UART3_TXD"),368 MA35_MUX(0x2, "UART3_TXD"),
325 MA35_MUX(0x5, "QSPI0_MISO0")),369 MA35_MUX(0x5, "QSPI0_MISO0")),
326 MA35_PIN(48, PD4, 0x98, 0x10,370 MA35_PIN(52, PD4, 0x98, 0x10,
327 MA35_MUX(0x0, "GPD4"),371 MA35_MUX(0x0, "GPD4"),
328 MA35_MUX(0x2, "UART1_nCTS"),372 MA35_MUX(0x2, "UART1_nCTS"),
329 MA35_MUX(0x3, "UART2_RXD"),373 MA35_MUX(0x3, "UART2_RXD"),
330 MA35_MUX(0x4, "I2C2_SDA"),374 MA35_MUX(0x4, "I2C2_SDA"),
331 MA35_MUX(0x5, "QSPI0_MOSI1")),375 MA35_MUX(0x5, "QSPI0_MOSI1")),
332 MA35_PIN(49, PD5, 0x98, 0x14,376 MA35_PIN(53, PD5, 0x98, 0x14,
333 MA35_MUX(0x0, "GPD5"),377 MA35_MUX(0x0, "GPD5"),
334 MA35_MUX(0x2, "UART1_nRTS"),378 MA35_MUX(0x2, "UART1_nRTS"),
335 MA35_MUX(0x3, "UART2_TXD"),379 MA35_MUX(0x3, "UART2_TXD"),
336 MA35_MUX(0x4, "I2C2_SCL"),380 MA35_MUX(0x4, "I2C2_SCL"),
337 MA35_MUX(0x5, "QSPI0_MISO1")),381 MA35_MUX(0x5, "QSPI0_MISO1")),
338 MA35_PIN(50, PD6, 0x98, 0x18,382 MA35_PIN(54, PD6, 0x98, 0x18,
339 MA35_MUX(0x0, "GPD6"),383 MA35_MUX(0x0, "GPD6"),
340 MA35_MUX(0x1, "EPWM0_SYNC_IN"),384 MA35_MUX(0x1, "EPWM0_SYNC_IN"),
341 MA35_MUX(0x2, "UART1_RXD"),385 MA35_MUX(0x2, "UART1_RXD"),
386 MA35_MUX(0x4, "USBHL3_DM"),
342 MA35_MUX(0x5, "QSPI1_MOSI1"),387 MA35_MUX(0x5, "QSPI1_MOSI1"),
343 MA35_MUX(0x6, "I2C0_SDA"),388 MA35_MUX(0x6, "I2C0_SDA"),
344 MA35_MUX(0x7, "I2S0_MCLK"),389 MA35_MUX(0x7, "I2S0_MCLK"),
@@ -346,10 +391,11 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { · 1 unmodified line
346 MA35_MUX(0x9, "EBI_AD5"),391 MA35_MUX(0x9, "EBI_AD5"),
347 MA35_MUX(0xa, "SPI3_SS1"),392 MA35_MUX(0xa, "SPI3_SS1"),
348 MA35_MUX(0xb, "TRACE_CLK")),393 MA35_MUX(0xb, "TRACE_CLK")),
349 MA35_PIN(51, PD7, 0x98, 0x1c,394 MA35_PIN(55, PD7, 0x98, 0x1c,
350 MA35_MUX(0x0, "GPD7"),395 MA35_MUX(0x0, "GPD7"),
351 MA35_MUX(0x1, "EPWM0_SYNC_OUT"),396 MA35_MUX(0x1, "EPWM0_SYNC_OUT"),
352 MA35_MUX(0x2, "UART1_TXD"),397 MA35_MUX(0x2, "UART1_TXD"),
398 MA35_MUX(0x4, "USBHL3_DP"),
353 MA35_MUX(0x5, "QSPI1_MISO1"),399 MA35_MUX(0x5, "QSPI1_MISO1"),
354 MA35_MUX(0x6, "I2C0_SCL"),400 MA35_MUX(0x6, "I2C0_SCL"),
355 MA35_MUX(0x7, "I2S1_MCLK"),401 MA35_MUX(0x7, "I2S1_MCLK"),
@@ -357,7 +403,7 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { · 1 unmodified line
357 MA35_MUX(0x9, "EBI_AD6"),403 MA35_MUX(0x9, "EBI_AD6"),
358 MA35_MUX(0xa, "SC1_nCD"),404 MA35_MUX(0xa, "SC1_nCD"),
359 MA35_MUX(0xb, "EADC0_ST")),405 MA35_MUX(0xb, "EADC0_ST")),
360 MA35_PIN(52, PD8, 0x9c, 0x0,406 MA35_PIN(56, PD8, 0x9c, 0x0,
361 MA35_MUX(0x0, "GPD8"),407 MA35_MUX(0x0, "GPD8"),
362 MA35_MUX(0x1, "EPWM0_BRAKE0"),408 MA35_MUX(0x1, "EPWM0_BRAKE0"),
363 MA35_MUX(0x2, "UART16_nCTS"),409 MA35_MUX(0x2, "UART16_nCTS"),
@@ -368,7 +414,7 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { · 4 unmodified lines
368 MA35_MUX(0x9, "EBI_AD7"),414 MA35_MUX(0x9, "EBI_AD7"),
369 MA35_MUX(0xa, "SC1_CLK"),415 MA35_MUX(0xa, "SC1_CLK"),
370 MA35_MUX(0xb, "TM0")),416 MA35_MUX(0xb, "TM0")),
371 MA35_PIN(53, PD9, 0x9c, 0x4,417 MA35_PIN(57, PD9, 0x9c, 0x4,
372 MA35_MUX(0x0, "GPD9"),418 MA35_MUX(0x0, "GPD9"),
373 MA35_MUX(0x1, "EPWM0_BRAKE1"),419 MA35_MUX(0x1, "EPWM0_BRAKE1"),
374 MA35_MUX(0x2, "UART16_nRTS"),420 MA35_MUX(0x2, "UART16_nRTS"),
@@ -379,7 +425,7 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { · 4 unmodified lines
379 MA35_MUX(0x9, "EBI_AD8"),425 MA35_MUX(0x9, "EBI_AD8"),
380 MA35_MUX(0xa, "SC1_DAT"),426 MA35_MUX(0xa, "SC1_DAT"),
381 MA35_MUX(0xb, "TM0_EXT")),427 MA35_MUX(0xb, "TM0_EXT")),
382 MA35_PIN(54, PD10, 0x9c, 0x8,428 MA35_PIN(58, PD10, 0x9c, 0x8,
383 MA35_MUX(0x0, "GPD10"),429 MA35_MUX(0x0, "GPD10"),
384 MA35_MUX(0x1, "EPWM1_BRAKE0"),430 MA35_MUX(0x1, "EPWM1_BRAKE0"),
385 MA35_MUX(0x2, "UART16_RXD"),431 MA35_MUX(0x2, "UART16_RXD"),
@@ -389,7 +435,7 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { · 3 unmodified lines
389 MA35_MUX(0x9, "EBI_AD9"),435 MA35_MUX(0x9, "EBI_AD9"),
390 MA35_MUX(0xa, "SC1_RST"),436 MA35_MUX(0xa, "SC1_RST"),
391 MA35_MUX(0xb, "TM2")),437 MA35_MUX(0xb, "TM2")),
392 MA35_PIN(55, PD11, 0x9c, 0xc,438 MA35_PIN(59, PD11, 0x9c, 0xc,
393 MA35_MUX(0x0, "GPD11"),439 MA35_MUX(0x0, "GPD11"),
394 MA35_MUX(0x1, "EPWM1_BRAKE1"),440 MA35_MUX(0x1, "EPWM1_BRAKE1"),
395 MA35_MUX(0x2, "UART16_TXD"),441 MA35_MUX(0x2, "UART16_TXD"),
@@ -399,7 +445,7 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { · 3 unmodified lines
399 MA35_MUX(0x9, "EBI_AD10"),445 MA35_MUX(0x9, "EBI_AD10"),
400 MA35_MUX(0xa, "SC1_PWR"),446 MA35_MUX(0xa, "SC1_PWR"),
401 MA35_MUX(0xb, "TM2_EXT")),447 MA35_MUX(0xb, "TM2_EXT")),
402 MA35_PIN(56, PD12, 0x9c, 0x10,448 MA35_PIN(60, PD12, 0x9c, 0x10,
403 MA35_MUX(0x0, "GPD12"),449 MA35_MUX(0x0, "GPD12"),
404 MA35_MUX(0x1, "EPWM0_BRAKE0"),450 MA35_MUX(0x1, "EPWM0_BRAKE0"),
405 MA35_MUX(0x2, "UART11_TXD"),451 MA35_MUX(0x2, "UART11_TXD"),
@@ -412,7 +458,7 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { · 6 unmodified lines
412 MA35_MUX(0xb, "TM5"),458 MA35_MUX(0xb, "TM5"),
413 MA35_MUX(0xc, "I2S1_LRCK"),459 MA35_MUX(0xc, "I2S1_LRCK"),
414 MA35_MUX(0xd, "INT1")),460 MA35_MUX(0xd, "INT1")),
415 MA35_PIN(57, PD13, 0x9c, 0x14,461 MA35_PIN(61, PD13, 0x9c, 0x14,
416 MA35_MUX(0x0, "GPD13"),462 MA35_MUX(0x0, "GPD13"),
417 MA35_MUX(0x1, "EPWM0_BRAKE1"),463 MA35_MUX(0x1, "EPWM0_BRAKE1"),
418 MA35_MUX(0x2, "UART11_RXD"),464 MA35_MUX(0x2, "UART11_RXD"),
@@ -424,11 +470,12 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { · 5 unmodified lines
424 MA35_MUX(0x9, "ECAP0_IC0"),470 MA35_MUX(0x9, "ECAP0_IC0"),
425 MA35_MUX(0xb, "TM5_EXT"),471 MA35_MUX(0xb, "TM5_EXT"),
426 MA35_MUX(0xc, "I2S1_BCLK")),472 MA35_MUX(0xc, "I2S1_BCLK")),
427 MA35_PIN(58, PD14, 0x9c, 0x18,473 MA35_PIN(62, PD14, 0x9c, 0x18,
428 MA35_MUX(0x0, "GPD14"),474 MA35_MUX(0x0, "GPD14"),
429 MA35_MUX(0x1, "EPWM0_SYNC_IN"),475 MA35_MUX(0x1, "EPWM0_SYNC_IN"),
430 MA35_MUX(0x2, "UART11_nCTS"),476 MA35_MUX(0x2, "UART11_nCTS"),
431 MA35_MUX(0x3, "CAN3_RXD"),477 MA35_MUX(0x3, "CAN3_RXD"),
478 MA35_MUX(0x4, "USBHL5_DM"),
432 MA35_MUX(0x6, "TRACE_DATA2"),479 MA35_MUX(0x6, "TRACE_DATA2"),
433 MA35_MUX(0x7, "EBI_MCLK"),480 MA35_MUX(0x7, "EBI_MCLK"),
434 MA35_MUX(0x8, "EBI_AD6"),481 MA35_MUX(0x8, "EBI_AD6"),
@@ -436,116 +483,117 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { · 1 unmodified line
436 MA35_MUX(0xb, "TM6"),483 MA35_MUX(0xb, "TM6"),
437 MA35_MUX(0xc, "I2S1_DI"),484 MA35_MUX(0xc, "I2S1_DI"),
438 MA35_MUX(0xd, "INT3")),485 MA35_MUX(0xd, "INT3")),
439 MA35_PIN(59, PD15, 0x9c, 0x1c,486 MA35_PIN(63, PD15, 0x9c, 0x1c,
440 MA35_MUX(0x0, "GPD15"),487 MA35_MUX(0x0, "GPD15"),
441 MA35_MUX(0x1, "EPWM0_SYNC_OUT"),488 MA35_MUX(0x1, "EPWM0_SYNC_OUT"),
442 MA35_MUX(0x2, "UART11_nRTS"),489 MA35_MUX(0x2, "UART11_nRTS"),
443 MA35_MUX(0x3, "CAN3_TXD"),490 MA35_MUX(0x3, "CAN3_TXD"),
491 MA35_MUX(0x4, "USBHL5_DP"),
444 MA35_MUX(0x6, "TRACE_DATA3"),492 MA35_MUX(0x6, "TRACE_DATA3"),
445 MA35_MUX(0x7, "EBI_ALE"),493 MA35_MUX(0x7, "EBI_ALE"),
446 MA35_MUX(0x8, "EBI_AD7"),494 MA35_MUX(0x8, "EBI_AD7"),
447 MA35_MUX(0x9, "ECAP0_IC2"),495 MA35_MUX(0x9, "ECAP0_IC2"),
448 MA35_MUX(0xb, "TM6_EXT"),496 MA35_MUX(0xb, "TM6_EXT"),
449 MA35_MUX(0xc, "I2S1_DO")),497 MA35_MUX(0xc, "I2S1_DO")),
450 MA35_PIN(60, PE0, 0xa0, 0x0,498 MA35_PIN(64, PE0, 0xa0, 0x0,
451 MA35_MUX(0x0, "GPE0"),499 MA35_MUX(0x0, "GPE0"),
452 MA35_MUX(0x2, "UART9_nCTS"),500 MA35_MUX(0x2, "UART9_nCTS"),
453 MA35_MUX(0x3, "UART8_RXD"),501 MA35_MUX(0x3, "UART8_RXD"),
454 MA35_MUX(0x7, "CCAP1_DATA0"),502 MA35_MUX(0x7, "CCAP1_DATA0"),
455 MA35_MUX(0x8, "RGMII0_MDC"),503 MA35_MUX(0x8, "RGMII0_MDC"),
456 MA35_MUX(0x9, "RMII0_MDC")),504 MA35_MUX(0x9, "RMII0_MDC")),
457 MA35_PIN(61, PE1, 0xa0, 0x4,505 MA35_PIN(65, PE1, 0xa0, 0x4,
458 MA35_MUX(0x0, "GPE1"),506 MA35_MUX(0x0, "GPE1"),
459 MA35_MUX(0x2, "UART9_nRTS"),507 MA35_MUX(0x2, "UART9_nRTS"),
460 MA35_MUX(0x3, "UART8_TXD"),508 MA35_MUX(0x3, "UART8_TXD"),
461 MA35_MUX(0x7, "CCAP1_DATA1"),509 MA35_MUX(0x7, "CCAP1_DATA1"),
462 MA35_MUX(0x8, "RGMII0_MDIO"),510 MA35_MUX(0x8, "RGMII0_MDIO"),
463 MA35_MUX(0x9, "RMII0_MDIO")),511 MA35_MUX(0x9, "RMII0_MDIO")),
464 MA35_PIN(62, PE2, 0xa0, 0x8,512 MA35_PIN(66, PE2, 0xa0, 0x8,
465 MA35_MUX(0x0, "GPE2"),513 MA35_MUX(0x0, "GPE2"),
466 MA35_MUX(0x2, "UART9_RXD"),514 MA35_MUX(0x2, "UART9_RXD"),
467 MA35_MUX(0x7, "CCAP1_DATA2"),515 MA35_MUX(0x7, "CCAP1_DATA2"),
468 MA35_MUX(0x8, "RGMII0_TXCTL"),516 MA35_MUX(0x8, "RGMII0_TXCTL"),
469 MA35_MUX(0x9, "RMII0_TXEN")),517 MA35_MUX(0x9, "RMII0_TXEN")),
470 MA35_PIN(63, PE3, 0xa0, 0xc,518 MA35_PIN(67, PE3, 0xa0, 0xc,
471 MA35_MUX(0x0, "GPE3"),519 MA35_MUX(0x0, "GPE3"),
472 MA35_MUX(0x2, "UART9_TXD"),520 MA35_MUX(0x2, "UART9_TXD"),
473 MA35_MUX(0x7, "CCAP1_DATA3"),521 MA35_MUX(0x7, "CCAP1_DATA3"),
474 MA35_MUX(0x8, "RGMII0_TXD0"),522 MA35_MUX(0x8, "RGMII0_TXD0"),
475 MA35_MUX(0x9, "RMII0_TXD0")),523 MA35_MUX(0x9, "RMII0_TXD0")),
476 MA35_PIN(64, PE4, 0xa0, 0x10,524 MA35_PIN(68, PE4, 0xa0, 0x10,
477 MA35_MUX(0x0, "GPE4"),525 MA35_MUX(0x0, "GPE4"),
478 MA35_MUX(0x2, "UART4_nCTS"),526 MA35_MUX(0x2, "UART4_nCTS"),
479 MA35_MUX(0x3, "UART3_RXD"),527 MA35_MUX(0x3, "UART3_RXD"),
480 MA35_MUX(0x7, "CCAP1_DATA4"),528 MA35_MUX(0x7, "CCAP1_DATA4"),
481 MA35_MUX(0x8, "RGMII0_TXD1"),529 MA35_MUX(0x8, "RGMII0_TXD1"),
482 MA35_MUX(0x9, "RMII0_TXD1")),530 MA35_MUX(0x9, "RMII0_TXD1")),
483 MA35_PIN(65, PE5, 0xa0, 0x14,531 MA35_PIN(69, PE5, 0xa0, 0x14,
484 MA35_MUX(0x0, "GPE5"),532 MA35_MUX(0x0, "GPE5"),
485 MA35_MUX(0x2, "UART4_nRTS"),533 MA35_MUX(0x2, "UART4_nRTS"),
486 MA35_MUX(0x3, "UART3_TXD"),534 MA35_MUX(0x3, "UART3_TXD"),
487 MA35_MUX(0x7, "CCAP1_DATA5"),535 MA35_MUX(0x7, "CCAP1_DATA5"),
488 MA35_MUX(0x8, "RGMII0_RXCLK"),536 MA35_MUX(0x8, "RGMII0_RXCLK"),
489 MA35_MUX(0x9, "RMII0_REFCLK")),537 MA35_MUX(0x9, "RMII0_REFCLK")),
490 MA35_PIN(66, PE6, 0xa0, 0x18,538 MA35_PIN(70, PE6, 0xa0, 0x18,
491 MA35_MUX(0x0, "GPE6"),539 MA35_MUX(0x0, "GPE6"),
492 MA35_MUX(0x2, "UART4_RXD"),540 MA35_MUX(0x2, "UART4_RXD"),
493 MA35_MUX(0x7, "CCAP1_DATA6"),541 MA35_MUX(0x7, "CCAP1_DATA6"),
494 MA35_MUX(0x8, "RGMII0_RXCTL"),542 MA35_MUX(0x8, "RGMII0_RXCTL"),
495 MA35_MUX(0x9, "RMII0_CRSDV")),543 MA35_MUX(0x9, "RMII0_CRSDV")),
496 MA35_PIN(67, PE7, 0xa0, 0x1c,544 MA35_PIN(71, PE7, 0xa0, 0x1c,
497 MA35_MUX(0x0, "GPE7"),545 MA35_MUX(0x0, "GPE7"),
498 MA35_MUX(0x2, "UART4_TXD"),546 MA35_MUX(0x2, "UART4_TXD"),
499 MA35_MUX(0x7, "CCAP1_DATA7"),547 MA35_MUX(0x7, "CCAP1_DATA7"),
500 MA35_MUX(0x8, "RGMII0_RXD0"),548 MA35_MUX(0x8, "RGMII0_RXD0"),
501 MA35_MUX(0x9, "RMII0_RXD0")),549 MA35_MUX(0x9, "RMII0_RXD0")),
502 MA35_PIN(68, PE8, 0xa4, 0x0,550 MA35_PIN(72, PE8, 0xa4, 0x0,
503 MA35_MUX(0x0, "GPE8"),551 MA35_MUX(0x0, "GPE8"),
504 MA35_MUX(0x2, "UART13_nCTS"),552 MA35_MUX(0x2, "UART13_nCTS"),
505 MA35_MUX(0x3, "UART12_RXD"),553 MA35_MUX(0x3, "UART12_RXD"),
506 MA35_MUX(0x7, "CCAP1_SCLK"),554 MA35_MUX(0x7, "CCAP1_SCLK"),
507 MA35_MUX(0x8, "RGMII0_RXD1"),555 MA35_MUX(0x8, "RGMII0_RXD1"),
508 MA35_MUX(0x9, "RMII0_RXD1")),556 MA35_MUX(0x9, "RMII0_RXD1")),
509 MA35_PIN(69, PE9, 0xa4, 0x4,557 MA35_PIN(73, PE9, 0xa4, 0x4,
510 MA35_MUX(0x0, "GPE9"),558 MA35_MUX(0x0, "GPE9"),
511 MA35_MUX(0x2, "UART13_nRTS"),559 MA35_MUX(0x2, "UART13_nRTS"),
512 MA35_MUX(0x3, "UART12_TXD"),560 MA35_MUX(0x3, "UART12_TXD"),
513 MA35_MUX(0x7, "CCAP1_PIXCLK"),561 MA35_MUX(0x7, "CCAP1_PIXCLK"),
514 MA35_MUX(0x8, "RGMII0_RXD2"),562 MA35_MUX(0x8, "RGMII0_RXD2"),
515 MA35_MUX(0x9, "RMII0_RXERR")),563 MA35_MUX(0x9, "RMII0_RXERR")),
516 MA35_PIN(70, PE10, 0xa4, 0x8,564 MA35_PIN(74, PE10, 0xa4, 0x8,
517 MA35_MUX(0x0, "GPE10"),565 MA35_MUX(0x0, "GPE10"),
518 MA35_MUX(0x2, "UART15_nCTS"),566 MA35_MUX(0x2, "UART15_nCTS"),
519 MA35_MUX(0x3, "UART14_RXD"),567 MA35_MUX(0x3, "UART14_RXD"),
520 MA35_MUX(0x5, "SPI1_SS0"),568 MA35_MUX(0x5, "SPI1_SS0"),
521 MA35_MUX(0x7, "CCAP1_HSYNC"),569 MA35_MUX(0x7, "CCAP1_HSYNC"),
522 MA35_MUX(0x8, "RGMII0_RXD3")),570 MA35_MUX(0x8, "RGMII0_RXD3")),
523 MA35_PIN(71, PE11, 0xa4, 0xc,571 MA35_PIN(75, PE11, 0xa4, 0xc,
524 MA35_MUX(0x0, "GPE11"),572 MA35_MUX(0x0, "GPE11"),
525 MA35_MUX(0x2, "UART15_nRTS"),573 MA35_MUX(0x2, "UART15_nRTS"),
526 MA35_MUX(0x3, "UART14_TXD"),574 MA35_MUX(0x3, "UART14_TXD"),
527 MA35_MUX(0x5, "SPI1_CLK"),575 MA35_MUX(0x5, "SPI1_CLK"),
528 MA35_MUX(0x7, "CCAP1_VSYNC"),576 MA35_MUX(0x7, "CCAP1_VSYNC"),
529 MA35_MUX(0x8, "RGMII0_TXCLK")),577 MA35_MUX(0x8, "RGMII0_TXCLK")),
530 MA35_PIN(72, PE12, 0xa4, 0x10,578 MA35_PIN(76, PE12, 0xa4, 0x10,
531 MA35_MUX(0x0, "GPE12"),579 MA35_MUX(0x0, "GPE12"),
532 MA35_MUX(0x2, "UART15_RXD"),580 MA35_MUX(0x2, "UART15_RXD"),
533 MA35_MUX(0x5, "SPI1_MOSI"),581 MA35_MUX(0x5, "SPI1_MOSI"),
534 MA35_MUX(0x7, "CCAP1_DATA8"),582 MA35_MUX(0x7, "CCAP1_DATA8"),
535 MA35_MUX(0x8, "RGMII0_TXD2")),583 MA35_MUX(0x8, "RGMII0_TXD2")),
536 MA35_PIN(73, PE13, 0xa4, 0x14,584 MA35_PIN(77, PE13, 0xa4, 0x14,
537 MA35_MUX(0x0, "GPE13"),585 MA35_MUX(0x0, "GPE13"),
538 MA35_MUX(0x2, "UART15_TXD"),586 MA35_MUX(0x2, "UART15_TXD"),
539 MA35_MUX(0x5, "SPI1_MISO"),587 MA35_MUX(0x5, "SPI1_MISO"),
540 MA35_MUX(0x7, "CCAP1_DATA9"),588 MA35_MUX(0x7, "CCAP1_DATA9"),
541 MA35_MUX(0x8, "RGMII0_TXD3")),589 MA35_MUX(0x8, "RGMII0_TXD3")),
542 MA35_PIN(74, PE14, 0xa4, 0x18,590 MA35_PIN(78, PE14, 0xa4, 0x18,
543 MA35_MUX(0x0, "GPE14"),591 MA35_MUX(0x0, "GPE14"),
544 MA35_MUX(0x1, "UART0_TXD")),592 MA35_MUX(0x1, "UART0_TXD")),
545 MA35_PIN(75, PE15, 0xa4, 0x1c,593 MA35_PIN(79, PE15, 0xa4, 0x1c,
546 MA35_MUX(0x0, "GPE15"),594 MA35_MUX(0x0, "GPE15"),
547 MA35_MUX(0x1, "UART0_RXD")),595 MA35_MUX(0x1, "UART0_RXD")),
548 MA35_PIN(76, PF0, 0xa8, 0x0,596 MA35_PIN(80, PF0, 0xa8, 0x0,
549 MA35_MUX(0x0, "GPF0"),597 MA35_MUX(0x0, "GPF0"),
550 MA35_MUX(0x2, "UART2_nCTS"),598 MA35_MUX(0x2, "UART2_nCTS"),
551 MA35_MUX(0x3, "UART1_RXD"),599 MA35_MUX(0x3, "UART1_RXD"),
@@ -553,7 +601,7 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { · 1 unmodified line
553 MA35_MUX(0x8, "RGMII1_MDC"),601 MA35_MUX(0x8, "RGMII1_MDC"),
554 MA35_MUX(0x9, "RMII1_MDC"),602 MA35_MUX(0x9, "RMII1_MDC"),
555 MA35_MUX(0xe, "KPI_COL0")),603 MA35_MUX(0xe, "KPI_COL0")),
556 MA35_PIN(77, PF1, 0xa8, 0x4,604 MA35_PIN(81, PF1, 0xa8, 0x4,
557 MA35_MUX(0x0, "GPF1"),605 MA35_MUX(0x0, "GPF1"),
558 MA35_MUX(0x2, "UART2_nRTS"),606 MA35_MUX(0x2, "UART2_nRTS"),
559 MA35_MUX(0x3, "UART1_TXD"),607 MA35_MUX(0x3, "UART1_TXD"),
@@ -561,21 +609,21 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { · 1 unmodified line
561 MA35_MUX(0x8, "RGMII1_MDIO"),609 MA35_MUX(0x8, "RGMII1_MDIO"),
562 MA35_MUX(0x9, "RMII1_MDIO"),610 MA35_MUX(0x9, "RMII1_MDIO"),
563 MA35_MUX(0xe, "KPI_COL1")),611 MA35_MUX(0xe, "KPI_COL1")),
564 MA35_PIN(78, PF2, 0xa8, 0x8,612 MA35_PIN(82, PF2, 0xa8, 0x8,
565 MA35_MUX(0x0, "GPF2"),613 MA35_MUX(0x0, "GPF2"),
566 MA35_MUX(0x2, "UART2_RXD"),614 MA35_MUX(0x2, "UART2_RXD"),
567 MA35_MUX(0x6, "RGMII0_TXD2"),615 MA35_MUX(0x6, "RGMII0_TXD2"),
568 MA35_MUX(0x8, "RGMII1_TXCTL"),616 MA35_MUX(0x8, "RGMII1_TXCTL"),
569 MA35_MUX(0x9, "RMII1_TXEN"),617 MA35_MUX(0x9, "RMII1_TXEN"),
570 MA35_MUX(0xe, "KPI_COL2")),618 MA35_MUX(0xe, "KPI_COL2")),
571 MA35_PIN(79, PF3, 0xa8, 0xc,619 MA35_PIN(83, PF3, 0xa8, 0xc,
572 MA35_MUX(0x0, "GPF3"),620 MA35_MUX(0x0, "GPF3"),
573 MA35_MUX(0x2, "UART2_TXD"),621 MA35_MUX(0x2, "UART2_TXD"),
574 MA35_MUX(0x6, "RGMII0_TXD3"),622 MA35_MUX(0x6, "RGMII0_TXD3"),
575 MA35_MUX(0x8, "RGMII1_TXD0"),623 MA35_MUX(0x8, "RGMII1_TXD0"),
576 MA35_MUX(0x9, "RMII1_TXD0"),624 MA35_MUX(0x9, "RMII1_TXD0"),
577 MA35_MUX(0xe, "KPI_COL3")),625 MA35_MUX(0xe, "KPI_COL3")),
578 MA35_PIN(80, PF4, 0xa8, 0x10,626 MA35_PIN(84, PF4, 0xa8, 0x10,
579 MA35_MUX(0x0, "GPF4"),627 MA35_MUX(0x0, "GPF4"),
580 MA35_MUX(0x2, "UART11_nCTS"),628 MA35_MUX(0x2, "UART11_nCTS"),
581 MA35_MUX(0x3, "UART10_RXD"),629 MA35_MUX(0x3, "UART10_RXD"),
@@ -583,9 +631,10 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { · 1 unmodified line
583 MA35_MUX(0x5, "SPI1_SS0"),631 MA35_MUX(0x5, "SPI1_SS0"),
584 MA35_MUX(0x8, "RGMII1_TXD1"),632 MA35_MUX(0x8, "RGMII1_TXD1"),
585 MA35_MUX(0x9, "RMII1_TXD1"),633 MA35_MUX(0x9, "RMII1_TXD1"),
634 MA35_MUX(0xc, "USBHL0_DM"),
586 MA35_MUX(0xd, "CAN2_RXD"),635 MA35_MUX(0xd, "CAN2_RXD"),
587 MA35_MUX(0xe, "KPI_ROW0")),636 MA35_MUX(0xe, "KPI_ROW0")),
588 MA35_PIN(81, PF5, 0xa8, 0x14,637 MA35_PIN(85, PF5, 0xa8, 0x14,
589 MA35_MUX(0x0, "GPF5"),638 MA35_MUX(0x0, "GPF5"),
590 MA35_MUX(0x2, "UART11_nRTS"),639 MA35_MUX(0x2, "UART11_nRTS"),
591 MA35_MUX(0x3, "UART10_TXD"),640 MA35_MUX(0x3, "UART10_TXD"),
@@ -593,9 +642,10 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { · 1 unmodified line
593 MA35_MUX(0x5, "SPI1_CLK"),642 MA35_MUX(0x5, "SPI1_CLK"),
594 MA35_MUX(0x8, "RGMII1_RXCLK"),643 MA35_MUX(0x8, "RGMII1_RXCLK"),
595 MA35_MUX(0x9, "RMII1_REFCLK"),644 MA35_MUX(0x9, "RMII1_REFCLK"),
645 MA35_MUX(0xc, "USBHL0_DP"),
596 MA35_MUX(0xd, "CAN2_TXD"),646 MA35_MUX(0xd, "CAN2_TXD"),
597 MA35_MUX(0xe, "KPI_ROW1")),647 MA35_MUX(0xe, "KPI_ROW1")),
598 MA35_PIN(82, PF6, 0xa8, 0x18,648 MA35_PIN(86, PF6, 0xa8, 0x18,
599 MA35_MUX(0x0, "GPF6"),649 MA35_MUX(0x0, "GPF6"),
600 MA35_MUX(0x2, "UART11_RXD"),650 MA35_MUX(0x2, "UART11_RXD"),
601 MA35_MUX(0x4, "I2S0_DI"),651 MA35_MUX(0x4, "I2S0_DI"),
@@ -605,7 +655,7 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { · 3 unmodified lines
605 MA35_MUX(0xa, "I2C4_SDA"),655 MA35_MUX(0xa, "I2C4_SDA"),
606 MA35_MUX(0xd, "SC0_CLK"),656 MA35_MUX(0xd, "SC0_CLK"),
607 MA35_MUX(0xe, "KPI_ROW2")),657 MA35_MUX(0xe, "KPI_ROW2")),
608 MA35_PIN(83, PF7, 0xa8, 0x1c,658 MA35_PIN(87, PF7, 0xa8, 0x1c,
609 MA35_MUX(0x0, "GPF7"),659 MA35_MUX(0x0, "GPF7"),
610 MA35_MUX(0x2, "UART11_TXD"),660 MA35_MUX(0x2, "UART11_TXD"),
611 MA35_MUX(0x4, "I2S0_DO"),661 MA35_MUX(0x4, "I2S0_DO"),
@@ -615,7 +665,7 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { · 3 unmodified lines
615 MA35_MUX(0xa, "I2C4_SCL"),665 MA35_MUX(0xa, "I2C4_SCL"),
616 MA35_MUX(0xd, "SC0_DAT"),666 MA35_MUX(0xd, "SC0_DAT"),
617 MA35_MUX(0xe, "KPI_ROW3")),667 MA35_MUX(0xe, "KPI_ROW3")),
618 MA35_PIN(84, PF8, 0xac, 0x0,668 MA35_PIN(88, PF8, 0xac, 0x0,
619 MA35_MUX(0x0, "GPF8"),669 MA35_MUX(0x0, "GPF8"),
620 MA35_MUX(0x2, "UART13_RXD"),670 MA35_MUX(0x2, "UART13_RXD"),
621 MA35_MUX(0x4, "I2C5_SDA"),671 MA35_MUX(0x4, "I2C5_SDA"),
@@ -624,7 +674,7 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { · 2 unmodified lines
624 MA35_MUX(0x9, "RMII1_RXD1"),674 MA35_MUX(0x9, "RMII1_RXD1"),
625 MA35_MUX(0xd, "SC0_RST"),675 MA35_MUX(0xd, "SC0_RST"),
626 MA35_MUX(0xe, "KPI_COL4")),676 MA35_MUX(0xe, "KPI_COL4")),
627 MA35_PIN(85, PF9, 0xac, 0x4,677 MA35_PIN(89, PF9, 0xac, 0x4,
628 MA35_MUX(0x0, "GPF9"),678 MA35_MUX(0x0, "GPF9"),
629 MA35_MUX(0x2, "UART13_TXD"),679 MA35_MUX(0x2, "UART13_TXD"),
630 MA35_MUX(0x4, "I2C5_SCL"),680 MA35_MUX(0x4, "I2C5_SCL"),
@@ -633,7 +683,7 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { · 2 unmodified lines
633 MA35_MUX(0x9, "RMII1_RXERR"),683 MA35_MUX(0x9, "RMII1_RXERR"),
634 MA35_MUX(0xd, "SC0_PWR"),684 MA35_MUX(0xd, "SC0_PWR"),
635 MA35_MUX(0xe, "KPI_COL5")),685 MA35_MUX(0xe, "KPI_COL5")),
636 MA35_PIN(86, PF10, 0xac, 0x8,686 MA35_PIN(90, PF10, 0xac, 0x8,
637 MA35_MUX(0x0, "GPF10"),687 MA35_MUX(0x0, "GPF10"),
638 MA35_MUX(0x2, "UART13_nCTS"),688 MA35_MUX(0x2, "UART13_nCTS"),
639 MA35_MUX(0x5, "I2S0_LRCK"),689 MA35_MUX(0x5, "I2S0_LRCK"),
@@ -641,7 +691,7 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { · 1 unmodified line
641 MA35_MUX(0x8, "RGMII1_RXD3"),691 MA35_MUX(0x8, "RGMII1_RXD3"),
642 MA35_MUX(0x9, "SC0_CLK"),692 MA35_MUX(0x9, "SC0_CLK"),
643 MA35_MUX(0xe, "KPI_COL6")),693 MA35_MUX(0xe, "KPI_COL6")),
644 MA35_PIN(87, PF11, 0xac, 0xc,694 MA35_PIN(91, PF11, 0xac, 0xc,
645 MA35_MUX(0x0, "GPF11"),695 MA35_MUX(0x0, "GPF11"),
646 MA35_MUX(0x2, "UART13_nRTS"),696 MA35_MUX(0x2, "UART13_nRTS"),
647 MA35_MUX(0x5, "I2S0_BCLK"),697 MA35_MUX(0x5, "I2S0_BCLK"),
@@ -649,21 +699,21 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { · 1 unmodified line
649 MA35_MUX(0x8, "RGMII1_TXCLK"),699 MA35_MUX(0x8, "RGMII1_TXCLK"),
650 MA35_MUX(0x9, "SC0_DAT"),700 MA35_MUX(0x9, "SC0_DAT"),
651 MA35_MUX(0xe, "KPI_COL7")),701 MA35_MUX(0xe, "KPI_COL7")),
652 MA35_PIN(88, PF12, 0xac, 0x10,702 MA35_PIN(92, PF12, 0xac, 0x10,
653 MA35_MUX(0x0, "GPF12"),703 MA35_MUX(0x0, "GPF12"),
654 MA35_MUX(0x5, "I2S0_DI"),704 MA35_MUX(0x5, "I2S0_DI"),
655 MA35_MUX(0x6, "SPI1_MOSI"),705 MA35_MUX(0x6, "SPI1_MOSI"),
656 MA35_MUX(0x8, "RGMII1_TXD2"),706 MA35_MUX(0x8, "RGMII1_TXD2"),
657 MA35_MUX(0x9, "SC0_RST"),707 MA35_MUX(0x9, "SC0_RST"),
658 MA35_MUX(0xe, "KPI_ROW4")),708 MA35_MUX(0xe, "KPI_ROW4")),
659 MA35_PIN(89, PF13, 0xac, 0x14,709 MA35_PIN(93, PF13, 0xac, 0x14,
660 MA35_MUX(0x0, "GPF13"),710 MA35_MUX(0x0, "GPF13"),
661 MA35_MUX(0x5, "I2S0_DO"),711 MA35_MUX(0x5, "I2S0_DO"),
662 MA35_MUX(0x6, "SPI1_MISO"),712 MA35_MUX(0x6, "SPI1_MISO"),
663 MA35_MUX(0x8, "RGMII1_TXD3"),713 MA35_MUX(0x8, "RGMII1_TXD3"),
664 MA35_MUX(0x9, "SC0_PWR"),714 MA35_MUX(0x9, "SC0_PWR"),
665 MA35_MUX(0xe, "KPI_ROW5")),715 MA35_MUX(0xe, "KPI_ROW5")),
666 MA35_PIN(90, PF14, 0xac, 0x18,716 MA35_PIN(94, PF14, 0xac, 0x18,
667 MA35_MUX(0x0, "GPF14"),717 MA35_MUX(0x0, "GPF14"),
668 MA35_MUX(0x1, "EPWM2_BRAKE0"),718 MA35_MUX(0x1, "EPWM2_BRAKE0"),
669 MA35_MUX(0x2, "EADC0_ST"),719 MA35_MUX(0x2, "EADC0_ST"),
@@ -679,10 +729,10 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { · 9 unmodified lines
679 MA35_MUX(0xd, "SPI1_SS1"),729 MA35_MUX(0xd, "SPI1_SS1"),
680 MA35_MUX(0xe, "QEI2_INDEX"),730 MA35_MUX(0xe, "QEI2_INDEX"),
681 MA35_MUX(0xf, "I2S0_MCLK")),731 MA35_MUX(0xf, "I2S0_MCLK")),
682 MA35_PIN(91, PF15, 0xac, 0x1c,732 MA35_PIN(95, PF15, 0xac, 0x1c,
683 MA35_MUX(0x0, "GPF15"),733 MA35_MUX(0x0, "GPF15"),
684 MA35_MUX(0x1, "HSUSB0_VBUSVLD")),734 MA35_MUX(0x1, "HSUSB0_VBUSVLD")),
685 MA35_PIN(92, PG0, 0xb0, 0x0,735 MA35_PIN(96, PG0, 0xb0, 0x0,
686 MA35_MUX(0x0, "GPG0"),736 MA35_MUX(0x0, "GPG0"),
687 MA35_MUX(0x1, "EPWM0_CH0"),737 MA35_MUX(0x1, "EPWM0_CH0"),
688 MA35_MUX(0x2, "UART7_TXD"),738 MA35_MUX(0x2, "UART7_TXD"),
@@ -696,19 +746,20 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { · 7 unmodified lines
696 MA35_MUX(0xc, "CLKO"),746 MA35_MUX(0xc, "CLKO"),
697 MA35_MUX(0xd, "INT0"),747 MA35_MUX(0xd, "INT0"),
698 MA35_MUX(0xf, "EBI_ADR15")),748 MA35_MUX(0xf, "EBI_ADR15")),
699 MA35_PIN(93, PG1, 0xb0, 0x4,749 MA35_PIN(97, PG1, 0xb0, 0x4,
700 MA35_MUX(0x0, "GPG1"),750 MA35_MUX(0x0, "GPG1"),
701 MA35_MUX(0x1, "EPWM0_CH3"),751 MA35_MUX(0x1, "EPWM0_CH3"),
702 MA35_MUX(0x2, "UART9_nRTS"),752 MA35_MUX(0x2, "UART9_nRTS"),
703 MA35_MUX(0x3, "UART6_TXD"),753 MA35_MUX(0x3, "UART6_TXD"),
704 MA35_MUX(0x4, "I2C4_SCL"),754 MA35_MUX(0x4, "I2C4_SCL"),
705 MA35_MUX(0x5, "CAN2_TXD"),755 MA35_MUX(0x5, "CAN2_TXD"),
756 MA35_MUX(0x6, "USBHL0_DP"),
706 MA35_MUX(0x7, "EBI_nCS0"),757 MA35_MUX(0x7, "EBI_nCS0"),
707 MA35_MUX(0x9, "QEI0_B"),758 MA35_MUX(0x9, "QEI0_B"),
708 MA35_MUX(0xb, "TM1_EXT"),759 MA35_MUX(0xb, "TM1_EXT"),
709 MA35_MUX(0xe, "RGMII1_PPS"),760 MA35_MUX(0xe, "RGMII1_PPS"),
710 MA35_MUX(0xf, "RMII1_PPS")),761 MA35_MUX(0xf, "RMII1_PPS")),
711 MA35_PIN(94, PG2, 0xb0, 0x8,762 MA35_PIN(98, PG2, 0xb0, 0x8,
712 MA35_MUX(0x0, "GPG2"),763 MA35_MUX(0x0, "GPG2"),
713 MA35_MUX(0x1, "EPWM0_CH4"),764 MA35_MUX(0x1, "EPWM0_CH4"),
714 MA35_MUX(0x2, "UART9_RXD"),765 MA35_MUX(0x2, "UART9_RXD"),
@@ -719,7 +770,7 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { · 4 unmodified lines
719 MA35_MUX(0xa, "QEI0_A"),770 MA35_MUX(0xa, "QEI0_A"),
720 MA35_MUX(0xb, "TM3"),771 MA35_MUX(0xb, "TM3"),
721 MA35_MUX(0xd, "INT1")),772 MA35_MUX(0xd, "INT1")),
722 MA35_PIN(95, PG3, 0xb0, 0xc,773 MA35_PIN(99, PG3, 0xb0, 0xc,
723 MA35_MUX(0x0, "GPG3"),774 MA35_MUX(0x0, "GPG3"),
724 MA35_MUX(0x1, "EPWM0_CH5"),775 MA35_MUX(0x1, "EPWM0_CH5"),
725 MA35_MUX(0x2, "UART9_TXD"),776 MA35_MUX(0x2, "UART9_TXD"),
@@ -731,7 +782,7 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { · 5 unmodified lines
731 MA35_MUX(0xa, "QEI0_B"),782 MA35_MUX(0xa, "QEI0_B"),
732 MA35_MUX(0xb, "TM3_EXT"),783 MA35_MUX(0xb, "TM3_EXT"),
733 MA35_MUX(0xc, "I2S1_MCLK")),784 MA35_MUX(0xc, "I2S1_MCLK")),
734 MA35_PIN(96, PG4, 0xb0, 0x10,785 MA35_PIN(100, PG4, 0xb0, 0x10,
735 MA35_MUX(0x0, "GPG4"),786 MA35_MUX(0x0, "GPG4"),
736 MA35_MUX(0x1, "EPWM1_CH0"),787 MA35_MUX(0x1, "EPWM1_CH0"),
737 MA35_MUX(0x2, "UART5_nCTS"),788 MA35_MUX(0x2, "UART5_nCTS"),
@@ -745,7 +796,7 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { · 7 unmodified lines
745 MA35_MUX(0xb, "TM4"),796 MA35_MUX(0xb, "TM4"),
746 MA35_MUX(0xd, "INT2"),797 MA35_MUX(0xd, "INT2"),
747 MA35_MUX(0xe, "ECAP1_IC2")),798 MA35_MUX(0xe, "ECAP1_IC2")),
748 MA35_PIN(97, PG5, 0xb0, 0x14,799 MA35_PIN(101, PG5, 0xb0, 0x14,
749 MA35_MUX(0x0, "GPG5"),800 MA35_MUX(0x0, "GPG5"),
750 MA35_MUX(0x1, "EPWM1_CH1"),801 MA35_MUX(0x1, "EPWM1_CH1"),
751 MA35_MUX(0x2, "UART5_nRTS"),802 MA35_MUX(0x2, "UART5_nRTS"),
@@ -757,7 +808,7 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { · 5 unmodified lines
757 MA35_MUX(0x9, "I2S1_DI"),808 MA35_MUX(0x9, "I2S1_DI"),
758 MA35_MUX(0xa, "SC1_DAT"),809 MA35_MUX(0xa, "SC1_DAT"),
759 MA35_MUX(0xb, "TM4_EXT")),810 MA35_MUX(0xb, "TM4_EXT")),
760 MA35_PIN(98, PG6, 0xb0, 0x18,811 MA35_PIN(102, PG6, 0xb0, 0x18,
761 MA35_MUX(0x0, "GPG6"),812 MA35_MUX(0x0, "GPG6"),
762 MA35_MUX(0x1, "EPWM1_CH2"),813 MA35_MUX(0x1, "EPWM1_CH2"),
763 MA35_MUX(0x2, "UART5_RXD"),814 MA35_MUX(0x2, "UART5_RXD"),
@@ -769,7 +820,7 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { · 5 unmodified lines
769 MA35_MUX(0xa, "SC1_RST"),820 MA35_MUX(0xa, "SC1_RST"),
770 MA35_MUX(0xb, "TM7"),821 MA35_MUX(0xb, "TM7"),
771 MA35_MUX(0xd, "INT3")),822 MA35_MUX(0xd, "INT3")),
772 MA35_PIN(99, PG7, 0xb0, 0x1c,823 MA35_PIN(103, PG7, 0xb0, 0x1c,
773 MA35_MUX(0x0, "GPG7"),824 MA35_MUX(0x0, "GPG7"),
774 MA35_MUX(0x1, "EPWM1_CH3"),825 MA35_MUX(0x1, "EPWM1_CH3"),
775 MA35_MUX(0x2, "UART5_TXD"),826 MA35_MUX(0x2, "UART5_TXD"),
@@ -780,27 +831,29 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { · 4 unmodified lines
780 MA35_MUX(0x9, "I2S1_LRCK"),831 MA35_MUX(0x9, "I2S1_LRCK"),
781 MA35_MUX(0xa, "SC1_PWR"),832 MA35_MUX(0xa, "SC1_PWR"),
782 MA35_MUX(0xb, "TM7_EXT")),833 MA35_MUX(0xb, "TM7_EXT")),
783 MA35_PIN(100, PG8, 0xb4, 0x0,834 MA35_PIN(104, PG8, 0xb4, 0x0,
784 MA35_MUX(0x0, "GPG8"),835 MA35_MUX(0x0, "GPG8"),
785 MA35_MUX(0x1, "EPWM1_CH4"),836 MA35_MUX(0x1, "EPWM1_CH4"),
786 MA35_MUX(0x2, "UART12_RXD"),837 MA35_MUX(0x2, "UART12_RXD"),
787 MA35_MUX(0x3, "CAN3_RXD"),838 MA35_MUX(0x3, "CAN3_RXD"),
839 MA35_MUX(0x4, "USBHL4_DM"),
788 MA35_MUX(0x5, "SPI2_SS0"),840 MA35_MUX(0x5, "SPI2_SS0"),
789 MA35_MUX(0x6, "LCM_VSYNC"),841 MA35_MUX(0x6, "LCM_VSYNC"),
790 MA35_MUX(0x7, "I2C3_SDA"),842 MA35_MUX(0x7, "I2C3_SDA"),
791 MA35_MUX(0xc, "EBI_AD7"),843 MA35_MUX(0xc, "EBI_AD7"),
792 MA35_MUX(0xd, "EBI_nCS0")),844 MA35_MUX(0xd, "EBI_nCS0")),
793 MA35_PIN(101, PG9, 0xb4, 0x4,845 MA35_PIN(105, PG9, 0xb4, 0x4,
794 MA35_MUX(0x0, "GPG9"),846 MA35_MUX(0x0, "GPG9"),
795 MA35_MUX(0x1, "EPWM1_CH5"),847 MA35_MUX(0x1, "EPWM1_CH5"),
796 MA35_MUX(0x2, "UART12_TXD"),848 MA35_MUX(0x2, "UART12_TXD"),
797 MA35_MUX(0x3, "CAN3_TXD"),849 MA35_MUX(0x3, "CAN3_TXD"),
850 MA35_MUX(0x4, "USBHL4_DP"),
798 MA35_MUX(0x5, "SPI2_CLK"),851 MA35_MUX(0x5, "SPI2_CLK"),
799 MA35_MUX(0x6, "LCM_HSYNC"),852 MA35_MUX(0x6, "LCM_HSYNC"),
800 MA35_MUX(0x7, "I2C3_SCL"),853 MA35_MUX(0x7, "I2C3_SCL"),
801 MA35_MUX(0xc, "EBI_AD8"),854 MA35_MUX(0xc, "EBI_AD8"),
802 MA35_MUX(0xd, "EBI_nCS1")),855 MA35_MUX(0xd, "EBI_nCS1")),
803 MA35_PIN(102, PG10, 0xb4, 0x8,856 MA35_PIN(106, PG10, 0xb4, 0x8,
804 MA35_MUX(0x0, "GPG10"),857 MA35_MUX(0x0, "GPG10"),
805 MA35_MUX(0x2, "UART12_nRTS"),858 MA35_MUX(0x2, "UART12_nRTS"),
806 MA35_MUX(0x3, "UART13_TXD"),859 MA35_MUX(0x3, "UART13_TXD"),
@@ -808,7 +861,7 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { · 1 unmodified line
808 MA35_MUX(0x6, "LCM_CLK"),861 MA35_MUX(0x6, "LCM_CLK"),
809 MA35_MUX(0xc, "EBI_AD9"),862 MA35_MUX(0xc, "EBI_AD9"),
810 MA35_MUX(0xd, "EBI_nWRH")),863 MA35_MUX(0xd, "EBI_nWRH")),
811 MA35_PIN(103, PG11, 0xb4, 0xc,864 MA35_PIN(107, PG11, 0xb4, 0xc,
812 MA35_MUX(0x0, "GPG11"),865 MA35_MUX(0x0, "GPG11"),
813 MA35_MUX(0x3, "JTAG_TDO"),866 MA35_MUX(0x3, "JTAG_TDO"),
814 MA35_MUX(0x5, "I2S0_MCLK"),867 MA35_MUX(0x5, "I2S0_MCLK"),
@@ -816,93 +869,93 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { · 1 unmodified line
816 MA35_MUX(0x7, "EBI_nWRH"),869 MA35_MUX(0x7, "EBI_nWRH"),
817 MA35_MUX(0x8, "EBI_nCS1"),870 MA35_MUX(0x8, "EBI_nCS1"),
818 MA35_MUX(0xa, "EBI_AD0")),871 MA35_MUX(0xa, "EBI_AD0")),
819 MA35_PIN(104, PG12, 0xb4, 0x10,872 MA35_PIN(108, PG12, 0xb4, 0x10,
820 MA35_MUX(0x0, "GPG12"),873 MA35_MUX(0x0, "GPG12"),
821 MA35_MUX(0x3, "JTAG_TCK/SW_CLK"),874 MA35_MUX(0x3, "JTAG_TCK/SW_CLK"),
822 MA35_MUX(0x5, "I2S0_LRCK"),875 MA35_MUX(0x5, "I2S0_LRCK"),
823 MA35_MUX(0x7, "EBI_nWRL"),876 MA35_MUX(0x7, "EBI_nWRL"),
824 MA35_MUX(0xa, "EBI_AD1")),877 MA35_MUX(0xa, "EBI_AD1")),
825 MA35_PIN(105, PG13, 0xb4, 0x14,878 MA35_PIN(109, PG13, 0xb4, 0x14,
826 MA35_MUX(0x0, "GPG13"),879 MA35_MUX(0x0, "GPG13"),
827 MA35_MUX(0x3, "JTAG_TMS/SW_DIO"),880 MA35_MUX(0x3, "JTAG_TMS/SW_DIO"),
828 MA35_MUX(0x5, "I2S0_BCLK"),881 MA35_MUX(0x5, "I2S0_BCLK"),
829 MA35_MUX(0x7, "EBI_MCLK"),882 MA35_MUX(0x7, "EBI_MCLK"),
830 MA35_MUX(0xa, "EBI_AD2")),883 MA35_MUX(0xa, "EBI_AD2")),
831 MA35_PIN(106, PG14, 0xb4, 0x18,884 MA35_PIN(110, PG14, 0xb4, 0x18,
832 MA35_MUX(0x0, "GPG14"),885 MA35_MUX(0x0, "GPG14"),
833 MA35_MUX(0x3, "JTAG_TDI"),886 MA35_MUX(0x3, "JTAG_TDI"),
834 MA35_MUX(0x5, "I2S0_DI"),887 MA35_MUX(0x5, "I2S0_DI"),
835 MA35_MUX(0x6, "NAND_nCS1"),888 MA35_MUX(0x6, "NAND_nCS1"),
836 MA35_MUX(0x7, "EBI_ALE"),889 MA35_MUX(0x7, "EBI_ALE"),
837 MA35_MUX(0xa, "EBI_AD3")),890 MA35_MUX(0xa, "EBI_AD3")),
838 MA35_PIN(107, PG15, 0xb4, 0x1c,891 MA35_PIN(111, PG15, 0xb4, 0x1c,
839 MA35_MUX(0x0, "GPG15"),892 MA35_MUX(0x0, "GPG15"),
840 MA35_MUX(0x3, "JTAG_nTRST"),893 MA35_MUX(0x3, "JTAG_nTRST"),
841 MA35_MUX(0x5, "I2S0_DO"),894 MA35_MUX(0x5, "I2S0_DO"),
842 MA35_MUX(0x7, "EBI_nCS0"),895 MA35_MUX(0x7, "EBI_nCS0"),
843 MA35_MUX(0xa, "EBI_AD4")),896 MA35_MUX(0xa, "EBI_AD4")),
844 MA35_PIN(108, PH0, 0xb8, 0x0,897 MA35_PIN(112, PH0, 0xb8, 0x0,
845 MA35_MUX(0x0, "GPH0"),898 MA35_MUX(0x0, "GPH0"),
846 MA35_MUX(0x2, "UART8_nCTS"),899 MA35_MUX(0x2, "UART8_nCTS"),
847 MA35_MUX(0x3, "UART7_RXD"),900 MA35_MUX(0x3, "UART7_RXD"),
848 MA35_MUX(0x6, "LCM_DATA8")),901 MA35_MUX(0x6, "LCM_DATA8")),
849 MA35_PIN(109, PH1, 0xb8, 0x4,902 MA35_PIN(113, PH1, 0xb8, 0x4,
850 MA35_MUX(0x0, "GPH1"),903 MA35_MUX(0x0, "GPH1"),
851 MA35_MUX(0x2, "UART8_nRTS"),904 MA35_MUX(0x2, "UART8_nRTS"),
852 MA35_MUX(0x3, "UART7_TXD"),905 MA35_MUX(0x3, "UART7_TXD"),
853 MA35_MUX(0x6, "LCM_DATA9")),906 MA35_MUX(0x6, "LCM_DATA9")),
854 MA35_PIN(110, PH2, 0xb8, 0x8,907 MA35_PIN(114, PH2, 0xb8, 0x8,
855 MA35_MUX(0x0, "GPH2"),908 MA35_MUX(0x0, "GPH2"),
856 MA35_MUX(0x2, "UART8_RXD"),909 MA35_MUX(0x2, "UART8_RXD"),
857 MA35_MUX(0x6, "LCM_DATA10")),910 MA35_MUX(0x6, "LCM_DATA10")),
858 MA35_PIN(111, PH3, 0xb8, 0xc,911 MA35_PIN(115, PH3, 0xb8, 0xc,
859 MA35_MUX(0x0, "GPH3"),912 MA35_MUX(0x0, "GPH3"),
860 MA35_MUX(0x2, "UART8_TXD"),913 MA35_MUX(0x2, "UART8_TXD"),
861 MA35_MUX(0x6, "LCM_DATA11")),914 MA35_MUX(0x6, "LCM_DATA11")),
862 MA35_PIN(112, PH4, 0xb8, 0x10,915 MA35_PIN(116, PH4, 0xb8, 0x10,
863 MA35_MUX(0x0, "GPH4"),916 MA35_MUX(0x0, "GPH4"),
864 MA35_MUX(0x2, "UART10_nCTS"),917 MA35_MUX(0x2, "UART10_nCTS"),
865 MA35_MUX(0x3, "UART9_RXD"),918 MA35_MUX(0x3, "UART9_RXD"),
866 MA35_MUX(0x6, "LCM_DATA12")),919 MA35_MUX(0x6, "LCM_DATA12")),
867 MA35_PIN(113, PH5, 0xb8, 0x14,920 MA35_PIN(117, PH5, 0xb8, 0x14,
868 MA35_MUX(0x0, "GPH5"),921 MA35_MUX(0x0, "GPH5"),
869 MA35_MUX(0x2, "UART10_nRTS"),922 MA35_MUX(0x2, "UART10_nRTS"),
870 MA35_MUX(0x3, "UART9_TXD"),923 MA35_MUX(0x3, "UART9_TXD"),
871 MA35_MUX(0x6, "LCM_DATA13")),924 MA35_MUX(0x6, "LCM_DATA13")),
872 MA35_PIN(114, PH6, 0xb8, 0x18,925 MA35_PIN(118, PH6, 0xb8, 0x18,
873 MA35_MUX(0x0, "GPH6"),926 MA35_MUX(0x0, "GPH6"),
874 MA35_MUX(0x2, "UART10_RXD"),927 MA35_MUX(0x2, "UART10_RXD"),
875 MA35_MUX(0x6, "LCM_DATA14")),928 MA35_MUX(0x6, "LCM_DATA14")),
876 MA35_PIN(115, PH7, 0xb8, 0x1c,929 MA35_PIN(119, PH7, 0xb8, 0x1c,
877 MA35_MUX(0x0, "GPH7"),930 MA35_MUX(0x0, "GPH7"),
878 MA35_MUX(0x2, "UART10_TXD"),931 MA35_MUX(0x2, "UART10_TXD"),
879 MA35_MUX(0x6, "LCM_DATA15")),932 MA35_MUX(0x6, "LCM_DATA15")),
880 MA35_PIN(116, PH8, 0xbc, 0x0,933 MA35_PIN(120, PH8, 0xbc, 0x0,
881 MA35_MUX(0x0, "GPH8"),934 MA35_MUX(0x0, "GPH8"),
882 MA35_MUX(0x6, "TAMPER0")),935 MA35_MUX(0x6, "TAMPER0")),
883 MA35_PIN(117, PH9, 0xbc, 0x4,936 MA35_PIN(121, PH9, 0xbc, 0x4,
884 MA35_MUX(0x0, "GPH9"),937 MA35_MUX(0x0, "GPH9"),
885 MA35_MUX(0x4, "CLK_32KOUT"),938 MA35_MUX(0x4, "CLK_32KOUT"),
886 MA35_MUX(0x6, "TAMPER1")),939 MA35_MUX(0x6, "TAMPER1")),
887 MA35_PIN(118, PH12, 0xbc, 0x10,940 MA35_PIN(124, PH12, 0xbc, 0x10,
888 MA35_MUX(0x0, "GPH12"),941 MA35_MUX(0x0, "GPH12"),
889 MA35_MUX(0x2, "UART14_nCTS"),942 MA35_MUX(0x2, "UART14_nCTS"),
890 MA35_MUX(0x3, "UART13_RXD"),943 MA35_MUX(0x3, "UART13_RXD"),
891 MA35_MUX(0x6, "LCM_DATA20")),944 MA35_MUX(0x6, "LCM_DATA20")),
892 MA35_PIN(119, PH13, 0xbc, 0x14,945 MA35_PIN(125, PH13, 0xbc, 0x14,
893 MA35_MUX(0x0, "GPH13"),946 MA35_MUX(0x0, "GPH13"),
894 MA35_MUX(0x2, "UART14_nRTS"),947 MA35_MUX(0x2, "UART14_nRTS"),
895 MA35_MUX(0x3, "UART13_TXD"),948 MA35_MUX(0x3, "UART13_TXD"),
896 MA35_MUX(0x6, "LCM_DATA21")),949 MA35_MUX(0x6, "LCM_DATA21")),
897 MA35_PIN(120, PH14, 0xbc, 0x18,950 MA35_PIN(126, PH14, 0xbc, 0x18,
898 MA35_MUX(0x0, "GPH14"),951 MA35_MUX(0x0, "GPH14"),
899 MA35_MUX(0x2, "UART14_RXD"),952 MA35_MUX(0x2, "UART14_RXD"),
900 MA35_MUX(0x6, "LCM_DATA22")),953 MA35_MUX(0x6, "LCM_DATA22")),
901 MA35_PIN(121, PH15, 0xbc, 0x1c,954 MA35_PIN(127, PH15, 0xbc, 0x1c,
902 MA35_MUX(0x0, "GPH15"),955 MA35_MUX(0x0, "GPH15"),
903 MA35_MUX(0x2, "UART14_TXD"),956 MA35_MUX(0x2, "UART14_TXD"),
904 MA35_MUX(0x6, "LCM_DATA23")),957 MA35_MUX(0x6, "LCM_DATA23")),
905 MA35_PIN(122, PI0, 0xc0, 0x0,958 MA35_PIN(128, PI0, 0xc0, 0x0,
906 MA35_MUX(0x0, "GPI0"),959 MA35_MUX(0x0, "GPI0"),
907 MA35_MUX(0x1, "EPWM0_CH0"),960 MA35_MUX(0x1, "EPWM0_CH0"),
908 MA35_MUX(0x2, "UART12_nCTS"),961 MA35_MUX(0x2, "UART12_nCTS"),
@@ -913,7 +966,7 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { · 4 unmodified lines
913 MA35_MUX(0x8, "EBI_ADR0"),966 MA35_MUX(0x8, "EBI_ADR0"),
914 MA35_MUX(0xb, "TM0"),967 MA35_MUX(0xb, "TM0"),
915 MA35_MUX(0xc, "ECAP1_IC0")),968 MA35_MUX(0xc, "ECAP1_IC0")),
916 MA35_PIN(123, PI1, 0xc0, 0x4,969 MA35_PIN(129, PI1, 0xc0, 0x4,
917 MA35_MUX(0x0, "GPI1"),970 MA35_MUX(0x0, "GPI1"),
918 MA35_MUX(0x1, "EPWM0_CH1"),971 MA35_MUX(0x1, "EPWM0_CH1"),
919 MA35_MUX(0x2, "UART12_nRTS"),972 MA35_MUX(0x2, "UART12_nRTS"),
@@ -924,26 +977,28 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { · 4 unmodified lines
924 MA35_MUX(0x8, "EBI_ADR1"),977 MA35_MUX(0x8, "EBI_ADR1"),
925 MA35_MUX(0xb, "TM0_EXT"),978 MA35_MUX(0xb, "TM0_EXT"),
926 MA35_MUX(0xc, "ECAP1_IC1")),979 MA35_MUX(0xc, "ECAP1_IC1")),
927 MA35_PIN(124, PI2, 0xc0, 0x8,980 MA35_PIN(130, PI2, 0xc0, 0x8,
928 MA35_MUX(0x0, "GPI2"),981 MA35_MUX(0x0, "GPI2"),
929 MA35_MUX(0x1, "EPWM0_CH2"),982 MA35_MUX(0x1, "EPWM0_CH2"),
930 MA35_MUX(0x2, "UART12_RXD"),983 MA35_MUX(0x2, "UART12_RXD"),
931 MA35_MUX(0x3, "CAN0_RXD"),984 MA35_MUX(0x3, "CAN0_RXD"),
985 MA35_MUX(0x4, "USBHL2_DM"),
932 MA35_MUX(0x5, "SPI3_MOSI"),986 MA35_MUX(0x5, "SPI3_MOSI"),
933 MA35_MUX(0x7, "SC0_DAT"),987 MA35_MUX(0x7, "SC0_DAT"),
934 MA35_MUX(0x8, "EBI_ADR2"),988 MA35_MUX(0x8, "EBI_ADR2"),
935 MA35_MUX(0xb, "TM1"),989 MA35_MUX(0xb, "TM1"),
936 MA35_MUX(0xc, "ECAP1_IC2")),990 MA35_MUX(0xc, "ECAP1_IC2")),
937 MA35_PIN(125, PI3, 0xc0, 0xc,991 MA35_PIN(131, PI3, 0xc0, 0xc,
938 MA35_MUX(0x0, "GPI3"),992 MA35_MUX(0x0, "GPI3"),
939 MA35_MUX(0x1, "EPWM0_CH3"),993 MA35_MUX(0x1, "EPWM0_CH3"),
940 MA35_MUX(0x2, "UART12_TXD"),994 MA35_MUX(0x2, "UART12_TXD"),
941 MA35_MUX(0x3, "CAN0_TXD"),995 MA35_MUX(0x3, "CAN0_TXD"),
996 MA35_MUX(0x4, "USBHL2_DP"),
942 MA35_MUX(0x5, "SPI3_MISO"),997 MA35_MUX(0x5, "SPI3_MISO"),
943 MA35_MUX(0x7, "SC0_RST"),998 MA35_MUX(0x7, "SC0_RST"),
944 MA35_MUX(0x8, "EBI_ADR3"),999 MA35_MUX(0x8, "EBI_ADR3"),
945 MA35_MUX(0xb, "TM1_EXT")),1000 MA35_MUX(0xb, "TM1_EXT")),
946 MA35_PIN(126, PI4, 0xc0, 0x10,1001 MA35_PIN(132, PI4, 0xc0, 0x10,
947 MA35_MUX(0x0, "GPI4"),1002 MA35_MUX(0x0, "GPI4"),
948 MA35_MUX(0x1, "EPWM0_CH4"),1003 MA35_MUX(0x1, "EPWM0_CH4"),
949 MA35_MUX(0x2, "UART14_nCTS"),1004 MA35_MUX(0x2, "UART14_nCTS"),
@@ -953,7 +1008,7 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { · 3 unmodified lines
953 MA35_MUX(0x6, "I2S1_LRCK"),1008 MA35_MUX(0x6, "I2S1_LRCK"),
954 MA35_MUX(0x8, "EBI_ADR4"),1009 MA35_MUX(0x8, "EBI_ADR4"),
955 MA35_MUX(0xd, "INT0")),1010 MA35_MUX(0xd, "INT0")),
956 MA35_PIN(127, PI5, 0xc0, 0x14,1011 MA35_PIN(133, PI5, 0xc0, 0x14,
957 MA35_MUX(0x0, "GPI5"),1012 MA35_MUX(0x0, "GPI5"),
958 MA35_MUX(0x1, "EPWM0_CH5"),1013 MA35_MUX(0x1, "EPWM0_CH5"),
959 MA35_MUX(0x2, "UART14_nRTS"),1014 MA35_MUX(0x2, "UART14_nRTS"),
@@ -962,65 +1017,67 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { · 2 unmodified lines
962 MA35_MUX(0x6, "I2S1_BCLK"),1017 MA35_MUX(0x6, "I2S1_BCLK"),
963 MA35_MUX(0x8, "EBI_ADR5"),1018 MA35_MUX(0x8, "EBI_ADR5"),
964 MA35_MUX(0xd, "INT1")),1019 MA35_MUX(0xd, "INT1")),
965 MA35_PIN(128, PI6, 0xc0, 0x18,1020 MA35_PIN(134, PI6, 0xc0, 0x18,
966 MA35_MUX(0x0, "GPI6"),1021 MA35_MUX(0x0, "GPI6"),
967 MA35_MUX(0x1, "EPWM0_BRAKE0"),1022 MA35_MUX(0x1, "EPWM0_BRAKE0"),
968 MA35_MUX(0x2, "UART14_RXD"),1023 MA35_MUX(0x2, "UART14_RXD"),
969 MA35_MUX(0x3, "CAN1_RXD"),1024 MA35_MUX(0x3, "CAN1_RXD"),
1025 MA35_MUX(0x4, "USBHL3_DM"),
970 MA35_MUX(0x6, "I2S1_DI"),1026 MA35_MUX(0x6, "I2S1_DI"),
971 MA35_MUX(0x8, "EBI_ADR6"),1027 MA35_MUX(0x8, "EBI_ADR6"),
972 MA35_MUX(0xc, "QEI1_INDEX"),1028 MA35_MUX(0xc, "QEI1_INDEX"),
973 MA35_MUX(0xd, "INT2")),1029 MA35_MUX(0xd, "INT2")),
974 MA35_PIN(129, PI7, 0xc0, 0x1c,1030 MA35_PIN(135, PI7, 0xc0, 0x1c,
975 MA35_MUX(0x0, "GPI7"),1031 MA35_MUX(0x0, "GPI7"),
976 MA35_MUX(0x1, "EPWM0_BRAKE1"),1032 MA35_MUX(0x1, "EPWM0_BRAKE1"),
977 MA35_MUX(0x2, "UART14_TXD"),1033 MA35_MUX(0x2, "UART14_TXD"),
978 MA35_MUX(0x3, "CAN1_TXD"),1034 MA35_MUX(0x3, "CAN1_TXD"),
1035 MA35_MUX(0x4, "USBHL3_DP"),
979 MA35_MUX(0x6, "I2S1_DO"),1036 MA35_MUX(0x6, "I2S1_DO"),
980 MA35_MUX(0x8, "EBI_ADR7"),1037 MA35_MUX(0x8, "EBI_ADR7"),
981 MA35_MUX(0xc, "ECAP0_IC0"),1038 MA35_MUX(0xc, "ECAP0_IC0"),
982 MA35_MUX(0xd, "INT3")),1039 MA35_MUX(0xd, "INT3")),
983 MA35_PIN(130, PI8, 0xc4, 0x0,1040 MA35_PIN(136, PI8, 0xc4, 0x0,
984 MA35_MUX(0x0, "GPI8"),1041 MA35_MUX(0x0, "GPI8"),
985 MA35_MUX(0x2, "UART4_nCTS"),1042 MA35_MUX(0x2, "UART4_nCTS"),
986 MA35_MUX(0x3, "UART3_RXD"),1043 MA35_MUX(0x3, "UART3_RXD"),
987 MA35_MUX(0x6, "LCM_DATA0"),1044 MA35_MUX(0x6, "LCM_DATA0"),
988 MA35_MUX(0xc, "EBI_AD11")),1045 MA35_MUX(0xc, "EBI_AD11")),
989 MA35_PIN(131, PI9, 0xc4, 0x4,1046 MA35_PIN(137, PI9, 0xc4, 0x4,
990 MA35_MUX(0x0, "GPI9"),1047 MA35_MUX(0x0, "GPI9"),
991 MA35_MUX(0x2, "UART4_nRTS"),1048 MA35_MUX(0x2, "UART4_nRTS"),
992 MA35_MUX(0x3, "UART3_TXD"),1049 MA35_MUX(0x3, "UART3_TXD"),
993 MA35_MUX(0x6, "LCM_DATA1"),1050 MA35_MUX(0x6, "LCM_DATA1"),
994 MA35_MUX(0xc, "EBI_AD12")),1051 MA35_MUX(0xc, "EBI_AD12")),
995 MA35_PIN(132, PI10, 0xc4, 0x8,1052 MA35_PIN(138, PI10, 0xc4, 0x8,
996 MA35_MUX(0x0, "GPI10"),1053 MA35_MUX(0x0, "GPI10"),
997 MA35_MUX(0x2, "UART4_RXD"),1054 MA35_MUX(0x2, "UART4_RXD"),
998 MA35_MUX(0x6, "LCM_DATA2"),1055 MA35_MUX(0x6, "LCM_DATA2"),
999 MA35_MUX(0xc, "EBI_AD13")),1056 MA35_MUX(0xc, "EBI_AD13")),
1000 MA35_PIN(133, PI11, 0xC4, 0xc,1057 MA35_PIN(139, PI11, 0xC4, 0xc,
1001 MA35_MUX(0x0, "GPI11"),1058 MA35_MUX(0x0, "GPI11"),
1002 MA35_MUX(0x2, "UART4_TXD"),1059 MA35_MUX(0x2, "UART4_TXD"),
1003 MA35_MUX(0x6, "LCM_DATA3"),1060 MA35_MUX(0x6, "LCM_DATA3"),
1004 MA35_MUX(0xc, "EBI_AD14")),1061 MA35_MUX(0xc, "EBI_AD14")),
1005 MA35_PIN(134, PI12, 0xc4, 0x10,1062 MA35_PIN(140, PI12, 0xc4, 0x10,
1006 MA35_MUX(0x0, "GPI12"),1063 MA35_MUX(0x0, "GPI12"),
1007 MA35_MUX(0x2, "UART6_nCTS"),1064 MA35_MUX(0x2, "UART6_nCTS"),
1008 MA35_MUX(0x3, "UART5_RXD"),1065 MA35_MUX(0x3, "UART5_RXD"),
1009 MA35_MUX(0x6, "LCM_DATA4")),1066 MA35_MUX(0x6, "LCM_DATA4")),
1010 MA35_PIN(135, PI13, 0xc4, 0x14,1067 MA35_PIN(141, PI13, 0xc4, 0x14,
1011 MA35_MUX(0x0, "GPI13"),1068 MA35_MUX(0x0, "GPI13"),
1012 MA35_MUX(0x2, "UART6_nRTS"),1069 MA35_MUX(0x2, "UART6_nRTS"),
1013 MA35_MUX(0x3, "UART5_TXD"),1070 MA35_MUX(0x3, "UART5_TXD"),
1014 MA35_MUX(0x6, "LCM_DATA5")),1071 MA35_MUX(0x6, "LCM_DATA5")),
1015 MA35_PIN(136, PI14, 0xc4, 0x18,1072 MA35_PIN(142, PI14, 0xc4, 0x18,
1016 MA35_MUX(0x0, "GPI14"),1073 MA35_MUX(0x0, "GPI14"),
1017 MA35_MUX(0x2, "UART6_RXD"),1074 MA35_MUX(0x2, "UART6_RXD"),
1018 MA35_MUX(0x6, "LCM_DATA6")),1075 MA35_MUX(0x6, "LCM_DATA6")),
1019 MA35_PIN(137, PI15, 0xc4, 0x1c,1076 MA35_PIN(143, PI15, 0xc4, 0x1c,
1020 MA35_MUX(0x0, "GPI15"),1077 MA35_MUX(0x0, "GPI15"),
1021 MA35_MUX(0x2, "UART6_TXD"),1078 MA35_MUX(0x2, "UART6_TXD"),
1022 MA35_MUX(0x6, "LCM_DATA7")),1079 MA35_MUX(0x6, "LCM_DATA7")),
1023 MA35_PIN(138, PJ0, 0xc8, 0x0,1080 MA35_PIN(144, PJ0, 0xc8, 0x0,
1024 MA35_MUX(0x0, "GPJ0"),1081 MA35_MUX(0x0, "GPJ0"),
1025 MA35_MUX(0x1, "EPWM1_BRAKE0"),1082 MA35_MUX(0x1, "EPWM1_BRAKE0"),
1026 MA35_MUX(0x2, "UART8_nCTS"),1083 MA35_MUX(0x2, "UART8_nCTS"),
@@ -1034,7 +1091,7 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { · 7 unmodified lines
1034 MA35_MUX(0xa, "EBI_ADR16"),1091 MA35_MUX(0xa, "EBI_ADR16"),
1035 MA35_MUX(0xb, "EBI_nCS0"),1092 MA35_MUX(0xb, "EBI_nCS0"),
1036 MA35_MUX(0xc, "EBI_AD7")),1093 MA35_MUX(0xc, "EBI_AD7")),
1037 MA35_PIN(139, PJ1, 0xc8, 0x4,1094 MA35_PIN(145, PJ1, 0xc8, 0x4,
1038 MA35_MUX(0x0, "GPJ1"),1095 MA35_MUX(0x0, "GPJ1"),
1039 MA35_MUX(0x1, "EPWM1_BRAKE1"),1096 MA35_MUX(0x1, "EPWM1_BRAKE1"),
1040 MA35_MUX(0x2, "UART8_nRTS"),1097 MA35_MUX(0x2, "UART8_nRTS"),
@@ -1048,11 +1105,12 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { · 7 unmodified lines
1048 MA35_MUX(0xa, "EBI_ADR17"),1105 MA35_MUX(0xa, "EBI_ADR17"),
1049 MA35_MUX(0xb, "EBI_nCS1"),1106 MA35_MUX(0xb, "EBI_nCS1"),
1050 MA35_MUX(0xc, "EBI_AD8")),1107 MA35_MUX(0xc, "EBI_AD8")),
1051 MA35_PIN(140, PJ2, 0xc8, 0x8,1108 MA35_PIN(146, PJ2, 0xc8, 0x8,
1052 MA35_MUX(0x0, "GPJ2"),1109 MA35_MUX(0x0, "GPJ2"),
1053 MA35_MUX(0x1, "EPWM1_CH4"),1110 MA35_MUX(0x1, "EPWM1_CH4"),
1054 MA35_MUX(0x2, "UART8_RXD"),1111 MA35_MUX(0x2, "UART8_RXD"),
1055 MA35_MUX(0x3, "CAN1_RXD"),1112 MA35_MUX(0x3, "CAN1_RXD"),
1113 MA35_MUX(0x4, "USBHL5_DM"),
1056 MA35_MUX(0x5, "SPI2_MOSI"),1114 MA35_MUX(0x5, "SPI2_MOSI"),
1057 MA35_MUX(0x6, "eMMC1_DAT6"),1115 MA35_MUX(0x6, "eMMC1_DAT6"),
1058 MA35_MUX(0x7, "I2S0_DI"),1116 MA35_MUX(0x7, "I2S0_DI"),
@@ -1061,11 +1119,12 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { · 2 unmodified lines
1061 MA35_MUX(0xa, "EBI_ADR18"),1119 MA35_MUX(0xa, "EBI_ADR18"),
1062 MA35_MUX(0xb, "EBI_nWRH"),1120 MA35_MUX(0xb, "EBI_nWRH"),
1063 MA35_MUX(0xc, "EBI_AD9")),1121 MA35_MUX(0xc, "EBI_AD9")),
1064 MA35_PIN(141, PJ3, 0xc8, 0xc,1122 MA35_PIN(147, PJ3, 0xc8, 0xc,
1065 MA35_MUX(0x0, "GPJ3"),1123 MA35_MUX(0x0, "GPJ3"),
1066 MA35_MUX(0x1, "EPWM1_CH5"),1124 MA35_MUX(0x1, "EPWM1_CH5"),
1067 MA35_MUX(0x2, "UART8_TXD"),1125 MA35_MUX(0x2, "UART8_TXD"),
1068 MA35_MUX(0x3, "CAN1_TXD"),1126 MA35_MUX(0x3, "CAN1_TXD"),
1127 MA35_MUX(0x4, "USBHL5_DP"),
1069 MA35_MUX(0x5, "SPI2_MISO"),1128 MA35_MUX(0x5, "SPI2_MISO"),
1070 MA35_MUX(0x6, "eMMC1_DAT7"),1129 MA35_MUX(0x6, "eMMC1_DAT7"),
1071 MA35_MUX(0x7, "I2S0_DO"),1130 MA35_MUX(0x7, "I2S0_DO"),
@@ -1074,39 +1133,43 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { · 2 unmodified lines
1074 MA35_MUX(0xa, "EBI_ADR19"),1133 MA35_MUX(0xa, "EBI_ADR19"),
1075 MA35_MUX(0xb, "EBI_nWRL"),1134 MA35_MUX(0xb, "EBI_nWRL"),
1076 MA35_MUX(0xc, "EBI_AD10")),1135 MA35_MUX(0xc, "EBI_AD10")),
1077 MA35_PIN(142, PJ4, 0xc8, 0x10,1136 MA35_PIN(148, PJ4, 0xc8, 0x10,
1078 MA35_MUX(0x0, "GPJ4"),1137 MA35_MUX(0x0, "GPJ4"),
1079 MA35_MUX(0x4, "I2C3_SDA"),1138 MA35_MUX(0x4, "I2C3_SDA"),
1080 MA35_MUX(0x6, "SD1_WP")),1139 MA35_MUX(0x6, "SD1_WP")),
1081 MA35_PIN(143, PJ5, 0xc8, 0x14,1140 MA35_PIN(149, PJ5, 0xc8, 0x14,
1082 MA35_MUX(0x0, "GPJ5"),1141 MA35_MUX(0x0, "GPJ5"),
1083 MA35_MUX(0x4, "I2C3_SCL"),1142 MA35_MUX(0x4, "I2C3_SCL"),
1084 MA35_MUX(0x6, "SD1_nCD")),1143 MA35_MUX(0x6, "SD1_nCD")),
1085 MA35_PIN(144, PJ6, 0xc8, 0x18,1144 MA35_PIN(150, PJ6, 0xc8, 0x18,
1086 MA35_MUX(0x0, "GPJ6"),1145 MA35_MUX(0x0, "GPJ6"),
1087 MA35_MUX(0x3, "CAN3_RXD"),1146 MA35_MUX(0x3, "CAN3_RXD"),
1147 MA35_MUX(0x4, "USBHL0_DM"),
1088 MA35_MUX(0x6, "SD1_CMD/eMMC1_CMD")),1148 MA35_MUX(0x6, "SD1_CMD/eMMC1_CMD")),
1089 MA35_PIN(145, PJ7, 0xc8, 0x1c,1149 MA35_PIN(151, PJ7, 0xc8, 0x1c,
1090 MA35_MUX(0x0, "GPJ7"),1150 MA35_MUX(0x0, "GPJ7"),
1091 MA35_MUX(0x3, "CAN3_TXD"),1151 MA35_MUX(0x3, "CAN3_TXD"),
1152 MA35_MUX(0x4, "USBHL0_DP"),
1092 MA35_MUX(0x6, "SD1_CLK/eMMC1_CLK")),1153 MA35_MUX(0x6, "SD1_CLK/eMMC1_CLK")),
1093 MA35_PIN(146, PJ8, 0xcc, 0x0,1154 MA35_PIN(152, PJ8, 0xcc, 0x0,
1094 MA35_MUX(0x0, "GPJ8"),1155 MA35_MUX(0x0, "GPJ8"),
1095 MA35_MUX(0x4, "I2C4_SDA"),1156 MA35_MUX(0x4, "I2C4_SDA"),
1096 MA35_MUX(0x6, "SD1_DAT0/eMMC1_DAT0")),1157 MA35_MUX(0x6, "SD1_DAT0/eMMC1_DAT0")),
1097 MA35_PIN(147, PJ9, 0xcc, 0x4,1158 MA35_PIN(153, PJ9, 0xcc, 0x4,
1098 MA35_MUX(0x0, "GPJ9"),1159 MA35_MUX(0x0, "GPJ9"),
1099 MA35_MUX(0x4, "I2C4_SCL"),1160 MA35_MUX(0x4, "I2C4_SCL"),
1100 MA35_MUX(0x6, "SD1_DAT1/eMMC1_DAT1")),1161 MA35_MUX(0x6, "SD1_DAT1/eMMC1_DAT1")),
1101 MA35_PIN(148, PJ10, 0xcc, 0x8,1162 MA35_PIN(154, PJ10, 0xcc, 0x8,
1102 MA35_MUX(0x0, "GPJ10"),1163 MA35_MUX(0x0, "GPJ10"),
1103 MA35_MUX(0x3, "CAN0_RXD"),1164 MA35_MUX(0x3, "CAN0_RXD"),
1165 MA35_MUX(0x4, "USBHL1_DM"),
1104 MA35_MUX(0x6, "SD1_DAT2/eMMC1_DAT2")),1166 MA35_MUX(0x6, "SD1_DAT2/eMMC1_DAT2")),
1105 MA35_PIN(149, PJ11, 0xcc, 0xc,1167 MA35_PIN(155, PJ11, 0xcc, 0xc,
1106 MA35_MUX(0x0, "GPJ11"),1168 MA35_MUX(0x0, "GPJ11"),
1107 MA35_MUX(0x3, "CAN0_TXD"),1169 MA35_MUX(0x3, "CAN0_TXD"),
1170 MA35_MUX(0x4, "USBHL1_DP"),
1108 MA35_MUX(0x6, "SD1_DAT3/eMMC1_DAT3")),1171 MA35_MUX(0x6, "SD1_DAT3/eMMC1_DAT3")),
1109 MA35_PIN(150, PJ12, 0xcc, 0x10,1172 MA35_PIN(156, PJ12, 0xcc, 0x10,
1110 MA35_MUX(0x0, "GPJ12"),1173 MA35_MUX(0x0, "GPJ12"),
1111 MA35_MUX(0x1, "EPWM1_CH2"),1174 MA35_MUX(0x1, "EPWM1_CH2"),
1112 MA35_MUX(0x2, "UART2_nCTS"),1175 MA35_MUX(0x2, "UART2_nCTS"),
@@ -1117,7 +1180,7 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { · 4 unmodified lines
1117 MA35_MUX(0x8, "EBI_ADR12"),1180 MA35_MUX(0x8, "EBI_ADR12"),
1118 MA35_MUX(0xb, "TM2"),1181 MA35_MUX(0xb, "TM2"),
1119 MA35_MUX(0xc, "QEI0_INDEX")),1182 MA35_MUX(0xc, "QEI0_INDEX")),
1120 MA35_PIN(151, PJ13, 0xcc, 0x14,1183 MA35_PIN(157, PJ13, 0xcc, 0x14,
1121 MA35_MUX(0x0, "GPJ13"),1184 MA35_MUX(0x0, "GPJ13"),
1122 MA35_MUX(0x1, "EPWM1_CH3"),1185 MA35_MUX(0x1, "EPWM1_CH3"),
1123 MA35_MUX(0x2, "UART2_nRTS"),1186 MA35_MUX(0x2, "UART2_nRTS"),
@@ -1127,27 +1190,29 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { · 3 unmodified lines
1127 MA35_MUX(0x7, "SC1_DAT"),1190 MA35_MUX(0x7, "SC1_DAT"),
1128 MA35_MUX(0x8, "EBI_ADR13"),1191 MA35_MUX(0x8, "EBI_ADR13"),
1129 MA35_MUX(0xb, "TM2_EXT")),1192 MA35_MUX(0xb, "TM2_EXT")),
1130 MA35_PIN(152, PJ14, 0xcc, 0x18,1193 MA35_PIN(158, PJ14, 0xcc, 0x18,
1131 MA35_MUX(0x0, "GPJ14"),1194 MA35_MUX(0x0, "GPJ14"),
1132 MA35_MUX(0x1, "EPWM1_CH4"),1195 MA35_MUX(0x1, "EPWM1_CH4"),
1133 MA35_MUX(0x2, "UART2_RXD"),1196 MA35_MUX(0x2, "UART2_RXD"),
1134 MA35_MUX(0x3, "CAN3_RXD"),1197 MA35_MUX(0x3, "CAN3_RXD"),
1198 MA35_MUX(0x4, "USBHL5_DM"),
1135 MA35_MUX(0x5, "SPI3_MISO"),1199 MA35_MUX(0x5, "SPI3_MISO"),
1136 MA35_MUX(0x7, "SC1_RST"),1200 MA35_MUX(0x7, "SC1_RST"),
1137 MA35_MUX(0x8, "EBI_ADR14"),1201 MA35_MUX(0x8, "EBI_ADR14"),
1138 MA35_MUX(0xb, "TM3")),1202 MA35_MUX(0xb, "TM3")),
1139 MA35_PIN(153, PJ15, 0xcc, 0x1c,1203 MA35_PIN(159, PJ15, 0xcc, 0x1c,
1140 MA35_MUX(0x0, "GPJ15"),1204 MA35_MUX(0x0, "GPJ15"),
1141 MA35_MUX(0x1, "EPWM1_CH5"),1205 MA35_MUX(0x1, "EPWM1_CH5"),
1142 MA35_MUX(0x2, "UART2_TXD"),1206 MA35_MUX(0x2, "UART2_TXD"),
1143 MA35_MUX(0x3, "CAN3_TXD"),1207 MA35_MUX(0x3, "CAN3_TXD"),
1208 MA35_MUX(0x4, "USBHL5_DP"),
1144 MA35_MUX(0x5, "SPI3_CLK"),1209 MA35_MUX(0x5, "SPI3_CLK"),
1145 MA35_MUX(0x6, "EADC0_ST"),1210 MA35_MUX(0x6, "EADC0_ST"),
1146 MA35_MUX(0x7, "SC1_PWR"),1211 MA35_MUX(0x7, "SC1_PWR"),
1147 MA35_MUX(0x8, "EBI_ADR15"),1212 MA35_MUX(0x8, "EBI_ADR15"),
1148 MA35_MUX(0xb, "TM3_EXT"),1213 MA35_MUX(0xb, "TM3_EXT"),
1149 MA35_MUX(0xd, "INT1")),1214 MA35_MUX(0xd, "INT1")),
1150 MA35_PIN(154, PK0, 0xd0, 0x0,1215 MA35_PIN(160, PK0, 0xd0, 0x0,
1151 MA35_MUX(0x0, "GPK0"),1216 MA35_MUX(0x0, "GPK0"),
1152 MA35_MUX(0x1, "EPWM0_SYNC_IN"),1217 MA35_MUX(0x1, "EPWM0_SYNC_IN"),
1153 MA35_MUX(0x2, "UART16_nCTS"),1218 MA35_MUX(0x2, "UART16_nCTS"),
@@ -1157,7 +1222,7 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { · 3 unmodified lines
1157 MA35_MUX(0x8, "EBI_ADR8"),1222 MA35_MUX(0x8, "EBI_ADR8"),
1158 MA35_MUX(0xb, "TM7"),1223 MA35_MUX(0xb, "TM7"),
1159 MA35_MUX(0xc, "ECAP0_IC1")),1224 MA35_MUX(0xc, "ECAP0_IC1")),
1160 MA35_PIN(155, PK1, 0xd0, 0x4,1225 MA35_PIN(161, PK1, 0xd0, 0x4,
1161 MA35_MUX(0x0, "GPK1"),1226 MA35_MUX(0x0, "GPK1"),
1162 MA35_MUX(0x1, "EPWM0_SYNC_OUT"),1227 MA35_MUX(0x1, "EPWM0_SYNC_OUT"),
1163 MA35_MUX(0x2, "UART16_nRTS"),1228 MA35_MUX(0x2, "UART16_nRTS"),
@@ -1167,25 +1232,27 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { · 3 unmodified lines
1167 MA35_MUX(0x8, "EBI_ADR9"),1232 MA35_MUX(0x8, "EBI_ADR9"),
1168 MA35_MUX(0xb, "TM7_EXT"),1233 MA35_MUX(0xb, "TM7_EXT"),
1169 MA35_MUX(0xc, "ECAP0_IC2")),1234 MA35_MUX(0xc, "ECAP0_IC2")),
1170 MA35_PIN(156, PK2, 0xd0, 0x8,1235 MA35_PIN(162, PK2, 0xd0, 0x8,
1171 MA35_MUX(0x0, "GPK2"),1236 MA35_MUX(0x0, "GPK2"),
1172 MA35_MUX(0x1, "EPWM1_CH0"),1237 MA35_MUX(0x1, "EPWM1_CH0"),
1173 MA35_MUX(0x2, "UART16_RXD"),1238 MA35_MUX(0x2, "UART16_RXD"),
1174 MA35_MUX(0x3, "CAN2_RXD"),1239 MA35_MUX(0x3, "CAN2_RXD"),
1240 MA35_MUX(0x4, "USBHL4_DM"),
1175 MA35_MUX(0x5, "SPI3_I2SMCLK"),1241 MA35_MUX(0x5, "SPI3_I2SMCLK"),
1176 MA35_MUX(0x7, "SC0_PWR"),1242 MA35_MUX(0x7, "SC0_PWR"),
1177 MA35_MUX(0x8, "EBI_ADR10"),1243 MA35_MUX(0x8, "EBI_ADR10"),
1178 MA35_MUX(0xc, "QEI0_A")),1244 MA35_MUX(0xc, "QEI0_A")),
1179 MA35_PIN(157, PK3, 0xd0, 0xc,1245 MA35_PIN(163, PK3, 0xd0, 0xc,
1180 MA35_MUX(0x0, "GPK3"),1246 MA35_MUX(0x0, "GPK3"),
1181 MA35_MUX(0x1, "EPWM1_CH1"),1247 MA35_MUX(0x1, "EPWM1_CH1"),
1182 MA35_MUX(0x2, "UART16_TXD"),1248 MA35_MUX(0x2, "UART16_TXD"),
1183 MA35_MUX(0x3, "CAN2_TXD"),1249 MA35_MUX(0x3, "CAN2_TXD"),
1250 MA35_MUX(0x4, "USBHL4_DP"),
1184 MA35_MUX(0x5, "SPI3_SS1"),1251 MA35_MUX(0x5, "SPI3_SS1"),
1185 MA35_MUX(0x7, "SC1_nCD"),1252 MA35_MUX(0x7, "SC1_nCD"),
1186 MA35_MUX(0x8, "EBI_ADR11"),1253 MA35_MUX(0x8, "EBI_ADR11"),
1187 MA35_MUX(0xc, "QEI0_B")),1254 MA35_MUX(0xc, "QEI0_B")),
1188 MA35_PIN(158, PK4, 0xd0, 0x10,1255 MA35_PIN(164, PK4, 0xd0, 0x10,
1189 MA35_MUX(0x0, "GPK4"),1256 MA35_MUX(0x0, "GPK4"),
1190 MA35_MUX(0x2, "UART12_nCTS"),1257 MA35_MUX(0x2, "UART12_nCTS"),
1191 MA35_MUX(0x3, "UART13_RXD"),1258 MA35_MUX(0x3, "UART13_RXD"),
@@ -1193,7 +1260,7 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { · 1 unmodified line
1193 MA35_MUX(0x6, "LCM_DEN"),1260 MA35_MUX(0x6, "LCM_DEN"),
1194 MA35_MUX(0xc, "EBI_AD10"),1261 MA35_MUX(0xc, "EBI_AD10"),
1195 MA35_MUX(0xd, "EBI_nWRL")),1262 MA35_MUX(0xd, "EBI_nWRL")),
1196 MA35_PIN(159, PK5, 0xd0, 0x14,1263 MA35_PIN(165, PK5, 0xd0, 0x14,
1197 MA35_MUX(0x0, "GPK5"),1264 MA35_MUX(0x0, "GPK5"),
1198 MA35_MUX(0x1, "EPWM1_CH1"),1265 MA35_MUX(0x1, "EPWM1_CH1"),
1199 MA35_MUX(0x2, "UART12_nRTS"),1266 MA35_MUX(0x2, "UART12_nRTS"),
@@ -1205,28 +1272,30 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { · 5 unmodified lines
1205 MA35_MUX(0x9, "EADC0_ST"),1272 MA35_MUX(0x9, "EADC0_ST"),
1206 MA35_MUX(0xb, "TM8_EXT"),1273 MA35_MUX(0xb, "TM8_EXT"),
1207 MA35_MUX(0xd, "INT1")),1274 MA35_MUX(0xd, "INT1")),
1208 MA35_PIN(160, PK6, 0xd0, 0x18,1275 MA35_PIN(166, PK6, 0xd0, 0x18,
1209 MA35_MUX(0x0, "GPK6"),1276 MA35_MUX(0x0, "GPK6"),
1210 MA35_MUX(0x1, "EPWM1_CH2"),1277 MA35_MUX(0x1, "EPWM1_CH2"),
1211 MA35_MUX(0x2, "UART12_RXD"),1278 MA35_MUX(0x2, "UART12_RXD"),
1212 MA35_MUX(0x3, "CAN0_RXD"),1279 MA35_MUX(0x3, "CAN0_RXD"),
1280 MA35_MUX(0x4, "USBHL4_DM"),
1213 MA35_MUX(0x5, "SPI2_MOSI"),1281 MA35_MUX(0x5, "SPI2_MOSI"),
1214 MA35_MUX(0x7, "I2S1_BCLK"),1282 MA35_MUX(0x7, "I2S1_BCLK"),
1215 MA35_MUX(0x8, "SC0_RST"),1283 MA35_MUX(0x8, "SC0_RST"),
1216 MA35_MUX(0xb, "TM6"),1284 MA35_MUX(0xb, "TM6"),
1217 MA35_MUX(0xd, "INT2")),1285 MA35_MUX(0xd, "INT2")),
1218 MA35_PIN(161, PK7, 0xd0, 0x1c,1286 MA35_PIN(167, PK7, 0xd0, 0x1c,
1219 MA35_MUX(0x0, "GPK7"),1287 MA35_MUX(0x0, "GPK7"),
1220 MA35_MUX(0x1, "EPWM1_CH3"),1288 MA35_MUX(0x1, "EPWM1_CH3"),
1221 MA35_MUX(0x2, "UART12_TXD"),1289 MA35_MUX(0x2, "UART12_TXD"),
1222 MA35_MUX(0x3, "CAN0_TXD"),1290 MA35_MUX(0x3, "CAN0_TXD"),
1291 MA35_MUX(0x4, "USBHL4_DP"),
1223 MA35_MUX(0x5, "SPI2_MISO"),1292 MA35_MUX(0x5, "SPI2_MISO"),
1224 MA35_MUX(0x7, "I2S1_LRCK"),1293 MA35_MUX(0x7, "I2S1_LRCK"),
1225 MA35_MUX(0x8, "SC0_PWR"),1294 MA35_MUX(0x8, "SC0_PWR"),
1226 MA35_MUX(0x9, "CLKO"),1295 MA35_MUX(0x9, "CLKO"),
1227 MA35_MUX(0xb, "TM6_EXT"),1296 MA35_MUX(0xb, "TM6_EXT"),
1228 MA35_MUX(0xd, "INT3")),1297 MA35_MUX(0xd, "INT3")),
1229 MA35_PIN(162, PK8, 0xd4, 0x0,1298 MA35_PIN(168, PK8, 0xd4, 0x0,
1230 MA35_MUX(0x0, "GPK8"),1299 MA35_MUX(0x0, "GPK8"),
1231 MA35_MUX(0x1, "EPWM1_CH0"),1300 MA35_MUX(0x1, "EPWM1_CH0"),
1232 MA35_MUX(0x4, "I2C3_SDA"),1301 MA35_MUX(0x4, "I2C3_SDA"),
@@ -1237,25 +1306,27 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { · 4 unmodified lines
1237 MA35_MUX(0xa, "EBI_ADR15"),1306 MA35_MUX(0xa, "EBI_ADR15"),
1238 MA35_MUX(0xb, "TM8"),1307 MA35_MUX(0xb, "TM8"),
1239 MA35_MUX(0xc, "QEI1_INDEX")),1308 MA35_MUX(0xc, "QEI1_INDEX")),
1240 MA35_PIN(163, PK9, 0xd4, 0x4,1309 MA35_PIN(169, PK9, 0xd4, 0x4,
1241 MA35_MUX(0x0, "GPK9"),1310 MA35_MUX(0x0, "GPK9"),
1242 MA35_MUX(0x4, "I2C3_SCL"),1311 MA35_MUX(0x4, "I2C3_SCL"),
1243 MA35_MUX(0x6, "CCAP0_SCLK"),1312 MA35_MUX(0x6, "CCAP0_SCLK"),
1244 MA35_MUX(0x8, "EBI_AD0"),1313 MA35_MUX(0x8, "EBI_AD0"),
1245 MA35_MUX(0xa, "EBI_ADR0")),1314 MA35_MUX(0xa, "EBI_ADR0")),
1246 MA35_PIN(164, PK10, 0xd4, 0x8,1315 MA35_PIN(170, PK10, 0xd4, 0x8,
1247 MA35_MUX(0x0, "GPK10"),1316 MA35_MUX(0x0, "GPK10"),
1248 MA35_MUX(0x3, "CAN1_RXD"),1317 MA35_MUX(0x3, "CAN1_RXD"),
1318 MA35_MUX(0x4, "USBHL3_DM"),
1249 MA35_MUX(0x6, "CCAP0_PIXCLK"),1319 MA35_MUX(0x6, "CCAP0_PIXCLK"),
1250 MA35_MUX(0x8, "EBI_AD1"),1320 MA35_MUX(0x8, "EBI_AD1"),
1251 MA35_MUX(0xa, "EBI_ADR1")),1321 MA35_MUX(0xa, "EBI_ADR1")),
1252 MA35_PIN(165, PK11, 0xd4, 0xc,1322 MA35_PIN(171, PK11, 0xd4, 0xc,
1253 MA35_MUX(0x0, "GPK11"),1323 MA35_MUX(0x0, "GPK11"),
1254 MA35_MUX(0x3, "CAN1_TXD"),1324 MA35_MUX(0x3, "CAN1_TXD"),
1325 MA35_MUX(0x4, "USBHL3_DP"),
1255 MA35_MUX(0x6, "CCAP0_HSYNC"),1326 MA35_MUX(0x6, "CCAP0_HSYNC"),
1256 MA35_MUX(0x8, "EBI_AD2"),1327 MA35_MUX(0x8, "EBI_AD2"),
1257 MA35_MUX(0xa, "EBI_ADR2")),1328 MA35_MUX(0xa, "EBI_ADR2")),
1258 MA35_PIN(166, PK12, 0xd4, 0x10,1329 MA35_PIN(172, PK12, 0xd4, 0x10,
1259 MA35_MUX(0x0, "GPK12"),1330 MA35_MUX(0x0, "GPK12"),
1260 MA35_MUX(0x1, "EPWM2_CH0"),1331 MA35_MUX(0x1, "EPWM2_CH0"),
1261 MA35_MUX(0x2, "UART1_nCTS"),1332 MA35_MUX(0x2, "UART1_nCTS"),
@@ -1266,7 +1337,7 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { · 4 unmodified lines
1266 MA35_MUX(0x8, "SC0_CLK"),1337 MA35_MUX(0x8, "SC0_CLK"),
1267 MA35_MUX(0xb, "TM10"),1338 MA35_MUX(0xb, "TM10"),
1268 MA35_MUX(0xd, "INT2")),1339 MA35_MUX(0xd, "INT2")),
1269 MA35_PIN(167, PK13, 0xd4, 0x14,1340 MA35_PIN(173, PK13, 0xd4, 0x14,
1270 MA35_MUX(0x0, "GPK13"),1341 MA35_MUX(0x0, "GPK13"),
1271 MA35_MUX(0x1, "EPWM2_CH1"),1342 MA35_MUX(0x1, "EPWM2_CH1"),
1272 MA35_MUX(0x2, "UART1_nRTS"),1343 MA35_MUX(0x2, "UART1_nRTS"),
@@ -1276,28 +1347,30 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { · 3 unmodified lines
1276 MA35_MUX(0x6, "SPI1_CLK"),1347 MA35_MUX(0x6, "SPI1_CLK"),
1277 MA35_MUX(0x8, "SC0_DAT"),1348 MA35_MUX(0x8, "SC0_DAT"),
1278 MA35_MUX(0xb, "TM10_EXT")),1349 MA35_MUX(0xb, "TM10_EXT")),
1279 MA35_PIN(168, PK14, 0xd4, 0x18,1350 MA35_PIN(174, PK14, 0xd4, 0x18,
1280 MA35_MUX(0x0, "GPK14"),1351 MA35_MUX(0x0, "GPK14"),
1281 MA35_MUX(0x1, "EPWM2_CH2"),1352 MA35_MUX(0x1, "EPWM2_CH2"),
1282 MA35_MUX(0x2, "UART1_RXD"),1353 MA35_MUX(0x2, "UART1_RXD"),
1283 MA35_MUX(0x3, "CAN3_RXD"),1354 MA35_MUX(0x3, "CAN3_RXD"),
1355 MA35_MUX(0x4, "USBHL4_DM"),
1284 MA35_MUX(0x5, "I2S0_DI"),1356 MA35_MUX(0x5, "I2S0_DI"),
1285 MA35_MUX(0x6, "SPI1_MOSI"),1357 MA35_MUX(0x6, "SPI1_MOSI"),
1286 MA35_MUX(0x8, "SC0_RST"),1358 MA35_MUX(0x8, "SC0_RST"),
1287 MA35_MUX(0xa, "I2C5_SDA"),1359 MA35_MUX(0xa, "I2C5_SDA"),
1288 MA35_MUX(0xb, "TM11"),1360 MA35_MUX(0xb, "TM11"),
1289 MA35_MUX(0xd, "INT3")),1361 MA35_MUX(0xd, "INT3")),
1290 MA35_PIN(169, PK15, 0xd4, 0x1c,1362 MA35_PIN(175, PK15, 0xd4, 0x1c,
1291 MA35_MUX(0x0, "GPK15"),1363 MA35_MUX(0x0, "GPK15"),
1292 MA35_MUX(0x1, "EPWM2_CH3"),1364 MA35_MUX(0x1, "EPWM2_CH3"),
1293 MA35_MUX(0x2, "UART1_TXD"),1365 MA35_MUX(0x2, "UART1_TXD"),
1294 MA35_MUX(0x3, "CAN3_TXD"),1366 MA35_MUX(0x3, "CAN3_TXD"),
1367 MA35_MUX(0x4, "USBHL4_DP"),
1295 MA35_MUX(0x5, "I2S0_DO"),1368 MA35_MUX(0x5, "I2S0_DO"),
1296 MA35_MUX(0x6, "SPI1_MISO"),1369 MA35_MUX(0x6, "SPI1_MISO"),
1297 MA35_MUX(0x8, "SC0_PWR"),1370 MA35_MUX(0x8, "SC0_PWR"),
1298 MA35_MUX(0xa, "I2C5_SCL"),1371 MA35_MUX(0xa, "I2C5_SCL"),
1299 MA35_MUX(0xb, "TM11_EXT")),1372 MA35_MUX(0xb, "TM11_EXT")),
1300 MA35_PIN(170, PL0, 0xd8, 0x0,1373 MA35_PIN(176, PL0, 0xd8, 0x0,
1301 MA35_MUX(0x0, "GPL0"),1374 MA35_MUX(0x0, "GPL0"),
1302 MA35_MUX(0x1, "EPWM1_CH0"),1375 MA35_MUX(0x1, "EPWM1_CH0"),
1303 MA35_MUX(0x2, "UART11_nCTS"),1376 MA35_MUX(0x2, "UART11_nCTS"),
@@ -1310,7 +1383,7 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { · 6 unmodified lines
1310 MA35_MUX(0x9, "SC1_CLK"),1383 MA35_MUX(0x9, "SC1_CLK"),
1311 MA35_MUX(0xb, "TM5"),1384 MA35_MUX(0xb, "TM5"),
1312 MA35_MUX(0xc, "QEI1_A")),1385 MA35_MUX(0xc, "QEI1_A")),
1313 MA35_PIN(171, PL1, 0xd8, 0x4,1386 MA35_PIN(177, PL1, 0xd8, 0x4,
1314 MA35_MUX(0x0, "GPL1"),1387 MA35_MUX(0x0, "GPL1"),
1315 MA35_MUX(0x1, "EPWM1_CH1"),1388 MA35_MUX(0x1, "EPWM1_CH1"),
1316 MA35_MUX(0x2, "UART11_nRTS"),1389 MA35_MUX(0x2, "UART11_nRTS"),
@@ -1323,11 +1396,12 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { · 6 unmodified lines
1323 MA35_MUX(0x9, "SC1_DAT"),1396 MA35_MUX(0x9, "SC1_DAT"),
1324 MA35_MUX(0xb, "TM5_EXT"),1397 MA35_MUX(0xb, "TM5_EXT"),
1325 MA35_MUX(0xc, "QEI1_B")),1398 MA35_MUX(0xc, "QEI1_B")),
1326 MA35_PIN(172, PL2, 0xd8, 0x8,1399 MA35_PIN(178, PL2, 0xd8, 0x8,
1327 MA35_MUX(0x0, "GPL2"),1400 MA35_MUX(0x0, "GPL2"),
1328 MA35_MUX(0x1, "EPWM1_CH2"),1401 MA35_MUX(0x1, "EPWM1_CH2"),
1329 MA35_MUX(0x2, "UART11_RXD"),1402 MA35_MUX(0x2, "UART11_RXD"),
1330 MA35_MUX(0x3, "CAN3_RXD"),1403 MA35_MUX(0x3, "CAN3_RXD"),
1404 MA35_MUX(0x4, "USBHL4_DM"),
1331 MA35_MUX(0x5, "SPI2_SS0"),1405 MA35_MUX(0x5, "SPI2_SS0"),
1332 MA35_MUX(0x6, "QSPI1_SS1"),1406 MA35_MUX(0x6, "QSPI1_SS1"),
1333 MA35_MUX(0x7, "I2S0_DI"),1407 MA35_MUX(0x7, "I2S0_DI"),
@@ -1335,11 +1409,12 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { · 1 unmodified line
1335 MA35_MUX(0x9, "SC1_RST"),1409 MA35_MUX(0x9, "SC1_RST"),
1336 MA35_MUX(0xb, "TM7"),1410 MA35_MUX(0xb, "TM7"),
1337 MA35_MUX(0xc, "QEI1_INDEX")),1411 MA35_MUX(0xc, "QEI1_INDEX")),
1338 MA35_PIN(173, PL3, 0xd8, 0xc,1412 MA35_PIN(179, PL3, 0xd8, 0xc,
1339 MA35_MUX(0x0, "GPL3"),1413 MA35_MUX(0x0, "GPL3"),
1340 MA35_MUX(0x1, "EPWM1_CH3"),1414 MA35_MUX(0x1, "EPWM1_CH3"),
1341 MA35_MUX(0x2, "UART11_TXD"),1415 MA35_MUX(0x2, "UART11_TXD"),
1342 MA35_MUX(0x3, "CAN3_TXD"),1416 MA35_MUX(0x3, "CAN3_TXD"),
1417 MA35_MUX(0x4, "USBHL4_DP"),
1343 MA35_MUX(0x5, "SPI2_CLK"),1418 MA35_MUX(0x5, "SPI2_CLK"),
1344 MA35_MUX(0x6, "QSPI1_CLK"),1419 MA35_MUX(0x6, "QSPI1_CLK"),
1345 MA35_MUX(0x7, "I2S0_DO"),1420 MA35_MUX(0x7, "I2S0_DO"),
@@ -1347,7 +1422,7 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { · 1 unmodified line
1347 MA35_MUX(0x9, "SC1_PWR"),1422 MA35_MUX(0x9, "SC1_PWR"),
1348 MA35_MUX(0xb, "TM7_EXT"),1423 MA35_MUX(0xb, "TM7_EXT"),
1349 MA35_MUX(0xc, "ECAP0_IC0")),1424 MA35_MUX(0xc, "ECAP0_IC0")),
1350 MA35_PIN(174, PL4, 0xd8, 0x10,1425 MA35_PIN(180, PL4, 0xd8, 0x10,
1351 MA35_MUX(0x0, "GPL4"),1426 MA35_MUX(0x0, "GPL4"),
1352 MA35_MUX(0x1, "EPWM1_CH4"),1427 MA35_MUX(0x1, "EPWM1_CH4"),
1353 MA35_MUX(0x2, "UART2_nCTS"),1428 MA35_MUX(0x2, "UART2_nCTS"),
@@ -1360,7 +1435,7 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { · 6 unmodified lines
1360 MA35_MUX(0x9, "SC1_nCD"),1435 MA35_MUX(0x9, "SC1_nCD"),
1361 MA35_MUX(0xb, "TM9"),1436 MA35_MUX(0xb, "TM9"),
1362 MA35_MUX(0xc, "ECAP0_IC1")),1437 MA35_MUX(0xc, "ECAP0_IC1")),
1363 MA35_PIN(175, PL5, 0xd8, 0x14,1438 MA35_PIN(181, PL5, 0xd8, 0x14,
1364 MA35_MUX(0x0, "GPL5"),1439 MA35_MUX(0x0, "GPL5"),
1365 MA35_MUX(0x1, "EPWM1_CH5"),1440 MA35_MUX(0x1, "EPWM1_CH5"),
1366 MA35_MUX(0x2, "UART2_nRTS"),1441 MA35_MUX(0x2, "UART2_nRTS"),
@@ -1373,28 +1448,30 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { · 6 unmodified lines
1373 MA35_MUX(0x9, "SC0_nCD"),1448 MA35_MUX(0x9, "SC0_nCD"),
1374 MA35_MUX(0xb, "TM9_EXT"),1449 MA35_MUX(0xb, "TM9_EXT"),
1375 MA35_MUX(0xc, "ECAP0_IC2")),1450 MA35_MUX(0xc, "ECAP0_IC2")),
1376 MA35_PIN(176, PL6, 0xd8, 0x18,1451 MA35_PIN(182, PL6, 0xd8, 0x18,
1377 MA35_MUX(0x0, "GPL6"),1452 MA35_MUX(0x0, "GPL6"),
1378 MA35_MUX(0x1, "EPWM0_CH0"),1453 MA35_MUX(0x1, "EPWM0_CH0"),
1379 MA35_MUX(0x2, "UART2_RXD"),1454 MA35_MUX(0x2, "UART2_RXD"),
1380 MA35_MUX(0x3, "CAN0_RXD"),1455 MA35_MUX(0x3, "CAN0_RXD"),
1456 MA35_MUX(0x4, "USBHL5_DM"),
1381 MA35_MUX(0x6, "QSPI1_MOSI1"),1457 MA35_MUX(0x6, "QSPI1_MOSI1"),
1382 MA35_MUX(0x7, "TRACE_CLK"),1458 MA35_MUX(0x7, "TRACE_CLK"),
1383 MA35_MUX(0x8, "EBI_AD5"),1459 MA35_MUX(0x8, "EBI_AD5"),
1384 MA35_MUX(0xb, "TM3"),1460 MA35_MUX(0xb, "TM3"),
1385 MA35_MUX(0xc, "ECAP1_IC0"),1461 MA35_MUX(0xc, "ECAP1_IC0"),
1386 MA35_MUX(0xd, "INT0")),1462 MA35_MUX(0xd, "INT0")),
1387 MA35_PIN(177, PL7, 0xd8, 0x1c,1463 MA35_PIN(183, PL7, 0xd8, 0x1c,
1388 MA35_MUX(0x0, "GPL7"),1464 MA35_MUX(0x0, "GPL7"),
1389 MA35_MUX(0x1, "EPWM0_CH1"),1465 MA35_MUX(0x1, "EPWM0_CH1"),
1390 MA35_MUX(0x2, "UART2_TXD"),1466 MA35_MUX(0x2, "UART2_TXD"),
1391 MA35_MUX(0x3, "CAN0_TXD"),1467 MA35_MUX(0x3, "CAN0_TXD"),
1468 MA35_MUX(0x4, "USBHL5_DP"),
1392 MA35_MUX(0x6, "QSPI1_MISO1"),1469 MA35_MUX(0x6, "QSPI1_MISO1"),
1393 MA35_MUX(0x8, "EBI_AD6"),1470 MA35_MUX(0x8, "EBI_AD6"),
1394 MA35_MUX(0xb, "TM3_EXT"),1471 MA35_MUX(0xb, "TM3_EXT"),
1395 MA35_MUX(0xc, "ECAP1_IC1"),1472 MA35_MUX(0xc, "ECAP1_IC1"),
1396 MA35_MUX(0xd, "INT1")),1473 MA35_MUX(0xd, "INT1")),
1397 MA35_PIN(178, PL8, 0xdc, 0x0,1474 MA35_PIN(184, PL8, 0xdc, 0x0,
1398 MA35_MUX(0x0, "GPL8"),1475 MA35_MUX(0x0, "GPL8"),
1399 MA35_MUX(0x1, "EPWM0_CH2"),1476 MA35_MUX(0x1, "EPWM0_CH2"),
1400 MA35_MUX(0x2, "UART14_nCTS"),1477 MA35_MUX(0x2, "UART14_nCTS"),
@@ -1408,7 +1485,7 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { · 7 unmodified lines
1408 MA35_MUX(0xb, "TM4"),1485 MA35_MUX(0xb, "TM4"),
1409 MA35_MUX(0xc, "ECAP1_IC2"),1486 MA35_MUX(0xc, "ECAP1_IC2"),
1410 MA35_MUX(0xd, "INT2")),1487 MA35_MUX(0xd, "INT2")),
1411 MA35_PIN(179, PL9, 0xdc, 0x4,1488 MA35_PIN(185, PL9, 0xdc, 0x4,
1412 MA35_MUX(0x0, "GPL9"),1489 MA35_MUX(0x0, "GPL9"),
1413 MA35_MUX(0x1, "EPWM0_CH3"),1490 MA35_MUX(0x1, "EPWM0_CH3"),
1414 MA35_MUX(0x2, "UART14_nRTS"),1491 MA35_MUX(0x2, "UART14_nRTS"),
@@ -1422,11 +1499,12 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { · 7 unmodified lines
1422 MA35_MUX(0xb, "TM4_EXT"),1499 MA35_MUX(0xb, "TM4_EXT"),
1423 MA35_MUX(0xc, "QEI0_A"),1500 MA35_MUX(0xc, "QEI0_A"),
1424 MA35_MUX(0xd, "INT3")),1501 MA35_MUX(0xd, "INT3")),
1425 MA35_PIN(180, PL10, 0xdc, 0x8,1502 MA35_PIN(186, PL10, 0xdc, 0x8,
1426 MA35_MUX(0x0, "GPL10"),1503 MA35_MUX(0x0, "GPL10"),
1427 MA35_MUX(0x1, "EPWM0_CH4"),1504 MA35_MUX(0x1, "EPWM0_CH4"),
1428 MA35_MUX(0x2, "UART14_RXD"),1505 MA35_MUX(0x2, "UART14_RXD"),
1429 MA35_MUX(0x3, "CAN3_RXD"),1506 MA35_MUX(0x3, "CAN3_RXD"),
1507 MA35_MUX(0x4, "USBHL2_DM"),
1430 MA35_MUX(0x5, "SPI3_MOSI"),1508 MA35_MUX(0x5, "SPI3_MOSI"),
1431 MA35_MUX(0x6, "EPWM0_CH5"),1509 MA35_MUX(0x6, "EPWM0_CH5"),
1432 MA35_MUX(0x7, "I2S1_DI"),1510 MA35_MUX(0x7, "I2S1_DI"),
@@ -1434,11 +1512,12 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { · 1 unmodified line
1434 MA35_MUX(0x9, "SC0_RST"),1512 MA35_MUX(0x9, "SC0_RST"),
1435 MA35_MUX(0xb, "EBI_nWRH"),1513 MA35_MUX(0xb, "EBI_nWRH"),
1436 MA35_MUX(0xc, "QEI0_B")),1514 MA35_MUX(0xc, "QEI0_B")),
1437 MA35_PIN(181, PL11, 0xdc, 0xc,1515 MA35_PIN(187, PL11, 0xdc, 0xc,
1438 MA35_MUX(0x0, "GPL11"),1516 MA35_MUX(0x0, "GPL11"),
1439 MA35_MUX(0x1, "EPWM0_CH5"),1517 MA35_MUX(0x1, "EPWM0_CH5"),
1440 MA35_MUX(0x2, "UART14_TXD"),1518 MA35_MUX(0x2, "UART14_TXD"),
1441 MA35_MUX(0x3, "CAN3_TXD"),1519 MA35_MUX(0x3, "CAN3_TXD"),
1520 MA35_MUX(0x4, "USBHL2_DP"),
1442 MA35_MUX(0x5, "SPI3_MISO"),1521 MA35_MUX(0x5, "SPI3_MISO"),
1443 MA35_MUX(0x6, "EPWM1_CH5"),1522 MA35_MUX(0x6, "EPWM1_CH5"),
1444 MA35_MUX(0x7, "I2S1_DO"),1523 MA35_MUX(0x7, "I2S1_DO"),
@@ -1446,7 +1525,7 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { · 1 unmodified line
1446 MA35_MUX(0x9, "SC0_PWR"),1525 MA35_MUX(0x9, "SC0_PWR"),
1447 MA35_MUX(0xb, "EBI_nWRL"),1526 MA35_MUX(0xb, "EBI_nWRL"),
1448 MA35_MUX(0xc, "QEI0_INDEX")),1527 MA35_MUX(0xc, "QEI0_INDEX")),
1449 MA35_PIN(182, PL12, 0xdc, 0x10,1528 MA35_PIN(188, PL12, 0xdc, 0x10,
1450 MA35_MUX(0x0, "GPL12"),1529 MA35_MUX(0x0, "GPL12"),
1451 MA35_MUX(0x1, "EPWM0_SYNC_IN"),1530 MA35_MUX(0x1, "EPWM0_SYNC_IN"),
1452 MA35_MUX(0x2, "UART7_nCTS"),1531 MA35_MUX(0x2, "UART7_nCTS"),
@@ -1463,7 +1542,7 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { · 10 unmodified lines
1463 MA35_MUX(0xd, "EBI_AD11"),1542 MA35_MUX(0xd, "EBI_AD11"),
1464 MA35_MUX(0xe, "RGMII0_PPS"),1543 MA35_MUX(0xe, "RGMII0_PPS"),
1465 MA35_MUX(0xf, "RMII0_PPS")),1544 MA35_MUX(0xf, "RMII0_PPS")),
1466 MA35_PIN(183, PL13, 0xdc, 0x14,1545 MA35_PIN(189, PL13, 0xdc, 0x14,
1467 MA35_MUX(0x0, "GPL13"),1546 MA35_MUX(0x0, "GPL13"),
1468 MA35_MUX(0x1, "EPWM0_SYNC_OUT"),1547 MA35_MUX(0x1, "EPWM0_SYNC_OUT"),
1469 MA35_MUX(0x2, "UART7_nRTS"),1548 MA35_MUX(0x2, "UART7_nRTS"),
@@ -1480,7 +1559,7 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { · 10 unmodified lines
1480 MA35_MUX(0xd, "EBI_AD12"),1559 MA35_MUX(0xd, "EBI_AD12"),
1481 MA35_MUX(0xe, "RGMII1_PPS"),1560 MA35_MUX(0xe, "RGMII1_PPS"),
1482 MA35_MUX(0xf, "RMII1_PPS")),1561 MA35_MUX(0xf, "RMII1_PPS")),
1483 MA35_PIN(184, PL14, 0xdc, 0x18,1562 MA35_PIN(190, PL14, 0xdc, 0x18,
1484 MA35_MUX(0x0, "GPL14"),1563 MA35_MUX(0x0, "GPL14"),
1485 MA35_MUX(0x1, "EPWM0_CH2"),1564 MA35_MUX(0x1, "EPWM0_CH2"),
1486 MA35_MUX(0x2, "UART7_RXD"),1565 MA35_MUX(0x2, "UART7_RXD"),
@@ -1492,7 +1571,7 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { · 5 unmodified lines
1492 MA35_MUX(0xb, "TM2"),1571 MA35_MUX(0xb, "TM2"),
1493 MA35_MUX(0xc, "INT0"),1572 MA35_MUX(0xc, "INT0"),
1494 MA35_MUX(0xd, "EBI_AD13")),1573 MA35_MUX(0xd, "EBI_AD13")),
1495 MA35_PIN(185, PL15, 0xdc, 0x1c,1574 MA35_PIN(191, PL15, 0xdc, 0x1c,
1496 MA35_MUX(0x0, "GPL15"),1575 MA35_MUX(0x0, "GPL15"),
1497 MA35_MUX(0x1, "EPWM0_CH1"),1576 MA35_MUX(0x1, "EPWM0_CH1"),
1498 MA35_MUX(0x2, "UART7_TXD"),1577 MA35_MUX(0x2, "UART7_TXD"),
@@ -1505,86 +1584,92 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { · 6 unmodified lines
1505 MA35_MUX(0xb, "TM2_EXT"),1584 MA35_MUX(0xb, "TM2_EXT"),
1506 MA35_MUX(0xc, "INT2"),1585 MA35_MUX(0xc, "INT2"),
1507 MA35_MUX(0xd, "EBI_AD14")),1586 MA35_MUX(0xd, "EBI_AD14")),
1508 MA35_PIN(186, PM0, 0xe0, 0x0,1587 MA35_PIN(192, PM0, 0xe0, 0x0,
1509 MA35_MUX(0x0, "GPM0"),1588 MA35_MUX(0x0, "GPM0"),
1510 MA35_MUX(0x4, "I2C4_SDA"),1589 MA35_MUX(0x4, "I2C4_SDA"),
1511 MA35_MUX(0x6, "CCAP0_VSYNC"),1590 MA35_MUX(0x6, "CCAP0_VSYNC"),
1512 MA35_MUX(0x8, "EBI_AD3"),1591 MA35_MUX(0x8, "EBI_AD3"),
1513 MA35_MUX(0xa, "EBI_ADR3")),1592 MA35_MUX(0xa, "EBI_ADR3")),
1514 MA35_PIN(187, PM1, 0xe0, 0x4,1593 MA35_PIN(193, PM1, 0xe0, 0x4,
1515 MA35_MUX(0x0, "GPM1"),1594 MA35_MUX(0x0, "GPM1"),
1516 MA35_MUX(0x4, "I2C4_SCL"),1595 MA35_MUX(0x4, "I2C4_SCL"),
1517 MA35_MUX(0x5, "SPI3_I2SMCLK"),1596 MA35_MUX(0x5, "SPI3_I2SMCLK"),
1518 MA35_MUX(0x6, "CCAP0_SFIELD"),1597 MA35_MUX(0x6, "CCAP0_SFIELD"),
1519 MA35_MUX(0x8, "EBI_AD4"),1598 MA35_MUX(0x8, "EBI_AD4"),
1520 MA35_MUX(0xa, "EBI_ADR4")),1599 MA35_MUX(0xa, "EBI_ADR4")),
1521 MA35_PIN(188, PM2, 0xe0, 0x8,1600 MA35_PIN(194, PM2, 0xe0, 0x8,
1522 MA35_MUX(0x0, "GPM2"),1601 MA35_MUX(0x0, "GPM2"),
1523 MA35_MUX(0x3, "CAN3_RXD"),1602 MA35_MUX(0x3, "CAN3_RXD"),
1603 MA35_MUX(0x4, "USBHL0_DM"),
1524 MA35_MUX(0x6, "CCAP0_DATA0"),1604 MA35_MUX(0x6, "CCAP0_DATA0"),
1525 MA35_MUX(0x8, "EBI_AD5"),1605 MA35_MUX(0x8, "EBI_AD5"),
1526 MA35_MUX(0xa, "EBI_ADR5")),1606 MA35_MUX(0xa, "EBI_ADR5")),
1527 MA35_PIN(189, PM3, 0xe0, 0xc,1607 MA35_PIN(195, PM3, 0xe0, 0xc,
1528 MA35_MUX(0x0, "GPM3"),1608 MA35_MUX(0x0, "GPM3"),
1529 MA35_MUX(0x3, "CAN3_TXD"),1609 MA35_MUX(0x3, "CAN3_TXD"),
1610 MA35_MUX(0x4, "USBHL0_DP"),
1530 MA35_MUX(0x6, "CCAP0_DATA1"),1611 MA35_MUX(0x6, "CCAP0_DATA1"),
1531 MA35_MUX(0x8, "EBI_AD6"),1612 MA35_MUX(0x8, "EBI_AD6"),
1532 MA35_MUX(0xa, "EBI_ADR6")),1613 MA35_MUX(0xa, "EBI_ADR6")),
1533 MA35_PIN(190, PM4, 0xe0, 0x10,1614 MA35_PIN(196, PM4, 0xe0, 0x10,
1534 MA35_MUX(0x0, "GPM4"),1615 MA35_MUX(0x0, "GPM4"),
1535 MA35_MUX(0x4, "I2C5_SDA"),1616 MA35_MUX(0x4, "I2C5_SDA"),
1536 MA35_MUX(0x6, "CCAP0_DATA2"),1617 MA35_MUX(0x6, "CCAP0_DATA2"),
1537 MA35_MUX(0x8, "EBI_AD7"),1618 MA35_MUX(0x8, "EBI_AD7"),
1538 MA35_MUX(0xa, "EBI_ADR7")),1619 MA35_MUX(0xa, "EBI_ADR7")),
1539 MA35_PIN(191, PM5, 0xe0, 0x14,1620 MA35_PIN(197, PM5, 0xe0, 0x14,
1540 MA35_MUX(0x0, "GPM5"),1621 MA35_MUX(0x0, "GPM5"),
1541 MA35_MUX(0x4, "I2C5_SCL"),1622 MA35_MUX(0x4, "I2C5_SCL"),
1542 MA35_MUX(0x6, "CCAP0_DATA3"),1623 MA35_MUX(0x6, "CCAP0_DATA3"),
1543 MA35_MUX(0x8, "EBI_AD8"),1624 MA35_MUX(0x8, "EBI_AD8"),
1544 MA35_MUX(0xa, "EBI_ADR8")),1625 MA35_MUX(0xa, "EBI_ADR8")),
1545 MA35_PIN(192, PM6, 0xe0, 0x18,1626 MA35_PIN(198, PM6, 0xe0, 0x18,
1546 MA35_MUX(0x0, "GPM6"),1627 MA35_MUX(0x0, "GPM6"),
1547 MA35_MUX(0x3, "CAN0_RXD"),1628 MA35_MUX(0x3, "CAN0_RXD"),
1629 MA35_MUX(0x4, "USBHL1_DM"),
1548 MA35_MUX(0x6, "CCAP0_DATA4"),1630 MA35_MUX(0x6, "CCAP0_DATA4"),
1549 MA35_MUX(0x8, "EBI_AD9"),1631 MA35_MUX(0x8, "EBI_AD9"),
1550 MA35_MUX(0xa, "EBI_ADR9")),1632 MA35_MUX(0xa, "EBI_ADR9")),
1551 MA35_PIN(193, PM7, 0xe0, 0x1c,1633 MA35_PIN(199, PM7, 0xe0, 0x1c,
1552 MA35_MUX(0x0, "GPM7"),1634 MA35_MUX(0x0, "GPM7"),
1553 MA35_MUX(0x3, "CAN0_TXD"),1635 MA35_MUX(0x3, "CAN0_TXD"),
1636 MA35_MUX(0x4, "USBHL1_DP"),
1554 MA35_MUX(0x6, "CCAP0_DATA5"),1637 MA35_MUX(0x6, "CCAP0_DATA5"),
1555 MA35_MUX(0x8, "EBI_AD10"),1638 MA35_MUX(0x8, "EBI_AD10"),
1556 MA35_MUX(0xa, "EBI_ADR10")),1639 MA35_MUX(0xa, "EBI_ADR10")),
1557 MA35_PIN(194, PM8, 0xe4, 0x0,1640 MA35_PIN(200, PM8, 0xe4, 0x0,
1558 MA35_MUX(0x0, "GPM8"),1641 MA35_MUX(0x0, "GPM8"),
1559 MA35_MUX(0x4, "I2C0_SDA"),1642 MA35_MUX(0x4, "I2C0_SDA"),
1560 MA35_MUX(0x6, "CCAP0_DATA6"),1643 MA35_MUX(0x6, "CCAP0_DATA6"),
1561 MA35_MUX(0x8, "EBI_AD11"),1644 MA35_MUX(0x8, "EBI_AD11"),
1562 MA35_MUX(0xa, "EBI_ADR11")),1645 MA35_MUX(0xa, "EBI_ADR11")),
1563 MA35_PIN(195, PM9, 0xe4, 0x4,1646 MA35_PIN(201, PM9, 0xe4, 0x4,
1564 MA35_MUX(0x0, "GPM9"),1647 MA35_MUX(0x0, "GPM9"),
1565 MA35_MUX(0x4, "I2C0_SCL"),1648 MA35_MUX(0x4, "I2C0_SCL"),
1566 MA35_MUX(0x6, "CCAP0_DATA7"),1649 MA35_MUX(0x6, "CCAP0_DATA7"),
1567 MA35_MUX(0x8, "EBI_AD12"),1650 MA35_MUX(0x8, "EBI_AD12"),
1568 MA35_MUX(0xa, "EBI_ADR12")),1651 MA35_MUX(0xa, "EBI_ADR12")),
1569 MA35_PIN(196, PM10, 0xe4, 0x8,1652 MA35_PIN(202, PM10, 0xe4, 0x8,
1570 MA35_MUX(0x0, "GPM10"),1653 MA35_MUX(0x0, "GPM10"),
1571 MA35_MUX(0x1, "EPWM1_CH2"),1654 MA35_MUX(0x1, "EPWM1_CH2"),
1572 MA35_MUX(0x3, "CAN2_RXD"),1655 MA35_MUX(0x3, "CAN2_RXD"),
1656 MA35_MUX(0x4, "USBHL4_DM"),
1573 MA35_MUX(0x5, "SPI3_SS0"),1657 MA35_MUX(0x5, "SPI3_SS0"),
1574 MA35_MUX(0x6, "CCAP0_DATA8"),1658 MA35_MUX(0x6, "CCAP0_DATA8"),
1575 MA35_MUX(0x7, "SPI2_I2SMCLK"),1659 MA35_MUX(0x7, "SPI2_I2SMCLK"),
1576 MA35_MUX(0x8, "EBI_AD13"),1660 MA35_MUX(0x8, "EBI_AD13"),
1577 MA35_MUX(0xa, "EBI_ADR13")),1661 MA35_MUX(0xa, "EBI_ADR13")),
1578 MA35_PIN(197, PM11, 0xe4, 0xc,1662 MA35_PIN(203, PM11, 0xe4, 0xc,
1579 MA35_MUX(0x0, "GPM11"),1663 MA35_MUX(0x0, "GPM11"),
1580 MA35_MUX(0x1, "EPWM1_CH3"),1664 MA35_MUX(0x1, "EPWM1_CH3"),
1581 MA35_MUX(0x3, "CAN2_TXD"),1665 MA35_MUX(0x3, "CAN2_TXD"),
1666 MA35_MUX(0x4, "USBHL4_DP"),
1582 MA35_MUX(0x5, "SPI3_SS1"),1667 MA35_MUX(0x5, "SPI3_SS1"),
1583 MA35_MUX(0x6, "CCAP0_DATA9"),1668 MA35_MUX(0x6, "CCAP0_DATA9"),
1584 MA35_MUX(0x7, "SPI2_SS1"),1669 MA35_MUX(0x7, "SPI2_SS1"),
1585 MA35_MUX(0x8, "EBI_AD14"),1670 MA35_MUX(0x8, "EBI_AD14"),
1586 MA35_MUX(0xa, "EBI_ADR14")),1671 MA35_MUX(0xa, "EBI_ADR14")),
1587 MA35_PIN(198, PM12, 0xe4, 0x10,1672 MA35_PIN(204, PM12, 0xe4, 0x10,
1588 MA35_MUX(0x0, "GPM12"),1673 MA35_MUX(0x0, "GPM12"),
1589 MA35_MUX(0x1, "EPWM1_CH4"),1674 MA35_MUX(0x1, "EPWM1_CH4"),
1590 MA35_MUX(0x2, "UART10_nCTS"),1675 MA35_MUX(0x2, "UART10_nCTS"),
@@ -1595,7 +1680,7 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { · 4 unmodified lines
1595 MA35_MUX(0x8, "EBI_AD8"),1680 MA35_MUX(0x8, "EBI_AD8"),
1596 MA35_MUX(0x9, "I2S1_MCLK"),1681 MA35_MUX(0x9, "I2S1_MCLK"),
1597 MA35_MUX(0xb, "TM8")),1682 MA35_MUX(0xb, "TM8")),
1598 MA35_PIN(199, PM13, 0xe4, 0x14,1683 MA35_PIN(205, PM13, 0xe4, 0x14,
1599 MA35_MUX(0x0, "GPM13"),1684 MA35_MUX(0x0, "GPM13"),
1600 MA35_MUX(0x1, "EPWM1_CH5"),1685 MA35_MUX(0x1, "EPWM1_CH5"),
1601 MA35_MUX(0x2, "UART10_nRTS"),1686 MA35_MUX(0x2, "UART10_nRTS"),
@@ -1605,99 +1690,66 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { · 3 unmodified lines
1605 MA35_MUX(0x8, "EBI_AD9"),1690 MA35_MUX(0x8, "EBI_AD9"),
1606 MA35_MUX(0x9, "ECAP1_IC0"),1691 MA35_MUX(0x9, "ECAP1_IC0"),
1607 MA35_MUX(0xb, "TM8_EXT")),1692 MA35_MUX(0xb, "TM8_EXT")),
1608 MA35_PIN(200, PM14, 0xe4, 0x18,1693 MA35_PIN(206, PM14, 0xe4, 0x18,
1609 MA35_MUX(0x0, "GPM14"),1694 MA35_MUX(0x0, "GPM14"),
1610 MA35_MUX(0x1, "EPWM1_BRAKE0"),1695 MA35_MUX(0x1, "EPWM1_BRAKE0"),
1611 MA35_MUX(0x2, "UART10_RXD"),1696 MA35_MUX(0x2, "UART10_RXD"),
1612 MA35_MUX(0x3, "TRACE_DATA2"),1697 MA35_MUX(0x3, "TRACE_DATA2"),
1613 MA35_MUX(0x4, "CAN2_RXD"),1698 MA35_MUX(0x4, "CAN2_RXD"),
1699 MA35_MUX(0x5, "USBHL3_DM"),
1614 MA35_MUX(0x6, "I2C3_SDA"),1700 MA35_MUX(0x6, "I2C3_SDA"),
1615 MA35_MUX(0x8, "EBI_AD10"),1701 MA35_MUX(0x8, "EBI_AD10"),
1616 MA35_MUX(0x9, "ECAP1_IC1"),1702 MA35_MUX(0x9, "ECAP1_IC1"),
1617 MA35_MUX(0xb, "TM10"),1703 MA35_MUX(0xb, "TM10"),
1618 MA35_MUX(0xd, "INT1")),1704 MA35_MUX(0xd, "INT1")),
1619 MA35_PIN(201, PM15, 0xe4, 0x1c,1705 MA35_PIN(207, PM15, 0xe4, 0x1c,
1620 MA35_MUX(0x0, "GPM15"),1706 MA35_MUX(0x0, "GPM15"),
1621 MA35_MUX(0x1, "EPWM1_BRAKE1"),1707 MA35_MUX(0x1, "EPWM1_BRAKE1"),
1622 MA35_MUX(0x2, "UART10_TXD"),1708 MA35_MUX(0x2, "UART10_TXD"),
1623 MA35_MUX(0x3, "TRACE_DATA3"),1709 MA35_MUX(0x3, "TRACE_DATA3"),
1624 MA35_MUX(0x4, "CAN2_TXD"),1710 MA35_MUX(0x4, "CAN2_TXD"),
1711 MA35_MUX(0x5, "USBHL3_DP"),
1625 MA35_MUX(0x6, "I2C3_SCL"),1712 MA35_MUX(0x6, "I2C3_SCL"),
1626 MA35_MUX(0x8, "EBI_AD11"),1713 MA35_MUX(0x8, "EBI_AD11"),
1627 MA35_MUX(0x9, "ECAP1_IC2"),1714 MA35_MUX(0x9, "ECAP1_IC2"),
1628 MA35_MUX(0xb, "TM10_EXT"),1715 MA35_MUX(0xb, "TM10_EXT"),
1629 MA35_MUX(0xd, "INT2")),1716 MA35_MUX(0xd, "INT2")),
1630 MA35_PIN(202, PN0, 0xe8, 0x0,1717 MA35_PIN(208, PN0, 0xe8, 0x0,
1631 MA35_MUX(0x0, "GPN0"),1718 MA35_MUX(0x0, "GPN0"),
1632 MA35_MUX(0x4, "I2C2_SDA"),1719 MA35_MUX(0x4, "I2C2_SDA"),
1633 MA35_MUX(0x6, "CCAP1_DATA0")),1720 MA35_MUX(0x6, "CCAP1_DATA0")),
1634 MA35_PIN(203, PN1, 0xe8, 0x4,1721 MA35_PIN(209, PN1, 0xe8, 0x4,
1635 MA35_MUX(0x0, "GPN1"),1722 MA35_MUX(0x0, "GPN1"),
1636 MA35_MUX(0x4, "I2C2_SCL"),1723 MA35_MUX(0x4, "I2C2_SCL"),
1637 MA35_MUX(0x6, "CCAP1_DATA1")),1724 MA35_MUX(0x6, "CCAP1_DATA1")),
1638 MA35_PIN(204, PN2, 0xe8, 0x8,1725 MA35_PIN(210, PN2, 0xe8, 0x8,
1639 MA35_MUX(0x0, "GPN2"),1726 MA35_MUX(0x0, "GPN2"),
1640 MA35_MUX(0x3, "CAN0_RXD"),1727 MA35_MUX(0x3, "CAN0_RXD"),
1728 MA35_MUX(0x4, "USBHL0_DM"),
1641 MA35_MUX(0x6, "CCAP1_DATA2")),1729 MA35_MUX(0x6, "CCAP1_DATA2")),
1642 MA35_PIN(205, PN3, 0xe8, 0xc,1730 MA35_PIN(211, PN3, 0xe8, 0xc,
1643 MA35_MUX(0x0, "GPN3"),1731 MA35_MUX(0x0, "GPN3"),
1644 MA35_MUX(0x3, "CAN0_TXD"),1732 MA35_MUX(0x3, "CAN0_TXD"),
1733 MA35_MUX(0x4, "USBHL0_DP"),
1645 MA35_MUX(0x6, "CCAP1_DATA3")),1734 MA35_MUX(0x6, "CCAP1_DATA3")),
1646 MA35_PIN(206, PN4, 0xe8, 0x10,1735 MA35_PIN(212, PN4, 0xe8, 0x10,
1647 MA35_MUX(0x0, "GPN4"),1736 MA35_MUX(0x0, "GPN4"),
1648 MA35_MUX(0x4, "I2C1_SDA"),1737 MA35_MUX(0x4, "I2C1_SDA"),
1649 MA35_MUX(0x6, "CCAP1_DATA4")),1738 MA35_MUX(0x6, "CCAP1_DATA4")),
1650 MA35_PIN(207, PN5, 0xe8, 0x14,1739 MA35_PIN(213, PN5, 0xe8, 0x14,
1651 MA35_MUX(0x0, "GPN5"),1740 MA35_MUX(0x0, "GPN5"),
1652 MA35_MUX(0x4, "I2C1_SCL"),1741 MA35_MUX(0x4, "I2C1_SCL"),
1653 MA35_MUX(0x6, "CCAP1_DATA5")),1742 MA35_MUX(0x6, "CCAP1_DATA5")),
1654 MA35_PIN(208, PN6, 0xe8, 0x18,1743 MA35_PIN(214, PN6, 0xe8, 0x18,
1655 MA35_MUX(0x0, "GPN6"),1744 MA35_MUX(0x0, "GPN6"),
1656 MA35_MUX(0x3, "CAN1_RXD"),1745 MA35_MUX(0x3, "CAN1_RXD"),
1746 MA35_MUX(0x4, "USBHL1_DM"),
1657 MA35_MUX(0x6, "CCAP1_DATA6")),1747 MA35_MUX(0x6, "CCAP1_DATA6")),
1658 MA35_PIN(209, PN7, 0xe8, 0x1c,1748 MA35_PIN(215, PN7, 0xe8, 0x1c,
1659 MA35_MUX(0x0, "GPN7"),1749 MA35_MUX(0x0, "GPN7"),
1660 MA35_MUX(0x3, "CAN1_TXD"),1750 MA35_MUX(0x3, "CAN1_TXD"),
1751 MA35_MUX(0x4, "USBHL1_DP"),
1661 MA35_MUX(0x6, "CCAP1_DATA7")),1752 MA35_MUX(0x6, "CCAP1_DATA7")),
1662 MA35_PIN(210, PN10, 0xec, 0x8,
1663 MA35_MUX(0x0, "GPN10"),
1664 MA35_MUX(0x3, "CAN2_RXD"),
1665 MA35_MUX(0x6, "CCAP1_SCLK")),
1666 MA35_PIN(211, PN11, 0xec, 0xc,
1667 MA35_MUX(0x0, "GPN11"),
1668 MA35_MUX(0x3, "CAN2_TXD"),
1669 MA35_MUX(0x6, "CCAP1_PIXCLK")),
1670 MA35_PIN(212, PN12, 0xec, 0x10,
1671 MA35_MUX(0x0, "GPN12"),
1672 MA35_MUX(0x2, "UART6_nCTS"),
1673 MA35_MUX(0x3, "UART12_RXD"),
1674 MA35_MUX(0x4, "I2C5_SDA"),
1675 MA35_MUX(0x6, "CCAP1_HSYNC")),
1676 MA35_PIN(213, PN13, 0xec, 0x14,
1677 MA35_MUX(0x0, "GPN13"),
1678 MA35_MUX(0x2, "UART6_nRTS"),
1679 MA35_MUX(0x3, "UART12_TXD"),
1680 MA35_MUX(0x4, "I2C5_SCL"),
1681 MA35_MUX(0x6, "CCAP1_VSYNC")),
1682 MA35_PIN(214, PN14, 0xec, 0x18,
1683 MA35_MUX(0x0, "GPN14"),
1684 MA35_MUX(0x2, "UART6_RXD"),
1685 MA35_MUX(0x3, "CAN3_RXD"),
1686 MA35_MUX(0x5, "SPI1_SS1"),
1687 MA35_MUX(0x6, "CCAP1_SFIELD"),
1688 MA35_MUX(0x7, "SPI1_I2SMCLK")),
1689 MA35_PIN(215, PN15, 0xec, 0x1c,
1690 MA35_MUX(0x0, "GPN15"),
1691 MA35_MUX(0x1, "EPWM2_CH4"),
1692 MA35_MUX(0x2, "UART6_TXD"),
1693 MA35_MUX(0x3, "CAN3_TXD"),
1694 MA35_MUX(0x5, "I2S0_MCLK"),
1695 MA35_MUX(0x6, "SPI1_SS1"),
1696 MA35_MUX(0x7, "SPI1_I2SMCLK"),
1697 MA35_MUX(0x8, "SC0_nCD"),
1698 MA35_MUX(0x9, "EADC0_ST"),
1699 MA35_MUX(0xa, "CLKO"),
1700 MA35_MUX(0xb, "TM6")),
1701 MA35_PIN(216, PN8, 0xec, 0x0,1753 MA35_PIN(216, PN8, 0xec, 0x0,
1702 MA35_MUX(0x0, "GPN8"),1754 MA35_MUX(0x0, "GPN8"),
1703 MA35_MUX(0x1, "EPWM2_CH4"),1755 MA35_MUX(0x1, "EPWM2_CH4"),
drivers/pinctrl/nxp/pinctrl-s32cc.c+30−34
@@ -2,7 +2,7 @@ · 1 unmodified line
2/*2/*
3 * Core driver for the S32 CC (Common Chassis) pin controller3 * Core driver for the S32 CC (Common Chassis) pin controller
4 *4 *
5 * Copyright 2017-2022,2024 NXP5 * Copyright 2017-2022,2024-2025 NXP
6 * Copyright (C) 2022 SUSE LLC6 * Copyright (C) 2022 SUSE LLC
7 * Copyright 2015-2016 Freescale Semiconductor, Inc.7 * Copyright 2015-2016 Freescale Semiconductor, Inc.
8 */8 */
@@ -236,10 +236,10 @@ static int s32_dt_group_node_to_map(struct pinctrl_dev *pctldev, · 227 unmodified lines
236 }236 }
237 237
238 ret = pinconf_generic_parse_dt_config(np, pctldev, &cfgs, &n_cfgs);238 ret = pinconf_generic_parse_dt_config(np, pctldev, &cfgs, &n_cfgs);
239 if (ret) {239 if (ret)
240 dev_err(dev, "%pOF: could not parse node property\n", np);240 return dev_err_probe(dev, ret,
241 return ret;241 "%pOF: could not parse node property\n",
242 }242 np);
243 243
244 if (n_cfgs)244 if (n_cfgs)
245 reserve++;245 reserve++;
@@ -763,15 +763,15 @@ static int s32_pinctrl_parse_groups(struct device_node *np, · 517 unmodified lines
763 grp->data.name = np->name;763 grp->data.name = np->name;
764 764
765 npins = of_property_count_elems_of_size(np, "pinmux", sizeof(u32));765 npins = of_property_count_elems_of_size(np, "pinmux", sizeof(u32));
766 if (npins < 0) {766 if (npins < 0)
767 dev_err(dev, "Failed to read 'pinmux' property in node %s.\n",767 return dev_err_probe(dev, -EINVAL,
768 grp->data.name);768 "Failed to read 'pinmux' in node %s\n",
769 return -EINVAL;769 grp->data.name);
770 }770
771 if (!npins) {771 if (!npins)
772 dev_err(dev, "The group %s has no pins.\n", grp->data.name);772 return dev_err_probe(dev, -EINVAL,
773 return -EINVAL;773 "The group %s has no pins\n",
774 }774 grp->data.name);
775 775
776 grp->data.npins = npins;776 grp->data.npins = npins;
777 777
@@ -812,10 +812,9 @@ static int s32_pinctrl_parse_functions(struct device_node *np, · 34 unmodified lines
812 /* Initialise function */812 /* Initialise function */
813 func->name = np->name;813 func->name = np->name;
814 func->ngroups = of_get_child_count(np);814 func->ngroups = of_get_child_count(np);
815 if (func->ngroups == 0) {815 if (func->ngroups == 0)
816 dev_err(info->dev, "no groups defined in %pOF\n", np);816 return dev_err_probe(info->dev, -EINVAL,
817 return -EINVAL;817 "No groups defined in %pOF\n", np);
818 }
819 818
820 groups = devm_kcalloc(info->dev, func->ngroups,819 groups = devm_kcalloc(info->dev, func->ngroups,
821 sizeof(*func->groups), GFP_KERNEL);820 sizeof(*func->groups), GFP_KERNEL);
@@ -886,10 +885,9 @@ static int s32_pinctrl_probe_dt(struct platform_device *pdev, · 64 unmodified lines
886 }885 }
887 886
888 nfuncs = of_get_child_count(np);887 nfuncs = of_get_child_count(np);
889 if (nfuncs <= 0) {888 if (nfuncs <= 0)
890 dev_err(&pdev->dev, "no functions defined\n");889 return dev_err_probe(&pdev->dev, -EINVAL,
891 return -EINVAL;890 "No functions defined\n");
892 }
893 891
894 info->nfunctions = nfuncs;892 info->nfunctions = nfuncs;
895 info->functions = devm_kcalloc(&pdev->dev, nfuncs,893 info->functions = devm_kcalloc(&pdev->dev, nfuncs,
@@ -919,18 +917,17 @@ static int s32_pinctrl_probe_dt(struct platform_device *pdev, · 23 unmodified lines
919int s32_pinctrl_probe(struct platform_device *pdev,917int s32_pinctrl_probe(struct platform_device *pdev,
920 const struct s32_pinctrl_soc_data *soc_data)918 const struct s32_pinctrl_soc_data *soc_data)
921{919{
922 struct s32_pinctrl *ipctl;
923 int ret;
924 struct pinctrl_desc *s32_pinctrl_desc;
925 struct s32_pinctrl_soc_info *info;
926#ifdef CONFIG_PM_SLEEP920#ifdef CONFIG_PM_SLEEP
927 struct s32_pinctrl_context *saved_context;921 struct s32_pinctrl_context *saved_context;
928#endif922#endif
923 struct pinctrl_desc *s32_pinctrl_desc;
924 struct s32_pinctrl_soc_info *info;
925 struct s32_pinctrl *ipctl;
926 int ret;
929 927
930 if (!soc_data || !soc_data->pins || !soc_data->npins) {928 if (!soc_data || !soc_data->pins || !soc_data->npins)
931 dev_err(&pdev->dev, "wrong pinctrl info\n");929 return dev_err_probe(&pdev->dev, -EINVAL,
932 return -EINVAL;930 "Wrong pinctrl info\n");
933 }
934 931
935 info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);932 info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
936 if (!info)933 if (!info)
@@ -965,10 +962,9 @@ int s32_pinctrl_probe(struct platform_device *pdev, · 28 unmodified lines
965 s32_pinctrl_desc->owner = THIS_MODULE;962 s32_pinctrl_desc->owner = THIS_MODULE;
966 963
967 ret = s32_pinctrl_probe_dt(pdev, ipctl);964 ret = s32_pinctrl_probe_dt(pdev, ipctl);
968 if (ret) {965 if (ret)
969 dev_err(&pdev->dev, "fail to probe dt properties\n");966 return dev_err_probe(&pdev->dev, ret,
970 return ret;967 "Fail to probe dt properties\n");
971 }
972 968
973 ipctl->pctl = devm_pinctrl_register(&pdev->dev, s32_pinctrl_desc,969 ipctl->pctl = devm_pinctrl_register(&pdev->dev, s32_pinctrl_desc,
974 ipctl);970 ipctl);
drivers/pinctrl/pinconf-generic.c+2−5
@@ -225,10 +225,9 @@ static int parse_fw_cfg(struct fwnode_handle *fwnode, · 224 unmodified lines
225 unsigned int count, unsigned long *cfg,225 unsigned int count, unsigned long *cfg,
226 unsigned int *ncfg)226 unsigned int *ncfg)
227{227{
228 unsigned long *properties;
229 int i, test;228 int i, test;
230 229
231 properties = bitmap_zalloc(count, GFP_KERNEL);230 unsigned long *properties __free(bitmap) = bitmap_zalloc(count, GFP_KERNEL);
232 231
233 for (i = 0; i < count; i++) {232 for (i = 0; i < count; i++) {
234 u32 val;233 u32 val;
@@ -263,7 +262,6 @@ static int parse_fw_cfg(struct fwnode_handle *fwnode, · 28 unmodified lines
263 if (ret) {262 if (ret) {
264 pr_err("%pfw: conflicting setting detected for %s\n",263 pr_err("%pfw: conflicting setting detected for %s\n",
265 fwnode, par->property);264 fwnode, par->property);
266 bitmap_free(properties);
267 return -EINVAL;265 return -EINVAL;
268 }266 }
269 }267 }
@@ -295,7 +293,6 @@ static int parse_fw_cfg(struct fwnode_handle *fwnode, · 25 unmodified lines
295 pr_err("%pfw: cannot have multiple drive configurations\n",293 pr_err("%pfw: cannot have multiple drive configurations\n",
296 fwnode);294 fwnode);
297 295
298 bitmap_free(properties);
299 return 0;296 return 0;
300}297}
301 298
@@ -419,7 +416,7 @@ int pinconf_generic_parse_dt_config(struct device_node *np, · 117 unmodified lines
419 * Now limit the number of configs to the real number of416 * Now limit the number of configs to the real number of
420 * found properties.417 * found properties.
421 */418 */
422 *configs = kmemdup(cfg, ncfg * sizeof(unsigned long), GFP_KERNEL);419 *configs = kmemdup_array(cfg, ncfg, sizeof(unsigned long), GFP_KERNEL);
423 if (!*configs) {420 if (!*configs) {
424 ret = -ENOMEM;421 ret = -ENOMEM;
425 goto out;422 goto out;
drivers/pinctrl/pinconf.c+7−2
@@ -275,7 +275,7 @@ void pinconf_show_setting(struct seq_file *s, · 274 unmodified lines
275 case PIN_MAP_TYPE_CONFIGS_GROUP:275 case PIN_MAP_TYPE_CONFIGS_GROUP:
276 seq_printf(s, "group %s (%d)",276 seq_printf(s, "group %s (%d)",
277 pctlops->get_group_name(pctldev,277 pctlops->get_group_name(pctldev,
278 setting->data.configs.group_or_pin),278 setting->data.configs.group_or_pin),
279 setting->data.configs.group_or_pin);279 setting->data.configs.group_or_pin);
280 break;280 break;
281 default:281 default:
@@ -348,8 +348,13 @@ static int pinconf_groups_show(struct seq_file *s, void *what) · 66 unmodified lines
348{348{
349 struct pinctrl_dev *pctldev = s->private;349 struct pinctrl_dev *pctldev = s->private;
350 const struct pinctrl_ops *pctlops = pctldev->desc->pctlops;350 const struct pinctrl_ops *pctlops = pctldev->desc->pctlops;
351 unsigned int ngroups = pctlops->get_groups_count(pctldev);
352 unsigned int selector = 0;351 unsigned int selector = 0;
352 unsigned int ngroups;
353
354 if (!pctlops->get_groups_count || !pctlops->get_group_name)
355 return 0;
356
357 ngroups = pctlops->get_groups_count(pctldev);
353 358
354 seq_puts(s, "Pin config settings per pin group\n");359 seq_puts(s, "Pin config settings per pin group\n");
355 seq_puts(s, "Format: group (name): configs\n");360 seq_puts(s, "Format: group (name): configs\n");
drivers/pinctrl/pinconf.h+31−1
@@ -167,11 +167,22 @@ pinconf_generic_parse_dt_pinmux(struct device_node *np, struct device *dev, · 166 unmodified lines
167}167}
168#endif168#endif
169 169
170#if defined(CONFIG_GENERIC_PINCTRL) && defined (CONFIG_OF)170#if defined(CONFIG_GENERIC_PINCTRL)
171int pinctrl_generic_pins_function_dt_node_to_map(struct pinctrl_dev *pctldev,171int pinctrl_generic_pins_function_dt_node_to_map(struct pinctrl_dev *pctldev,
172 struct device_node *np,172 struct device_node *np,
173 struct pinctrl_map **maps,173 struct pinctrl_map **maps,
174 unsigned int *num_maps);174 unsigned int *num_maps);
175
176int pinctrl_generic_pinmux_dt_node_to_map(struct pinctrl_dev *pctldev,
177 struct device_node *np,
178 struct pinctrl_map **maps,
179 unsigned int *num_maps);
180
181int pinctrl_generic_to_map(struct pinctrl_dev *pctldev, struct device_node *parent,
182 struct device_node *np, struct pinctrl_map **maps,
183 unsigned int *num_maps, unsigned int *num_reserved_maps,
184 const char **group_name, unsigned int ngroups,
185 void *data, unsigned int *pins, unsigned int npins);
175#else186#else
176static inline int187static inline int
177pinctrl_generic_pins_function_dt_node_to_map(struct pinctrl_dev *pctldev,188pinctrl_generic_pins_function_dt_node_to_map(struct pinctrl_dev *pctldev,
@@ -181,4 +192,23 @@ pinctrl_generic_pins_function_dt_node_to_map(struct pinctrl_dev *pctldev, · 3 unmodified lines
181{192{
182 return -ENOTSUPP;193 return -ENOTSUPP;
183}194}
195
196static inline int
197pinctrl_generic_pinmux_dt_node_to_map(struct pinctrl_dev *pctldev,
198 struct device_node *np,
199 struct pinctrl_map **maps,
200 unsigned int *num_maps)
201{
202 return -ENOTSUPP;
203}
204
205static inline int
206pinctrl_generic_to_map(struct pinctrl_dev *pctldev, struct device_node *parent,
207 struct device_node *np, struct pinctrl_map **maps,
208 unsigned int *num_maps, unsigned int *num_reserved_maps,
209 const char **group_name, unsigned int ngroups,
210 void *data, unsigned int *pins, unsigned int npins)
211{
212 return -ENOTSUPP;
213}
184#endif214#endif
drivers/pinctrl/pinctrl-aw9523.c+1−1
@@ -1033,7 +1033,7 @@ static void aw9523_remove(struct i2c_client *client) · 1032 unmodified lines
1033}1033}
1034 1034
1035static const struct i2c_device_id aw9523_i2c_id_table[] = {1035static const struct i2c_device_id aw9523_i2c_id_table[] = {
1036 { "aw9523_i2c" },1036 { .name = "aw9523_i2c" },
1037 { }1037 { }
1038};1038};
1039MODULE_DEVICE_TABLE(i2c, aw9523_i2c_id_table);1039MODULE_DEVICE_TABLE(i2c, aw9523_i2c_id_table);
drivers/pinctrl/pinctrl-cy8c95x0.c+3−3
@@ -1461,9 +1461,9 @@ static int cy8c95x0_probe(struct i2c_client *client) · 1460 unmodified lines
1461}1461}
1462 1462
1463static const struct i2c_device_id cy8c95x0_id[] = {1463static const struct i2c_device_id cy8c95x0_id[] = {
1464 { "cy8c9520", 20 },1464 { .name = "cy8c9520", .driver_data = 20 },
1465 { "cy8c9540", 40 },1465 { .name = "cy8c9540", .driver_data = 40 },
1466 { "cy8c9560", 60 },1466 { .name = "cy8c9560", .driver_data = 60 },
1467 { }1467 { }
1468};1468};
1469MODULE_DEVICE_TABLE(i2c, cy8c95x0_id);1469MODULE_DEVICE_TABLE(i2c, cy8c95x0_id);
drivers/pinctrl/pinctrl-equilibrium.c+2−1
@@ -532,8 +532,9 @@ static int eqbr_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, · 531 unmodified lines
532static int eqbr_pinconf_group_get(struct pinctrl_dev *pctldev,532static int eqbr_pinconf_group_get(struct pinctrl_dev *pctldev,
533 unsigned int group, unsigned long *config)533 unsigned int group, unsigned long *config)
534{534{
535 unsigned int i, npins, old = 0;
536 const unsigned int *pins;535 const unsigned int *pins;
536 unsigned int i, npins;
537 unsigned long old = 0;
537 int ret;538 int ret;
538 539
539 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);540 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
drivers/pinctrl/pinctrl-generic-mux.c+184−0
@@ -0,0 +1,184 @@
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Generic Pin Control Driver for Board-Level Mux Chips
4 * Copyright 2026 NXP
5 */
6
7#include <linux/cleanup.h>
8#include <linux/module.h>
9#include <linux/of.h>
10#include <linux/mutex.h>
11#include <linux/mux/consumer.h>
12#include <linux/platform_device.h>
13#include <linux/pinctrl/pinconf-generic.h>
14#include <linux/pinctrl/pinctrl.h>
15#include <linux/pinctrl/pinmux.h>
16#include <linux/slab.h>
17
18#include "core.h"
19#include "pinconf.h"
20#include "pinmux.h"
21#include "pinctrl-utils.h"
22
23struct mux_pin_function {
24 struct mux_state *mux_state;
25};
26
27struct mux_pinctrl {
28 struct device *dev;
29 struct pinctrl_dev *pctl;
30
31 /* mutex protect [pinctrl|pinmux]_generic functions */
32 struct mutex lock;
33};
34
35static int
36mux_pinmux_dt_node_to_map(struct pinctrl_dev *pctldev,
37 struct device_node *np_config,
38 struct pinctrl_map **maps, unsigned int *num_maps)
39{
40 unsigned int num_reserved_maps = 0;
41 struct mux_pin_function *function;
42 const char **group_names;
43 int ret;
44
45 function = devm_kzalloc(pctldev->dev, sizeof(*function), GFP_KERNEL);
46 if (!function)
47 return -ENOMEM;
48
49 group_names = devm_kcalloc(pctldev->dev, 1, sizeof(*group_names), GFP_KERNEL);
50 if (!group_names)
51 return -ENOMEM;
52
53 function->mux_state = devm_mux_state_get_from_np(pctldev->dev, NULL, np_config);
54 if (IS_ERR(function->mux_state))
55 return PTR_ERR(function->mux_state);
56
57 ret = pinctrl_generic_to_map(pctldev, np_config, np_config, maps,
58 num_maps, &num_reserved_maps, group_names,
59 0, &np_config->name, NULL, 0);
60
61 if (ret)
62 return ret;
63
64 ret = pinmux_generic_add_function(pctldev, np_config->name, group_names,
65 1, function);
66 if (ret < 0) {
67 pinctrl_utils_free_map(pctldev, *maps, *num_maps);
68 return ret;
69 }
70
71 return 0;
72}
73
74static const struct pinctrl_ops mux_pinctrl_ops = {
75 .get_groups_count = pinctrl_generic_get_group_count,
76 .get_group_name = pinctrl_generic_get_group_name,
77 .get_group_pins = pinctrl_generic_get_group_pins,
78 .dt_node_to_map = mux_pinmux_dt_node_to_map,
79 .dt_free_map = pinctrl_utils_free_map,
80};
81
82static int mux_pinmux_set_mux(struct pinctrl_dev *pctldev,
83 unsigned int func_selector,
84 unsigned int group_selector)
85{
86 struct mux_pinctrl *mpctl = pinctrl_dev_get_drvdata(pctldev);
87 const struct function_desc *function;
88 struct mux_pin_function *func;
89 int ret;
90
91 guard(mutex)(&mpctl->lock);
92
93 function = pinmux_generic_get_function(pctldev, func_selector);
94 func = function->data;
95
96 ret = mux_state_select(func->mux_state);
97 if (ret)
98 return ret;
99
100 return 0;
101}
102
103static void mux_pinmux_release_mux(struct pinctrl_dev *pctldev,
104 unsigned int func_selector,
105 unsigned int group_selector)
106{
107 struct mux_pinctrl *mpctl = pinctrl_dev_get_drvdata(pctldev);
108 const struct function_desc *function;
109 struct mux_pin_function *func;
110
111 guard(mutex)(&mpctl->lock);
112
113 function = pinmux_generic_get_function(pctldev, func_selector);
114 func = function->data;
115
116 mux_state_deselect(func->mux_state);
117}
118
119static const struct pinmux_ops mux_pinmux_ops = {
120 .get_functions_count = pinmux_generic_get_function_count,
121 .get_function_name = pinmux_generic_get_function_name,
122 .get_function_groups = pinmux_generic_get_function_groups,
123 .set_mux = mux_pinmux_set_mux,
124 .release_mux = mux_pinmux_release_mux,
125};
126
127static int mux_pinctrl_probe(struct platform_device *pdev)
128{
129 struct device *dev = &pdev->dev;
130 struct mux_pinctrl *mpctl;
131 struct pinctrl_desc *pctl_desc;
132 int ret;
133
134 mpctl = devm_kzalloc(dev, sizeof(*mpctl), GFP_KERNEL);
135 if (!mpctl)
136 return -ENOMEM;
137
138 mpctl->dev = dev;
139
140 platform_set_drvdata(pdev, mpctl);
141
142 pctl_desc = devm_kzalloc(dev, sizeof(*pctl_desc), GFP_KERNEL);
143 if (!pctl_desc)
144 return -ENOMEM;
145
146 ret = devm_mutex_init(dev, &mpctl->lock);
147 if (ret)
148 return ret;
149
150 pctl_desc->name = dev_name(dev);
151 pctl_desc->owner = THIS_MODULE;
152 pctl_desc->pctlops = &mux_pinctrl_ops;
153 pctl_desc->pmxops = &mux_pinmux_ops;
154
155 ret = devm_pinctrl_register_and_init(dev, pctl_desc, mpctl,
156 &mpctl->pctl);
157 if (ret)
158 return dev_err_probe(dev, ret, "Failed to register pinctrl.\n");
159
160 ret = pinctrl_enable(mpctl->pctl);
161 if (ret)
162 return dev_err_probe(dev, ret, "Failed to enable pinctrl.\n");
163
164 return 0;
165}
166
167static const struct of_device_id mux_pinctrl_of_match[] = {
168 { .compatible = "pinctrl-multiplexer" },
169 { }
170};
171MODULE_DEVICE_TABLE(of, mux_pinctrl_of_match);
172
173static struct platform_driver mux_pinctrl_driver = {
174 .driver = {
175 .name = "generic-pinctrl-mux",
176 .of_match_table = mux_pinctrl_of_match,
177 },
178 .probe = mux_pinctrl_probe,
179};
180module_platform_driver(mux_pinctrl_driver);
181
182MODULE_AUTHOR("Frank Li <Frank.Li@nxp.com>");
183MODULE_DESCRIPTION("Generic Pin Control Driver for Board-Level Mux Chips");
184MODULE_LICENSE("GPL");
drivers/pinctrl/pinctrl-generic.c+152−59
@@ -17,6 +17,61 @@ · 16 unmodified lines
17#include "pinctrl-utils.h"17#include "pinctrl-utils.h"
18#include "pinmux.h"18#include "pinmux.h"
19 19
20int pinctrl_generic_to_map(struct pinctrl_dev *pctldev, struct device_node *parent,
21 struct device_node *np, struct pinctrl_map **maps,
22 unsigned int *num_maps, unsigned int *num_reserved_maps,
23 const char **group_names, unsigned int ngroups,
24 void *data, unsigned int *pins, unsigned int npins)
25{
26 struct device *dev = pctldev->dev;
27 unsigned int num_configs;
28 const char *group_name;
29 unsigned long *configs;
30 int ret, reserve = 1;
31
32 group_name = devm_kasprintf(dev, GFP_KERNEL, "%pOFn.%pOFn", parent, np);
33 if (!group_name)
34 return -ENOMEM;
35
36 group_names[ngroups] = group_name;
37
38 ret = pinctrl_utils_reserve_map(pctldev, maps, num_reserved_maps, num_maps, reserve);
39 if (ret)
40 return ret;
41
42 ret = pinctrl_utils_add_map_mux(pctldev, maps, num_reserved_maps, num_maps, group_name,
43 parent->name);
44 if (ret < 0)
45 return ret;
46
47 ret = pinctrl_generic_add_group(pctldev, group_name, pins, npins, data);
48 if (ret < 0)
49 return dev_err_probe(dev, ret, "failed to add group %s: %d\n",
50 group_name, ret);
51
52 ret = pinconf_generic_parse_dt_config(np, pctldev, &configs, &num_configs);
53 if (ret)
54 return dev_err_probe(dev, ret, "failed to parse pin config of group %s\n",
55 group_name);
56
57 if (num_configs == 0)
58 return 0;
59
60 ret = pinctrl_utils_reserve_map(pctldev, maps, num_reserved_maps, num_maps, reserve);
61 if (ret)
62 return ret;
63
64 ret = pinctrl_utils_add_map_configs(pctldev, maps, num_reserved_maps, num_maps, group_name,
65 configs,
66 num_configs, PIN_MAP_TYPE_CONFIGS_GROUP);
67 kfree(configs);
68 if (ret)
69 return ret;
70
71 return 0;
72};
73EXPORT_SYMBOL_GPL(pinctrl_generic_to_map);
74
20static int pinctrl_generic_pins_function_dt_subnode_to_map(struct pinctrl_dev *pctldev,75static int pinctrl_generic_pins_function_dt_subnode_to_map(struct pinctrl_dev *pctldev,
21 struct device_node *parent,76 struct device_node *parent,
22 struct device_node *np,77 struct device_node *np,
@@ -27,11 +82,9 @@ static int pinctrl_generic_pins_function_dt_subnode_to_map(struct pinctrl_dev *p · 4 unmodified lines
27 unsigned int ngroups)82 unsigned int ngroups)
28{83{
29 struct device *dev = pctldev->dev;84 struct device *dev = pctldev->dev;
85 unsigned int pin, *pins;
30 const char **functions;86 const char **functions;
31 const char *group_name;87 int npins, ret;
32 unsigned long *configs;
33 unsigned int num_configs, pin, *pins;
34 int npins, ret, reserve = 1;
35 88
36 npins = of_property_count_u32_elems(np, "pins");89 npins = of_property_count_u32_elems(np, "pins");
37 90
@@ -41,12 +94,6 @@ static int pinctrl_generic_pins_function_dt_subnode_to_map(struct pinctrl_dev *p · 3 unmodified lines
41 return npins;94 return npins;
42 }95 }
43 96
44 group_name = devm_kasprintf(dev, GFP_KERNEL, "%pOFn.%pOFn", parent, np);
45 if (!group_name)
46 return -ENOMEM;
47
48 group_names[ngroups] = group_name;
49
50 pins = devm_kcalloc(dev, npins, sizeof(*pins), GFP_KERNEL);97 pins = devm_kcalloc(dev, npins, sizeof(*pins), GFP_KERNEL);
51 if (!pins)98 if (!pins)
52 return -ENOMEM;99 return -ENOMEM;
@@ -67,53 +114,69 @@ static int pinctrl_generic_pins_function_dt_subnode_to_map(struct pinctrl_dev *p · 14 unmodified lines
67 return ret;114 return ret;
68 }115 }
69 116
70 ret = pinctrl_utils_reserve_map(pctldev, maps, num_reserved_maps, num_maps, reserve);117 return pinctrl_generic_to_map(pctldev, parent, np, maps, num_maps,
71 if (ret)118 num_reserved_maps, group_names, ngroups,
72 return ret;119 functions, pins, npins);
120}
73 121
74 ret = pinctrl_utils_add_map_mux(pctldev, maps, num_reserved_maps, num_maps, group_name,122static int pinctrl_generic_pinmux_dt_subnode_to_map(struct pinctrl_dev *pctldev,
75 parent->name);123 struct device_node *parent,
76 if (ret < 0)124 struct device_node *np,
77 return ret;125 struct pinctrl_map **maps,
126 unsigned int *num_maps,
127 unsigned int *num_reserved_maps,
128 const char **group_names,
129 unsigned int ngroups)
130{
131 struct device *dev = pctldev->dev;
132 unsigned int *pins, *muxes;
133 int npins, ret;
78 134
79 ret = pinctrl_generic_add_group(pctldev, group_name, pins, npins, functions);135 npins = of_property_count_u32_elems(np, "pinmux");
80 if (ret < 0)
81 return dev_err_probe(dev, ret, "failed to add group %s: %d\n",
82 group_name, ret);
83 136
84 ret = pinconf_generic_parse_dt_config(np, pctldev, &configs, &num_configs);137 if (npins < 1) {
85 if (ret)138 dev_err(dev, "invalid pinctrl group %pOFn.%pOFn %d\n",
86 return dev_err_probe(dev, ret, "failed to parse pin config of group %s\n",139 parent, np, npins);
87 group_name);140 return npins;
141 }
88 142
89 if (num_configs == 0)143 pins = devm_kcalloc(dev, npins, sizeof(*pins), GFP_KERNEL);
90 return 0;144 if (!pins)
145 return -ENOMEM;
91 146
92 ret = pinctrl_utils_reserve_map(pctldev, maps, num_reserved_maps, num_maps, reserve);147 muxes = devm_kcalloc(dev, npins, sizeof(*muxes), GFP_KERNEL);
93 if (ret)148 if (!muxes)
94 return ret;149 return -ENOMEM;
95 150
96 ret = pinctrl_utils_add_map_configs(pctldev, maps, num_reserved_maps, num_maps, group_name,151 for (int i = 0; i < npins; i++) {
97 configs,152 unsigned int pinmux;
98 num_configs, PIN_MAP_TYPE_CONFIGS_GROUP);
99 kfree(configs);
100 if (ret)
101 return ret;
102 153
103 return 0;154 ret = of_property_read_u32_index(np, "pinmux", i, &pinmux);
104};155 if (ret)
156 return ret;
105 157
106/*158 pins[i] = pinmux >> 16;
107 * For platforms that do not define groups or functions in the driver, but159 muxes[i] = pinmux & GENMASK(15, 0);
108 * instead use the devicetree to describe them. This function will, unlike160 }
109 * pinconf_generic_dt_node_to_map() etc which rely on driver defined groups161
110 * and functions, create them in addition to parsing pinconf properties and162 return pinctrl_generic_to_map(pctldev, parent, np, maps, num_maps,
111 * adding mappings.163 num_reserved_maps, group_names, ngroups,
112 */164 muxes, pins, npins);
113int pinctrl_generic_pins_function_dt_node_to_map(struct pinctrl_dev *pctldev,165}
114 struct device_node *np,166
115 struct pinctrl_map **maps,167static int pinctrl_generic_dt_node_to_map(struct pinctrl_dev *pctldev,
116 unsigned int *num_maps)168 struct device_node *np,
169 struct pinctrl_map **maps,
170 unsigned int *num_maps,
171 int (dt_subnode_to_map)(
172 struct pinctrl_dev *,
173 struct device_node *,
174 struct device_node *,
175 struct pinctrl_map **,
176 unsigned int *,
177 unsigned int *,
178 const char **,
179 unsigned int))
117{180{
118 struct device *dev = pctldev->dev;181 struct device *dev = pctldev->dev;
119 struct device_node *child_np;182 struct device_node *child_np;
@@ -136,11 +199,8 @@ int pinctrl_generic_pins_function_dt_node_to_map(struct pinctrl_dev *pctldev, · 16 unmodified lines
136 if (!group_names)199 if (!group_names)
137 return -ENOMEM;200 return -ENOMEM;
138 201
139 ret = pinctrl_generic_pins_function_dt_subnode_to_map(pctldev, np, np,202 ret = dt_subnode_to_map(pctldev, np, np, maps, num_maps,
140 maps, num_maps,203 &num_reserved_maps, group_names, ngroups);
141 &num_reserved_maps,
142 group_names,
143 ngroups);
144 if (ret) {204 if (ret) {
145 pinctrl_utils_free_map(pctldev, *maps, *num_maps);205 pinctrl_utils_free_map(pctldev, *maps, *num_maps);
146 return dev_err_probe(dev, ret, "error figuring out mappings for %s\n", np->name);206 return dev_err_probe(dev, ret, "error figuring out mappings for %s\n", np->name);
@@ -164,11 +224,8 @@ parent: · 17 unmodified lines
164 224
165 ngroups = 0;225 ngroups = 0;
166 for_each_available_child_of_node_scoped(np, child_np) {226 for_each_available_child_of_node_scoped(np, child_np) {
167 ret = pinctrl_generic_pins_function_dt_subnode_to_map(pctldev, np, child_np,227 ret = dt_subnode_to_map(pctldev, np, child_np, maps, num_maps,
168 maps, num_maps,228 &num_reserved_maps, group_names, ngroups);
169 &num_reserved_maps,
170 group_names,
171 ngroups);
172 if (ret) {229 if (ret) {
173 pinctrl_utils_free_map(pctldev, *maps, *num_maps);230 pinctrl_utils_free_map(pctldev, *maps, *num_maps);
174 return dev_err_probe(dev, ret, "error figuring out mappings for %s\n",231 return dev_err_probe(dev, ret, "error figuring out mappings for %s\n",
@@ -186,4 +243,40 @@ parent: · 11 unmodified lines
186 243
187 return 0;244 return 0;
188}245}
246
247/*
248 * For platforms that do not define groups or functions in the driver, but
249 * instead use the devicetree to describe them. This function will, unlike
250 * pinconf_generic_dt_node_to_map() etc which rely on driver defined groups
251 * and functions, create them in addition to parsing pinconf properties and
252 * adding mappings.
253 */
254int pinctrl_generic_pins_function_dt_node_to_map(struct pinctrl_dev *pctldev,
255 struct device_node *np,
256 struct pinctrl_map **maps,
257 unsigned int *num_maps)
258{
259 return pinctrl_generic_dt_node_to_map(pctldev, np, maps, num_maps,
260 &pinctrl_generic_pins_function_dt_subnode_to_map);
261}
189EXPORT_SYMBOL_GPL(pinctrl_generic_pins_function_dt_node_to_map);262EXPORT_SYMBOL_GPL(pinctrl_generic_pins_function_dt_node_to_map);
263
264/*
265 * For platforms that do not define groups or functions in the driver, but
266 * instead use the devicetree to describe them. This function will, unlike
267 * pinconf_generic_dt_node_to_map() etc which rely on driver defined groups
268 * and functions, create them in addition to parsing pinconf properties and
269 * adding mappings.
270 *
271 * It assumes that the upper 16 bits of the pinmux items contain the pin
272 * and the lower 16 the mux setting.
273 */
274int pinctrl_generic_pinmux_dt_node_to_map(struct pinctrl_dev *pctldev,
275 struct device_node *np,
276 struct pinctrl_map **maps,
277 unsigned int *num_maps)
278{
279 return pinctrl_generic_dt_node_to_map(pctldev, np, maps, num_maps,
280 &pinctrl_generic_pinmux_dt_subnode_to_map);
281};
282EXPORT_SYMBOL_GPL(pinctrl_generic_pinmux_dt_node_to_map);
drivers/pinctrl/pinctrl-ingenic.c+2−1
@@ -4334,7 +4334,8 @@ static int ingenic_pinconf_group_get(struct pinctrl_dev *pctldev, · 4333 unmodified lines
4334 unsigned int group, unsigned long *config)4334 unsigned int group, unsigned long *config)
4335{4335{
4336 const unsigned int *pins;4336 const unsigned int *pins;
4337 unsigned int i, npins, old = 0;4337 unsigned int i, npins;
4338 unsigned long old = 0;
4338 int ret;4339 int ret;
4339 4340
4340 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);4341 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
drivers/pinctrl/pinctrl-max77620.c+3−3
@@ -645,9 +645,9 @@ static const struct dev_pm_ops max77620_pinctrl_pm_ops = { · 644 unmodified lines
645};645};
646 646
647static const struct platform_device_id max77620_pinctrl_devtype[] = {647static const struct platform_device_id max77620_pinctrl_devtype[] = {
648 { .name = "max77620-pinctrl", },648 { .name = "max77620-pinctrl" },
649 { .name = "max20024-pinctrl", },649 { .name = "max20024-pinctrl" },
650 {},650 { }
651};651};
652MODULE_DEVICE_TABLE(platform, max77620_pinctrl_devtype);652MODULE_DEVICE_TABLE(platform, max77620_pinctrl_devtype);
653 653
drivers/pinctrl/pinctrl-mcp23s08_i2c.c+3−3
@@ -67,9 +67,9 @@ static const struct mcp23s08_info mcp23018_i2c = { · 66 unmodified lines
67};67};
68 68
69static const struct i2c_device_id mcp230xx_id[] = {69static const struct i2c_device_id mcp230xx_id[] = {
70 { "mcp23008", (kernel_ulong_t)&mcp23008_i2c },70 { .name = "mcp23008", .driver_data = (kernel_ulong_t)&mcp23008_i2c },
71 { "mcp23017", (kernel_ulong_t)&mcp23017_i2c },71 { .name = "mcp23017", .driver_data = (kernel_ulong_t)&mcp23017_i2c },
72 { "mcp23018", (kernel_ulong_t)&mcp23018_i2c },72 { .name = "mcp23018", .driver_data = (kernel_ulong_t)&mcp23018_i2c },
73 { }73 { }
74};74};
75MODULE_DEVICE_TABLE(i2c, mcp230xx_id);75MODULE_DEVICE_TABLE(i2c, mcp230xx_id);
drivers/pinctrl/pinctrl-rockchip.c+1−1
@@ -5303,6 +5303,7 @@ static const struct of_device_id rockchip_pinctrl_dt_match[] = { · 5302 unmodified lines
5303 .data = &rk3588_pin_ctrl },5303 .data = &rk3588_pin_ctrl },
5304 {},5304 {},
5305};5305};
5306MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match);
5306 5307
5307static struct platform_driver rockchip_pinctrl_driver = {5308static struct platform_driver rockchip_pinctrl_driver = {
5308 .probe = rockchip_pinctrl_probe,5309 .probe = rockchip_pinctrl_probe,
@@ -5329,4 +5330,3 @@ module_exit(rockchip_pinctrl_drv_unregister); · 20 unmodified lines
5329MODULE_DESCRIPTION("ROCKCHIP Pin Controller Driver");5330MODULE_DESCRIPTION("ROCKCHIP Pin Controller Driver");
5330MODULE_LICENSE("GPL");5331MODULE_LICENSE("GPL");
5331MODULE_ALIAS("platform:pinctrl-rockchip");5332MODULE_ALIAS("platform:pinctrl-rockchip");
5332MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match);
drivers/pinctrl/pinctrl-single.c+2−1
@@ -619,8 +619,9 @@ static int pcs_pinconf_set(struct pinctrl_dev *pctldev, · 618 unmodified lines
619static int pcs_pinconf_group_get(struct pinctrl_dev *pctldev,619static int pcs_pinconf_group_get(struct pinctrl_dev *pctldev,
620 unsigned group, unsigned long *config)620 unsigned group, unsigned long *config)
621{621{
622 unsigned long old = 0;
622 const unsigned *pins;623 const unsigned *pins;
623 unsigned npins, old = 0;624 unsigned npins;
624 int i, ret;625 int i, ret;
625 626
626 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);627 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
drivers/pinctrl/pinctrl-sx150x.c+10−10
@@ -839,16 +839,16 @@ static const struct pinconf_ops sx150x_pinconf_ops = { · 838 unmodified lines
839};839};
840 840
841static const struct i2c_device_id sx150x_id[] = {841static const struct i2c_device_id sx150x_id[] = {
842 {"sx1501q", (kernel_ulong_t) &sx1501q_device_data },842 { .name = "sx1501q", .driver_data = (kernel_ulong_t)&sx1501q_device_data },
843 {"sx1502q", (kernel_ulong_t) &sx1502q_device_data },843 { .name = "sx1502q", .driver_data = (kernel_ulong_t)&sx1502q_device_data },
844 {"sx1503q", (kernel_ulong_t) &sx1503q_device_data },844 { .name = "sx1503q", .driver_data = (kernel_ulong_t)&sx1503q_device_data },
845 {"sx1504q", (kernel_ulong_t) &sx1504q_device_data },845 { .name = "sx1504q", .driver_data = (kernel_ulong_t)&sx1504q_device_data },
846 {"sx1505q", (kernel_ulong_t) &sx1505q_device_data },846 { .name = "sx1505q", .driver_data = (kernel_ulong_t)&sx1505q_device_data },
847 {"sx1506q", (kernel_ulong_t) &sx1506q_device_data },847 { .name = "sx1506q", .driver_data = (kernel_ulong_t)&sx1506q_device_data },
848 {"sx1507q", (kernel_ulong_t) &sx1507q_device_data },848 { .name = "sx1507q", .driver_data = (kernel_ulong_t)&sx1507q_device_data },
849 {"sx1508q", (kernel_ulong_t) &sx1508q_device_data },849 { .name = "sx1508q", .driver_data = (kernel_ulong_t)&sx1508q_device_data },
850 {"sx1509q", (kernel_ulong_t) &sx1509q_device_data },850 { .name = "sx1509q", .driver_data = (kernel_ulong_t)&sx1509q_device_data },
851 {}851 { }
852};852};
853 853
854static const struct of_device_id sx150x_of_match[] = {854static const struct of_device_id sx150x_of_match[] = {
drivers/pinctrl/pinctrl-tps6594.c+2−2
@@ -562,8 +562,8 @@ static int tps6594_pinctrl_probe(struct platform_device *pdev) · 561 unmodified lines
562}562}
563 563
564static const struct platform_device_id tps6594_pinctrl_id_table[] = {564static const struct platform_device_id tps6594_pinctrl_id_table[] = {
565 { "tps6594-pinctrl", },565 { .name = "tps6594-pinctrl" },
566 {}566 { }
567};567};
568MODULE_DEVICE_TABLE(platform, tps6594_pinctrl_id_table);568MODULE_DEVICE_TABLE(platform, tps6594_pinctrl_id_table);
569 569
drivers/pinctrl/pinmux.c+5−0
@@ -517,6 +517,7 @@ void pinmux_disable_setting(const struct pinctrl_setting *setting) · 516 unmodified lines
517{517{
518 struct pinctrl_dev *pctldev = setting->pctldev;518 struct pinctrl_dev *pctldev = setting->pctldev;
519 const struct pinctrl_ops *pctlops = pctldev->desc->pctlops;519 const struct pinctrl_ops *pctlops = pctldev->desc->pctlops;
520 const struct pinmux_ops *ops = pctldev->desc->pmxops;
520 int ret = 0;521 int ret = 0;
521 const unsigned int *pins = NULL;522 const unsigned int *pins = NULL;
522 unsigned int num_pins = 0;523 unsigned int num_pins = 0;
@@ -563,6 +564,10 @@ void pinmux_disable_setting(const struct pinctrl_setting *setting) · 40 unmodified lines
563 pins[i], desc->name, gname);564 pins[i], desc->name, gname);
564 }565 }
565 }566 }
567
568 if (ops->release_mux)
569 ops->release_mux(pctldev, setting->data.mux.func,
570 setting->data.mux.group);
566}571}
567 572
568#ifdef CONFIG_DEBUG_FS573#ifdef CONFIG_DEBUG_FS
drivers/pinctrl/qcom/Kconfig+23−12
@@ -6,6 +6,7 @@ config PINCTRL_MSM · 5 unmodified lines
6 depends on GPIOLIB6 depends on GPIOLIB
7 # OF for pinconf_generic_dt_node_to_map_group() from GENERIC_PINCONF7 # OF for pinconf_generic_dt_node_to_map_group() from GENERIC_PINCONF
8 depends on OF8 depends on OF
9 default ARCH_QCOM
9 select QCOM_SCM10 select QCOM_SCM
10 select PINMUX11 select PINMUX
11 select GENERIC_PINMUX_FUNCTIONS12 select GENERIC_PINMUX_FUNCTIONS
@@ -49,11 +50,12 @@ config PINCTRL_QCOM_SSBI_PMIC · 37 unmodified lines
49 devices are pm8058 and pm8921.50 devices are pm8058 and pm8921.
50 51
51config PINCTRL_LPASS_LPI52config PINCTRL_LPASS_LPI
52 tristate "Qualcomm Technologies Inc LPASS LPI pin controller driver"53 tristate "Qualcomm LPASS LPI pin controller driver"
53 select PINMUX54 select PINMUX
54 select PINCONF55 select PINCONF
55 select GENERIC_PINCONF56 select GENERIC_PINCONF
56 select GENERIC_PINCTRL_GROUPS57 select GENERIC_PINCTRL_GROUPS
58 depends on PM_CLK
57 depends on GPIOLIB59 depends on GPIOLIB
58 help60 help
59 This is the pinctrl, pinmux, pinconf and gpiolib driver for the61 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
@@ -61,7 +63,7 @@ config PINCTRL_LPASS_LPI · 1 unmodified line
61 (Low Power Island) found on the Qualcomm Technologies Inc SoCs.63 (Low Power Island) found on the Qualcomm Technologies Inc SoCs.
62 64
63config PINCTRL_MILOS_LPASS_LPI65config PINCTRL_MILOS_LPASS_LPI
64 tristate "Qualcomm Technologies Inc Milos LPASS LPI pin controller driver"66 tristate "Qualcomm Milos LPASS LPI pin controller driver"
65 depends on ARM64 || COMPILE_TEST67 depends on ARM64 || COMPILE_TEST
66 depends on PINCTRL_LPASS_LPI68 depends on PINCTRL_LPASS_LPI
67 help69 help
@@ -71,7 +73,7 @@ config PINCTRL_MILOS_LPASS_LPI · 3 unmodified lines
71 platform.73 platform.
72 74
73config PINCTRL_SC7280_LPASS_LPI75config PINCTRL_SC7280_LPASS_LPI
74 tristate "Qualcomm Technologies Inc SC7280 and SM8350 LPASS LPI pin controller driver"76 tristate "Qualcomm SC7280 and SM8350 LPASS LPI pin controller driver"
75 depends on ARM64 || COMPILE_TEST77 depends on ARM64 || COMPILE_TEST
76 depends on PINCTRL_LPASS_LPI78 depends on PINCTRL_LPASS_LPI
77 help79 help
@@ -81,7 +83,7 @@ config PINCTRL_SC7280_LPASS_LPI · 3 unmodified lines
81 and SM8350 platforms.83 and SM8350 platforms.
82 84
83config PINCTRL_SDM660_LPASS_LPI85config PINCTRL_SDM660_LPASS_LPI
84 tristate "Qualcomm Technologies Inc SDM660 LPASS LPI pin controller driver"86 tristate "Qualcomm SDM660 LPASS LPI pin controller driver"
85 depends on GPIOLIB87 depends on GPIOLIB
86 depends on ARM64 || COMPILE_TEST88 depends on ARM64 || COMPILE_TEST
87 depends on PINCTRL_LPASS_LPI89 depends on PINCTRL_LPASS_LPI
@@ -91,7 +93,7 @@ config PINCTRL_SDM660_LPASS_LPI · 3 unmodified lines
91 (Low Power Island) found on the Qualcomm Technologies Inc SDM660 platform.93 (Low Power Island) found on the Qualcomm Technologies Inc SDM660 platform.
92 94
93config PINCTRL_SM4250_LPASS_LPI95config PINCTRL_SM4250_LPASS_LPI
94 tristate "Qualcomm Technologies Inc SM4250 LPASS LPI pin controller driver"96 tristate "Qualcomm SM4250 LPASS LPI pin controller driver"
95 depends on ARM64 || COMPILE_TEST97 depends on ARM64 || COMPILE_TEST
96 depends on PINCTRL_LPASS_LPI98 depends on PINCTRL_LPASS_LPI
97 help99 help
@@ -100,7 +102,7 @@ config PINCTRL_SM4250_LPASS_LPI · 2 unmodified lines
100 (Low Power Island) found on the Qualcomm Technologies Inc SM4250 platform.102 (Low Power Island) found on the Qualcomm Technologies Inc SM4250 platform.
101 103
102config PINCTRL_SDM670_LPASS_LPI104config PINCTRL_SDM670_LPASS_LPI
103 tristate "Qualcomm Technologies Inc SDM670 LPASS LPI pin controller driver"105 tristate "Qualcomm SDM670 LPASS LPI pin controller driver"
104 depends on GPIOLIB106 depends on GPIOLIB
105 depends on ARM64 || COMPILE_TEST107 depends on ARM64 || COMPILE_TEST
106 depends on PINCTRL_LPASS_LPI108 depends on PINCTRL_LPASS_LPI
@@ -110,7 +112,7 @@ config PINCTRL_SDM670_LPASS_LPI · 3 unmodified lines
110 (Low Power Island) found on the Qualcomm Technologies Inc SDM670 platform.112 (Low Power Island) found on the Qualcomm Technologies Inc SDM670 platform.
111 113
112config PINCTRL_SM6115_LPASS_LPI114config PINCTRL_SM6115_LPASS_LPI
113 tristate "Qualcomm Technologies Inc SM6115 LPASS LPI pin controller driver"115 tristate "Qualcomm SM6115 LPASS LPI pin controller driver"
114 depends on ARM64 || COMPILE_TEST116 depends on ARM64 || COMPILE_TEST
115 depends on PINCTRL_LPASS_LPI117 depends on PINCTRL_LPASS_LPI
116 help118 help
@@ -118,8 +120,17 @@ config PINCTRL_SM6115_LPASS_LPI · 1 unmodified line
118 Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI120 Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI
119 (Low Power Island) found on the Qualcomm Technologies Inc SM6115 platform.121 (Low Power Island) found on the Qualcomm Technologies Inc SM6115 platform.
120 122
123config PINCTRL_SM6350_LPASS_LPI
124 tristate "Qualcomm SM6350 LPASS LPI pin controller driver"
125 depends on ARM64 || COMPILE_TEST
126 depends on PINCTRL_LPASS_LPI
127 help
128 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
129 Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI
130 (Low Power Island) found on the Qualcomm Technologies Inc SM6350 platform.
131
121config PINCTRL_SM8250_LPASS_LPI132config PINCTRL_SM8250_LPASS_LPI
122 tristate "Qualcomm Technologies Inc SM8250 LPASS LPI pin controller driver"133 tristate "Qualcomm SM8250 LPASS LPI pin controller driver"
123 depends on ARM64 || COMPILE_TEST134 depends on ARM64 || COMPILE_TEST
124 depends on PINCTRL_LPASS_LPI135 depends on PINCTRL_LPASS_LPI
125 help136 help
@@ -128,7 +139,7 @@ config PINCTRL_SM8250_LPASS_LPI · 2 unmodified lines
128 (Low Power Island) found on the Qualcomm Technologies Inc SM8250 platform.139 (Low Power Island) found on the Qualcomm Technologies Inc SM8250 platform.
129 140
130config PINCTRL_SM8450_LPASS_LPI141config PINCTRL_SM8450_LPASS_LPI
131 tristate "Qualcomm Technologies Inc SM8450 LPASS LPI pin controller driver"142 tristate "Qualcomm SM8450 LPASS LPI pin controller driver"
132 depends on ARM64 || COMPILE_TEST143 depends on ARM64 || COMPILE_TEST
133 depends on PINCTRL_LPASS_LPI144 depends on PINCTRL_LPASS_LPI
134 help145 help
@@ -137,7 +148,7 @@ config PINCTRL_SM8450_LPASS_LPI · 2 unmodified lines
137 (Low Power Island) found on the Qualcomm Technologies Inc SM8450 platform.148 (Low Power Island) found on the Qualcomm Technologies Inc SM8450 platform.
138 149
139config PINCTRL_SC8280XP_LPASS_LPI150config PINCTRL_SC8280XP_LPASS_LPI
140 tristate "Qualcomm Technologies Inc SC8280XP LPASS LPI pin controller driver"151 tristate "Qualcomm SC8280XP LPASS LPI pin controller driver"
141 depends on ARM64 || COMPILE_TEST152 depends on ARM64 || COMPILE_TEST
142 depends on PINCTRL_LPASS_LPI153 depends on PINCTRL_LPASS_LPI
143 help154 help
@@ -146,7 +157,7 @@ config PINCTRL_SC8280XP_LPASS_LPI · 2 unmodified lines
146 (Low Power Island) found on the Qualcomm Technologies Inc SC8280XP platform.157 (Low Power Island) found on the Qualcomm Technologies Inc SC8280XP platform.
147 158
148config PINCTRL_SM8550_LPASS_LPI159config PINCTRL_SM8550_LPASS_LPI
149 tristate "Qualcomm Technologies Inc SM8550 LPASS LPI pin controller driver"160 tristate "Qualcomm SM8550 LPASS LPI pin controller driver"
150 depends on ARM64 || COMPILE_TEST161 depends on ARM64 || COMPILE_TEST
151 depends on PINCTRL_LPASS_LPI162 depends on PINCTRL_LPASS_LPI
152 help163 help
@@ -156,7 +167,7 @@ config PINCTRL_SM8550_LPASS_LPI · 3 unmodified lines
156 platform.167 platform.
157 168
158config PINCTRL_SM8650_LPASS_LPI169config PINCTRL_SM8650_LPASS_LPI
159 tristate "Qualcomm Technologies Inc SM8650 LPASS LPI pin controller driver"170 tristate "Qualcomm SM8650 LPASS LPI pin controller driver"
160 depends on ARM64 || COMPILE_TEST171 depends on ARM64 || COMPILE_TEST
161 depends on PINCTRL_LPASS_LPI172 depends on PINCTRL_LPASS_LPI
162 help173 help
drivers/pinctrl/qcom/Kconfig.msm+131−42
@@ -4,6 +4,7 @@ if PINCTRL_MSM · 3 unmodified lines
4config PINCTRL_APQ80644config PINCTRL_APQ8064
5 tristate "Qualcomm APQ8064 pin controller driver"5 tristate "Qualcomm APQ8064 pin controller driver"
6 depends on ARM || COMPILE_TEST6 depends on ARM || COMPILE_TEST
7 default ARCH_QCOM
7 help8 help
8 This is the pinctrl, pinmux, pinconf and gpiolib driver for the9 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
9 Qualcomm TLMM block found in the Qualcomm APQ8064 platform.10 Qualcomm TLMM block found in the Qualcomm APQ8064 platform.
@@ -11,13 +12,15 @@ config PINCTRL_APQ8064 · 1 unmodified line
11config PINCTRL_APQ808412config PINCTRL_APQ8084
12 tristate "Qualcomm APQ8084 pin controller driver"13 tristate "Qualcomm APQ8084 pin controller driver"
13 depends on ARM || COMPILE_TEST14 depends on ARM || COMPILE_TEST
15 default ARCH_QCOM
14 help16 help
15 This is the pinctrl, pinmux, pinconf and gpiolib driver for the17 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
16 Qualcomm TLMM block found in the Qualcomm APQ8084 platform.18 Qualcomm TLMM block found in the Qualcomm APQ8084 platform.
17 19
18config PINCTRL_ELIZA20config PINCTRL_ELIZA
19 tristate "Qualcomm Technologies Inc Eliza pin controller driver"21 tristate "Qualcomm Eliza pin controller driver"
20 depends on ARM64 || COMPILE_TEST22 depends on ARM64 || COMPILE_TEST
23 default ARCH_QCOM
21 help24 help
22 This is the pinctrl, pinmux, pinconf and gpiolib driver for the25 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
23 Qualcomm Technologies Inc Top Level Mode Multiplexer block (TLMM)26 Qualcomm Technologies Inc Top Level Mode Multiplexer block (TLMM)
@@ -26,8 +29,9 @@ config PINCTRL_ELIZA · 2 unmodified lines
26 If unsure, say N.29 If unsure, say N.
27 30
28config PINCTRL_GLYMUR31config PINCTRL_GLYMUR
29 tristate "Qualcomm Technologies Inc Glymur pin controller driver"32 tristate "Qualcomm Glymur pin controller driver"
30 depends on ARM64 || COMPILE_TEST33 depends on ARM64 || COMPILE_TEST
34 default ARCH_QCOM
31 help35 help
32 This is the pinctrl, pinmux, pinconf and gpiolib driver for the36 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
33 Qualcomm Technologies Inc Top Level Mode Multiplexer block (TLMM)37 Qualcomm Technologies Inc Top Level Mode Multiplexer block (TLMM)
@@ -36,8 +40,9 @@ config PINCTRL_GLYMUR · 2 unmodified lines
36 If unsure, say N.40 If unsure, say N.
37 41
38config PINCTRL_HAWI42config PINCTRL_HAWI
39 tristate "Qualcomm Technologies Inc Hawi pin controller driver"43 tristate "Qualcomm Hawi pin controller driver"
40 depends on ARM64 || COMPILE_TEST44 depends on ARM64 || COMPILE_TEST
45 default ARCH_QCOM
41 help46 help
42 This is the pinctrl, pinmux, pinconf and gpiolib driver for the47 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
43 Qualcomm Technologies Inc Top Level Mode Multiplexer block (TLMM)48 Qualcomm Technologies Inc Top Level Mode Multiplexer block (TLMM)
@@ -48,13 +53,15 @@ config PINCTRL_HAWI · 4 unmodified lines
48config PINCTRL_IPQ401953config PINCTRL_IPQ4019
49 tristate "Qualcomm IPQ4019 pin controller driver"54 tristate "Qualcomm IPQ4019 pin controller driver"
50 depends on ARM || COMPILE_TEST55 depends on ARM || COMPILE_TEST
56 default ARCH_QCOM
51 help57 help
52 This is the pinctrl, pinmux, pinconf and gpiolib driver for the58 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
53 Qualcomm TLMM block found in the Qualcomm IPQ4019 platform.59 Qualcomm TLMM block found in the Qualcomm IPQ4019 platform.
54 60
55config PINCTRL_IPQ501861config PINCTRL_IPQ5018
56 tristate "Qualcomm Technologies, Inc. IPQ5018 pin controller driver"62 tristate "Qualcomm IPQ5018 pin controller driver"
57 depends on ARM64 || COMPILE_TEST63 depends on ARM64 || COMPILE_TEST
64 default ARCH_QCOM
58 help65 help
59 This is the pinctrl, pinmux, pinconf and gpiolib driver for66 This is the pinctrl, pinmux, pinconf and gpiolib driver for
60 the Qualcomm Technologies Inc. TLMM block found on the67 the Qualcomm Technologies Inc. TLMM block found on the
@@ -64,29 +71,33 @@ config PINCTRL_IPQ5018 · 3 unmodified lines
64config PINCTRL_IPQ806471config PINCTRL_IPQ8064
65 tristate "Qualcomm IPQ8064 pin controller driver"72 tristate "Qualcomm IPQ8064 pin controller driver"
66 depends on ARM || COMPILE_TEST73 depends on ARM || COMPILE_TEST
74 default ARCH_QCOM
67 help75 help
68 This is the pinctrl, pinmux, pinconf and gpiolib driver for the76 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
69 Qualcomm TLMM block found in the Qualcomm IPQ8064 platform.77 Qualcomm TLMM block found in the Qualcomm IPQ8064 platform.
70 78
71config PINCTRL_IPQ521079config PINCTRL_IPQ5210
72 tristate "Qualcomm Technologies Inc IPQ5210 pin controller driver"80 tristate "Qualcomm IPQ5210 pin controller driver"
73 depends on ARM64 || COMPILE_TEST81 depends on ARM64 || COMPILE_TEST
82 default ARCH_QCOM
74 help83 help
75 This is the pinctrl, pinmux, pinconf and gpiolib driver for the84 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
76 Qualcomm Technologies Inc TLMM block found on the Qualcomm85 Qualcomm Technologies Inc TLMM block found on the Qualcomm
77 Technologies Inc IPQ5210 platform.86 Technologies Inc IPQ5210 platform.
78 87
79config PINCTRL_IPQ533288config PINCTRL_IPQ5332
80 tristate "Qualcomm Technologies Inc IPQ5332 pin controller driver"89 tristate "Qualcomm IPQ5332 pin controller driver"
81 depends on ARM64 || COMPILE_TEST90 depends on ARM64 || COMPILE_TEST
91 default ARCH_QCOM
82 help92 help
83 This is the pinctrl, pinmux, pinconf and gpiolib driver for the93 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
84 Qualcomm Technologies Inc TLMM block found on the Qualcomm94 Qualcomm Technologies Inc TLMM block found on the Qualcomm
85 Technologies Inc IPQ5332 platform.95 Technologies Inc IPQ5332 platform.
86 96
87config PINCTRL_IPQ542497config PINCTRL_IPQ5424
88 tristate "Qualcomm Technologies, Inc. IPQ5424 pin controller driver"98 tristate "Qualcomm IPQ5424 pin controller driver"
89 depends on ARM64 || COMPILE_TEST99 depends on ARM64 || COMPILE_TEST
100 default ARCH_QCOM
90 help101 help
91 This is the pinctrl, pinmux, pinconf and gpiolib driver for102 This is the pinctrl, pinmux, pinconf and gpiolib driver for
92 the Qualcomm Technologies Inc. TLMM block found on the103 the Qualcomm Technologies Inc. TLMM block found on the
@@ -94,8 +105,9 @@ config PINCTRL_IPQ5424 · 1 unmodified line
94 IPQ5424.105 IPQ5424.
95 106
96config PINCTRL_IPQ8074107config PINCTRL_IPQ8074
97 tristate "Qualcomm Technologies, Inc. IPQ8074 pin controller driver"108 tristate "Qualcomm IPQ8074 pin controller driver"
98 depends on ARM64 || COMPILE_TEST109 depends on ARM64 || COMPILE_TEST
110 default ARCH_QCOM
99 help111 help
100 This is the pinctrl, pinmux, pinconf and gpiolib driver for112 This is the pinctrl, pinmux, pinconf and gpiolib driver for
101 the Qualcomm Technologies Inc. TLMM block found on the113 the Qualcomm Technologies Inc. TLMM block found on the
@@ -103,8 +115,9 @@ config PINCTRL_IPQ8074 · 1 unmodified line
103 IPQ8074.115 IPQ8074.
104 116
105config PINCTRL_IPQ6018117config PINCTRL_IPQ6018
106 tristate "Qualcomm Technologies, Inc. IPQ6018 pin controller driver"118 tristate "Qualcomm IPQ6018 pin controller driver"
107 depends on ARM64 || COMPILE_TEST119 depends on ARM64 || COMPILE_TEST
120 default ARCH_QCOM
108 help121 help
109 This is the pinctrl, pinmux, pinconf and gpiolib driver for122 This is the pinctrl, pinmux, pinconf and gpiolib driver for
110 the Qualcomm Technologies Inc. TLMM block found on the123 the Qualcomm Technologies Inc. TLMM block found on the
@@ -112,17 +125,29 @@ config PINCTRL_IPQ6018 · 1 unmodified line
112 IPQ6018.125 IPQ6018.
113 126
114config PINCTRL_IPQ9574127config PINCTRL_IPQ9574
115 tristate "Qualcomm Technologies, Inc. IPQ9574 pin controller driver"128 tristate "Qualcomm IPQ9574 pin controller driver"
116 depends on ARM64 || COMPILE_TEST129 depends on ARM64 || COMPILE_TEST
130 default ARCH_QCOM
117 help131 help
118 This is the pinctrl, pinmux, pinconf and gpiolib driver for132 This is the pinctrl, pinmux, pinconf and gpiolib driver for
119 the Qualcomm Technologies Inc. TLMM block found on the133 the Qualcomm Technologies Inc. TLMM block found on the
120 Qualcomm Technologies Inc. IPQ9574 platform. Select this for134 Qualcomm Technologies Inc. IPQ9574 platform. Select this for
121 IPQ9574.135 IPQ9574.
122 136
137config PINCTRL_IPQ9650
138 tristate "Qualcomm IPQ9650 pin controller driver"
139 depends on ARM64 || COMPILE_TEST
140 default ARCH_QCOM
141 help
142 This is the pinctrl, pinmux, pinconf and gpiolib driver for
143 the Qualcomm Technologies Inc. TLMM block found on the
144 Qualcomm Technologies Inc. IPQ9650 platform. Select this for
145 IPQ9650.
146
123config PINCTRL_KAANAPALI147config PINCTRL_KAANAPALI
124 tristate "Qualcomm Technologies Inc Kaanapali pin controller driver"148 tristate "Qualcomm Kaanapali pin controller driver"
125 depends on ARM64 || COMPILE_TEST149 depends on ARM64 || COMPILE_TEST
150 default ARCH_QCOM
126 help151 help
127 This is the pinctrl, pinmux, pinconf and gpiolib driver for the152 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
128 Qualcomm Technologies Inc TLMM block found on the Qualcomm153 Qualcomm Technologies Inc TLMM block found on the Qualcomm
@@ -131,6 +156,7 @@ config PINCTRL_KAANAPALI · 2 unmodified lines
131config PINCTRL_MSM8226156config PINCTRL_MSM8226
132 tristate "Qualcomm 8226 pin controller driver"157 tristate "Qualcomm 8226 pin controller driver"
133 depends on ARM || COMPILE_TEST158 depends on ARM || COMPILE_TEST
159 default ARCH_QCOM
134 help160 help
135 This is the pinctrl, pinmux, pinconf and gpiolib driver for the161 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
136 Qualcomm Technologies Inc TLMM block found on the Qualcomm162 Qualcomm Technologies Inc TLMM block found on the Qualcomm
@@ -139,6 +165,7 @@ config PINCTRL_MSM8226 · 2 unmodified lines
139config PINCTRL_MSM8660165config PINCTRL_MSM8660
140 tristate "Qualcomm 8660 pin controller driver"166 tristate "Qualcomm 8660 pin controller driver"
141 depends on ARM || COMPILE_TEST167 depends on ARM || COMPILE_TEST
168 default ARCH_QCOM
142 help169 help
143 This is the pinctrl, pinmux, pinconf and gpiolib driver for the170 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
144 Qualcomm TLMM block found in the Qualcomm 8660 platform.171 Qualcomm TLMM block found in the Qualcomm 8660 platform.
@@ -146,12 +173,14 @@ config PINCTRL_MSM8660 · 1 unmodified line
146config PINCTRL_MSM8960173config PINCTRL_MSM8960
147 tristate "Qualcomm 8960 pin controller driver"174 tristate "Qualcomm 8960 pin controller driver"
148 depends on ARM || COMPILE_TEST175 depends on ARM || COMPILE_TEST
176 default ARCH_QCOM
149 help177 help
150 This is the pinctrl, pinmux, pinconf and gpiolib driver for the178 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
151 Qualcomm TLMM block found in the Qualcomm 8960 platform.179 Qualcomm TLMM block found in the Qualcomm 8960 platform.
152 180
153config PINCTRL_MDM9607181config PINCTRL_MDM9607
154 tristate "Qualcomm 9607 pin controller driver"182 tristate "Qualcomm 9607 pin controller driver"
183 default ARCH_QCOM if ARM
155 help184 help
156 This is the pinctrl, pinmux, pinconf and gpiolib driver for the185 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
157 Qualcomm TLMM block found in the Qualcomm 9607 platform.186 Qualcomm TLMM block found in the Qualcomm 9607 platform.
@@ -159,6 +188,7 @@ config PINCTRL_MDM9607 · 1 unmodified line
159config PINCTRL_MDM9615188config PINCTRL_MDM9615
160 tristate "Qualcomm 9615 pin controller driver"189 tristate "Qualcomm 9615 pin controller driver"
161 depends on ARM || COMPILE_TEST190 depends on ARM || COMPILE_TEST
191 default ARCH_QCOM
162 help192 help
163 This is the pinctrl, pinmux, pinconf and gpiolib driver for the193 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
164 Qualcomm TLMM block found in the Qualcomm 9615 platform.194 Qualcomm TLMM block found in the Qualcomm 9615 platform.
@@ -166,6 +196,7 @@ config PINCTRL_MDM9615 · 1 unmodified line
166config PINCTRL_MSM8X74196config PINCTRL_MSM8X74
167 tristate "Qualcomm 8x74 pin controller driver"197 tristate "Qualcomm 8x74 pin controller driver"
168 depends on ARM || COMPILE_TEST198 depends on ARM || COMPILE_TEST
199 default ARCH_QCOM
169 help200 help
170 This is the pinctrl, pinmux, pinconf and gpiolib driver for the201 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
171 Qualcomm TLMM block found in the Qualcomm 8974 platform.202 Qualcomm TLMM block found in the Qualcomm 8974 platform.
@@ -173,12 +204,14 @@ config PINCTRL_MSM8X74 · 1 unmodified line
173config PINCTRL_MSM8909204config PINCTRL_MSM8909
174 tristate "Qualcomm 8909 pin controller driver"205 tristate "Qualcomm 8909 pin controller driver"
175 depends on ARM || COMPILE_TEST206 depends on ARM || COMPILE_TEST
207 default ARCH_QCOM
176 help208 help
177 This is the pinctrl, pinmux, pinconf and gpiolib driver for the209 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
178 Qualcomm TLMM block found on the Qualcomm MSM8909 platform.210 Qualcomm TLMM block found on the Qualcomm MSM8909 platform.
179 211
180config PINCTRL_MSM8916212config PINCTRL_MSM8916
181 tristate "Qualcomm 8916 pin controller driver"213 tristate "Qualcomm 8916 pin controller driver"
214 default ARCH_QCOM
182 help215 help
183 This is the pinctrl, pinmux, pinconf and gpiolib driver for the216 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
184 Qualcomm TLMM block found on the Qualcomm 8916 platform.217 Qualcomm TLMM block found on the Qualcomm 8916 platform.
@@ -192,6 +225,7 @@ config PINCTRL_MSM8917 · 7 unmodified lines
192config PINCTRL_MSM8953225config PINCTRL_MSM8953
193 tristate "Qualcomm 8953 pin controller driver"226 tristate "Qualcomm 8953 pin controller driver"
194 depends on ARM64 || COMPILE_TEST227 depends on ARM64 || COMPILE_TEST
228 default ARCH_QCOM
195 help229 help
196 This is the pinctrl, pinmux, pinconf and gpiolib driver for the230 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
197 Qualcomm TLMM block found on the Qualcomm MSM8953 platform.231 Qualcomm TLMM block found on the Qualcomm MSM8953 platform.
@@ -201,6 +235,7 @@ config PINCTRL_MSM8953 · 3 unmodified lines
201config PINCTRL_MSM8976235config PINCTRL_MSM8976
202 tristate "Qualcomm 8976 pin controller driver"236 tristate "Qualcomm 8976 pin controller driver"
203 depends on ARM64 || COMPILE_TEST237 depends on ARM64 || COMPILE_TEST
238 default ARCH_QCOM
204 help239 help
205 This is the pinctrl, pinmux, pinconf and gpiolib driver for the240 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
206 Qualcomm TLMM block found on the Qualcomm MSM8976 platform.241 Qualcomm TLMM block found on the Qualcomm MSM8976 platform.
@@ -210,6 +245,7 @@ config PINCTRL_MSM8976 · 3 unmodified lines
210config PINCTRL_MSM8994245config PINCTRL_MSM8994
211 tristate "Qualcomm 8994 pin controller driver"246 tristate "Qualcomm 8994 pin controller driver"
212 depends on ARM64 || COMPILE_TEST247 depends on ARM64 || COMPILE_TEST
248 default ARCH_QCOM
213 help249 help
214 This is the pinctrl, pinmux, pinconf and gpiolib driver for the250 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
215 Qualcomm TLMM block found in the Qualcomm 8994 platform. The251 Qualcomm TLMM block found in the Qualcomm 8994 platform. The
@@ -218,6 +254,7 @@ config PINCTRL_MSM8994 · 2 unmodified lines
218config PINCTRL_MSM8996254config PINCTRL_MSM8996
219 tristate "Qualcomm MSM8996 pin controller driver"255 tristate "Qualcomm MSM8996 pin controller driver"
220 depends on ARM64 || COMPILE_TEST256 depends on ARM64 || COMPILE_TEST
257 default ARCH_QCOM
221 help258 help
222 This is the pinctrl, pinmux, pinconf and gpiolib driver for the259 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
223 Qualcomm TLMM block found in the Qualcomm MSM8996 platform.260 Qualcomm TLMM block found in the Qualcomm MSM8996 platform.
@@ -225,13 +262,23 @@ config PINCTRL_MSM8996 · 1 unmodified line
225config PINCTRL_MSM8998262config PINCTRL_MSM8998
226 tristate "Qualcomm MSM8998 pin controller driver"263 tristate "Qualcomm MSM8998 pin controller driver"
227 depends on ARM64 || COMPILE_TEST264 depends on ARM64 || COMPILE_TEST
265 default ARCH_QCOM
228 help266 help
229 This is the pinctrl, pinmux, pinconf and gpiolib driver for the267 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
230 Qualcomm TLMM block found in the Qualcomm MSM8998 platform.268 Qualcomm TLMM block found in the Qualcomm MSM8998 platform.
231 269
270config PINCTRL_NORD
271 tristate "Qualcomm Nord pin controller driver"
272 depends on ARM64 || COMPILE_TEST
273 default ARCH_QCOM
274 help
275 This is the pinctrl, pinmux and pinconf driver for the Qualcomm
276 TLMM block found on the Qualcomm NORD platforms.
277
232config PINCTRL_QCM2290278config PINCTRL_QCM2290
233 tristate "Qualcomm QCM2290 pin controller driver"279 tristate "Qualcomm QCM2290 pin controller driver"
234 depends on ARM64 || COMPILE_TEST280 depends on ARM64 || COMPILE_TEST
281 default ARCH_QCOM
235 help282 help
236 This is the pinctrl, pinmux, pinconf and gpiolib driver for the283 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
237 TLMM block found in the Qualcomm QCM2290 platform.284 TLMM block found in the Qualcomm QCM2290 platform.
@@ -239,48 +286,54 @@ config PINCTRL_QCM2290 · 1 unmodified line
239config PINCTRL_QCS404286config PINCTRL_QCS404
240 tristate "Qualcomm QCS404 pin controller driver"287 tristate "Qualcomm QCS404 pin controller driver"
241 depends on ARM64 || COMPILE_TEST288 depends on ARM64 || COMPILE_TEST
289 default ARCH_QCOM
242 help290 help
243 This is the pinctrl, pinmux, pinconf and gpiolib driver for the291 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
244 TLMM block found in the Qualcomm QCS404 platform.292 TLMM block found in the Qualcomm QCS404 platform.
245 293
246config PINCTRL_QCS615294config PINCTRL_QCS615
247 tristate "Qualcomm Technologies QCS615 pin controller driver"295 tristate "Qualcomm QCS615 pin controller driver"
248 depends on ARM64 || COMPILE_TEST296 depends on ARM64 || COMPILE_TEST
297 default ARCH_QCOM
249 help298 help
250 This is the pinctrl, pinmux, pinconf and gpiolib driver for the299 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
251 TLMM block found on the Qualcomm QCS615 platform.300 TLMM block found on the Qualcomm QCS615 platform.
252 301
253config PINCTRL_QCS8300302config PINCTRL_QCS8300
254 tristate "Qualcomm Technologies QCS8300 pin controller driver"303 tristate "Qualcomm QCS8300 pin controller driver"
255 depends on ARM64 || COMPILE_TEST304 depends on ARM64 || COMPILE_TEST
305 default ARCH_QCOM
256 help306 help
257 This is the pinctrl, pinmux and pinconf driver for the Qualcomm307 This is the pinctrl, pinmux and pinconf driver for the Qualcomm
258 TLMM block found on the Qualcomm QCS8300 platform.308 TLMM block found on the Qualcomm QCS8300 platform.
259 309
260config PINCTRL_QDF2XXX310config PINCTRL_QDF2XXX
261 tristate "Qualcomm Technologies QDF2xxx pin controller driver"311 tristate "Qualcomm QDF2xxx pin controller driver"
262 depends on ACPI312 depends on ACPI
313 default ARCH_QCOM if ARM64
263 help314 help
264 This is the GPIO driver for the TLMM block found on the315 This is the GPIO driver for the TLMM block found on the
265 Qualcomm Technologies QDF2xxx SOCs.316 Qualcomm Technologies QDF2xxx SOCs.
266 317
267config PINCTRL_QDU1000318config PINCTRL_QDU1000
268 tristate "Qualcomm Technologies Inc QDU1000/QRU1000 pin controller driver"319 tristate "Qualcomm QDU1000/QRU1000 pin controller driver"
269 depends on ARM64 || COMPILE_TEST320 depends on ARM64 || COMPILE_TEST
321 default ARCH_QCOM
270 help322 help
271 This is the pinctrl, pinmux, pinconf, and gpiolib driver for the323 This is the pinctrl, pinmux, pinconf, and gpiolib driver for the
272 Qualcomm Technologies Inc TLMM block found on the Qualcomm324 Qualcomm Technologies Inc TLMM block found on the Qualcomm
273 Technologies Inc QDU1000 and QRU1000 platforms.325 Technologies Inc QDU1000 and QRU1000 platforms.
274 326
275config PINCTRL_SA8775P327config PINCTRL_SA8775P
276 tristate "Qualcomm Technologies Inc SA8775P pin controller driver"328 tristate "Qualcomm SA8775P pin controller driver"
277 depends on ARM64 || COMPILE_TEST329 depends on ARM64 || COMPILE_TEST
330 default ARCH_QCOM
278 help331 help
279 This is the pinctrl, pinmux and pinconf driver for the Qualcomm332 This is the pinctrl, pinmux and pinconf driver for the Qualcomm
280 TLMM block found on the Qualcomm SA8775P platforms.333 TLMM block found on the Qualcomm SA8775P platforms.
281 334
282config PINCTRL_SAR2130P335config PINCTRL_SAR2130P
283 tristate "Qualcomm Technologies Inc SAR2130P pin controller driver"336 tristate "Qualcomm SAR2130P pin controller driver"
284 depends on ARM64 || COMPILE_TEST337 depends on ARM64 || COMPILE_TEST
285 help338 help
286 This is the pinctrl, pinmux, pinconf and gpiolib driver for the339 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
@@ -288,202 +341,238 @@ config PINCTRL_SAR2130P · 1 unmodified line
288 Technologies Inc SAR2130P platform.341 Technologies Inc SAR2130P platform.
289 342
290config PINCTRL_SC7180343config PINCTRL_SC7180
291 tristate "Qualcomm Technologies Inc SC7180 pin controller driver"344 tristate "Qualcomm SC7180 pin controller driver"
292 depends on ARM64 || COMPILE_TEST345 depends on ARM64 || COMPILE_TEST
346 default ARCH_QCOM
293 help347 help
294 This is the pinctrl, pinmux, pinconf and gpiolib driver for the348 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
295 Qualcomm Technologies Inc TLMM block found on the Qualcomm349 Qualcomm Technologies Inc TLMM block found on the Qualcomm
296 Technologies Inc SC7180 platform.350 Technologies Inc SC7180 platform.
297 351
298config PINCTRL_SC7280352config PINCTRL_SC7280
299 tristate "Qualcomm Technologies Inc SC7280 pin controller driver"353 tristate "Qualcomm SC7280 pin controller driver"
300 depends on ARM64 || COMPILE_TEST354 depends on ARM64 || COMPILE_TEST
355 default ARCH_QCOM
301 help356 help
302 This is the pinctrl, pinmux, pinconf and gpiolib driver for the357 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
303 Qualcomm Technologies Inc TLMM block found on the Qualcomm358 Qualcomm Technologies Inc TLMM block found on the Qualcomm
304 Technologies Inc SC7280 platform.359 Technologies Inc SC7280 platform.
305 360
306config PINCTRL_SC8180X361config PINCTRL_SC8180X
307 tristate "Qualcomm Technologies Inc SC8180x pin controller driver"362 tristate "Qualcomm SC8180x pin controller driver"
308 depends on (OF || ACPI)363 depends on (OF || ACPI)
309 depends on ARM64 || COMPILE_TEST364 depends on ARM64 || COMPILE_TEST
365 default ARCH_QCOM
310 help366 help
311 This is the pinctrl, pinmux, pinconf and gpiolib driver for the367 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
312 Qualcomm Technologies Inc TLMM block found on the Qualcomm368 Qualcomm Technologies Inc TLMM block found on the Qualcomm
313 Technologies Inc SC8180x platform.369 Technologies Inc SC8180x platform.
314 370
315config PINCTRL_SC8280XP371config PINCTRL_SC8280XP
316 tristate "Qualcomm Technologies Inc SC8280xp pin controller driver"372 tristate "Qualcomm SC8280xp pin controller driver"
317 depends on ARM64 || COMPILE_TEST373 depends on ARM64 || COMPILE_TEST
374 default ARCH_QCOM
318 help375 help
319 This is the pinctrl, pinmux, pinconf and gpiolib driver for the376 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
320 Qualcomm Technologies Inc TLMM block found on the Qualcomm377 Qualcomm Technologies Inc TLMM block found on the Qualcomm
321 Technologies Inc SC8280xp platform.378 Technologies Inc SC8280xp platform.
322 379
323config PINCTRL_SDM660380config PINCTRL_SDM660
324 tristate "Qualcomm Technologies Inc SDM660 pin controller driver"381 tristate "Qualcomm SDM660 pin controller driver"
325 depends on ARM64 || COMPILE_TEST382 depends on ARM64 || COMPILE_TEST
383 default ARCH_QCOM
326 help384 help
327 This is the pinctrl, pinmux, pinconf and gpiolib driver for the385 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
328 Qualcomm Technologies Inc TLMM block found on the Qualcomm386 Qualcomm Technologies Inc TLMM block found on the Qualcomm
329 Technologies Inc SDM660 platform.387 Technologies Inc SDM660 platform.
330 388
331config PINCTRL_SDM670389config PINCTRL_SDM670
332 tristate "Qualcomm Technologies Inc SDM670 pin controller driver"390 tristate "Qualcomm SDM670 pin controller driver"
333 depends on ARM64 || COMPILE_TEST391 depends on ARM64 || COMPILE_TEST
392 default ARCH_QCOM
334 help393 help
335 This is the pinctrl, pinmux, pinconf and gpiolib driver for the394 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
336 Qualcomm Technologies Inc TLMM block found on the Qualcomm395 Qualcomm Technologies Inc TLMM block found on the Qualcomm
337 Technologies Inc SDM670 platform.396 Technologies Inc SDM670 platform.
338 397
339config PINCTRL_SDM845398config PINCTRL_SDM845
340 tristate "Qualcomm Technologies Inc SDM845 pin controller driver"399 tristate "Qualcomm SDM845 pin controller driver"
341 depends on (OF || ACPI)400 depends on (OF || ACPI)
342 depends on ARM64 || COMPILE_TEST401 depends on ARM64 || COMPILE_TEST
402 default ARCH_QCOM
343 help403 help
344 This is the pinctrl, pinmux, pinconf and gpiolib driver for the404 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
345 Qualcomm Technologies Inc TLMM block found on the Qualcomm405 Qualcomm Technologies Inc TLMM block found on the Qualcomm
346 Technologies Inc SDM845 platform.406 Technologies Inc SDM845 platform.
347 407
348config PINCTRL_SDX55408config PINCTRL_SDX55
349 tristate "Qualcomm Technologies Inc SDX55 pin controller driver"409 tristate "Qualcomm SDX55 pin controller driver"
350 depends on ARM || COMPILE_TEST410 depends on ARM || COMPILE_TEST
411 default ARCH_QCOM
351 help412 help
352 This is the pinctrl, pinmux, pinconf and gpiolib driver for the413 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
353 Qualcomm Technologies Inc TLMM block found on the Qualcomm414 Qualcomm Technologies Inc TLMM block found on the Qualcomm
354 Technologies Inc SDX55 platform.415 Technologies Inc SDX55 platform.
355 416
356config PINCTRL_SDX65417config PINCTRL_SDX65
357 tristate "Qualcomm Technologies Inc SDX65 pin controller driver"418 tristate "Qualcomm SDX65 pin controller driver"
358 depends on ARM || COMPILE_TEST419 depends on ARM || COMPILE_TEST
420 default ARCH_QCOM
359 help421 help
360 This is the pinctrl, pinmux, pinconf and gpiolib driver for the422 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
361 Qualcomm Technologies Inc TLMM block found on the Qualcomm423 Qualcomm Technologies Inc TLMM block found on the Qualcomm
362 Technologies Inc SDX65 platform.424 Technologies Inc SDX65 platform.
363 425
364config PINCTRL_SDX75426config PINCTRL_SDX75
365 tristate "Qualcomm Technologies Inc SDX75 pin controller driver"427 tristate "Qualcomm SDX75 pin controller driver"
366 depends on ARM64 || COMPILE_TEST428 depends on ARM64 || COMPILE_TEST
429 default ARCH_QCOM
367 help430 help
368 This is the pinctrl, pinmux, pinconf and gpiolib driver for the431 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
369 Qualcomm Technologies Inc TLMM block found on the Qualcomm432 Qualcomm Technologies Inc TLMM block found on the Qualcomm
370 Technologies Inc SDX75 platform.433 Technologies Inc SDX75 platform.
371 434
435config PINCTRL_SHIKRA
436 tristate "Qualcomm Shikra pin controller driver"
437 depends on ARM64 || COMPILE_TEST
438 default ARCH_QCOM
439 help
440 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
441 Qualcomm Technologies Inc Top Level Mode Multiplexer block (TLMM)
442 found on the Qualcomm Technologies Inc Shikra platform.
443 Say Y here to compile statically, or M here to compile it as a module.
444 If unsure, say N.
445
372config PINCTRL_SM4450446config PINCTRL_SM4450
373 tristate "Qualcomm Technologies Inc SM4450 pin controller driver"447 tristate "Qualcomm SM4450 pin controller driver"
374 depends on ARM64 || COMPILE_TEST448 depends on ARM64 || COMPILE_TEST
449 default ARCH_QCOM
375 help450 help
376 This is the pinctrl, pinmux, pinconf and gpiolib driver for the451 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
377 Qualcomm Technologies Inc TLMM block found on the Qualcomm452 Qualcomm Technologies Inc TLMM block found on the Qualcomm
378 Technologies Inc SM4450 platform.453 Technologies Inc SM4450 platform.
379 454
380config PINCTRL_SM6115455config PINCTRL_SM6115
381 tristate "Qualcomm Technologies Inc SM6115,SM4250 pin controller driver"456 tristate "Qualcomm SM6115,SM4250 pin controller driver"
382 depends on ARM64 || COMPILE_TEST457 depends on ARM64 || COMPILE_TEST
458 default ARCH_QCOM
383 help459 help
384 This is the pinctrl, pinmux, pinconf and gpiolib driver for the460 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
385 Qualcomm Technologies Inc TLMM block found on the Qualcomm461 Qualcomm Technologies Inc TLMM block found on the Qualcomm
386 Technologies Inc SM6115 and SM4250 platforms.462 Technologies Inc SM6115 and SM4250 platforms.
387 463
388config PINCTRL_SM6125464config PINCTRL_SM6125
389 tristate "Qualcomm Technologies Inc SM6125 pin controller driver"465 tristate "Qualcomm SM6125 pin controller driver"
390 depends on ARM64 || COMPILE_TEST466 depends on ARM64 || COMPILE_TEST
467 default ARCH_QCOM
391 help468 help
392 This is the pinctrl, pinmux, pinconf and gpiolib driver for the469 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
393 Qualcomm Technologies Inc TLMM block found on the Qualcomm470 Qualcomm Technologies Inc TLMM block found on the Qualcomm
394 Technologies Inc SM6125 platform.471 Technologies Inc SM6125 platform.
395 472
396config PINCTRL_SM6350473config PINCTRL_SM6350
397 tristate "Qualcomm Technologies Inc SM6350 pin controller driver"474 tristate "Qualcomm SM6350 pin controller driver"
398 depends on ARM64 || COMPILE_TEST475 depends on ARM64 || COMPILE_TEST
476 default ARCH_QCOM
399 help477 help
400 This is the pinctrl, pinmux, pinconf and gpiolib driver for the478 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
401 Qualcomm Technologies Inc TLMM block found on the Qualcomm479 Qualcomm Technologies Inc TLMM block found on the Qualcomm
402 Technologies Inc SM6350 platform.480 Technologies Inc SM6350 platform.
403 481
404config PINCTRL_SM6375482config PINCTRL_SM6375
405 tristate "Qualcomm Technologies Inc SM6375 pin controller driver"483 tristate "Qualcomm SM6375 pin controller driver"
406 depends on ARM64 || COMPILE_TEST484 depends on ARM64 || COMPILE_TEST
485 default ARCH_QCOM
407 help486 help
408 This is the pinctrl, pinmux, pinconf and gpiolib driver for the487 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
409 Qualcomm Technologies Inc TLMM block found on the Qualcomm488 Qualcomm Technologies Inc TLMM block found on the Qualcomm
410 Technologies Inc SM6375 platform.489 Technologies Inc SM6375 platform.
411 490
412config PINCTRL_SM7150491config PINCTRL_SM7150
413 tristate "Qualcomm Technologies Inc SM7150 pin controller driver"492 tristate "Qualcomm SM7150 pin controller driver"
414 depends on ARM64 || COMPILE_TEST493 depends on ARM64 || COMPILE_TEST
494 default ARCH_QCOM
415 help495 help
416 This is the pinctrl, pinmux, pinconf and gpiolib driver for the496 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
417 Qualcomm Technologies Inc TLMM block found on the Qualcomm497 Qualcomm Technologies Inc TLMM block found on the Qualcomm
418 Technologies Inc SM7150 platform.498 Technologies Inc SM7150 platform.
419 499
420config PINCTRL_MILOS500config PINCTRL_MILOS
421 tristate "Qualcomm Technologies Inc Milos pin controller driver"501 tristate "Qualcomm Milos pin controller driver"
422 depends on ARM64 || COMPILE_TEST502 depends on ARM64 || COMPILE_TEST
503 default ARCH_QCOM
423 help504 help
424 This is the pinctrl, pinmux, pinconf and gpiolib driver for the505 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
425 Qualcomm Technologies Inc TLMM block found on the Qualcomm506 Qualcomm Technologies Inc TLMM block found on the Qualcomm
426 Technologies Inc Milos platform.507 Technologies Inc Milos platform.
427 508
428config PINCTRL_SM8150509config PINCTRL_SM8150
429 tristate "Qualcomm Technologies Inc SM8150 pin controller driver"510 tristate "Qualcomm SM8150 pin controller driver"
430 depends on ARM64 || COMPILE_TEST511 depends on ARM64 || COMPILE_TEST
512 default ARCH_QCOM
431 help513 help
432 This is the pinctrl, pinmux, pinconf and gpiolib driver for the514 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
433 Qualcomm Technologies Inc TLMM block found on the Qualcomm515 Qualcomm Technologies Inc TLMM block found on the Qualcomm
434 Technologies Inc SM8150 platform.516 Technologies Inc SM8150 platform.
435 517
436config PINCTRL_SM8250518config PINCTRL_SM8250
437 tristate "Qualcomm Technologies Inc SM8250 pin controller driver"519 tristate "Qualcomm SM8250 pin controller driver"
438 depends on ARM64 || COMPILE_TEST520 depends on ARM64 || COMPILE_TEST
521 default ARCH_QCOM
439 help522 help
440 This is the pinctrl, pinmux, pinconf and gpiolib driver for the523 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
441 Qualcomm Technologies Inc TLMM block found on the Qualcomm524 Qualcomm Technologies Inc TLMM block found on the Qualcomm
442 Technologies Inc SM8250 platform.525 Technologies Inc SM8250 platform.
443 526
444config PINCTRL_SM8350527config PINCTRL_SM8350
445 tristate "Qualcomm Technologies Inc SM8350 pin controller driver"528 tristate "Qualcomm SM8350 pin controller driver"
446 depends on ARM64 || COMPILE_TEST529 depends on ARM64 || COMPILE_TEST
530 default ARCH_QCOM
447 help531 help
448 This is the pinctrl, pinmux, pinconf and gpiolib driver for the532 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
449 Qualcomm Technologies Inc TLMM block found on the Qualcomm533 Qualcomm Technologies Inc TLMM block found on the Qualcomm
450 Technologies Inc SM8350 platform.534 Technologies Inc SM8350 platform.
451 535
452config PINCTRL_SM8450536config PINCTRL_SM8450
453 tristate "Qualcomm Technologies Inc SM8450 pin controller driver"537 tristate "Qualcomm SM8450 pin controller driver"
454 depends on ARM64 || COMPILE_TEST538 depends on ARM64 || COMPILE_TEST
539 default ARCH_QCOM
455 help540 help
456 This is the pinctrl, pinmux, pinconf and gpiolib driver for the541 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
457 Qualcomm Technologies Inc TLMM block found on the Qualcomm542 Qualcomm Technologies Inc TLMM block found on the Qualcomm
458 Technologies Inc SM8450 platform.543 Technologies Inc SM8450 platform.
459 544
460config PINCTRL_SM8550545config PINCTRL_SM8550
461 tristate "Qualcomm Technologies Inc SM8550 pin controller driver"546 tristate "Qualcomm SM8550 pin controller driver"
462 depends on ARM64 || COMPILE_TEST547 depends on ARM64 || COMPILE_TEST
548 default ARCH_QCOM
463 help549 help
464 This is the pinctrl, pinmux, pinconf and gpiolib driver for the550 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
465 Qualcomm Technologies Inc TLMM block found on the Qualcomm551 Qualcomm Technologies Inc TLMM block found on the Qualcomm
466 Technologies Inc SM8550 platform.552 Technologies Inc SM8550 platform.
467 553
468config PINCTRL_SM8650554config PINCTRL_SM8650
469 tristate "Qualcomm Technologies Inc SM8650 pin controller driver"555 tristate "Qualcomm SM8650 pin controller driver"
470 depends on ARM64 || COMPILE_TEST556 depends on ARM64 || COMPILE_TEST
557 default ARCH_QCOM
471 help558 help
472 This is the pinctrl, pinmux, pinconf and gpiolib driver for the559 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
473 Qualcomm Technologies Inc TLMM block found on the Qualcomm560 Qualcomm Technologies Inc TLMM block found on the Qualcomm
474 Technologies Inc SM8650 platform.561 Technologies Inc SM8650 platform.
475 562
476config PINCTRL_SM8750563config PINCTRL_SM8750
477 tristate "Qualcomm Technologies Inc SM8750 pin controller driver"564 tristate "Qualcomm SM8750 pin controller driver"
478 depends on ARM64 || COMPILE_TEST565 depends on ARM64 || COMPILE_TEST
566 default ARCH_QCOM
479 help567 help
480 This is the pinctrl, pinmux, pinconf and gpiolib driver for the568 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
481 Qualcomm Technologies Inc TLMM block found on the Qualcomm569 Qualcomm Technologies Inc TLMM block found on the Qualcomm
482 Technologies Inc SM8750 platform.570 Technologies Inc SM8750 platform.
483 571
484config PINCTRL_X1E80100572config PINCTRL_X1E80100
485 tristate "Qualcomm Technologies Inc X1E80100 pin controller driver"573 tristate "Qualcomm X1E80100 pin controller driver"
486 depends on ARM64 || COMPILE_TEST574 depends on ARM64 || COMPILE_TEST
575 default ARCH_QCOM
487 help576 help
488 This is the pinctrl, pinmux, pinconf and gpiolib driver for the577 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
489 Qualcomm Technologies Inc Top Level Mode Multiplexer block (TLMM)578 Qualcomm Technologies Inc Top Level Mode Multiplexer block (TLMM)
drivers/pinctrl/qcom/Makefile+4−0
@@ -15,6 +15,7 @@ obj-$(CONFIG_PINCTRL_IPQ5424) += pinctrl-ipq5424.o · 14 unmodified lines
15obj-$(CONFIG_PINCTRL_IPQ8074) += pinctrl-ipq8074.o15obj-$(CONFIG_PINCTRL_IPQ8074) += pinctrl-ipq8074.o
16obj-$(CONFIG_PINCTRL_IPQ6018) += pinctrl-ipq6018.o16obj-$(CONFIG_PINCTRL_IPQ6018) += pinctrl-ipq6018.o
17obj-$(CONFIG_PINCTRL_IPQ9574) += pinctrl-ipq9574.o17obj-$(CONFIG_PINCTRL_IPQ9574) += pinctrl-ipq9574.o
18obj-$(CONFIG_PINCTRL_IPQ9650) += pinctrl-ipq9650.o
18obj-$(CONFIG_PINCTRL_KAANAPALI) += pinctrl-kaanapali.o19obj-$(CONFIG_PINCTRL_KAANAPALI) += pinctrl-kaanapali.o
19obj-$(CONFIG_PINCTRL_MSM8226) += pinctrl-msm8226.o20obj-$(CONFIG_PINCTRL_MSM8226) += pinctrl-msm8226.o
20obj-$(CONFIG_PINCTRL_MSM8660) += pinctrl-msm8660.o21obj-$(CONFIG_PINCTRL_MSM8660) += pinctrl-msm8660.o
@@ -37,6 +38,7 @@ obj-$(CONFIG_PINCTRL_MDM9607) += pinctrl-mdm9607.o · 16 unmodified lines
37obj-$(CONFIG_PINCTRL_MDM9615) += pinctrl-mdm9615.o38obj-$(CONFIG_PINCTRL_MDM9615) += pinctrl-mdm9615.o
38obj-$(CONFIG_PINCTRL_MILOS) += pinctrl-milos.o39obj-$(CONFIG_PINCTRL_MILOS) += pinctrl-milos.o
39obj-$(CONFIG_PINCTRL_MILOS_LPASS_LPI) += pinctrl-milos-lpass-lpi.o40obj-$(CONFIG_PINCTRL_MILOS_LPASS_LPI) += pinctrl-milos-lpass-lpi.o
41obj-$(CONFIG_PINCTRL_NORD) += pinctrl-nord.o
40obj-$(CONFIG_PINCTRL_QCOM_SPMI_PMIC) += pinctrl-spmi-gpio.o42obj-$(CONFIG_PINCTRL_QCOM_SPMI_PMIC) += pinctrl-spmi-gpio.o
41obj-$(CONFIG_PINCTRL_QCOM_SPMI_PMIC) += pinctrl-spmi-mpp.o43obj-$(CONFIG_PINCTRL_QCOM_SPMI_PMIC) += pinctrl-spmi-mpp.o
42obj-$(CONFIG_PINCTRL_QCOM_SSBI_PMIC) += pinctrl-ssbi-gpio.o44obj-$(CONFIG_PINCTRL_QCOM_SSBI_PMIC) += pinctrl-ssbi-gpio.o
@@ -57,12 +59,14 @@ obj-$(CONFIG_PINCTRL_SDM845) += pinctrl-sdm845.o · 14 unmodified lines
57obj-$(CONFIG_PINCTRL_SDX55) += pinctrl-sdx55.o59obj-$(CONFIG_PINCTRL_SDX55) += pinctrl-sdx55.o
58obj-$(CONFIG_PINCTRL_SDX65) += pinctrl-sdx65.o60obj-$(CONFIG_PINCTRL_SDX65) += pinctrl-sdx65.o
59obj-$(CONFIG_PINCTRL_SDX75) += pinctrl-sdx75.o61obj-$(CONFIG_PINCTRL_SDX75) += pinctrl-sdx75.o
62obj-$(CONFIG_PINCTRL_SHIKRA) += pinctrl-shikra.o
60obj-$(CONFIG_PINCTRL_SM4250_LPASS_LPI) += pinctrl-sm4250-lpass-lpi.o63obj-$(CONFIG_PINCTRL_SM4250_LPASS_LPI) += pinctrl-sm4250-lpass-lpi.o
61obj-$(CONFIG_PINCTRL_SM4450) += pinctrl-sm4450.o64obj-$(CONFIG_PINCTRL_SM4450) += pinctrl-sm4450.o
62obj-$(CONFIG_PINCTRL_SM6115) += pinctrl-sm6115.o65obj-$(CONFIG_PINCTRL_SM6115) += pinctrl-sm6115.o
63obj-$(CONFIG_PINCTRL_SM6115_LPASS_LPI) += pinctrl-sm6115-lpass-lpi.o66obj-$(CONFIG_PINCTRL_SM6115_LPASS_LPI) += pinctrl-sm6115-lpass-lpi.o
64obj-$(CONFIG_PINCTRL_SM6125) += pinctrl-sm6125.o67obj-$(CONFIG_PINCTRL_SM6125) += pinctrl-sm6125.o
65obj-$(CONFIG_PINCTRL_SM6350) += pinctrl-sm6350.o68obj-$(CONFIG_PINCTRL_SM6350) += pinctrl-sm6350.o
69obj-$(CONFIG_PINCTRL_SM6350_LPASS_LPI) += pinctrl-sm6350-lpass-lpi.o
66obj-$(CONFIG_PINCTRL_SM6375) += pinctrl-sm6375.o70obj-$(CONFIG_PINCTRL_SM6375) += pinctrl-sm6375.o
67obj-$(CONFIG_PINCTRL_SM7150) += pinctrl-sm7150.o71obj-$(CONFIG_PINCTRL_SM7150) += pinctrl-sm7150.o
68obj-$(CONFIG_PINCTRL_SM8150) += pinctrl-sm8150.o72obj-$(CONFIG_PINCTRL_SM8150) += pinctrl-sm8150.o
drivers/pinctrl/qcom/pinctrl-apq8064.c+1−1
@@ -622,6 +622,7 @@ static const struct of_device_id apq8064_pinctrl_of_match[] = { · 621 unmodified lines
622 { .compatible = "qcom,apq8064-pinctrl", },622 { .compatible = "qcom,apq8064-pinctrl", },
623 { },623 { },
624};624};
625MODULE_DEVICE_TABLE(of, apq8064_pinctrl_of_match);
625 626
626static struct platform_driver apq8064_pinctrl_driver = {627static struct platform_driver apq8064_pinctrl_driver = {
627 .driver = {628 .driver = {
@@ -646,4 +647,3 @@ module_exit(apq8064_pinctrl_exit); · 18 unmodified lines
646MODULE_AUTHOR("Bjorn Andersson <bjorn.andersson@sonymobile.com>");647MODULE_AUTHOR("Bjorn Andersson <bjorn.andersson@sonymobile.com>");
647MODULE_DESCRIPTION("Qualcomm APQ8064 pinctrl driver");648MODULE_DESCRIPTION("Qualcomm APQ8064 pinctrl driver");
648MODULE_LICENSE("GPL v2");649MODULE_LICENSE("GPL v2");
649MODULE_DEVICE_TABLE(of, apq8064_pinctrl_of_match);
drivers/pinctrl/qcom/pinctrl-apq8084.c+1−1
@@ -1198,6 +1198,7 @@ static const struct of_device_id apq8084_pinctrl_of_match[] = { · 1197 unmodified lines
1198 { .compatible = "qcom,apq8084-pinctrl", },1198 { .compatible = "qcom,apq8084-pinctrl", },
1199 { },1199 { },
1200};1200};
1201MODULE_DEVICE_TABLE(of, apq8084_pinctrl_of_match);
1201 1202
1202static struct platform_driver apq8084_pinctrl_driver = {1203static struct platform_driver apq8084_pinctrl_driver = {
1203 .driver = {1204 .driver = {
@@ -1221,4 +1222,3 @@ module_exit(apq8084_pinctrl_exit); · 17 unmodified lines
1221 1222
1222MODULE_DESCRIPTION("Qualcomm APQ8084 pinctrl driver");1223MODULE_DESCRIPTION("Qualcomm APQ8084 pinctrl driver");
1223MODULE_LICENSE("GPL v2");1224MODULE_LICENSE("GPL v2");
1224MODULE_DEVICE_TABLE(of, apq8084_pinctrl_of_match);
drivers/pinctrl/qcom/pinctrl-eliza.c+133−55
@@ -54,30 +54,6 @@ · 53 unmodified lines
54 .intr_detection_width = 2, \54 .intr_detection_width = 2, \
55 }55 }
56 56
57#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \
58 { \
59 .grp = PINCTRL_PINGROUP(#pg_name, \
60 pg_name##_pins, \
61 ARRAY_SIZE(pg_name##_pins)), \
62 .ctl_reg = ctl, \
63 .io_reg = 0, \
64 .intr_cfg_reg = 0, \
65 .intr_status_reg = 0, \
66 .mux_bit = -1, \
67 .pull_bit = pull, \
68 .drv_bit = drv, \
69 .oe_bit = -1, \
70 .in_bit = -1, \
71 .out_bit = -1, \
72 .intr_enable_bit = -1, \
73 .intr_status_bit = -1, \
74 .intr_target_bit = -1, \
75 .intr_raw_status_bit = -1, \
76 .intr_polarity_bit = -1, \
77 .intr_detection_bit = -1, \
78 .intr_detection_width = -1, \
79 }
80
81#define UFS_RESET(pg_name, ctl, io) \57#define UFS_RESET(pg_name, ctl, io) \
82 { \58 { \
83 .grp = PINCTRL_PINGROUP(#pg_name, \59 .grp = PINCTRL_PINGROUP(#pg_name, \
@@ -563,15 +539,32 @@ enum eliza_functions { · 479 unmodified lines
563 msm_mux_qup1_se0,539 msm_mux_qup1_se0,
564 msm_mux_qup1_se1,540 msm_mux_qup1_se1,
565 msm_mux_qup1_se2,541 msm_mux_qup1_se2,
542 msm_mux_qup1_se2_l2_mira,
543 msm_mux_qup1_se2_l2_mirb,
544 msm_mux_qup1_se2_l3_mira,
545 msm_mux_qup1_se2_l3_mirb,
566 msm_mux_qup1_se3,546 msm_mux_qup1_se3,
567 msm_mux_qup1_se4,547 msm_mux_qup1_se4_01,
548 msm_mux_qup1_se4_23,
568 msm_mux_qup1_se5,549 msm_mux_qup1_se5,
569 msm_mux_qup1_se6,550 msm_mux_qup1_se6,
551 msm_mux_qup1_se6_l1_mira,
552 msm_mux_qup1_se6_l1_mirb,
553 msm_mux_qup1_se6_l3_mira,
554 msm_mux_qup1_se6_l3_mirb,
570 msm_mux_qup1_se7,555 msm_mux_qup1_se7,
556 msm_mux_qup1_se7_l0_mira,
557 msm_mux_qup1_se7_l0_mirb,
558 msm_mux_qup1_se7_l1_mira,
559 msm_mux_qup1_se7_l1_mirb,
571 msm_mux_qup2_se0,560 msm_mux_qup2_se0,
572 msm_mux_qup2_se1,561 msm_mux_qup2_se1,
573 msm_mux_qup2_se2,562 msm_mux_qup2_se2,
574 msm_mux_qup2_se3,563 msm_mux_qup2_se3,
564 msm_mux_qup2_se3_l0_mira,
565 msm_mux_qup2_se3_l0_mirb,
566 msm_mux_qup2_se3_l1_mira,
567 msm_mux_qup2_se3_l1_mirb,
575 msm_mux_qup2_se4,568 msm_mux_qup2_se4,
576 msm_mux_qup2_se5,569 msm_mux_qup2_se5,
577 msm_mux_qup2_se6,570 msm_mux_qup2_se6,
@@ -978,15 +971,35 @@ static const char *const qup1_se1_groups[] = { · 400 unmodified lines
978};971};
979 972
980static const char *const qup1_se2_groups[] = {973static const char *const qup1_se2_groups[] = {
981 "gpio52", "gpio53", "gpio54", "gpio52", "gpio55", "gpio53", "gpio40", "gpio42", "gpio30",974 "gpio52", "gpio53", "gpio40", "gpio42", "gpio30",
975};
976
977static const char *const qup1_se2_l2_mira_groups[] = {
978 "gpio54",
979};
980
981static const char *const qup1_se2_l2_mirb_groups[] = {
982 "gpio52",
983};
984
985static const char *const qup1_se2_l3_mira_groups[] = {
986 "gpio55",
987};
988
989static const char *const qup1_se2_l3_mirb_groups[] = {
990 "gpio53",
982};991};
983 992
984static const char *const qup1_se3_groups[] = {993static const char *const qup1_se3_groups[] = {
985 "gpio44", "gpio45", "gpio46", "gpio47",994 "gpio44", "gpio45", "gpio46", "gpio47",
986};995};
987 996
988static const char *const qup1_se4_groups[] = {997static const char *const qup1_se4_01_groups[] = {
989 "gpio36", "gpio37", "gpio37", "gpio36",998 "gpio36", "gpio37",
999};
1000
1001static const char *const qup1_se4_23_groups[] = {
1002 "gpio36", "gpio37",
990};1003};
991 1004
992static const char *const qup1_se5_groups[] = {1005static const char *const qup1_se5_groups[] = {
@@ -994,11 +1007,43 @@ static const char *const qup1_se5_groups[] = { · 1 unmodified line
994};1007};
995 1008
996static const char *const qup1_se6_groups[] = {1009static const char *const qup1_se6_groups[] = {
997 "gpio40", "gpio42", "gpio54", "gpio42", "gpio40", "gpio55",1010 "gpio40", "gpio42",
1011};
1012
1013static const char *const qup1_se6_l1_mira_groups[] = {
1014 "gpio42",
1015};
1016
1017static const char *const qup1_se6_l1_mirb_groups[] = {
1018 "gpio54",
1019};
1020
1021static const char *const qup1_se6_l3_mira_groups[] = {
1022 "gpio40",
1023};
1024
1025static const char *const qup1_se6_l3_mirb_groups[] = {
1026 "gpio55",
998};1027};
999 1028
1000static const char *const qup1_se7_groups[] = {1029static const char *const qup1_se7_groups[] = {
1001 "gpio81", "gpio78", "gpio80", "gpio114", "gpio114", "gpio78",1030 "gpio78", "gpio114",
1031};
1032
1033static const char *const qup1_se7_l0_mira_groups[] = {
1034 "gpio81",
1035};
1036
1037static const char *const qup1_se7_l0_mirb_groups[] = {
1038 "gpio78",
1039};
1040
1041static const char *const qup1_se7_l1_mira_groups[] = {
1042 "gpio80",
1043};
1044
1045static const char *const qup1_se7_l1_mirb_groups[] = {
1046 "gpio114",
1002};1047};
1003 1048
1004static const char *const qup2_se0_groups[] = {1049static const char *const qup2_se0_groups[] = {
@@ -1014,7 +1059,23 @@ static const char *const qup2_se2_groups[] = { · 9 unmodified lines
1014};1059};
1015 1060
1016static const char *const qup2_se3_groups[] = {1061static const char *const qup2_se3_groups[] = {
1017 "gpio79", "gpio116", "gpio97", "gpio100", "gpio100", "gpio116",1062 "gpio100", "gpio116",
1063};
1064
1065static const char *const qup2_se3_l0_mira_groups[] = {
1066 "gpio79",
1067};
1068
1069static const char *const qup2_se3_l0_mirb_groups[] = {
1070 "gpio116",
1071};
1072
1073static const char *const qup2_se3_l1_mira_groups[] = {
1074 "gpio97",
1075};
1076
1077static const char *const qup2_se3_l1_mirb_groups[] = {
1078 "gpio100",
1018};1079};
1019 1080
1020static const char *const qup2_se4_groups[] = {1081static const char *const qup2_se4_groups[] = {
@@ -1236,15 +1297,32 @@ static const struct pinfunction eliza_functions[] = { · 215 unmodified lines
1236 MSM_PIN_FUNCTION(qup1_se0),1297 MSM_PIN_FUNCTION(qup1_se0),
1237 MSM_PIN_FUNCTION(qup1_se1),1298 MSM_PIN_FUNCTION(qup1_se1),
1238 MSM_PIN_FUNCTION(qup1_se2),1299 MSM_PIN_FUNCTION(qup1_se2),
1300 MSM_PIN_FUNCTION(qup1_se2_l2_mira),
1301 MSM_PIN_FUNCTION(qup1_se2_l2_mirb),
1302 MSM_PIN_FUNCTION(qup1_se2_l3_mira),
1303 MSM_PIN_FUNCTION(qup1_se2_l3_mirb),
1239 MSM_PIN_FUNCTION(qup1_se3),1304 MSM_PIN_FUNCTION(qup1_se3),
1240 MSM_PIN_FUNCTION(qup1_se4),1305 MSM_PIN_FUNCTION(qup1_se4_01),
1306 MSM_PIN_FUNCTION(qup1_se4_23),
1241 MSM_PIN_FUNCTION(qup1_se5),1307 MSM_PIN_FUNCTION(qup1_se5),
1242 MSM_PIN_FUNCTION(qup1_se6),1308 MSM_PIN_FUNCTION(qup1_se6),
1309 MSM_PIN_FUNCTION(qup1_se6_l1_mira),
1310 MSM_PIN_FUNCTION(qup1_se6_l1_mirb),
1311 MSM_PIN_FUNCTION(qup1_se6_l3_mira),
1312 MSM_PIN_FUNCTION(qup1_se6_l3_mirb),
1243 MSM_PIN_FUNCTION(qup1_se7),1313 MSM_PIN_FUNCTION(qup1_se7),
1314 MSM_PIN_FUNCTION(qup1_se7_l0_mira),
1315 MSM_PIN_FUNCTION(qup1_se7_l0_mirb),
1316 MSM_PIN_FUNCTION(qup1_se7_l1_mira),
1317 MSM_PIN_FUNCTION(qup1_se7_l1_mirb),
1244 MSM_PIN_FUNCTION(qup2_se0),1318 MSM_PIN_FUNCTION(qup2_se0),
1245 MSM_PIN_FUNCTION(qup2_se1),1319 MSM_PIN_FUNCTION(qup2_se1),
1246 MSM_PIN_FUNCTION(qup2_se2),1320 MSM_PIN_FUNCTION(qup2_se2),
1247 MSM_PIN_FUNCTION(qup2_se3),1321 MSM_PIN_FUNCTION(qup2_se3),
1322 MSM_PIN_FUNCTION(qup2_se3_l0_mira),
1323 MSM_PIN_FUNCTION(qup2_se3_l0_mirb),
1324 MSM_PIN_FUNCTION(qup2_se3_l1_mira),
1325 MSM_PIN_FUNCTION(qup2_se3_l1_mirb),
1248 MSM_PIN_FUNCTION(qup2_se4),1326 MSM_PIN_FUNCTION(qup2_se4),
1249 MSM_PIN_FUNCTION(qup2_se5),1327 MSM_PIN_FUNCTION(qup2_se5),
1250 MSM_PIN_FUNCTION(qup2_se6),1328 MSM_PIN_FUNCTION(qup2_se6),
@@ -1322,33 +1400,33 @@ static const struct msm_pingroup eliza_groups[] = { · 71 unmodified lines
1322 [33] = PINGROUP(33, qup1_se1, ibi_i3c, host2wlan_sol, gcc_gp3, _, _, _, _, _, _, _),1400 [33] = PINGROUP(33, qup1_se1, ibi_i3c, host2wlan_sol, gcc_gp3, _, _, _, _, _, _, _),
1323 [34] = PINGROUP(34, qup1_se1, qup1_se5, tb_trig_sdc1, ddr_bist_start, qdss_gpio_tracedata, _, _, _, _, _, _),1401 [34] = PINGROUP(34, qup1_se1, qup1_se5, tb_trig_sdc1, ddr_bist_start, qdss_gpio_tracedata, _, _, _, _, _, _),
1324 [35] = PINGROUP(35, qup1_se1, qup1_se5, tb_trig_sdc2, gcc_gp2, qdss_gpio_tracedata, _, _, _, _, _, _),1402 [35] = PINGROUP(35, qup1_se1, qup1_se5, tb_trig_sdc2, gcc_gp2, qdss_gpio_tracedata, _, _, _, _, _, _),
1325 [36] = PINGROUP(36, qup1_se4, qup1_se4, ibi_i3c, _, _, _, _, _, _, _, _),1403 [36] = PINGROUP(36, qup1_se4_01, qup1_se4_23, ibi_i3c, _, _, _, _, _, _, _, _),
1326 [37] = PINGROUP(37, qup1_se4, qup1_se4, ibi_i3c, _, _, _, _, _, _, _, _),1404 [37] = PINGROUP(37, qup1_se4_01, qup1_se4_23, ibi_i3c, _, _, _, _, _, _, _, _),
1327 [38] = PINGROUP(38, _, _, _, _, _, _, _, _, _, _, _),1405 [38] = PINGROUP(38, sdc2, _, _, _, _, _, _, _, _, _, _),
1328 [39] = PINGROUP(39, _, _, _, _, _, _, _, _, _, _, _),1406 [39] = PINGROUP(39, sdc2, _, _, _, _, _, _, _, _, _, _),
1329 [40] = PINGROUP(40, qup1_se6, qup1_se2, qup1_se6, _, qdss_gpio_tracedata, gnss_adc1, ddr_pxi1, _, _, _, _),1407 [40] = PINGROUP(40, qup1_se6, qup1_se2, qup1_se6_l3_mira, _, qdss_gpio_tracedata, gnss_adc1, ddr_pxi1, _, _, _, _),
1330 [41] = PINGROUP(41, _, _, _, _, _, _, _, _, _, _, _),1408 [41] = PINGROUP(41, _, _, _, _, _, _, _, _, _, _, _),
1331 [42] = PINGROUP(42, qup1_se6, qup1_se2, qup1_se6, qdss_gpio_tracedata, gnss_adc0, ddr_pxi1, _, _, _, _, _),1409 [42] = PINGROUP(42, qup1_se6, qup1_se2, qup1_se6_l1_mira, qdss_gpio_tracedata, gnss_adc0, ddr_pxi1, _, _, _, _, _),
1332 [43] = PINGROUP(43, _, _, _, _, _, _, _, _, _, _, _),1410 [43] = PINGROUP(43, _, _, _, _, _, _, _, _, _, _, _),
1333 [44] = PINGROUP(44, qup1_se3, _, _, _, _, _, _, _, _, _, _),1411 [44] = PINGROUP(44, qup1_se3, _, _, _, _, _, _, _, _, _, _),
1334 [45] = PINGROUP(45, qup1_se3, _, _, _, _, _, _, _, _, _, _),1412 [45] = PINGROUP(45, qup1_se3, _, _, _, _, _, _, _, _, _, _),
1335 [46] = PINGROUP(46, qup1_se3, hdmi_tx_cec, _, _, _, _, _, _, _, _, _),1413 [46] = PINGROUP(46, qup1_se3, hdmi_tx_cec, _, _, _, _, _, _, _, _, _),
1336 [47] = PINGROUP(47, qup1_se3, hdmi_hot_plug, _, _, _, _, _, _, _, _, _),1414 [47] = PINGROUP(47, qup1_se3, hdmi_hot_plug, _, _, _, _, _, _, _, _, _),
1337 [48] = PINGROUP(48, _, _, _, _, _, _, _, _, _, _, _),1415 [48] = PINGROUP(48, sdc2, _, _, _, _, _, _, _, _, _, _),
1338 [49] = PINGROUP(49, _, _, _, _, _, _, _, _, _, _, _),1416 [49] = PINGROUP(49, sdc2, _, _, _, _, _, _, _, _, _, _),
1339 [50] = PINGROUP(50, sdc2_fb_clk, _, _, _, _, _, _, _, _, _, _),1417 [50] = PINGROUP(50, sdc2_fb_clk, _, _, _, _, _, _, _, _, _, _),
1340 [51] = PINGROUP(51, _, _, _, _, _, _, _, _, _, _, _),1418 [51] = PINGROUP(51, sdc2, _, _, _, _, _, _, _, _, _, _),
1341 [52] = PINGROUP(52, qup1_se2, pcie1_clk_req_n, qup1_se2, ddr_bist_complete, qdss_gpio_tracedata, _, vsense_trigger_mirnat, _, _, _, _),1419 [52] = PINGROUP(52, qup1_se2, pcie1_clk_req_n, qup1_se2_l2_mirb, ddr_bist_complete, qdss_gpio_tracedata, _, vsense_trigger_mirnat, _, _, _, _),
1342 [53] = PINGROUP(53, qup1_se2, qup1_se2, gcc_gp1, ddr_bist_stop, _, qdss_gpio_tracedata, _, _, _, _, _),1420 [53] = PINGROUP(53, qup1_se2, qup1_se2_l3_mirb, gcc_gp1, ddr_bist_stop, _, qdss_gpio_tracedata, _, _, _, _, _),
1343 [54] = PINGROUP(54, qup1_se2, qup1_se6, qdss_gpio_traceclk, gnss_adc1, atest_usb, ddr_pxi0, _, _, _, _, _),1421 [54] = PINGROUP(54, qup1_se2_l2_mira, qup1_se6_l1_mirb, qdss_gpio_traceclk, gnss_adc1, atest_usb, ddr_pxi0, _, _, _, _, _),
1344 [55] = PINGROUP(55, qup1_se2, dp0_hot, qup1_se6, _, gnss_adc0, atest_usb, ddr_pxi0, _, _, _, _),1422 [55] = PINGROUP(55, qup1_se2_l3_mira, dp0_hot, qup1_se6_l3_mirb, _, gnss_adc0, atest_usb, ddr_pxi0, _, _, _, _),
1345 [56] = PINGROUP(56, usb0_hs, tsense_pwm1, tsense_pwm2, tsense_pwm3, tsense_pwm4, _, _, _, _, _, _),1423 [56] = PINGROUP(56, usb0_hs, tsense_pwm1, tsense_pwm2, tsense_pwm3, tsense_pwm4, _, _, _, _, _, _),
1346 [57] = PINGROUP(57, sd_write_protect, _, _, _, _, _, _, _, _, _, _),1424 [57] = PINGROUP(57, sd_write_protect, _, _, _, _, _, _, _, _, _, _),
1347 [58] = PINGROUP(58, _, _, _, _, _, _, _, _, _, _, _),1425 [58] = PINGROUP(58, _, _, _, _, _, _, _, _, _, _, _),
1348 [59] = PINGROUP(59, _, _, _, _, _, _, _, _, _, _, _),1426 [59] = PINGROUP(59, _, _, _, _, _, _, _, _, _, _, _),
1349 [60] = PINGROUP(60, i2s0_sck, _, _, _, _, _, _, _, _, _, _),1427 [60] = PINGROUP(60, i2s0_sck, _, _, _, _, _, _, _, _, _, _),
1350 [61] = PINGROUP(61, i2s0_ws, _, _, _, _, _, _, _, _, _, _),1428 [61] = PINGROUP(61, i2s0_ws, _, _, _, _, _, _, _, _, _, _),
1351 [62] = PINGROUP(62, _, _, _, _, _, _, _, _, _, _, _),1429 [62] = PINGROUP(62, sdc2, _, _, _, _, _, _, _, _, _, _),
1352 [63] = PINGROUP(63, resout_gpio, i2s0_data1, cci_timer, vfr_0, _, _, _, _, _, _, _),1430 [63] = PINGROUP(63, resout_gpio, i2s0_data1, cci_timer, vfr_0, _, _, _, _, _, _, _),
1353 [64] = PINGROUP(64, i2s0_data0, _, _, _, _, _, _, _, _, _, _),1431 [64] = PINGROUP(64, i2s0_data0, _, _, _, _, _, _, _, _, _, _),
1354 [65] = PINGROUP(65, cam_mclk, _, qdss_gpio_tracedata, _, _, _, _, _, _, _, _),1432 [65] = PINGROUP(65, cam_mclk, _, qdss_gpio_tracedata, _, _, _, _, _, _, _, _),
@@ -1364,10 +1442,10 @@ static const struct msm_pingroup eliza_groups[] = { · 9 unmodified lines
1364 [75] = PINGROUP(75, cci_i2c_scl, _, phase_flag, _, _, _, _, _, _, _, _),1442 [75] = PINGROUP(75, cci_i2c_scl, _, phase_flag, _, _, _, _, _, _, _, _),
1365 [76] = PINGROUP(76, cci_i2c_sda, cci_timer, prng_rosc2, _, phase_flag, _, _, _, _, _, _),1443 [76] = PINGROUP(76, cci_i2c_sda, cci_timer, prng_rosc2, _, phase_flag, _, _, _, _, _, _),
1366 [77] = PINGROUP(77, cci_i2c_scl, jitter_bist, _, _, _, _, _, _, _, _, _),1444 [77] = PINGROUP(77, cci_i2c_scl, jitter_bist, _, _, _, _, _, _, _, _, _),
1367 [78] = PINGROUP(78, qup1_se7, qup1_se7, _, phase_flag, _, _, _, _, _, _, _),1445 [78] = PINGROUP(78, qup1_se7, qup1_se7_l0_mirb, _, phase_flag, _, _, _, _, _, _, _),
1368 [79] = PINGROUP(79, qspi0, mdp_vsync, qup2_se3, _, _, _, _, _, _, _, _),1446 [79] = PINGROUP(79, qspi0, mdp_vsync, qup2_se3_l0_mira, _, _, _, _, _, _, _, _),
1369 [80] = PINGROUP(80, pcie0_clk_req_n, qup1_se7, _, phase_flag, _, _, _, _, _, _, _),1447 [80] = PINGROUP(80, pcie0_clk_req_n, qup1_se7_l1_mira, _, phase_flag, _, _, _, _, _, _, _),
1370 [81] = PINGROUP(81, wcn_sw_ctrl, qup1_se7, dbg_out_clk, _, _, _, _, _, _, _, _),1448 [81] = PINGROUP(81, wcn_sw_ctrl, qup1_se7_l0_mira, dbg_out_clk, _, _, _, _, _, _, _, _),
1371 [82] = PINGROUP(82, _, _, _, _, _, _, _, _, _, _, _),1449 [82] = PINGROUP(82, _, _, _, _, _, _, _, _, _, _, _),
1372 [83] = PINGROUP(83, _, _, _, _, _, _, _, _, _, _, _),1450 [83] = PINGROUP(83, _, _, _, _, _, _, _, _, _, _, _),
1373 [84] = PINGROUP(84, uim0_data, _, _, _, _, _, _, _, _, _, _),1451 [84] = PINGROUP(84, uim0_data, _, _, _, _, _, _, _, _, _, _),
@@ -1383,10 +1461,10 @@ static const struct msm_pingroup eliza_groups[] = { · 9 unmodified lines
1383 [94] = PINGROUP(94, qlink_wmss, _, _, _, _, _, _, _, _, _, _),1461 [94] = PINGROUP(94, qlink_wmss, _, _, _, _, _, _, _, _, _, _),
1384 [95] = PINGROUP(95, qlink_big_request, _, _, _, _, _, _, _, _, _, _),1462 [95] = PINGROUP(95, qlink_big_request, _, _, _, _, _, _, _, _, _, _),
1385 [96] = PINGROUP(96, qlink_big_enable, _, _, _, _, _, _, _, _, _, _),1463 [96] = PINGROUP(96, qlink_big_enable, _, _, _, _, _, _, _, _, _, _),
1386 [97] = PINGROUP(97, uim1_data, qspi0, qup2_se3, _, _, _, _, _, _, _, _),1464 [97] = PINGROUP(97, uim1_data, qspi0, qup2_se3_l1_mira, _, _, _, _, _, _, _, _),
1387 [98] = PINGROUP(98, uim1_clk, qspi0, _, _, _, _, _, _, _, _, _),1465 [98] = PINGROUP(98, uim1_clk, qspi0, _, _, _, _, _, _, _, _, _),
1388 [99] = PINGROUP(99, uim1_reset, qspi0, _, _, _, _, _, _, _, _, _),1466 [99] = PINGROUP(99, uim1_reset, qspi0, _, _, _, _, _, _, _, _, _),
1389 [100] = PINGROUP(100, uim1_present, qspi0, qup2_se3, coex_uart2_tx, qup2_se3, mdp_vsync, _, _, _, _, _),1467 [100] = PINGROUP(100, uim1_present, qspi0, qup2_se3, coex_uart2_tx, qup2_se3_l1_mirb, mdp_vsync, _, _, _, _, _),
1390 [101] = PINGROUP(101, _, _, _, _, _, _, _, _, _, _, _),1468 [101] = PINGROUP(101, _, _, _, _, _, _, _, _, _, _, _),
1391 [102] = PINGROUP(102, _, _, _, _, _, _, _, _, _, _, _),1469 [102] = PINGROUP(102, _, _, _, _, _, _, _, _, _, _, _),
1392 [103] = PINGROUP(103, _, _, _, _, _, _, _, _, _, _, _),1470 [103] = PINGROUP(103, _, _, _, _, _, _, _, _, _, _, _),
@@ -1400,9 +1478,9 @@ static const struct msm_pingroup eliza_groups[] = { · 7 unmodified lines
1400 [111] = PINGROUP(111, coex_uart1_tx, _, _, _, _, _, _, _, _, _, _),1478 [111] = PINGROUP(111, coex_uart1_tx, _, _, _, _, _, _, _, _, _, _),
1401 [112] = PINGROUP(112, coex_uart1_rx, _, _, _, _, _, _, _, _, _, _),1479 [112] = PINGROUP(112, coex_uart1_rx, _, _, _, _, _, _, _, _, _, _),
1402 [113] = PINGROUP(113, _, nav_gpio3, _, _, _, _, _, _, _, _, _),1480 [113] = PINGROUP(113, _, nav_gpio3, _, _, _, _, _, _, _, _, _),
1403 [114] = PINGROUP(114, qup1_se7, qup1_se7, _, qdss_gpio_tracedata, _, _, _, _, _, _, _),1481 [114] = PINGROUP(114, qup1_se7, qup1_se7_l1_mirb, _, qdss_gpio_tracedata, _, _, _, _, _, _, _),
1404 [115] = PINGROUP(115, _, qspi0, cci_async_in, _, _, _, _, _, _, _, _),1482 [115] = PINGROUP(115, _, qspi0, cci_async_in, _, _, _, _, _, _, _, _),
1405 [116] = PINGROUP(116, qspi0, coex_uart2_rx, qup2_se3, qup2_se3, _, _, _, _, _, _, _),1483 [116] = PINGROUP(116, qspi0, coex_uart2_rx, qup2_se3, qup2_se3_l0_mirb, _, _, _, _, _, _, _),
1406 [117] = PINGROUP(117, nav_gpio1, _, vfr_1, _, _, _, _, _, _, _, _),1484 [117] = PINGROUP(117, nav_gpio1, _, vfr_1, _, _, _, _, _, _, _, _),
1407 [118] = PINGROUP(118, nav_gpio2, _, _, _, _, _, _, _, _, _, _),1485 [118] = PINGROUP(118, nav_gpio2, _, _, _, _, _, _, _, _, _, _),
1408 [119] = PINGROUP(119, nav_gpio0, _, _, _, _, _, _, _, _, _, _),1486 [119] = PINGROUP(119, nav_gpio0, _, _, _, _, _, _, _, _, _, _),
@@ -1519,6 +1597,7 @@ static const struct of_device_id eliza_tlmm_of_match[] = { · 110 unmodified lines
1519 { .compatible = "qcom,eliza-tlmm", },1597 { .compatible = "qcom,eliza-tlmm", },
1520 {},1598 {},
1521};1599};
1600MODULE_DEVICE_TABLE(of, eliza_tlmm_of_match);
1522 1601
1523static struct platform_driver eliza_tlmm_driver = {1602static struct platform_driver eliza_tlmm_driver = {
1524 .driver = {1603 .driver = {
@@ -1542,4 +1621,3 @@ module_exit(eliza_tlmm_exit); · 17 unmodified lines
1542 1621
1543MODULE_DESCRIPTION("QTI Eliza TLMM driver");1622MODULE_DESCRIPTION("QTI Eliza TLMM driver");
1544MODULE_LICENSE("GPL");1623MODULE_LICENSE("GPL");
1545MODULE_DEVICE_TABLE(of, eliza_tlmm_of_match);
drivers/pinctrl/qcom/pinctrl-glymur.c+1−1
@@ -1777,6 +1777,7 @@ static const struct of_device_id glymur_tlmm_of_match[] = { · 1776 unmodified lines
1777 { .compatible = "qcom,mahua-tlmm", .data = &mahua_tlmm },1777 { .compatible = "qcom,mahua-tlmm", .data = &mahua_tlmm },
1778 { },1778 { },
1779};1779};
1780MODULE_DEVICE_TABLE(of, glymur_tlmm_of_match);
1780 1781
1781static int glymur_tlmm_probe(struct platform_device *pdev)1782static int glymur_tlmm_probe(struct platform_device *pdev)
1782{1783{
@@ -1811,4 +1812,3 @@ module_exit(glymur_tlmm_exit); · 28 unmodified lines
1811 1812
1812MODULE_DESCRIPTION("QTI Glymur TLMM driver");1813MODULE_DESCRIPTION("QTI Glymur TLMM driver");
1813MODULE_LICENSE("GPL");1814MODULE_LICENSE("GPL");
1814MODULE_DEVICE_TABLE(of, glymur_tlmm_of_match);
drivers/pinctrl/qcom/pinctrl-hawi.c+1−1
@@ -1584,6 +1584,7 @@ static const struct of_device_id hawi_tlmm_of_match[] = { · 1583 unmodified lines
1584 { .compatible = "qcom,hawi-tlmm", },1584 { .compatible = "qcom,hawi-tlmm", },
1585 {},1585 {},
1586};1586};
1587MODULE_DEVICE_TABLE(of, hawi_tlmm_of_match);
1587 1588
1588static struct platform_driver hawi_tlmm_driver = {1589static struct platform_driver hawi_tlmm_driver = {
1589 .driver = {1590 .driver = {
@@ -1607,4 +1608,3 @@ module_exit(hawi_tlmm_exit); · 17 unmodified lines
1607 1608
1608MODULE_DESCRIPTION("QTI Hawi TLMM driver");1609MODULE_DESCRIPTION("QTI Hawi TLMM driver");
1609MODULE_LICENSE("GPL");1610MODULE_LICENSE("GPL");
1610MODULE_DEVICE_TABLE(of, hawi_tlmm_of_match);
drivers/pinctrl/qcom/pinctrl-ipq4019.c+1−1
@@ -702,6 +702,7 @@ static const struct of_device_id ipq4019_pinctrl_of_match[] = { · 701 unmodified lines
702 { .compatible = "qcom,ipq4019-pinctrl", },702 { .compatible = "qcom,ipq4019-pinctrl", },
703 { },703 { },
704};704};
705MODULE_DEVICE_TABLE(of, ipq4019_pinctrl_of_match);
705 706
706static struct platform_driver ipq4019_pinctrl_driver = {707static struct platform_driver ipq4019_pinctrl_driver = {
707 .driver = {708 .driver = {
@@ -725,4 +726,3 @@ module_exit(ipq4019_pinctrl_exit); · 17 unmodified lines
725 726
726MODULE_DESCRIPTION("Qualcomm ipq4019 pinctrl driver");727MODULE_DESCRIPTION("Qualcomm ipq4019 pinctrl driver");
727MODULE_LICENSE("GPL v2");728MODULE_LICENSE("GPL v2");
728MODULE_DEVICE_TABLE(of, ipq4019_pinctrl_of_match);
drivers/pinctrl/qcom/pinctrl-ipq6018.c+1−1
@@ -1072,6 +1072,7 @@ static const struct of_device_id ipq6018_pinctrl_of_match[] = { · 1071 unmodified lines
1072 { .compatible = "qcom,ipq6018-pinctrl", },1072 { .compatible = "qcom,ipq6018-pinctrl", },
1073 { },1073 { },
1074};1074};
1075MODULE_DEVICE_TABLE(of, ipq6018_pinctrl_of_match);
1075 1076
1076static struct platform_driver ipq6018_pinctrl_driver = {1077static struct platform_driver ipq6018_pinctrl_driver = {
1077 .driver = {1078 .driver = {
@@ -1095,4 +1096,3 @@ module_exit(ipq6018_pinctrl_exit); · 17 unmodified lines
1095 1096
1096MODULE_DESCRIPTION("QTI ipq6018 pinctrl driver");1097MODULE_DESCRIPTION("QTI ipq6018 pinctrl driver");
1097MODULE_LICENSE("GPL v2");1098MODULE_LICENSE("GPL v2");
1098MODULE_DEVICE_TABLE(of, ipq6018_pinctrl_of_match);
drivers/pinctrl/qcom/pinctrl-ipq8064.c+1−1
@@ -624,6 +624,7 @@ static const struct of_device_id ipq8064_pinctrl_of_match[] = { · 623 unmodified lines
624 { .compatible = "qcom,ipq8064-pinctrl", },624 { .compatible = "qcom,ipq8064-pinctrl", },
625 { },625 { },
626};626};
627MODULE_DEVICE_TABLE(of, ipq8064_pinctrl_of_match);
627 628
628static struct platform_driver ipq8064_pinctrl_driver = {629static struct platform_driver ipq8064_pinctrl_driver = {
629 .driver = {630 .driver = {
@@ -648,4 +649,3 @@ module_exit(ipq8064_pinctrl_exit); · 18 unmodified lines
648MODULE_AUTHOR("Andy Gross <agross@codeaurora.org>");649MODULE_AUTHOR("Andy Gross <agross@codeaurora.org>");
649MODULE_DESCRIPTION("Qualcomm IPQ8064 pinctrl driver");650MODULE_DESCRIPTION("Qualcomm IPQ8064 pinctrl driver");
650MODULE_LICENSE("GPL v2");651MODULE_LICENSE("GPL v2");
651MODULE_DEVICE_TABLE(of, ipq8064_pinctrl_of_match);
drivers/pinctrl/qcom/pinctrl-ipq8074.c+1−1
@@ -1033,6 +1033,7 @@ static const struct of_device_id ipq8074_pinctrl_of_match[] = { · 1032 unmodified lines
1033 { .compatible = "qcom,ipq8074-pinctrl", },1033 { .compatible = "qcom,ipq8074-pinctrl", },
1034 { },1034 { },
1035};1035};
1036MODULE_DEVICE_TABLE(of, ipq8074_pinctrl_of_match);
1036 1037
1037static struct platform_driver ipq8074_pinctrl_driver = {1038static struct platform_driver ipq8074_pinctrl_driver = {
1038 .driver = {1039 .driver = {
@@ -1056,4 +1057,3 @@ module_exit(ipq8074_pinctrl_exit); · 17 unmodified lines
1056 1057
1057MODULE_DESCRIPTION("Qualcomm ipq8074 pinctrl driver");1058MODULE_DESCRIPTION("Qualcomm ipq8074 pinctrl driver");
1058MODULE_LICENSE("GPL v2");1059MODULE_LICENSE("GPL v2");
1059MODULE_DEVICE_TABLE(of, ipq8074_pinctrl_of_match);
drivers/pinctrl/qcom/pinctrl-ipq9650.c+762−0
@@ -0,0 +1,762 @@
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
4 */
5
6#include <linux/module.h>
7#include <linux/of.h>
8#include <linux/platform_device.h>
9
10#include "pinctrl-msm.h"
11
12#define REG_SIZE 0x1000
13#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \
14 { \
15 .grp = PINCTRL_PINGROUP("gpio" #id, \
16 gpio##id##_pins, \
17 ARRAY_SIZE(gpio##id##_pins)), \
18 .ctl_reg = REG_SIZE * id, \
19 .io_reg = 0x4 + REG_SIZE * id, \
20 .intr_cfg_reg = 0x8 + REG_SIZE * id, \
21 .intr_status_reg = 0xc + REG_SIZE * id, \
22 .mux_bit = 2, \
23 .pull_bit = 0, \
24 .drv_bit = 6, \
25 .oe_bit = 9, \
26 .in_bit = 0, \
27 .out_bit = 1, \
28 .intr_enable_bit = 0, \
29 .intr_status_bit = 0, \
30 .intr_target_bit = 5, \
31 .intr_target_kpss_val = 3, \
32 .intr_raw_status_bit = 4, \
33 .intr_polarity_bit = 1, \
34 .intr_detection_bit = 2, \
35 .intr_detection_width = 2, \
36 .funcs = (int[]){ \
37 msm_mux_gpio, /* gpio mode */ \
38 msm_mux_##f1, \
39 msm_mux_##f2, \
40 msm_mux_##f3, \
41 msm_mux_##f4, \
42 msm_mux_##f5, \
43 msm_mux_##f6, \
44 msm_mux_##f7, \
45 msm_mux_##f8, \
46 msm_mux_##f9, \
47 }, \
48 .nfuncs = 10, \
49 }
50
51static const struct pinctrl_pin_desc ipq9650_pins[] = {
52 PINCTRL_PIN(0, "GPIO_0"),
53 PINCTRL_PIN(1, "GPIO_1"),
54 PINCTRL_PIN(2, "GPIO_2"),
55 PINCTRL_PIN(3, "GPIO_3"),
56 PINCTRL_PIN(4, "GPIO_4"),
57 PINCTRL_PIN(5, "GPIO_5"),
58 PINCTRL_PIN(6, "GPIO_6"),
59 PINCTRL_PIN(7, "GPIO_7"),
60 PINCTRL_PIN(8, "GPIO_8"),
61 PINCTRL_PIN(9, "GPIO_9"),
62 PINCTRL_PIN(10, "GPIO_10"),
63 PINCTRL_PIN(11, "GPIO_11"),
64 PINCTRL_PIN(12, "GPIO_12"),
65 PINCTRL_PIN(13, "GPIO_13"),
66 PINCTRL_PIN(14, "GPIO_14"),
67 PINCTRL_PIN(15, "GPIO_15"),
68 PINCTRL_PIN(16, "GPIO_16"),
69 PINCTRL_PIN(17, "GPIO_17"),
70 PINCTRL_PIN(18, "GPIO_18"),
71 PINCTRL_PIN(19, "GPIO_19"),
72 PINCTRL_PIN(20, "GPIO_20"),
73 PINCTRL_PIN(21, "GPIO_21"),
74 PINCTRL_PIN(22, "GPIO_22"),
75 PINCTRL_PIN(23, "GPIO_23"),
76 PINCTRL_PIN(24, "GPIO_24"),
77 PINCTRL_PIN(25, "GPIO_25"),
78 PINCTRL_PIN(26, "GPIO_26"),
79 PINCTRL_PIN(27, "GPIO_27"),
80 PINCTRL_PIN(28, "GPIO_28"),
81 PINCTRL_PIN(29, "GPIO_29"),
82 PINCTRL_PIN(30, "GPIO_30"),
83 PINCTRL_PIN(31, "GPIO_31"),
84 PINCTRL_PIN(32, "GPIO_32"),
85 PINCTRL_PIN(33, "GPIO_33"),
86 PINCTRL_PIN(34, "GPIO_34"),
87 PINCTRL_PIN(35, "GPIO_35"),
88 PINCTRL_PIN(36, "GPIO_36"),
89 PINCTRL_PIN(37, "GPIO_37"),
90 PINCTRL_PIN(38, "GPIO_38"),
91 PINCTRL_PIN(39, "GPIO_39"),
92 PINCTRL_PIN(40, "GPIO_40"),
93 PINCTRL_PIN(41, "GPIO_41"),
94 PINCTRL_PIN(42, "GPIO_42"),
95 PINCTRL_PIN(43, "GPIO_43"),
96 PINCTRL_PIN(44, "GPIO_44"),
97 PINCTRL_PIN(45, "GPIO_45"),
98 PINCTRL_PIN(46, "GPIO_46"),
99 PINCTRL_PIN(47, "GPIO_47"),
100 PINCTRL_PIN(48, "GPIO_48"),
101 PINCTRL_PIN(49, "GPIO_49"),
102 PINCTRL_PIN(50, "GPIO_50"),
103 PINCTRL_PIN(51, "GPIO_51"),
104 PINCTRL_PIN(52, "GPIO_52"),
105 PINCTRL_PIN(53, "GPIO_53"),
106};
107
108#define DECLARE_MSM_GPIO_PINS(pin) \
109 static const unsigned int gpio##pin##_pins[] = { pin }
110DECLARE_MSM_GPIO_PINS(0);
111DECLARE_MSM_GPIO_PINS(1);
112DECLARE_MSM_GPIO_PINS(2);
113DECLARE_MSM_GPIO_PINS(3);
114DECLARE_MSM_GPIO_PINS(4);
115DECLARE_MSM_GPIO_PINS(5);
116DECLARE_MSM_GPIO_PINS(6);
117DECLARE_MSM_GPIO_PINS(7);
118DECLARE_MSM_GPIO_PINS(8);
119DECLARE_MSM_GPIO_PINS(9);
120DECLARE_MSM_GPIO_PINS(10);
121DECLARE_MSM_GPIO_PINS(11);
122DECLARE_MSM_GPIO_PINS(12);
123DECLARE_MSM_GPIO_PINS(13);
124DECLARE_MSM_GPIO_PINS(14);
125DECLARE_MSM_GPIO_PINS(15);
126DECLARE_MSM_GPIO_PINS(16);
127DECLARE_MSM_GPIO_PINS(17);
128DECLARE_MSM_GPIO_PINS(18);
129DECLARE_MSM_GPIO_PINS(19);
130DECLARE_MSM_GPIO_PINS(20);
131DECLARE_MSM_GPIO_PINS(21);
132DECLARE_MSM_GPIO_PINS(22);
133DECLARE_MSM_GPIO_PINS(23);
134DECLARE_MSM_GPIO_PINS(24);
135DECLARE_MSM_GPIO_PINS(25);
136DECLARE_MSM_GPIO_PINS(26);
137DECLARE_MSM_GPIO_PINS(27);
138DECLARE_MSM_GPIO_PINS(28);
139DECLARE_MSM_GPIO_PINS(29);
140DECLARE_MSM_GPIO_PINS(30);
141DECLARE_MSM_GPIO_PINS(31);
142DECLARE_MSM_GPIO_PINS(32);
143DECLARE_MSM_GPIO_PINS(33);
144DECLARE_MSM_GPIO_PINS(34);
145DECLARE_MSM_GPIO_PINS(35);
146DECLARE_MSM_GPIO_PINS(36);
147DECLARE_MSM_GPIO_PINS(37);
148DECLARE_MSM_GPIO_PINS(38);
149DECLARE_MSM_GPIO_PINS(39);
150DECLARE_MSM_GPIO_PINS(40);
151DECLARE_MSM_GPIO_PINS(41);
152DECLARE_MSM_GPIO_PINS(42);
153DECLARE_MSM_GPIO_PINS(43);
154DECLARE_MSM_GPIO_PINS(44);
155DECLARE_MSM_GPIO_PINS(45);
156DECLARE_MSM_GPIO_PINS(46);
157DECLARE_MSM_GPIO_PINS(47);
158DECLARE_MSM_GPIO_PINS(48);
159DECLARE_MSM_GPIO_PINS(49);
160DECLARE_MSM_GPIO_PINS(50);
161DECLARE_MSM_GPIO_PINS(51);
162DECLARE_MSM_GPIO_PINS(52);
163DECLARE_MSM_GPIO_PINS(53);
164
165enum ipq9650_functions {
166 msm_mux_atest_char_start,
167 msm_mux_atest_char_status0,
168 msm_mux_atest_char_status1,
169 msm_mux_atest_char_status2,
170 msm_mux_atest_char_status3,
171 msm_mux_atest_tic_en,
172 msm_mux_audio_pri_mclk_in0,
173 msm_mux_audio_pri_mclk_out0,
174 msm_mux_audio_pri_mclk_in1,
175 msm_mux_audio_pri_mclk_out1,
176 msm_mux_audio_pri,
177 msm_mux_audio_sec,
178 msm_mux_audio_sec_mclk_in0,
179 msm_mux_audio_sec_mclk_out0,
180 msm_mux_audio_sec_mclk_in1,
181 msm_mux_audio_sec_mclk_out1,
182 msm_mux_core_voltage_0,
183 msm_mux_core_voltage_1,
184 msm_mux_core_voltage_2,
185 msm_mux_core_voltage_3,
186 msm_mux_core_voltage_4,
187 msm_mux_cri_rng0,
188 msm_mux_cri_rng1,
189 msm_mux_cri_rng2,
190 msm_mux_dbg_out_clk,
191 msm_mux_gcc_plltest_bypassnl,
192 msm_mux_gcc_plltest_resetn,
193 msm_mux_gcc_tlmm,
194 msm_mux_gpio,
195 msm_mux_mdc_mst,
196 msm_mux_mdc_slv0,
197 msm_mux_mdc_slv1,
198 msm_mux_mdio_mst,
199 msm_mux_mdio_slv,
200 msm_mux_mdio_slv0,
201 msm_mux_mdio_slv1,
202 msm_mux_pcie0_clk_req_n,
203 msm_mux_pcie0_wake,
204 msm_mux_pcie1_clk_req_n,
205 msm_mux_pcie1_wake,
206 msm_mux_pcie2_clk_req_n,
207 msm_mux_pcie2_wake,
208 msm_mux_pcie3_clk_req_n,
209 msm_mux_pcie3_wake,
210 msm_mux_pcie4_clk_req_n,
211 msm_mux_pcie4_wake,
212 msm_mux_pll_bist_sync,
213 msm_mux_pll_test,
214 msm_mux_pwm,
215 msm_mux_qdss_cti_trig_in_a0,
216 msm_mux_qdss_cti_trig_in_a1,
217 msm_mux_qdss_cti_trig_in_b0,
218 msm_mux_qdss_cti_trig_in_b1,
219 msm_mux_qdss_cti_trig_out_a0,
220 msm_mux_qdss_cti_trig_out_a1,
221 msm_mux_qdss_cti_trig_out_b0,
222 msm_mux_qdss_cti_trig_out_b1,
223 msm_mux_qdss_traceclk_a,
224 msm_mux_qdss_tracectl_a,
225 msm_mux_qdss_tracedata_a,
226 msm_mux_qspi_data,
227 msm_mux_qspi_clk,
228 msm_mux_qspi_cs_n,
229 msm_mux_qup_se0,
230 msm_mux_qup_se1,
231 msm_mux_qup_se2,
232 msm_mux_qup_se3,
233 msm_mux_qup_se4,
234 msm_mux_qup_se5,
235 msm_mux_qup_se6,
236 msm_mux_qup_se7,
237 msm_mux_resout,
238 msm_mux_rx_los0,
239 msm_mux_rx_los1,
240 msm_mux_rx_los2,
241 msm_mux_sdc_clk,
242 msm_mux_sdc_cmd,
243 msm_mux_sdc_data,
244 msm_mux_tsens_max,
245 msm_mux_tsn,
246 msm_mux__,
247};
248
249static const char *const gpio_groups[] = {
250 "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6",
251 "gpio7", "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13",
252 "gpio14", "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20",
253 "gpio21", "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27",
254 "gpio28", "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34",
255 "gpio35", "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41",
256 "gpio42", "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48",
257 "gpio49", "gpio50", "gpio51", "gpio52", "gpio53",
258};
259
260static const char *const atest_char_start_groups[] = {
261 "gpio21",
262};
263
264static const char *const atest_char_status0_groups[] = {
265 "gpio33",
266};
267
268static const char *const atest_char_status1_groups[] = {
269 "gpio35",
270};
271
272static const char *const atest_char_status2_groups[] = {
273 "gpio22",
274};
275
276static const char *const atest_char_status3_groups[] = {
277 "gpio23",
278};
279
280static const char *const atest_tic_en_groups[] = {
281 "gpio53",
282};
283
284static const char *const audio_pri_mclk_in0_groups[] = {
285 "gpio53",
286};
287
288static const char *const audio_pri_mclk_out0_groups[] = {
289 "gpio53",
290};
291
292static const char *const audio_pri_mclk_in1_groups[] = {
293 "gpio51",
294};
295
296static const char *const audio_pri_mclk_out1_groups[] = {
297 "gpio51",
298};
299
300static const char *const audio_pri_groups[] = {
301 "gpio36", "gpio37", "gpio38", "gpio39",
302};
303
304static const char *const audio_sec_mclk_in0_groups[] = {
305 "gpio37",
306};
307
308static const char *const audio_sec_mclk_out0_groups[] = {
309 "gpio37",
310};
311
312static const char *const audio_sec_mclk_in1_groups[] = {
313 "gpio37",
314};
315
316static const char *const audio_sec_mclk_out1_groups[] = {
317 "gpio37",
318};
319
320static const char *const audio_sec_groups[] = {
321 "gpio45", "gpio46", "gpio47", "gpio48",
322};
323
324static const char *const core_voltage_0_groups[] = {
325 "gpio16",
326};
327
328static const char *const core_voltage_1_groups[] = {
329 "gpio17",
330};
331
332static const char *const core_voltage_2_groups[] = {
333 "gpio33",
334};
335
336static const char *const core_voltage_3_groups[] = {
337 "gpio34",
338};
339
340static const char *const core_voltage_4_groups[] = {
341 "gpio35",
342};
343
344static const char *const cri_rng0_groups[] = {
345 "gpio6",
346};
347
348static const char *const cri_rng1_groups[] = {
349 "gpio7",
350};
351
352static const char *const cri_rng2_groups[] = {
353 "gpio8",
354};
355
356static const char *const dbg_out_clk_groups[] = {
357 "gpio46",
358};
359
360static const char *const gcc_plltest_bypassnl_groups[] = {
361 "gpio33",
362};
363
364static const char *const gcc_plltest_resetn_groups[] = {
365 "gpio35",
366};
367
368static const char *const gcc_tlmm_groups[] = {
369 "gpio34",
370};
371
372static const char *const mdc_mst_groups[] = {
373 "gpio22",
374};
375
376static const char *const mdc_slv0_groups[] = {
377 "gpio20",
378};
379
380static const char *const mdc_slv1_groups[] = {
381 "gpio14",
382};
383
384static const char *const mdio_mst_groups[] = {
385 "gpio23",
386};
387
388static const char *const mdio_slv_groups[] = {
389 "gpio46",
390 "gpio47",
391};
392
393static const char *const mdio_slv0_groups[] = {
394 "gpio21",
395};
396
397static const char *const mdio_slv1_groups[] = {
398 "gpio15",
399};
400
401static const char *const pcie0_clk_req_n_groups[] = {
402 "gpio24",
403};
404
405static const char *const pcie0_wake_groups[] = {
406 "gpio26",
407};
408
409static const char *const pcie1_clk_req_n_groups[] = {
410 "gpio27",
411};
412
413static const char *const pcie1_wake_groups[] = {
414 "gpio29",
415};
416
417static const char *const pcie2_clk_req_n_groups[] = {
418 "gpio51",
419};
420
421static const char *const pcie2_wake_groups[] = {
422 "gpio53",
423};
424
425static const char *const pcie3_clk_req_n_groups[] = {
426 "gpio40",
427};
428
429static const char *const pcie3_wake_groups[] = {
430 "gpio42",
431};
432
433static const char *const pcie4_clk_req_n_groups[] = {
434 "gpio30",
435};
436
437static const char *const pcie4_wake_groups[] = {
438 "gpio32",
439};
440
441static const char *const pll_bist_sync_groups[] = {
442 "gpio47",
443};
444
445static const char *const pll_test_groups[] = {
446 "gpio39",
447};
448
449static const char *const pwm_groups[] = {
450 "gpio6", "gpio7", "gpio8", "gpio9", "gpio10", "gpio11", "gpio16",
451 "gpio17", "gpio33", "gpio34", "gpio35", "gpio43", "gpio44", "gpio45",
452 "gpio46", "gpio47", "gpio48",
453};
454
455static const char *const qdss_cti_trig_in_a0_groups[] = {
456 "gpio53",
457};
458
459static const char *const qdss_cti_trig_in_a1_groups[] = {
460 "gpio29",
461};
462
463static const char *const qdss_cti_trig_in_b0_groups[] = {
464 "gpio42",
465};
466
467static const char *const qdss_cti_trig_in_b1_groups[] = {
468 "gpio43",
469};
470
471static const char *const qdss_cti_trig_out_a0_groups[] = {
472 "gpio51",
473};
474
475static const char *const qdss_cti_trig_out_a1_groups[] = {
476 "gpio27",
477};
478
479static const char *const qdss_cti_trig_out_b0_groups[] = {
480 "gpio40",
481};
482
483static const char *const qdss_cti_trig_out_b1_groups[] = {
484 "gpio44",
485};
486
487static const char *const qdss_traceclk_a_groups[] = {
488 "gpio45",
489};
490
491static const char *const qdss_tracectl_a_groups[] = {
492 "gpio46",
493};
494
495static const char *const qdss_tracedata_a_groups[] = {
496 "gpio6", "gpio7", "gpio8", "gpio9", "gpio10", "gpio11",
497 "gpio12", "gpio13", "gpio14", "gpio15", "gpio20", "gpio21",
498 "gpio36", "gpio37", "gpio38", "gpio39",
499};
500
501static const char *const qspi_data_groups[] = {
502 "gpio0", "gpio1", "gpio2", "gpio3",
503};
504
505static const char *const qspi_clk_groups[] = {
506 "gpio5",
507};
508
509static const char *const qspi_cs_n_groups[] = {
510 "gpio4",
511};
512
513static const char *const qup_se0_groups[] = {
514 "gpio6", "gpio7", "gpio8", "gpio9", "gpio51", "gpio53",
515};
516
517static const char *const qup_se1_groups[] = {
518 "gpio10", "gpio11", "gpio12", "gpio13", "gpio27", "gpio29",
519};
520
521static const char *const qup_se2_groups[] = {
522 "gpio27", "gpio29", "gpio33", "gpio34",
523};
524
525static const char *const qup_se3_groups[] = {
526 "gpio16", "gpio17", "gpio20", "gpio21",
527};
528
529static const char *const qup_se4_groups[] = {
530 "gpio14", "gpio15", "gpio40", "gpio42", "gpio43", "gpio44",
531};
532
533static const char *const qup_se5_groups[] = {
534 "gpio40", "gpio42", "gpio45", "gpio46", "gpio47", "gpio48",
535};
536
537static const char *const qup_se6_groups[] = {
538 "gpio43", "gpio44", "gpio51", "gpio53",
539};
540
541static const char *const qup_se7_groups[] = {
542 "gpio36", "gpio37", "gpio38", "gpio39",
543};
544
545static const char *const resout_groups[] = {
546 "gpio49",
547};
548
549static const char *const rx_los0_groups[] = {
550 "gpio39", "gpio47", "gpio50",
551};
552
553static const char *const rx_los1_groups[] = {
554 "gpio38", "gpio46",
555};
556
557static const char *const rx_los2_groups[] = {
558 "gpio37", "gpio45",
559};
560
561static const char *const sdc_clk_groups[] = {
562 "gpio5",
563};
564
565static const char *const sdc_cmd_groups[] = {
566 "gpio4",
567};
568
569static const char *const sdc_data_groups[] = {
570 "gpio0", "gpio1", "gpio2", "gpio3",
571};
572
573static const char *const tsens_max_groups[] = {
574 "gpio14",
575};
576
577static const char *const tsn_groups[] = {
578 "gpio50",
579};
580
581static const struct pinfunction ipq9650_functions[] = {
582 MSM_PIN_FUNCTION(atest_char_start),
583 MSM_PIN_FUNCTION(atest_char_status0),
584 MSM_PIN_FUNCTION(atest_char_status1),
585 MSM_PIN_FUNCTION(atest_char_status2),
586 MSM_PIN_FUNCTION(atest_char_status3),
587 MSM_PIN_FUNCTION(atest_tic_en),
588 MSM_PIN_FUNCTION(audio_pri_mclk_in0),
589 MSM_PIN_FUNCTION(audio_pri_mclk_out0),
590 MSM_PIN_FUNCTION(audio_pri_mclk_in1),
591 MSM_PIN_FUNCTION(audio_pri_mclk_out1),
592 MSM_PIN_FUNCTION(audio_pri),
593 MSM_PIN_FUNCTION(audio_sec),
594 MSM_PIN_FUNCTION(audio_sec_mclk_in0),
595 MSM_PIN_FUNCTION(audio_sec_mclk_out0),
596 MSM_PIN_FUNCTION(audio_sec_mclk_in1),
597 MSM_PIN_FUNCTION(audio_sec_mclk_out1),
598 MSM_PIN_FUNCTION(core_voltage_0),
599 MSM_PIN_FUNCTION(core_voltage_1),
600 MSM_PIN_FUNCTION(core_voltage_2),
601 MSM_PIN_FUNCTION(core_voltage_3),
602 MSM_PIN_FUNCTION(core_voltage_4),
603 MSM_PIN_FUNCTION(cri_rng0),
604 MSM_PIN_FUNCTION(cri_rng1),
605 MSM_PIN_FUNCTION(cri_rng2),
606 MSM_PIN_FUNCTION(dbg_out_clk),
607 MSM_PIN_FUNCTION(gcc_plltest_bypassnl),
608 MSM_PIN_FUNCTION(gcc_plltest_resetn),
609 MSM_PIN_FUNCTION(gcc_tlmm),
610 MSM_GPIO_PIN_FUNCTION(gpio),
611 MSM_PIN_FUNCTION(mdc_mst),
612 MSM_PIN_FUNCTION(mdc_slv0),
613 MSM_PIN_FUNCTION(mdc_slv1),
614 MSM_PIN_FUNCTION(mdio_mst),
615 MSM_PIN_FUNCTION(mdio_slv),
616 MSM_PIN_FUNCTION(mdio_slv0),
617 MSM_PIN_FUNCTION(mdio_slv1),
618 MSM_PIN_FUNCTION(pcie0_clk_req_n),
619 MSM_PIN_FUNCTION(pcie0_wake),
620 MSM_PIN_FUNCTION(pcie1_clk_req_n),
621 MSM_PIN_FUNCTION(pcie1_wake),
622 MSM_PIN_FUNCTION(pcie2_clk_req_n),
623 MSM_PIN_FUNCTION(pcie2_wake),
624 MSM_PIN_FUNCTION(pcie3_clk_req_n),
625 MSM_PIN_FUNCTION(pcie3_wake),
626 MSM_PIN_FUNCTION(pcie4_clk_req_n),
627 MSM_PIN_FUNCTION(pcie4_wake),
628 MSM_PIN_FUNCTION(pll_bist_sync),
629 MSM_PIN_FUNCTION(pll_test),
630 MSM_PIN_FUNCTION(pwm),
631 MSM_PIN_FUNCTION(qdss_cti_trig_in_a0),
632 MSM_PIN_FUNCTION(qdss_cti_trig_in_a1),
633 MSM_PIN_FUNCTION(qdss_cti_trig_in_b0),
634 MSM_PIN_FUNCTION(qdss_cti_trig_in_b1),
635 MSM_PIN_FUNCTION(qdss_cti_trig_out_a0),
636 MSM_PIN_FUNCTION(qdss_cti_trig_out_a1),
637 MSM_PIN_FUNCTION(qdss_cti_trig_out_b0),
638 MSM_PIN_FUNCTION(qdss_cti_trig_out_b1),
639 MSM_PIN_FUNCTION(qdss_traceclk_a),
640 MSM_PIN_FUNCTION(qdss_tracectl_a),
641 MSM_PIN_FUNCTION(qdss_tracedata_a),
642 MSM_PIN_FUNCTION(qspi_data),
643 MSM_PIN_FUNCTION(qspi_clk),
644 MSM_PIN_FUNCTION(qspi_cs_n),
645 MSM_PIN_FUNCTION(qup_se0),
646 MSM_PIN_FUNCTION(qup_se1),
647 MSM_PIN_FUNCTION(qup_se2),
648 MSM_PIN_FUNCTION(qup_se3),
649 MSM_PIN_FUNCTION(qup_se4),
650 MSM_PIN_FUNCTION(qup_se5),
651 MSM_PIN_FUNCTION(qup_se6),
652 MSM_PIN_FUNCTION(qup_se7),
653 MSM_PIN_FUNCTION(resout),
654 MSM_PIN_FUNCTION(rx_los0),
655 MSM_PIN_FUNCTION(rx_los1),
656 MSM_PIN_FUNCTION(rx_los2),
657 MSM_PIN_FUNCTION(sdc_clk),
658 MSM_PIN_FUNCTION(sdc_cmd),
659 MSM_PIN_FUNCTION(sdc_data),
660 MSM_PIN_FUNCTION(tsens_max),
661 MSM_PIN_FUNCTION(tsn),
662};
663
664static const struct msm_pingroup ipq9650_groups[] = {
665 [0] = PINGROUP(0, sdc_data, qspi_data, _, _, _, _, _, _, _),
666 [1] = PINGROUP(1, sdc_data, qspi_data, _, _, _, _, _, _, _),
667 [2] = PINGROUP(2, sdc_data, qspi_data, _, _, _, _, _, _, _),
668 [3] = PINGROUP(3, sdc_data, qspi_data, _, _, _, _, _, _, _),
669 [4] = PINGROUP(4, sdc_cmd, qspi_cs_n, _, _, _, _, _, _, _),
670 [5] = PINGROUP(5, sdc_clk, qspi_clk, _, _, _, _, _, _, _),
671 [6] = PINGROUP(6, qup_se0, pwm, _, cri_rng0, qdss_tracedata_a, _, _, _, _),
672 [7] = PINGROUP(7, qup_se0, pwm, _, cri_rng1, qdss_tracedata_a, _, _, _, _),
673 [8] = PINGROUP(8, qup_se0, pwm, _, cri_rng2, qdss_tracedata_a, _, _, _, _),
674 [9] = PINGROUP(9, qup_se0, pwm, _, qdss_tracedata_a, _, _, _, _, _),
675 [10] = PINGROUP(10, qup_se1, pwm, _, _, qdss_tracedata_a, _, _, _, _),
676 [11] = PINGROUP(11, qup_se1, pwm, _, _, qdss_tracedata_a, _, _, _, _),
677 [12] = PINGROUP(12, qup_se1, _, qdss_tracedata_a, _, _, _, _, _, _),
678 [13] = PINGROUP(13, qup_se1, _, qdss_tracedata_a, _, _, _, _, _, _),
679 [14] = PINGROUP(14, qup_se4, mdc_slv1, tsens_max, _, qdss_tracedata_a, _, _, _, _),
680 [15] = PINGROUP(15, qup_se4, mdio_slv1, _, qdss_tracedata_a, _, _, _, _, _),
681 [16] = PINGROUP(16, core_voltage_0, qup_se3, pwm, _, _, _, _, _, _),
682 [17] = PINGROUP(17, core_voltage_1, qup_se3, pwm, _, _, _, _, _, _),
683 [18] = PINGROUP(18, _, _, _, _, _, _, _, _, _),
684 [19] = PINGROUP(19, _, _, _, _, _, _, _, _, _),
685 [20] = PINGROUP(20, mdc_slv0, qup_se3, _, qdss_tracedata_a, _, _, _, _, _),
686 [21] = PINGROUP(21, mdio_slv0, qup_se3, atest_char_start, _, qdss_tracedata_a, _, _, _, _),
687 [22] = PINGROUP(22, mdc_mst, atest_char_status2, _, _, _, _, _, _, _),
688 [23] = PINGROUP(23, mdio_mst, atest_char_status3, _, _, _, _, _, _, _),
689 [24] = PINGROUP(24, pcie0_clk_req_n, _, _, _, _, _, _, _, _),
690 [25] = PINGROUP(25, _, _, _, _, _, _, _, _, _),
691 [26] = PINGROUP(26, pcie0_wake, _, _, _, _, _, _, _, _),
692 [27] = PINGROUP(27, pcie1_clk_req_n, qup_se2, qup_se1, _, qdss_cti_trig_out_a1, _, _, _, _),
693 [28] = PINGROUP(28, _, _, _, _, _, _, _, _, _),
694 [29] = PINGROUP(29, pcie1_wake, qup_se2, qup_se1, _, qdss_cti_trig_in_a1, _, _, _, _),
695 [30] = PINGROUP(30, pcie4_clk_req_n, _, _, _, _, _, _, _, _),
696 [31] = PINGROUP(31, _, _, _, _, _, _, _, _, _),
697 [32] = PINGROUP(32, pcie4_wake, _, _, _, _, _, _, _, _),
698 [33] = PINGROUP(33, core_voltage_2, qup_se2, gcc_plltest_bypassnl, pwm, atest_char_status0, _, _, _, _),
699 [34] = PINGROUP(34, core_voltage_3, qup_se2, gcc_tlmm, pwm, _, _, _, _, _),
700 [35] = PINGROUP(35, core_voltage_4, gcc_plltest_resetn, pwm, atest_char_status1, _, _, _, _, _),
701 [36] = PINGROUP(36, audio_pri, qup_se7, qdss_tracedata_a, _, _, _, _, _, _),
702 [37] = PINGROUP(37, audio_pri, qup_se7, audio_sec_mclk_out0, audio_sec_mclk_in0, rx_los2, qdss_tracedata_a, _, _, _),
703 [38] = PINGROUP(38, audio_pri, qup_se7, rx_los1, qdss_tracedata_a, _, _, _, _, _),
704 [39] = PINGROUP(39, audio_pri, qup_se7, audio_sec_mclk_out1, audio_sec_mclk_in1, pll_test, rx_los0, _, qdss_tracedata_a, _),
705 [40] = PINGROUP(40, pcie3_clk_req_n, qup_se5, qup_se4, _, qdss_cti_trig_out_b0, _, _, _, _),
706 [41] = PINGROUP(41, _, _, _, _, _, _, _, _, _),
707 [42] = PINGROUP(42, pcie3_wake, qup_se5, qup_se4, _, qdss_cti_trig_in_b0, _, _, _, _),
708 [43] = PINGROUP(43, qup_se4, qup_se6, pwm, _, qdss_cti_trig_in_b1, _, _, _, _),
709 [44] = PINGROUP(44, qup_se4, qup_se6, pwm, _, qdss_cti_trig_out_b1, _, _, _, _),
710 [45] = PINGROUP(45, qup_se5, rx_los2, audio_sec, pwm, _, qdss_traceclk_a, _, _, _),
711 [46] = PINGROUP(46, qup_se5, rx_los1, audio_sec, mdio_slv, pwm, dbg_out_clk, qdss_tracectl_a, _, _),
712 [47] = PINGROUP(47, qup_se5, rx_los0, audio_sec, mdio_slv, pll_bist_sync, pwm, _, _, _),
713 [48] = PINGROUP(48, qup_se5, audio_sec, pwm, _, _, _, _, _, _),
714 [49] = PINGROUP(49, resout, _, _, _, _, _, _, _, _),
715 [50] = PINGROUP(50, tsn, rx_los0, _, _, _, _, _, _, _),
716 [51] = PINGROUP(51, pcie2_clk_req_n, qup_se6, qup_se0, audio_pri_mclk_out1, audio_pri_mclk_in1, qdss_cti_trig_out_a0, _, _, _),
717 [52] = PINGROUP(52, _, _, _, _, _, _, _, _, _),
718 [53] = PINGROUP(53, pcie2_wake, qup_se6, qup_se0, audio_pri_mclk_out0, audio_pri_mclk_in0, qdss_cti_trig_in_a0, _, atest_tic_en, _),
719};
720
721static const struct msm_pinctrl_soc_data ipq9650_tlmm = {
722 .pins = ipq9650_pins,
723 .npins = ARRAY_SIZE(ipq9650_pins),
724 .functions = ipq9650_functions,
725 .nfunctions = ARRAY_SIZE(ipq9650_functions),
726 .groups = ipq9650_groups,
727 .ngroups = ARRAY_SIZE(ipq9650_groups),
728 .ngpios = 54,
729};
730
731static const struct of_device_id ipq9650_tlmm_of_match[] = {
732 { .compatible = "qcom,ipq9650-tlmm", },
733 {},
734};
735
736static int ipq9650_tlmm_probe(struct platform_device *pdev)
737{
738 return msm_pinctrl_probe(pdev, &ipq9650_tlmm);
739}
740
741static struct platform_driver ipq9650_tlmm_driver = {
742 .driver = {
743 .name = "ipq9650-tlmm",
744 .of_match_table = ipq9650_tlmm_of_match,
745 },
746 .probe = ipq9650_tlmm_probe,
747};
748
749static int __init ipq9650_tlmm_init(void)
750{
751 return platform_driver_register(&ipq9650_tlmm_driver);
752}
753arch_initcall(ipq9650_tlmm_init);
754
755static void __exit ipq9650_tlmm_exit(void)
756{
757 platform_driver_unregister(&ipq9650_tlmm_driver);
758}
759module_exit(ipq9650_tlmm_exit);
760
761MODULE_DESCRIPTION("QTI IPQ9650 TLMM driver");
762MODULE_LICENSE("GPL");
drivers/pinctrl/qcom/pinctrl-kaanapali.c+1−1
@@ -1774,6 +1774,7 @@ static const struct of_device_id kaanapali_tlmm_of_match[] = { · 1773 unmodified lines
1774 { .compatible = "qcom,kaanapali-tlmm",},1774 { .compatible = "qcom,kaanapali-tlmm",},
1775 {},1775 {},
1776};1776};
1777MODULE_DEVICE_TABLE(of, kaanapali_tlmm_of_match);
1777 1778
1778static struct platform_driver kaanapali_tlmm_driver = {1779static struct platform_driver kaanapali_tlmm_driver = {
1779 .driver = {1780 .driver = {
@@ -1797,4 +1798,3 @@ module_exit(kaanapali_tlmm_exit); · 17 unmodified lines
1797 1798
1798MODULE_DESCRIPTION("QTI Kaanapali TLMM driver");1799MODULE_DESCRIPTION("QTI Kaanapali TLMM driver");
1799MODULE_LICENSE("GPL");1800MODULE_LICENSE("GPL");
1800MODULE_DEVICE_TABLE(of, kaanapali_tlmm_of_match);
drivers/pinctrl/qcom/pinctrl-lpass-lpi.c+88−48
@@ -11,10 +11,13 @@ · 10 unmodified lines
11#include <linux/of.h>11#include <linux/of.h>
12#include <linux/platform_device.h>12#include <linux/platform_device.h>
13#include <linux/seq_file.h>13#include <linux/seq_file.h>
14#include <linux/cleanup.h>
14 15
15#include <linux/pinctrl/pinconf-generic.h>16#include <linux/pinctrl/pinconf-generic.h>
16#include <linux/pinctrl/pinconf.h>17#include <linux/pinctrl/pinconf.h>
17#include <linux/pinctrl/pinmux.h>18#include <linux/pinctrl/pinmux.h>
19#include <linux/pm_clock.h>
20#include <linux/pm_runtime.h>
18 21
19#include "../pinctrl-utils.h"22#include "../pinctrl-utils.h"
20 23
@@ -22,7 +25,6 @@ · 1 unmodified line
22 25
23#define MAX_NR_GPIO 3226#define MAX_NR_GPIO 32
24#define GPIO_FUNC 027#define GPIO_FUNC 0
25#define MAX_LPI_NUM_CLKS 2
26 28
27struct lpi_pinctrl {29struct lpi_pinctrl {
28 struct device *dev;30 struct device *dev;
@@ -31,15 +33,14 @@ struct lpi_pinctrl { · 2 unmodified lines
31 struct pinctrl_desc desc;33 struct pinctrl_desc desc;
32 char __iomem *tlmm_base;34 char __iomem *tlmm_base;
33 char __iomem *slew_base;35 char __iomem *slew_base;
34 struct clk_bulk_data clks[MAX_LPI_NUM_CLKS];
35 /* Protects from concurrent register updates */36 /* Protects from concurrent register updates */
36 struct mutex lock;37 struct mutex lock;
37 DECLARE_BITMAP(ever_gpio, MAX_NR_GPIO);38 DECLARE_BITMAP(ever_gpio, MAX_NR_GPIO);
38 const struct lpi_pinctrl_variant_data *data;39 const struct lpi_pinctrl_variant_data *data;
39};40};
40 41
41static int lpi_gpio_read(struct lpi_pinctrl *state, unsigned int pin,42static void __iomem *lpi_gpio_reg(struct lpi_pinctrl *state,
42 unsigned int addr)43 unsigned int pin, unsigned int addr)
43{44{
44 u32 pin_offset;45 u32 pin_offset;
45 46
@@ -48,22 +49,34 @@ static int lpi_gpio_read(struct lpi_pinctrl *state, unsigned int pin, · 2 unmodified lines
48 else49 else
49 pin_offset = LPI_TLMM_REG_OFFSET * pin;50 pin_offset = LPI_TLMM_REG_OFFSET * pin;
50 51
51 return ioread32(state->tlmm_base + pin_offset + addr);52 return state->tlmm_base + pin_offset + addr;
52}53}
53 54
54static int lpi_gpio_write(struct lpi_pinctrl *state, unsigned int pin,55static void lpi_gpio_read_reg(struct lpi_pinctrl *state,
55 unsigned int addr, unsigned int val)56 unsigned int pin, unsigned int addr, u32 *val)
56{57{
57 u32 pin_offset;58 *val = ioread32(lpi_gpio_reg(state, pin, addr));
59}
58 60
59 if (state->data->flags & LPI_FLAG_USE_PREDEFINED_PIN_OFFSET)61static void lpi_gpio_write_reg(struct lpi_pinctrl *state,
60 pin_offset = state->data->groups[pin].pin_offset;62 unsigned int pin, unsigned int addr,
61 else63 unsigned int val)
62 pin_offset = LPI_TLMM_REG_OFFSET * pin;64{
65 iowrite32(val, lpi_gpio_reg(state, pin, addr));
66}
63 67
64 iowrite32(val, state->tlmm_base + pin_offset + addr);68static int lpi_gpio_read(struct lpi_pinctrl *state, unsigned int pin,
69 unsigned int addr, u32 *val)
70{
71 int ret;
65 72
66 return 0;73 ret = pm_runtime_resume_and_get(state->dev);
74 if (ret < 0)
75 return ret;
76
77 lpi_gpio_read_reg(state, pin, addr, val);
78
79 return pm_runtime_put_autosuspend(state->dev);
67}80}
68 81
69static const struct pinctrl_ops lpi_gpio_pinctrl_ops = {82static const struct pinctrl_ops lpi_gpio_pinctrl_ops = {
@@ -107,8 +120,8 @@ static int lpi_gpio_set_mux(struct pinctrl_dev *pctldev, unsigned int function, · 37 unmodified lines
107{120{
108 struct lpi_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);121 struct lpi_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
109 const struct lpi_pingroup *g = &pctrl->data->groups[group];122 const struct lpi_pingroup *g = &pctrl->data->groups[group];
110 u32 val;123 u32 io_val, val;
111 int i, pin = g->pin;124 int i, pin = g->pin, ret;
112 125
113 for (i = 0; i < g->nfuncs; i++) {126 for (i = 0; i < g->nfuncs; i++) {
114 if (g->funcs[i] == function)127 if (g->funcs[i] == function)
@@ -118,8 +131,12 @@ static int lpi_gpio_set_mux(struct pinctrl_dev *pctldev, unsigned int function, · 3 unmodified lines
118 if (WARN_ON(i == g->nfuncs))131 if (WARN_ON(i == g->nfuncs))
119 return -EINVAL;132 return -EINVAL;
120 133
121 mutex_lock(&pctrl->lock);134 ret = pm_runtime_resume_and_get(pctrl->dev);
122 val = lpi_gpio_read(pctrl, pin, LPI_GPIO_CFG_REG);135 if (ret < 0)
136 return ret;
137
138 guard(mutex)(&pctrl->lock);
139 lpi_gpio_read_reg(pctrl, pin, LPI_GPIO_CFG_REG, &val);
123 140
124 /*141 /*
125 * If this is the first time muxing to GPIO and the direction is142 * If this is the first time muxing to GPIO and the direction is
@@ -129,24 +146,25 @@ static int lpi_gpio_set_mux(struct pinctrl_dev *pctldev, unsigned int function, · 3 unmodified lines
129 */146 */
130 if (i == GPIO_FUNC && (val & LPI_GPIO_OE_MASK) &&147 if (i == GPIO_FUNC && (val & LPI_GPIO_OE_MASK) &&
131 !test_and_set_bit(group, pctrl->ever_gpio)) {148 !test_and_set_bit(group, pctrl->ever_gpio)) {
132 u32 io_val = lpi_gpio_read(pctrl, group, LPI_GPIO_VALUE_REG);149 lpi_gpio_read_reg(pctrl, group, LPI_GPIO_VALUE_REG, &io_val);
133 150
134 if (io_val & LPI_GPIO_VALUE_IN_MASK) {151 if (io_val & LPI_GPIO_VALUE_IN_MASK) {
135 if (!(io_val & LPI_GPIO_VALUE_OUT_MASK))152 if (!(io_val & LPI_GPIO_VALUE_OUT_MASK))
136 lpi_gpio_write(pctrl, group, LPI_GPIO_VALUE_REG,153 lpi_gpio_write_reg(pctrl, group,
137 io_val | LPI_GPIO_VALUE_OUT_MASK);154 LPI_GPIO_VALUE_REG,
155 io_val | LPI_GPIO_VALUE_OUT_MASK);
138 } else {156 } else {
139 if (io_val & LPI_GPIO_VALUE_OUT_MASK)157 if (io_val & LPI_GPIO_VALUE_OUT_MASK)
140 lpi_gpio_write(pctrl, group, LPI_GPIO_VALUE_REG,158 lpi_gpio_write_reg(pctrl, group,
141 io_val & ~LPI_GPIO_VALUE_OUT_MASK);159 LPI_GPIO_VALUE_REG,
160 io_val & ~LPI_GPIO_VALUE_OUT_MASK);
142 }161 }
143 }162 }
144 163
145 u32p_replace_bits(&val, i, LPI_GPIO_FUNCTION_MASK);164 u32p_replace_bits(&val, i, LPI_GPIO_FUNCTION_MASK);
146 lpi_gpio_write(pctrl, pin, LPI_GPIO_CFG_REG, val);165 lpi_gpio_write_reg(pctrl, pin, LPI_GPIO_CFG_REG, val);
147 mutex_unlock(&pctrl->lock);
148 166
149 return 0;167 return pm_runtime_put_autosuspend(pctrl->dev);
150}168}
151 169
152static const struct pinmux_ops lpi_gpio_pinmux_ops = {170static const struct pinmux_ops lpi_gpio_pinmux_ops = {
@@ -162,11 +180,15 @@ static int lpi_config_get(struct pinctrl_dev *pctldev, · 9 unmodified lines
162 unsigned int param = pinconf_to_config_param(*config);180 unsigned int param = pinconf_to_config_param(*config);
163 struct lpi_pinctrl *state = dev_get_drvdata(pctldev->dev);181 struct lpi_pinctrl *state = dev_get_drvdata(pctldev->dev);
164 unsigned int arg = 0;182 unsigned int arg = 0;
183 u32 ctl_reg;
165 int is_out;184 int is_out;
166 int pull;185 int pull;
167 u32 ctl_reg;186 int ret;
187
188 ret = lpi_gpio_read(state, pin, LPI_GPIO_CFG_REG, &ctl_reg);
189 if (ret)
190 return ret;
168 191
169 ctl_reg = lpi_gpio_read(state, pin, LPI_GPIO_CFG_REG);
170 is_out = ctl_reg & LPI_GPIO_OE_MASK;192 is_out = ctl_reg & LPI_GPIO_OE_MASK;
171 pull = FIELD_GET(LPI_GPIO_PULL_MASK, ctl_reg);193 pull = FIELD_GET(LPI_GPIO_PULL_MASK, ctl_reg);
172 194
@@ -197,6 +219,7 @@ static int lpi_config_get(struct pinctrl_dev *pctldev, · 24 unmodified lines
197 }219 }
198 220
199 *config = pinconf_to_config_packed(param, arg);221 *config = pinconf_to_config_packed(param, arg);
222
200 return 0;223 return 0;
201}224}
202 225
@@ -206,7 +229,7 @@ static int lpi_config_set_slew_rate(struct lpi_pinctrl *pctrl, · 3 unmodified lines
206{229{
207 unsigned long sval;230 unsigned long sval;
208 void __iomem *reg;231 void __iomem *reg;
209 int slew_offset;232 int slew_offset, ret;
210 233
211 if (slew > LPI_SLEW_RATE_MAX) {234 if (slew > LPI_SLEW_RATE_MAX) {
212 dev_err(pctrl->dev, "invalid slew rate %u for pin: %d\n",235 dev_err(pctrl->dev, "invalid slew rate %u for pin: %d\n",
@@ -220,9 +243,15 @@ static int lpi_config_set_slew_rate(struct lpi_pinctrl *pctrl, · 7 unmodified lines
220 243
221 if (pctrl->data->flags & LPI_FLAG_SLEW_RATE_SAME_REG)244 if (pctrl->data->flags & LPI_FLAG_SLEW_RATE_SAME_REG)
222 reg = pctrl->tlmm_base + LPI_TLMM_REG_OFFSET * group + LPI_GPIO_CFG_REG;245 reg = pctrl->tlmm_base + LPI_TLMM_REG_OFFSET * group + LPI_GPIO_CFG_REG;
246 else if (g->slew_base_spare_1)
247 reg = pctrl->slew_base + LPI_SPARE_1_REG;
223 else248 else
224 reg = pctrl->slew_base + LPI_SLEW_RATE_CTL_REG;249 reg = pctrl->slew_base + LPI_SLEW_RATE_CTL_REG;
225 250
251 ret = pm_runtime_resume_and_get(pctrl->dev);
252 if (ret < 0)
253 return ret;
254
226 mutex_lock(&pctrl->lock);255 mutex_lock(&pctrl->lock);
227 256
228 sval = ioread32(reg);257 sval = ioread32(reg);
@@ -232,7 +261,7 @@ static int lpi_config_set_slew_rate(struct lpi_pinctrl *pctrl, · 3 unmodified lines
232 261
233 mutex_unlock(&pctrl->lock);262 mutex_unlock(&pctrl->lock);
234 263
235 return 0;264 return pm_runtime_put_autosuspend(pctrl->dev);
236}265}
237 266
238static int lpi_config_set(struct pinctrl_dev *pctldev, unsigned int group,267static int lpi_config_set(struct pinctrl_dev *pctldev, unsigned int group,
@@ -242,8 +271,8 @@ static int lpi_config_set(struct pinctrl_dev *pctldev, unsigned int group, · 3 unmodified lines
242 unsigned int param, arg, pullup = LPI_GPIO_BIAS_DISABLE, strength = 2;271 unsigned int param, arg, pullup = LPI_GPIO_BIAS_DISABLE, strength = 2;
243 bool value, output_enabled = false;272 bool value, output_enabled = false;
244 const struct lpi_pingroup *g;273 const struct lpi_pingroup *g;
245 int i, ret;
246 u32 val;274 u32 val;
275 int i, ret;
247 276
248 g = &pctrl->data->groups[group];277 g = &pctrl->data->groups[group];
249 for (i = 0; i < nconfs; i++) {278 for (i = 0; i < nconfs; i++) {
@@ -287,23 +316,26 @@ static int lpi_config_set(struct pinctrl_dev *pctldev, unsigned int group, · 37 unmodified lines
287 * As per Hardware Programming Guide, when configuring pin as output,316 * As per Hardware Programming Guide, when configuring pin as output,
288 * set the pin value before setting output-enable (OE).317 * set the pin value before setting output-enable (OE).
289 */318 */
319 ret = pm_runtime_resume_and_get(pctrl->dev);
320 if (ret < 0)
321 return ret;
322
323 guard(mutex)(&pctrl->lock);
290 if (output_enabled) {324 if (output_enabled) {
291 val = u32_encode_bits(value ? 1 : 0, LPI_GPIO_VALUE_OUT_MASK);325 val = u32_encode_bits(value ? 1 : 0, LPI_GPIO_VALUE_OUT_MASK);
292 lpi_gpio_write(pctrl, group, LPI_GPIO_VALUE_REG, val);326 lpi_gpio_write_reg(pctrl, group, LPI_GPIO_VALUE_REG, val);
293 }327 }
294 328
295 mutex_lock(&pctrl->lock);329 lpi_gpio_read_reg(pctrl, group, LPI_GPIO_CFG_REG, &val);
296 val = lpi_gpio_read(pctrl, group, LPI_GPIO_CFG_REG);
297 330
298 u32p_replace_bits(&val, pullup, LPI_GPIO_PULL_MASK);331 u32p_replace_bits(&val, pullup, LPI_GPIO_PULL_MASK);
299 u32p_replace_bits(&val, LPI_GPIO_DS_TO_VAL(strength),332 u32p_replace_bits(&val, LPI_GPIO_DS_TO_VAL(strength),
300 LPI_GPIO_OUT_STRENGTH_MASK);333 LPI_GPIO_OUT_STRENGTH_MASK);
301 u32p_replace_bits(&val, output_enabled, LPI_GPIO_OE_MASK);334 u32p_replace_bits(&val, output_enabled, LPI_GPIO_OE_MASK);
302 335
303 lpi_gpio_write(pctrl, group, LPI_GPIO_CFG_REG, val);336 lpi_gpio_write_reg(pctrl, group, LPI_GPIO_CFG_REG, val);
304 mutex_unlock(&pctrl->lock);
305 337
306 return 0;338 return pm_runtime_put_autosuspend(pctrl->dev);
307}339}
308 340
309static const struct pinconf_ops lpi_gpio_pinconf_ops = {341static const struct pinconf_ops lpi_gpio_pinconf_ops = {
@@ -352,9 +384,14 @@ static int lpi_gpio_direction_output(struct gpio_chip *chip, · 42 unmodified lines
352static int lpi_gpio_get(struct gpio_chip *chip, unsigned int pin)384static int lpi_gpio_get(struct gpio_chip *chip, unsigned int pin)
353{385{
354 struct lpi_pinctrl *state = gpiochip_get_data(chip);386 struct lpi_pinctrl *state = gpiochip_get_data(chip);
387 u32 val;
388 int ret;
389
390 ret = lpi_gpio_read(state, pin, LPI_GPIO_VALUE_REG, &val);
391 if (ret)
392 return ret;
355 393
356 return lpi_gpio_read(state, pin, LPI_GPIO_VALUE_REG) &394 return val & LPI_GPIO_VALUE_IN_MASK;
357 LPI_GPIO_VALUE_IN_MASK;
358}395}
359 396
360static int lpi_gpio_set(struct gpio_chip *chip, unsigned int pin, int value)397static int lpi_gpio_set(struct gpio_chip *chip, unsigned int pin, int value)
@@ -397,7 +434,9 @@ static void lpi_gpio_dbg_show_one(struct seq_file *s, · 36 unmodified lines
397 434
398 pctldev = pctldev ? : state->ctrl;435 pctldev = pctldev ? : state->ctrl;
399 pindesc = pctldev->desc->pins[offset];436 pindesc = pctldev->desc->pins[offset];
400 ctl_reg = lpi_gpio_read(state, offset, LPI_GPIO_CFG_REG);437 if (lpi_gpio_read(state, offset, LPI_GPIO_CFG_REG, &ctl_reg))
438 return;
439
401 is_out = ctl_reg & LPI_GPIO_OE_MASK;440 is_out = ctl_reg & LPI_GPIO_OE_MASK;
402 441
403 func = FIELD_GET(LPI_GPIO_FUNCTION_MASK, ctl_reg);442 func = FIELD_GET(LPI_GPIO_FUNCTION_MASK, ctl_reg);
@@ -480,9 +519,6 @@ int lpi_pinctrl_probe(struct platform_device *pdev) · 76 unmodified lines
480 pctrl->data = data;519 pctrl->data = data;
481 pctrl->dev = &pdev->dev;520 pctrl->dev = &pdev->dev;
482 521
483 pctrl->clks[0].id = "core";
484 pctrl->clks[1].id = "audio";
485
486 pctrl->tlmm_base = devm_platform_ioremap_resource(pdev, 0);522 pctrl->tlmm_base = devm_platform_ioremap_resource(pdev, 0);
487 if (IS_ERR(pctrl->tlmm_base))523 if (IS_ERR(pctrl->tlmm_base))
488 return dev_err_probe(dev, PTR_ERR(pctrl->tlmm_base),524 return dev_err_probe(dev, PTR_ERR(pctrl->tlmm_base),
@@ -495,13 +531,19 @@ int lpi_pinctrl_probe(struct platform_device *pdev) · 6 unmodified lines
495 "Slew resource not provided\n");531 "Slew resource not provided\n");
496 }532 }
497 533
498 ret = devm_clk_bulk_get_optional(dev, MAX_LPI_NUM_CLKS, pctrl->clks);534 ret = devm_pm_clk_create(dev);
499 if (ret)535 if (ret)
500 return ret;536 return ret;
501 537
502 ret = clk_bulk_prepare_enable(MAX_LPI_NUM_CLKS, pctrl->clks);538 ret = of_pm_clk_add_clks(dev);
539 if (ret < 0 && ret != -ENODEV)
540 return ret;
541
542 pm_runtime_set_autosuspend_delay(dev, 100);
543 pm_runtime_use_autosuspend(dev);
544 ret = devm_pm_runtime_enable(dev);
503 if (ret)545 if (ret)
504 return dev_err_probe(dev, ret, "Can't enable clocks\n");546 return ret;
505 547
506 pctrl->desc.pctlops = &lpi_gpio_pinctrl_ops;548 pctrl->desc.pctlops = &lpi_gpio_pinctrl_ops;
507 pctrl->desc.pmxops = &lpi_gpio_pinmux_ops;549 pctrl->desc.pmxops = &lpi_gpio_pinmux_ops;
@@ -540,7 +582,6 @@ int lpi_pinctrl_probe(struct platform_device *pdev) · 32 unmodified lines
540 582
541err_pinctrl:583err_pinctrl:
542 mutex_destroy(&pctrl->lock);584 mutex_destroy(&pctrl->lock);
543 clk_bulk_disable_unprepare(MAX_LPI_NUM_CLKS, pctrl->clks);
544 585
545 return ret;586 return ret;
546}587}
@@ -552,7 +593,6 @@ void lpi_pinctrl_remove(struct platform_device *pdev) · 5 unmodified lines
552 int i;593 int i;
553 594
554 mutex_destroy(&pctrl->lock);595 mutex_destroy(&pctrl->lock);
555 clk_bulk_disable_unprepare(MAX_LPI_NUM_CLKS, pctrl->clks);
556 596
557 for (i = 0; i < pctrl->data->npins; i++)597 for (i = 0; i < pctrl->data->npins; i++)
558 pinctrl_generic_remove_group(pctrl->ctrl, i);598 pinctrl_generic_remove_group(pctrl->ctrl, i);
drivers/pinctrl/qcom/pinctrl-lpass-lpi.h+20−0
@@ -16,6 +16,7 @@ struct platform_device; · 15 unmodified lines
16struct pinctrl_pin_desc;16struct pinctrl_pin_desc;
17 17
18#define LPI_SLEW_RATE_CTL_REG 0xa00018#define LPI_SLEW_RATE_CTL_REG 0xa000
19#define LPI_SPARE_1_REG 0xc000
19#define LPI_TLMM_REG_OFFSET 0x100020#define LPI_TLMM_REG_OFFSET 0x1000
20#define LPI_SLEW_RATE_MAX 0x0321#define LPI_SLEW_RATE_MAX 0x03
21#define LPI_SLEW_BITS_SIZE 0x0222#define LPI_SLEW_BITS_SIZE 0x02
@@ -47,6 +48,7 @@ struct pinctrl_pin_desc; · 25 unmodified lines
47 { \48 { \
48 .pin = id, \49 .pin = id, \
49 .slew_offset = soff, \50 .slew_offset = soff, \
51 .slew_base_spare_1 = false, \
50 .funcs = (int[]){ \52 .funcs = (int[]){ \
51 LPI_MUX_gpio, \53 LPI_MUX_gpio, \
52 LPI_MUX_##f1, \54 LPI_MUX_##f1, \
@@ -62,6 +64,7 @@ struct pinctrl_pin_desc; · 9 unmodified lines
62 { \64 { \
63 .pin = id, \65 .pin = id, \
64 .slew_offset = soff, \66 .slew_offset = soff, \
67 .slew_base_spare_1 = false, \
65 .funcs = (int[]){ \68 .funcs = (int[]){ \
66 LPI_MUX_gpio, \69 LPI_MUX_gpio, \
67 LPI_MUX_##f1, \70 LPI_MUX_##f1, \
@@ -73,6 +76,22 @@ struct pinctrl_pin_desc; · 5 unmodified lines
73 .pin_offset = poff, \76 .pin_offset = poff, \
74 }77 }
75 78
79#define LPI_PINGROUP_SLEW_SPARE_1(id, soff, f1, f2, f3, f4) \
80 { \
81 .pin = id, \
82 .slew_offset = soff, \
83 .slew_base_spare_1 = true, \
84 .funcs = (int[]){ \
85 LPI_MUX_gpio, \
86 LPI_MUX_##f1, \
87 LPI_MUX_##f2, \
88 LPI_MUX_##f3, \
89 LPI_MUX_##f4, \
90 }, \
91 .nfuncs = 5, \
92 .pin_offset = 0, \
93 }
94
76/*95/*
77 * Slew rate control is done in the same register as rest of the96 * Slew rate control is done in the same register as rest of the
78 * pin configuration.97 * pin configuration.
@@ -87,6 +106,7 @@ struct lpi_pingroup { · 8 unmodified lines
87 unsigned int *funcs;106 unsigned int *funcs;
88 unsigned int nfuncs;107 unsigned int nfuncs;
89 unsigned int pin_offset;108 unsigned int pin_offset;
109 bool slew_base_spare_1;
90};110};
91 111
92struct lpi_function {112struct lpi_function {
drivers/pinctrl/qcom/pinctrl-mdm9607.c+1−1
@@ -1050,6 +1050,7 @@ static const struct of_device_id mdm9607_pinctrl_of_match[] = { · 1049 unmodified lines
1050 { .compatible = "qcom,mdm9607-tlmm", },1050 { .compatible = "qcom,mdm9607-tlmm", },
1051 { }1051 { }
1052};1052};
1053MODULE_DEVICE_TABLE(of, mdm9607_pinctrl_of_match);
1053 1054
1054static struct platform_driver mdm9607_pinctrl_driver = {1055static struct platform_driver mdm9607_pinctrl_driver = {
1055 .driver = {1056 .driver = {
@@ -1073,4 +1074,3 @@ module_exit(mdm9607_pinctrl_exit); · 17 unmodified lines
1073 1074
1074MODULE_DESCRIPTION("Qualcomm mdm9607 pinctrl driver");1075MODULE_DESCRIPTION("Qualcomm mdm9607 pinctrl driver");
1075MODULE_LICENSE("GPL v2");1076MODULE_LICENSE("GPL v2");
1076MODULE_DEVICE_TABLE(of, mdm9607_pinctrl_of_match);
drivers/pinctrl/qcom/pinctrl-mdm9615.c+1−1
@@ -439,6 +439,7 @@ static const struct of_device_id mdm9615_pinctrl_of_match[] = { · 438 unmodified lines
439 { .compatible = "qcom,mdm9615-pinctrl", },439 { .compatible = "qcom,mdm9615-pinctrl", },
440 { },440 { },
441};441};
442MODULE_DEVICE_TABLE(of, mdm9615_pinctrl_of_match);
442 443
443static struct platform_driver mdm9615_pinctrl_driver = {444static struct platform_driver mdm9615_pinctrl_driver = {
444 .driver = {445 .driver = {
@@ -463,4 +464,3 @@ module_exit(mdm9615_pinctrl_exit); · 18 unmodified lines
463MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");464MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
464MODULE_DESCRIPTION("Qualcomm MDM9615 pinctrl driver");465MODULE_DESCRIPTION("Qualcomm MDM9615 pinctrl driver");
465MODULE_LICENSE("GPL v2");466MODULE_LICENSE("GPL v2");
466MODULE_DEVICE_TABLE(of, mdm9615_pinctrl_of_match);
drivers/pinctrl/qcom/pinctrl-milos-lpass-lpi.c+7−0
@@ -7,6 +7,8 @@ · 6 unmodified lines
7#include <linux/gpio/driver.h>7#include <linux/gpio/driver.h>
8#include <linux/module.h>8#include <linux/module.h>
9#include <linux/platform_device.h>9#include <linux/platform_device.h>
10#include <linux/pm_clock.h>
11#include <linux/pm_runtime.h>
10 12
11#include "pinctrl-lpass-lpi.h"13#include "pinctrl-lpass-lpi.h"
12 14
@@ -203,10 +205,15 @@ static const struct of_device_id lpi_pinctrl_of_match[] = { · 190 unmodified lines
203};205};
204MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match);206MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match);
205 207
208static const struct dev_pm_ops lpi_pinctrl_pm_ops = {
209 RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL)
210};
211
206static struct platform_driver lpi_pinctrl_driver = {212static struct platform_driver lpi_pinctrl_driver = {
207 .driver = {213 .driver = {
208 .name = "qcom-milos-lpass-lpi-pinctrl",214 .name = "qcom-milos-lpass-lpi-pinctrl",
209 .of_match_table = lpi_pinctrl_of_match,215 .of_match_table = lpi_pinctrl_of_match,
216 .pm = pm_ptr(&lpi_pinctrl_pm_ops),
210 },217 },
211 .probe = lpi_pinctrl_probe,218 .probe = lpi_pinctrl_probe,
212 .remove = lpi_pinctrl_remove,219 .remove = lpi_pinctrl_remove,
drivers/pinctrl/qcom/pinctrl-milos.c+1−1
@@ -1310,6 +1310,7 @@ static const struct of_device_id milos_tlmm_of_match[] = { · 1309 unmodified lines
1310 { .compatible = "qcom,milos-tlmm" },1310 { .compatible = "qcom,milos-tlmm" },
1311 { /* sentinel */ }1311 { /* sentinel */ }
1312};1312};
1313MODULE_DEVICE_TABLE(of, milos_tlmm_of_match);
1313 1314
1314static struct platform_driver milos_tlmm_driver = {1315static struct platform_driver milos_tlmm_driver = {
1315 .driver = {1316 .driver = {
@@ -1333,4 +1334,3 @@ module_exit(milos_tlmm_exit); · 17 unmodified lines
1333 1334
1334MODULE_DESCRIPTION("QTI Milos TLMM driver");1335MODULE_DESCRIPTION("QTI Milos TLMM driver");
1335MODULE_LICENSE("GPL");1336MODULE_LICENSE("GPL");
1336MODULE_DEVICE_TABLE(of, milos_tlmm_of_match);
drivers/pinctrl/qcom/pinctrl-msm.c+12−9
@@ -1012,10 +1012,8 @@ static void msm_gpio_irq_ack(struct irq_data *d) · 1011 unmodified lines
1012 1012
1013static void msm_gpio_irq_eoi(struct irq_data *d)1013static void msm_gpio_irq_eoi(struct irq_data *d)
1014{1014{
1015 d = d->parent_data;1015 if (d->parent_data)
1016 1016 irq_chip_eoi_parent(d);
1017 if (d)
1018 d->chip->irq_eoi(d);
1019}1017}
1020 1018
1021static bool msm_gpio_needs_dual_edge_parent_workaround(struct irq_data *d,1019static bool msm_gpio_needs_dual_edge_parent_workaround(struct irq_data *d,
@@ -1593,11 +1591,11 @@ int msm_pinctrl_probe(struct platform_device *pdev, · 571 unmodified lines
1593 pctrl->desc.pins = pctrl->soc->pins;1591 pctrl->desc.pins = pctrl->soc->pins;
1594 pctrl->desc.npins = pctrl->soc->npins;1592 pctrl->desc.npins = pctrl->soc->npins;
1595 1593
1596 pctrl->pctrl = devm_pinctrl_register(&pdev->dev, &pctrl->desc, pctrl);1594 ret = devm_pinctrl_register_and_init(&pdev->dev, &pctrl->desc,
1597 if (IS_ERR(pctrl->pctrl)) {1595 pctrl, &pctrl->pctrl);
1598 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");1596 if (ret)
1599 return PTR_ERR(pctrl->pctrl);1597 return dev_err_probe(&pdev->dev, ret,
1600 }1598 "Couldn't register pinctrl driver\n");
1601 1599
1602 for (i = 0; i < soc_data->nfunctions; i++) {1600 for (i = 0; i < soc_data->nfunctions; i++) {
1603 func = &soc_data->functions[i];1601 func = &soc_data->functions[i];
@@ -1607,6 +1605,11 @@ int msm_pinctrl_probe(struct platform_device *pdev, · 3 unmodified lines
1607 return ret;1605 return ret;
1608 }1606 }
1609 1607
1608 ret = pinctrl_enable(pctrl->pctrl);
1609 if (ret)
1610 return dev_err_probe(&pdev->dev, ret,
1611 "Couldn't enable pinctrl driver\n");
1612
1610 ret = msm_gpio_init(pctrl);1613 ret = msm_gpio_init(pctrl);
1611 if (ret)1614 if (ret)
1612 return ret;1615 return ret;
drivers/pinctrl/qcom/pinctrl-msm8226.c+1−1
@@ -645,6 +645,7 @@ static const struct of_device_id msm8226_pinctrl_of_match[] = { · 644 unmodified lines
645 { .compatible = "qcom,msm8226-pinctrl", },645 { .compatible = "qcom,msm8226-pinctrl", },
646 { },646 { },
647};647};
648MODULE_DEVICE_TABLE(of, msm8226_pinctrl_of_match);
648 649
649static struct platform_driver msm8226_pinctrl_driver = {650static struct platform_driver msm8226_pinctrl_driver = {
650 .driver = {651 .driver = {
@@ -669,4 +670,3 @@ module_exit(msm8226_pinctrl_exit); · 18 unmodified lines
669MODULE_AUTHOR("Bartosz Dudziak <bartosz.dudziak@snejp.pl>");670MODULE_AUTHOR("Bartosz Dudziak <bartosz.dudziak@snejp.pl>");
670MODULE_DESCRIPTION("Qualcomm MSM8226 pinctrl driver");671MODULE_DESCRIPTION("Qualcomm MSM8226 pinctrl driver");
671MODULE_LICENSE("GPL v2");672MODULE_LICENSE("GPL v2");
672MODULE_DEVICE_TABLE(of, msm8226_pinctrl_of_match);
drivers/pinctrl/qcom/pinctrl-msm8660.c+1−1
@@ -974,6 +974,7 @@ static const struct of_device_id msm8660_pinctrl_of_match[] = { · 973 unmodified lines
974 { .compatible = "qcom,msm8660-pinctrl", },974 { .compatible = "qcom,msm8660-pinctrl", },
975 { },975 { },
976};976};
977MODULE_DEVICE_TABLE(of, msm8660_pinctrl_of_match);
977 978
978static struct platform_driver msm8660_pinctrl_driver = {979static struct platform_driver msm8660_pinctrl_driver = {
979 .driver = {980 .driver = {
@@ -998,4 +999,3 @@ module_exit(msm8660_pinctrl_exit); · 18 unmodified lines
998MODULE_AUTHOR("Bjorn Andersson <bjorn.andersson@sonymobile.com>");999MODULE_AUTHOR("Bjorn Andersson <bjorn.andersson@sonymobile.com>");
999MODULE_DESCRIPTION("Qualcomm MSM8660 pinctrl driver");1000MODULE_DESCRIPTION("Qualcomm MSM8660 pinctrl driver");
1000MODULE_LICENSE("GPL v2");1001MODULE_LICENSE("GPL v2");
1001MODULE_DEVICE_TABLE(of, msm8660_pinctrl_of_match);
drivers/pinctrl/qcom/pinctrl-msm8916.c+1−1
@@ -960,6 +960,7 @@ static const struct of_device_id msm8916_pinctrl_of_match[] = { · 959 unmodified lines
960 { .compatible = "qcom,msm8916-pinctrl", },960 { .compatible = "qcom,msm8916-pinctrl", },
961 { },961 { },
962};962};
963MODULE_DEVICE_TABLE(of, msm8916_pinctrl_of_match);
963 964
964static struct platform_driver msm8916_pinctrl_driver = {965static struct platform_driver msm8916_pinctrl_driver = {
965 .driver = {966 .driver = {
@@ -983,4 +984,3 @@ module_exit(msm8916_pinctrl_exit); · 17 unmodified lines
983 984
984MODULE_DESCRIPTION("Qualcomm msm8916 pinctrl driver");985MODULE_DESCRIPTION("Qualcomm msm8916 pinctrl driver");
985MODULE_LICENSE("GPL v2");986MODULE_LICENSE("GPL v2");
986MODULE_DEVICE_TABLE(of, msm8916_pinctrl_of_match);
drivers/pinctrl/qcom/pinctrl-msm8953.c+1−1
@@ -1807,6 +1807,7 @@ static const struct of_device_id msm8953_pinctrl_of_match[] = { · 1806 unmodified lines
1807 { .compatible = "qcom,msm8953-pinctrl", },1807 { .compatible = "qcom,msm8953-pinctrl", },
1808 { },1808 { },
1809};1809};
1810MODULE_DEVICE_TABLE(of, msm8953_pinctrl_of_match);
1810 1811
1811static struct platform_driver msm8953_pinctrl_driver = {1812static struct platform_driver msm8953_pinctrl_driver = {
1812 .driver = {1813 .driver = {
@@ -1830,4 +1831,3 @@ module_exit(msm8953_pinctrl_exit); · 17 unmodified lines
1830 1831
1831MODULE_DESCRIPTION("QTI msm8953 pinctrl driver");1832MODULE_DESCRIPTION("QTI msm8953 pinctrl driver");
1832MODULE_LICENSE("GPL v2");1833MODULE_LICENSE("GPL v2");
1833MODULE_DEVICE_TABLE(of, msm8953_pinctrl_of_match);
drivers/pinctrl/qcom/pinctrl-msm8960.c+1−1
@@ -1239,6 +1239,7 @@ static const struct of_device_id msm8960_pinctrl_of_match[] = { · 1238 unmodified lines
1239 { .compatible = "qcom,msm8960-pinctrl", },1239 { .compatible = "qcom,msm8960-pinctrl", },
1240 { },1240 { },
1241};1241};
1242MODULE_DEVICE_TABLE(of, msm8960_pinctrl_of_match);
1242 1243
1243static struct platform_driver msm8960_pinctrl_driver = {1244static struct platform_driver msm8960_pinctrl_driver = {
1244 .driver = {1245 .driver = {
@@ -1263,4 +1264,3 @@ module_exit(msm8960_pinctrl_exit); · 18 unmodified lines
1263MODULE_AUTHOR("Bjorn Andersson <bjorn.andersson@sonymobile.com>");1264MODULE_AUTHOR("Bjorn Andersson <bjorn.andersson@sonymobile.com>");
1264MODULE_DESCRIPTION("Qualcomm MSM8960 pinctrl driver");1265MODULE_DESCRIPTION("Qualcomm MSM8960 pinctrl driver");
1265MODULE_LICENSE("GPL v2");1266MODULE_LICENSE("GPL v2");
1266MODULE_DEVICE_TABLE(of, msm8960_pinctrl_of_match);
drivers/pinctrl/qcom/pinctrl-msm8976.c+1−1
@@ -1087,6 +1087,7 @@ static const struct of_device_id msm8976_pinctrl_of_match[] = { · 1086 unmodified lines
1087 { .compatible = "qcom,msm8976-pinctrl", },1087 { .compatible = "qcom,msm8976-pinctrl", },
1088 { },1088 { },
1089};1089};
1090MODULE_DEVICE_TABLE(of, msm8976_pinctrl_of_match);
1090 1091
1091static struct platform_driver msm8976_pinctrl_driver = {1092static struct platform_driver msm8976_pinctrl_driver = {
1092 .driver = {1093 .driver = {
@@ -1110,4 +1111,3 @@ module_exit(msm8976_pinctrl_exit); · 17 unmodified lines
1110 1111
1111MODULE_DESCRIPTION("Qualcomm msm8976 pinctrl driver");1112MODULE_DESCRIPTION("Qualcomm msm8976 pinctrl driver");
1112MODULE_LICENSE("GPL v2");1113MODULE_LICENSE("GPL v2");
1113MODULE_DEVICE_TABLE(of, msm8976_pinctrl_of_match);
drivers/pinctrl/qcom/pinctrl-msm8994.c+1−1
@@ -1334,6 +1334,7 @@ static const struct of_device_id msm8994_pinctrl_of_match[] = { · 1333 unmodified lines
1334 { .compatible = "qcom,msm8994-pinctrl", },1334 { .compatible = "qcom,msm8994-pinctrl", },
1335 { }1335 { }
1336};1336};
1337MODULE_DEVICE_TABLE(of, msm8994_pinctrl_of_match);
1337 1338
1338static struct platform_driver msm8994_pinctrl_driver = {1339static struct platform_driver msm8994_pinctrl_driver = {
1339 .driver = {1340 .driver = {
@@ -1357,4 +1358,3 @@ module_exit(msm8994_pinctrl_exit); · 17 unmodified lines
1357 1358
1358MODULE_DESCRIPTION("Qualcomm MSM8994 pinctrl driver");1359MODULE_DESCRIPTION("Qualcomm MSM8994 pinctrl driver");
1359MODULE_LICENSE("GPL v2");1360MODULE_LICENSE("GPL v2");
1360MODULE_DEVICE_TABLE(of, msm8994_pinctrl_of_match);
drivers/pinctrl/qcom/pinctrl-msm8996.c+1−1
@@ -1911,6 +1911,7 @@ static const struct of_device_id msm8996_pinctrl_of_match[] = { · 1910 unmodified lines
1911 { .compatible = "qcom,msm8996-pinctrl", },1911 { .compatible = "qcom,msm8996-pinctrl", },
1912 { }1912 { }
1913};1913};
1914MODULE_DEVICE_TABLE(of, msm8996_pinctrl_of_match);
1914 1915
1915static struct platform_driver msm8996_pinctrl_driver = {1916static struct platform_driver msm8996_pinctrl_driver = {
1916 .driver = {1917 .driver = {
@@ -1934,4 +1935,3 @@ module_exit(msm8996_pinctrl_exit); · 17 unmodified lines
1934 1935
1935MODULE_DESCRIPTION("Qualcomm msm8996 pinctrl driver");1936MODULE_DESCRIPTION("Qualcomm msm8996 pinctrl driver");
1936MODULE_LICENSE("GPL v2");1937MODULE_LICENSE("GPL v2");
1937MODULE_DEVICE_TABLE(of, msm8996_pinctrl_of_match);
drivers/pinctrl/qcom/pinctrl-msm8998.c+1−1
@@ -1525,6 +1525,7 @@ static const struct of_device_id msm8998_pinctrl_of_match[] = { · 1524 unmodified lines
1525 { .compatible = "qcom,msm8998-pinctrl", },1525 { .compatible = "qcom,msm8998-pinctrl", },
1526 { },1526 { },
1527};1527};
1528MODULE_DEVICE_TABLE(of, msm8998_pinctrl_of_match);
1528 1529
1529static struct platform_driver msm8998_pinctrl_driver = {1530static struct platform_driver msm8998_pinctrl_driver = {
1530 .driver = {1531 .driver = {
@@ -1548,4 +1549,3 @@ module_exit(msm8998_pinctrl_exit); · 17 unmodified lines
1548 1549
1549MODULE_DESCRIPTION("QTI msm8998 pinctrl driver");1550MODULE_DESCRIPTION("QTI msm8998 pinctrl driver");
1550MODULE_LICENSE("GPL v2");1551MODULE_LICENSE("GPL v2");
1551MODULE_DEVICE_TABLE(of, msm8998_pinctrl_of_match);
drivers/pinctrl/qcom/pinctrl-msm8x74.c+1−1
@@ -1073,6 +1073,7 @@ static const struct of_device_id msm8x74_pinctrl_of_match[] = { · 1072 unmodified lines
1073 { .compatible = "qcom,msm8974-pinctrl", },1073 { .compatible = "qcom,msm8974-pinctrl", },
1074 { },1074 { },
1075};1075};
1076MODULE_DEVICE_TABLE(of, msm8x74_pinctrl_of_match);
1076 1077
1077static struct platform_driver msm8x74_pinctrl_driver = {1078static struct platform_driver msm8x74_pinctrl_driver = {
1078 .driver = {1079 .driver = {
@@ -1097,5 +1098,4 @@ module_exit(msm8x74_pinctrl_exit); · 18 unmodified lines
1097MODULE_AUTHOR("Bjorn Andersson <bjorn.andersson@sonymobile.com>");1098MODULE_AUTHOR("Bjorn Andersson <bjorn.andersson@sonymobile.com>");
1098MODULE_DESCRIPTION("Qualcomm MSM8x74 pinctrl driver");1099MODULE_DESCRIPTION("Qualcomm MSM8x74 pinctrl driver");
1099MODULE_LICENSE("GPL v2");1100MODULE_LICENSE("GPL v2");
1100MODULE_DEVICE_TABLE(of, msm8x74_pinctrl_of_match);
1101 1101
drivers/pinctrl/qcom/pinctrl-nord.c+1770−0
@@ -0,0 +1,1770 @@
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
4 */
5
6#include <linux/module.h>
7#include <linux/of.h>
8#include <linux/platform_device.h>
9
10#include "pinctrl-msm.h"
11
12#define REG_SIZE 0x1000
13#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11) \
14 { \
15 .grp = PINCTRL_PINGROUP("gpio" #id, \
16 gpio##id##_pins, \
17 ARRAY_SIZE(gpio##id##_pins)), \
18 .ctl_reg = REG_SIZE * id, \
19 .io_reg = 0x4 + REG_SIZE * id, \
20 .intr_cfg_reg = 0x8 + REG_SIZE * id, \
21 .intr_status_reg = 0xc + REG_SIZE * id, \
22 .mux_bit = 2, \
23 .pull_bit = 0, \
24 .drv_bit = 6, \
25 .egpio_enable = 12, \
26 .egpio_present = 11, \
27 .oe_bit = 9, \
28 .in_bit = 0, \
29 .out_bit = 1, \
30 .intr_enable_bit = 0, \
31 .intr_status_bit = 0, \
32 .intr_wakeup_present_bit = 6, \
33 .intr_wakeup_enable_bit = 7, \
34 .intr_target_bit = 8, \
35 .intr_target_kpss_val = 3, \
36 .intr_raw_status_bit = 4, \
37 .intr_polarity_bit = 1, \
38 .intr_detection_bit = 2, \
39 .intr_detection_width = 2, \
40 .funcs = (int[]){ \
41 msm_mux_gpio, /* gpio mode */ \
42 msm_mux_##f1, \
43 msm_mux_##f2, \
44 msm_mux_##f3, \
45 msm_mux_##f4, \
46 msm_mux_##f5, \
47 msm_mux_##f6, \
48 msm_mux_##f7, \
49 msm_mux_##f8, \
50 msm_mux_##f9, \
51 msm_mux_##f10, \
52 msm_mux_##f11 /* egpio mode */ \
53 }, \
54 .nfuncs = 12, \
55 }
56
57#define UFS_RESET(pg_name, ctl, io) \
58 { \
59 .grp = PINCTRL_PINGROUP(#pg_name, \
60 pg_name##_pins, \
61 ARRAY_SIZE(pg_name##_pins)), \
62 .ctl_reg = ctl, \
63 .io_reg = io, \
64 .intr_cfg_reg = 0, \
65 .intr_status_reg = 0, \
66 .mux_bit = -1, \
67 .pull_bit = 3, \
68 .drv_bit = 0, \
69 .oe_bit = -1, \
70 .in_bit = -1, \
71 .out_bit = 0, \
72 .intr_enable_bit = -1, \
73 .intr_status_bit = -1, \
74 .intr_target_bit = -1, \
75 .intr_raw_status_bit = -1, \
76 .intr_polarity_bit = -1, \
77 .intr_detection_bit = -1, \
78 .intr_detection_width = -1, \
79 }
80
81static const struct pinctrl_pin_desc nord_pins[] = {
82 PINCTRL_PIN(0, "GPIO_0"),
83 PINCTRL_PIN(1, "GPIO_1"),
84 PINCTRL_PIN(2, "GPIO_2"),
85 PINCTRL_PIN(3, "GPIO_3"),
86 PINCTRL_PIN(4, "GPIO_4"),
87 PINCTRL_PIN(5, "GPIO_5"),
88 PINCTRL_PIN(6, "GPIO_6"),
89 PINCTRL_PIN(7, "GPIO_7"),
90 PINCTRL_PIN(8, "GPIO_8"),
91 PINCTRL_PIN(9, "GPIO_9"),
92 PINCTRL_PIN(10, "GPIO_10"),
93 PINCTRL_PIN(11, "GPIO_11"),
94 PINCTRL_PIN(12, "GPIO_12"),
95 PINCTRL_PIN(13, "GPIO_13"),
96 PINCTRL_PIN(14, "GPIO_14"),
97 PINCTRL_PIN(15, "GPIO_15"),
98 PINCTRL_PIN(16, "GPIO_16"),
99 PINCTRL_PIN(17, "GPIO_17"),
100 PINCTRL_PIN(18, "GPIO_18"),
101 PINCTRL_PIN(19, "GPIO_19"),
102 PINCTRL_PIN(20, "GPIO_20"),
103 PINCTRL_PIN(21, "GPIO_21"),
104 PINCTRL_PIN(22, "GPIO_22"),
105 PINCTRL_PIN(23, "GPIO_23"),
106 PINCTRL_PIN(24, "GPIO_24"),
107 PINCTRL_PIN(25, "GPIO_25"),
108 PINCTRL_PIN(26, "GPIO_26"),
109 PINCTRL_PIN(27, "GPIO_27"),
110 PINCTRL_PIN(28, "GPIO_28"),
111 PINCTRL_PIN(29, "GPIO_29"),
112 PINCTRL_PIN(30, "GPIO_30"),
113 PINCTRL_PIN(31, "GPIO_31"),
114 PINCTRL_PIN(32, "GPIO_32"),
115 PINCTRL_PIN(33, "GPIO_33"),
116 PINCTRL_PIN(34, "GPIO_34"),
117 PINCTRL_PIN(35, "GPIO_35"),
118 PINCTRL_PIN(36, "GPIO_36"),
119 PINCTRL_PIN(37, "GPIO_37"),
120 PINCTRL_PIN(38, "GPIO_38"),
121 PINCTRL_PIN(39, "GPIO_39"),
122 PINCTRL_PIN(40, "GPIO_40"),
123 PINCTRL_PIN(41, "GPIO_41"),
124 PINCTRL_PIN(42, "GPIO_42"),
125 PINCTRL_PIN(43, "GPIO_43"),
126 PINCTRL_PIN(44, "GPIO_44"),
127 PINCTRL_PIN(45, "GPIO_45"),
128 PINCTRL_PIN(46, "GPIO_46"),
129 PINCTRL_PIN(47, "GPIO_47"),
130 PINCTRL_PIN(48, "GPIO_48"),
131 PINCTRL_PIN(49, "GPIO_49"),
132 PINCTRL_PIN(50, "GPIO_50"),
133 PINCTRL_PIN(51, "GPIO_51"),
134 PINCTRL_PIN(52, "GPIO_52"),
135 PINCTRL_PIN(53, "GPIO_53"),
136 PINCTRL_PIN(54, "GPIO_54"),
137 PINCTRL_PIN(55, "GPIO_55"),
138 PINCTRL_PIN(56, "GPIO_56"),
139 PINCTRL_PIN(57, "GPIO_57"),
140 PINCTRL_PIN(58, "GPIO_58"),
141 PINCTRL_PIN(59, "GPIO_59"),
142 PINCTRL_PIN(60, "GPIO_60"),
143 PINCTRL_PIN(61, "GPIO_61"),
144 PINCTRL_PIN(62, "GPIO_62"),
145 PINCTRL_PIN(63, "GPIO_63"),
146 PINCTRL_PIN(64, "GPIO_64"),
147 PINCTRL_PIN(65, "GPIO_65"),
148 PINCTRL_PIN(66, "GPIO_66"),
149 PINCTRL_PIN(67, "GPIO_67"),
150 PINCTRL_PIN(68, "GPIO_68"),
151 PINCTRL_PIN(69, "GPIO_69"),
152 PINCTRL_PIN(70, "GPIO_70"),
153 PINCTRL_PIN(71, "GPIO_71"),
154 PINCTRL_PIN(72, "GPIO_72"),
155 PINCTRL_PIN(73, "GPIO_73"),
156 PINCTRL_PIN(74, "GPIO_74"),
157 PINCTRL_PIN(75, "GPIO_75"),
158 PINCTRL_PIN(76, "GPIO_76"),
159 PINCTRL_PIN(77, "GPIO_77"),
160 PINCTRL_PIN(78, "GPIO_78"),
161 PINCTRL_PIN(79, "GPIO_79"),
162 PINCTRL_PIN(80, "GPIO_80"),
163 PINCTRL_PIN(81, "GPIO_81"),
164 PINCTRL_PIN(82, "GPIO_82"),
165 PINCTRL_PIN(83, "GPIO_83"),
166 PINCTRL_PIN(84, "GPIO_84"),
167 PINCTRL_PIN(85, "GPIO_85"),
168 PINCTRL_PIN(86, "GPIO_86"),
169 PINCTRL_PIN(87, "GPIO_87"),
170 PINCTRL_PIN(88, "GPIO_88"),
171 PINCTRL_PIN(89, "GPIO_89"),
172 PINCTRL_PIN(90, "GPIO_90"),
173 PINCTRL_PIN(91, "GPIO_91"),
174 PINCTRL_PIN(92, "GPIO_92"),
175 PINCTRL_PIN(93, "GPIO_93"),
176 PINCTRL_PIN(94, "GPIO_94"),
177 PINCTRL_PIN(95, "GPIO_95"),
178 PINCTRL_PIN(96, "GPIO_96"),
179 PINCTRL_PIN(97, "GPIO_97"),
180 PINCTRL_PIN(98, "GPIO_98"),
181 PINCTRL_PIN(99, "GPIO_99"),
182 PINCTRL_PIN(100, "GPIO_100"),
183 PINCTRL_PIN(101, "GPIO_101"),
184 PINCTRL_PIN(102, "GPIO_102"),
185 PINCTRL_PIN(103, "GPIO_103"),
186 PINCTRL_PIN(104, "GPIO_104"),
187 PINCTRL_PIN(105, "GPIO_105"),
188 PINCTRL_PIN(106, "GPIO_106"),
189 PINCTRL_PIN(107, "GPIO_107"),
190 PINCTRL_PIN(108, "GPIO_108"),
191 PINCTRL_PIN(109, "GPIO_109"),
192 PINCTRL_PIN(110, "GPIO_110"),
193 PINCTRL_PIN(111, "GPIO_111"),
194 PINCTRL_PIN(112, "GPIO_112"),
195 PINCTRL_PIN(113, "GPIO_113"),
196 PINCTRL_PIN(114, "GPIO_114"),
197 PINCTRL_PIN(115, "GPIO_115"),
198 PINCTRL_PIN(116, "GPIO_116"),
199 PINCTRL_PIN(117, "GPIO_117"),
200 PINCTRL_PIN(118, "GPIO_118"),
201 PINCTRL_PIN(119, "GPIO_119"),
202 PINCTRL_PIN(120, "GPIO_120"),
203 PINCTRL_PIN(121, "GPIO_121"),
204 PINCTRL_PIN(122, "GPIO_122"),
205 PINCTRL_PIN(123, "GPIO_123"),
206 PINCTRL_PIN(124, "GPIO_124"),
207 PINCTRL_PIN(125, "GPIO_125"),
208 PINCTRL_PIN(126, "GPIO_126"),
209 PINCTRL_PIN(127, "GPIO_127"),
210 PINCTRL_PIN(128, "GPIO_128"),
211 PINCTRL_PIN(129, "GPIO_129"),
212 PINCTRL_PIN(130, "GPIO_130"),
213 PINCTRL_PIN(131, "GPIO_131"),
214 PINCTRL_PIN(132, "GPIO_132"),
215 PINCTRL_PIN(133, "GPIO_133"),
216 PINCTRL_PIN(134, "GPIO_134"),
217 PINCTRL_PIN(135, "GPIO_135"),
218 PINCTRL_PIN(136, "GPIO_136"),
219 PINCTRL_PIN(137, "GPIO_137"),
220 PINCTRL_PIN(138, "GPIO_138"),
221 PINCTRL_PIN(139, "GPIO_139"),
222 PINCTRL_PIN(140, "GPIO_140"),
223 PINCTRL_PIN(141, "GPIO_141"),
224 PINCTRL_PIN(142, "GPIO_142"),
225 PINCTRL_PIN(143, "GPIO_143"),
226 PINCTRL_PIN(144, "GPIO_144"),
227 PINCTRL_PIN(145, "GPIO_145"),
228 PINCTRL_PIN(146, "GPIO_146"),
229 PINCTRL_PIN(147, "GPIO_147"),
230 PINCTRL_PIN(148, "GPIO_148"),
231 PINCTRL_PIN(149, "GPIO_149"),
232 PINCTRL_PIN(150, "GPIO_150"),
233 PINCTRL_PIN(151, "GPIO_151"),
234 PINCTRL_PIN(152, "GPIO_152"),
235 PINCTRL_PIN(153, "GPIO_153"),
236 PINCTRL_PIN(154, "GPIO_154"),
237 PINCTRL_PIN(155, "GPIO_155"),
238 PINCTRL_PIN(156, "GPIO_156"),
239 PINCTRL_PIN(157, "GPIO_157"),
240 PINCTRL_PIN(158, "GPIO_158"),
241 PINCTRL_PIN(159, "GPIO_159"),
242 PINCTRL_PIN(160, "GPIO_160"),
243 PINCTRL_PIN(161, "GPIO_161"),
244 PINCTRL_PIN(162, "GPIO_162"),
245 PINCTRL_PIN(163, "GPIO_163"),
246 PINCTRL_PIN(164, "GPIO_164"),
247 PINCTRL_PIN(165, "GPIO_165"),
248 PINCTRL_PIN(166, "GPIO_166"),
249 PINCTRL_PIN(167, "GPIO_167"),
250 PINCTRL_PIN(168, "GPIO_168"),
251 PINCTRL_PIN(169, "GPIO_169"),
252 PINCTRL_PIN(170, "GPIO_170"),
253 PINCTRL_PIN(171, "GPIO_171"),
254 PINCTRL_PIN(172, "GPIO_172"),
255 PINCTRL_PIN(173, "GPIO_173"),
256 PINCTRL_PIN(174, "GPIO_174"),
257 PINCTRL_PIN(175, "GPIO_175"),
258 PINCTRL_PIN(176, "GPIO_176"),
259 PINCTRL_PIN(177, "GPIO_177"),
260 PINCTRL_PIN(178, "GPIO_178"),
261 PINCTRL_PIN(179, "GPIO_179"),
262 PINCTRL_PIN(180, "GPIO_180"),
263 PINCTRL_PIN(181, "UFS_RESET"),
264};
265
266#define DECLARE_MSM_GPIO_PINS(pin) \
267 static const unsigned int gpio##pin##_pins[] = { pin }
268DECLARE_MSM_GPIO_PINS(0);
269DECLARE_MSM_GPIO_PINS(1);
270DECLARE_MSM_GPIO_PINS(2);
271DECLARE_MSM_GPIO_PINS(3);
272DECLARE_MSM_GPIO_PINS(4);
273DECLARE_MSM_GPIO_PINS(5);
274DECLARE_MSM_GPIO_PINS(6);
275DECLARE_MSM_GPIO_PINS(7);
276DECLARE_MSM_GPIO_PINS(8);
277DECLARE_MSM_GPIO_PINS(9);
278DECLARE_MSM_GPIO_PINS(10);
279DECLARE_MSM_GPIO_PINS(11);
280DECLARE_MSM_GPIO_PINS(12);
281DECLARE_MSM_GPIO_PINS(13);
282DECLARE_MSM_GPIO_PINS(14);
283DECLARE_MSM_GPIO_PINS(15);
284DECLARE_MSM_GPIO_PINS(16);
285DECLARE_MSM_GPIO_PINS(17);
286DECLARE_MSM_GPIO_PINS(18);
287DECLARE_MSM_GPIO_PINS(19);
288DECLARE_MSM_GPIO_PINS(20);
289DECLARE_MSM_GPIO_PINS(21);
290DECLARE_MSM_GPIO_PINS(22);
291DECLARE_MSM_GPIO_PINS(23);
292DECLARE_MSM_GPIO_PINS(24);
293DECLARE_MSM_GPIO_PINS(25);
294DECLARE_MSM_GPIO_PINS(26);
295DECLARE_MSM_GPIO_PINS(27);
296DECLARE_MSM_GPIO_PINS(28);
297DECLARE_MSM_GPIO_PINS(29);
298DECLARE_MSM_GPIO_PINS(30);
299DECLARE_MSM_GPIO_PINS(31);
300DECLARE_MSM_GPIO_PINS(32);
301DECLARE_MSM_GPIO_PINS(33);
302DECLARE_MSM_GPIO_PINS(34);
303DECLARE_MSM_GPIO_PINS(35);
304DECLARE_MSM_GPIO_PINS(36);
305DECLARE_MSM_GPIO_PINS(37);
306DECLARE_MSM_GPIO_PINS(38);
307DECLARE_MSM_GPIO_PINS(39);
308DECLARE_MSM_GPIO_PINS(40);
309DECLARE_MSM_GPIO_PINS(41);
310DECLARE_MSM_GPIO_PINS(42);
311DECLARE_MSM_GPIO_PINS(43);
312DECLARE_MSM_GPIO_PINS(44);
313DECLARE_MSM_GPIO_PINS(45);
314DECLARE_MSM_GPIO_PINS(46);
315DECLARE_MSM_GPIO_PINS(47);
316DECLARE_MSM_GPIO_PINS(48);
317DECLARE_MSM_GPIO_PINS(49);
318DECLARE_MSM_GPIO_PINS(50);
319DECLARE_MSM_GPIO_PINS(51);
320DECLARE_MSM_GPIO_PINS(52);
321DECLARE_MSM_GPIO_PINS(53);
322DECLARE_MSM_GPIO_PINS(54);
323DECLARE_MSM_GPIO_PINS(55);
324DECLARE_MSM_GPIO_PINS(56);
325DECLARE_MSM_GPIO_PINS(57);
326DECLARE_MSM_GPIO_PINS(58);
327DECLARE_MSM_GPIO_PINS(59);
328DECLARE_MSM_GPIO_PINS(60);
329DECLARE_MSM_GPIO_PINS(61);
330DECLARE_MSM_GPIO_PINS(62);
331DECLARE_MSM_GPIO_PINS(63);
332DECLARE_MSM_GPIO_PINS(64);
333DECLARE_MSM_GPIO_PINS(65);
334DECLARE_MSM_GPIO_PINS(66);
335DECLARE_MSM_GPIO_PINS(67);
336DECLARE_MSM_GPIO_PINS(68);
337DECLARE_MSM_GPIO_PINS(69);
338DECLARE_MSM_GPIO_PINS(70);
339DECLARE_MSM_GPIO_PINS(71);
340DECLARE_MSM_GPIO_PINS(72);
341DECLARE_MSM_GPIO_PINS(73);
342DECLARE_MSM_GPIO_PINS(74);
343DECLARE_MSM_GPIO_PINS(75);
344DECLARE_MSM_GPIO_PINS(76);
345DECLARE_MSM_GPIO_PINS(77);
346DECLARE_MSM_GPIO_PINS(78);
347DECLARE_MSM_GPIO_PINS(79);
348DECLARE_MSM_GPIO_PINS(80);
349DECLARE_MSM_GPIO_PINS(81);
350DECLARE_MSM_GPIO_PINS(82);
351DECLARE_MSM_GPIO_PINS(83);
352DECLARE_MSM_GPIO_PINS(84);
353DECLARE_MSM_GPIO_PINS(85);
354DECLARE_MSM_GPIO_PINS(86);
355DECLARE_MSM_GPIO_PINS(87);
356DECLARE_MSM_GPIO_PINS(88);
357DECLARE_MSM_GPIO_PINS(89);
358DECLARE_MSM_GPIO_PINS(90);
359DECLARE_MSM_GPIO_PINS(91);
360DECLARE_MSM_GPIO_PINS(92);
361DECLARE_MSM_GPIO_PINS(93);
362DECLARE_MSM_GPIO_PINS(94);
363DECLARE_MSM_GPIO_PINS(95);
364DECLARE_MSM_GPIO_PINS(96);
365DECLARE_MSM_GPIO_PINS(97);
366DECLARE_MSM_GPIO_PINS(98);
367DECLARE_MSM_GPIO_PINS(99);
368DECLARE_MSM_GPIO_PINS(100);
369DECLARE_MSM_GPIO_PINS(101);
370DECLARE_MSM_GPIO_PINS(102);
371DECLARE_MSM_GPIO_PINS(103);
372DECLARE_MSM_GPIO_PINS(104);
373DECLARE_MSM_GPIO_PINS(105);
374DECLARE_MSM_GPIO_PINS(106);
375DECLARE_MSM_GPIO_PINS(107);
376DECLARE_MSM_GPIO_PINS(108);
377DECLARE_MSM_GPIO_PINS(109);
378DECLARE_MSM_GPIO_PINS(110);
379DECLARE_MSM_GPIO_PINS(111);
380DECLARE_MSM_GPIO_PINS(112);
381DECLARE_MSM_GPIO_PINS(113);
382DECLARE_MSM_GPIO_PINS(114);
383DECLARE_MSM_GPIO_PINS(115);
384DECLARE_MSM_GPIO_PINS(116);
385DECLARE_MSM_GPIO_PINS(117);
386DECLARE_MSM_GPIO_PINS(118);
387DECLARE_MSM_GPIO_PINS(119);
388DECLARE_MSM_GPIO_PINS(120);
389DECLARE_MSM_GPIO_PINS(121);
390DECLARE_MSM_GPIO_PINS(122);
391DECLARE_MSM_GPIO_PINS(123);
392DECLARE_MSM_GPIO_PINS(124);
393DECLARE_MSM_GPIO_PINS(125);
394DECLARE_MSM_GPIO_PINS(126);
395DECLARE_MSM_GPIO_PINS(127);
396DECLARE_MSM_GPIO_PINS(128);
397DECLARE_MSM_GPIO_PINS(129);
398DECLARE_MSM_GPIO_PINS(130);
399DECLARE_MSM_GPIO_PINS(131);
400DECLARE_MSM_GPIO_PINS(132);
401DECLARE_MSM_GPIO_PINS(133);
402DECLARE_MSM_GPIO_PINS(134);
403DECLARE_MSM_GPIO_PINS(135);
404DECLARE_MSM_GPIO_PINS(136);
405DECLARE_MSM_GPIO_PINS(137);
406DECLARE_MSM_GPIO_PINS(138);
407DECLARE_MSM_GPIO_PINS(139);
408DECLARE_MSM_GPIO_PINS(140);
409DECLARE_MSM_GPIO_PINS(141);
410DECLARE_MSM_GPIO_PINS(142);
411DECLARE_MSM_GPIO_PINS(143);
412DECLARE_MSM_GPIO_PINS(144);
413DECLARE_MSM_GPIO_PINS(145);
414DECLARE_MSM_GPIO_PINS(146);
415DECLARE_MSM_GPIO_PINS(147);
416DECLARE_MSM_GPIO_PINS(148);
417DECLARE_MSM_GPIO_PINS(149);
418DECLARE_MSM_GPIO_PINS(150);
419DECLARE_MSM_GPIO_PINS(151);
420DECLARE_MSM_GPIO_PINS(152);
421DECLARE_MSM_GPIO_PINS(153);
422DECLARE_MSM_GPIO_PINS(154);
423DECLARE_MSM_GPIO_PINS(155);
424DECLARE_MSM_GPIO_PINS(156);
425DECLARE_MSM_GPIO_PINS(157);
426DECLARE_MSM_GPIO_PINS(158);
427DECLARE_MSM_GPIO_PINS(159);
428DECLARE_MSM_GPIO_PINS(160);
429DECLARE_MSM_GPIO_PINS(161);
430DECLARE_MSM_GPIO_PINS(162);
431DECLARE_MSM_GPIO_PINS(163);
432DECLARE_MSM_GPIO_PINS(164);
433DECLARE_MSM_GPIO_PINS(165);
434DECLARE_MSM_GPIO_PINS(166);
435DECLARE_MSM_GPIO_PINS(167);
436DECLARE_MSM_GPIO_PINS(168);
437DECLARE_MSM_GPIO_PINS(169);
438DECLARE_MSM_GPIO_PINS(170);
439DECLARE_MSM_GPIO_PINS(171);
440DECLARE_MSM_GPIO_PINS(172);
441DECLARE_MSM_GPIO_PINS(173);
442DECLARE_MSM_GPIO_PINS(174);
443DECLARE_MSM_GPIO_PINS(175);
444DECLARE_MSM_GPIO_PINS(176);
445DECLARE_MSM_GPIO_PINS(177);
446DECLARE_MSM_GPIO_PINS(178);
447DECLARE_MSM_GPIO_PINS(179);
448DECLARE_MSM_GPIO_PINS(180);
449
450static const unsigned int ufs_reset_pins[] = { 181 };
451
452enum nord_functions {
453 msm_mux_gpio,
454 msm_mux_aoss_cti,
455 msm_mux_atest_char,
456 msm_mux_atest_usb20,
457 msm_mux_atest_usb21,
458 msm_mux_aud_intfc0_clk,
459 msm_mux_aud_intfc0_data,
460 msm_mux_aud_intfc0_ws,
461 msm_mux_aud_intfc10_clk,
462 msm_mux_aud_intfc10_data,
463 msm_mux_aud_intfc10_ws,
464 msm_mux_aud_intfc1_clk,
465 msm_mux_aud_intfc1_data,
466 msm_mux_aud_intfc1_ws,
467 msm_mux_aud_intfc2_clk,
468 msm_mux_aud_intfc2_data,
469 msm_mux_aud_intfc2_ws,
470 msm_mux_aud_intfc3_clk,
471 msm_mux_aud_intfc3_data,
472 msm_mux_aud_intfc3_ws,
473 msm_mux_aud_intfc4_clk,
474 msm_mux_aud_intfc4_data,
475 msm_mux_aud_intfc4_ws,
476 msm_mux_aud_intfc5_clk,
477 msm_mux_aud_intfc5_data,
478 msm_mux_aud_intfc5_ws,
479 msm_mux_aud_intfc6_clk,
480 msm_mux_aud_intfc6_data,
481 msm_mux_aud_intfc6_ws,
482 msm_mux_aud_intfc7_clk,
483 msm_mux_aud_intfc7_data,
484 msm_mux_aud_intfc7_ws,
485 msm_mux_aud_intfc8_clk,
486 msm_mux_aud_intfc8_data,
487 msm_mux_aud_intfc8_ws,
488 msm_mux_aud_intfc9_clk,
489 msm_mux_aud_intfc9_data,
490 msm_mux_aud_intfc9_ws,
491 msm_mux_aud_mclk0_mira,
492 msm_mux_aud_mclk0_mirb,
493 msm_mux_aud_mclk1_mira,
494 msm_mux_aud_mclk1_mirb,
495 msm_mux_aud_mclk2_mira,
496 msm_mux_aud_mclk2_mirb,
497 msm_mux_aud_refclk0,
498 msm_mux_aud_refclk1,
499 msm_mux_bist_done,
500 msm_mux_ccu_async_in,
501 msm_mux_ccu_i2c_scl,
502 msm_mux_ccu_i2c_sda,
503 msm_mux_ccu_timer,
504 msm_mux_clink_debug,
505 msm_mux_dbg_out,
506 msm_mux_dbg_out_clk,
507 msm_mux_ddr_bist_complete,
508 msm_mux_ddr_bist_fail,
509 msm_mux_ddr_bist_start,
510 msm_mux_ddr_bist_stop,
511 msm_mux_ddr_pxi,
512 msm_mux_dp_rx0,
513 msm_mux_dp_rx00,
514 msm_mux_dp_rx01,
515 msm_mux_dp_rx0_mute,
516 msm_mux_dp_rx1,
517 msm_mux_dp_rx10,
518 msm_mux_dp_rx11,
519 msm_mux_dp_rx1_mute,
520 msm_mux_edp0_hot,
521 msm_mux_edp0_lcd,
522 msm_mux_edp1_hot,
523 msm_mux_edp1_lcd,
524 msm_mux_edp2_hot,
525 msm_mux_edp2_lcd,
526 msm_mux_edp3_hot,
527 msm_mux_edp3_lcd,
528 msm_mux_emac0_mcg,
529 msm_mux_emac0_mdc,
530 msm_mux_emac0_mdio,
531 msm_mux_emac0_ptp,
532 msm_mux_emac1_mcg,
533 msm_mux_emac1_mdc,
534 msm_mux_emac1_mdio,
535 msm_mux_emac1_ptp,
536 msm_mux_gcc_gp1_clk,
537 msm_mux_gcc_gp2_clk,
538 msm_mux_gcc_gp3_clk,
539 msm_mux_gcc_gp4_clk,
540 msm_mux_gcc_gp5_clk,
541 msm_mux_gcc_gp6_clk,
542 msm_mux_gcc_gp7_clk,
543 msm_mux_gcc_gp8_clk,
544 msm_mux_jitter_bist,
545 msm_mux_lbist_pass,
546 msm_mux_mbist_pass,
547 msm_mux_mdp0_vsync_out,
548 msm_mux_mdp1_vsync_out,
549 msm_mux_mdp_vsync_e,
550 msm_mux_mdp_vsync_p,
551 msm_mux_mdp_vsync_s,
552 msm_mux_pcie0_clk_req_n,
553 msm_mux_pcie1_clk_req_n,
554 msm_mux_pcie2_clk_req_n,
555 msm_mux_pcie3_clk_req_n,
556 msm_mux_phase_flag,
557 msm_mux_pll_bist_sync,
558 msm_mux_pll_clk_aux,
559 msm_mux_prng_rosc0,
560 msm_mux_prng_rosc1,
561 msm_mux_pwrbrk_i_n,
562 msm_mux_qdss,
563 msm_mux_qdss_cti,
564 msm_mux_qspi,
565 msm_mux_qup0_se0,
566 msm_mux_qup0_se1,
567 msm_mux_qup0_se2,
568 msm_mux_qup0_se3,
569 msm_mux_qup0_se4,
570 msm_mux_qup0_se5,
571 msm_mux_qup1_se0,
572 msm_mux_qup1_se1,
573 msm_mux_qup1_se2,
574 msm_mux_qup1_se3,
575 msm_mux_qup1_se4,
576 msm_mux_qup1_se5,
577 msm_mux_qup1_se6,
578 msm_mux_qup2_se0,
579 msm_mux_qup2_se1,
580 msm_mux_qup2_se2,
581 msm_mux_qup2_se3,
582 msm_mux_qup2_se4,
583 msm_mux_qup2_se5,
584 msm_mux_qup2_se6,
585 msm_mux_qup3_se0_mira,
586 msm_mux_qup3_se0_mirb,
587 msm_mux_sailss_ospi,
588 msm_mux_sdc4_clk,
589 msm_mux_sdc4_cmd,
590 msm_mux_sdc4_data,
591 msm_mux_smb_alert,
592 msm_mux_smb_alert_n,
593 msm_mux_smb_clk,
594 msm_mux_smb_dat,
595 msm_mux_tb_trig_sdc4,
596 msm_mux_tmess_prng0,
597 msm_mux_tmess_prng1,
598 msm_mux_tsc_timer,
599 msm_mux_tsense_pwm,
600 msm_mux_usb0_hs,
601 msm_mux_usb0_phy_ps,
602 msm_mux_usb1_hs,
603 msm_mux_usb1_phy_ps,
604 msm_mux_usb2_hs,
605 msm_mux_usxgmii0_phy,
606 msm_mux_usxgmii1_phy,
607 msm_mux_vsense_trigger_mirnat,
608 msm_mux_wcn_sw,
609 msm_mux_wcn_sw_ctrl,
610 msm_mux__,
611};
612
613static const char *const gpio_groups[] = {
614 "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5",
615 "gpio6", "gpio7", "gpio8", "gpio9", "gpio10", "gpio11",
616 "gpio12", "gpio13", "gpio14", "gpio15", "gpio16", "gpio17",
617 "gpio18", "gpio19", "gpio20", "gpio21", "gpio22", "gpio23",
618 "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29",
619 "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
620 "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41",
621 "gpio42", "gpio43", "gpio44", "gpio45", "gpio46", "gpio47",
622 "gpio48", "gpio49", "gpio50", "gpio51", "gpio52", "gpio53",
623 "gpio54", "gpio55", "gpio56", "gpio57", "gpio58", "gpio59",
624 "gpio60", "gpio61", "gpio62", "gpio63", "gpio64", "gpio65",
625 "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", "gpio71",
626 "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77",
627 "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83",
628 "gpio84", "gpio85", "gpio86", "gpio87", "gpio88", "gpio89",
629 "gpio90", "gpio91", "gpio92", "gpio93", "gpio94", "gpio95",
630 "gpio96", "gpio97", "gpio98", "gpio99", "gpio100", "gpio101",
631 "gpio102", "gpio103", "gpio104", "gpio105", "gpio106", "gpio107",
632 "gpio108", "gpio109", "gpio110", "gpio111", "gpio112", "gpio113",
633 "gpio114", "gpio115", "gpio116", "gpio117", "gpio118", "gpio119",
634 "gpio120", "gpio121", "gpio122", "gpio123", "gpio124", "gpio125",
635 "gpio126", "gpio127", "gpio128", "gpio129", "gpio130", "gpio131",
636 "gpio132", "gpio133", "gpio134", "gpio135", "gpio136", "gpio137",
637 "gpio138", "gpio139", "gpio140", "gpio141", "gpio142", "gpio143",
638 "gpio144", "gpio145", "gpio146", "gpio147", "gpio148", "gpio149",
639 "gpio150", "gpio151", "gpio152", "gpio153", "gpio154", "gpio155",
640 "gpio156", "gpio157", "gpio158", "gpio159", "gpio160", "gpio161",
641 "gpio162", "gpio163", "gpio164", "gpio165", "gpio166", "gpio167",
642 "gpio168", "gpio169", "gpio170", "gpio171", "gpio172", "gpio173",
643 "gpio174", "gpio175", "gpio176", "gpio177", "gpio178", "gpio179",
644 "gpio180",
645};
646
647static const char *const aoss_cti_groups[] = {
648 "gpio83",
649 "gpio84",
650 "gpio85",
651 "gpio86",
652};
653
654static const char *const atest_char_groups[] = {
655 "gpio176", "gpio177", "gpio178", "gpio179", "gpio180",
656};
657
658static const char *const atest_usb20_groups[] = {
659 "gpio126",
660 "gpio128",
661 "gpio130",
662};
663
664static const char *const atest_usb21_groups[] = {
665 "gpio127",
666 "gpio129",
667 "gpio131",
668};
669
670static const char *const aud_intfc0_clk_groups[] = {
671 "gpio57",
672};
673
674static const char *const aud_intfc0_data_groups[] = {
675 "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", "gpio64", "gpio65", "gpio66",
676};
677
678static const char *const aud_intfc0_ws_groups[] = {
679 "gpio58",
680};
681
682static const char *const aud_intfc10_clk_groups[] = {
683 "gpio61",
684};
685
686static const char *const aud_intfc10_data_groups[] = {
687 "gpio81", "gpio82",
688};
689
690static const char *const aud_intfc10_ws_groups[] = {
691 "gpio62",
692};
693
694static const char *const aud_intfc1_clk_groups[] = {
695 "gpio67",
696};
697
698static const char *const aud_intfc1_data_groups[] = {
699 "gpio69", "gpio70", "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76",
700};
701
702static const char *const aud_intfc1_ws_groups[] = {
703 "gpio68",
704};
705
706static const char *const aud_intfc2_clk_groups[] = {
707 "gpio77",
708};
709
710static const char *const aud_intfc2_data_groups[] = {
711 "gpio79", "gpio80", "gpio81", "gpio82",
712};
713
714static const char *const aud_intfc2_ws_groups[] = {
715 "gpio78",
716};
717
718static const char *const aud_intfc3_clk_groups[] = {
719 "gpio83",
720};
721
722static const char *const aud_intfc3_data_groups[] = {
723 "gpio85", "gpio86",
724};
725
726static const char *const aud_intfc3_ws_groups[] = {
727 "gpio84",
728};
729
730static const char *const aud_intfc4_clk_groups[] = {
731 "gpio87",
732};
733
734static const char *const aud_intfc4_data_groups[] = {
735 "gpio89", "gpio90",
736};
737
738static const char *const aud_intfc4_ws_groups[] = {
739 "gpio88",
740};
741
742static const char *const aud_intfc5_clk_groups[] = {
743 "gpio91",
744};
745
746static const char *const aud_intfc5_data_groups[] = {
747 "gpio93", "gpio94",
748};
749
750static const char *const aud_intfc5_ws_groups[] = {
751 "gpio92",
752};
753
754static const char *const aud_intfc6_clk_groups[] = {
755 "gpio95",
756};
757
758static const char *const aud_intfc6_data_groups[] = {
759 "gpio97", "gpio98",
760};
761
762static const char *const aud_intfc6_ws_groups[] = {
763 "gpio96",
764};
765
766static const char *const aud_intfc7_clk_groups[] = {
767 "gpio63",
768};
769
770static const char *const aud_intfc7_data_groups[] = {
771 "gpio65", "gpio66",
772};
773
774static const char *const aud_intfc7_ws_groups[] = {
775 "gpio64",
776};
777
778static const char *const aud_intfc8_clk_groups[] = {
779 "gpio73",
780};
781
782static const char *const aud_intfc8_data_groups[] = {
783 "gpio75", "gpio76",
784};
785
786static const char *const aud_intfc8_ws_groups[] = {
787 "gpio74",
788};
789
790static const char *const aud_intfc9_clk_groups[] = {
791 "gpio70",
792};
793
794static const char *const aud_intfc9_data_groups[] = {
795 "gpio72",
796};
797
798static const char *const aud_intfc9_ws_groups[] = {
799 "gpio71",
800};
801
802static const char *const aud_mclk0_mira_groups[] = {
803 "gpio99",
804};
805
806static const char *const aud_mclk0_mirb_groups[] = {
807 "gpio86",
808};
809
810static const char *const aud_mclk1_mira_groups[] = {
811 "gpio100",
812};
813
814static const char *const aud_mclk1_mirb_groups[] = {
815 "gpio90",
816};
817
818static const char *const aud_mclk2_mira_groups[] = {
819 "gpio101",
820};
821
822static const char *const aud_mclk2_mirb_groups[] = {
823 "gpio94",
824};
825
826static const char *const aud_refclk0_groups[] = {
827 "gpio100",
828};
829
830static const char *const aud_refclk1_groups[] = {
831 "gpio101",
832};
833
834static const char *const bist_done_groups[] = {
835 "gpio168",
836};
837
838static const char *const ccu_async_in_groups[] = {
839 "gpio45", "gpio176", "gpio177", "gpio178", "gpio179", "gpio180",
840};
841
842static const char *const ccu_i2c_scl_groups[] = {
843 "gpio16", "gpio18", "gpio20", "gpio22", "gpio24",
844 "gpio114", "gpio116", "gpio126", "gpio130", "gpio132",
845};
846
847static const char *const ccu_i2c_sda_groups[] = {
848 "gpio15", "gpio17", "gpio19", "gpio21", "gpio23",
849 "gpio113", "gpio115", "gpio125", "gpio129", "gpio131",
850};
851
852static const char *const ccu_timer_groups[] = {
853 "gpio25", "gpio26", "gpio27", "gpio28", "gpio29", "gpio30",
854 "gpio31", "gpio32", "gpio33", "gpio34", "gpio143", "gpio144",
855 "gpio150", "gpio151", "gpio152", "gpio153",
856};
857
858static const char *const clink_debug_groups[] = {
859 "gpio12", "gpio13", "gpio14", "gpio51",
860 "gpio52", "gpio53", "gpio54", "gpio55",
861};
862
863static const char *const dbg_out_groups[] = {
864 "gpio113",
865};
866
867static const char *const dbg_out_clk_groups[] = {
868 "gpio165",
869};
870
871static const char *const ddr_bist_complete_groups[] = {
872 "gpio37",
873};
874
875static const char *const ddr_bist_fail_groups[] = {
876 "gpio39",
877};
878
879static const char *const ddr_bist_start_groups[] = {
880 "gpio36",
881};
882
883static const char *const ddr_bist_stop_groups[] = {
884 "gpio38",
885};
886
887static const char *const ddr_pxi_groups[] = {
888 "gpio99", "gpio100", "gpio109", "gpio110", "gpio113", "gpio114",
889 "gpio115", "gpio116", "gpio117", "gpio118", "gpio119", "gpio120",
890 "gpio121", "gpio122", "gpio126", "gpio127", "gpio128", "gpio129",
891 "gpio130", "gpio131", "gpio132", "gpio133", "gpio134", "gpio135",
892 "gpio136", "gpio137", "gpio138", "gpio139", "gpio162", "gpio163",
893 "gpio164", "gpio165",
894};
895
896static const char *const dp_rx0_groups[] = {
897 "gpio55", "gpio83", "gpio84", "gpio85", "gpio86",
898 "gpio88", "gpio89", "gpio137", "gpio138",
899};
900
901static const char *const dp_rx00_groups[] = {
902 "gpio99",
903};
904
905static const char *const dp_rx01_groups[] = {
906 "gpio100",
907};
908
909static const char *const dp_rx0_mute_groups[] = {
910 "gpio35",
911};
912
913static const char *const dp_rx1_groups[] = {
914 "gpio56", "gpio92", "gpio93", "gpio95", "gpio96",
915 "gpio97", "gpio98", "gpio158", "gpio159",
916};
917
918static const char *const dp_rx10_groups[] = {
919 "gpio121",
920};
921
922static const char *const dp_rx11_groups[] = {
923 "gpio122",
924};
925
926static const char *const dp_rx1_mute_groups[] = {
927 "gpio36",
928};
929
930static const char *const edp0_hot_groups[] = {
931 "gpio51",
932};
933
934static const char *const edp0_lcd_groups[] = {
935 "gpio47",
936};
937
938static const char *const edp1_hot_groups[] = {
939 "gpio52",
940};
941
942static const char *const edp1_lcd_groups[] = {
943 "gpio48",
944};
945
946static const char *const edp2_hot_groups[] = {
947 "gpio53",
948};
949
950static const char *const edp2_lcd_groups[] = {
951 "gpio49",
952};
953
954static const char *const edp3_hot_groups[] = {
955 "gpio54",
956};
957
958static const char *const edp3_lcd_groups[] = {
959 "gpio50",
960};
961
962static const char *const emac0_mcg_groups[] = {
963 "gpio16", "gpio17", "gpio18", "gpio19",
964};
965
966static const char *const emac0_mdc_groups[] = {
967 "gpio47",
968};
969
970static const char *const emac0_mdio_groups[] = {
971 "gpio48",
972};
973
974static const char *const emac0_ptp_groups[] = {
975 "gpio133", "gpio134", "gpio135", "gpio136",
976 "gpio139", "gpio140", "gpio141", "gpio142",
977};
978
979static const char *const emac1_mcg_groups[] = {
980 "gpio20", "gpio21", "gpio22", "gpio23",
981};
982
983static const char *const emac1_mdc_groups[] = {
984 "gpio49",
985};
986
987static const char *const emac1_mdio_groups[] = {
988 "gpio50",
989};
990
991static const char *const emac1_ptp_groups[] = {
992 "gpio37", "gpio38", "gpio39", "gpio40",
993 "gpio41", "gpio42", "gpio43", "gpio44",
994};
995
996static const char *const gcc_gp1_clk_groups[] = {
997 "gpio51",
998};
999
1000static const char *const gcc_gp2_clk_groups[] = {
1001 "gpio52",
1002};
1003
1004static const char *const gcc_gp3_clk_groups[] = {
1005 "gpio42",
1006};
1007
1008static const char *const gcc_gp4_clk_groups[] = {
1009 "gpio43",
1010};
1011
1012static const char *const gcc_gp5_clk_groups[] = {
1013 "gpio105",
1014};
1015
1016static const char *const gcc_gp6_clk_groups[] = {
1017 "gpio106",
1018};
1019
1020static const char *const gcc_gp7_clk_groups[] = {
1021 "gpio13",
1022};
1023
1024static const char *const gcc_gp8_clk_groups[] = {
1025 "gpio14",
1026};
1027
1028static const char *const jitter_bist_groups[] = {
1029 "gpio123",
1030 "gpio138",
1031};
1032
1033static const char *const lbist_pass_groups[] = {
1034 "gpio121",
1035};
1036
1037static const char *const mbist_pass_groups[] = {
1038 "gpio122",
1039};
1040
1041static const char *const mdp0_vsync_out_groups[] = {
1042 "gpio113", "gpio114", "gpio115", "gpio116", "gpio121", "gpio122",
1043 "gpio139", "gpio140", "gpio141", "gpio142", "gpio143",
1044};
1045
1046static const char *const mdp1_vsync_out_groups[] = {
1047 "gpio123", "gpio124", "gpio125", "gpio126", "gpio129", "gpio130",
1048 "gpio131", "gpio132", "gpio133", "gpio134", "gpio135",
1049};
1050
1051static const char *const mdp_vsync_e_groups[] = {
1052 "gpio109",
1053};
1054
1055static const char *const mdp_vsync_p_groups[] = {
1056 "gpio110",
1057};
1058
1059static const char *const mdp_vsync_s_groups[] = {
1060 "gpio144",
1061};
1062
1063static const char *const pcie0_clk_req_n_groups[] = {
1064 "gpio1",
1065};
1066
1067static const char *const pcie1_clk_req_n_groups[] = {
1068 "gpio4",
1069};
1070
1071static const char *const pcie2_clk_req_n_groups[] = {
1072 "gpio7",
1073};
1074
1075static const char *const pcie3_clk_req_n_groups[] = {
1076 "gpio10",
1077};
1078
1079static const char *const phase_flag_groups[] = {
1080 "gpio67", "gpio68", "gpio69", "gpio70", "gpio71", "gpio72", "gpio73", "gpio74",
1081 "gpio75", "gpio76", "gpio77", "gpio78", "gpio79", "gpio80", "gpio81", "gpio82",
1082 "gpio83", "gpio84", "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90",
1083 "gpio91", "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio98", "gpio101",
1084};
1085
1086static const char *const pll_bist_sync_groups[] = {
1087 "gpio176",
1088};
1089
1090static const char *const pll_clk_aux_groups[] = {
1091 "gpio100",
1092};
1093
1094static const char *const prng_rosc0_groups[] = {
1095 "gpio117",
1096};
1097
1098static const char *const prng_rosc1_groups[] = {
1099 "gpio118",
1100};
1101
1102static const char *const pwrbrk_i_n_groups[] = {
1103 "gpio167",
1104};
1105
1106static const char *const qdss_cti_groups[] = {
1107 "gpio41", "gpio42", "gpio110", "gpio138",
1108 "gpio142", "gpio144", "gpio162", "gpio163",
1109};
1110
1111static const char *const qdss_groups[] = {
1112 "gpio67", "gpio68", "gpio69", "gpio70", "gpio71", "gpio72", "gpio73", "gpio74",
1113 "gpio75", "gpio76", "gpio77", "gpio78", "gpio79", "gpio80", "gpio81", "gpio82",
1114 "gpio83", "gpio84", "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90",
1115 "gpio91", "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98",
1116 "gpio99", "gpio100", "gpio101", "gpio108",
1117};
1118
1119static const char *const qspi_groups[] = {
1120 "gpio102", "gpio103", "gpio104", "gpio105", "gpio106", "gpio107", "gpio108",
1121};
1122
1123static const char *const qup0_se0_groups[] = {
1124 "gpio109", "gpio110", "gpio111", "gpio112",
1125};
1126
1127static const char *const qup0_se1_groups[] = {
1128 "gpio109", "gpio110", "gpio111", "gpio112",
1129};
1130
1131static const char *const qup0_se2_groups[] = {
1132 "gpio113", "gpio114", "gpio115", "gpio116",
1133};
1134
1135static const char *const qup0_se3_groups[] = {
1136 "gpio113", "gpio114", "gpio115", "gpio116",
1137};
1138
1139static const char *const qup0_se4_groups[] = {
1140 "gpio117", "gpio118", "gpio119", "gpio120",
1141};
1142
1143static const char *const qup0_se5_groups[] = {
1144 "gpio109", "gpio110", "gpio121", "gpio122",
1145};
1146
1147static const char *const qup1_se0_groups[] = {
1148 "gpio123", "gpio124", "gpio125", "gpio126",
1149};
1150
1151static const char *const qup1_se1_groups[] = {
1152 "gpio123", "gpio124", "gpio125", "gpio126",
1153};
1154
1155static const char *const qup1_se2_groups[] = {
1156 "gpio127", "gpio128", "gpio129", "gpio130",
1157};
1158
1159static const char *const qup1_se3_groups[] = {
1160 "gpio129", "gpio130",
1161};
1162
1163static const char *const qup1_se4_groups[] = {
1164 "gpio131", "gpio132", "gpio137", "gpio138",
1165};
1166
1167static const char *const qup1_se5_groups[] = {
1168 "gpio133", "gpio134", "gpio135", "gpio136",
1169};
1170
1171static const char *const qup1_se6_groups[] = {
1172 "gpio131", "gpio132", "gpio137", "gpio138",
1173};
1174
1175static const char *const qup2_se0_groups[] = {
1176 "gpio139", "gpio140", "gpio141", "gpio142",
1177};
1178
1179static const char *const qup2_se1_groups[] = {
1180 "gpio143", "gpio144", "gpio154", "gpio155",
1181};
1182
1183static const char *const qup2_se2_groups[] = {
1184 "gpio145", "gpio146", "gpio147", "gpio148", "gpio149",
1185};
1186
1187static const char *const qup2_se3_groups[] = {
1188 "gpio150", "gpio151", "gpio152", "gpio153",
1189};
1190
1191static const char *const qup2_se4_groups[] = {
1192 "gpio143", "gpio144", "gpio150", "gpio151",
1193 "gpio152", "gpio154", "gpio155",
1194};
1195
1196static const char *const qup2_se5_groups[] = {
1197 "gpio156", "gpio157", "gpio158", "gpio159",
1198};
1199
1200static const char *const qup2_se6_groups[] = {
1201 "gpio156", "gpio157", "gpio158", "gpio159",
1202};
1203
1204static const char *const qup3_se0_mira_groups[] = {
1205 "gpio102", "gpio103", "gpio104", "gpio105",
1206 "gpio106", "gpio107", "gpio108",
1207};
1208
1209static const char *const qup3_se0_mirb_groups[] = {
1210 "gpio102", "gpio103",
1211};
1212
1213static const char *const sailss_ospi_groups[] = {
1214 "gpio164",
1215 "gpio165",
1216};
1217
1218static const char *const sdc4_clk_groups[] = {
1219 "gpio175",
1220};
1221
1222static const char *const sdc4_cmd_groups[] = {
1223 "gpio174",
1224};
1225
1226static const char *const sdc4_data_groups[] = {
1227 "gpio170",
1228 "gpio171",
1229 "gpio172",
1230 "gpio173",
1231};
1232
1233static const char *const smb_alert_groups[] = {
1234 "gpio110",
1235};
1236
1237static const char *const smb_alert_n_groups[] = {
1238 "gpio109",
1239};
1240
1241static const char *const smb_clk_groups[] = {
1242 "gpio112",
1243};
1244
1245static const char *const smb_dat_groups[] = {
1246 "gpio111",
1247};
1248
1249static const char *const tb_trig_sdc4_groups[] = {
1250 "gpio169",
1251};
1252
1253static const char *const tmess_prng0_groups[] = {
1254 "gpio94",
1255};
1256
1257static const char *const tmess_prng1_groups[] = {
1258 "gpio95",
1259};
1260
1261static const char *const tsc_timer_groups[] = {
1262 "gpio25", "gpio26", "gpio27", "gpio28", "gpio29",
1263 "gpio30", "gpio31", "gpio32", "gpio33", "gpio34",
1264};
1265
1266static const char *const tsense_pwm_groups[] = {
1267 "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", "gpio50",
1268};
1269
1270static const char *const usb0_hs_groups[] = {
1271 "gpio12",
1272};
1273
1274static const char *const usb0_phy_ps_groups[] = {
1275 "gpio164",
1276};
1277
1278static const char *const usb1_hs_groups[] = {
1279 "gpio13",
1280};
1281
1282static const char *const usb1_phy_ps_groups[] = {
1283 "gpio165",
1284};
1285
1286static const char *const usb2_hs_groups[] = {
1287 "gpio14",
1288};
1289
1290static const char *const usxgmii0_phy_groups[] = {
1291 "gpio45",
1292};
1293
1294static const char *const usxgmii1_phy_groups[] = {
1295 "gpio46",
1296};
1297
1298static const char *const vsense_trigger_mirnat_groups[] = {
1299 "gpio132",
1300};
1301
1302static const char *const wcn_sw_groups[] = {
1303 "gpio161",
1304};
1305
1306static const char *const wcn_sw_ctrl_groups[] = {
1307 "gpio160",
1308};
1309
1310static const struct pinfunction nord_functions[] = {
1311 MSM_GPIO_PIN_FUNCTION(gpio),
1312 MSM_PIN_FUNCTION(aoss_cti),
1313 MSM_PIN_FUNCTION(atest_char),
1314 MSM_PIN_FUNCTION(atest_usb20),
1315 MSM_PIN_FUNCTION(atest_usb21),
1316 MSM_PIN_FUNCTION(aud_intfc0_clk),
1317 MSM_PIN_FUNCTION(aud_intfc0_data),
1318 MSM_PIN_FUNCTION(aud_intfc0_ws),
1319 MSM_PIN_FUNCTION(aud_intfc10_clk),
1320 MSM_PIN_FUNCTION(aud_intfc10_data),
1321 MSM_PIN_FUNCTION(aud_intfc10_ws),
1322 MSM_PIN_FUNCTION(aud_intfc1_clk),
1323 MSM_PIN_FUNCTION(aud_intfc1_data),
1324 MSM_PIN_FUNCTION(aud_intfc1_ws),
1325 MSM_PIN_FUNCTION(aud_intfc2_clk),
1326 MSM_PIN_FUNCTION(aud_intfc2_data),
1327 MSM_PIN_FUNCTION(aud_intfc2_ws),
1328 MSM_PIN_FUNCTION(aud_intfc3_clk),
1329 MSM_PIN_FUNCTION(aud_intfc3_data),
1330 MSM_PIN_FUNCTION(aud_intfc3_ws),
1331 MSM_PIN_FUNCTION(aud_intfc4_clk),
1332 MSM_PIN_FUNCTION(aud_intfc4_data),
1333 MSM_PIN_FUNCTION(aud_intfc4_ws),
1334 MSM_PIN_FUNCTION(aud_intfc5_clk),
1335 MSM_PIN_FUNCTION(aud_intfc5_data),
1336 MSM_PIN_FUNCTION(aud_intfc5_ws),
1337 MSM_PIN_FUNCTION(aud_intfc6_clk),
1338 MSM_PIN_FUNCTION(aud_intfc6_data),
1339 MSM_PIN_FUNCTION(aud_intfc6_ws),
1340 MSM_PIN_FUNCTION(aud_intfc7_clk),
1341 MSM_PIN_FUNCTION(aud_intfc7_data),
1342 MSM_PIN_FUNCTION(aud_intfc7_ws),
1343 MSM_PIN_FUNCTION(aud_intfc8_clk),
1344 MSM_PIN_FUNCTION(aud_intfc8_data),
1345 MSM_PIN_FUNCTION(aud_intfc8_ws),
1346 MSM_PIN_FUNCTION(aud_intfc9_clk),
1347 MSM_PIN_FUNCTION(aud_intfc9_data),
1348 MSM_PIN_FUNCTION(aud_intfc9_ws),
1349 MSM_PIN_FUNCTION(aud_mclk0_mira),
1350 MSM_PIN_FUNCTION(aud_mclk0_mirb),
1351 MSM_PIN_FUNCTION(aud_mclk1_mira),
1352 MSM_PIN_FUNCTION(aud_mclk1_mirb),
1353 MSM_PIN_FUNCTION(aud_mclk2_mira),
1354 MSM_PIN_FUNCTION(aud_mclk2_mirb),
1355 MSM_PIN_FUNCTION(aud_refclk0),
1356 MSM_PIN_FUNCTION(aud_refclk1),
1357 MSM_PIN_FUNCTION(bist_done),
1358 MSM_PIN_FUNCTION(ccu_async_in),
1359 MSM_PIN_FUNCTION(ccu_i2c_scl),
1360 MSM_PIN_FUNCTION(ccu_i2c_sda),
1361 MSM_PIN_FUNCTION(ccu_timer),
1362 MSM_PIN_FUNCTION(clink_debug),
1363 MSM_PIN_FUNCTION(dbg_out),
1364 MSM_PIN_FUNCTION(dbg_out_clk),
1365 MSM_PIN_FUNCTION(ddr_bist_complete),
1366 MSM_PIN_FUNCTION(ddr_bist_fail),
1367 MSM_PIN_FUNCTION(ddr_bist_start),
1368 MSM_PIN_FUNCTION(ddr_bist_stop),
1369 MSM_PIN_FUNCTION(ddr_pxi),
1370 MSM_PIN_FUNCTION(dp_rx0),
1371 MSM_PIN_FUNCTION(dp_rx00),
1372 MSM_PIN_FUNCTION(dp_rx01),
1373 MSM_PIN_FUNCTION(dp_rx0_mute),
1374 MSM_PIN_FUNCTION(dp_rx1),
1375 MSM_PIN_FUNCTION(dp_rx10),
1376 MSM_PIN_FUNCTION(dp_rx11),
1377 MSM_PIN_FUNCTION(dp_rx1_mute),
1378 MSM_PIN_FUNCTION(edp0_hot),
1379 MSM_PIN_FUNCTION(edp0_lcd),
1380 MSM_PIN_FUNCTION(edp1_hot),
1381 MSM_PIN_FUNCTION(edp1_lcd),
1382 MSM_PIN_FUNCTION(edp2_hot),
1383 MSM_PIN_FUNCTION(edp2_lcd),
1384 MSM_PIN_FUNCTION(edp3_hot),
1385 MSM_PIN_FUNCTION(edp3_lcd),
1386 MSM_PIN_FUNCTION(emac0_mcg),
1387 MSM_PIN_FUNCTION(emac0_mdc),
1388 MSM_PIN_FUNCTION(emac0_mdio),
1389 MSM_PIN_FUNCTION(emac0_ptp),
1390 MSM_PIN_FUNCTION(emac1_mcg),
1391 MSM_PIN_FUNCTION(emac1_mdc),
1392 MSM_PIN_FUNCTION(emac1_mdio),
1393 MSM_PIN_FUNCTION(emac1_ptp),
1394 MSM_PIN_FUNCTION(gcc_gp1_clk),
1395 MSM_PIN_FUNCTION(gcc_gp2_clk),
1396 MSM_PIN_FUNCTION(gcc_gp3_clk),
1397 MSM_PIN_FUNCTION(gcc_gp4_clk),
1398 MSM_PIN_FUNCTION(gcc_gp5_clk),
1399 MSM_PIN_FUNCTION(gcc_gp6_clk),
1400 MSM_PIN_FUNCTION(gcc_gp7_clk),
1401 MSM_PIN_FUNCTION(gcc_gp8_clk),
1402 MSM_PIN_FUNCTION(jitter_bist),
1403 MSM_PIN_FUNCTION(lbist_pass),
1404 MSM_PIN_FUNCTION(mbist_pass),
1405 MSM_PIN_FUNCTION(mdp0_vsync_out),
1406 MSM_PIN_FUNCTION(mdp1_vsync_out),
1407 MSM_PIN_FUNCTION(mdp_vsync_e),
1408 MSM_PIN_FUNCTION(mdp_vsync_p),
1409 MSM_PIN_FUNCTION(mdp_vsync_s),
1410 MSM_PIN_FUNCTION(pcie0_clk_req_n),
1411 MSM_PIN_FUNCTION(pcie1_clk_req_n),
1412 MSM_PIN_FUNCTION(pcie2_clk_req_n),
1413 MSM_PIN_FUNCTION(pcie3_clk_req_n),
1414 MSM_PIN_FUNCTION(phase_flag),
1415 MSM_PIN_FUNCTION(pll_bist_sync),
1416 MSM_PIN_FUNCTION(pll_clk_aux),
1417 MSM_PIN_FUNCTION(prng_rosc0),
1418 MSM_PIN_FUNCTION(prng_rosc1),
1419 MSM_PIN_FUNCTION(pwrbrk_i_n),
1420 MSM_PIN_FUNCTION(qdss),
1421 MSM_PIN_FUNCTION(qdss_cti),
1422 MSM_PIN_FUNCTION(qspi),
1423 MSM_PIN_FUNCTION(qup0_se0),
1424 MSM_PIN_FUNCTION(qup0_se1),
1425 MSM_PIN_FUNCTION(qup0_se2),
1426 MSM_PIN_FUNCTION(qup0_se3),
1427 MSM_PIN_FUNCTION(qup0_se4),
1428 MSM_PIN_FUNCTION(qup0_se5),
1429 MSM_PIN_FUNCTION(qup1_se0),
1430 MSM_PIN_FUNCTION(qup1_se1),
1431 MSM_PIN_FUNCTION(qup1_se2),
1432 MSM_PIN_FUNCTION(qup1_se3),
1433 MSM_PIN_FUNCTION(qup1_se4),
1434 MSM_PIN_FUNCTION(qup1_se5),
1435 MSM_PIN_FUNCTION(qup1_se6),
1436 MSM_PIN_FUNCTION(qup2_se0),
1437 MSM_PIN_FUNCTION(qup2_se1),
1438 MSM_PIN_FUNCTION(qup2_se2),
1439 MSM_PIN_FUNCTION(qup2_se3),
1440 MSM_PIN_FUNCTION(qup2_se4),
1441 MSM_PIN_FUNCTION(qup2_se5),
1442 MSM_PIN_FUNCTION(qup2_se6),
1443 MSM_PIN_FUNCTION(qup3_se0_mira),
1444 MSM_PIN_FUNCTION(qup3_se0_mirb),
1445 MSM_PIN_FUNCTION(sailss_ospi),
1446 MSM_PIN_FUNCTION(sdc4_clk),
1447 MSM_PIN_FUNCTION(sdc4_cmd),
1448 MSM_PIN_FUNCTION(sdc4_data),
1449 MSM_PIN_FUNCTION(smb_alert),
1450 MSM_PIN_FUNCTION(smb_alert_n),
1451 MSM_PIN_FUNCTION(smb_clk),
1452 MSM_PIN_FUNCTION(smb_dat),
1453 MSM_PIN_FUNCTION(tb_trig_sdc4),
1454 MSM_PIN_FUNCTION(tmess_prng0),
1455 MSM_PIN_FUNCTION(tmess_prng1),
1456 MSM_PIN_FUNCTION(tsc_timer),
1457 MSM_PIN_FUNCTION(tsense_pwm),
1458 MSM_PIN_FUNCTION(usb0_hs),
1459 MSM_PIN_FUNCTION(usb0_phy_ps),
1460 MSM_PIN_FUNCTION(usb1_hs),
1461 MSM_PIN_FUNCTION(usb1_phy_ps),
1462 MSM_PIN_FUNCTION(usb2_hs),
1463 MSM_PIN_FUNCTION(usxgmii0_phy),
1464 MSM_PIN_FUNCTION(usxgmii1_phy),
1465 MSM_PIN_FUNCTION(vsense_trigger_mirnat),
1466 MSM_PIN_FUNCTION(wcn_sw),
1467 MSM_PIN_FUNCTION(wcn_sw_ctrl),
1468};
1469
1470/* Every pin is maintained as a single group, and missing or non-existing pin
1471 * would be maintained as dummy group to synchronize pin group index with
1472 * pin descriptor registered with pinctrl core.
1473 * Clients would not be able to request these dummy pin groups.
1474 */
1475static const struct msm_pingroup nord_groups[] = {
1476 [0] = PINGROUP(0, _, _, _, _, _, _, _, _, _, _, _),
1477 [1] = PINGROUP(1, pcie0_clk_req_n, _, _, _, _, _, _, _, _, _, _),
1478 [2] = PINGROUP(2, _, _, _, _, _, _, _, _, _, _, _),
1479 [3] = PINGROUP(3, _, _, _, _, _, _, _, _, _, _, _),
1480 [4] = PINGROUP(4, pcie1_clk_req_n, _, _, _, _, _, _, _, _, _, _),
1481 [5] = PINGROUP(5, _, _, _, _, _, _, _, _, _, _, _),
1482 [6] = PINGROUP(6, _, _, _, _, _, _, _, _, _, _, _),
1483 [7] = PINGROUP(7, pcie2_clk_req_n, _, _, _, _, _, _, _, _, _, _),
1484 [8] = PINGROUP(8, _, _, _, _, _, _, _, _, _, _, _),
1485 [9] = PINGROUP(9, _, _, _, _, _, _, _, _, _, _, _),
1486 [10] = PINGROUP(10, pcie3_clk_req_n, _, _, _, _, _, _, _, _, _, _),
1487 [11] = PINGROUP(11, _, _, _, _, _, _, _, _, _, _, _),
1488 [12] = PINGROUP(12, usb0_hs, clink_debug, _, _, _, _, _, _, _, _, _),
1489 [13] = PINGROUP(13, usb1_hs, clink_debug, gcc_gp7_clk, _, _, _, _, _, _, _, _),
1490 [14] = PINGROUP(14, usb2_hs, clink_debug, gcc_gp8_clk, _, _, _, _, _, _, _, _),
1491 [15] = PINGROUP(15, ccu_i2c_sda, _, _, _, _, _, _, _, _, _, _),
1492 [16] = PINGROUP(16, ccu_i2c_scl, emac0_mcg, _, _, _, _, _, _, _, _, _),
1493 [17] = PINGROUP(17, ccu_i2c_sda, emac0_mcg, _, _, _, _, _, _, _, _, _),
1494 [18] = PINGROUP(18, ccu_i2c_scl, emac0_mcg, _, _, _, _, _, _, _, _, _),
1495 [19] = PINGROUP(19, ccu_i2c_sda, emac0_mcg, _, _, _, _, _, _, _, _, _),
1496 [20] = PINGROUP(20, ccu_i2c_scl, emac1_mcg, _, _, _, _, _, _, _, _, _),
1497 [21] = PINGROUP(21, ccu_i2c_sda, emac1_mcg, _, _, _, _, _, _, _, _, _),
1498 [22] = PINGROUP(22, ccu_i2c_scl, emac1_mcg, _, _, _, _, _, _, _, _, _),
1499 [23] = PINGROUP(23, ccu_i2c_sda, emac1_mcg, _, _, _, _, _, _, _, _, _),
1500 [24] = PINGROUP(24, ccu_i2c_scl, _, _, _, _, _, _, _, _, _, _),
1501 [25] = PINGROUP(25, ccu_timer, tsc_timer, _, _, _, _, _, _, _, _, _),
1502 [26] = PINGROUP(26, ccu_timer, tsc_timer, _, _, _, _, _, _, _, _, _),
1503 [27] = PINGROUP(27, ccu_timer, tsc_timer, _, _, _, _, _, _, _, _, _),
1504 [28] = PINGROUP(28, ccu_timer, tsc_timer, _, _, _, _, _, _, _, _, _),
1505 [29] = PINGROUP(29, ccu_timer, tsc_timer, _, _, _, _, _, _, _, _, _),
1506 [30] = PINGROUP(30, ccu_timer, tsc_timer, _, _, _, _, _, _, _, _, _),
1507 [31] = PINGROUP(31, ccu_timer, tsc_timer, _, _, _, _, _, _, _, _, _),
1508 [32] = PINGROUP(32, ccu_timer, tsc_timer, _, _, _, _, _, _, _, _, _),
1509 [33] = PINGROUP(33, ccu_timer, tsc_timer, _, _, _, _, _, _, _, _, _),
1510 [34] = PINGROUP(34, ccu_timer, tsc_timer, _, _, _, _, _, _, _, _, _),
1511 [35] = PINGROUP(35, dp_rx0_mute, _, _, _, _, _, _, _, _, _, _),
1512 [36] = PINGROUP(36, dp_rx1_mute, ddr_bist_start, _, _, _, _, _, _, _, _, _),
1513 [37] = PINGROUP(37, emac1_ptp, ddr_bist_complete, _, _, _, _, _, _, _, _, _),
1514 [38] = PINGROUP(38, emac1_ptp, ddr_bist_stop, _, _, _, _, _, _, _, _, _),
1515 [39] = PINGROUP(39, emac1_ptp, ddr_bist_fail, _, _, _, _, _, _, _, _, _),
1516 [40] = PINGROUP(40, emac1_ptp, _, _, _, _, _, _, _, _, _, _),
1517 [41] = PINGROUP(41, emac1_ptp, qdss_cti, _, _, _, _, _, _, _, _, _),
1518 [42] = PINGROUP(42, emac1_ptp, qdss_cti, gcc_gp3_clk, _, _, _, _, _, _, _, _),
1519 [43] = PINGROUP(43, emac1_ptp, gcc_gp4_clk, tsense_pwm, _, _, _, _, _, _, _, _),
1520 [44] = PINGROUP(44, emac1_ptp, tsense_pwm, _, _, _, _, _, _, _, _, _),
1521 [45] = PINGROUP(45, usxgmii0_phy, ccu_async_in, tsense_pwm, _, _, _, _, _, _, _, _),
1522 [46] = PINGROUP(46, usxgmii1_phy, tsense_pwm, _, _, _, _, _, _, _, _, _),
1523 [47] = PINGROUP(47, emac0_mdc, edp0_lcd, tsense_pwm, _, _, _, _, _, _, _, _),
1524 [48] = PINGROUP(48, emac0_mdio, edp1_lcd, tsense_pwm, _, _, _, _, _, _, _, _),
1525 [49] = PINGROUP(49, emac1_mdc, edp2_lcd, tsense_pwm, _, _, _, _, _, _, _, _),
1526 [50] = PINGROUP(50, emac1_mdio, edp3_lcd, tsense_pwm, _, _, _, _, _, _, _, _),
1527 [51] = PINGROUP(51, edp0_hot, clink_debug, gcc_gp1_clk, _, _, _, _, _, _, _, _),
1528 [52] = PINGROUP(52, edp1_hot, clink_debug, gcc_gp2_clk, _, _, _, _, _, _, _, _),
1529 [53] = PINGROUP(53, edp2_hot, clink_debug, _, _, _, _, _, _, _, _, _),
1530 [54] = PINGROUP(54, edp3_hot, clink_debug, _, _, _, _, _, _, _, _, _),
1531 [55] = PINGROUP(55, dp_rx0, clink_debug, _, _, _, _, _, _, _, _, _),
1532 [56] = PINGROUP(56, dp_rx1, _, _, _, _, _, _, _, _, _, _),
1533 [57] = PINGROUP(57, aud_intfc0_clk, _, _, _, _, _, _, _, _, _, _),
1534 [58] = PINGROUP(58, aud_intfc0_ws, _, _, _, _, _, _, _, _, _, _),
1535 [59] = PINGROUP(59, aud_intfc0_data, _, _, _, _, _, _, _, _, _, _),
1536 [60] = PINGROUP(60, aud_intfc0_data, _, _, _, _, _, _, _, _, _, _),
1537 [61] = PINGROUP(61, aud_intfc0_data, aud_intfc10_clk, _, _, _, _, _, _, _, _, _),
1538 [62] = PINGROUP(62, aud_intfc0_data, aud_intfc10_ws, _, _, _, _, _, _, _, _, _),
1539 [63] = PINGROUP(63, aud_intfc0_data, aud_intfc7_clk, _, _, _, _, _, _, _, _, _),
1540 [64] = PINGROUP(64, aud_intfc0_data, aud_intfc7_ws, _, _, _, _, _, _, _, _, _),
1541 [65] = PINGROUP(65, aud_intfc0_data, aud_intfc7_data, _, _, _, _, _, _, _, _, _),
1542 [66] = PINGROUP(66, aud_intfc0_data, aud_intfc7_data, _, _, _, _, _, _, _, _, _),
1543 [67] = PINGROUP(67, aud_intfc1_clk, phase_flag, _, qdss, _, _, _, _, _, _, _),
1544 [68] = PINGROUP(68, aud_intfc1_ws, phase_flag, _, qdss, _, _, _, _, _, _, _),
1545 [69] = PINGROUP(69, aud_intfc1_data, phase_flag, _, qdss, _, _, _, _, _, _, _),
1546 [70] = PINGROUP(70, aud_intfc1_data, aud_intfc9_clk, phase_flag,
1547 _, qdss, _, _, _, _, _, _),
1548 [71] = PINGROUP(71, aud_intfc1_data, aud_intfc9_ws, phase_flag,
1549 _, qdss, _, _, _, _, _, _),
1550 [72] = PINGROUP(72, aud_intfc1_data, aud_intfc9_data, phase_flag,
1551 _, qdss, _, _, _, _, _, _),
1552 [73] = PINGROUP(73, aud_intfc1_data, aud_intfc8_clk, phase_flag,
1553 _, qdss, _, _, _, _, _, _),
1554 [74] = PINGROUP(74, aud_intfc1_data, aud_intfc8_ws, phase_flag,
1555 _, qdss, _, _, _, _, _, _),
1556 [75] = PINGROUP(75, aud_intfc1_data, aud_intfc8_data, phase_flag,
1557 _, qdss, _, _, _, _, _, _),
1558 [76] = PINGROUP(76, aud_intfc1_data, aud_intfc8_data, phase_flag,
1559 _, qdss, _, _, _, _, _, _),
1560 [77] = PINGROUP(77, aud_intfc2_clk, phase_flag, _, qdss, _, _, _, _, _, _, _),
1561 [78] = PINGROUP(78, aud_intfc2_ws, phase_flag, _, qdss, _, _, _, _, _, _, _),
1562 [79] = PINGROUP(79, aud_intfc2_data, phase_flag, _, qdss, _, _, _, _, _, _, _),
1563 [80] = PINGROUP(80, aud_intfc2_data, phase_flag, _, _, qdss, _, _, _, _, _, _),
1564 [81] = PINGROUP(81, aud_intfc2_data, aud_intfc10_data, phase_flag,
1565 _, _, qdss, _, _, _, _, _),
1566 [82] = PINGROUP(82, aud_intfc2_data, aud_intfc10_data, phase_flag,
1567 _, qdss, _, _, _, _, _, _),
1568 [83] = PINGROUP(83, aud_intfc3_clk, dp_rx0, aoss_cti, phase_flag, _, qdss,
1569 _, _, _, _, _),
1570 [84] = PINGROUP(84, aud_intfc3_ws, dp_rx0, aoss_cti, phase_flag, _, qdss,
1571 _, _, _, _, _),
1572 [85] = PINGROUP(85, aud_intfc3_data, dp_rx0, aoss_cti, phase_flag,
1573 _, qdss, _, _, _, _, _),
1574 [86] = PINGROUP(86, aud_intfc3_data, aud_mclk0_mirb, dp_rx0, aoss_cti, phase_flag,
1575 _, qdss, _, _, _, _),
1576 [87] = PINGROUP(87, aud_intfc4_clk, phase_flag, _, qdss, _, _, _, _, _, _, _),
1577 [88] = PINGROUP(88, aud_intfc4_ws, dp_rx0, phase_flag, _, qdss, _, _, _, _, _, _),
1578 [89] = PINGROUP(89, aud_intfc4_data, dp_rx0, phase_flag, _, qdss,
1579 _, _, _, _, _, _),
1580 [90] = PINGROUP(90, aud_intfc4_data, aud_mclk1_mirb, phase_flag,
1581 _, qdss, _, _, _, _, _, _),
1582 [91] = PINGROUP(91, aud_intfc5_clk, phase_flag, _, qdss, _, _, _, _, _, _, _),
1583 [92] = PINGROUP(92, aud_intfc5_ws, dp_rx1, phase_flag, _, qdss, _, _, _, _, _, _),
1584 [93] = PINGROUP(93, aud_intfc5_data, dp_rx1, phase_flag, _, qdss,
1585 _, _, _, _, _, _),
1586 [94] = PINGROUP(94, aud_intfc5_data, aud_mclk2_mirb, phase_flag, tmess_prng0,
1587 _, qdss, _, _, _, _, _),
1588 [95] = PINGROUP(95, aud_intfc6_clk, dp_rx1, phase_flag, tmess_prng1,
1589 _, qdss, _, _, _, _, _),
1590 [96] = PINGROUP(96, aud_intfc6_ws, dp_rx1, phase_flag, _, qdss,
1591 _, _, _, _, _, _),
1592 [97] = PINGROUP(97, aud_intfc6_data, dp_rx1, qdss, _, _, _, _, _, _, _, _),
1593 [98] = PINGROUP(98, aud_intfc6_data, dp_rx1, phase_flag, _, qdss,
1594 _, _, _, _, _, _),
1595 [99] = PINGROUP(99, aud_mclk0_mira, qdss, dp_rx00, ddr_pxi, _, _, _, _, _, _, _),
1596 [100] = PINGROUP(100, aud_mclk1_mira, aud_refclk0, pll_clk_aux,
1597 qdss, dp_rx01, ddr_pxi, _, _, _, _, _),
1598 [101] = PINGROUP(101, aud_mclk2_mira, aud_refclk1, phase_flag, _, qdss,
1599 _, _, _, _, _, _),
1600 [102] = PINGROUP(102, qspi, qup3_se0_mira, qup3_se0_mirb, _, _, _, _, _, _, _, _),
1601 [103] = PINGROUP(103, qspi, qup3_se0_mira, qup3_se0_mirb, _, _, _, _, _, _, _, _),
1602 [104] = PINGROUP(104, qspi, qup3_se0_mira, _, _, _, _, _, _, _, _, _),
1603 [105] = PINGROUP(105, qspi, qup3_se0_mira, gcc_gp5_clk, _, _, _, _, _, _, _, _),
1604 [106] = PINGROUP(106, qspi, qup3_se0_mira, gcc_gp6_clk, _, _, _, _, _, _, _, _),
1605 [107] = PINGROUP(107, qspi, qup3_se0_mira, _, _, _, _, _, _, _, _, _),
1606 [108] = PINGROUP(108, qspi, qup3_se0_mira, qdss, _, _, _, _, _, _, _, _),
1607 [109] = PINGROUP(109, qup0_se0, qup0_se1, qup0_se5, mdp_vsync_e,
1608 smb_alert_n, _, ddr_pxi, _, _, _, _),
1609 [110] = PINGROUP(110, qup0_se0, qup0_se1, qup0_se5, qdss_cti,
1610 mdp_vsync_p, smb_alert, _, ddr_pxi, _, _, _),
1611 [111] = PINGROUP(111, qup0_se1, qup0_se0, smb_dat, _, _, _, _, _, _, _, _),
1612 [112] = PINGROUP(112, qup0_se1, qup0_se0, smb_clk, _, _, _, _, _, _, _, _),
1613 [113] = PINGROUP(113, qup0_se2, qup0_se3, ccu_i2c_sda, mdp0_vsync_out,
1614 dbg_out, ddr_pxi, _, _, _, _, _),
1615 [114] = PINGROUP(114, qup0_se2, qup0_se3, ccu_i2c_scl, mdp0_vsync_out,
1616 _, ddr_pxi, _, _, _, _, _),
1617 [115] = PINGROUP(115, qup0_se3, qup0_se2, ccu_i2c_sda, mdp0_vsync_out,
1618 _, ddr_pxi, _, _, _, _, _),
1619 [116] = PINGROUP(116, qup0_se3, qup0_se2, ccu_i2c_scl, mdp0_vsync_out,
1620 _, ddr_pxi, _, _, _, _, _),
1621 [117] = PINGROUP(117, qup0_se4, prng_rosc0, _, ddr_pxi, _, _, _, _, _, _, _),
1622 [118] = PINGROUP(118, qup0_se4, prng_rosc1, _, ddr_pxi, _, _, _, _, _, _, _),
1623 [119] = PINGROUP(119, qup0_se4, _, ddr_pxi, _, _, _, _, _, _, _, _),
1624 [120] = PINGROUP(120, qup0_se4, _, ddr_pxi, _, _, _, _, _, _, _, _),
1625 [121] = PINGROUP(121, qup0_se5, lbist_pass, mdp0_vsync_out, _, dp_rx10, ddr_pxi,
1626 _, _, _, _, _),
1627 [122] = PINGROUP(122, qup0_se5, mbist_pass, mdp0_vsync_out, _, dp_rx11, ddr_pxi,
1628 _, _, _, _, _),
1629 [123] = PINGROUP(123, qup1_se0, qup1_se1, mdp1_vsync_out, jitter_bist,
1630 _, _, _, _, _, _, _),
1631 [124] = PINGROUP(124, qup1_se0, qup1_se1, mdp1_vsync_out, _, _, _, _, _, _, _, _),
1632 [125] = PINGROUP(125, qup1_se1, qup1_se0, ccu_i2c_sda, mdp1_vsync_out,
1633 _, _, _, _, _, _, _),
1634 [126] = PINGROUP(126, qup1_se1, qup1_se0, ccu_i2c_scl, mdp1_vsync_out,
1635 _, atest_usb20, ddr_pxi, _, _, _, _),
1636 [127] = PINGROUP(127, qup1_se2, qup1_se2, _, atest_usb21, ddr_pxi,
1637 _, _, _, _, _, _),
1638 [128] = PINGROUP(128, qup1_se2, qup1_se2, _, atest_usb20, ddr_pxi,
1639 _, _, _, _, _, _),
1640 [129] = PINGROUP(129, qup1_se3, qup1_se3, ccu_i2c_sda, mdp1_vsync_out,
1641 _, atest_usb21, ddr_pxi, _, _, _, _),
1642 [130] = PINGROUP(130, qup1_se3, qup1_se3, ccu_i2c_scl, mdp1_vsync_out,
1643 _, atest_usb20, ddr_pxi, _, _, _, _),
1644 [131] = PINGROUP(131, qup1_se4, qup1_se6, ccu_i2c_sda, mdp1_vsync_out,
1645 _, atest_usb21, ddr_pxi, _, _, _, _),
1646 [132] = PINGROUP(132, qup1_se4, qup1_se6, ccu_i2c_scl, mdp1_vsync_out,
1647 _, vsense_trigger_mirnat, ddr_pxi, _, _, _, _),
1648 [133] = PINGROUP(133, qup1_se5, emac0_ptp, mdp1_vsync_out, _, ddr_pxi,
1649 _, _, _, _, _, _),
1650 [134] = PINGROUP(134, qup1_se5, emac0_ptp, mdp1_vsync_out, _, ddr_pxi,
1651 _, _, _, _, _, _),
1652 [135] = PINGROUP(135, qup1_se5, emac0_ptp, mdp1_vsync_out, _, ddr_pxi,
1653 _, _, _, _, _, _),
1654 [136] = PINGROUP(136, qup1_se5, emac0_ptp, _, ddr_pxi, _, _, _, _, _, _, _),
1655 [137] = PINGROUP(137, qup1_se6, qup1_se4, dp_rx0, _, ddr_pxi, _, _, _, _, _, _),
1656 [138] = PINGROUP(138, qup1_se6, qup1_se4, dp_rx0, qdss_cti, jitter_bist, ddr_pxi,
1657 _, _, _, _, _),
1658 [139] = PINGROUP(139, qup2_se0, emac0_ptp, mdp0_vsync_out, ddr_pxi,
1659 _, _, _, _, _, _, _),
1660 [140] = PINGROUP(140, qup2_se0, emac0_ptp, mdp0_vsync_out, _, _, _, _, _, _, _, _),
1661 [141] = PINGROUP(141, qup2_se0, emac0_ptp, mdp0_vsync_out, _, _, _, _, _, _, _, _),
1662 [142] = PINGROUP(142, qup2_se0, emac0_ptp, qdss_cti, mdp0_vsync_out, _, _, _, _, _, _, _),
1663 [143] = PINGROUP(143, qup2_se1, qup2_se4, ccu_timer, mdp0_vsync_out,
1664 _, _, _, _, _, _, _),
1665 [144] = PINGROUP(144, qup2_se1, qup2_se4, ccu_timer, qdss_cti, mdp_vsync_s,
1666 _, _, _, _, _, _),
1667 [145] = PINGROUP(145, qup2_se2, _, _, _, _, _, _, _, _, _, _),
1668 [146] = PINGROUP(146, qup2_se2, _, _, _, _, _, _, _, _, _, _),
1669 [147] = PINGROUP(147, qup2_se2, _, _, _, _, _, _, _, _, _, _),
1670 [148] = PINGROUP(148, qup2_se2, _, _, _, _, _, _, _, _, _, _),
1671 [149] = PINGROUP(149, qup2_se2, _, _, _, _, _, _, _, _, _, _),
1672 [150] = PINGROUP(150, qup2_se3, qup2_se4, ccu_timer, _, _, _, _, _, _, _, _),
1673 [151] = PINGROUP(151, qup2_se3, qup2_se4, ccu_timer, _, _, _, _, _, _, _, _),
1674 [152] = PINGROUP(152, qup2_se3, qup2_se4, ccu_timer, _, _, _, _, _, _, _, _),
1675 [153] = PINGROUP(153, qup2_se3, ccu_timer, _, _, _, _, _, _, _, _, _),
1676 [154] = PINGROUP(154, qup2_se4, qup2_se1, _, _, _, _, _, _, _, _, _),
1677 [155] = PINGROUP(155, qup2_se4, qup2_se1, _, _, _, _, _, _, _, _, _),
1678 [156] = PINGROUP(156, qup2_se5, qup2_se6, _, _, _, _, _, _, _, _, _),
1679 [157] = PINGROUP(157, qup2_se5, qup2_se6, _, _, _, _, _, _, _, _, _),
1680 [158] = PINGROUP(158, qup2_se6, qup2_se5, dp_rx1, _, _, _, _, _, _, _, _),
1681 [159] = PINGROUP(159, qup2_se6, qup2_se5, dp_rx1, _, _, _, _, _, _, _, _),
1682 [160] = PINGROUP(160, wcn_sw_ctrl, _, _, _, _, _, _, _, _, _, _),
1683 [161] = PINGROUP(161, wcn_sw, _, _, _, _, _, _, _, _, _, _),
1684 [162] = PINGROUP(162, qdss_cti, _, ddr_pxi, _, _, _, _, _, _, _, _),
1685 [163] = PINGROUP(163, qdss_cti, _, ddr_pxi, _, _, _, _, _, _, _, _),
1686 [164] = PINGROUP(164, usb0_phy_ps, _, sailss_ospi, ddr_pxi, _, _, _, _, _, _, _),
1687 [165] = PINGROUP(165, usb1_phy_ps, dbg_out_clk, sailss_ospi, ddr_pxi,
1688 _, _, _, _, _, _, _),
1689 [166] = PINGROUP(166, _, _, _, _, _, _, _, _, _, _, _),
1690 [167] = PINGROUP(167, pwrbrk_i_n, _, _, _, _, _, _, _, _, _, _),
1691 [168] = PINGROUP(168, bist_done, _, _, _, _, _, _, _, _, _, _),
1692 [169] = PINGROUP(169, tb_trig_sdc4, _, _, _, _, _, _, _, _, _, _),
1693 [170] = PINGROUP(170, sdc4_data, _, _, _, _, _, _, _, _, _, _),
1694 [171] = PINGROUP(171, sdc4_data, _, _, _, _, _, _, _, _, _, _),
1695 [172] = PINGROUP(172, sdc4_data, _, _, _, _, _, _, _, _, _, _),
1696 [173] = PINGROUP(173, sdc4_data, _, _, _, _, _, _, _, _, _, _),
1697 [174] = PINGROUP(174, sdc4_cmd, _, _, _, _, _, _, _, _, _, _),
1698 [175] = PINGROUP(175, sdc4_clk, _, _, _, _, _, _, _, _, _, _),
1699 [176] = PINGROUP(176, ccu_async_in, pll_bist_sync, atest_char,
1700 _, _, _, _, _, _, _, _),
1701 [177] = PINGROUP(177, ccu_async_in, atest_char, _, _, _, _, _, _, _, _, _),
1702 [178] = PINGROUP(178, ccu_async_in, atest_char, _, _, _, _, _, _, _, _, _),
1703 [179] = PINGROUP(179, ccu_async_in, atest_char, _, _, _, _, _, _, _, _, _),
1704 [180] = PINGROUP(180, ccu_async_in, atest_char, _, _, _, _, _, _, _, _, _),
1705 [181] = UFS_RESET(ufs_reset, 0xbd004, 0xbe000),
1706};
1707
1708static const struct msm_gpio_wakeirq_map nord_pdc_map[] = {
1709 { 0, 67 }, { 1, 68 }, { 2, 82 }, { 3, 69 }, { 4, 70 },
1710 { 5, 83 }, { 6, 71 }, { 7, 72 }, { 8, 84 }, { 9, 73 },
1711 { 10, 119 }, { 11, 85 }, { 45, 107 }, { 46, 98 }, { 102, 77 },
1712 { 108, 78 }, { 110, 120 }, { 114, 80 }, { 116, 81 }, { 120, 117 },
1713 { 124, 108 }, { 126, 99 }, { 128, 100 }, { 132, 101 }, { 138, 87 },
1714 { 142, 88 }, { 144, 89 }, { 153, 90 }, { 157, 91 }, { 159, 118 },
1715 { 160, 110 }, { 161, 79 }, { 166, 109 }, { 168, 111 },
1716};
1717
1718static const struct msm_pinctrl_soc_data nord_tlmm = {
1719 .pins = nord_pins,
1720 .npins = ARRAY_SIZE(nord_pins),
1721 .functions = nord_functions,
1722 .nfunctions = ARRAY_SIZE(nord_functions),
1723 .groups = nord_groups,
1724 .ngroups = ARRAY_SIZE(nord_groups),
1725 .ngpios = 182,
1726 .wakeirq_map = nord_pdc_map,
1727 .nwakeirq_map = ARRAY_SIZE(nord_pdc_map),
1728 .egpio_func = 11,
1729};
1730
1731static const struct of_device_id nord_tlmm_of_match[] = {
1732 { .compatible = "qcom,nord-tlmm", .data = &nord_tlmm },
1733 {},
1734};
1735
1736static int nord_tlmm_probe(struct platform_device *pdev)
1737{
1738 const struct msm_pinctrl_soc_data *pinctrl_data;
1739 struct device *dev = &pdev->dev;
1740
1741 pinctrl_data = device_get_match_data(dev);
1742 if (!pinctrl_data)
1743 return -EINVAL;
1744
1745 return msm_pinctrl_probe(pdev, &nord_tlmm);
1746}
1747
1748static struct platform_driver nord_tlmm_driver = {
1749 .driver = {
1750 .name = "nord-tlmm",
1751 .of_match_table = nord_tlmm_of_match,
1752 },
1753 .probe = nord_tlmm_probe,
1754};
1755
1756static int __init nord_tlmm_init(void)
1757{
1758 return platform_driver_register(&nord_tlmm_driver);
1759}
1760arch_initcall(nord_tlmm_init);
1761
1762static void __exit nord_tlmm_exit(void)
1763{
1764 platform_driver_unregister(&nord_tlmm_driver);
1765}
1766module_exit(nord_tlmm_exit);
1767
1768MODULE_DESCRIPTION("QTI Nord TLMM driver");
1769MODULE_LICENSE("GPL");
1770MODULE_DEVICE_TABLE(of, nord_tlmm_of_match);
drivers/pinctrl/qcom/pinctrl-qcm2290.c+1−24
@@ -75,29 +75,6 @@ · 74 unmodified lines
75 .intr_detection_width = -1, \75 .intr_detection_width = -1, \
76 }76 }
77 77
78#define UFS_RESET(pg_name, offset) \
79 { \
80 .grp = PINCTRL_PINGROUP(#pg_name, \
81 pg_name##_pins, \
82 ARRAY_SIZE(pg_name##_pins)), \
83 .ctl_reg = offset, \
84 .io_reg = offset + 0x4, \
85 .intr_cfg_reg = 0, \
86 .intr_status_reg = 0, \
87 .mux_bit = -1, \
88 .pull_bit = 3, \
89 .drv_bit = 0, \
90 .oe_bit = -1, \
91 .in_bit = -1, \
92 .out_bit = 0, \
93 .intr_enable_bit = -1, \
94 .intr_status_bit = -1, \
95 .intr_target_bit = -1, \
96 .intr_raw_status_bit = -1, \
97 .intr_polarity_bit = -1, \
98 .intr_detection_bit = -1, \
99 .intr_detection_width = -1, \
100 }
101static const struct pinctrl_pin_desc qcm2290_pins[] = {78static const struct pinctrl_pin_desc qcm2290_pins[] = {
102 PINCTRL_PIN(0, "GPIO_0"),79 PINCTRL_PIN(0, "GPIO_0"),
103 PINCTRL_PIN(1, "GPIO_1"),80 PINCTRL_PIN(1, "GPIO_1"),
@@ -1124,6 +1101,7 @@ static const struct of_device_id qcm2290_pinctrl_of_match[] = { · 1020 unmodified lines
1124 { .compatible = "qcom,qcm2290-tlmm", },1101 { .compatible = "qcom,qcm2290-tlmm", },
1125 { },1102 { },
1126};1103};
1104MODULE_DEVICE_TABLE(of, qcm2290_pinctrl_of_match);
1127 1105
1128static struct platform_driver qcm2290_pinctrl_driver = {1106static struct platform_driver qcm2290_pinctrl_driver = {
1129 .driver = {1107 .driver = {
@@ -1147,4 +1125,3 @@ module_exit(qcm2290_pinctrl_exit); · 17 unmodified lines
1147 1125
1148MODULE_DESCRIPTION("QTI QCM2290 pinctrl driver");1126MODULE_DESCRIPTION("QTI QCM2290 pinctrl driver");
1149MODULE_LICENSE("GPL v2");1127MODULE_LICENSE("GPL v2");
1150MODULE_DEVICE_TABLE(of, qcm2290_pinctrl_of_match);
drivers/pinctrl/qcom/pinctrl-qcs404.c+1−1
@@ -1635,6 +1635,7 @@ static const struct of_device_id qcs404_pinctrl_of_match[] = { · 1634 unmodified lines
1635 { .compatible = "qcom,qcs404-pinctrl", },1635 { .compatible = "qcom,qcs404-pinctrl", },
1636 { },1636 { },
1637};1637};
1638MODULE_DEVICE_TABLE(of, qcs404_pinctrl_of_match);
1638 1639
1639static struct platform_driver qcs404_pinctrl_driver = {1640static struct platform_driver qcs404_pinctrl_driver = {
1640 .driver = {1641 .driver = {
@@ -1658,4 +1659,3 @@ module_exit(qcs404_pinctrl_exit); · 17 unmodified lines
1658 1659
1659MODULE_DESCRIPTION("Qualcomm QCS404 pinctrl driver");1660MODULE_DESCRIPTION("Qualcomm QCS404 pinctrl driver");
1660MODULE_LICENSE("GPL v2");1661MODULE_LICENSE("GPL v2");
1661MODULE_DEVICE_TABLE(of, qcs404_pinctrl_of_match);
drivers/pinctrl/qcom/pinctrl-qcs615.c+1−1
@@ -1073,6 +1073,7 @@ static const struct of_device_id qcs615_tlmm_of_match[] = { · 1072 unmodified lines
1073 },1073 },
1074 {},1074 {},
1075};1075};
1076MODULE_DEVICE_TABLE(of, qcs615_tlmm_of_match);
1076 1077
1077static int qcs615_tlmm_probe(struct platform_device *pdev)1078static int qcs615_tlmm_probe(struct platform_device *pdev)
1078{1079{
@@ -1101,4 +1102,3 @@ module_exit(qcs615_tlmm_exit); · 22 unmodified lines
1101 1102
1102MODULE_DESCRIPTION("QTI QCS615 TLMM driver");1103MODULE_DESCRIPTION("QTI QCS615 TLMM driver");
1103MODULE_LICENSE("GPL");1104MODULE_LICENSE("GPL");
1104MODULE_DEVICE_TABLE(of, qcs615_tlmm_of_match);
drivers/pinctrl/qcom/pinctrl-qcs8300.c+0−6
@@ -100,12 +100,6 @@ · 99 unmodified lines
100 .intr_detection_width = -1, \100 .intr_detection_width = -1, \
101 }101 }
102 102
103#define QUP_I3C(qup_mode, qup_offset) \
104 { \
105 .mode = qup_mode, \
106 .offset = qup_offset, \
107 }
108
109#define QUP_I3C_6_MODE_OFFSET 0xaf000103#define QUP_I3C_6_MODE_OFFSET 0xaf000
110#define QUP_I3C_7_MODE_OFFSET 0xb0000104#define QUP_I3C_7_MODE_OFFSET 0xb0000
111#define QUP_I3C_13_MODE_OFFSET 0xb1000105#define QUP_I3C_13_MODE_OFFSET 0xb1000
drivers/pinctrl/qcom/pinctrl-qdu1000.c+0−30
@@ -75,36 +75,6 @@ · 74 unmodified lines
75 .intr_detection_width = -1, \75 .intr_detection_width = -1, \
76 }76 }
77 77
78#define UFS_RESET(pg_name, offset) \
79 { \
80 .grp = PINCTRL_PINGROUP(#pg_name, \
81 pg_name##_pins, \
82 ARRAY_SIZE(pg_name##_pins)), \
83 .ctl_reg = offset, \
84 .io_reg = offset + 0x4, \
85 .intr_cfg_reg = 0, \
86 .intr_status_reg = 0, \
87 .mux_bit = -1, \
88 .pull_bit = 3, \
89 .drv_bit = 0, \
90 .oe_bit = -1, \
91 .in_bit = -1, \
92 .out_bit = 0, \
93 .intr_enable_bit = -1, \
94 .intr_status_bit = -1, \
95 .intr_target_bit = -1, \
96 .intr_raw_status_bit = -1, \
97 .intr_polarity_bit = -1, \
98 .intr_detection_bit = -1, \
99 .intr_detection_width = -1, \
100 }
101
102#define QUP_I3C(qup_mode, qup_offset) \
103 { \
104 .mode = qup_mode, \
105 .offset = qup_offset, \
106 }
107
108static const struct pinctrl_pin_desc qdu1000_pins[] = {78static const struct pinctrl_pin_desc qdu1000_pins[] = {
109 PINCTRL_PIN(0, "GPIO_0"),79 PINCTRL_PIN(0, "GPIO_0"),
110 PINCTRL_PIN(1, "GPIO_1"),80 PINCTRL_PIN(1, "GPIO_1"),
drivers/pinctrl/qcom/pinctrl-sa8775p.c+0−6
@@ -101,12 +101,6 @@ · 100 unmodified lines
101 .intr_detection_width = -1, \101 .intr_detection_width = -1, \
102 }102 }
103 103
104#define QUP_I3C(qup_mode, qup_offset) \
105 { \
106 .mode = qup_mode, \
107 .offset = qup_offset, \
108 }
109
110#define QUP_I3C_6_MODE_OFFSET 0xAF000104#define QUP_I3C_6_MODE_OFFSET 0xAF000
111#define QUP_I3C_7_MODE_OFFSET 0xB0000105#define QUP_I3C_7_MODE_OFFSET 0xB0000
112#define QUP_I3C_13_MODE_OFFSET 0xB1000106#define QUP_I3C_13_MODE_OFFSET 0xB1000
drivers/pinctrl/qcom/pinctrl-sc7180.c+1−1
@@ -1148,6 +1148,7 @@ static const struct of_device_id sc7180_pinctrl_of_match[] = { · 1147 unmodified lines
1148 { .compatible = "qcom,sc7180-pinctrl", },1148 { .compatible = "qcom,sc7180-pinctrl", },
1149 { },1149 { },
1150};1150};
1151MODULE_DEVICE_TABLE(of, sc7180_pinctrl_of_match);
1151 1152
1152static struct platform_driver sc7180_pinctrl_driver = {1153static struct platform_driver sc7180_pinctrl_driver = {
1153 .driver = {1154 .driver = {
@@ -1172,4 +1173,3 @@ module_exit(sc7180_pinctrl_exit); · 18 unmodified lines
1172 1173
1173MODULE_DESCRIPTION("QTI sc7180 pinctrl driver");1174MODULE_DESCRIPTION("QTI sc7180 pinctrl driver");
1174MODULE_LICENSE("GPL v2");1175MODULE_LICENSE("GPL v2");
1175MODULE_DEVICE_TABLE(of, sc7180_pinctrl_of_match);
drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c+13−6
@@ -7,6 +7,8 @@ · 6 unmodified lines
7#include <linux/gpio/driver.h>7#include <linux/gpio/driver.h>
8#include <linux/module.h>8#include <linux/module.h>
9#include <linux/platform_device.h>9#include <linux/platform_device.h>
10#include <linux/pm_clock.h>
11#include <linux/pm_runtime.h>
10 12
11#include "pinctrl-lpass-lpi.h"13#include "pinctrl-lpass-lpi.h"
12 14
@@ -129,20 +131,25 @@ static const struct lpi_pinctrl_variant_data sc7280_lpi_data = { · 116 unmodified lines
129 131
130static const struct of_device_id lpi_pinctrl_of_match[] = {132static const struct of_device_id lpi_pinctrl_of_match[] = {
131 {133 {
132 .compatible = "qcom,sc7280-lpass-lpi-pinctrl",134 .compatible = "qcom,sc7280-lpass-lpi-pinctrl",
133 .data = &sc7280_lpi_data,135 .data = &sc7280_lpi_data,
134 }, {136 }, {
135 .compatible = "qcom,sm8350-lpass-lpi-pinctrl",137 .compatible = "qcom,sm8350-lpass-lpi-pinctrl",
136 .data = &sc7280_lpi_data,138 .data = &sc7280_lpi_data,
137 },139 },
138 { }140 { }
139};141};
140MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match);142MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match);
141 143
144static const struct dev_pm_ops lpi_pinctrl_pm_ops = {
145 RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL)
146};
147
142static struct platform_driver lpi_pinctrl_driver = {148static struct platform_driver lpi_pinctrl_driver = {
143 .driver = {149 .driver = {
144 .name = "qcom-sc7280-lpass-lpi-pinctrl",150 .name = "qcom-sc7280-lpass-lpi-pinctrl",
145 .of_match_table = lpi_pinctrl_of_match,151 .of_match_table = lpi_pinctrl_of_match,
152 .pm = pm_ptr(&lpi_pinctrl_pm_ops),
146 },153 },
147 .probe = lpi_pinctrl_probe,154 .probe = lpi_pinctrl_probe,
148 .remove = lpi_pinctrl_remove,155 .remove = lpi_pinctrl_remove,
drivers/pinctrl/qcom/pinctrl-sc7280.c+1−1
@@ -1494,6 +1494,7 @@ static const struct of_device_id sc7280_pinctrl_of_match[] = { · 1493 unmodified lines
1494 { .compatible = "qcom,sc7280-pinctrl", },1494 { .compatible = "qcom,sc7280-pinctrl", },
1495 { },1495 { },
1496};1496};
1497MODULE_DEVICE_TABLE(of, sc7280_pinctrl_of_match);
1497 1498
1498static struct platform_driver sc7280_pinctrl_driver = {1499static struct platform_driver sc7280_pinctrl_driver = {
1499 .driver = {1500 .driver = {
@@ -1518,4 +1519,3 @@ module_exit(sc7280_pinctrl_exit); · 18 unmodified lines
1518 1519
1519MODULE_DESCRIPTION("QTI sc7280 pinctrl driver");1520MODULE_DESCRIPTION("QTI sc7280 pinctrl driver");
1520MODULE_LICENSE("GPL v2");1521MODULE_LICENSE("GPL v2");
1521MODULE_DEVICE_TABLE(of, sc7280_pinctrl_of_match);
drivers/pinctrl/qcom/pinctrl-sc8280xp-lpass-lpi.c+11−4
@@ -6,6 +6,8 @@ · 5 unmodified lines
6#include <linux/gpio/driver.h>6#include <linux/gpio/driver.h>
7#include <linux/module.h>7#include <linux/module.h>
8#include <linux/platform_device.h>8#include <linux/platform_device.h>
9#include <linux/pm_clock.h>
10#include <linux/pm_runtime.h>
9 11
10#include "pinctrl-lpass-lpi.h"12#include "pinctrl-lpass-lpi.h"
11 13
@@ -166,17 +168,22 @@ static const struct lpi_pinctrl_variant_data sc8280xp_lpi_data = { · 154 unmodified lines
166 168
167static const struct of_device_id lpi_pinctrl_of_match[] = {169static const struct of_device_id lpi_pinctrl_of_match[] = {
168 {170 {
169 .compatible = "qcom,sc8280xp-lpass-lpi-pinctrl",171 .compatible = "qcom,sc8280xp-lpass-lpi-pinctrl",
170 .data = &sc8280xp_lpi_data,172 .data = &sc8280xp_lpi_data,
171 },173 },
172 { }174 { }
173};175};
174MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match);176MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match);
175 177
178static const struct dev_pm_ops lpi_pinctrl_pm_ops = {
179 RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL)
180};
181
176static struct platform_driver lpi_pinctrl_driver = {182static struct platform_driver lpi_pinctrl_driver = {
177 .driver = {183 .driver = {
178 .name = "qcom-sc8280xp-lpass-lpi-pinctrl",184 .name = "qcom-sc8280xp-lpass-lpi-pinctrl",
179 .of_match_table = lpi_pinctrl_of_match,185 .of_match_table = lpi_pinctrl_of_match,
186 .pm = pm_ptr(&lpi_pinctrl_pm_ops),
180 },187 },
181 .probe = lpi_pinctrl_probe,188 .probe = lpi_pinctrl_probe,
182 .remove = lpi_pinctrl_remove,189 .remove = lpi_pinctrl_remove,
drivers/pinctrl/qcom/pinctrl-sdm660-lpass-lpi.c+7−0
@@ -10,6 +10,8 @@ · 9 unmodified lines
10#include <linux/module.h>10#include <linux/module.h>
11#include <linux/of.h>11#include <linux/of.h>
12#include <linux/platform_device.h>12#include <linux/platform_device.h>
13#include <linux/pm_clock.h>
14#include <linux/pm_runtime.h>
13#include <linux/pinctrl/pinctrl.h>15#include <linux/pinctrl/pinctrl.h>
14 16
15#include "pinctrl-lpass-lpi.h"17#include "pinctrl-lpass-lpi.h"
@@ -145,10 +147,15 @@ static const struct of_device_id sdm660_lpi_pinctrl_of_match[] = { · 129 unmodified lines
145};147};
146MODULE_DEVICE_TABLE(of, sdm660_lpi_pinctrl_of_match);148MODULE_DEVICE_TABLE(of, sdm660_lpi_pinctrl_of_match);
147 149
150static const struct dev_pm_ops lpi_pinctrl_pm_ops = {
151 RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL)
152};
153
148static struct platform_driver sdm660_lpi_pinctrl_driver = {154static struct platform_driver sdm660_lpi_pinctrl_driver = {
149 .driver = {155 .driver = {
150 .name = "qcom-sdm660-lpass-lpi-pinctrl",156 .name = "qcom-sdm660-lpass-lpi-pinctrl",
151 .of_match_table = sdm660_lpi_pinctrl_of_match,157 .of_match_table = sdm660_lpi_pinctrl_of_match,
158 .pm = pm_ptr(&lpi_pinctrl_pm_ops),
152 },159 },
153 .probe = lpi_pinctrl_probe,160 .probe = lpi_pinctrl_probe,
154 .remove = lpi_pinctrl_remove,161 .remove = lpi_pinctrl_remove,
drivers/pinctrl/qcom/pinctrl-sdm660.c+1−1
@@ -1433,6 +1433,7 @@ static const struct of_device_id sdm660_pinctrl_of_match[] = { · 1432 unmodified lines
1433 { .compatible = "qcom,sdm630-pinctrl", },1433 { .compatible = "qcom,sdm630-pinctrl", },
1434 { },1434 { },
1435};1435};
1436MODULE_DEVICE_TABLE(of, sdm660_pinctrl_of_match);
1436 1437
1437static struct platform_driver sdm660_pinctrl_driver = {1438static struct platform_driver sdm660_pinctrl_driver = {
1438 .driver = {1439 .driver = {
@@ -1456,4 +1457,3 @@ module_exit(sdm660_pinctrl_exit); · 17 unmodified lines
1456 1457
1457MODULE_DESCRIPTION("QTI sdm660 pinctrl driver");1458MODULE_DESCRIPTION("QTI sdm660 pinctrl driver");
1458MODULE_LICENSE("GPL v2");1459MODULE_LICENSE("GPL v2");
1459MODULE_DEVICE_TABLE(of, sdm660_pinctrl_of_match);
drivers/pinctrl/qcom/pinctrl-sdm670-lpass-lpi.c+7−0
@@ -7,6 +7,8 @@ · 6 unmodified lines
7#include <linux/module.h>7#include <linux/module.h>
8#include <linux/of.h>8#include <linux/of.h>
9#include <linux/platform_device.h>9#include <linux/platform_device.h>
10#include <linux/pm_clock.h>
11#include <linux/pm_runtime.h>
10#include <linux/pinctrl/pinctrl.h>12#include <linux/pinctrl/pinctrl.h>
11 13
12#include "pinctrl-lpass-lpi.h"14#include "pinctrl-lpass-lpi.h"
@@ -151,10 +153,15 @@ static const struct of_device_id sdm670_lpi_pinctrl_of_match[] = { · 138 unmodified lines
151};153};
152MODULE_DEVICE_TABLE(of, sdm670_lpi_pinctrl_of_match);154MODULE_DEVICE_TABLE(of, sdm670_lpi_pinctrl_of_match);
153 155
156static const struct dev_pm_ops lpi_pinctrl_pm_ops = {
157 RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL)
158};
159
154static struct platform_driver sdm670_lpi_pinctrl_driver = {160static struct platform_driver sdm670_lpi_pinctrl_driver = {
155 .driver = {161 .driver = {
156 .name = "qcom-sdm670-lpass-lpi-pinctrl",162 .name = "qcom-sdm670-lpass-lpi-pinctrl",
157 .of_match_table = sdm670_lpi_pinctrl_of_match,163 .of_match_table = sdm670_lpi_pinctrl_of_match,
164 .pm = pm_ptr(&lpi_pinctrl_pm_ops),
158 },165 },
159 .probe = lpi_pinctrl_probe,166 .probe = lpi_pinctrl_probe,
160 .remove = lpi_pinctrl_remove,167 .remove = lpi_pinctrl_remove,
drivers/pinctrl/qcom/pinctrl-sdm845.c+1−1
@@ -1339,6 +1339,7 @@ static const struct of_device_id sdm845_pinctrl_of_match[] = { · 1338 unmodified lines
1339 { .compatible = "qcom,sdm845-pinctrl", },1339 { .compatible = "qcom,sdm845-pinctrl", },
1340 { },1340 { },
1341};1341};
1342MODULE_DEVICE_TABLE(of, sdm845_pinctrl_of_match);
1342 1343
1343static struct platform_driver sdm845_pinctrl_driver = {1344static struct platform_driver sdm845_pinctrl_driver = {
1344 .driver = {1345 .driver = {
@@ -1364,4 +1365,3 @@ module_exit(sdm845_pinctrl_exit); · 19 unmodified lines
1364 1365
1365MODULE_DESCRIPTION("QTI sdm845 pinctrl driver");1366MODULE_DESCRIPTION("QTI sdm845 pinctrl driver");
1366MODULE_LICENSE("GPL v2");1367MODULE_LICENSE("GPL v2");
1367MODULE_DEVICE_TABLE(of, sdm845_pinctrl_of_match);
drivers/pinctrl/qcom/pinctrl-sdx55.c+1−1
@@ -981,6 +981,7 @@ static const struct of_device_id sdx55_pinctrl_of_match[] = { · 980 unmodified lines
981 { .compatible = "qcom,sdx55-pinctrl", },981 { .compatible = "qcom,sdx55-pinctrl", },
982 { },982 { },
983};983};
984MODULE_DEVICE_TABLE(of, sdx55_pinctrl_of_match);
984 985
985static struct platform_driver sdx55_pinctrl_driver = {986static struct platform_driver sdx55_pinctrl_driver = {
986 .driver = {987 .driver = {
@@ -1004,4 +1005,3 @@ module_exit(sdx55_pinctrl_exit); · 17 unmodified lines
1004 1005
1005MODULE_DESCRIPTION("QTI sdx55 pinctrl driver");1006MODULE_DESCRIPTION("QTI sdx55 pinctrl driver");
1006MODULE_LICENSE("GPL v2");1007MODULE_LICENSE("GPL v2");
1007MODULE_DEVICE_TABLE(of, sdx55_pinctrl_of_match);
drivers/pinctrl/qcom/pinctrl-sdx65.c+1−1
@@ -929,6 +929,7 @@ static const struct of_device_id sdx65_pinctrl_of_match[] = { · 928 unmodified lines
929 { .compatible = "qcom,sdx65-tlmm", },929 { .compatible = "qcom,sdx65-tlmm", },
930 { },930 { },
931};931};
932MODULE_DEVICE_TABLE(of, sdx65_pinctrl_of_match);
932 933
933static struct platform_driver sdx65_pinctrl_driver = {934static struct platform_driver sdx65_pinctrl_driver = {
934 .driver = {935 .driver = {
@@ -952,4 +953,3 @@ module_exit(sdx65_pinctrl_exit); · 17 unmodified lines
952 953
953MODULE_DESCRIPTION("QTI sdx65 pinctrl driver");954MODULE_DESCRIPTION("QTI sdx65 pinctrl driver");
954MODULE_LICENSE("GPL v2");955MODULE_LICENSE("GPL v2");
955MODULE_DEVICE_TABLE(of, sdx65_pinctrl_of_match);
drivers/pinctrl/qcom/pinctrl-shikra.c+1253−0
@@ -0,0 +1,1253 @@
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
4 */
5
6#include <linux/module.h>
7#include <linux/of.h>
8#include <linux/platform_device.h>
9
10#include "pinctrl-msm.h"
11
12#define REG_SIZE 0x1000
13#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11) \
14 { \
15 .grp = PINCTRL_PINGROUP("gpio" #id, \
16 gpio##id##_pins, \
17 ARRAY_SIZE(gpio##id##_pins)), \
18 .funcs = (int[]){ \
19 msm_mux_gpio, /* gpio mode */ \
20 msm_mux_##f1, \
21 msm_mux_##f2, \
22 msm_mux_##f3, \
23 msm_mux_##f4, \
24 msm_mux_##f5, \
25 msm_mux_##f6, \
26 msm_mux_##f7, \
27 msm_mux_##f8, \
28 msm_mux_##f9, \
29 msm_mux_##f10, \
30 msm_mux_##f11 \
31 }, \
32 .nfuncs = 12, \
33 .ctl_reg = REG_SIZE * id, \
34 .io_reg = 0x4 + REG_SIZE * id, \
35 .intr_cfg_reg = 0x8 + REG_SIZE * id, \
36 .intr_status_reg = 0xc + REG_SIZE * id, \
37 .mux_bit = 2, \
38 .pull_bit = 0, \
39 .drv_bit = 6, \
40 .oe_bit = 9, \
41 .in_bit = 0, \
42 .out_bit = 1, \
43 .intr_enable_bit = 0, \
44 .intr_status_bit = 0, \
45 .intr_wakeup_enable_bit = 7, \
46 .intr_wakeup_present_bit = 6, \
47 .intr_target_bit = 8, \
48 .intr_target_kpss_val = 3, \
49 .intr_raw_status_bit = 4, \
50 .intr_polarity_bit = 1, \
51 .intr_detection_bit = 2, \
52 .intr_detection_width = 2, \
53 }
54
55#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \
56 { \
57 .grp = PINCTRL_PINGROUP(#pg_name, \
58 pg_name##_pins, \
59 ARRAY_SIZE(pg_name##_pins)), \
60 .ctl_reg = ctl, \
61 .io_reg = 0, \
62 .intr_cfg_reg = 0, \
63 .intr_status_reg = 0, \
64 .mux_bit = -1, \
65 .pull_bit = pull, \
66 .drv_bit = drv, \
67 .oe_bit = -1, \
68 .in_bit = -1, \
69 .out_bit = -1, \
70 .intr_enable_bit = -1, \
71 .intr_status_bit = -1, \
72 .intr_target_bit = -1, \
73 .intr_raw_status_bit = -1, \
74 .intr_polarity_bit = -1, \
75 .intr_detection_bit = -1, \
76 .intr_detection_width = -1, \
77 }
78
79static const struct pinctrl_pin_desc shikra_pins[] = {
80 PINCTRL_PIN(0, "GPIO_0"),
81 PINCTRL_PIN(1, "GPIO_1"),
82 PINCTRL_PIN(2, "GPIO_2"),
83 PINCTRL_PIN(3, "GPIO_3"),
84 PINCTRL_PIN(4, "GPIO_4"),
85 PINCTRL_PIN(5, "GPIO_5"),
86 PINCTRL_PIN(6, "GPIO_6"),
87 PINCTRL_PIN(7, "GPIO_7"),
88 PINCTRL_PIN(8, "GPIO_8"),
89 PINCTRL_PIN(9, "GPIO_9"),
90 PINCTRL_PIN(10, "GPIO_10"),
91 PINCTRL_PIN(11, "GPIO_11"),
92 PINCTRL_PIN(12, "GPIO_12"),
93 PINCTRL_PIN(13, "GPIO_13"),
94 PINCTRL_PIN(14, "GPIO_14"),
95 PINCTRL_PIN(15, "GPIO_15"),
96 PINCTRL_PIN(16, "GPIO_16"),
97 PINCTRL_PIN(17, "GPIO_17"),
98 PINCTRL_PIN(18, "GPIO_18"),
99 PINCTRL_PIN(19, "GPIO_19"),
100 PINCTRL_PIN(20, "GPIO_20"),
101 PINCTRL_PIN(21, "GPIO_21"),
102 PINCTRL_PIN(22, "GPIO_22"),
103 PINCTRL_PIN(23, "GPIO_23"),
104 PINCTRL_PIN(24, "GPIO_24"),
105 PINCTRL_PIN(25, "GPIO_25"),
106 PINCTRL_PIN(26, "GPIO_26"),
107 PINCTRL_PIN(27, "GPIO_27"),
108 PINCTRL_PIN(28, "GPIO_28"),
109 PINCTRL_PIN(29, "GPIO_29"),
110 PINCTRL_PIN(30, "GPIO_30"),
111 PINCTRL_PIN(31, "GPIO_31"),
112 PINCTRL_PIN(32, "GPIO_32"),
113 PINCTRL_PIN(33, "GPIO_33"),
114 PINCTRL_PIN(34, "GPIO_34"),
115 PINCTRL_PIN(35, "GPIO_35"),
116 PINCTRL_PIN(36, "GPIO_36"),
117 PINCTRL_PIN(37, "GPIO_37"),
118 PINCTRL_PIN(38, "GPIO_38"),
119 PINCTRL_PIN(39, "GPIO_39"),
120 PINCTRL_PIN(40, "GPIO_40"),
121 PINCTRL_PIN(41, "GPIO_41"),
122 PINCTRL_PIN(42, "GPIO_42"),
123 PINCTRL_PIN(43, "GPIO_43"),
124 PINCTRL_PIN(44, "GPIO_44"),
125 PINCTRL_PIN(45, "GPIO_45"),
126 PINCTRL_PIN(46, "GPIO_46"),
127 PINCTRL_PIN(47, "GPIO_47"),
128 PINCTRL_PIN(48, "GPIO_48"),
129 PINCTRL_PIN(49, "GPIO_49"),
130 PINCTRL_PIN(50, "GPIO_50"),
131 PINCTRL_PIN(51, "GPIO_51"),
132 PINCTRL_PIN(52, "GPIO_52"),
133 PINCTRL_PIN(53, "GPIO_53"),
134 PINCTRL_PIN(54, "GPIO_54"),
135 PINCTRL_PIN(55, "GPIO_55"),
136 PINCTRL_PIN(56, "GPIO_56"),
137 PINCTRL_PIN(57, "GPIO_57"),
138 PINCTRL_PIN(58, "GPIO_58"),
139 PINCTRL_PIN(59, "GPIO_59"),
140 PINCTRL_PIN(60, "GPIO_60"),
141 PINCTRL_PIN(61, "GPIO_61"),
142 PINCTRL_PIN(62, "GPIO_62"),
143 PINCTRL_PIN(63, "GPIO_63"),
144 PINCTRL_PIN(64, "GPIO_64"),
145 PINCTRL_PIN(65, "GPIO_65"),
146 PINCTRL_PIN(66, "GPIO_66"),
147 PINCTRL_PIN(67, "GPIO_67"),
148 PINCTRL_PIN(68, "GPIO_68"),
149 PINCTRL_PIN(69, "GPIO_69"),
150 PINCTRL_PIN(70, "GPIO_70"),
151 PINCTRL_PIN(71, "GPIO_71"),
152 PINCTRL_PIN(72, "GPIO_72"),
153 PINCTRL_PIN(73, "GPIO_73"),
154 PINCTRL_PIN(74, "GPIO_74"),
155 PINCTRL_PIN(75, "GPIO_75"),
156 PINCTRL_PIN(76, "GPIO_76"),
157 PINCTRL_PIN(77, "GPIO_77"),
158 PINCTRL_PIN(78, "GPIO_78"),
159 PINCTRL_PIN(79, "GPIO_79"),
160 PINCTRL_PIN(80, "GPIO_80"),
161 PINCTRL_PIN(81, "GPIO_81"),
162 PINCTRL_PIN(82, "GPIO_82"),
163 PINCTRL_PIN(83, "GPIO_83"),
164 PINCTRL_PIN(84, "GPIO_84"),
165 PINCTRL_PIN(85, "GPIO_85"),
166 PINCTRL_PIN(86, "GPIO_86"),
167 PINCTRL_PIN(87, "GPIO_87"),
168 PINCTRL_PIN(88, "GPIO_88"),
169 PINCTRL_PIN(89, "GPIO_89"),
170 PINCTRL_PIN(90, "GPIO_90"),
171 PINCTRL_PIN(91, "GPIO_91"),
172 PINCTRL_PIN(92, "GPIO_92"),
173 PINCTRL_PIN(93, "GPIO_93"),
174 PINCTRL_PIN(94, "GPIO_94"),
175 PINCTRL_PIN(95, "GPIO_95"),
176 PINCTRL_PIN(96, "GPIO_96"),
177 PINCTRL_PIN(97, "GPIO_97"),
178 PINCTRL_PIN(98, "GPIO_98"),
179 PINCTRL_PIN(99, "GPIO_99"),
180 PINCTRL_PIN(100, "GPIO_100"),
181 PINCTRL_PIN(101, "GPIO_101"),
182 PINCTRL_PIN(102, "GPIO_102"),
183 PINCTRL_PIN(103, "GPIO_103"),
184 PINCTRL_PIN(104, "GPIO_104"),
185 PINCTRL_PIN(105, "GPIO_105"),
186 PINCTRL_PIN(106, "GPIO_106"),
187 PINCTRL_PIN(107, "GPIO_107"),
188 PINCTRL_PIN(108, "GPIO_108"),
189 PINCTRL_PIN(109, "GPIO_109"),
190 PINCTRL_PIN(110, "GPIO_110"),
191 PINCTRL_PIN(111, "GPIO_111"),
192 PINCTRL_PIN(112, "GPIO_112"),
193 PINCTRL_PIN(113, "GPIO_113"),
194 PINCTRL_PIN(114, "GPIO_114"),
195 PINCTRL_PIN(115, "GPIO_115"),
196 PINCTRL_PIN(116, "GPIO_116"),
197 PINCTRL_PIN(117, "GPIO_117"),
198 PINCTRL_PIN(118, "GPIO_118"),
199 PINCTRL_PIN(119, "GPIO_119"),
200 PINCTRL_PIN(120, "GPIO_120"),
201 PINCTRL_PIN(121, "GPIO_121"),
202 PINCTRL_PIN(122, "GPIO_122"),
203 PINCTRL_PIN(123, "GPIO_123"),
204 PINCTRL_PIN(124, "GPIO_124"),
205 PINCTRL_PIN(125, "GPIO_125"),
206 PINCTRL_PIN(126, "GPIO_126"),
207 PINCTRL_PIN(127, "GPIO_127"),
208 PINCTRL_PIN(128, "GPIO_128"),
209 PINCTRL_PIN(129, "GPIO_129"),
210 PINCTRL_PIN(130, "GPIO_130"),
211 PINCTRL_PIN(131, "GPIO_131"),
212 PINCTRL_PIN(132, "GPIO_132"),
213 PINCTRL_PIN(133, "GPIO_133"),
214 PINCTRL_PIN(134, "GPIO_134"),
215 PINCTRL_PIN(135, "GPIO_135"),
216 PINCTRL_PIN(136, "GPIO_136"),
217 PINCTRL_PIN(137, "GPIO_137"),
218 PINCTRL_PIN(138, "GPIO_138"),
219 PINCTRL_PIN(139, "GPIO_139"),
220 PINCTRL_PIN(140, "GPIO_140"),
221 PINCTRL_PIN(141, "GPIO_141"),
222 PINCTRL_PIN(142, "GPIO_142"),
223 PINCTRL_PIN(143, "GPIO_143"),
224 PINCTRL_PIN(144, "GPIO_144"),
225 PINCTRL_PIN(145, "GPIO_145"),
226 PINCTRL_PIN(146, "GPIO_146"),
227 PINCTRL_PIN(147, "GPIO_147"),
228 PINCTRL_PIN(148, "GPIO_148"),
229 PINCTRL_PIN(149, "GPIO_149"),
230 PINCTRL_PIN(150, "GPIO_150"),
231 PINCTRL_PIN(151, "GPIO_151"),
232 PINCTRL_PIN(152, "GPIO_152"),
233 PINCTRL_PIN(153, "GPIO_153"),
234 PINCTRL_PIN(154, "GPIO_154"),
235 PINCTRL_PIN(155, "GPIO_155"),
236 PINCTRL_PIN(156, "GPIO_156"),
237 PINCTRL_PIN(157, "GPIO_157"),
238 PINCTRL_PIN(158, "GPIO_158"),
239 PINCTRL_PIN(159, "GPIO_159"),
240 PINCTRL_PIN(160, "GPIO_160"),
241 PINCTRL_PIN(161, "GPIO_161"),
242 PINCTRL_PIN(162, "GPIO_162"),
243 PINCTRL_PIN(163, "GPIO_163"),
244 PINCTRL_PIN(164, "GPIO_164"),
245 PINCTRL_PIN(165, "GPIO_165"),
246 PINCTRL_PIN(166, "SDC1_RCLK"),
247 PINCTRL_PIN(167, "SDC1_CLK"),
248 PINCTRL_PIN(168, "SDC1_CMD"),
249 PINCTRL_PIN(169, "SDC1_DATA"),
250 PINCTRL_PIN(170, "SDC2_CLK"),
251 PINCTRL_PIN(171, "SDC2_CMD"),
252 PINCTRL_PIN(172, "SDC2_DATA"),
253};
254
255#define DECLARE_MSM_GPIO_PINS(pin) \
256 static const unsigned int gpio##pin##_pins[] = { pin }
257DECLARE_MSM_GPIO_PINS(0);
258DECLARE_MSM_GPIO_PINS(1);
259DECLARE_MSM_GPIO_PINS(2);
260DECLARE_MSM_GPIO_PINS(3);
261DECLARE_MSM_GPIO_PINS(4);
262DECLARE_MSM_GPIO_PINS(5);
263DECLARE_MSM_GPIO_PINS(6);
264DECLARE_MSM_GPIO_PINS(7);
265DECLARE_MSM_GPIO_PINS(8);
266DECLARE_MSM_GPIO_PINS(9);
267DECLARE_MSM_GPIO_PINS(10);
268DECLARE_MSM_GPIO_PINS(11);
269DECLARE_MSM_GPIO_PINS(12);
270DECLARE_MSM_GPIO_PINS(13);
271DECLARE_MSM_GPIO_PINS(14);
272DECLARE_MSM_GPIO_PINS(15);
273DECLARE_MSM_GPIO_PINS(16);
274DECLARE_MSM_GPIO_PINS(17);
275DECLARE_MSM_GPIO_PINS(18);
276DECLARE_MSM_GPIO_PINS(19);
277DECLARE_MSM_GPIO_PINS(20);
278DECLARE_MSM_GPIO_PINS(21);
279DECLARE_MSM_GPIO_PINS(22);
280DECLARE_MSM_GPIO_PINS(23);
281DECLARE_MSM_GPIO_PINS(24);
282DECLARE_MSM_GPIO_PINS(25);
283DECLARE_MSM_GPIO_PINS(26);
284DECLARE_MSM_GPIO_PINS(27);
285DECLARE_MSM_GPIO_PINS(28);
286DECLARE_MSM_GPIO_PINS(29);
287DECLARE_MSM_GPIO_PINS(30);
288DECLARE_MSM_GPIO_PINS(31);
289DECLARE_MSM_GPIO_PINS(32);
290DECLARE_MSM_GPIO_PINS(33);
291DECLARE_MSM_GPIO_PINS(34);
292DECLARE_MSM_GPIO_PINS(35);
293DECLARE_MSM_GPIO_PINS(36);
294DECLARE_MSM_GPIO_PINS(37);
295DECLARE_MSM_GPIO_PINS(38);
296DECLARE_MSM_GPIO_PINS(39);
297DECLARE_MSM_GPIO_PINS(40);
298DECLARE_MSM_GPIO_PINS(41);
299DECLARE_MSM_GPIO_PINS(42);
300DECLARE_MSM_GPIO_PINS(43);
301DECLARE_MSM_GPIO_PINS(44);
302DECLARE_MSM_GPIO_PINS(45);
303DECLARE_MSM_GPIO_PINS(46);
304DECLARE_MSM_GPIO_PINS(47);
305DECLARE_MSM_GPIO_PINS(48);
306DECLARE_MSM_GPIO_PINS(49);
307DECLARE_MSM_GPIO_PINS(50);
308DECLARE_MSM_GPIO_PINS(51);
309DECLARE_MSM_GPIO_PINS(52);
310DECLARE_MSM_GPIO_PINS(53);
311DECLARE_MSM_GPIO_PINS(54);
312DECLARE_MSM_GPIO_PINS(55);
313DECLARE_MSM_GPIO_PINS(56);
314DECLARE_MSM_GPIO_PINS(57);
315DECLARE_MSM_GPIO_PINS(58);
316DECLARE_MSM_GPIO_PINS(59);
317DECLARE_MSM_GPIO_PINS(60);
318DECLARE_MSM_GPIO_PINS(61);
319DECLARE_MSM_GPIO_PINS(62);
320DECLARE_MSM_GPIO_PINS(63);
321DECLARE_MSM_GPIO_PINS(64);
322DECLARE_MSM_GPIO_PINS(65);
323DECLARE_MSM_GPIO_PINS(66);
324DECLARE_MSM_GPIO_PINS(67);
325DECLARE_MSM_GPIO_PINS(68);
326DECLARE_MSM_GPIO_PINS(69);
327DECLARE_MSM_GPIO_PINS(70);
328DECLARE_MSM_GPIO_PINS(71);
329DECLARE_MSM_GPIO_PINS(72);
330DECLARE_MSM_GPIO_PINS(73);
331DECLARE_MSM_GPIO_PINS(74);
332DECLARE_MSM_GPIO_PINS(75);
333DECLARE_MSM_GPIO_PINS(76);
334DECLARE_MSM_GPIO_PINS(77);
335DECLARE_MSM_GPIO_PINS(78);
336DECLARE_MSM_GPIO_PINS(79);
337DECLARE_MSM_GPIO_PINS(80);
338DECLARE_MSM_GPIO_PINS(81);
339DECLARE_MSM_GPIO_PINS(82);
340DECLARE_MSM_GPIO_PINS(83);
341DECLARE_MSM_GPIO_PINS(84);
342DECLARE_MSM_GPIO_PINS(85);
343DECLARE_MSM_GPIO_PINS(86);
344DECLARE_MSM_GPIO_PINS(87);
345DECLARE_MSM_GPIO_PINS(88);
346DECLARE_MSM_GPIO_PINS(89);
347DECLARE_MSM_GPIO_PINS(90);
348DECLARE_MSM_GPIO_PINS(91);
349DECLARE_MSM_GPIO_PINS(92);
350DECLARE_MSM_GPIO_PINS(93);
351DECLARE_MSM_GPIO_PINS(94);
352DECLARE_MSM_GPIO_PINS(95);
353DECLARE_MSM_GPIO_PINS(96);
354DECLARE_MSM_GPIO_PINS(97);
355DECLARE_MSM_GPIO_PINS(98);
356DECLARE_MSM_GPIO_PINS(99);
357DECLARE_MSM_GPIO_PINS(100);
358DECLARE_MSM_GPIO_PINS(101);
359DECLARE_MSM_GPIO_PINS(102);
360DECLARE_MSM_GPIO_PINS(103);
361DECLARE_MSM_GPIO_PINS(104);
362DECLARE_MSM_GPIO_PINS(105);
363DECLARE_MSM_GPIO_PINS(106);
364DECLARE_MSM_GPIO_PINS(107);
365DECLARE_MSM_GPIO_PINS(108);
366DECLARE_MSM_GPIO_PINS(109);
367DECLARE_MSM_GPIO_PINS(110);
368DECLARE_MSM_GPIO_PINS(111);
369DECLARE_MSM_GPIO_PINS(112);
370DECLARE_MSM_GPIO_PINS(113);
371DECLARE_MSM_GPIO_PINS(114);
372DECLARE_MSM_GPIO_PINS(115);
373DECLARE_MSM_GPIO_PINS(116);
374DECLARE_MSM_GPIO_PINS(117);
375DECLARE_MSM_GPIO_PINS(118);
376DECLARE_MSM_GPIO_PINS(119);
377DECLARE_MSM_GPIO_PINS(120);
378DECLARE_MSM_GPIO_PINS(121);
379DECLARE_MSM_GPIO_PINS(122);
380DECLARE_MSM_GPIO_PINS(123);
381DECLARE_MSM_GPIO_PINS(124);
382DECLARE_MSM_GPIO_PINS(125);
383DECLARE_MSM_GPIO_PINS(126);
384DECLARE_MSM_GPIO_PINS(127);
385DECLARE_MSM_GPIO_PINS(128);
386DECLARE_MSM_GPIO_PINS(129);
387DECLARE_MSM_GPIO_PINS(130);
388DECLARE_MSM_GPIO_PINS(131);
389DECLARE_MSM_GPIO_PINS(132);
390DECLARE_MSM_GPIO_PINS(133);
391DECLARE_MSM_GPIO_PINS(134);
392DECLARE_MSM_GPIO_PINS(135);
393DECLARE_MSM_GPIO_PINS(136);
394DECLARE_MSM_GPIO_PINS(137);
395DECLARE_MSM_GPIO_PINS(138);
396DECLARE_MSM_GPIO_PINS(139);
397DECLARE_MSM_GPIO_PINS(140);
398DECLARE_MSM_GPIO_PINS(141);
399DECLARE_MSM_GPIO_PINS(142);
400DECLARE_MSM_GPIO_PINS(143);
401DECLARE_MSM_GPIO_PINS(144);
402DECLARE_MSM_GPIO_PINS(145);
403DECLARE_MSM_GPIO_PINS(146);
404DECLARE_MSM_GPIO_PINS(147);
405DECLARE_MSM_GPIO_PINS(148);
406DECLARE_MSM_GPIO_PINS(149);
407DECLARE_MSM_GPIO_PINS(150);
408DECLARE_MSM_GPIO_PINS(151);
409DECLARE_MSM_GPIO_PINS(152);
410DECLARE_MSM_GPIO_PINS(153);
411DECLARE_MSM_GPIO_PINS(154);
412DECLARE_MSM_GPIO_PINS(155);
413DECLARE_MSM_GPIO_PINS(156);
414DECLARE_MSM_GPIO_PINS(157);
415DECLARE_MSM_GPIO_PINS(158);
416DECLARE_MSM_GPIO_PINS(159);
417DECLARE_MSM_GPIO_PINS(160);
418DECLARE_MSM_GPIO_PINS(161);
419DECLARE_MSM_GPIO_PINS(162);
420DECLARE_MSM_GPIO_PINS(163);
421DECLARE_MSM_GPIO_PINS(164);
422DECLARE_MSM_GPIO_PINS(165);
423
424static const unsigned int sdc1_rclk_pins[] = { 166 };
425static const unsigned int sdc1_clk_pins[] = { 167 };
426static const unsigned int sdc1_cmd_pins[] = { 168 };
427static const unsigned int sdc1_data_pins[] = { 169 };
428static const unsigned int sdc2_clk_pins[] = { 170 };
429static const unsigned int sdc2_cmd_pins[] = { 171 };
430static const unsigned int sdc2_data_pins[] = { 172 };
431
432enum shikra_functions {
433 msm_mux_gpio,
434 msm_mux_agera_pll,
435 msm_mux_atest_bbrx,
436 msm_mux_atest_char,
437 msm_mux_atest_gpsadc,
438 msm_mux_atest_tsens,
439 msm_mux_atest_usb,
440 msm_mux_cam_mclk,
441 msm_mux_cci_async,
442 msm_mux_cci_i2c0,
443 msm_mux_cci_i2c1,
444 msm_mux_cci_timer,
445 msm_mux_char_exec,
446 msm_mux_cri_trng,
447 msm_mux_dac_calib,
448 msm_mux_dbg_out_clk,
449 msm_mux_ddr_bist,
450 msm_mux_ddr_pxi,
451 msm_mux_dmic,
452 msm_mux_emac_dll,
453 msm_mux_emac_mcg,
454 msm_mux_emac_phy,
455 msm_mux_emac0_ptp_aux,
456 msm_mux_emac0_ptp_pps,
457 msm_mux_emac1_ptp_aux,
458 msm_mux_emac1_ptp_pps,
459 msm_mux_ext_mclk,
460 msm_mux_gcc_gp,
461 msm_mux_gsm0_tx,
462 msm_mux_i2s0,
463 msm_mux_i2s1,
464 msm_mux_i2s2,
465 msm_mux_i2s3,
466 msm_mux_jitter_bist,
467 msm_mux_m_voc,
468 msm_mux_mdp_vsync_e,
469 msm_mux_mdp_vsync_out0,
470 msm_mux_mdp_vsync_out1,
471 msm_mux_mdp_vsync_p,
472 msm_mux_mdp_vsync_s,
473 msm_mux_mpm_pwr,
474 msm_mux_mss_lte,
475 msm_mux_nav_gpio,
476 msm_mux_pa_indicator_or,
477 msm_mux_pbs_in,
478 msm_mux_pbs_out,
479 msm_mux_pcie0_clk_req_n,
480 msm_mux_phase_flag,
481 msm_mux_pll,
482 msm_mux_prng_rosc,
483 msm_mux_pwm,
484 msm_mux_qdss_cti,
485 msm_mux_qup0_se0,
486 msm_mux_qup0_se1,
487 msm_mux_qup0_se1_01,
488 msm_mux_qup0_se1_23,
489 msm_mux_qup0_se2,
490 msm_mux_qup0_se3_01,
491 msm_mux_qup0_se3_23,
492 msm_mux_qup0_se4_01,
493 msm_mux_qup0_se4_23,
494 msm_mux_qup0_se5,
495 msm_mux_qup0_se6,
496 msm_mux_qup0_se7_01,
497 msm_mux_qup0_se7_23,
498 msm_mux_qup0_se8,
499 msm_mux_qup0_se9,
500 msm_mux_qup0_se9_01,
501 msm_mux_qup0_se9_23,
502 msm_mux_rgmii,
503 msm_mux_sd_write_protect,
504 msm_mux_sdc_cdc,
505 msm_mux_sdc_tb_trig,
506 msm_mux_ssbi_wtr,
507 msm_mux_swr0_rx,
508 msm_mux_swr0_tx,
509 msm_mux_tgu_ch_trigout,
510 msm_mux_tsc_async,
511 msm_mux_tsense_pwm,
512 msm_mux_uim1,
513 msm_mux_uim2,
514 msm_mux_unused_adsp,
515 msm_mux_unused_gsm1,
516 msm_mux_usb0_phy_ps,
517 msm_mux_vfr,
518 msm_mux_vsense_trigger_mirnat,
519 msm_mux_wlan,
520 msm_mux__,
521};
522
523static const char *const gpio_groups[] = {
524 "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5",
525 "gpio6", "gpio7", "gpio8", "gpio9", "gpio10", "gpio11",
526 "gpio12", "gpio13", "gpio14", "gpio15", "gpio16", "gpio17",
527 "gpio18", "gpio19", "gpio20", "gpio21", "gpio22", "gpio23",
528 "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29",
529 "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
530 "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41",
531 "gpio42", "gpio43", "gpio44", "gpio45", "gpio46", "gpio47",
532 "gpio48", "gpio49", "gpio50", "gpio51", "gpio52", "gpio53",
533 "gpio54", "gpio55", "gpio56", "gpio57", "gpio58", "gpio59",
534 "gpio60", "gpio61", "gpio62", "gpio63", "gpio64", "gpio65",
535 "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", "gpio71",
536 "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77",
537 "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83",
538 "gpio84", "gpio85", "gpio86", "gpio87", "gpio88", "gpio89",
539 "gpio90", "gpio91", "gpio92", "gpio93", "gpio94", "gpio95",
540 "gpio96", "gpio97", "gpio98", "gpio99", "gpio100", "gpio101",
541 "gpio102", "gpio103", "gpio104", "gpio105", "gpio106", "gpio107",
542 "gpio108", "gpio109", "gpio110", "gpio111", "gpio112", "gpio113",
543 "gpio114", "gpio115", "gpio116", "gpio117", "gpio118", "gpio119",
544 "gpio120", "gpio121", "gpio122", "gpio123", "gpio124", "gpio125",
545 "gpio126", "gpio127", "gpio128", "gpio129", "gpio130", "gpio131",
546 "gpio132", "gpio133", "gpio134", "gpio135", "gpio136", "gpio137",
547 "gpio138", "gpio139", "gpio140", "gpio141", "gpio142", "gpio143",
548 "gpio144", "gpio145", "gpio146", "gpio147", "gpio148", "gpio149",
549 "gpio150", "gpio151", "gpio152", "gpio153", "gpio154", "gpio155",
550 "gpio156", "gpio157", "gpio158", "gpio159", "gpio160", "gpio161",
551 "gpio162", "gpio163", "gpio164", "gpio165",
552};
553
554static const char *const agera_pll_groups[] = {
555 "gpio22", "gpio23",
556};
557
558static const char *const atest_bbrx_groups[] = {
559 "gpio58", "gpio59",
560};
561
562static const char *const atest_char_groups[] = {
563 "gpio56", "gpio57", "gpio54", "gpio55", "gpio62",
564};
565
566static const char *const atest_gpsadc_groups[] = {
567 "gpio60", "gpio96",
568};
569
570static const char *const atest_tsens_groups[] = {
571 "gpio1", "gpio2",
572};
573
574static const char *const atest_usb_groups[] = {
575 "gpio53", "gpio58", "gpio59", "gpio60", "gpio61", "gpio96",
576 "gpio98", "gpio99", "gpio100", "gpio101",
577};
578
579static const char *const cam_mclk_groups[] = {
580 "gpio34", "gpio35", "gpio96", "gpio98",
581};
582
583static const char *const cci_async_groups[] = {
584 "gpio39",
585};
586
587static const char *const cci_i2c0_groups[] = {
588 "gpio36", "gpio37",
589};
590
591static const char *const cci_i2c1_groups[] = {
592 "gpio41", "gpio42",
593};
594
595static const char *const cci_timer_groups[] = {
596 "gpio38", "gpio40", "gpio43", "gpio47",
597};
598
599static const char *const char_exec_groups[] = {
600 "gpio12", "gpio13",
601};
602
603static const char *const cri_trng_groups[] = {
604 "gpio6", "gpio7", "gpio20",
605};
606
607static const char *const dac_calib_groups[] = {
608 "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", "gpio8",
609 "gpio9", "gpio14", "gpio15", "gpio16", "gpio17", "gpio18",
610 "gpio19", "gpio63", "gpio64", "gpio66", "gpio68", "gpio69",
611 "gpio70", "gpio88", "gpio89", "gpio90", "gpio97", "gpio116",
612 "gpio117", "gpio118",
613};
614
615static const char *const dbg_out_clk_groups[] = {
616 "gpio61",
617};
618
619static const char *const ddr_bist_groups[] = {
620 "gpio1", "gpio2", "gpio3", "gpio4",
621};
622
623static const char *const ddr_pxi_groups[] = {
624 "gpio98", "gpio99", "gpio100", "gpio101",
625};
626
627static const char *const dmic_groups[] = {
628 "gpio96", "gpio97", "gpio98", "gpio99",
629};
630
631static const char *const emac_dll_groups[] = {
632 "gpio58", "gpio59", "gpio60", "gpio61",
633};
634
635static const char *const emac_mcg_groups[] = {
636 "gpio28", "gpio29", "gpio40", "gpio43", "gpio44", "gpio45",
637 "gpio46", "gpio47",
638};
639
640static const char *const emac_phy_groups[] = {
641 "gpio120", "gpio136",
642};
643
644static const char *const emac0_ptp_aux_groups[] = {
645 "gpio60", "gpio63", "gpio69", "gpio85",
646};
647
648static const char *const emac0_ptp_pps_groups[] = {
649 "gpio60", "gpio63", "gpio69", "gpio85",
650};
651
652static const char *const emac1_ptp_aux_groups[] = {
653 "gpio31", "gpio33", "gpio60", "gpio68",
654};
655
656static const char *const emac1_ptp_pps_groups[] = {
657 "gpio31", "gpio33", "gpio60", "gpio68",
658};
659
660static const char *const ext_mclk_groups[] = {
661 "gpio103", "gpio104", "gpio110", "gpio114",
662};
663
664static const char *const gcc_gp_groups[] = {
665 "gpio45", "gpio53", "gpio61", "gpio88", "gpio89", "gpio110",
666};
667
668static const char *const gsm0_tx_groups[] = {
669 "gpio75",
670};
671
672static const char *const i2s0_groups[] = {
673 "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110",
674};
675
676static const char *const i2s1_groups[] = {
677 "gpio96", "gpio97", "gpio98", "gpio99",
678};
679
680static const char *const i2s2_groups[] = {
681 "gpio100", "gpio101", "gpio102", "gpio103",
682};
683
684static const char *const i2s3_groups[] = {
685 "gpio111", "gpio112", "gpio113", "gpio114",
686};
687
688static const char *const jitter_bist_groups[] = {
689 "gpio96", "gpio99",
690};
691
692static const char *const m_voc_groups[] = {
693 "gpio0",
694};
695
696static const char *const mdp_vsync_e_groups[] = {
697 "gpio94",
698};
699
700static const char *const mdp_vsync_out0_groups[] = {
701 "gpio86",
702};
703
704static const char *const mdp_vsync_out1_groups[] = {
705 "gpio86",
706};
707
708static const char *const mdp_vsync_p_groups[] = {
709 "gpio86",
710};
711
712static const char *const mdp_vsync_s_groups[] = {
713 "gpio95",
714};
715
716static const char *const mpm_pwr_groups[] = {
717 "gpio1",
718};
719
720static const char *const mss_lte_groups[] = {
721 "gpio115", "gpio116",
722};
723
724static const char *const nav_gpio_groups[] = {
725 "gpio53", "gpio58", "gpio63", "gpio71", "gpio91", "gpio92",
726 "gpio95", "gpio100", "gpio101", "gpio104",
727};
728
729static const char *const pa_indicator_or_groups[] = {
730 "gpio61",
731};
732
733static const char *const pbs_in_groups[] = {
734 "gpio48", "gpio49", "gpio50", "gpio51", "gpio53", "gpio54",
735 "gpio55", "gpio56", "gpio57", "gpio58", "gpio59", "gpio60",
736 "gpio61", "gpio62", "gpio63", "gpio74",
737};
738
739static const char *const pbs_out_groups[] = {
740 "gpio22", "gpio23", "gpio24",
741};
742
743static const char *const pcie0_clk_req_n_groups[] = {
744 "gpio117",
745};
746
747static const char *const phase_flag_groups[] = {
748 "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5",
749 "gpio6", "gpio7", "gpio8", "gpio9", "gpio11", "gpio16",
750 "gpio17", "gpio28", "gpio29", "gpio30", "gpio31", "gpio48",
751 "gpio49", "gpio50", "gpio54", "gpio55", "gpio56", "gpio57",
752 "gpio62", "gpio63", "gpio64", "gpio69", "gpio70", "gpio71",
753 "gpio72", "gpio74", "gpio102",
754};
755
756static const char *const pll_groups[] = {
757 "gpio14", "gpio22", "gpio43", "gpio44", "gpio74", "gpio76",
758};
759
760static const char *const prng_rosc_groups[] = {
761 "gpio27", "gpio28",
762};
763
764static const char *const pwm_groups[] = {
765 "gpio32", "gpio40", "gpio45", "gpio53", "gpio54", "gpio55",
766 "gpio56", "gpio57", "gpio58", "gpio61", "gpio62", "gpio68",
767 "gpio77", "gpio79", "gpio80", "gpio87", "gpio102"
768};
769
770static const char *const qdss_cti_groups[] = {
771 "gpio28", "gpio29", "gpio30", "gpio31", "gpio94", "gpio95",
772};
773
774static const char *const qup0_se0_groups[] = {
775 "gpio0", "gpio1", "gpio2", "gpio3",
776};
777
778static const char *const qup0_se1_groups[] = {
779 "gpio28", "gpio29",
780};
781
782static const char *const qup0_se1_01_groups[] = {
783 "gpio4", "gpio5",
784};
785
786static const char *const qup0_se1_23_groups[] = {
787 "gpio4", "gpio5",
788};
789
790static const char *const qup0_se2_groups[] = {
791 "gpio6", "gpio7", "gpio8", "gpio9", "gpio30", "gpio31",
792};
793
794static const char *const qup0_se3_01_groups[] = {
795 "gpio10", "gpio11",
796};
797
798static const char *const qup0_se3_23_groups[] = {
799 "gpio10", "gpio11",
800};
801
802static const char *const qup0_se4_01_groups[] = {
803 "gpio12", "gpio13",
804};
805
806static const char *const qup0_se4_23_groups[] = {
807 "gpio12", "gpio13",
808};
809
810static const char *const qup0_se5_groups[] = {
811 "gpio14", "gpio15", "gpio16", "gpio17",
812};
813
814static const char *const qup0_se6_groups[] = {
815 "gpio18", "gpio19", "gpio28", "gpio29", "gpio30", "gpio31",
816};
817
818static const char *const qup0_se7_01_groups[] = {
819 "gpio20", "gpio21",
820};
821
822static const char *const qup0_se7_23_groups[] = {
823 "gpio20", "gpio21",
824};
825
826static const char *const qup0_se8_groups[] = {
827 "gpio22", "gpio23", "gpio24", "gpio25",
828};
829
830static const char *const qup0_se9_groups[] = {
831 "gpio48", "gpio49", "gpio50", "gpio51",
832};
833
834static const char *const qup0_se9_01_groups[] = {
835 "gpio26", "gpio27",
836};
837
838static const char *const qup0_se9_23_groups[] = {
839 "gpio26", "gpio27",
840};
841
842static const char *const rgmii_groups[] = {
843 "gpio121", "gpio122", "gpio123", "gpio124", "gpio125", "gpio126",
844 "gpio127", "gpio128", "gpio129", "gpio130", "gpio131", "gpio132",
845 "gpio133", "gpio134", "gpio137", "gpio138", "gpio139", "gpio140",
846 "gpio141", "gpio142", "gpio143", "gpio144", "gpio145", "gpio146",
847 "gpio147", "gpio148", "gpio149", "gpio150",
848};
849
850static const char *const sd_write_protect_groups[] = {
851 "gpio109",
852};
853
854static const char *const sdc_cdc_groups[] = {
855 "gpio98", "gpio99", "gpio100", "gpio101",
856};
857
858static const char *const sdc_tb_trig_groups[] = {
859 "gpio32", "gpio33",
860};
861
862static const char *const ssbi_wtr_groups[] = {
863 "gpio68", "gpio69", "gpio70", "gpio71",
864};
865
866static const char *const swr0_rx_groups[] = {
867 "gpio107", "gpio108", "gpio109",
868};
869
870static const char *const swr0_tx_groups[] = {
871 "gpio105", "gpio106",
872};
873
874static const char *const tgu_ch_trigout_groups[] = {
875 "gpio14", "gpio15", "gpio16", "gpio17",
876};
877
878static const char *const tsc_async_groups[] = {
879 "gpio45", "gpio46",
880};
881
882static const char *const tsense_pwm_groups[] = {
883 "gpio21",
884};
885
886static const char *const uim1_groups[] = {
887 "gpio81", "gpio82", "gpio83", "gpio84",
888};
889
890static const char *const uim2_groups[] = {
891 "gpio77", "gpio78", "gpio79", "gpio80",
892};
893
894static const char *const unused_adsp_groups[] = {
895 "gpio35",
896};
897
898static const char *const unused_gsm1_groups[] = {
899 "gpio64",
900};
901
902static const char *const usb0_phy_ps_groups[] = {
903 "gpio90",
904};
905
906static const char *const vfr_groups[] = {
907 "gpio59",
908};
909
910static const char *const vsense_trigger_mirnat_groups[] = {
911 "gpio58",
912};
913
914static const char *const wlan_groups[] = {
915 "gpio14", "gpio15",
916};
917
918static const struct pinfunction shikra_functions[] = {
919 MSM_GPIO_PIN_FUNCTION(gpio),
920 MSM_PIN_FUNCTION(agera_pll),
921 MSM_PIN_FUNCTION(atest_bbrx),
922 MSM_PIN_FUNCTION(atest_char),
923 MSM_PIN_FUNCTION(atest_gpsadc),
924 MSM_PIN_FUNCTION(atest_tsens),
925 MSM_PIN_FUNCTION(atest_usb),
926 MSM_PIN_FUNCTION(cam_mclk),
927 MSM_PIN_FUNCTION(cci_async),
928 MSM_PIN_FUNCTION(cci_i2c0),
929 MSM_PIN_FUNCTION(cci_i2c1),
930 MSM_PIN_FUNCTION(cci_timer),
931 MSM_PIN_FUNCTION(char_exec),
932 MSM_PIN_FUNCTION(cri_trng),
933 MSM_PIN_FUNCTION(dac_calib),
934 MSM_PIN_FUNCTION(dbg_out_clk),
935 MSM_PIN_FUNCTION(ddr_bist),
936 MSM_PIN_FUNCTION(ddr_pxi),
937 MSM_PIN_FUNCTION(dmic),
938 MSM_PIN_FUNCTION(emac_dll),
939 MSM_PIN_FUNCTION(emac_mcg),
940 MSM_PIN_FUNCTION(emac_phy),
941 MSM_PIN_FUNCTION(emac0_ptp_aux),
942 MSM_PIN_FUNCTION(emac0_ptp_pps),
943 MSM_PIN_FUNCTION(emac1_ptp_aux),
944 MSM_PIN_FUNCTION(emac1_ptp_pps),
945 MSM_PIN_FUNCTION(ext_mclk),
946 MSM_PIN_FUNCTION(gcc_gp),
947 MSM_PIN_FUNCTION(gsm0_tx),
948 MSM_PIN_FUNCTION(i2s0),
949 MSM_PIN_FUNCTION(i2s1),
950 MSM_PIN_FUNCTION(i2s2),
951 MSM_PIN_FUNCTION(i2s3),
952 MSM_PIN_FUNCTION(jitter_bist),
953 MSM_PIN_FUNCTION(m_voc),
954 MSM_PIN_FUNCTION(mdp_vsync_e),
955 MSM_PIN_FUNCTION(mdp_vsync_out0),
956 MSM_PIN_FUNCTION(mdp_vsync_out1),
957 MSM_PIN_FUNCTION(mdp_vsync_p),
958 MSM_PIN_FUNCTION(mdp_vsync_s),
959 MSM_PIN_FUNCTION(mpm_pwr),
960 MSM_PIN_FUNCTION(mss_lte),
961 MSM_PIN_FUNCTION(nav_gpio),
962 MSM_PIN_FUNCTION(pa_indicator_or),
963 MSM_PIN_FUNCTION(pbs_in),
964 MSM_PIN_FUNCTION(pbs_out),
965 MSM_PIN_FUNCTION(pcie0_clk_req_n),
966 MSM_PIN_FUNCTION(phase_flag),
967 MSM_PIN_FUNCTION(pll),
968 MSM_PIN_FUNCTION(prng_rosc),
969 MSM_PIN_FUNCTION(pwm),
970 MSM_PIN_FUNCTION(qdss_cti),
971 MSM_PIN_FUNCTION(qup0_se0),
972 MSM_PIN_FUNCTION(qup0_se1),
973 MSM_PIN_FUNCTION(qup0_se1_01),
974 MSM_PIN_FUNCTION(qup0_se1_23),
975 MSM_PIN_FUNCTION(qup0_se2),
976 MSM_PIN_FUNCTION(qup0_se3_01),
977 MSM_PIN_FUNCTION(qup0_se3_23),
978 MSM_PIN_FUNCTION(qup0_se4_01),
979 MSM_PIN_FUNCTION(qup0_se4_23),
980 MSM_PIN_FUNCTION(qup0_se5),
981 MSM_PIN_FUNCTION(qup0_se6),
982 MSM_PIN_FUNCTION(qup0_se7_01),
983 MSM_PIN_FUNCTION(qup0_se7_23),
984 MSM_PIN_FUNCTION(qup0_se8),
985 MSM_PIN_FUNCTION(qup0_se9),
986 MSM_PIN_FUNCTION(qup0_se9_01),
987 MSM_PIN_FUNCTION(qup0_se9_23),
988 MSM_PIN_FUNCTION(rgmii),
989 MSM_PIN_FUNCTION(sd_write_protect),
990 MSM_PIN_FUNCTION(sdc_cdc),
991 MSM_PIN_FUNCTION(sdc_tb_trig),
992 MSM_PIN_FUNCTION(ssbi_wtr),
993 MSM_PIN_FUNCTION(swr0_rx),
994 MSM_PIN_FUNCTION(swr0_tx),
995 MSM_PIN_FUNCTION(tgu_ch_trigout),
996 MSM_PIN_FUNCTION(tsc_async),
997 MSM_PIN_FUNCTION(tsense_pwm),
998 MSM_PIN_FUNCTION(uim1),
999 MSM_PIN_FUNCTION(uim2),
1000 MSM_PIN_FUNCTION(unused_adsp),
1001 MSM_PIN_FUNCTION(unused_gsm1),
1002 MSM_PIN_FUNCTION(usb0_phy_ps),
1003 MSM_PIN_FUNCTION(vfr),
1004 MSM_PIN_FUNCTION(vsense_trigger_mirnat),
1005 MSM_PIN_FUNCTION(wlan),
1006};
1007
1008static const struct msm_pingroup shikra_groups[] = {
1009 [0] = PINGROUP(0, qup0_se0, m_voc, _, phase_flag, _, _, _, _, _, _, _),
1010 [1] = PINGROUP(1, qup0_se0, mpm_pwr, ddr_bist, _, phase_flag, atest_tsens, _, _, _, _, _),
1011 [2] = PINGROUP(2, qup0_se0, ddr_bist, _, phase_flag, atest_tsens, _, _, _, _, _, _),
1012 [3] = PINGROUP(3, qup0_se0, ddr_bist, _, phase_flag, dac_calib, _, _, _, _, _, _),
1013 [4] = PINGROUP(4, qup0_se1_23, qup0_se1_01, ddr_bist, _, phase_flag, dac_calib, _, _, _,
1014 _, _),
1015 [5] = PINGROUP(5, qup0_se1_23, qup0_se1_01, _, phase_flag, dac_calib, _, _, _, _, _, _),
1016 [6] = PINGROUP(6, qup0_se2, cri_trng, _, phase_flag, dac_calib, _, _, _, _, _, _),
1017 [7] = PINGROUP(7, qup0_se2, cri_trng, _, phase_flag, dac_calib, _, _, _, _, _, _),
1018 [8] = PINGROUP(8, qup0_se2, _, phase_flag, dac_calib, _, _, _, _, _, _, _),
1019 [9] = PINGROUP(9, qup0_se2, _, phase_flag, dac_calib, _, _, _, _, _, _, _),
1020 [10] = PINGROUP(10, qup0_se3_01, qup0_se3_23, _, _, _, _, _, _, _, _, _),
1021 [11] = PINGROUP(11, qup0_se3_01, qup0_se3_23, _, phase_flag, _, _, _, _, _, _, _),
1022 [12] = PINGROUP(12, qup0_se4_01, qup0_se4_23, char_exec, _, _, _, _, _, _, _, _),
1023 [13] = PINGROUP(13, qup0_se4_01, qup0_se4_23, char_exec, _, _, _, _, _, _, _, _),
1024 [14] = PINGROUP(14, qup0_se5, pll, tgu_ch_trigout, dac_calib, wlan, _, _, _, _, _, _),
1025 [15] = PINGROUP(15, qup0_se5, tgu_ch_trigout, _, dac_calib, wlan, _, _, _, _, _, _),
1026 [16] = PINGROUP(16, qup0_se5, tgu_ch_trigout, _, phase_flag, dac_calib, _, _, _, _, _, _),
1027 [17] = PINGROUP(17, qup0_se5, tgu_ch_trigout, _, phase_flag, dac_calib, _, _, _, _, _, _),
1028 [18] = PINGROUP(18, qup0_se6, dac_calib, _, _, _, _, _, _, _, _, _),
1029 [19] = PINGROUP(19, qup0_se6, dac_calib, _, _, _, _, _, _, _, _, _),
1030 [20] = PINGROUP(20, qup0_se7_01, qup0_se7_23, cri_trng, _, _, _, _, _, _, _, _),
1031 [21] = PINGROUP(21, qup0_se7_01, qup0_se7_23, tsense_pwm, _, _, _, _, _, _, _, _),
1032 [22] = PINGROUP(22, qup0_se8, pll, agera_pll, pbs_out, _, _, _, _, _, _, _),
1033 [23] = PINGROUP(23, qup0_se8, agera_pll, pbs_out, _, _, _, _, _, _, _, _),
1034 [24] = PINGROUP(24, qup0_se8, pbs_out, _, _, _, _, _, _, _, _, _),
1035 [25] = PINGROUP(25, qup0_se8, _, _, _, _, _, _, _, _, _, _),
1036 [26] = PINGROUP(26, qup0_se9_23, qup0_se9_01, _, _, _, _, _, _, _, _, _),
1037 [27] = PINGROUP(27, qup0_se9_23, qup0_se9_01, prng_rosc, _, _, _, _, _, _, _, _),
1038 [28] = PINGROUP(28, qup0_se1, qup0_se6, emac_mcg, prng_rosc, _, phase_flag, qdss_cti,
1039 _, _, _, _),
1040 [29] = PINGROUP(29, qup0_se1, qup0_se6, emac_mcg, _, phase_flag, qdss_cti, _, _, _, _, _),
1041 [30] = PINGROUP(30, qup0_se2, qup0_se6, _, phase_flag, qdss_cti, _, _, _, _, _, _),
1042 [31] = PINGROUP(31, qup0_se2, qup0_se6, emac1_ptp_aux, emac1_ptp_pps, _, phase_flag,
1043 qdss_cti, _, _, _, _),
1044 [32] = PINGROUP(32, pwm, sdc_tb_trig, _, _, _, _, _, _, _, _, _),
1045 [33] = PINGROUP(33, emac1_ptp_aux, emac1_ptp_pps, sdc_tb_trig, _, _, _, _, _, _, _, _),
1046 [34] = PINGROUP(34, cam_mclk, _, _, _, _, _, _, _, _, _, _),
1047 [35] = PINGROUP(35, cam_mclk, unused_adsp, _, _, _, _, _, _, _, _, _),
1048 [36] = PINGROUP(36, cci_i2c0, _, _, _, _, _, _, _, _, _, _),
1049 [37] = PINGROUP(37, cci_i2c0, _, _, _, _, _, _, _, _, _, _),
1050 [38] = PINGROUP(38, cci_timer, _, _, _, _, _, _, _, _, _, _),
1051 [39] = PINGROUP(39, cci_async, _, _, _, _, _, _, _, _, _, _),
1052 [40] = PINGROUP(40, cci_timer, emac_mcg, pwm, _, _, _, _, _, _, _, _),
1053 [41] = PINGROUP(41, cci_i2c1, _, _, _, _, _, _, _, _, _, _),
1054 [42] = PINGROUP(42, cci_i2c1, _, _, _, _, _, _, _, _, _, _),
1055 [43] = PINGROUP(43, cci_timer, emac_mcg, pll, _, _, _, _, _, _, _, _),
1056 [44] = PINGROUP(44, emac_mcg, pll, _, _, _, _, _, _, _, _, _),
1057 [45] = PINGROUP(45, tsc_async, emac_mcg, pwm, gcc_gp, _, _, _, _, _, _, _),
1058 [46] = PINGROUP(46, tsc_async, emac_mcg, _, _, _, _, _, _, _, _, _),
1059 [47] = PINGROUP(47, cci_timer, emac_mcg, _, _, _, _, _, _, _, _, _),
1060 [48] = PINGROUP(48, _, qup0_se9, _, _, pbs_in, phase_flag, _, _, _, _, _),
1061 [49] = PINGROUP(49, _, qup0_se9, _, _, pbs_in, phase_flag, _, _, _, _, _),
1062 [50] = PINGROUP(50, _, qup0_se9, _, _, pbs_in, phase_flag, _, _, _, _, _),
1063 [51] = PINGROUP(51, _, qup0_se9, pbs_in, _, _, _, _, _, _, _, _),
1064 [52] = PINGROUP(52, _, _, _, _, _, _, _, _, _, _, _),
1065 [53] = PINGROUP(53, _, nav_gpio, gcc_gp, pwm, _, pbs_in, atest_usb, _, _, _, _),
1066 [54] = PINGROUP(54, _, pwm, _, pbs_in, phase_flag, atest_char, _, _, _, _, _),
1067 [55] = PINGROUP(55, _, pwm, _, pbs_in, phase_flag, atest_char, _, _, _, _, _),
1068 [56] = PINGROUP(56, _, pwm, _, pbs_in, phase_flag, atest_char, _, _, _, _, _),
1069 [57] = PINGROUP(57, _, pwm, _, pbs_in, phase_flag, atest_char, _, _, _, _, _),
1070 [58] = PINGROUP(58, _, nav_gpio, pwm, _, pbs_in, atest_bbrx, atest_usb,
1071 vsense_trigger_mirnat, emac_dll, _, _),
1072 [59] = PINGROUP(59, _, vfr, _, pbs_in, atest_bbrx, atest_usb, emac_dll, _, _, _, _),
1073 [60] = PINGROUP(60, _, emac1_ptp_aux, emac1_ptp_pps, emac0_ptp_aux, emac0_ptp_pps, _,
1074 pbs_in, atest_gpsadc, atest_usb, emac_dll, _),
1075 [61] = PINGROUP(61, _, pwm, gcc_gp, pa_indicator_or, dbg_out_clk, pbs_in, atest_usb,
1076 emac_dll, _, _, _),
1077 [62] = PINGROUP(62, _, pwm, _, pbs_in, phase_flag, atest_char, _, _, _, _, _),
1078 [63] = PINGROUP(63, _, nav_gpio, emac0_ptp_aux, emac0_ptp_pps, _, pbs_in, phase_flag,
1079 dac_calib, _, _, _),
1080 [64] = PINGROUP(64, _, unused_gsm1, dac_calib, _, _, _, _, _, _, _, _),
1081 [65] = PINGROUP(65, _, _, _, _, _, _, _, _, _, _, _),
1082 [66] = PINGROUP(66, _, dac_calib, _, _, _, _, _, _, _, _, _),
1083 [67] = PINGROUP(67, _, _, _, _, _, _, _, _, _, _, _),
1084 [68] = PINGROUP(68, _, ssbi_wtr, emac1_ptp_aux, emac1_ptp_pps, pwm, dac_calib, _, _, _,
1085 _, _),
1086 [69] = PINGROUP(69, _, ssbi_wtr, emac0_ptp_aux, emac0_ptp_pps, _, phase_flag, dac_calib,
1087 _, _, _, _),
1088 [70] = PINGROUP(70, _, ssbi_wtr, _, phase_flag, dac_calib, _, _, _, _, _, _),
1089 [71] = PINGROUP(71, _, ssbi_wtr, nav_gpio, _, phase_flag, _, _, _, _, _, _),
1090 [72] = PINGROUP(72, _, _, phase_flag, _, _, _, _, _, _, _, _),
1091 [73] = PINGROUP(73, _, _, _, _, _, _, _, _, _, _, _),
1092 [74] = PINGROUP(74, pll, _, pbs_in, phase_flag, _, _, _, _, _, _, _),
1093 [75] = PINGROUP(75, gsm0_tx, _, _, _, _, _, _, _, _, _, _),
1094 [76] = PINGROUP(76, pll, _, _, _, _, _, _, _, _, _, _),
1095 [77] = PINGROUP(77, uim2, pwm, _, _, _, _, _, _, _, _, _),
1096 [78] = PINGROUP(78, uim2, _, _, _, _, _, _, _, _, _, _),
1097 [79] = PINGROUP(79, uim2, pwm, _, _, _, _, _, _, _, _, _),
1098 [80] = PINGROUP(80, uim2, pwm, _, _, _, _, _, _, _, _, _),
1099 [81] = PINGROUP(81, uim1, _, _, _, _, _, _, _, _, _, _),
1100 [82] = PINGROUP(82, uim1, _, _, _, _, _, _, _, _, _, _),
1101 [83] = PINGROUP(83, uim1, _, _, _, _, _, _, _, _, _, _),
1102 [84] = PINGROUP(84, uim1, _, _, _, _, _, _, _, _, _, _),
1103 [85] = PINGROUP(85, emac0_ptp_aux, emac0_ptp_pps, _, _, _, _, _, _, _, _, _),
1104 [86] = PINGROUP(86, mdp_vsync_p, mdp_vsync_out0, mdp_vsync_out1, _, _, _, _, _, _, _, _),
1105 [87] = PINGROUP(87, _, pwm, _, _, _, _, _, _, _, _, _),
1106 [88] = PINGROUP(88, gcc_gp, _, dac_calib, _, _, _, _, _, _, _, _),
1107 [89] = PINGROUP(89, gcc_gp, _, dac_calib, _, _, _, _, _, _, _, _),
1108 [90] = PINGROUP(90, usb0_phy_ps, _, dac_calib, _, _, _, _, _, _, _, _),
1109 [91] = PINGROUP(91, nav_gpio, _, _, _, _, _, _, _, _, _, _),
1110 [92] = PINGROUP(92, nav_gpio, _, _, _, _, _, _, _, _, _, _),
1111 [93] = PINGROUP(93, _, _, _, _, _, _, _, _, _, _, _),
1112 [94] = PINGROUP(94, mdp_vsync_e, qdss_cti, qdss_cti, _, _, _, _, _, _, _, _),
1113 [95] = PINGROUP(95, nav_gpio, mdp_vsync_s, qdss_cti, qdss_cti, _, _, _, _, _, _, _),
1114 [96] = PINGROUP(96, dmic, cam_mclk, i2s1, jitter_bist, atest_gpsadc, atest_usb, _, _, _,
1115 _, _),
1116 [97] = PINGROUP(97, dmic, i2s1, dac_calib, _, _, _, _, _, _, _, _),
1117 [98] = PINGROUP(98, dmic, cam_mclk, i2s1, _, sdc_cdc, atest_usb, ddr_pxi, _, _, _, _),
1118 [99] = PINGROUP(99, dmic, i2s1, jitter_bist, sdc_cdc, atest_usb, ddr_pxi, _, _, _, _, _),
1119 [100] = PINGROUP(100, i2s2, nav_gpio, _, sdc_cdc, atest_usb, ddr_pxi, _, _, _, _, _),
1120 [101] = PINGROUP(101, i2s2, nav_gpio, _, sdc_cdc, atest_usb, ddr_pxi, _, _, _, _, _),
1121 [102] = PINGROUP(102, i2s2, pwm, _, phase_flag, _, _, _, _, _, _, _),
1122 [103] = PINGROUP(103, ext_mclk, i2s2, _, _, _, _, _, _, _, _, _),
1123 [104] = PINGROUP(104, ext_mclk, nav_gpio, _, _, _, _, _, _, _, _, _),
1124 [105] = PINGROUP(105, swr0_tx, i2s0, _, _, _, _, _, _, _, _, _),
1125 [106] = PINGROUP(106, swr0_tx, i2s0, _, _, _, _, _, _, _, _, _),
1126 [107] = PINGROUP(107, swr0_rx, i2s0, _, _, _, _, _, _, _, _, _),
1127 [108] = PINGROUP(108, swr0_rx, i2s0, _, _, _, _, _, _, _, _, _),
1128 [109] = PINGROUP(109, swr0_rx, i2s0, sd_write_protect, _, _, _, _, _, _, _, _),
1129 [110] = PINGROUP(110, ext_mclk, i2s0, _, gcc_gp, _, _, _, _, _, _, _),
1130 [111] = PINGROUP(111, i2s3, _, _, _, _, _, _, _, _, _, _),
1131 [112] = PINGROUP(112, i2s3, _, _, _, _, _, _, _, _, _, _),
1132 [113] = PINGROUP(113, i2s3, _, _, _, _, _, _, _, _, _, _),
1133 [114] = PINGROUP(114, ext_mclk, i2s3, _, _, _, _, _, _, _, _, _),
1134 [115] = PINGROUP(115, mss_lte, _, _, _, _, _, _, _, _, _, _),
1135 [116] = PINGROUP(116, mss_lte, _, dac_calib, _, _, _, _, _, _, _, _),
1136 [117] = PINGROUP(117, pcie0_clk_req_n, _, dac_calib, _, _, _, _, _, _, _, _),
1137 [118] = PINGROUP(118, _, dac_calib, _, _, _, _, _, _, _, _, _),
1138 [119] = PINGROUP(119, _, _, _, _, _, _, _, _, _, _, _),
1139 [120] = PINGROUP(120, emac_phy, _, _, _, _, _, _, _, _, _, _),
1140 [121] = PINGROUP(121, rgmii, _, _, _, _, _, _, _, _, _, _),
1141 [122] = PINGROUP(122, rgmii, _, _, _, _, _, _, _, _, _, _),
1142 [123] = PINGROUP(123, rgmii, _, _, _, _, _, _, _, _, _, _),
1143 [124] = PINGROUP(124, rgmii, _, _, _, _, _, _, _, _, _, _),
1144 [125] = PINGROUP(125, rgmii, _, _, _, _, _, _, _, _, _, _),
1145 [126] = PINGROUP(126, rgmii, _, _, _, _, _, _, _, _, _, _),
1146 [127] = PINGROUP(127, rgmii, _, _, _, _, _, _, _, _, _, _),
1147 [128] = PINGROUP(128, rgmii, _, _, _, _, _, _, _, _, _, _),
1148 [129] = PINGROUP(129, rgmii, _, _, _, _, _, _, _, _, _, _),
1149 [130] = PINGROUP(130, rgmii, _, _, _, _, _, _, _, _, _, _),
1150 [131] = PINGROUP(131, rgmii, _, _, _, _, _, _, _, _, _, _),
1151 [132] = PINGROUP(132, rgmii, _, _, _, _, _, _, _, _, _, _),
1152 [133] = PINGROUP(133, rgmii, _, _, _, _, _, _, _, _, _, _),
1153 [134] = PINGROUP(134, rgmii, _, _, _, _, _, _, _, _, _, _),
1154 [135] = PINGROUP(135, _, _, _, _, _, _, _, _, _, _, _),
1155 [136] = PINGROUP(136, emac_phy, _, _, _, _, _, _, _, _, _, _),
1156 [137] = PINGROUP(137, rgmii, _, _, _, _, _, _, _, _, _, _),
1157 [138] = PINGROUP(138, rgmii, _, _, _, _, _, _, _, _, _, _),
1158 [139] = PINGROUP(139, rgmii, _, _, _, _, _, _, _, _, _, _),
1159 [140] = PINGROUP(140, rgmii, _, _, _, _, _, _, _, _, _, _),
1160 [141] = PINGROUP(141, rgmii, _, _, _, _, _, _, _, _, _, _),
1161 [142] = PINGROUP(142, rgmii, _, _, _, _, _, _, _, _, _, _),
1162 [143] = PINGROUP(143, rgmii, _, _, _, _, _, _, _, _, _, _),
1163 [144] = PINGROUP(144, rgmii, _, _, _, _, _, _, _, _, _, _),
1164 [145] = PINGROUP(145, rgmii, _, _, _, _, _, _, _, _, _, _),
1165 [146] = PINGROUP(146, rgmii, _, _, _, _, _, _, _, _, _, _),
1166 [147] = PINGROUP(147, rgmii, _, _, _, _, _, _, _, _, _, _),
1167 [148] = PINGROUP(148, rgmii, _, _, _, _, _, _, _, _, _, _),
1168 [149] = PINGROUP(149, rgmii, _, _, _, _, _, _, _, _, _, _),
1169 [150] = PINGROUP(150, rgmii, _, _, _, _, _, _, _, _, _, _),
1170 [151] = PINGROUP(151, _, _, _, _, _, _, _, _, _, _, _),
1171 [152] = PINGROUP(152, _, _, _, _, _, _, _, _, _, _, _),
1172 [153] = PINGROUP(153, _, _, _, _, _, _, _, _, _, _, _),
1173 [154] = PINGROUP(154, _, _, _, _, _, _, _, _, _, _, _),
1174 [155] = PINGROUP(155, _, _, _, _, _, _, _, _, _, _, _),
1175 [156] = PINGROUP(156, _, _, _, _, _, _, _, _, _, _, _),
1176 [157] = PINGROUP(157, _, _, _, _, _, _, _, _, _, _, _),
1177 [158] = PINGROUP(158, _, _, _, _, _, _, _, _, _, _, _),
1178 [159] = PINGROUP(159, _, _, _, _, _, _, _, _, _, _, _),
1179 [160] = PINGROUP(160, _, _, _, _, _, _, _, _, _, _, _),
1180 [161] = PINGROUP(161, _, _, _, _, _, _, _, _, _, _, _),
1181 [162] = PINGROUP(162, _, _, _, _, _, _, _, _, _, _, _),
1182 [163] = PINGROUP(163, _, _, _, _, _, _, _, _, _, _, _),
1183 [164] = PINGROUP(164, _, _, _, _, _, _, _, _, _, _, _),
1184 [165] = PINGROUP(165, _, _, _, _, _, _, _, _, _, _, _),
1185 [166] = SDC_QDSD_PINGROUP(sdc1_rclk, 0xac004, 0, 0),
1186 [167] = SDC_QDSD_PINGROUP(sdc1_clk, 0xac000, 13, 6),
1187 [168] = SDC_QDSD_PINGROUP(sdc1_cmd, 0xac000, 11, 3),
1188 [169] = SDC_QDSD_PINGROUP(sdc1_data, 0xac000, 9, 0),
1189 [170] = SDC_QDSD_PINGROUP(sdc2_clk, 0xaa000, 14, 6),
1190 [171] = SDC_QDSD_PINGROUP(sdc2_cmd, 0xaa000, 11, 3),
1191 [172] = SDC_QDSD_PINGROUP(sdc2_data, 0xaa000, 9, 0),
1192};
1193
1194static const struct msm_gpio_wakeirq_map shikra_mpm_map[] = {
1195 {1, 9 }, {2, 31 }, {5, 49 }, {6, 53 }, {9, 72 }, {10, 10 },
1196 {12, 22 }, {14, 26 }, {17, 29 }, {18, 24 }, {20, 32 }, {22, 33 },
1197 {25, 34 }, {27, 35 }, {28, 36 }, {29, 37 }, {30, 38 }, {31, 39 },
1198 {32, 40 }, {33, 41 }, {38, 42 }, {40, 43 }, {43, 44 }, {44, 45 },
1199 {45, 46 }, {46, 47 }, {47, 48 }, {48, 60 }, {50, 50 }, {51, 51 },
1200 {52, 61 }, {53, 62 }, {57, 52 }, {58, 63 }, {60, 54 }, {63, 64 },
1201 {73, 55 }, {74, 56 }, {75, 57 }, {77, 3 }, {80, 4 }, {84, 5 },
1202 {85, 67 }, {86, 69 }, {88, 70 }, {89, 71 }, {90, 73 }, {91, 74 },
1203 {92, 75 }, {93, 76 }, {94, 77 }, {95, 78 }, {97, 79 }, {99, 80 },
1204 {100, 11 }, {101, 13 }, {102, 14 }, {103, 15 }, {106, 16 }, {108, 17 },
1205 {112, 18 }, {116, 19 }, {117, 20 }, {119, 21 }, {120, 23 }, {136, 25 },
1206 {159, 27 }, {161, 28 },
1207};
1208
1209static const struct msm_pinctrl_soc_data shikra_tlmm = {
1210 .pins = shikra_pins,
1211 .npins = ARRAY_SIZE(shikra_pins),
1212 .functions = shikra_functions,
1213 .nfunctions = ARRAY_SIZE(shikra_functions),
1214 .groups = shikra_groups,
1215 .ngroups = ARRAY_SIZE(shikra_groups),
1216 .ngpios = 166,
1217 .wakeirq_map = shikra_mpm_map,
1218 .nwakeirq_map = ARRAY_SIZE(shikra_mpm_map),
1219};
1220
1221static int shikra_tlmm_probe(struct platform_device *pdev)
1222{
1223 return msm_pinctrl_probe(pdev, &shikra_tlmm);
1224}
1225
1226static const struct of_device_id shikra_tlmm_of_match[] = {
1227 { .compatible = "qcom,shikra-tlmm", .data = &shikra_tlmm },
1228 {},
1229};
1230MODULE_DEVICE_TABLE(of, shikra_tlmm_of_match);
1231
1232static struct platform_driver shikra_tlmm_driver = {
1233 .driver = {
1234 .name = "shikra-tlmm",
1235 .of_match_table = shikra_tlmm_of_match,
1236 },
1237 .probe = shikra_tlmm_probe,
1238};
1239
1240static int __init shikra_tlmm_init(void)
1241{
1242 return platform_driver_register(&shikra_tlmm_driver);
1243}
1244arch_initcall(shikra_tlmm_init);
1245
1246static void __exit shikra_tlmm_exit(void)
1247{
1248 platform_driver_unregister(&shikra_tlmm_driver);
1249}
1250module_exit(shikra_tlmm_exit);
1251
1252MODULE_DESCRIPTION("QTI Shikra TLMM driver");
1253MODULE_LICENSE("GPL");
drivers/pinctrl/qcom/pinctrl-sm4250-lpass-lpi.c+7−0
@@ -7,6 +7,8 @@ · 6 unmodified lines
7#include <linux/gpio/driver.h>7#include <linux/gpio/driver.h>
8#include <linux/module.h>8#include <linux/module.h>
9#include <linux/platform_device.h>9#include <linux/platform_device.h>
10#include <linux/pm_clock.h>
11#include <linux/pm_runtime.h>
10 12
11#include "pinctrl-lpass-lpi.h"13#include "pinctrl-lpass-lpi.h"
12 14
@@ -221,10 +223,15 @@ static const struct of_device_id lpi_pinctrl_of_match[] = { · 208 unmodified lines
221};223};
222MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match);224MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match);
223 225
226static const struct dev_pm_ops lpi_pinctrl_pm_ops = {
227 RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL)
228};
229
224static struct platform_driver lpi_pinctrl_driver = {230static struct platform_driver lpi_pinctrl_driver = {
225 .driver = {231 .driver = {
226 .name = "qcom-sm4250-lpass-lpi-pinctrl",232 .name = "qcom-sm4250-lpass-lpi-pinctrl",
227 .of_match_table = lpi_pinctrl_of_match,233 .of_match_table = lpi_pinctrl_of_match,
234 .pm = pm_ptr(&lpi_pinctrl_pm_ops),
228 },235 },
229 .probe = lpi_pinctrl_probe,236 .probe = lpi_pinctrl_probe,
230 .remove = lpi_pinctrl_remove,237 .remove = lpi_pinctrl_remove,
drivers/pinctrl/qcom/pinctrl-sm4450.c+0−7
@@ -99,13 +99,6 @@ · 98 unmodified lines
99 .intr_detection_width = -1, \99 .intr_detection_width = -1, \
100 }100 }
101 101
102#define QUP_I3C(qup_mode, qup_offset) \
103 { \
104 .mode = qup_mode, \
105 .offset = qup_offset, \
106 }
107
108
109static const struct pinctrl_pin_desc sm4450_pins[] = {102static const struct pinctrl_pin_desc sm4450_pins[] = {
110 PINCTRL_PIN(0, "GPIO_0"),103 PINCTRL_PIN(0, "GPIO_0"),
111 PINCTRL_PIN(1, "GPIO_1"),104 PINCTRL_PIN(1, "GPIO_1"),
drivers/pinctrl/qcom/pinctrl-sm6115-lpass-lpi.c+7−0
@@ -7,6 +7,8 @@ · 6 unmodified lines
7#include <linux/gpio/driver.h>7#include <linux/gpio/driver.h>
8#include <linux/module.h>8#include <linux/module.h>
9#include <linux/platform_device.h>9#include <linux/platform_device.h>
10#include <linux/pm_clock.h>
11#include <linux/pm_runtime.h>
10 12
11#include "pinctrl-lpass-lpi.h"13#include "pinctrl-lpass-lpi.h"
12 14
@@ -141,10 +143,15 @@ static const struct of_device_id lpi_pinctrl_of_match[] = { · 128 unmodified lines
141};143};
142MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match);144MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match);
143 145
146static const struct dev_pm_ops lpi_pinctrl_pm_ops = {
147 RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL)
148};
149
144static struct platform_driver lpi_pinctrl_driver = {150static struct platform_driver lpi_pinctrl_driver = {
145 .driver = {151 .driver = {
146 .name = "qcom-sm6115-lpass-lpi-pinctrl",152 .name = "qcom-sm6115-lpass-lpi-pinctrl",
147 .of_match_table = lpi_pinctrl_of_match,153 .of_match_table = lpi_pinctrl_of_match,
154 .pm = pm_ptr(&lpi_pinctrl_pm_ops),
148 },155 },
149 .probe = lpi_pinctrl_probe,156 .probe = lpi_pinctrl_probe,
150 .remove = lpi_pinctrl_remove,157 .remove = lpi_pinctrl_remove,
drivers/pinctrl/qcom/pinctrl-sm6115.c+26−16
@@ -47,6 +47,8 @@ enum { · 46 unmodified lines
47 .mux_bit = 2, \47 .mux_bit = 2, \
48 .pull_bit = 0, \48 .pull_bit = 0, \
49 .drv_bit = 6, \49 .drv_bit = 6, \
50 .egpio_enable = 12, \
51 .egpio_present = 11, \
50 .oe_bit = 9, \52 .oe_bit = 9, \
51 .in_bit = 0, \53 .in_bit = 0, \
52 .out_bit = 1, \54 .out_bit = 1, \
@@ -374,6 +376,7 @@ enum sm6115_functions { · 321 unmodified lines
374 msm_mux_ddr_pxi1,376 msm_mux_ddr_pxi1,
375 msm_mux_ddr_pxi2,377 msm_mux_ddr_pxi2,
376 msm_mux_ddr_pxi3,378 msm_mux_ddr_pxi3,
379 msm_mux_egpio,
377 msm_mux_gcc_gp1,380 msm_mux_gcc_gp1,
378 msm_mux_gcc_gp2,381 msm_mux_gcc_gp2,
379 msm_mux_gcc_gp3,382 msm_mux_gcc_gp3,
@@ -451,6 +454,11 @@ static const char * const gpio_groups[] = { · 71 unmodified lines
451 "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110",454 "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110",
452 "gpio111", "gpio112",455 "gpio111", "gpio112",
453};456};
457static const char * const egpio_groups[] = {
458 "gpio98", "gpio99", "gpio100", "gpio101", "gpio102", "gpio103",
459 "gpio104", "gpio105", "gpio106", "gpio107", "gpio108", "gpio109",
460 "gpio110", "gpio111", "gpio112",
461};
454static const char * const ddr_bist_groups[] = {462static const char * const ddr_bist_groups[] = {
455 "gpio0", "gpio1", "gpio2", "gpio3",463 "gpio0", "gpio1", "gpio2", "gpio3",
456};464};
@@ -681,6 +689,7 @@ static const struct pinfunction sm6115_functions[] = { · 224 unmodified lines
681 MSM_PIN_FUNCTION(ddr_pxi1),689 MSM_PIN_FUNCTION(ddr_pxi1),
682 MSM_PIN_FUNCTION(ddr_pxi2),690 MSM_PIN_FUNCTION(ddr_pxi2),
683 MSM_PIN_FUNCTION(ddr_pxi3),691 MSM_PIN_FUNCTION(ddr_pxi3),
692 MSM_PIN_FUNCTION(egpio),
684 MSM_PIN_FUNCTION(gcc_gp1),693 MSM_PIN_FUNCTION(gcc_gp1),
685 MSM_PIN_FUNCTION(gcc_gp2),694 MSM_PIN_FUNCTION(gcc_gp2),
686 MSM_PIN_FUNCTION(gcc_gp3),695 MSM_PIN_FUNCTION(gcc_gp3),
@@ -839,21 +848,21 @@ static const struct msm_pingroup sm6115_groups[] = { · 152 unmodified lines
839 [95] = PINGROUP(95, WEST, nav_gpio, gp_pdm0, qdss_gpio, wlan1_adc1, _, _, _, _, _),848 [95] = PINGROUP(95, WEST, nav_gpio, gp_pdm0, qdss_gpio, wlan1_adc1, _, _, _, _, _),
840 [96] = PINGROUP(96, WEST, qup4, nav_gpio, mdp_vsync, gp_pdm1, sd_write, jitter_bist, qdss_cti, qdss_cti, _),849 [96] = PINGROUP(96, WEST, qup4, nav_gpio, mdp_vsync, gp_pdm1, sd_write, jitter_bist, qdss_cti, qdss_cti, _),
841 [97] = PINGROUP(97, WEST, qup4, nav_gpio, mdp_vsync, gp_pdm2, jitter_bist, qdss_cti, qdss_cti, _, _),850 [97] = PINGROUP(97, WEST, qup4, nav_gpio, mdp_vsync, gp_pdm2, jitter_bist, qdss_cti, qdss_cti, _, _),
842 [98] = PINGROUP(98, SOUTH, _, _, _, _, _, _, _, _, _),851 [98] = PINGROUP(98, SOUTH, _, _, _, _, _, _, _, _, egpio),
843 [99] = PINGROUP(99, SOUTH, _, _, _, _, _, _, _, _, _),852 [99] = PINGROUP(99, SOUTH, _, _, _, _, _, _, _, _, egpio),
844 [100] = PINGROUP(100, SOUTH, atest, _, _, _, _, _, _, _, _),853 [100] = PINGROUP(100, SOUTH, atest, _, _, _, _, _, _, _, egpio),
845 [101] = PINGROUP(101, SOUTH, atest, _, _, _, _, _, _, _, _),854 [101] = PINGROUP(101, SOUTH, atest, _, _, _, _, _, _, _, egpio),
846 [102] = PINGROUP(102, SOUTH, _, phase_flag, dac_calib, ddr_pxi2, _, _, _, _, _),855 [102] = PINGROUP(102, SOUTH, _, phase_flag, dac_calib, ddr_pxi2, _, _, _, _, egpio),
847 [103] = PINGROUP(103, SOUTH, _, phase_flag, dac_calib, ddr_pxi2, _, _, _, _, _),856 [103] = PINGROUP(103, SOUTH, _, phase_flag, dac_calib, ddr_pxi2, _, _, _, _, egpio),
848 [104] = PINGROUP(104, SOUTH, _, phase_flag, qdss_gpio, dac_calib, ddr_pxi3, _, _, _, _),857 [104] = PINGROUP(104, SOUTH, _, phase_flag, qdss_gpio, dac_calib, ddr_pxi3, _, _, _, egpio),
849 [105] = PINGROUP(105, SOUTH, _, phase_flag, qdss_gpio, dac_calib, ddr_pxi3, _, _, _, _),858 [105] = PINGROUP(105, SOUTH, _, phase_flag, qdss_gpio, dac_calib, ddr_pxi3, _, _, _, egpio),
850 [106] = PINGROUP(106, SOUTH, nav_gpio, gcc_gp3, qdss_gpio, _, _, _, _, _, _),859 [106] = PINGROUP(106, SOUTH, nav_gpio, gcc_gp3, qdss_gpio, _, _, _, _, _, egpio),
851 [107] = PINGROUP(107, SOUTH, nav_gpio, gcc_gp2, qdss_gpio, _, _, _, _, _, _),860 [107] = PINGROUP(107, SOUTH, nav_gpio, gcc_gp2, qdss_gpio, _, _, _, _, _, egpio),
852 [108] = PINGROUP(108, SOUTH, nav_gpio, _, _, _, _, _, _, _, _),861 [108] = PINGROUP(108, SOUTH, nav_gpio, _, _, _, _, _, _, _, egpio),
853 [109] = PINGROUP(109, SOUTH, _, qdss_gpio, _, _, _, _, _, _, _),862 [109] = PINGROUP(109, SOUTH, _, qdss_gpio, _, _, _, _, _, _, egpio),
854 [110] = PINGROUP(110, SOUTH, _, qdss_gpio, _, _, _, _, _, _, _),863 [110] = PINGROUP(110, SOUTH, _, qdss_gpio, _, _, _, _, _, _, egpio),
855 [111] = PINGROUP(111, SOUTH, _, _, _, _, _, _, _, _, _),864 [111] = PINGROUP(111, SOUTH, _, _, _, _, _, _, _, _, egpio),
856 [112] = PINGROUP(112, SOUTH, _, _, _, _, _, _, _, _, _),865 [112] = PINGROUP(112, SOUTH, _, _, _, _, _, _, _, _, egpio),
857 [113] = UFS_RESET(ufs_reset, 0x78000),866 [113] = UFS_RESET(ufs_reset, 0x78000),
858 [114] = SDC_QDSD_PINGROUP(sdc1_rclk, WEST, 0x75000, 15, 0),867 [114] = SDC_QDSD_PINGROUP(sdc1_rclk, WEST, 0x75000, 15, 0),
859 [115] = SDC_QDSD_PINGROUP(sdc1_clk, WEST, 0x75000, 13, 6),868 [115] = SDC_QDSD_PINGROUP(sdc1_clk, WEST, 0x75000, 13, 6),
@@ -886,6 +895,7 @@ static const struct msm_pinctrl_soc_data sm6115_tlmm = { · 26 unmodified lines
886 .ntiles = ARRAY_SIZE(sm6115_tiles),895 .ntiles = ARRAY_SIZE(sm6115_tiles),
887 .wakeirq_map = sm6115_mpm_map,896 .wakeirq_map = sm6115_mpm_map,
888 .nwakeirq_map = ARRAY_SIZE(sm6115_mpm_map),897 .nwakeirq_map = ARRAY_SIZE(sm6115_mpm_map),
898 .egpio_func = 9,
889};899};
890 900
891static int sm6115_tlmm_probe(struct platform_device *pdev)901static int sm6115_tlmm_probe(struct platform_device *pdev)
@@ -897,6 +907,7 @@ static const struct of_device_id sm6115_tlmm_of_match[] = { · 5 unmodified lines
897 { .compatible = "qcom,sm6115-tlmm", },907 { .compatible = "qcom,sm6115-tlmm", },
898 { }908 { }
899};909};
910MODULE_DEVICE_TABLE(of, sm6115_tlmm_of_match);
900 911
901static struct platform_driver sm6115_tlmm_driver = {912static struct platform_driver sm6115_tlmm_driver = {
902 .driver = {913 .driver = {
@@ -920,4 +931,3 @@ module_exit(sm6115_tlmm_exit); · 17 unmodified lines
920 931
921MODULE_DESCRIPTION("QTI sm6115 tlmm driver");932MODULE_DESCRIPTION("QTI sm6115 tlmm driver");
922MODULE_LICENSE("GPL v2");933MODULE_LICENSE("GPL v2");
923MODULE_DEVICE_TABLE(of, sm6115_tlmm_of_match);
drivers/pinctrl/qcom/pinctrl-sm6125.c+1−1
@@ -1256,6 +1256,7 @@ static const struct of_device_id sm6125_tlmm_of_match[] = { · 1255 unmodified lines
1256 { .compatible = "qcom,sm6125-tlmm", },1256 { .compatible = "qcom,sm6125-tlmm", },
1257 { },1257 { },
1258};1258};
1259MODULE_DEVICE_TABLE(of, sm6125_tlmm_of_match);
1259 1260
1260static struct platform_driver sm6125_tlmm_driver = {1261static struct platform_driver sm6125_tlmm_driver = {
1261 .driver = {1262 .driver = {
@@ -1279,4 +1280,3 @@ module_exit(sm6125_tlmm_exit); · 17 unmodified lines
1279 1280
1280MODULE_DESCRIPTION("QTI sm6125 TLMM driver");1281MODULE_DESCRIPTION("QTI sm6125 TLMM driver");
1281MODULE_LICENSE("GPL v2");1282MODULE_LICENSE("GPL v2");
1282MODULE_DEVICE_TABLE(of, sm6125_tlmm_of_match);
drivers/pinctrl/qcom/pinctrl-sm6350-lpass-lpi.c+156−0
@@ -0,0 +1,156 @@
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2026, Luca Weiss <luca.weiss@fairphone.com>
4 */
5
6#include <linux/gpio/driver.h>
7#include <linux/module.h>
8#include <linux/platform_device.h>
9#include <linux/pm_clock.h>
10#include <linux/pm_runtime.h>
11
12#include "pinctrl-lpass-lpi.h"
13
14enum lpass_lpi_functions {
15 LPI_MUX_dmic1_clk,
16 LPI_MUX_dmic1_data,
17 LPI_MUX_dmic2_clk,
18 LPI_MUX_dmic2_data,
19 LPI_MUX_dmic3_clk,
20 LPI_MUX_dmic3_data,
21 LPI_MUX_i2s1_clk,
22 LPI_MUX_i2s1_data,
23 LPI_MUX_i2s1_ws,
24 LPI_MUX_i2s2_clk,
25 LPI_MUX_i2s2_data,
26 LPI_MUX_i2s2_ws,
27 LPI_MUX_qua_mi2s_data,
28 LPI_MUX_qua_mi2s_sclk,
29 LPI_MUX_qua_mi2s_ws,
30 LPI_MUX_swr_rx_clk,
31 LPI_MUX_swr_rx_data,
32 LPI_MUX_swr_tx_clk,
33 LPI_MUX_swr_tx_data,
34 LPI_MUX_wsa_swr_clk,
35 LPI_MUX_wsa_swr_data,
36 LPI_MUX_gpio,
37 LPI_MUX__,
38};
39
40static const struct pinctrl_pin_desc sm6350_lpi_pins[] = {
41 PINCTRL_PIN(0, "gpio0"),
42 PINCTRL_PIN(1, "gpio1"),
43 PINCTRL_PIN(2, "gpio2"),
44 PINCTRL_PIN(3, "gpio3"),
45 PINCTRL_PIN(4, "gpio4"),
46 PINCTRL_PIN(5, "gpio5"),
47 PINCTRL_PIN(6, "gpio6"),
48 PINCTRL_PIN(7, "gpio7"),
49 PINCTRL_PIN(8, "gpio8"),
50 PINCTRL_PIN(9, "gpio9"),
51 PINCTRL_PIN(10, "gpio10"),
52 PINCTRL_PIN(11, "gpio11"),
53 PINCTRL_PIN(12, "gpio12"),
54 PINCTRL_PIN(13, "gpio13"),
55 PINCTRL_PIN(14, "gpio14"),
56};
57
58static const char * const swr_tx_clk_groups[] = { "gpio0" };
59static const char * const swr_tx_data_groups[] = { "gpio1", "gpio2", "gpio14" };
60static const char * const swr_rx_clk_groups[] = { "gpio3" };
61static const char * const swr_rx_data_groups[] = { "gpio4", "gpio5" };
62static const char * const dmic1_clk_groups[] = { "gpio6" };
63static const char * const dmic1_data_groups[] = { "gpio7" };
64static const char * const dmic2_clk_groups[] = { "gpio8" };
65static const char * const dmic2_data_groups[] = { "gpio9" };
66static const char * const i2s2_clk_groups[] = { "gpio10" };
67static const char * const i2s2_ws_groups[] = { "gpio11" };
68static const char * const dmic3_clk_groups[] = { "gpio12" };
69static const char * const dmic3_data_groups[] = { "gpio13" };
70static const char * const qua_mi2s_sclk_groups[] = { "gpio0" };
71static const char * const qua_mi2s_ws_groups[] = { "gpio1" };
72static const char * const qua_mi2s_data_groups[] = { "gpio2", "gpio3", "gpio4", "gpio5" };
73static const char * const i2s1_clk_groups[] = { "gpio6" };
74static const char * const i2s1_ws_groups[] = { "gpio7" };
75static const char * const i2s1_data_groups[] = { "gpio8", "gpio9" };
76static const char * const wsa_swr_clk_groups[] = { "gpio10" };
77static const char * const wsa_swr_data_groups[] = { "gpio11" };
78static const char * const i2s2_data_groups[] = { "gpio12", "gpio13" };
79
80static const struct lpi_pingroup sm6350_groups[] = {
81 LPI_PINGROUP(0, 0, swr_tx_clk, qua_mi2s_sclk, _, _),
82 LPI_PINGROUP(1, 2, swr_tx_data, qua_mi2s_ws, _, _),
83 LPI_PINGROUP(2, 4, swr_tx_data, qua_mi2s_data, _, _),
84 LPI_PINGROUP(3, 8, swr_rx_clk, qua_mi2s_data, _, _),
85 LPI_PINGROUP(4, 10, swr_rx_data, qua_mi2s_data, _, _),
86 LPI_PINGROUP(5, 12, swr_rx_data, _, qua_mi2s_data, _),
87 LPI_PINGROUP(6, LPI_NO_SLEW, dmic1_clk, i2s1_clk, _, _),
88 LPI_PINGROUP(7, LPI_NO_SLEW, dmic1_data, i2s1_ws, _, _),
89 LPI_PINGROUP(8, LPI_NO_SLEW, dmic2_clk, i2s1_data, _, _),
90 LPI_PINGROUP(9, LPI_NO_SLEW, dmic2_data, i2s1_data, _, _),
91 LPI_PINGROUP(10, 16, i2s2_clk, wsa_swr_clk, _, _),
92 LPI_PINGROUP(11, 18, i2s2_ws, wsa_swr_data, _, _),
93 LPI_PINGROUP(12, LPI_NO_SLEW, dmic3_clk, i2s2_data, _, _),
94 LPI_PINGROUP(13, LPI_NO_SLEW, dmic3_data, i2s2_data, _, _),
95 LPI_PINGROUP_SLEW_SPARE_1(14, 0, swr_tx_data, _, _, _),
96};
97
98static const struct lpi_function sm6350_functions[] = {
99 LPI_FUNCTION(dmic1_clk),
100 LPI_FUNCTION(dmic1_data),
101 LPI_FUNCTION(dmic2_clk),
102 LPI_FUNCTION(dmic2_data),
103 LPI_FUNCTION(dmic3_clk),
104 LPI_FUNCTION(dmic3_data),
105 LPI_FUNCTION(i2s1_clk),
106 LPI_FUNCTION(i2s1_data),
107 LPI_FUNCTION(i2s1_ws),
108 LPI_FUNCTION(i2s2_clk),
109 LPI_FUNCTION(i2s2_data),
110 LPI_FUNCTION(i2s2_ws),
111 LPI_FUNCTION(qua_mi2s_data),
112 LPI_FUNCTION(qua_mi2s_sclk),
113 LPI_FUNCTION(qua_mi2s_ws),
114 LPI_FUNCTION(swr_rx_clk),
115 LPI_FUNCTION(swr_rx_data),
116 LPI_FUNCTION(swr_tx_clk),
117 LPI_FUNCTION(swr_tx_data),
118 LPI_FUNCTION(wsa_swr_clk),
119 LPI_FUNCTION(wsa_swr_data),
120};
121
122static const struct lpi_pinctrl_variant_data sm6350_lpi_data = {
123 .pins = sm6350_lpi_pins,
124 .npins = ARRAY_SIZE(sm6350_lpi_pins),
125 .groups = sm6350_groups,
126 .ngroups = ARRAY_SIZE(sm6350_groups),
127 .functions = sm6350_functions,
128 .nfunctions = ARRAY_SIZE(sm6350_functions),
129};
130
131static const struct of_device_id lpi_pinctrl_of_match[] = {
132 {
133 .compatible = "qcom,sm6350-lpass-lpi-pinctrl",
134 .data = &sm6350_lpi_data,
135 },
136 { }
137};
138MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match);
139
140static const struct dev_pm_ops lpi_pinctrl_pm_ops = {
141 RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL)
142};
143
144static struct platform_driver lpi_pinctrl_driver = {
145 .driver = {
146 .name = "qcom-sm6350-lpass-lpi-pinctrl",
147 .of_match_table = lpi_pinctrl_of_match,
148 .pm = pm_ptr(&lpi_pinctrl_pm_ops),
149 },
150 .probe = lpi_pinctrl_probe,
151 .remove = lpi_pinctrl_remove,
152};
153
154module_platform_driver(lpi_pinctrl_driver);
155MODULE_DESCRIPTION("Qualcomm SM6350 LPI GPIO pin control driver");
156MODULE_LICENSE("GPL");
drivers/pinctrl/qcom/pinctrl-sm6350.c+1−1
@@ -1363,6 +1363,7 @@ static const struct of_device_id sm6350_tlmm_of_match[] = { · 1362 unmodified lines
1363 { .compatible = "qcom,sm6350-tlmm" },1363 { .compatible = "qcom,sm6350-tlmm" },
1364 { },1364 { },
1365};1365};
1366MODULE_DEVICE_TABLE(of, sm6350_tlmm_of_match);
1366 1367
1367static struct platform_driver sm6350_tlmm_driver = {1368static struct platform_driver sm6350_tlmm_driver = {
1368 .driver = {1369 .driver = {
@@ -1386,4 +1387,3 @@ module_exit(sm6350_tlmm_exit); · 17 unmodified lines
1386 1387
1387MODULE_DESCRIPTION("QTI SM6350 TLMM driver");1388MODULE_DESCRIPTION("QTI SM6350 TLMM driver");
1388MODULE_LICENSE("GPL v2");1389MODULE_LICENSE("GPL v2");
1389MODULE_DEVICE_TABLE(of, sm6350_tlmm_of_match);
drivers/pinctrl/qcom/pinctrl-sm6375.c+1−1
@@ -1506,6 +1506,7 @@ static const struct of_device_id sm6375_tlmm_of_match[] = { · 1505 unmodified lines
1506 { .compatible = "qcom,sm6375-tlmm", },1506 { .compatible = "qcom,sm6375-tlmm", },
1507 { },1507 { },
1508};1508};
1509MODULE_DEVICE_TABLE(of, sm6375_tlmm_of_match);
1509 1510
1510static struct platform_driver sm6375_tlmm_driver = {1511static struct platform_driver sm6375_tlmm_driver = {
1511 .driver = {1512 .driver = {
@@ -1529,4 +1530,3 @@ module_exit(sm6375_tlmm_exit); · 17 unmodified lines
1529 1530
1530MODULE_DESCRIPTION("QTI SM6375 TLMM driver");1531MODULE_DESCRIPTION("QTI SM6375 TLMM driver");
1531MODULE_LICENSE("GPL");1532MODULE_LICENSE("GPL");
1532MODULE_DEVICE_TABLE(of, sm6375_tlmm_of_match);
drivers/pinctrl/qcom/pinctrl-sm8150.c+1−1
@@ -1532,6 +1532,7 @@ static const struct of_device_id sm8150_pinctrl_of_match[] = { · 1531 unmodified lines
1532 { .compatible = "qcom,sm8150-pinctrl", },1532 { .compatible = "qcom,sm8150-pinctrl", },
1533 { },1533 { },
1534};1534};
1535MODULE_DEVICE_TABLE(of, sm8150_pinctrl_of_match);
1535 1536
1536static struct platform_driver sm8150_pinctrl_driver = {1537static struct platform_driver sm8150_pinctrl_driver = {
1537 .driver = {1538 .driver = {
@@ -1555,4 +1556,3 @@ module_exit(sm8150_pinctrl_exit); · 17 unmodified lines
1555 1556
1556MODULE_DESCRIPTION("QTI sm8150 pinctrl driver");1557MODULE_DESCRIPTION("QTI sm8150 pinctrl driver");
1557MODULE_LICENSE("GPL v2");1558MODULE_LICENSE("GPL v2");
1558MODULE_DEVICE_TABLE(of, sm8150_pinctrl_of_match);
drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c+11−4
@@ -7,6 +7,8 @@ · 6 unmodified lines
7#include <linux/gpio/driver.h>7#include <linux/gpio/driver.h>
8#include <linux/module.h>8#include <linux/module.h>
9#include <linux/platform_device.h>9#include <linux/platform_device.h>
10#include <linux/pm_clock.h>
11#include <linux/pm_runtime.h>
10 12
11#include "pinctrl-lpass-lpi.h"13#include "pinctrl-lpass-lpi.h"
12 14
@@ -127,17 +129,22 @@ static const struct lpi_pinctrl_variant_data sm8250_lpi_data = { · 114 unmodified lines
127 129
128static const struct of_device_id lpi_pinctrl_of_match[] = {130static const struct of_device_id lpi_pinctrl_of_match[] = {
129 {131 {
130 .compatible = "qcom,sm8250-lpass-lpi-pinctrl",132 .compatible = "qcom,sm8250-lpass-lpi-pinctrl",
131 .data = &sm8250_lpi_data,133 .data = &sm8250_lpi_data,
132 },134 },
133 { }135 { }
134};136};
135MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match);137MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match);
136 138
139static const struct dev_pm_ops lpi_pinctrl_pm_ops = {
140 RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL)
141};
142
137static struct platform_driver lpi_pinctrl_driver = {143static struct platform_driver lpi_pinctrl_driver = {
138 .driver = {144 .driver = {
139 .name = "qcom-sm8250-lpass-lpi-pinctrl",145 .name = "qcom-sm8250-lpass-lpi-pinctrl",
140 .of_match_table = lpi_pinctrl_of_match,146 .of_match_table = lpi_pinctrl_of_match,
147 .pm = pm_ptr(&lpi_pinctrl_pm_ops),
141 },148 },
142 .probe = lpi_pinctrl_probe,149 .probe = lpi_pinctrl_probe,
143 .remove = lpi_pinctrl_remove,150 .remove = lpi_pinctrl_remove,
drivers/pinctrl/qcom/pinctrl-sm8250.c+1−1
@@ -1354,6 +1354,7 @@ static const struct of_device_id sm8250_pinctrl_of_match[] = { · 1353 unmodified lines
1354 { .compatible = "qcom,sm8250-pinctrl", },1354 { .compatible = "qcom,sm8250-pinctrl", },
1355 { },1355 { },
1356};1356};
1357MODULE_DEVICE_TABLE(of, sm8250_pinctrl_of_match);
1357 1358
1358static struct platform_driver sm8250_pinctrl_driver = {1359static struct platform_driver sm8250_pinctrl_driver = {
1359 .driver = {1360 .driver = {
@@ -1377,4 +1378,3 @@ module_exit(sm8250_pinctrl_exit); · 17 unmodified lines
1377 1378
1378MODULE_DESCRIPTION("QTI sm8250 pinctrl driver");1379MODULE_DESCRIPTION("QTI sm8250 pinctrl driver");
1379MODULE_LICENSE("GPL v2");1380MODULE_LICENSE("GPL v2");
1380MODULE_DEVICE_TABLE(of, sm8250_pinctrl_of_match);
drivers/pinctrl/qcom/pinctrl-sm8350.c+1−1
@@ -1632,6 +1632,7 @@ static const struct of_device_id sm8350_tlmm_of_match[] = { · 1631 unmodified lines
1632 { .compatible = "qcom,sm8350-tlmm", },1632 { .compatible = "qcom,sm8350-tlmm", },
1633 { },1633 { },
1634};1634};
1635MODULE_DEVICE_TABLE(of, sm8350_tlmm_of_match);
1635 1636
1636static struct platform_driver sm8350_tlmm_driver = {1637static struct platform_driver sm8350_tlmm_driver = {
1637 .driver = {1638 .driver = {
@@ -1655,4 +1656,3 @@ module_exit(sm8350_tlmm_exit); · 17 unmodified lines
1655 1656
1656MODULE_DESCRIPTION("QTI SM8350 TLMM driver");1657MODULE_DESCRIPTION("QTI SM8350 TLMM driver");
1657MODULE_LICENSE("GPL v2");1658MODULE_LICENSE("GPL v2");
1658MODULE_DEVICE_TABLE(of, sm8350_tlmm_of_match);
drivers/pinctrl/qcom/pinctrl-sm8450-lpass-lpi.c+11−4
@@ -6,6 +6,8 @@ · 5 unmodified lines
6#include <linux/gpio/driver.h>6#include <linux/gpio/driver.h>
7#include <linux/module.h>7#include <linux/module.h>
8#include <linux/platform_device.h>8#include <linux/platform_device.h>
9#include <linux/pm_clock.h>
10#include <linux/pm_runtime.h>
9 11
10#include "pinctrl-lpass-lpi.h"12#include "pinctrl-lpass-lpi.h"
11 13
@@ -195,17 +197,22 @@ static const struct lpi_pinctrl_variant_data sm8450_lpi_data = { · 183 unmodified lines
195 197
196static const struct of_device_id lpi_pinctrl_of_match[] = {198static const struct of_device_id lpi_pinctrl_of_match[] = {
197 {199 {
198 .compatible = "qcom,sm8450-lpass-lpi-pinctrl",200 .compatible = "qcom,sm8450-lpass-lpi-pinctrl",
199 .data = &sm8450_lpi_data,201 .data = &sm8450_lpi_data,
200 },202 },
201 { }203 { }
202};204};
203MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match);205MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match);
204 206
207static const struct dev_pm_ops lpi_pinctrl_pm_ops = {
208 RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL)
209};
210
205static struct platform_driver lpi_pinctrl_driver = {211static struct platform_driver lpi_pinctrl_driver = {
206 .driver = {212 .driver = {
207 .name = "qcom-sm8450-lpass-lpi-pinctrl",213 .name = "qcom-sm8450-lpass-lpi-pinctrl",
208 .of_match_table = lpi_pinctrl_of_match,214 .of_match_table = lpi_pinctrl_of_match,
215 .pm = pm_ptr(&lpi_pinctrl_pm_ops),
209 },216 },
210 .probe = lpi_pinctrl_probe,217 .probe = lpi_pinctrl_probe,
211 .remove = lpi_pinctrl_remove,218 .remove = lpi_pinctrl_remove,
drivers/pinctrl/qcom/pinctrl-sm8450.c+1−1
@@ -1667,6 +1667,7 @@ static const struct of_device_id sm8450_tlmm_of_match[] = { · 1666 unmodified lines
1667 { .compatible = "qcom,sm8450-tlmm", },1667 { .compatible = "qcom,sm8450-tlmm", },
1668 { },1668 { },
1669};1669};
1670MODULE_DEVICE_TABLE(of, sm8450_tlmm_of_match);
1670 1671
1671static struct platform_driver sm8450_tlmm_driver = {1672static struct platform_driver sm8450_tlmm_driver = {
1672 .driver = {1673 .driver = {
@@ -1690,4 +1691,3 @@ module_exit(sm8450_tlmm_exit); · 17 unmodified lines
1690 1691
1691MODULE_DESCRIPTION("QTI SM8450 TLMM driver");1692MODULE_DESCRIPTION("QTI SM8450 TLMM driver");
1692MODULE_LICENSE("GPL v2");1693MODULE_LICENSE("GPL v2");
1693MODULE_DEVICE_TABLE(of, sm8450_tlmm_of_match);
drivers/pinctrl/qcom/pinctrl-sm8550-lpass-lpi.c+11−4
@@ -6,6 +6,8 @@ · 5 unmodified lines
6#include <linux/gpio/driver.h>6#include <linux/gpio/driver.h>
7#include <linux/module.h>7#include <linux/module.h>
8#include <linux/platform_device.h>8#include <linux/platform_device.h>
9#include <linux/pm_clock.h>
10#include <linux/pm_runtime.h>
9 11
10#include "pinctrl-lpass-lpi.h"12#include "pinctrl-lpass-lpi.h"
11 13
@@ -203,17 +205,22 @@ static const struct lpi_pinctrl_variant_data sm8550_lpi_data = { · 191 unmodified lines
203 205
204static const struct of_device_id lpi_pinctrl_of_match[] = {206static const struct of_device_id lpi_pinctrl_of_match[] = {
205 {207 {
206 .compatible = "qcom,sm8550-lpass-lpi-pinctrl",208 .compatible = "qcom,sm8550-lpass-lpi-pinctrl",
207 .data = &sm8550_lpi_data,209 .data = &sm8550_lpi_data,
208 },210 },
209 { }211 { }
210};212};
211MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match);213MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match);
212 214
215static const struct dev_pm_ops lpi_pinctrl_pm_ops = {
216 RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL)
217};
218
213static struct platform_driver lpi_pinctrl_driver = {219static struct platform_driver lpi_pinctrl_driver = {
214 .driver = {220 .driver = {
215 .name = "qcom-sm8550-lpass-lpi-pinctrl",221 .name = "qcom-sm8550-lpass-lpi-pinctrl",
216 .of_match_table = lpi_pinctrl_of_match,222 .of_match_table = lpi_pinctrl_of_match,
223 .pm = pm_ptr(&lpi_pinctrl_pm_ops),
217 },224 },
218 .probe = lpi_pinctrl_probe,225 .probe = lpi_pinctrl_probe,
219 .remove = lpi_pinctrl_remove,226 .remove = lpi_pinctrl_remove,
drivers/pinctrl/qcom/pinctrl-sm8550.c+1−1
@@ -1752,6 +1752,7 @@ static const struct of_device_id sm8550_tlmm_of_match[] = { · 1751 unmodified lines
1752 { .compatible = "qcom,sm8550-tlmm", },1752 { .compatible = "qcom,sm8550-tlmm", },
1753 {},1753 {},
1754};1754};
1755MODULE_DEVICE_TABLE(of, sm8550_tlmm_of_match);
1755 1756
1756static struct platform_driver sm8550_tlmm_driver = {1757static struct platform_driver sm8550_tlmm_driver = {
1757 .driver = {1758 .driver = {
@@ -1775,4 +1776,3 @@ module_exit(sm8550_tlmm_exit); · 17 unmodified lines
1775 1776
1776MODULE_DESCRIPTION("QTI SM8550 TLMM driver");1777MODULE_DESCRIPTION("QTI SM8550 TLMM driver");
1777MODULE_LICENSE("GPL");1778MODULE_LICENSE("GPL");
1778MODULE_DEVICE_TABLE(of, sm8550_tlmm_of_match);
drivers/pinctrl/qcom/pinctrl-sm8650-lpass-lpi.c+11−4
@@ -6,6 +6,8 @@ · 5 unmodified lines
6#include <linux/gpio/driver.h>6#include <linux/gpio/driver.h>
7#include <linux/module.h>7#include <linux/module.h>
8#include <linux/platform_device.h>8#include <linux/platform_device.h>
9#include <linux/pm_clock.h>
10#include <linux/pm_runtime.h>
9 11
10#include "pinctrl-lpass-lpi.h"12#include "pinctrl-lpass-lpi.h"
11 13
@@ -210,17 +212,22 @@ static const struct lpi_pinctrl_variant_data sm8650_lpi_data = { · 198 unmodified lines
210 212
211static const struct of_device_id lpi_pinctrl_of_match[] = {213static const struct of_device_id lpi_pinctrl_of_match[] = {
212 {214 {
213 .compatible = "qcom,sm8650-lpass-lpi-pinctrl",215 .compatible = "qcom,sm8650-lpass-lpi-pinctrl",
214 .data = &sm8650_lpi_data,216 .data = &sm8650_lpi_data,
215 },217 },
216 { }218 { }
217};219};
218MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match);220MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match);
219 221
222static const struct dev_pm_ops lpi_pinctrl_pm_ops = {
223 RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL)
224};
225
220static struct platform_driver lpi_pinctrl_driver = {226static struct platform_driver lpi_pinctrl_driver = {
221 .driver = {227 .driver = {
222 .name = "qcom-sm8650-lpass-lpi-pinctrl",228 .name = "qcom-sm8650-lpass-lpi-pinctrl",
223 .of_match_table = lpi_pinctrl_of_match,229 .of_match_table = lpi_pinctrl_of_match,
230 .pm = pm_ptr(&lpi_pinctrl_pm_ops),
224 },231 },
225 .probe = lpi_pinctrl_probe,232 .probe = lpi_pinctrl_probe,
226 .remove = lpi_pinctrl_remove,233 .remove = lpi_pinctrl_remove,
drivers/pinctrl/qcom/pinctrl-sm8650.c+1−1
@@ -1732,6 +1732,7 @@ static const struct of_device_id sm8650_tlmm_of_match[] = { · 1731 unmodified lines
1732 { .compatible = "qcom,sm8650-tlmm", },1732 { .compatible = "qcom,sm8650-tlmm", },
1733 {},1733 {},
1734};1734};
1735MODULE_DEVICE_TABLE(of, sm8650_tlmm_of_match);
1735 1736
1736static struct platform_driver sm8650_tlmm_driver = {1737static struct platform_driver sm8650_tlmm_driver = {
1737 .driver = {1738 .driver = {
@@ -1755,4 +1756,3 @@ module_exit(sm8650_tlmm_exit); · 17 unmodified lines
1755 1756
1756MODULE_DESCRIPTION("QTI SM8650 TLMM driver");1757MODULE_DESCRIPTION("QTI SM8650 TLMM driver");
1757MODULE_LICENSE("GPL");1758MODULE_LICENSE("GPL");
1758MODULE_DEVICE_TABLE(of, sm8650_tlmm_of_match);
drivers/pinctrl/qcom/pinctrl-sm8750.c+1−1
@@ -1701,6 +1701,7 @@ static const struct of_device_id sm8750_tlmm_of_match[] = { · 1700 unmodified lines
1701 { .compatible = "qcom,sm8750-tlmm", },1701 { .compatible = "qcom,sm8750-tlmm", },
1702 {},1702 {},
1703};1703};
1704MODULE_DEVICE_TABLE(of, sm8750_tlmm_of_match);
1704 1705
1705static struct platform_driver sm8750_tlmm_driver = {1706static struct platform_driver sm8750_tlmm_driver = {
1706 .driver = {1707 .driver = {
@@ -1724,4 +1725,3 @@ module_exit(sm8750_tlmm_exit); · 17 unmodified lines
1724 1725
1725MODULE_DESCRIPTION("QTI SM8750 TLMM driver");1726MODULE_DESCRIPTION("QTI SM8750 TLMM driver");
1726MODULE_LICENSE("GPL");1727MODULE_LICENSE("GPL");
1727MODULE_DEVICE_TABLE(of, sm8750_tlmm_of_match);
drivers/pinctrl/qcom/pinctrl-spmi-gpio.c+1−0
@@ -1229,6 +1229,7 @@ static const struct of_device_id pmic_gpio_of_match[] = { · 1228 unmodified lines
1229 { .compatible = "qcom,pm7550-gpio", .data = (void *) 12 },1229 { .compatible = "qcom,pm7550-gpio", .data = (void *) 12 },
1230 { .compatible = "qcom,pm7550ba-gpio", .data = (void *) 8},1230 { .compatible = "qcom,pm7550ba-gpio", .data = (void *) 8},
1231 { .compatible = "qcom,pm8005-gpio", .data = (void *) 4 },1231 { .compatible = "qcom,pm8005-gpio", .data = (void *) 4 },
1232 { .compatible = "qcom,pm8010-gpio", .data = (void *) 2 },
1232 { .compatible = "qcom,pm8019-gpio", .data = (void *) 6 },1233 { .compatible = "qcom,pm8019-gpio", .data = (void *) 6 },
1233 /* pm8150 has 10 GPIOs with holes on 2, 5, 7 and 8 */1234 /* pm8150 has 10 GPIOs with holes on 2, 5, 7 and 8 */
1234 { .compatible = "qcom,pm8150-gpio", .data = (void *) 10 },1235 { .compatible = "qcom,pm8150-gpio", .data = (void *) 10 },
drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c+5−5
@@ -53,7 +53,7 @@ · 52 unmodified lines
53#define PM8XXX_GPIO_PHYSICAL_OFFSET 153#define PM8XXX_GPIO_PHYSICAL_OFFSET 1
54 54
55/* custom pinconf parameters */55/* custom pinconf parameters */
56#define PM8XXX_QCOM_DRIVE_STRENGH (PIN_CONFIG_END + 1)56#define PM8XXX_QCOM_DRIVE_STRENGTH (PIN_CONFIG_END + 1)
57#define PM8XXX_QCOM_PULL_UP_STRENGTH (PIN_CONFIG_END + 2)57#define PM8XXX_QCOM_PULL_UP_STRENGTH (PIN_CONFIG_END + 2)
58 58
59/**59/**
@@ -97,13 +97,13 @@ struct pm8xxx_gpio { · 37 unmodified lines
97};97};
98 98
99static const struct pinconf_generic_params pm8xxx_gpio_bindings[] = {99static const struct pinconf_generic_params pm8xxx_gpio_bindings[] = {
100 {"qcom,drive-strength", PM8XXX_QCOM_DRIVE_STRENGH, 0},100 {"qcom,drive-strength", PM8XXX_QCOM_DRIVE_STRENGTH, 0},
101 {"qcom,pull-up-strength", PM8XXX_QCOM_PULL_UP_STRENGTH, 0},101 {"qcom,pull-up-strength", PM8XXX_QCOM_PULL_UP_STRENGTH, 0},
102};102};
103 103
104#ifdef CONFIG_DEBUG_FS104#ifdef CONFIG_DEBUG_FS
105static const struct pin_config_item pm8xxx_conf_items[ARRAY_SIZE(pm8xxx_gpio_bindings)] = {105static const struct pin_config_item pm8xxx_conf_items[ARRAY_SIZE(pm8xxx_gpio_bindings)] = {
106 PCONFDUMP(PM8XXX_QCOM_DRIVE_STRENGH, "drive-strength", NULL, true),106 PCONFDUMP(PM8XXX_QCOM_DRIVE_STRENGTH, "drive-strength", NULL, true),
107 PCONFDUMP(PM8XXX_QCOM_PULL_UP_STRENGTH, "pull up strength", NULL, true),107 PCONFDUMP(PM8XXX_QCOM_PULL_UP_STRENGTH, "pull up strength", NULL, true),
108};108};
109#endif109#endif
@@ -291,7 +291,7 @@ static int pm8xxx_pin_config_get(struct pinctrl_dev *pctldev, · 181 unmodified lines
291 case PIN_CONFIG_POWER_SOURCE:291 case PIN_CONFIG_POWER_SOURCE:
292 arg = pin->power_source;292 arg = pin->power_source;
293 break;293 break;
294 case PM8XXX_QCOM_DRIVE_STRENGH:294 case PM8XXX_QCOM_DRIVE_STRENGTH:
295 arg = pin->output_strength;295 arg = pin->output_strength;
296 break;296 break;
297 case PIN_CONFIG_DRIVE_PUSH_PULL:297 case PIN_CONFIG_DRIVE_PUSH_PULL:
@@ -373,7 +373,7 @@ static int pm8xxx_pin_config_set(struct pinctrl_dev *pctldev, · 75 unmodified lines
373 pin->power_source = arg;373 pin->power_source = arg;
374 banks |= BIT(0);374 banks |= BIT(0);
375 break;375 break;
376 case PM8XXX_QCOM_DRIVE_STRENGH:376 case PM8XXX_QCOM_DRIVE_STRENGTH:
377 if (arg > PMIC_GPIO_STRENGTH_LOW) {377 if (arg > PMIC_GPIO_STRENGTH_LOW) {
378 dev_err(pctrl->dev, "invalid drive strength\n");378 dev_err(pctrl->dev, "invalid drive strength\n");
379 return -EINVAL;379 return -EINVAL;
drivers/pinctrl/qcom/pinctrl-x1e80100.c+1−1
@@ -1851,6 +1851,7 @@ static const struct of_device_id x1e80100_pinctrl_of_match[] = { · 1850 unmodified lines
1851 { .compatible = "qcom,x1e80100-tlmm", },1851 { .compatible = "qcom,x1e80100-tlmm", },
1852 { },1852 { },
1853};1853};
1854MODULE_DEVICE_TABLE(of, x1e80100_pinctrl_of_match);
1854 1855
1855static struct platform_driver x1e80100_pinctrl_driver = {1856static struct platform_driver x1e80100_pinctrl_driver = {
1856 .driver = {1857 .driver = {
@@ -1874,4 +1875,3 @@ module_exit(x1e80100_pinctrl_exit); · 17 unmodified lines
1874 1875
1875MODULE_DESCRIPTION("QTI X1E80100 TLMM pinctrl driver");1876MODULE_DESCRIPTION("QTI X1E80100 TLMM pinctrl driver");
1876MODULE_LICENSE("GPL");1877MODULE_LICENSE("GPL");
1877MODULE_DEVICE_TABLE(of, x1e80100_pinctrl_of_match);
drivers/pinctrl/qcom/tlmm-test.c+10−11
@@ -33,7 +33,7 @@ · 32 unmodified lines
33 * dynamically, rather then relying on e.g. Devicetree and phandles.33 * dynamically, rather then relying on e.g. Devicetree and phandles.
34 */34 */
35 35
36#define MSM_PULL_MASK GENMASK(2, 0)36#define MSM_PULL_MASK GENMASK(1, 0)
37#define MSM_PULL_DOWN 137#define MSM_PULL_DOWN 1
38#define MSM_PULL_UP 338#define MSM_PULL_UP 3
39#define TLMM_REG_SIZE 0x100039#define TLMM_REG_SIZE 0x1000
@@ -581,6 +581,9 @@ static int tlmm_reg_base(struct device_node *tlmm, struct resource *res) · 541 unmodified lines
581 int ret;581 int ret;
582 int i;582 int i;
583 583
584 if (!strcmp(tlmm_reg_name, "default_region"))
585 return of_address_to_resource(tlmm, 0, res);
586
584 count = of_property_count_strings(tlmm, "reg-names");587 count = of_property_count_strings(tlmm, "reg-names");
585 if (count <= 0) {588 if (count <= 0) {
586 pr_err("failed to find tlmm reg name\n");589 pr_err("failed to find tlmm reg name\n");
@@ -597,18 +600,14 @@ static int tlmm_reg_base(struct device_node *tlmm, struct resource *res) · 10 unmodified lines
597 return -EINVAL;600 return -EINVAL;
598 }601 }
599 602
600 if (!strcmp(tlmm_reg_name, "default_region")) {603 for (i = 0; i < count; i++) {
601 ret = of_address_to_resource(tlmm, 0, res);604 if (!strcmp(reg_names[i], tlmm_reg_name)) {
602 } else {605 ret = of_address_to_resource(tlmm, i, res);
603 for (i = 0; i < count; i++) {606 break;
604 if (!strcmp(reg_names[i], tlmm_reg_name)) {
605 ret = of_address_to_resource(tlmm, i, res);
606 break;
607 }
608 }607 }
609 if (i == count)
610 ret = -EINVAL;
611 }608 }
609 if (i == count)
610 ret = -EINVAL;
612 611
613 kfree(reg_names);612 kfree(reg_names);
614 613
drivers/pinctrl/realtek/Kconfig+6−6
@@ -2,8 +2,8 @@ · 1 unmodified line
2 2
3config PINCTRL_RTD3config PINCTRL_RTD
4 tristate "Realtek DHC core pin controller driver"4 tristate "Realtek DHC core pin controller driver"
5 depends on ARCH_REALTEK5 depends on ARCH_REALTEK || (COMPILE_TEST && OF)
6 default y6 default ARCH_REALTEK
7 select PINMUX7 select PINMUX
8 select GENERIC_PINCONF8 select GENERIC_PINCONF
9 select REGMAP_MMIO9 select REGMAP_MMIO
@@ -11,22 +11,22 @@ config PINCTRL_RTD · 1 unmodified line
11config PINCTRL_RTD1619B11config PINCTRL_RTD1619B
12 tristate "Realtek DHC 1619B pin controller driver"12 tristate "Realtek DHC 1619B pin controller driver"
13 depends on PINCTRL_RTD13 depends on PINCTRL_RTD
14 default y14 default ARCH_REALTEK
15 15
16config PINCTRL_RTD1319D16config PINCTRL_RTD1319D
17 tristate "Realtek DHC 1319D pin controller driver"17 tristate "Realtek DHC 1319D pin controller driver"
18 depends on PINCTRL_RTD18 depends on PINCTRL_RTD
19 default y19 default ARCH_REALTEK
20 20
21config PINCTRL_RTD1315E21config PINCTRL_RTD1315E
22 tristate "Realtek DHC 1315E pin controller driver"22 tristate "Realtek DHC 1315E pin controller driver"
23 depends on PINCTRL_RTD23 depends on PINCTRL_RTD
24 default y24 default ARCH_REALTEK
25 25
26config PINCTRL_RTD162526config PINCTRL_RTD1625
27 tristate "Realtek DHC 1625 pin controller driver"27 tristate "Realtek DHC 1625 pin controller driver"
28 depends on PINCTRL_RTD28 depends on PINCTRL_RTD
29 default y29 default ARCH_REALTEK
30 help30 help
31 This driver enables support for the pin controller on the Realtek31 This driver enables support for the pin controller on the Realtek
32 RTD1625 SoCs.32 RTD1625 SoCs.
drivers/pinctrl/realtek/pinctrl-rtd.c+6−6
@@ -34,14 +34,14 @@ struct rtd_pinctrl { · 33 unmodified lines
34};34};
35 35
36/* custom pinconf parameters */36/* custom pinconf parameters */
37#define RTD_DRIVE_STRENGH_P (PIN_CONFIG_END + 1)37#define RTD_DRIVE_STRENGTH_P (PIN_CONFIG_END + 1)
38#define RTD_DRIVE_STRENGH_N (PIN_CONFIG_END + 2)38#define RTD_DRIVE_STRENGTH_N (PIN_CONFIG_END + 2)
39#define RTD_DUTY_CYCLE (PIN_CONFIG_END + 3)39#define RTD_DUTY_CYCLE (PIN_CONFIG_END + 3)
40#define RTD_HIGH_VIL (PIN_CONFIG_END + 4)40#define RTD_HIGH_VIL (PIN_CONFIG_END + 4)
41 41
42static const struct pinconf_generic_params rtd_custom_bindings[] = {42static const struct pinconf_generic_params rtd_custom_bindings[] = {
43 {"realtek,drive-strength-p", RTD_DRIVE_STRENGH_P, 0},43 {"realtek,drive-strength-p", RTD_DRIVE_STRENGTH_P, 0},
44 {"realtek,drive-strength-n", RTD_DRIVE_STRENGH_N, 0},44 {"realtek,drive-strength-n", RTD_DRIVE_STRENGTH_N, 0},
45 {"realtek,duty-cycle", RTD_DUTY_CYCLE, 0},45 {"realtek,duty-cycle", RTD_DUTY_CYCLE, 0},
46 {"realtek,high-vil-microvolt", RTD_HIGH_VIL, 0},46 {"realtek,high-vil-microvolt", RTD_HIGH_VIL, 0},
47};47};
@@ -473,7 +473,7 @@ static int rtd_pconf_parse_conf(struct rtd_pinctrl *data, · 425 unmodified lines
473 val = 1;473 val = 1;
474 break;474 break;
475 475
476 case RTD_DRIVE_STRENGH_P:476 case RTD_DRIVE_STRENGTH_P:
477 sconfig_desc = rtd_pinctrl_find_sconfig(data, pinnr);477 sconfig_desc = rtd_pinctrl_find_sconfig(data, pinnr);
478 if (!sconfig_desc) {478 if (!sconfig_desc) {
479 dev_err(data->dev, "P driving unsupported for pin: %s\n", name);479 dev_err(data->dev, "P driving unsupported for pin: %s\n", name);
@@ -490,7 +490,7 @@ static int rtd_pconf_parse_conf(struct rtd_pinctrl *data, · 10 unmodified lines
490 val = set_val << p_off;490 val = set_val << p_off;
491 break;491 break;
492 492
493 case RTD_DRIVE_STRENGH_N:493 case RTD_DRIVE_STRENGTH_N:
494 sconfig_desc = rtd_pinctrl_find_sconfig(data, pinnr);494 sconfig_desc = rtd_pinctrl_find_sconfig(data, pinnr);
495 if (!sconfig_desc) {495 if (!sconfig_desc) {
496 dev_err(data->dev, "N driving unsupported for pin: %s\n", name);496 dev_err(data->dev, "N driving unsupported for pin: %s\n", name);
drivers/pinctrl/renesas/core.c+12−12
@@ -1380,40 +1380,40 @@ static int sh_pfc_probe(struct platform_device *pdev) · 1379 unmodified lines
1380 1380
1381static const struct platform_device_id sh_pfc_id_table[] = {1381static const struct platform_device_id sh_pfc_id_table[] = {
1382#ifdef CONFIG_PINCTRL_PFC_SH72031382#ifdef CONFIG_PINCTRL_PFC_SH7203
1383 { "pfc-sh7203", (kernel_ulong_t)&sh7203_pinmux_info },1383 { .name = "pfc-sh7203", .driver_data = (kernel_ulong_t)&sh7203_pinmux_info },
1384#endif1384#endif
1385#ifdef CONFIG_PINCTRL_PFC_SH72641385#ifdef CONFIG_PINCTRL_PFC_SH7264
1386 { "pfc-sh7264", (kernel_ulong_t)&sh7264_pinmux_info },1386 { .name = "pfc-sh7264", .driver_data = (kernel_ulong_t)&sh7264_pinmux_info },
1387#endif1387#endif
1388#ifdef CONFIG_PINCTRL_PFC_SH72691388#ifdef CONFIG_PINCTRL_PFC_SH7269
1389 { "pfc-sh7269", (kernel_ulong_t)&sh7269_pinmux_info },1389 { .name = "pfc-sh7269", .driver_data = (kernel_ulong_t)&sh7269_pinmux_info },
1390#endif1390#endif
1391#ifdef CONFIG_PINCTRL_PFC_SH77201391#ifdef CONFIG_PINCTRL_PFC_SH7720
1392 { "pfc-sh7720", (kernel_ulong_t)&sh7720_pinmux_info },1392 { .name = "pfc-sh7720", .driver_data = (kernel_ulong_t)&sh7720_pinmux_info },
1393#endif1393#endif
1394#ifdef CONFIG_PINCTRL_PFC_SH77221394#ifdef CONFIG_PINCTRL_PFC_SH7722
1395 { "pfc-sh7722", (kernel_ulong_t)&sh7722_pinmux_info },1395 { .name = "pfc-sh7722", .driver_data = (kernel_ulong_t)&sh7722_pinmux_info },
1396#endif1396#endif
1397#ifdef CONFIG_PINCTRL_PFC_SH77231397#ifdef CONFIG_PINCTRL_PFC_SH7723
1398 { "pfc-sh7723", (kernel_ulong_t)&sh7723_pinmux_info },1398 { .name = "pfc-sh7723", .driver_data = (kernel_ulong_t)&sh7723_pinmux_info },
1399#endif1399#endif
1400#ifdef CONFIG_PINCTRL_PFC_SH77241400#ifdef CONFIG_PINCTRL_PFC_SH7724
1401 { "pfc-sh7724", (kernel_ulong_t)&sh7724_pinmux_info },1401 { .name = "pfc-sh7724", .driver_data = (kernel_ulong_t)&sh7724_pinmux_info },
1402#endif1402#endif
1403#ifdef CONFIG_PINCTRL_PFC_SH77341403#ifdef CONFIG_PINCTRL_PFC_SH7734
1404 { "pfc-sh7734", (kernel_ulong_t)&sh7734_pinmux_info },1404 { .name = "pfc-sh7734", .driver_data = (kernel_ulong_t)&sh7734_pinmux_info },
1405#endif1405#endif
1406#ifdef CONFIG_PINCTRL_PFC_SH77571406#ifdef CONFIG_PINCTRL_PFC_SH7757
1407 { "pfc-sh7757", (kernel_ulong_t)&sh7757_pinmux_info },1407 { .name = "pfc-sh7757", .driver_data = (kernel_ulong_t)&sh7757_pinmux_info },
1408#endif1408#endif
1409#ifdef CONFIG_PINCTRL_PFC_SH77851409#ifdef CONFIG_PINCTRL_PFC_SH7785
1410 { "pfc-sh7785", (kernel_ulong_t)&sh7785_pinmux_info },1410 { .name = "pfc-sh7785", .driver_data = (kernel_ulong_t)&sh7785_pinmux_info },
1411#endif1411#endif
1412#ifdef CONFIG_PINCTRL_PFC_SH77861412#ifdef CONFIG_PINCTRL_PFC_SH7786
1413 { "pfc-sh7786", (kernel_ulong_t)&sh7786_pinmux_info },1413 { .name = "pfc-sh7786", .driver_data = (kernel_ulong_t)&sh7786_pinmux_info },
1414#endif1414#endif
1415#ifdef CONFIG_PINCTRL_PFC_SHX31415#ifdef CONFIG_PINCTRL_PFC_SHX3
1416 { "pfc-shx3", (kernel_ulong_t)&shx3_pinmux_info },1416 { .name = "pfc-shx3", .driver_data = (kernel_ulong_t)&shx3_pinmux_info },
1417#endif1417#endif
1418 { /* sentinel */ }1418 { /* sentinel */ }
1419};1419};
drivers/pinctrl/renesas/pinctrl-rzg2l.c+562−26
@@ -11,12 +11,14 @@ · 10 unmodified lines
11#include <linux/gpio/driver.h>11#include <linux/gpio/driver.h>
12#include <linux/interrupt.h>12#include <linux/interrupt.h>
13#include <linux/io.h>13#include <linux/io.h>
14#include <linux/mfd/syscon.h>
14#include <linux/module.h>15#include <linux/module.h>
15#include <linux/mutex.h>16#include <linux/mutex.h>
16#include <linux/of.h>17#include <linux/of.h>
17#include <linux/of_irq.h>18#include <linux/of_irq.h>
18#include <linux/platform_device.h>19#include <linux/platform_device.h>
19#include <linux/property.h>20#include <linux/property.h>
21#include <linux/regmap.h>
20#include <linux/seq_file.h>22#include <linux/seq_file.h>
21#include <linux/spinlock.h>23#include <linux/spinlock.h>
22 24
@@ -26,6 +28,7 @@ · 3 unmodified lines
26#include <linux/pinctrl/pinctrl.h>28#include <linux/pinctrl/pinctrl.h>
27#include <linux/pinctrl/pinmux.h>29#include <linux/pinctrl/pinmux.h>
28 30
31#include <dt-bindings/pinctrl/renesas,r9a08g046-pinctrl.h>
29#include <dt-bindings/pinctrl/renesas,r9a09g047-pinctrl.h>32#include <dt-bindings/pinctrl/renesas,r9a09g047-pinctrl.h>
30#include <dt-bindings/pinctrl/renesas,r9a09g057-pinctrl.h>33#include <dt-bindings/pinctrl/renesas,r9a09g057-pinctrl.h>
31#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>34#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
@@ -63,10 +66,18 @@ · 31 unmodified lines
63#define PIN_CFG_SMT BIT(16) /* Schmitt-trigger input control */66#define PIN_CFG_SMT BIT(16) /* Schmitt-trigger input control */
64#define PIN_CFG_ELC BIT(17)67#define PIN_CFG_ELC BIT(17)
65#define PIN_CFG_IOLH_RZV2H BIT(18)68#define PIN_CFG_IOLH_RZV2H BIT(18)
69#define PIN_CFG_PVDD1833_OTH_AWO_POC BIT(19) /* known on RZ/G3L only */
70#define PIN_CFG_PVDD1833_OTH_ISO_POC BIT(20) /* known on RZ/G3L only */
71#define PIN_CFG_WDTOVF_N_POC BIT(21) /* known on RZ/G3L only */
66 72
67#define RZG2L_SINGLE_PIN BIT_ULL(63) /* Dedicated pin */73#define RZG2L_SINGLE_PIN BIT_ULL(63) /* Dedicated pin */
68#define RZG2L_VARIABLE_CFG BIT_ULL(62) /* Variable cfg for port pins */74#define RZG2L_VARIABLE_CFG BIT_ULL(62) /* Variable cfg for port pins */
69 75
76#define PIN_CFG_OTHER_POC_MASK \
77 (PIN_CFG_PVDD1833_OTH_AWO_POC | \
78 PIN_CFG_PVDD1833_OTH_ISO_POC | \
79 PIN_CFG_WDTOVF_N_POC)
80
70#define RZG2L_MPXED_COMMON_PIN_FUNCS(group) \81#define RZG2L_MPXED_COMMON_PIN_FUNCS(group) \
71 (PIN_CFG_IOLH_##group | \82 (PIN_CFG_IOLH_##group | \
72 PIN_CFG_PUPD | \83 PIN_CFG_PUPD | \
@@ -85,6 +96,18 @@ · 12 unmodified lines
85 96
86#define RZG2L_MPXED_ETH_PIN_FUNCS(x) ((x) | PIN_CFG_NF)97#define RZG2L_MPXED_ETH_PIN_FUNCS(x) ((x) | PIN_CFG_NF)
87 98
99#define RZG3L_MPXED_ETH_PIN_FUNCS(ether) \
100 (PIN_CFG_IO_VMC_##ether | \
101 PIN_CFG_IOLH_C | \
102 PIN_CFG_PUPD | \
103 PIN_CFG_NF)
104
105#define RZG3L_MPXED_PIN_FUNCS(group) (RZG2L_MPXED_COMMON_PIN_FUNCS(group) | \
106 PIN_CFG_SOFT_PS)
107
108#define RZG3L_MPXED_PIN_FUNCS_POC(grp, poc) (RZG2L_MPXED_COMMON_PIN_FUNCS(grp) | \
109 PIN_CFG_PVDD1833_OTH_##poc##_POC)
110
88#define PIN_CFG_PIN_MAP_MASK GENMASK_ULL(61, 54)111#define PIN_CFG_PIN_MAP_MASK GENMASK_ULL(61, 54)
89#define PIN_CFG_PIN_REG_MASK GENMASK_ULL(53, 46)112#define PIN_CFG_PIN_REG_MASK GENMASK_ULL(53, 46)
90#define PIN_CFG_MASK GENMASK_ULL(31, 0)113#define PIN_CFG_MASK GENMASK_ULL(31, 0)
@@ -131,6 +154,18 @@ · 40 unmodified lines
131 FIELD_PREP_CONST(VARIABLE_PIN_CFG_PORT_MASK, (port)) | \154 FIELD_PREP_CONST(VARIABLE_PIN_CFG_PORT_MASK, (port)) | \
132 FIELD_PREP_CONST(PIN_CFG_MASK, (cfg)))155 FIELD_PREP_CONST(PIN_CFG_MASK, (cfg)))
133 156
157#define RZG3L_CLONE_CHANNEL_PIN_MASK GENMASK(31, 24)
158#define RZG3L_CLONE_CHANNEL_PORT_MASK GENMASK(23, 19)
159#define RZG3L_CLONE_CHANNEL_BIT_MASK GENMASK(12, 9)
160#define RZG3L_CLONE_CHANNEL_VAL_MASK BIT(8)
161#define RZG3L_CLONE_CHANNEL_PFC_MASK GENMASK(7, 0)
162#define RZG3L_CLONE_CHANNEL_DATA(port, pins, bit, val, pfc) \
163 (FIELD_PREP_CONST(RZG3L_CLONE_CHANNEL_PIN_MASK, (pins)) | \
164 FIELD_PREP_CONST(RZG3L_CLONE_CHANNEL_PORT_MASK, (port)) | \
165 FIELD_PREP_CONST(RZG3L_CLONE_CHANNEL_BIT_MASK, (bit)) | \
166 FIELD_PREP_CONST(RZG3L_CLONE_CHANNEL_VAL_MASK, (val)) | \
167 FIELD_PREP_CONST(RZG3L_CLONE_CHANNEL_PFC_MASK, (pfc)))
168
134#define P(off) (0x0000 + (off))169#define P(off) (0x0000 + (off))
135#define PM(off) (0x0100 + (off) * 2)170#define PM(off) (0x0100 + (off) * 2)
136#define PMC(off) (0x0200 + (off))171#define PMC(off) (0x0200 + (off))
@@ -145,7 +180,8 @@ · 8 unmodified lines
145#define SMT(off) (0x3400 + (off) * 8)180#define SMT(off) (0x3400 + (off) * 8)
146#define SD_CH(off, ch) ((off) + (ch) * 4)181#define SD_CH(off, ch) ((off) + (ch) * 4)
147#define ETH_POC(off, ch) ((off) + (ch) * 4)182#define ETH_POC(off, ch) ((off) + (ch) * 4)
148#define QSPI (0x3008)183#define QSPI (0x3008) /* known on RZ/{G2L,G2LC,G2UL,Five} only */
184#define OTHER_POC (0x3028) /* known on RZ/G3L only */
149 185
150#define PVDD_2500 2 /* I/O domain voltage 2.5V */186#define PVDD_2500 2 /* I/O domain voltage 2.5V */
151#define PVDD_1800 1 /* I/O domain voltage <= 1.8V */187#define PVDD_1800 1 /* I/O domain voltage <= 1.8V */
@@ -220,12 +256,16 @@ static const struct pin_config_item renesas_rzv2h_conf_items[] = { · 68 unmodified lines
220 * @sd_ch: SD_CH register offset256 * @sd_ch: SD_CH register offset
221 * @eth_poc: ETH_POC register offset257 * @eth_poc: ETH_POC register offset
222 * @oen: OEN register offset258 * @oen: OEN register offset
259 * @qspi: QSPI register offset
260 * @other_poc: OTHER_POC register offset
223 */261 */
224struct rzg2l_register_offsets {262struct rzg2l_register_offsets {
225 u16 pwpr;263 u16 pwpr;
226 u16 sd_ch;264 u16 sd_ch;
227 u16 eth_poc;265 u16 eth_poc;
228 u16 oen;266 u16 oen;
267 u16 qspi;
268 u16 other_poc;
229};269};
230 270
231/**271/**
@@ -287,6 +327,8 @@ struct rzg2l_pinctrl_data { · 55 unmodified lines
287 const struct rzg2l_dedicated_configs *dedicated_pins;327 const struct rzg2l_dedicated_configs *dedicated_pins;
288 unsigned int n_port_pins;328 unsigned int n_port_pins;
289 unsigned int n_dedicated_pins;329 unsigned int n_dedicated_pins;
330 const u32 *clone_channel_data;
331 unsigned int n_clone_channel_data;
290 const struct rzg2l_hwcfg *hwcfg;332 const struct rzg2l_hwcfg *hwcfg;
291 const u64 *variable_pin_cfg;333 const u64 *variable_pin_cfg;
292 unsigned int n_variable_pin_cfg;334 unsigned int n_variable_pin_cfg;
@@ -319,12 +361,16 @@ struct rzg2l_pinctrl_pin_settings { · 26 unmodified lines
319 * @pmc: PMC registers cache361 * @pmc: PMC registers cache
320 * @pfc: PFC registers cache362 * @pfc: PFC registers cache
321 * @iolh: IOLH registers cache363 * @iolh: IOLH registers cache
322 * @pupd: PUPD registers cache
323 * @ien: IEN registers cache364 * @ien: IEN registers cache
365 * @pupd: PUPD registers cache
324 * @smt: SMT registers cache366 * @smt: SMT registers cache
367 * @sr: SR registers cache
368 * @nod: NOD registers cache
369 * @clone: Clone register cache
325 * @sd_ch: SD_CH registers cache370 * @sd_ch: SD_CH registers cache
326 * @eth_poc: ET_POC registers cache371 * @eth_poc: ET_POC registers cache
327 * @oen: Output Enable register cache372 * @oen: Output Enable register cache
373 * @other_poc: OTHER_POC register cache
328 * @qspi: QSPI registers cache374 * @qspi: QSPI registers cache
329 */375 */
330struct rzg2l_pinctrl_reg_cache {376struct rzg2l_pinctrl_reg_cache {
@@ -336,9 +382,13 @@ struct rzg2l_pinctrl_reg_cache { · 5 unmodified lines
336 u32 *ien[2];382 u32 *ien[2];
337 u32 *pupd[2];383 u32 *pupd[2];
338 u32 *smt[2];384 u32 *smt[2];
385 u32 *sr[2];
386 u32 *nod[2];
387 u32 clone;
339 u8 sd_ch[2];388 u8 sd_ch[2];
340 u8 eth_poc[2];389 u8 eth_poc[2];
341 u8 oen;390 u8 oen;
391 u8 other_poc;
342 u8 qspi;392 u8 qspi;
343};393};
344 394
@@ -353,6 +403,8 @@ struct rzg2l_pinctrl { · 8 unmodified lines
353 403
354 struct clk *clk;404 struct clk *clk;
355 405
406 struct regmap *syscon;
407
356 struct gpio_chip gpio_chip;408 struct gpio_chip gpio_chip;
357 struct pinctrl_gpio_range gpio_range;409 struct pinctrl_gpio_range gpio_range;
358 DECLARE_BITMAP(tint_slot, RZG2L_TINT_MAX_INTERRUPT);410 DECLARE_BITMAP(tint_slot, RZG2L_TINT_MAX_INTERRUPT);
@@ -366,6 +418,7 @@ struct rzg2l_pinctrl { · 7 unmodified lines
366 struct rzg2l_pinctrl_reg_cache *cache;418 struct rzg2l_pinctrl_reg_cache *cache;
367 struct rzg2l_pinctrl_reg_cache *dedicated_cache;419 struct rzg2l_pinctrl_reg_cache *dedicated_cache;
368 atomic_t wakeup_path;420 atomic_t wakeup_path;
421 u32 clone_offset;
369};422};
370 423
371static const u16 available_ps[] = { 1800, 2500, 3300 };424static const u16 available_ps[] = { 1800, 2500, 3300 };
@@ -388,6 +441,60 @@ static u64 rzg2l_pinctrl_get_variable_pin_cfg(struct rzg2l_pinctrl *pctrl, · 16 unmodified lines
388 return 0;441 return 0;
389}442}
390 443
444static const u64 r9a08g046_variable_pin_cfg[] = {
445 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PA, 0, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0) | PIN_CFG_IEN),
446 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PA, 1, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0)),
447 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PA, 2, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0)),
448 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PA, 3, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0)),
449 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PA, 4, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0)),
450 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PA, 5, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0)),
451 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PA, 6, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0) | PIN_CFG_IEN),
452 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PA, 7, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0)),
453 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PB, 0, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0)),
454 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PB, 1, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0) | PIN_CFG_OEN),
455 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PB, 2, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0)),
456 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PB, 3, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0)),
457 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PB, 4, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0)),
458 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PB, 5, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0)),
459 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PB, 6, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0)),
460 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PB, 7, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0)),
461 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PD, 0, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1) | PIN_CFG_IEN),
462 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PD, 1, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)),
463 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PD, 2, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)),
464 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PD, 3, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)),
465 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PD, 4, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)),
466 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PD, 5, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)),
467 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PD, 6, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)),
468 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PD, 7, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)),
469 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PE, 0, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)),
470 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PE, 1, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1) | PIN_CFG_OEN),
471 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PE, 2, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)),
472 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PE, 3, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)),
473 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PE, 4, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)),
474 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PE, 5, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)),
475 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PE, 6, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)),
476 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PE, 7, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)),
477 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 0, RZG3L_MPXED_PIN_FUNCS(B)),
478 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 1, RZG3L_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN),
479 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 2, RZG3L_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN),
480 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 3, RZG3L_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN),
481 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 4, RZG3L_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN),
482 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 5, RZG3L_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN),
483 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 6, RZG3L_MPXED_PIN_FUNCS_POC(B, ISO)),
484 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 7, RZG3L_MPXED_PIN_FUNCS_POC(B, ISO)),
485 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PH, 0, RZG3L_MPXED_PIN_FUNCS(B)),
486 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PH, 1, RZG3L_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN),
487 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PH, 2, RZG3L_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN),
488 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PH, 3, RZG3L_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN),
489 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PH, 4, RZG3L_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN),
490 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PH, 5, RZG3L_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN),
491 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PJ, 0, RZG3L_MPXED_PIN_FUNCS(A) | PIN_CFG_IEN),
492 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PJ, 1, RZG3L_MPXED_PIN_FUNCS(A)),
493 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PJ, 2, RZG3L_MPXED_PIN_FUNCS(A)),
494 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PJ, 3, RZG3L_MPXED_PIN_FUNCS(A)),
495 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PJ, 4, RZG3L_MPXED_PIN_FUNCS(A)),
496};
497
391static const u64 r9a09g047_variable_pin_cfg[] = {498static const u64 r9a09g047_variable_pin_cfg[] = {
392 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 0, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),499 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 0, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
393 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 1, RZV2H_MPXED_PIN_FUNCS),500 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 1, RZV2H_MPXED_PIN_FUNCS),
@@ -537,6 +644,45 @@ static int rzg2l_validate_pin(struct rzg2l_pinctrl *pctrl, · 143 unmodified lines
537 return 0;644 return 0;
538}645}
539 646
647static int rzg2l_pinctrl_set_clone_mode(struct rzg2l_pinctrl *pctrl,
648 u8 port, u8 pin, u8 func)
649{
650 unsigned int i;
651
652 if (!pctrl->data->clone_channel_data)
653 return 0;
654
655 switch (func) {
656 case 2:
657 case 4 ... 7:
658 break;
659 default:
660 return 0;
661 }
662
663 for (i = 0; i < pctrl->data->n_clone_channel_data; i++) {
664 u32 pin_data = pctrl->data->clone_channel_data[i];
665 unsigned int pin_func_mask = FIELD_GET(RZG3L_CLONE_CHANNEL_PFC_MASK, pin_data);
666 unsigned int pin_mask = FIELD_GET(RZG3L_CLONE_CHANNEL_PIN_MASK, pin_data);
667 u32 bit, val;
668
669 if (!(pin_func_mask & BIT(func)) ||
670 FIELD_GET(RZG3L_CLONE_CHANNEL_PORT_MASK, pin_data) != port)
671 continue;
672
673 if (!(pin_mask & BIT(pin)))
674 continue;
675
676 bit = FIELD_GET(RZG3L_CLONE_CHANNEL_BIT_MASK, pin_data);
677 val = FIELD_GET(RZG3L_CLONE_CHANNEL_VAL_MASK, pin_data);
678
679 return regmap_update_bits(pctrl->syscon, pctrl->clone_offset,
680 BIT(bit), val << bit);
681 }
682
683 return 0;
684}
685
540static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pinctrl *pctrl,686static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pinctrl *pctrl,
541 u8 pin, u8 off, u8 func)687 u8 pin, u8 off, u8 func)
542{688{
@@ -601,16 +747,22 @@ static int rzg2l_pinctrl_set_mux(struct pinctrl_dev *pctldev, · 58 unmodified lines
601 for (i = 0; i < group->grp.npins; i++) {747 for (i = 0; i < group->grp.npins; i++) {
602 u64 *pin_data = pctrl->desc.pins[pins[i]].drv_data;748 u64 *pin_data = pctrl->desc.pins[pins[i]].drv_data;
603 u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data);749 u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data);
750 u32 port = RZG2L_PIN_ID_TO_PORT(pins[i]);
604 u32 pin = RZG2L_PIN_ID_TO_PIN(pins[i]);751 u32 pin = RZG2L_PIN_ID_TO_PIN(pins[i]);
752 unsigned int func;
605 753
606 ret = rzg2l_validate_pin(pctrl, *pin_data, RZG2L_PIN_ID_TO_PORT(pins[i]), pin);754 ret = rzg2l_validate_pin(pctrl, *pin_data, port, pin);
607 if (ret)755 if (ret)
608 return ret;756 return ret;
609 757
610 dev_dbg(pctrl->dev, "port:%u pin: %u off:%x PSEL:%u\n",758 func = psel_val[i] - hwcfg->func_base;
611 RZG2L_PIN_ID_TO_PORT(pins[i]), pin, off, psel_val[i] - hwcfg->func_base);759 dev_dbg(pctrl->dev, "port:%u pin: %u off:%x PSEL:%u\n", port, pin, off, func);
760
761 ret = rzg2l_pinctrl_set_clone_mode(pctrl, port, pin, func);
762 if (ret)
763 return ret;
612 764
613 rzg2l_pinctrl_set_pfc_mode(pctrl, pin, off, psel_val[i] - hwcfg->func_base);765 rzg2l_pinctrl_set_pfc_mode(pctrl, pin, off, func);
614 }766 }
615 767
616 return 0;768 return 0;
@@ -894,7 +1046,8 @@ static void rzg2l_rmw_pin_config(struct rzg2l_pinctrl *pctrl, u32 offset, · 277 unmodified lines
894 raw_spin_unlock_irqrestore(&pctrl->lock, flags);1046 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
895}1047}
896 1048
897static int rzg2l_caps_to_pwr_reg(const struct rzg2l_register_offsets *regs, u32 caps)1049static int rzg2l_caps_to_pwr_reg(const struct rzg2l_register_offsets *regs,
1050 u32 caps, u8 *mask)
898{1051{
899 if (caps & PIN_CFG_IO_VMC_SD0)1052 if (caps & PIN_CFG_IO_VMC_SD0)
900 return SD_CH(regs->sd_ch, 0);1053 return SD_CH(regs->sd_ch, 0);
@@ -906,6 +1059,16 @@ static int rzg2l_caps_to_pwr_reg(const struct rzg2l_register_offsets *regs, u32 · 5 unmodified lines
906 return ETH_POC(regs->eth_poc, 1);1059 return ETH_POC(regs->eth_poc, 1);
907 if (caps & PIN_CFG_IO_VMC_QSPI)1060 if (caps & PIN_CFG_IO_VMC_QSPI)
908 return QSPI;1061 return QSPI;
1062 if (caps & PIN_CFG_OTHER_POC_MASK) {
1063 if (caps & PIN_CFG_PVDD1833_OTH_AWO_POC)
1064 *mask = BIT(0);
1065 else if (caps & PIN_CFG_PVDD1833_OTH_ISO_POC)
1066 *mask = BIT(1);
1067 else
1068 *mask = BIT(2);
1069
1070 return OTHER_POC;
1071 }
909 1072
910 return -EINVAL;1073 return -EINVAL;
911}1074}
@@ -914,17 +1077,20 @@ static int rzg2l_get_power_source(struct rzg2l_pinctrl *pctrl, u32 pin, u32 caps · 2 unmodified lines
914{1077{
915 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;1078 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;
916 const struct rzg2l_register_offsets *regs = &hwcfg->regs;1079 const struct rzg2l_register_offsets *regs = &hwcfg->regs;
1080 u8 val, mask;
917 int pwr_reg;1081 int pwr_reg;
918 u8 val;
919 1082
920 if (caps & PIN_CFG_SOFT_PS)1083 if (caps & PIN_CFG_SOFT_PS)
921 return pctrl->settings[pin].power_source;1084 return pctrl->settings[pin].power_source;
922 1085
923 pwr_reg = rzg2l_caps_to_pwr_reg(regs, caps);1086 pwr_reg = rzg2l_caps_to_pwr_reg(regs, caps, &mask);
924 if (pwr_reg < 0)1087 if (pwr_reg < 0)
925 return pwr_reg;1088 return pwr_reg;
926 1089
927 val = readb(pctrl->base + pwr_reg);1090 val = readb(pctrl->base + pwr_reg);
1091 if (pwr_reg == OTHER_POC)
1092 val = field_get(mask, val);
1093
928 switch (val) {1094 switch (val) {
929 case PVDD_1800:1095 case PVDD_1800:
930 return 1800;1096 return 1800;
@@ -942,8 +1108,8 @@ static int rzg2l_set_power_source(struct rzg2l_pinctrl *pctrl, u32 pin, u32 caps · 11 unmodified lines
942{1108{
943 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;1109 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;
944 const struct rzg2l_register_offsets *regs = &hwcfg->regs;1110 const struct rzg2l_register_offsets *regs = &hwcfg->regs;
1111 u8 poc_val, val, mask;
945 int pwr_reg;1112 int pwr_reg;
946 u8 val;
947 1113
948 if (caps & PIN_CFG_SOFT_PS) {1114 if (caps & PIN_CFG_SOFT_PS) {
949 pctrl->settings[pin].power_source = ps;1115 pctrl->settings[pin].power_source = ps;
@@ -952,25 +1118,37 @@ static int rzg2l_set_power_source(struct rzg2l_pinctrl *pctrl, u32 pin, u32 caps · 2 unmodified lines
952 1118
953 switch (ps) {1119 switch (ps) {
954 case 1800:1120 case 1800:
955 val = PVDD_1800;1121 poc_val = PVDD_1800;
956 break;1122 break;
957 case 2500:1123 case 2500:
958 if (!(caps & (PIN_CFG_IO_VMC_ETH0 | PIN_CFG_IO_VMC_ETH1)))1124 if (!(caps & (PIN_CFG_IO_VMC_ETH0 | PIN_CFG_IO_VMC_ETH1)))
959 return -EINVAL;1125 return -EINVAL;
960 val = PVDD_2500;1126 poc_val = PVDD_2500;
961 break;1127 break;
962 case 3300:1128 case 3300:
963 val = PVDD_3300;1129 poc_val = PVDD_3300;
964 break;1130 break;
965 default:1131 default:
966 return -EINVAL;1132 return -EINVAL;
967 }1133 }
968 1134
969 pwr_reg = rzg2l_caps_to_pwr_reg(regs, caps);1135 pwr_reg = rzg2l_caps_to_pwr_reg(regs, caps, &mask);
970 if (pwr_reg < 0)1136 if (pwr_reg < 0)
971 return pwr_reg;1137 return pwr_reg;
972 1138
973 writeb(val, pctrl->base + pwr_reg);1139 if (pwr_reg == OTHER_POC) {
1140 scoped_guard(raw_spinlock_irqsave, &pctrl->lock) {
1141 val = readb(pctrl->base + pwr_reg);
1142 if (poc_val)
1143 val |= mask;
1144 else
1145 val &= ~mask;
1146 writeb(val, pctrl->base + pwr_reg);
1147 }
1148 } else {
1149 writeb(poc_val, pctrl->base + pwr_reg);
1150 }
1151
974 pctrl->settings[pin].power_source = ps;1152 pctrl->settings[pin].power_source = ps;
975 1153
976 return 0;1154 return 0;
@@ -1083,7 +1261,7 @@ static int rzg2l_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int _pin) · 106 unmodified lines
1083 u64 caps = FIELD_GET(PIN_CFG_MASK, *pin_data);1261 u64 caps = FIELD_GET(PIN_CFG_MASK, *pin_data);
1084 u8 pin = RZG2L_PIN_ID_TO_PIN(_pin);1262 u8 pin = RZG2L_PIN_ID_TO_PIN(_pin);
1085 1263
1086 if (pin > pctrl->data->hwcfg->oen_max_pin)1264 if (pin != pctrl->data->hwcfg->oen_max_pin)
1087 return -EINVAL;1265 return -EINVAL;
1088 1266
1089 /*1267 /*
@@ -1103,7 +1281,7 @@ static int rzg2l_read_oen(struct rzg2l_pinctrl *pctrl, unsigned int _pin) · 13 unmodified lines
1103 int bit;1281 int bit;
1104 1282
1105 if (!pctrl->data->pin_to_oen_bit)1283 if (!pctrl->data->pin_to_oen_bit)
1106 return -EOPNOTSUPP;1284 return -ENOTSUPP;
1107 1285
1108 bit = pctrl->data->pin_to_oen_bit(pctrl, _pin);1286 bit = pctrl->data->pin_to_oen_bit(pctrl, _pin);
1109 if (bit < 0)1287 if (bit < 0)
@@ -1145,7 +1323,7 @@ static int rzg2l_write_oen(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oe · 35 unmodified lines
1145 u8 val;1323 u8 val;
1146 1324
1147 if (!pctrl->data->pin_to_oen_bit)1325 if (!pctrl->data->pin_to_oen_bit)
1148 return -EOPNOTSUPP;1326 return -ENOTSUPP;
1149 1327
1150 bit = pctrl->data->pin_to_oen_bit(pctrl, _pin);1328 bit = pctrl->data->pin_to_oen_bit(pctrl, _pin);
1151 if (bit < 0)1329 if (bit < 0)
@@ -1576,7 +1754,7 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, · 424 unmodified lines
1576 break;1754 break;
1577 1755
1578 default:1756 default:
1579 return -EOPNOTSUPP;1757 return -ENOTSUPP;
1580 }1758 }
1581 }1759 }
1582 1760
@@ -1643,8 +1821,9 @@ static int rzg2l_pinctrl_pinconf_group_get(struct pinctrl_dev *pctldev, · 60 unmodified lines
1643 unsigned int group,1821 unsigned int group,
1644 unsigned long *config)1822 unsigned long *config)
1645{1823{
1824 unsigned long prev_config = 0;
1646 const unsigned int *pins;1825 const unsigned int *pins;
1647 unsigned int i, npins, prev_config = 0;1826 unsigned int i, npins;
1648 int ret;1827 int ret;
1649 1828
1650 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);1829 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
@@ -1658,7 +1837,7 @@ static int rzg2l_pinctrl_pinconf_group_get(struct pinctrl_dev *pctldev, · 7 unmodified lines
1658 1837
1659 /* Check config matching between to pin */1838 /* Check config matching between to pin */
1660 if (i && prev_config != *config)1839 if (i && prev_config != *config)
1661 return -EOPNOTSUPP;1840 return -ENOTSUPP;
1662 1841
1663 prev_config = *config;1842 prev_config = *config;
1664 }1843 }
@@ -2089,6 +2268,70 @@ static const u64 r9a09g047_gpio_configs[] = { · 424 unmodified lines
2089 RZG2L_GPIO_PORT_PACK(4, 0x3c, RZV2H_MPXED_PIN_FUNCS), /* PS */2268 RZG2L_GPIO_PORT_PACK(4, 0x3c, RZV2H_MPXED_PIN_FUNCS), /* PS */
2090};2269};
2091 2270
2271static const char * const rzg3l_gpio_names[] = {
2272 "", "", "", "", "", "", "", "",
2273 "", "", "", "", "", "", "", "",
2274 "P20", "P21", "P22", "P23", "P24", "P25", "P26", "P27",
2275 "P30", "P31", "P32", "P33", "P34", "P35", "P36", "P37",
2276 "", "", "", "", "", "", "", "",
2277 "P50", "P51", "P52", "P53", "P54", "P55", "P56", "P57",
2278 "P60", "P61", "P62", "P63", "P64", "P65", "P66", "P67",
2279 "P70", "P71", "P72", "P73", "P74", "P75", "P76", "P77",
2280 "P80", "P81", "P82", "P83", "P84", "P85", "P86", "P87",
2281 "", "", "", "", "", "", "", "",
2282 "PA0", "PA1", "PA2", "PA3", "PA4", "PA5", "PA6", "PA7",
2283 "PB0", "PB1", "PB2", "PB3", "PB4", "PB5", "PB6", "PB7",
2284 "PC0", "PC1", "PC2", "PC3", "PC4", "PC5", "PC6", "PC7",
2285 "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", "PD6", "PD7",
2286 "PE0", "PE1", "PE2", "PE3", "PE4", "PE5", "PE6", "PE7",
2287 "PF0", "PF1", "PF2", "PF3", "PF4", "PF5", "PF6", "PF7",
2288 "PG0", "PG1", "PG2", "PG3", "PG4", "PG5", "PG6", "PG7",
2289 "PH0", "PH1", "PH2", "PH3", "PH4", "PH5", "PH6", "PH7",
2290 "", "", "", "", "", "", "", "",
2291 "PJ0", "PJ1", "PJ2", "PJ3", "PJ4", "PJ5", "PJ6", "PJ7",
2292 "PK0", "PK1", "PK2", "PK3", "PK4", "PK5", "PK6", "PK7",
2293 "PL0", "PL1", "PL2", "PL3", "PL4", "PL5", "PL6", "PL7",
2294 "PM0", "PM1", "PM2", "PM3", "PM4", "PM5", "PM6", "PM7",
2295 "", "", "", "", "", "", "", "",
2296 "", "", "", "", "", "", "", "",
2297 "", "", "", "", "", "", "", "",
2298 "", "", "", "", "", "", "", "",
2299 "", "", "", "", "", "", "", "",
2300 "PS0", "PS1", "PS2", "PS3", "PS4", "PS5", "PS6", "PS7",
2301};
2302
2303static const u64 r9a08g046_gpio_configs[] = {
2304 0x0,
2305 0x0,
2306 RZG2L_GPIO_PORT_PACK(2, 0x22, PIN_CFG_NF | PIN_CFG_IEN), /* P2 */
2307 RZG2L_GPIO_PORT_PACK(7, 0x23, RZG3L_MPXED_PIN_FUNCS_POC(A, AWO)), /* P3 */
2308 0x0,
2309 RZG2L_GPIO_PORT_PACK(7, 0x25, RZG3L_MPXED_PIN_FUNCS_POC(A, ISO)), /* P5 */
2310 RZG2L_GPIO_PORT_PACK(7, 0x26, RZG3L_MPXED_PIN_FUNCS_POC(A, ISO)), /* P6 */
2311 RZG2L_GPIO_PORT_PACK(8, 0x27, RZG3L_MPXED_PIN_FUNCS_POC(A, ISO)), /* P7 */
2312 RZG2L_GPIO_PORT_PACK(6, 0x28, RZG3L_MPXED_PIN_FUNCS_POC(A, ISO)), /* P8 */
2313 0x0,
2314 RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x2a), /* PA */
2315 RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x2b), /* PB */
2316 RZG2L_GPIO_PORT_PACK(3, 0x2c, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0)), /* PC */
2317 RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x2d), /* PD */
2318 RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x2e), /* PE */
2319 RZG2L_GPIO_PORT_PACK(3, 0x2f, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)), /* PF */
2320 RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x30), /* PG */
2321 RZG2L_GPIO_PORT_PACK_VARIABLE(6, 0x31), /* PH */
2322 0x0,
2323 RZG2L_GPIO_PORT_PACK_VARIABLE(5, 0x33), /* PJ */
2324 RZG2L_GPIO_PORT_PACK(4, 0x34, RZG3L_MPXED_PIN_FUNCS_POC(B, ISO)), /* PK */
2325 RZG2L_GPIO_PORT_PACK(5, 0x35, RZG3L_MPXED_PIN_FUNCS(C)), /* PL */
2326 RZG2L_GPIO_PORT_PACK(8, 0x36, RZG3L_MPXED_PIN_FUNCS(C)), /* PM */
2327 0x0,
2328 0x0,
2329 0x0,
2330 0x0,
2331 0x0,
2332 RZG2L_GPIO_PORT_PACK(2, 0x3c, RZG3L_MPXED_PIN_FUNCS(A)), /* PS */
2333};
2334
2092static const char * const rzv2h_gpio_names[] = {2335static const char * const rzv2h_gpio_names[] = {
2093 "P00", "P01", "P02", "P03", "P04", "P05", "P06", "P07",2336 "P00", "P01", "P02", "P03", "P04", "P05", "P06", "P07",
2094 "P10", "P11", "P12", "P13", "P14", "P15", "P16", "P17",2337 "P10", "P11", "P12", "P13", "P14", "P15", "P16", "P17",
@@ -2427,6 +2670,128 @@ static struct rzg2l_dedicated_configs rzg3e_dedicated_pins[] = { · 332 unmodified lines
2427 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) },2670 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) },
2428};2671};
2429 2672
2673static const struct rzg2l_dedicated_configs rzg3l_dedicated_pins[] = {
2674 { "WDTOVF_N", RZG2L_SINGLE_PIN_PACK(0x5, 0,
2675 (PIN_CFG_IOLH_A | PIN_CFG_WDTOVF_N_POC)) },
2676 { "SCIF0_RXD", RZG2L_SINGLE_PIN_PACK(0x6, 0,
2677 (PIN_CFG_IOLH_A | PIN_CFG_PUPD | PIN_CFG_PVDD1833_OTH_AWO_POC)) },
2678 { "SCIF0_TXD", RZG2L_SINGLE_PIN_PACK(0x6, 1,
2679 (PIN_CFG_IOLH_A | PIN_CFG_PUPD | PIN_CFG_PVDD1833_OTH_AWO_POC)) },
2680 { "SD0_CLK", RZG2L_SINGLE_PIN_PACK(0x9, 0, PIN_CFG_IOLH_B) },
2681 { "SD0_CMD", RZG2L_SINGLE_PIN_PACK(0x9, 1,
2682 (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD)) },
2683 { "SD0_RST#", RZG2L_SINGLE_PIN_PACK(0x9, 2, PIN_CFG_IOLH_B) },
2684 { "SD0_DS", RZG2L_SINGLE_PIN_PACK(0x9, 5,
2685 (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD)) },
2686 { "SD0_DAT0", RZG2L_SINGLE_PIN_PACK(0x0a, 0,
2687 (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD)) },
2688 { "SD0_DAT1", RZG2L_SINGLE_PIN_PACK(0x0a, 1,
2689 (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD)) },
2690 { "SD0_DAT2", RZG2L_SINGLE_PIN_PACK(0x0a, 2,
2691 (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD)) },
2692 { "SD0_DAT3", RZG2L_SINGLE_PIN_PACK(0x0a, 3,
2693 (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD)) },
2694 { "SD0_DAT4", RZG2L_SINGLE_PIN_PACK(0x0a, 4,
2695 (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD)) },
2696 { "SD0_DAT5", RZG2L_SINGLE_PIN_PACK(0x0a, 5,
2697 (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD)) },
2698 { "SD0_DAT6", RZG2L_SINGLE_PIN_PACK(0x0a, 6,
2699 (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD)) },
2700 { "SD0_DAT7", RZG2L_SINGLE_PIN_PACK(0x0a, 7,
2701 (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD)) },
2702};
2703
2704static const u32 r9a08g046_clone_channel_data[] = {
2705 /* I2C ch2 Bit:0 Value:0 PFC:4 */
2706 RZG3L_CLONE_CHANNEL_DATA(RZG3L_PG, GENMASK(7, 6), 0, 0, BIT(4)),
2707 RZG3L_CLONE_CHANNEL_DATA(RZG3L_PH, GENMASK(3, 2), 0, 0, BIT(4)),
2708 RZG3L_CLONE_CHANNEL_DATA(RZG3L_PK, GENMASK(1, 0), 0, 0, BIT(4)),
2709 RZG3L_CLONE_CHANNEL_DATA(RZG3L_PA, GENMASK(5, 4) | GENMASK(1, 0), 0, 0, BIT(4)),
2710 RZG3L_CLONE_CHANNEL_DATA(RZG3L_PB, GENMASK(5, 4) | GENMASK(1, 0), 0, 0, BIT(4)),
2711 RZG3L_CLONE_CHANNEL_DATA(RZG3L_PC, GENMASK(1, 0), 0, 0, BIT(4)),
2712 RZG3L_CLONE_CHANNEL_DATA(RZG3L_PD, GENMASK(7, 6) | GENMASK(3, 2), 0, 0, BIT(4)),
2713 RZG3L_CLONE_CHANNEL_DATA(RZG3L_PE, GENMASK(7, 6) | GENMASK(3, 2), 0, 0, BIT(4)),
2714 /* I2C ch2 Bit:0 Value:1 PFC:4 */
2715 RZG3L_CLONE_CHANNEL_DATA(RZG3L_P5, GENMASK(5, 4) | GENMASK(1, 0), 0, 1, BIT(4)),
2716 RZG3L_CLONE_CHANNEL_DATA(RZG3L_P6, GENMASK(6, 5) | GENMASK(2, 1), 0, 1, BIT(4)),
2717 RZG3L_CLONE_CHANNEL_DATA(RZG3L_P8, GENMASK(5, 4) | GENMASK(1, 0), 0, 1, BIT(4)),
2718 /* I2C ch3 Bit:1 Value:0 PFC:4 */
2719 RZG3L_CLONE_CHANNEL_DATA(RZG3L_PF, GENMASK(1, 0), 1, 0, BIT(4)),
2720 /* I2C ch3 Bit:1 Value:1 PFC:4 */
2721 RZG3L_CLONE_CHANNEL_DATA(RZG3L_P2, GENMASK(1, 0), 1, 1, BIT(4)),
2722 RZG3L_CLONE_CHANNEL_DATA(RZG3L_P5, BIT(6) | GENMASK(3, 2), 1, 1, BIT(4)),
2723 RZG3L_CLONE_CHANNEL_DATA(RZG3L_P6, GENMASK(4, 3) | BIT(0), 1, 1, BIT(4)),
2724 RZG3L_CLONE_CHANNEL_DATA(RZG3L_P7, GENMASK(7, 6), 1, 1, BIT(4)),
2725 RZG3L_CLONE_CHANNEL_DATA(RZG3L_P8, GENMASK(3, 2), 1, 1, BIT(4)),
2726 /* SCIF ch3 Bit:4 Value:0 PFC:{6,7} */
2727 RZG3L_CLONE_CHANNEL_DATA(RZG3L_PG, GENMASK(6, 4), 4, 0, BIT(6)),
2728 RZG3L_CLONE_CHANNEL_DATA(RZG3L_PH, GENMASK(5, 3), 4, 0, BIT(7)),
2729 RZG3L_CLONE_CHANNEL_DATA(RZG3L_PA, GENMASK(4, 2), 4, 0, BIT(7)),
2730 RZG3L_CLONE_CHANNEL_DATA(RZG3L_PB, GENMASK(5, 3), 4, 0, BIT(7)),
2731 RZG3L_CLONE_CHANNEL_DATA(RZG3L_PD, GENMASK(2, 0), 4, 0, BIT(7)),
2732 RZG3L_CLONE_CHANNEL_DATA(RZG3L_PE, GENMASK(3, 1), 4, 0, BIT(7)),
2733 /* SCIF ch3 Bit:4 Value:1 PFC:7 */
2734 RZG3L_CLONE_CHANNEL_DATA(RZG3L_P5, GENMASK(2, 0), 4, 1, BIT(7)),
2735 /* SCIF ch4 Bit:5 Value:0 PFC:7 */
2736 RZG3L_CLONE_CHANNEL_DATA(RZG3L_PK, GENMASK(2, 0), 5, 0, BIT(7)),
2737 RZG3L_CLONE_CHANNEL_DATA(RZG3L_PA, GENMASK(7, 5), 5, 0, BIT(7)),
2738 RZG3L_CLONE_CHANNEL_DATA(RZG3L_PB, GENMASK(7, 6), 5, 0, BIT(7)),
2739 RZG3L_CLONE_CHANNEL_DATA(RZG3L_PC, BIT(0), 5, 0, BIT(7)),
2740 RZG3L_CLONE_CHANNEL_DATA(RZG3L_PD, GENMASK(5, 3), 5, 0, BIT(7)),
2741 RZG3L_CLONE_CHANNEL_DATA(RZG3L_PE, GENMASK(6, 4), 5, 0, BIT(7)),
2742 /* SCIF ch4 Bit:5 Value:1 PFC:7 */
2743 RZG3L_CLONE_CHANNEL_DATA(RZG3L_P5, GENMASK(5, 3), 5, 1, BIT(7)),
2744 RZG3L_CLONE_CHANNEL_DATA(RZG3L_P6, GENMASK(4, 2), 5, 1, BIT(7)),
2745 RZG3L_CLONE_CHANNEL_DATA(RZG3L_P7, GENMASK(7, 5), 5, 1, BIT(7)),
2746 /* SCIF ch5 Bit:6 Value:0 PFC:7 */
2747 RZG3L_CLONE_CHANNEL_DATA(RZG3L_PE, BIT(7), 6, 0, BIT(7)),
2748 RZG3L_CLONE_CHANNEL_DATA(RZG3L_PF, GENMASK(1, 0), 6, 0, BIT(7)),
2749 /* SCIF ch5 Bit:6 Value:1 PFC:7 */
2750 RZG3L_CLONE_CHANNEL_DATA(RZG3L_P5, BIT(6), 6, 1, BIT(7)),
2751 RZG3L_CLONE_CHANNEL_DATA(RZG3L_P6, GENMASK(6, 5) | GENMASK(1, 0), 6, 1, BIT(7)),
2752 RZG3L_CLONE_CHANNEL_DATA(RZG3L_P7, GENMASK(4, 2) | BIT(0), 6, 1, BIT(7)),
2753 RZG3L_CLONE_CHANNEL_DATA(RZG3L_P8, GENMASK(2, 0), 6, 1, BIT(7)),
2754 /* RSPI ch1 Bit:8 Value:0 PFC:2 */
2755 RZG3L_CLONE_CHANNEL_DATA(RZG3L_PH, GENMASK(5, 0), 8, 0, BIT(2)),
2756 RZG3L_CLONE_CHANNEL_DATA(RZG3L_PD, GENMASK(7, 5), 8, 0, BIT(2)),
2757 RZG3L_CLONE_CHANNEL_DATA(RZG3L_PE, GENMASK(3, 0), 8, 0, BIT(2)),
2758 /* RSPI ch1 Bit:8 Value:1 PFC:2 */
2759 RZG3L_CLONE_CHANNEL_DATA(RZG3L_P5, GENMASK(6, 0), 8, 1, BIT(2)),
2760 /* RSPI ch2 Bit:9 Value:0 PFC:2 */
2761 RZG3L_CLONE_CHANNEL_DATA(RZG3L_PE, GENMASK(7, 4), 9, 0, BIT(2)),
2762 RZG3L_CLONE_CHANNEL_DATA(RZG3L_PF, GENMASK(2, 0), 9, 0, BIT(2)),
2763 /* RSPI ch2 Bit:9 Value:1 PFC:2 */
2764 RZG3L_CLONE_CHANNEL_DATA(RZG3L_P6, GENMASK(6, 0), 9, 1, BIT(2)),
2765 RZG3L_CLONE_CHANNEL_DATA(RZG3L_P7, BIT(7), 9, 1, BIT(2)),
2766 RZG3L_CLONE_CHANNEL_DATA(RZG3L_P8, GENMASK(5, 0), 9, 1, BIT(2)),
2767 /* RSCI ch1 Bit:12 Value:0 PFC:{5,6} shared pins based on RSCI mode */
2768 RZG3L_CLONE_CHANNEL_DATA(RZG3L_PG, GENMASK(3, 0), 12, 0, GENMASK(6, 5)),
2769 RZG3L_CLONE_CHANNEL_DATA(RZG3L_PA, GENMASK(3, 0), 12, 0, GENMASK(6, 5)),
2770 RZG3L_CLONE_CHANNEL_DATA(RZG3L_PB, GENMASK(7, 6), 12, 0, GENMASK(6, 5)),
2771 RZG3L_CLONE_CHANNEL_DATA(RZG3L_PC, GENMASK(1, 0), 12, 0, GENMASK(6, 5)),
2772 RZG3L_CLONE_CHANNEL_DATA(RZG3L_PD, GENMASK(7, 4), 12, 0, GENMASK(6, 5)),
2773 /* RSCI ch1 Bit:12 Value:1 PFC:{5,6} shared pins based on RSCI mode */
2774 RZG3L_CLONE_CHANNEL_DATA(RZG3L_P5, GENMASK(3, 0), 12, 1, GENMASK(6, 5)),
2775 /* RSCI ch2 Bit:13 Value:0 PFC:{5,6} shared pins based on RSCI mode */
2776 RZG3L_CLONE_CHANNEL_DATA(RZG3L_PH, GENMASK(3, 0), 13, 0, GENMASK(6, 5)),
2777 RZG3L_CLONE_CHANNEL_DATA(RZG3L_PK, GENMASK(3, 0), 13, 0, GENMASK(6, 5)),
2778 RZG3L_CLONE_CHANNEL_DATA(RZG3L_PA, GENMASK(7, 4), 13, 0, GENMASK(6, 5)),
2779 RZG3L_CLONE_CHANNEL_DATA(RZG3L_PD, GENMASK(3, 0), 13, 0, GENMASK(6, 5)),
2780 RZG3L_CLONE_CHANNEL_DATA(RZG3L_PE, GENMASK(3, 0), 13, 0, GENMASK(6, 5)),
2781 /* RSCI ch2 Bit:13 Value:1 PFC:{5,6} shared pins based on RSCI mode */
2782 RZG3L_CLONE_CHANNEL_DATA(RZG3L_P5, GENMASK(6, 4), 13, 1, GENMASK(6, 5)),
2783 RZG3L_CLONE_CHANNEL_DATA(RZG3L_P6, GENMASK(6, 5) | BIT(0), 13, 1, GENMASK(6, 5)),
2784 RZG3L_CLONE_CHANNEL_DATA(RZG3L_P7, GENMASK(7, 6) | GENMASK(1, 0), 13, 1, GENMASK(6, 5)),
2785 RZG3L_CLONE_CHANNEL_DATA(RZG3L_P8, GENMASK(1, 0), 13, 1, GENMASK(6, 5)),
2786 /* RSCI ch3 Bit:14 Value:0 PFC:{5,6} shared pins based on RSCI mode */
2787 RZG3L_CLONE_CHANNEL_DATA(RZG3L_PE, GENMASK(7, 6), 14, 0, GENMASK(6, 5)),
2788 RZG3L_CLONE_CHANNEL_DATA(RZG3L_PF, GENMASK(1, 0), 14, 0, GENMASK(6, 5)),
2789 /* RSCI ch3 Bit:14 Value:1 PFC:{5,6} shared pins based on RSCI mode */
2790 RZG3L_CLONE_CHANNEL_DATA(RZG3L_P6, GENMASK(4, 1), 14, 1, GENMASK(6, 5)),
2791 RZG3L_CLONE_CHANNEL_DATA(RZG3L_P7, GENMASK(5, 2), 14, 1, GENMASK(6, 5)),
2792 RZG3L_CLONE_CHANNEL_DATA(RZG3L_P8, GENMASK(5, 2), 14, 1, GENMASK(6, 5)),
2793};
2794
2430static int rzg2l_gpio_get_gpioint(unsigned int virq, struct rzg2l_pinctrl *pctrl)2795static int rzg2l_gpio_get_gpioint(unsigned int virq, struct rzg2l_pinctrl *pctrl)
2431{2796{
2432 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[virq];2797 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[virq];
@@ -2760,6 +3125,16 @@ static int rzg2l_pinctrl_reg_cache_alloc(struct rzg2l_pinctrl *pctrl) · 327 unmodified lines
2760 if (!cache->smt[i])3125 if (!cache->smt[i])
2761 return -ENOMEM;3126 return -ENOMEM;
2762 3127
3128 cache->sr[i] = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->sr[i]),
3129 GFP_KERNEL);
3130 if (!cache->sr[i])
3131 return -ENOMEM;
3132
3133 cache->nod[i] = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->nod[i]),
3134 GFP_KERNEL);
3135 if (!cache->nod[i])
3136 return -ENOMEM;
3137
2763 /* Allocate dedicated cache. */3138 /* Allocate dedicated cache. */
2764 dedicated_cache->iolh[i] = devm_kcalloc(pctrl->dev, n_dedicated_pins,3139 dedicated_cache->iolh[i] = devm_kcalloc(pctrl->dev, n_dedicated_pins,
2765 sizeof(*dedicated_cache->iolh[i]),3140 sizeof(*dedicated_cache->iolh[i]),
@@ -2772,6 +3147,24 @@ static int rzg2l_pinctrl_reg_cache_alloc(struct rzg2l_pinctrl *pctrl) · 6 unmodified lines
2772 GFP_KERNEL);3147 GFP_KERNEL);
2773 if (!dedicated_cache->ien[i])3148 if (!dedicated_cache->ien[i])
2774 return -ENOMEM;3149 return -ENOMEM;
3150
3151 dedicated_cache->sr[i] = devm_kcalloc(pctrl->dev, n_dedicated_pins,
3152 sizeof(*dedicated_cache->sr[i]),
3153 GFP_KERNEL);
3154 if (!dedicated_cache->sr[i])
3155 return -ENOMEM;
3156
3157 dedicated_cache->nod[i] = devm_kcalloc(pctrl->dev, n_dedicated_pins,
3158 sizeof(*dedicated_cache->nod[i]),
3159 GFP_KERNEL);
3160 if (!dedicated_cache->nod[i])
3161 return -ENOMEM;
3162
3163 dedicated_cache->pupd[i] = devm_kcalloc(pctrl->dev, n_dedicated_pins,
3164 sizeof(*dedicated_cache->pupd[i]),
3165 GFP_KERNEL);
3166 if (!dedicated_cache->pupd[i])
3167 return -ENOMEM;
2775 }3168 }
2776 3169
2777 pctrl->cache = cache;3170 pctrl->cache = cache;
@@ -2819,6 +3212,7 @@ static int rzg2l_gpio_register(struct rzg2l_pinctrl *pctrl) · 41 unmodified lines
2819 chip->direction_output = rzg2l_gpio_direction_output;3212 chip->direction_output = rzg2l_gpio_direction_output;
2820 chip->get = rzg2l_gpio_get;3213 chip->get = rzg2l_gpio_get;
2821 chip->set = rzg2l_gpio_set;3214 chip->set = rzg2l_gpio_set;
3215 chip->set_config = gpiochip_generic_config;
2822 chip->label = name;3216 chip->label = name;
2823 chip->parent = pctrl->dev;3217 chip->parent = pctrl->dev;
2824 chip->owner = THIS_MODULE;3218 chip->owner = THIS_MODULE;
@@ -2956,6 +3350,9 @@ static int rzg2l_pinctrl_probe(struct platform_device *pdev) · 131 unmodified lines
2956 BUILD_BUG_ON(ARRAY_SIZE(r9a08g045_gpio_configs) * RZG2L_PINS_PER_PORT >3350 BUILD_BUG_ON(ARRAY_SIZE(r9a08g045_gpio_configs) * RZG2L_PINS_PER_PORT >
2957 ARRAY_SIZE(rzg2l_gpio_names));3351 ARRAY_SIZE(rzg2l_gpio_names));
2958 3352
3353 BUILD_BUG_ON(ARRAY_SIZE(r9a08g046_gpio_configs) * RZG2L_PINS_PER_PORT >
3354 ARRAY_SIZE(rzg3l_gpio_names));
3355
2959 BUILD_BUG_ON(ARRAY_SIZE(r9a09g047_gpio_configs) * RZG2L_PINS_PER_PORT >3356 BUILD_BUG_ON(ARRAY_SIZE(r9a09g047_gpio_configs) * RZG2L_PINS_PER_PORT >
2960 ARRAY_SIZE(rzg3e_gpio_names));3357 ARRAY_SIZE(rzg3e_gpio_names));
2961 3358
@@ -2982,6 +3379,16 @@ static int rzg2l_pinctrl_probe(struct platform_device *pdev) · 20 unmodified lines
2982 "failed to enable GPIO clk\n");3379 "failed to enable GPIO clk\n");
2983 }3380 }
2984 3381
3382 if (pctrl->data->clone_channel_data) {
3383 struct device_node *np = pctrl->dev->of_node;
3384
3385 pctrl->syscon = syscon_regmap_lookup_by_phandle_args(np, "renesas,clonech",
3386 1, &pctrl->clone_offset);
3387 if (IS_ERR(pctrl->syscon))
3388 return dev_err_probe(pctrl->dev, PTR_ERR(pctrl->syscon),
3389 "Failed to parse renesas,clonech\n");
3390 }
3391
2985 raw_spin_lock_init(&pctrl->lock);3392 raw_spin_lock_init(&pctrl->lock);
2986 spin_lock_init(&pctrl->bitmap_lock);3393 spin_lock_init(&pctrl->bitmap_lock);
2987 mutex_init(&pctrl->mutex);3394 mutex_init(&pctrl->mutex);
@@ -3003,7 +3410,7 @@ static void rzg2l_pinctrl_pm_setup_regs(struct rzg2l_pinctrl *pctrl, bool suspen · 15 unmodified lines
3003 struct rzg2l_pinctrl_reg_cache *cache = pctrl->cache;3410 struct rzg2l_pinctrl_reg_cache *cache = pctrl->cache;
3004 3411
3005 for (u32 port = 0; port < nports; port++) {3412 for (u32 port = 0; port < nports; port++) {
3006 bool has_iolh, has_ien, has_pupd, has_smt;3413 bool has_iolh, has_ien, has_pupd, has_smt, has_sr, has_nod;
3007 u32 off, caps;3414 u32 off, caps;
3008 u8 pincnt;3415 u8 pincnt;
3009 u64 cfg;3416 u64 cfg;
@@ -3024,6 +3431,8 @@ static void rzg2l_pinctrl_pm_setup_regs(struct rzg2l_pinctrl *pctrl, bool suspen · 14 unmodified lines
3024 has_ien = !!(caps & PIN_CFG_IEN);3431 has_ien = !!(caps & PIN_CFG_IEN);
3025 has_pupd = !!(caps & PIN_CFG_PUPD);3432 has_pupd = !!(caps & PIN_CFG_PUPD);
3026 has_smt = !!(caps & PIN_CFG_SMT);3433 has_smt = !!(caps & PIN_CFG_SMT);
3434 has_sr = !!(caps & PIN_CFG_SR);
3435 has_nod = !!(caps & PIN_CFG_NOD);
3027 3436
3028 if (suspend)3437 if (suspend)
3029 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + PFC(off), cache->pfc[port]);3438 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + PFC(off), cache->pfc[port]);
@@ -3075,6 +3484,24 @@ static void rzg2l_pinctrl_pm_setup_regs(struct rzg2l_pinctrl *pctrl, bool suspen · 45 unmodified lines
3075 cache->smt[1][port]);3484 cache->smt[1][port]);
3076 }3485 }
3077 }3486 }
3487
3488 if (has_sr) {
3489 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + SR(off),
3490 cache->sr[0][port]);
3491 if (pincnt >= 4) {
3492 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + SR(off) + 4,
3493 cache->sr[1][port]);
3494 }
3495 }
3496
3497 if (has_nod) {
3498 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + NOD(off),
3499 cache->nod[0][port]);
3500 if (pincnt >= 4) {
3501 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + NOD(off) + 4,
3502 cache->nod[1][port]);
3503 }
3504 }
3078 }3505 }
3079}3506}
3080 3507
@@ -3089,7 +3516,7 @@ static void rzg2l_pinctrl_pm_setup_dedicated_regs(struct rzg2l_pinctrl *pctrl, b · 8 unmodified lines
3089 * port offset are close together.3516 * port offset are close together.
3090 */3517 */
3091 for (i = 0, caps = 0; i < pctrl->data->n_dedicated_pins; i++) {3518 for (i = 0, caps = 0; i < pctrl->data->n_dedicated_pins; i++) {
3092 bool has_iolh, has_ien;3519 bool has_iolh, has_ien, has_sr, has_nod, has_pupd;
3093 u32 off, next_off = 0;3520 u32 off, next_off = 0;
3094 u64 cfg, next_cfg;3521 u64 cfg, next_cfg;
3095 u8 pincnt;3522 u8 pincnt;
@@ -3108,8 +3535,12 @@ static void rzg2l_pinctrl_pm_setup_dedicated_regs(struct rzg2l_pinctrl *pctrl, b · 12 unmodified lines
3108 }3535 }
3109 3536
3110 /* And apply them in a single shot. */3537 /* And apply them in a single shot. */
3111 has_iolh = !!(caps & (PIN_CFG_IOLH_A | PIN_CFG_IOLH_B | PIN_CFG_IOLH_C));3538 has_iolh = !!(caps & (PIN_CFG_IOLH_A | PIN_CFG_IOLH_B |
3539 PIN_CFG_IOLH_C | PIN_CFG_IOLH_RZV2H));
3112 has_ien = !!(caps & PIN_CFG_IEN);3540 has_ien = !!(caps & PIN_CFG_IEN);
3541 has_sr = !!(caps & PIN_CFG_SR);
3542 has_nod = !!(caps & PIN_CFG_NOD);
3543 has_pupd = !!(caps & PIN_CFG_PUPD);
3113 pincnt = hweight8(FIELD_GET(RZG2L_SINGLE_PIN_BITS_MASK, cfg));3544 pincnt = hweight8(FIELD_GET(RZG2L_SINGLE_PIN_BITS_MASK, cfg));
3114 3545
3115 if (has_iolh) {3546 if (has_iolh) {
@@ -3120,6 +3551,18 @@ static void rzg2l_pinctrl_pm_setup_dedicated_regs(struct rzg2l_pinctrl *pctrl, b · 4 unmodified lines
3120 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IEN(off),3551 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IEN(off),
3121 cache->ien[0][i]);3552 cache->ien[0][i]);
3122 }3553 }
3554 if (has_sr) {
3555 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + SR(off),
3556 cache->sr[0][i]);
3557 }
3558 if (has_nod) {
3559 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + NOD(off),
3560 cache->nod[0][i]);
3561 }
3562 if (has_pupd) {
3563 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + PUPD(off),
3564 cache->pupd[0][i]);
3565 }
3123 3566
3124 if (pincnt >= 4) {3567 if (pincnt >= 4) {
3125 if (has_iolh) {3568 if (has_iolh) {
@@ -3132,6 +3575,21 @@ static void rzg2l_pinctrl_pm_setup_dedicated_regs(struct rzg2l_pinctrl *pctrl, b · 6 unmodified lines
3132 pctrl->base + IEN(off) + 4,3575 pctrl->base + IEN(off) + 4,
3133 cache->ien[1][i]);3576 cache->ien[1][i]);
3134 }3577 }
3578 if (has_sr) {
3579 RZG2L_PCTRL_REG_ACCESS32(suspend,
3580 pctrl->base + SR(off) + 4,
3581 cache->sr[1][i]);
3582 }
3583 if (has_nod) {
3584 RZG2L_PCTRL_REG_ACCESS32(suspend,
3585 pctrl->base + NOD(off) + 4,
3586 cache->nod[1][i]);
3587 }
3588 if (has_pupd) {
3589 RZG2L_PCTRL_REG_ACCESS32(suspend,
3590 pctrl->base + PUPD(off) + 4,
3591 cache->pupd[1][i]);
3592 }
3135 }3593 }
3136 caps = 0;3594 caps = 0;
3137 }3595 }
@@ -3214,8 +3672,19 @@ static int rzg2l_pinctrl_suspend_noirq(struct device *dev) · 76 unmodified lines
3214 cache->eth_poc[i] = readb(pctrl->base + ETH_POC(regs->eth_poc, i));3672 cache->eth_poc[i] = readb(pctrl->base + ETH_POC(regs->eth_poc, i));
3215 }3673 }
3216 3674
3217 cache->qspi = readb(pctrl->base + QSPI);3675 if (regs->qspi)
3676 cache->qspi = readb(pctrl->base + regs->qspi);
3218 cache->oen = readb(pctrl->base + pctrl->data->hwcfg->regs.oen);3677 cache->oen = readb(pctrl->base + pctrl->data->hwcfg->regs.oen);
3678 if (regs->other_poc)
3679 cache->other_poc = readb(pctrl->base + regs->other_poc);
3680
3681 if (pctrl->syscon) {
3682 int ret;
3683
3684 ret = regmap_read(pctrl->syscon, pctrl->clone_offset, &cache->clone);
3685 if (ret)
3686 return ret;
3687 }
3219 3688
3220 if (!atomic_read(&pctrl->wakeup_path))3689 if (!atomic_read(&pctrl->wakeup_path))
3221 clk_disable_unprepare(pctrl->clk);3690 clk_disable_unprepare(pctrl->clk);
@@ -3234,13 +3703,22 @@ static int rzg2l_pinctrl_resume_noirq(struct device *dev) · 12 unmodified lines
3234 unsigned long flags;3703 unsigned long flags;
3235 int ret;3704 int ret;
3236 3705
3706 if (pctrl->syscon) {
3707 ret = regmap_write(pctrl->syscon, pctrl->clone_offset, cache->clone);
3708 if (ret)
3709 return ret;
3710 }
3711
3237 if (!atomic_read(&pctrl->wakeup_path)) {3712 if (!atomic_read(&pctrl->wakeup_path)) {
3238 ret = clk_prepare_enable(pctrl->clk);3713 ret = clk_prepare_enable(pctrl->clk);
3239 if (ret)3714 if (ret)
3240 return ret;3715 return ret;
3241 }3716 }
3242 3717
3243 writeb(cache->qspi, pctrl->base + QSPI);3718 if (regs->qspi)
3719 writeb(cache->qspi, pctrl->base + regs->qspi);
3720 if (regs->other_poc)
3721 writeb(cache->other_poc, pctrl->base + regs->other_poc);
3244 3722
3245 raw_spin_lock_irqsave(&pctrl->lock, flags);3723 raw_spin_lock_irqsave(&pctrl->lock, flags);
3246 rzg2l_oen_write_with_pwpr(pctrl, cache->oen);3724 rzg2l_oen_write_with_pwpr(pctrl, cache->oen);
@@ -3298,6 +3776,7 @@ static const struct rzg2l_hwcfg rzg2l_hwcfg = { · 51 unmodified lines
3298 .sd_ch = 0x3000,3776 .sd_ch = 0x3000,
3299 .eth_poc = 0x300c,3777 .eth_poc = 0x300c,
3300 .oen = 0x3018,3778 .oen = 0x3018,
3779 .qspi = QSPI,
3301 },3780 },
3302 .iolh_groupa_ua = {3781 .iolh_groupa_ua = {
3303 /* 3v3 power source */3782 /* 3v3 power source */
@@ -3308,6 +3787,40 @@ static const struct rzg2l_hwcfg rzg2l_hwcfg = { · 4 unmodified lines
3308 .oen_max_pin = 0,3787 .oen_max_pin = 0,
3309};3788};
3310 3789
3790static const struct rzg2l_hwcfg rzg3l_hwcfg = {
3791 .regs = {
3792 .pwpr = 0x3000,
3793 .sd_ch = 0x3004,
3794 .eth_poc = 0x3010,
3795 .oen = 0x3018,
3796 .other_poc = OTHER_POC,
3797 },
3798 .iolh_groupa_ua = {
3799 /* 1v8 power source */
3800 [RZG2L_IOLH_IDX_1V8] = 2200, 4400, 9000, 10000,
3801 /* 3v3 power source */
3802 [RZG2L_IOLH_IDX_3V3] = 1900, 4000, 8000, 9000,
3803 },
3804 .iolh_groupb_ua = {
3805 /* 1v8 power source */
3806 [RZG2L_IOLH_IDX_1V8] = 7000, 8000, 9000, 10000,
3807 /* 3v3 power source */
3808 [RZG2L_IOLH_IDX_3V3] = 4000, 6000, 8000, 9000,
3809 },
3810 .iolh_groupc_ua = {
3811 /* 1v8 power source */
3812 [RZG2L_IOLH_IDX_1V8] = 5200, 6000, 6550, 6800,
3813 /* 2v5 source */
3814 [RZG2L_IOLH_IDX_2V5] = 4700, 5300, 5800, 6100,
3815 /* 3v3 power source */
3816 [RZG2L_IOLH_IDX_3V3] = 4500, 5200, 5700, 6050,
3817 },
3818 .tint_start_index = 17,
3819 .drive_strength_ua = true,
3820 .func_base = 0,
3821 .oen_max_pin = 1, /* Pin 1 of P{B,E}1_ISO is the maximum OEN pin. */
3822};
3823
3311static const struct rzg2l_hwcfg rzg3s_hwcfg = {3824static const struct rzg2l_hwcfg rzg3s_hwcfg = {
3312 .regs = {3825 .regs = {
3313 .pwpr = 0x3000,3826 .pwpr = 0x3000,
@@ -3401,6 +3914,25 @@ static struct rzg2l_pinctrl_data r9a08g045_data = { · 87 unmodified lines
3401 .bias_param_to_hw = &rzg2l_bias_param_to_hw,3914 .bias_param_to_hw = &rzg2l_bias_param_to_hw,
3402};3915};
3403 3916
3917static struct rzg2l_pinctrl_data r9a08g046_data = {
3918 .port_pins = rzg3l_gpio_names,
3919 .port_pin_configs = r9a08g046_gpio_configs,
3920 .n_ports = ARRAY_SIZE(r9a08g046_gpio_configs),
3921 .variable_pin_cfg = r9a08g046_variable_pin_cfg,
3922 .n_variable_pin_cfg = ARRAY_SIZE(r9a08g046_variable_pin_cfg),
3923 .dedicated_pins = rzg3l_dedicated_pins,
3924 .n_port_pins = ARRAY_SIZE(r9a08g046_gpio_configs) * RZG2L_PINS_PER_PORT,
3925 .n_dedicated_pins = ARRAY_SIZE(rzg3l_dedicated_pins),
3926 .clone_channel_data = r9a08g046_clone_channel_data,
3927 .n_clone_channel_data = ARRAY_SIZE(r9a08g046_clone_channel_data),
3928 .hwcfg = &rzg3l_hwcfg,
3929 .pwpr_pfc_lock_unlock = &rzg2l_pwpr_pfc_lock_unlock,
3930 .pmc_writeb = &rzg2l_pmc_writeb,
3931 .pin_to_oen_bit = &rzg2l_pin_to_oen_bit,
3932 .hw_to_bias_param = &rzg2l_hw_to_bias_param,
3933 .bias_param_to_hw = &rzg2l_bias_param_to_hw,
3934};
3935
3404static struct rzg2l_pinctrl_data r9a09g047_data = {3936static struct rzg2l_pinctrl_data r9a09g047_data = {
3405 .port_pins = rzg3e_gpio_names,3937 .port_pins = rzg3e_gpio_names,
3406 .port_pin_configs = r9a09g047_gpio_configs,3938 .port_pin_configs = r9a09g047_gpio_configs,
@@ -3481,6 +4013,10 @@ static const struct of_device_id rzg2l_pinctrl_of_table[] = { · 74 unmodified lines
3481 .compatible = "renesas,r9a08g045-pinctrl",4013 .compatible = "renesas,r9a08g045-pinctrl",
3482 .data = &r9a08g045_data,4014 .data = &r9a08g045_data,
3483 },4015 },
4016 {
4017 .compatible = "renesas,r9a08g046-pinctrl",
4018 .data = &r9a08g046_data,
4019 },
3484 {4020 {
3485 .compatible = "renesas,r9a09g047-pinctrl",4021 .compatible = "renesas,r9a09g047-pinctrl",
3486 .data = &r9a09g047_data,4022 .data = &r9a09g047_data,
drivers/pinctrl/renesas/pinctrl-rzt2h.c+8−5
@@ -191,6 +191,12 @@ static void rzt2h_pinctrl_set_pfc_mode(struct rzt2h_pinctrl *pctrl, · 190 unmodified lines
191 191
192 guard(raw_spinlock_irqsave)(&pctrl->lock);192 guard(raw_spinlock_irqsave)(&pctrl->lock);
193 193
194 reg64 = rzt2h_pinctrl_readq(pctrl, port, PFC(port));
195 /* Check if pin is already configured to the desired function */
196 if ((rzt2h_pinctrl_readb(pctrl, port, PMC(port)) & BIT(pin)) &&
197 field_get(PFC_PIN_MASK(pin), reg64) == func)
198 return;
199
194 /* Set pin to 'Non-use (Hi-Z input protection)' */200 /* Set pin to 'Non-use (Hi-Z input protection)' */
195 reg16 = rzt2h_pinctrl_readw(pctrl, port, PM(port));201 reg16 = rzt2h_pinctrl_readw(pctrl, port, PM(port));
196 reg16 &= ~PM_PIN_MASK(pin);202 reg16 &= ~PM_PIN_MASK(pin);
@@ -200,7 +206,6 @@ static void rzt2h_pinctrl_set_pfc_mode(struct rzt2h_pinctrl *pctrl, · 3 unmodified lines
200 rzt2h_pinctrl_set_gpio_en(pctrl, port, pin, true);206 rzt2h_pinctrl_set_gpio_en(pctrl, port, pin, true);
201 207
202 /* Select Pin function mode with PFC register */208 /* Select Pin function mode with PFC register */
203 reg64 = rzt2h_pinctrl_readq(pctrl, port, PFC(port));
204 reg64 &= ~PFC_PIN_MASK(pin);209 reg64 &= ~PFC_PIN_MASK(pin);
205 rzt2h_pinctrl_writeq(pctrl, port, reg64 | ((u64)func << (pin * 8)), PFC(port));210 rzt2h_pinctrl_writeq(pctrl, port, reg64 | ((u64)func << (pin * 8)), PFC(port));
206 211
@@ -1140,7 +1145,7 @@ static int rzt2h_pinctrl_register(struct rzt2h_pinctrl *pctrl) · 933 unmodified lines
1140 struct pinctrl_desc *desc = &pctrl->desc;1145 struct pinctrl_desc *desc = &pctrl->desc;
1141 struct device *dev = pctrl->dev;1146 struct device *dev = pctrl->dev;
1142 struct pinctrl_pin_desc *pins;1147 struct pinctrl_pin_desc *pins;
1143 unsigned int i, j;1148 unsigned int i;
1144 int ret;1149 int ret;
1145 1150
1146 desc->name = DRV_NAME;1151 desc->name = DRV_NAME;
@@ -1157,11 +1162,9 @@ static int rzt2h_pinctrl_register(struct rzt2h_pinctrl *pctrl) · 10 unmodified lines
1157 pctrl->pins = pins;1162 pctrl->pins = pins;
1158 desc->pins = pins;1163 desc->pins = pins;
1159 1164
1160 for (i = 0, j = 0; i < pctrl->data->n_port_pins; i++) {1165 for (i = 0; i < pctrl->data->n_port_pins; i++) {
1161 pins[i].number = i;1166 pins[i].number = i;
1162 pins[i].name = rzt2h_gpio_names[i];1167 pins[i].name = rzt2h_gpio_names[i];
1163 if (i && !(i % RZT2H_PINS_PER_PORT))
1164 j++;
1165 }1168 }
1166 1169
1167 ret = devm_pinctrl_register_and_init(dev, desc, pctrl, &pctrl->pctl);1170 ret = devm_pinctrl_register_and_init(dev, desc, pctrl, &pctrl->pctl);
drivers/pinctrl/renesas/pinctrl-rzv2m.c+4−3
@@ -661,7 +661,7 @@ static int rzv2m_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, · 660 unmodified lines
661 }661 }
662 662
663 default:663 default:
664 return -EOPNOTSUPP;664 return -ENOTSUPP;
665 }665 }
666 }666 }
667 667
@@ -695,8 +695,9 @@ static int rzv2m_pinctrl_pinconf_group_get(struct pinctrl_dev *pctldev, · 27 unmodified lines
695 unsigned int group,695 unsigned int group,
696 unsigned long *config)696 unsigned long *config)
697{697{
698 unsigned long prev_config = 0;
698 const unsigned int *pins;699 const unsigned int *pins;
699 unsigned int i, npins, prev_config = 0;700 unsigned int i, npins;
700 int ret;701 int ret;
701 702
702 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);703 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
@@ -710,7 +711,7 @@ static int rzv2m_pinctrl_pinconf_group_get(struct pinctrl_dev *pctldev, · 7 unmodified lines
710 711
711 /* Check config matches previous pins */712 /* Check config matches previous pins */
712 if (i && prev_config != *config)713 if (i && prev_config != *config)
713 return -EOPNOTSUPP;714 return -ENOTSUPP;
714 715
715 prev_config = *config;716 prev_config = *config;
716 }717 }
drivers/pinctrl/renesas/pinctrl.c+25−0
@@ -719,6 +719,30 @@ static int sh_pfc_pinconf_set(struct pinctrl_dev *pctldev, unsigned _pin, · 718 unmodified lines
719 return 0;719 return 0;
720}720}
721 721
722static int sh_pfc_pinconf_group_get(struct pinctrl_dev *pctldev,
723 unsigned int group, unsigned long *config)
724{
725 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
726 const unsigned int *pins = pmx->pfc->info->groups[group].pins;
727 unsigned int num_pins = pmx->pfc->info->groups[group].nr_pins;
728 unsigned long prev_config = 0;
729 int ret;
730
731 for (unsigned int i = 0; i < num_pins; ++i) {
732 ret = sh_pfc_pinconf_get(pctldev, pins[i], config);
733 if (ret)
734 return ret;
735
736 /* configs should match for all pins in the group */
737 if (i && prev_config != *config)
738 return -ENOTSUPP;
739
740 prev_config = *config;
741 }
742
743 return 0;
744}
745
722static int sh_pfc_pinconf_group_set(struct pinctrl_dev *pctldev, unsigned group,746static int sh_pfc_pinconf_group_set(struct pinctrl_dev *pctldev, unsigned group,
723 unsigned long *configs,747 unsigned long *configs,
724 unsigned num_configs)748 unsigned num_configs)
@@ -745,6 +769,7 @@ static const struct pinconf_ops sh_pfc_pinconf_ops = { · 20 unmodified lines
745 .is_generic = true,769 .is_generic = true,
746 .pin_config_get = sh_pfc_pinconf_get,770 .pin_config_get = sh_pfc_pinconf_get,
747 .pin_config_set = sh_pfc_pinconf_set,771 .pin_config_set = sh_pfc_pinconf_set,
772 .pin_config_group_get = sh_pfc_pinconf_group_get,
748 .pin_config_group_set = sh_pfc_pinconf_group_set,773 .pin_config_group_set = sh_pfc_pinconf_group_set,
749 .pin_config_config_dbg_show = pinconf_generic_dump_config,774 .pin_config_config_dbg_show = pinconf_generic_dump_config,
750};775};
drivers/pinctrl/sophgo/pinctrl-cv18xx.c+12−20
@@ -27,8 +27,9 @@ · 26 unmodified lines
27#include "pinctrl-cv18xx.h"27#include "pinctrl-cv18xx.h"
28 28
29struct cv1800_priv {29struct cv1800_priv {
30 u32 *power_cfg;30 void __iomem *regs[2];
31 void __iomem *regs[2];31 unsigned int num_power_cfg;
32 u32 power_cfg[] __counted_by(num_power_cfg);
32};33};
33 34
34static unsigned int cv1800_dt_get_pin_mux(u32 value)35static unsigned int cv1800_dt_get_pin_mux(u32 value)
@@ -333,13 +334,11 @@ static int cv1800_pinconf_compute_config(struct sophgo_pinctrl *pctrl, · 298 unmodified lines
333 334
334 switch (param) {335 switch (param) {
335 case PIN_CONFIG_BIAS_PULL_DOWN:336 case PIN_CONFIG_BIAS_PULL_DOWN:
336 v &= ~PIN_IO_PULLDOWN;337 FIELD_MODIFY(PIN_IO_PULLDOWN, &v, arg);
337 v |= FIELD_PREP(PIN_IO_PULLDOWN, arg);
338 m |= PIN_IO_PULLDOWN;338 m |= PIN_IO_PULLDOWN;
339 break;339 break;
340 case PIN_CONFIG_BIAS_PULL_UP:340 case PIN_CONFIG_BIAS_PULL_UP:
341 v &= ~PIN_IO_PULLUP;341 FIELD_MODIFY(PIN_IO_PULLUP, &v, arg);
342 v |= FIELD_PREP(PIN_IO_PULLUP, arg);
343 m |= PIN_IO_PULLUP;342 m |= PIN_IO_PULLUP;
344 break;343 break;
345 case PIN_CONFIG_DRIVE_STRENGTH_UA:344 case PIN_CONFIG_DRIVE_STRENGTH_UA:
@@ -347,8 +346,7 @@ static int cv1800_pinconf_compute_config(struct sophgo_pinctrl *pctrl, · 1 unmodified line
347 priv->power_cfg, arg);346 priv->power_cfg, arg);
348 if (ret < 0)347 if (ret < 0)
349 return ret;348 return ret;
350 v &= ~PIN_IO_DRIVE;349 FIELD_MODIFY(PIN_IO_DRIVE, &v, ret);
351 v |= FIELD_PREP(PIN_IO_DRIVE, ret);
352 m |= PIN_IO_DRIVE;350 m |= PIN_IO_DRIVE;
353 break;351 break;
354 case PIN_CONFIG_INPUT_SCHMITT_UV:352 case PIN_CONFIG_INPUT_SCHMITT_UV:
@@ -356,21 +354,18 @@ static int cv1800_pinconf_compute_config(struct sophgo_pinctrl *pctrl, · 1 unmodified line
356 priv->power_cfg, arg);354 priv->power_cfg, arg);
357 if (ret < 0)355 if (ret < 0)
358 return ret;356 return ret;
359 v &= ~PIN_IO_SCHMITT;357 FIELD_MODIFY(PIN_IO_SCHMITT, &v, ret);
360 v |= FIELD_PREP(PIN_IO_SCHMITT, ret);
361 m |= PIN_IO_SCHMITT;358 m |= PIN_IO_SCHMITT;
362 break;359 break;
363 case PIN_CONFIG_POWER_SOURCE:360 case PIN_CONFIG_POWER_SOURCE:
364 /* Ignore power source as it is always fixed */361 /* Ignore power source as it is always fixed */
365 break;362 break;
366 case PIN_CONFIG_SLEW_RATE:363 case PIN_CONFIG_SLEW_RATE:
367 v &= ~PIN_IO_OUT_FAST_SLEW;364 FIELD_MODIFY(PIN_IO_OUT_FAST_SLEW, &v, arg);
368 v |= FIELD_PREP(PIN_IO_OUT_FAST_SLEW, arg);
369 m |= PIN_IO_OUT_FAST_SLEW;365 m |= PIN_IO_OUT_FAST_SLEW;
370 break;366 break;
371 case PIN_CONFIG_BIAS_BUS_HOLD:367 case PIN_CONFIG_BIAS_BUS_HOLD:
372 v &= ~PIN_IO_BUS_HOLD;368 FIELD_MODIFY(PIN_IO_BUS_HOLD, &v, arg);
373 v |= FIELD_PREP(PIN_IO_BUS_HOLD, arg);
374 m |= PIN_IO_BUS_HOLD;369 m |= PIN_IO_BUS_HOLD;
375 break;370 break;
376 default:371 default:
@@ -417,14 +412,11 @@ static int cv1800_pinctrl_init(struct platform_device *pdev, · 40 unmodified lines
417 const struct sophgo_pinctrl_data *pctrl_data = pctrl->data;412 const struct sophgo_pinctrl_data *pctrl_data = pctrl->data;
418 struct cv1800_priv *priv;413 struct cv1800_priv *priv;
419 414
420 priv = devm_kzalloc(&pdev->dev, sizeof(struct cv1800_priv), GFP_KERNEL);415 priv = devm_kzalloc(&pdev->dev, struct_size(priv, power_cfg, pctrl_data->npds),
416 GFP_KERNEL);
421 if (!priv)417 if (!priv)
422 return -ENOMEM;418 return -ENOMEM;
423 419 priv->num_power_cfg = pctrl_data->npds;
424 priv->power_cfg = devm_kcalloc(&pdev->dev, pctrl_data->npds,
425 sizeof(u32), GFP_KERNEL);
426 if (!priv->power_cfg)
427 return -ENOMEM;
428 420
429 priv->regs[0] = devm_platform_ioremap_resource_byname(pdev, "sys");421 priv->regs[0] = devm_platform_ioremap_resource_byname(pdev, "sys");
430 if (IS_ERR(priv->regs[0]))422 if (IS_ERR(priv->regs[0]))
drivers/pinctrl/spacemit/Kconfig+1−3
@@ -8,9 +8,7 @@ config PINCTRL_SPACEMIT_K1 · 7 unmodified lines
8 depends on ARCH_SPACEMIT || COMPILE_TEST8 depends on ARCH_SPACEMIT || COMPILE_TEST
9 depends on OF9 depends on OF
10 default ARCH_SPACEMIT10 default ARCH_SPACEMIT
11 select GENERIC_PINCTRL_GROUPS11 select GENERIC_PINCTRL
12 select GENERIC_PINMUX_FUNCTIONS
13 select GENERIC_PINCONF
14 help12 help
15 Say Y to select the pinctrl driver for K1/K3 SoC.13 Say Y to select the pinctrl driver for K1/K3 SoC.
16 This pin controller allows selecting the mux function for14 This pin controller allows selecting the mux function for
drivers/pinctrl/spacemit/pinctrl-k1.c+13−169
@@ -114,11 +114,6 @@ struct spacemit_pinctrl_data { · 113 unmodified lines
114 const struct spacemit_pinctrl_dconf *dconf;114 const struct spacemit_pinctrl_dconf *dconf;
115};115};
116 116
117struct spacemit_pin_mux_config {
118 const struct spacemit_pin *pin;
119 u32 config;
120};
121
122/* map pin id to pinctrl register offset, refer MFPR definition */117/* map pin id to pinctrl register offset, refer MFPR definition */
123static unsigned int spacemit_k1_pin_to_offset(unsigned int pin)118static unsigned int spacemit_k1_pin_to_offset(unsigned int pin)
124{119{
@@ -228,16 +223,6 @@ static inline void __iomem *spacemit_pin_to_reg(struct spacemit_pinctrl *pctrl, · 103 unmodified lines
228 return pctrl->regs + pctrl->data->pin_to_offset(pin);223 return pctrl->regs + pctrl->data->pin_to_offset(pin);
229}224}
230 225
231static u16 spacemit_dt_get_pin(u32 value)
232{
233 return value >> 16;
234}
235
236static u16 spacemit_dt_get_pin_mux(u32 value)
237{
238 return value & GENMASK(15, 0);
239}
240
241static const struct spacemit_pin *spacemit_get_pin(struct spacemit_pinctrl *pctrl,226static const struct spacemit_pin *spacemit_get_pin(struct spacemit_pinctrl *pctrl,
242 unsigned long pin)227 unsigned long pin)
243{228{
@@ -409,38 +394,6 @@ static inline u32 spacemit_get_drive_strength_mA(enum spacemit_pin_io_type type, · 165 unmodified lines
409 }394 }
410}395}
411 396
412static int spacemit_pctrl_check_power(struct pinctrl_dev *pctldev,
413 struct device_node *dn,
414 struct spacemit_pin_mux_config *pinmuxs,
415 int num_pins, const char *grpname)
416{
417 struct spacemit_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
418 struct device *dev = pctrl->dev;
419 enum spacemit_pin_io_type type;
420 u32 power = 0, i;
421
422 of_property_read_u32(dn, "power-source", &power);
423
424 for (i = 0; i < num_pins; i++) {
425 type = spacemit_to_pin_io_type(pinmuxs[i].pin);
426
427 if (type != IO_TYPE_EXTERNAL)
428 continue;
429
430 switch (power) {
431 case PIN_POWER_STATE_1V8:
432 case PIN_POWER_STATE_3V3:
433 break;
434 default:
435 dev_err(dev, "group %s has unsupported power\n",
436 grpname);
437 return -ENOTSUPP;
438 }
439 }
440
441 return 0;
442}
443
444static void spacemit_set_io_pwr_domain(struct spacemit_pinctrl *pctrl,397static void spacemit_set_io_pwr_domain(struct spacemit_pinctrl *pctrl,
445 const struct spacemit_pin *spin,398 const struct spacemit_pin *spin,
446 const enum spacemit_pin_io_type type)399 const enum spacemit_pin_io_type type)
@@ -477,126 +430,12 @@ static void spacemit_set_io_pwr_domain(struct spacemit_pinctrl *pctrl, · 30 unmodified lines
477 writel_relaxed(val, pctrl->regs + IO_PWR_DOMAIN_OFFSET + offset);430 writel_relaxed(val, pctrl->regs + IO_PWR_DOMAIN_OFFSET + offset);
478}431}
479 432
480static int spacemit_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
481 struct device_node *np,
482 struct pinctrl_map **maps,
483 unsigned int *num_maps)
484{
485 struct spacemit_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
486 struct device *dev = pctrl->dev;
487 struct device_node *child;
488 struct pinctrl_map *map;
489 const char **grpnames;
490 const char *grpname;
491 int ngroups = 0;
492 int nmaps = 0;
493 int ret;
494
495 for_each_available_child_of_node(np, child)
496 ngroups += 1;
497
498 grpnames = devm_kcalloc(dev, ngroups, sizeof(*grpnames), GFP_KERNEL);
499 if (!grpnames)
500 return -ENOMEM;
501
502 map = kzalloc_objs(*map, ngroups * 2);
503 if (!map)
504 return -ENOMEM;
505
506 ngroups = 0;
507 guard(mutex)(&pctrl->mutex);
508 for_each_available_child_of_node_scoped(np, child) {
509 struct spacemit_pin_mux_config *pinmuxs;
510 unsigned int config, *pins;
511 int i, npins;
512
513 npins = of_property_count_u32_elems(child, "pinmux");
514
515 if (npins < 1) {
516 dev_err(dev, "invalid pinctrl group %pOFn.%pOFn\n",
517 np, child);
518 return -EINVAL;
519 }
520
521 grpname = devm_kasprintf(dev, GFP_KERNEL, "%pOFn.%pOFn",
522 np, child);
523 if (!grpname)
524 return -ENOMEM;
525
526 grpnames[ngroups++] = grpname;
527
528 pins = devm_kcalloc(dev, npins, sizeof(*pins), GFP_KERNEL);
529 if (!pins)
530 return -ENOMEM;
531
532 pinmuxs = devm_kcalloc(dev, npins, sizeof(*pinmuxs), GFP_KERNEL);
533 if (!pinmuxs)
534 return -ENOMEM;
535
536 for (i = 0; i < npins; i++) {
537 ret = of_property_read_u32_index(child, "pinmux",
538 i, &config);
539
540 if (ret)
541 return -EINVAL;
542
543 pins[i] = spacemit_dt_get_pin(config);
544 pinmuxs[i].config = config;
545 pinmuxs[i].pin = spacemit_get_pin(pctrl, pins[i]);
546
547 if (!pinmuxs[i].pin)
548 return dev_err_probe(dev, -ENODEV, "failed to get pin %d\n", pins[i]);
549 }
550
551 ret = spacemit_pctrl_check_power(pctldev, child, pinmuxs,
552 npins, grpname);
553 if (ret < 0)
554 return ret;
555
556 map[nmaps].type = PIN_MAP_TYPE_MUX_GROUP;
557 map[nmaps].data.mux.function = np->name;
558 map[nmaps].data.mux.group = grpname;
559 nmaps += 1;
560
561 ret = pinctrl_generic_add_group(pctldev, grpname,
562 pins, npins, pinmuxs);
563 if (ret < 0)
564 return dev_err_probe(dev, ret, "failed to add group %s: %d\n", grpname, ret);
565
566 ret = pinconf_generic_parse_dt_config(child, pctldev,
567 &map[nmaps].data.configs.configs,
568 &map[nmaps].data.configs.num_configs);
569 if (ret)
570 return dev_err_probe(dev, ret, "failed to parse pin config of group %s\n",
571 grpname);
572
573 if (map[nmaps].data.configs.num_configs == 0)
574 continue;
575
576 map[nmaps].type = PIN_MAP_TYPE_CONFIGS_GROUP;
577 map[nmaps].data.configs.group_or_pin = grpname;
578 nmaps += 1;
579 }
580
581 ret = pinmux_generic_add_function(pctldev, np->name,
582 grpnames, ngroups, NULL);
583 if (ret < 0) {
584 pinctrl_utils_free_map(pctldev, map, nmaps);
585 return dev_err_probe(dev, ret, "error adding function %s\n", np->name);
586 }
587
588 *maps = map;
589 *num_maps = nmaps;
590
591 return 0;
592}
593
594static const struct pinctrl_ops spacemit_pctrl_ops = {433static const struct pinctrl_ops spacemit_pctrl_ops = {
595 .get_groups_count = pinctrl_generic_get_group_count,434 .get_groups_count = pinctrl_generic_get_group_count,
596 .get_group_name = pinctrl_generic_get_group_name,435 .get_group_name = pinctrl_generic_get_group_name,
597 .get_group_pins = pinctrl_generic_get_group_pins,436 .get_group_pins = pinctrl_generic_get_group_pins,
598 .pin_dbg_show = spacemit_pctrl_dbg_show,437 .pin_dbg_show = spacemit_pctrl_dbg_show,
599 .dt_node_to_map = spacemit_pctrl_dt_node_to_map,438 .dt_node_to_map = pinctrl_generic_pinmux_dt_node_to_map,
600 .dt_free_map = pinctrl_utils_free_map,439 .dt_free_map = pinctrl_utils_free_map,
601};440};
602 441
@@ -605,8 +444,8 @@ static int spacemit_pmx_set_mux(struct pinctrl_dev *pctldev, · 2 unmodified lines
605{444{
606 struct spacemit_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);445 struct spacemit_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
607 const struct group_desc *group;446 const struct group_desc *group;
608 const struct spacemit_pin_mux_config *configs;
609 unsigned int i, mux;447 unsigned int i, mux;
448 unsigned int *configs;
610 void __iomem *reg;449 void __iomem *reg;
611 450
612 group = pinctrl_generic_get_group(pctldev, gsel);451 group = pinctrl_generic_get_group(pctldev, gsel);
@@ -616,11 +455,17 @@ static int spacemit_pmx_set_mux(struct pinctrl_dev *pctldev, · 3 unmodified lines
616 configs = group->data;455 configs = group->data;
617 456
618 for (i = 0; i < group->grp.npins; i++) {457 for (i = 0; i < group->grp.npins; i++) {
619 const struct spacemit_pin *spin = configs[i].pin;458 const struct spacemit_pin *spin;
620 u32 value = configs[i].config;459 u32 value = configs[i];
460
461 spin = spacemit_get_pin(pctrl, group->grp.pins[i]);
462 if (!spin) {
463 dev_err(pctrl->dev, "Invalid pin %u\n", group->grp.pins[i]);
464 return -EINVAL;
465 }
621 466
622 reg = spacemit_pin_to_reg(pctrl, spin->pin);467 reg = spacemit_pin_to_reg(pctrl, spin->pin);
623 mux = spacemit_dt_get_pin_mux(value);468 mux = value;
624 469
625 guard(raw_spinlock_irqsave)(&pctrl->lock);470 guard(raw_spinlock_irqsave)(&pctrl->lock);
626 value = readl_relaxed(reg) & ~PAD_MUX;471 value = readl_relaxed(reg) & ~PAD_MUX;
@@ -777,9 +622,8 @@ static int spacemit_pinconf_generate_config(struct spacemit_pinctrl *pctrl, · 150 unmodified lines
777 return -EINVAL;622 return -EINVAL;
778 }623 }
779 } else {624 } else {
780 v &= ~PAD_SLEW_RATE;
781 slew_rate = slew_rate > 1 ? (slew_rate - 2) : 0;625 slew_rate = slew_rate > 1 ? (slew_rate - 2) : 0;
782 v |= FIELD_PREP(PAD_SLEW_RATE, slew_rate);626 FIELD_MODIFY(PAD_SLEW_RATE, &v, slew_rate);
783 }627 }
784 }628 }
785 629
@@ -795,7 +639,7 @@ static int spacemit_pin_set_config(struct spacemit_pinctrl *pctrl, · 9 unmodified lines
795 void __iomem *reg;639 void __iomem *reg;
796 unsigned int mux;640 unsigned int mux;
797 641
798 if (!pin)642 if (!spin)
799 return -EINVAL;643 return -EINVAL;
800 644
801 reg = spacemit_pin_to_reg(pctrl, spin->pin);645 reg = spacemit_pin_to_reg(pctrl, spin->pin);
drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c+5−8
@@ -845,6 +845,7 @@ int jh7110_pinctrl_probe(struct platform_device *pdev) · 844 unmodified lines
845 struct jh7110_pinctrl *sfp;845 struct jh7110_pinctrl *sfp;
846 struct pinctrl_desc *jh7110_pinctrl_desc;846 struct pinctrl_desc *jh7110_pinctrl_desc;
847 struct reset_control *rst;847 struct reset_control *rst;
848 unsigned int num_saved_regs;
848 struct clk *clk;849 struct clk *clk;
849 int ret;850 int ret;
850 851
@@ -857,16 +858,12 @@ int jh7110_pinctrl_probe(struct platform_device *pdev) · 6 unmodified lines
857 return -EINVAL;858 return -EINVAL;
858 }859 }
859 860
860 sfp = devm_kzalloc(dev, sizeof(*sfp), GFP_KERNEL);861 num_saved_regs = IS_ENABLED(CONFIG_PM_SLEEP) ? info->nsaved_regs : 0;
862 sfp = devm_kzalloc(dev, struct_size(sfp, saved_regs, num_saved_regs),
863 GFP_KERNEL);
861 if (!sfp)864 if (!sfp)
862 return -ENOMEM;865 return -ENOMEM;
863 866 sfp->num_saved_regs = num_saved_regs;
864#if IS_ENABLED(CONFIG_PM_SLEEP)
865 sfp->saved_regs = devm_kcalloc(dev, info->nsaved_regs,
866 sizeof(*sfp->saved_regs), GFP_KERNEL);
867 if (!sfp->saved_regs)
868 return -ENOMEM;
869#endif
870 867
871 sfp->base = devm_platform_ioremap_resource(pdev, 0);868 sfp->base = devm_platform_ioremap_resource(pdev, 0);
872 if (IS_ERR(sfp->base))869 if (IS_ERR(sfp->base))
drivers/pinctrl/starfive/pinctrl-starfive-jh7110.h+2−1
@@ -21,7 +21,8 @@ struct jh7110_pinctrl { · 20 unmodified lines
21 /* register read/write mutex */21 /* register read/write mutex */
22 struct mutex mutex;22 struct mutex mutex;
23 const struct jh7110_pinctrl_soc_info *info;23 const struct jh7110_pinctrl_soc_info *info;
24 u32 *saved_regs;24 unsigned int num_saved_regs;
25 u32 saved_regs[] __counted_by(num_saved_regs);
25};26};
26 27
27struct jh7110_gpio_irq_reg {28struct jh7110_gpio_irq_reg {
drivers/pinctrl/sunxi/pinctrl-sun55i-a523-r.c+0−1
@@ -26,7 +26,6 @@ static const u8 a523_r_irq_bank_muxes[SUNXI_PINCTRL_MAX_BANKS] = · 25 unmodified lines
26static struct sunxi_pinctrl_desc a523_r_pinctrl_data = {26static struct sunxi_pinctrl_desc a523_r_pinctrl_data = {
27 .irq_banks = ARRAY_SIZE(a523_r_irq_bank_map),27 .irq_banks = ARRAY_SIZE(a523_r_irq_bank_map),
28 .irq_bank_map = a523_r_irq_bank_map,28 .irq_bank_map = a523_r_irq_bank_map,
29 .irq_read_needs_mux = true,
30 .io_bias_cfg_variant = BIAS_VOLTAGE_PIO_POW_MODE_SEL,29 .io_bias_cfg_variant = BIAS_VOLTAGE_PIO_POW_MODE_SEL,
31 .pin_base = PL_BASE,30 .pin_base = PL_BASE,
32};31};
drivers/pinctrl/sunxi/pinctrl-sun55i-a523.c+0−1
@@ -26,7 +26,6 @@ static const u8 a523_irq_bank_muxes[SUNXI_PINCTRL_MAX_BANKS] = · 25 unmodified lines
26static struct sunxi_pinctrl_desc a523_pinctrl_data = {26static struct sunxi_pinctrl_desc a523_pinctrl_data = {
27 .irq_banks = ARRAY_SIZE(a523_irq_bank_map),27 .irq_banks = ARRAY_SIZE(a523_irq_bank_map),
28 .irq_bank_map = a523_irq_bank_map,28 .irq_bank_map = a523_irq_bank_map,
29 .irq_read_needs_mux = true,
30 .io_bias_cfg_variant = BIAS_VOLTAGE_PIO_POW_MODE_SEL,29 .io_bias_cfg_variant = BIAS_VOLTAGE_PIO_POW_MODE_SEL,
31};30};
32 31
drivers/pinctrl/sunxi/pinctrl-sunxi.c+1−1
@@ -925,7 +925,7 @@ static int sunxi_pmx_request(struct pinctrl_dev *pctldev, unsigned offset) · 924 unmodified lines
925 return 0;925 return 0;
926 926
927out:927out:
928 regulator_put(s_reg->regulator);928 regulator_put(reg);
929 929
930 return ret;930 return ret;
931}931}
drivers/pinctrl/tegra/Kconfig+34−10
@@ -1,43 +1,67 @@
1# SPDX-License-Identifier: GPL-2.0-only1# SPDX-License-Identifier: GPL-2.0-only
2config PINCTRL_TEGRA2config PINCTRL_TEGRA
3 bool3 bool "NVIDIA Tegra pin controllers common" if COMPILE_TEST && !ARCH_TEGRA
4 select PINMUX4 select PINMUX
5 select PINCONF5 select PINCONF
6 6
7config PINCTRL_TEGRA207config PINCTRL_TEGRA20
8 bool8 bool "NVIDIA Tegra20 pin controller" if COMPILE_TEST && !ARCH_TEGRA
9 select PINCTRL_TEGRA9 select PINCTRL_TEGRA
10 depends on COMMON_CLK
10 11
11config PINCTRL_TEGRA3012config PINCTRL_TEGRA30
12 bool13 bool "NVIDIA Tegra30 pin controller" if COMPILE_TEST && !ARCH_TEGRA
13 select PINCTRL_TEGRA14 select PINCTRL_TEGRA
14 15
15config PINCTRL_TEGRA11416config PINCTRL_TEGRA114
16 bool17 bool "NVIDIA Tegra114 pin controller" if COMPILE_TEST && !ARCH_TEGRA
17 select PINCTRL_TEGRA18 select PINCTRL_TEGRA
18 19
19config PINCTRL_TEGRA12420config PINCTRL_TEGRA124
20 bool21 bool "NVIDIA Tegra124 pin controller" if COMPILE_TEST && !ARCH_TEGRA
21 select PINCTRL_TEGRA22 select PINCTRL_TEGRA
22 23
23config PINCTRL_TEGRA21024config PINCTRL_TEGRA210
24 bool25 bool "NVIDIA Tegra210 pin controller" if COMPILE_TEST && !ARCH_TEGRA
25 select PINCTRL_TEGRA26 select PINCTRL_TEGRA
26 27
27config PINCTRL_TEGRA18628config PINCTRL_TEGRA186
28 bool29 bool "NVIDIA Tegra186 pin controller" if COMPILE_TEST && !ARCH_TEGRA
29 select PINCTRL_TEGRA30 select PINCTRL_TEGRA
30 31
31config PINCTRL_TEGRA19432config PINCTRL_TEGRA194
32 bool33 bool "NVIDIA Tegra194 pin controller" if COMPILE_TEST && !ARCH_TEGRA
33 select PINCTRL_TEGRA34 select PINCTRL_TEGRA
34 35
35config PINCTRL_TEGRA23436config PINCTRL_TEGRA234
36 bool37 bool "NVIDIA Tegra234 pin controller" if COMPILE_TEST && !ARCH_TEGRA
37 select PINCTRL_TEGRA38 select PINCTRL_TEGRA
38 39
40config PINCTRL_TEGRA238
41 tristate "NVIDIA Tegra238 pinctrl driver"
42 depends on ARCH_TEGRA || COMPILE_TEST
43 default m if ARCH_TEGRA_238_SOC
44 select PINCTRL_TEGRA
45 help
46 Say Y or M here to enable support for the pinctrl driver for
47 NVIDIA Tegra238 SoC. This driver controls the pin multiplexing
48 and configuration for the MAIN and AON pin controllers found
49 on Tegra238.
50
51config PINCTRL_TEGRA264
52 tristate "NVIDIA Tegra264 pinctrl driver"
53 depends on ARCH_TEGRA || COMPILE_TEST
54 default m if ARCH_TEGRA_264_SOC
55 select PINCTRL_TEGRA
56 help
57 Say Y or M here to enable support for the pinctrl driver for
58 NVIDIA Tegra264 SoC. This driver controls the pin multiplexing
59 and configuration for the MAIN, AON and UPHY pin controllers found
60 on Tegra264.
61
39config PINCTRL_TEGRA_XUSB62config PINCTRL_TEGRA_XUSB
40 def_bool y if ARCH_TEGRA63 bool "NVIDIA Tegra XUSB pin controller" if COMPILE_TEST && !ARCH_TEGRA
64 default y if ARCH_TEGRA
41 select GENERIC_PHY65 select GENERIC_PHY
42 select PINCONF66 select PINCONF
43 select PINMUX67 select PINMUX
drivers/pinctrl/tegra/Makefile+2−0
@@ -8,4 +8,6 @@ obj-$(CONFIG_PINCTRL_TEGRA210) += pinctrl-tegra210.o · 7 unmodified lines
8obj-$(CONFIG_PINCTRL_TEGRA186) += pinctrl-tegra186.o8obj-$(CONFIG_PINCTRL_TEGRA186) += pinctrl-tegra186.o
9obj-$(CONFIG_PINCTRL_TEGRA194) += pinctrl-tegra194.o9obj-$(CONFIG_PINCTRL_TEGRA194) += pinctrl-tegra194.o
10obj-$(CONFIG_PINCTRL_TEGRA234) += pinctrl-tegra234.o10obj-$(CONFIG_PINCTRL_TEGRA234) += pinctrl-tegra234.o
11obj-$(CONFIG_PINCTRL_TEGRA238) += pinctrl-tegra238.o
12obj-$(CONFIG_PINCTRL_TEGRA264) += pinctrl-tegra264.o
11obj-$(CONFIG_PINCTRL_TEGRA_XUSB) += pinctrl-tegra-xusb.o13obj-$(CONFIG_PINCTRL_TEGRA_XUSB) += pinctrl-tegra-xusb.o
drivers/pinctrl/tegra/pinctrl-tegra.c+2−0
@@ -13,6 +13,7 @@ · 12 unmodified lines
13#include <linux/err.h>13#include <linux/err.h>
14#include <linux/init.h>14#include <linux/init.h>
15#include <linux/io.h>15#include <linux/io.h>
16#include <linux/module.h>
16#include <linux/of.h>17#include <linux/of.h>
17#include <linux/platform_device.h>18#include <linux/platform_device.h>
18#include <linux/seq_file.h>19#include <linux/seq_file.h>
@@ -936,3 +937,4 @@ int tegra_pinctrl_probe(struct platform_device *pdev, · 917 unmodified lines
936 937
937 return 0;938 return 0;
938}939}
940EXPORT_SYMBOL_GPL(tegra_pinctrl_probe);
drivers/pinctrl/tegra/pinctrl-tegra238.c+2080−0
@@ -0,0 +1,2080 @@
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Pinctrl data for the NVIDIA Tegra238 pinmux
4 *
5 * Copyright (c) 2022-2026, NVIDIA CORPORATION. All rights reserved.
6 */
7
8#include <linux/mod_devicetable.h>
9#include <linux/module.h>
10#include <linux/platform_device.h>
11#include <linux/property.h>
12#include <linux/pinctrl/pinctrl.h>
13#include <linux/pinctrl/pinmux.h>
14
15#include "pinctrl-tegra.h"
16
17/* Define unique ID for each pins */
18enum {
19 TEGRA_PIN_GPU_PWR_REQ_PA0,
20 TEGRA_PIN_GP_PWM5_PA1,
21 TEGRA_PIN_GP_PWM6_PA2,
22 TEGRA_PIN_SPI3_SCK_PA3,
23 TEGRA_PIN_SPI3_MISO_PA4,
24 TEGRA_PIN_SPI3_MOSI_PA5,
25 TEGRA_PIN_SPI3_CS0_PA6,
26 TEGRA_PIN_SPI3_CS1_PA7,
27 TEGRA_PIN_SPI1_SCK_PB0,
28 TEGRA_PIN_SPI1_MISO_PB1,
29 TEGRA_PIN_SPI1_MOSI_PB2,
30 TEGRA_PIN_SPI1_CS0_PB3,
31 TEGRA_PIN_SPI1_CS1_PB4,
32 TEGRA_PIN_PWR_I2C_SCL_PC0,
33 TEGRA_PIN_PWR_I2C_SDA_PC1,
34 TEGRA_PIN_EXTPERIPH1_CLK_PC2,
35 TEGRA_PIN_EXTPERIPH2_CLK_PC3,
36 TEGRA_PIN_CAM_I2C_SCL_PC4,
37 TEGRA_PIN_CAM_I2C_SDA_PC5,
38 TEGRA_PIN_SOC_GPIO23_PC6,
39 TEGRA_PIN_SOC_GPIO24_PC7,
40 TEGRA_PIN_SOC_GPIO27_PD0,
41 TEGRA_PIN_SOC_GPIO55_PD1,
42 TEGRA_PIN_SOC_GPIO29_PD2,
43 TEGRA_PIN_SOC_GPIO33_PD3,
44 TEGRA_PIN_SOC_GPIO32_PD4,
45 TEGRA_PIN_SOC_GPIO35_PD5,
46 TEGRA_PIN_SOC_GPIO37_PD6,
47 TEGRA_PIN_SOC_GPIO56_PD7,
48 TEGRA_PIN_UART1_TX_PE0,
49 TEGRA_PIN_UART1_RX_PE1,
50 TEGRA_PIN_UART1_RTS_PE2,
51 TEGRA_PIN_UART1_CTS_PE3,
52 TEGRA_PIN_SOC_GPIO13_PF0,
53 TEGRA_PIN_SOC_GPIO14_PF1,
54 TEGRA_PIN_SOC_GPIO15_PF2,
55 TEGRA_PIN_SOC_GPIO16_PF3,
56 TEGRA_PIN_SOC_GPIO17_PF4,
57 TEGRA_PIN_SOC_GPIO18_PF5,
58 TEGRA_PIN_SOC_GPIO20_PF6,
59 TEGRA_PIN_SOC_GPIO21_PF7,
60 TEGRA_PIN_SOC_GPIO22_PG0,
61 TEGRA_PIN_SOC_GPIO06_PG1,
62 TEGRA_PIN_UART4_TX_PG2,
63 TEGRA_PIN_UART4_RX_PG3,
64 TEGRA_PIN_UART4_RTS_PG4,
65 TEGRA_PIN_UART4_CTS_PG5,
66 TEGRA_PIN_SOC_GPIO41_PG6,
67 TEGRA_PIN_SOC_GPIO42_PG7,
68 TEGRA_PIN_SOC_GPIO43_PH0,
69 TEGRA_PIN_SOC_GPIO44_PH1,
70 TEGRA_PIN_GEN1_I2C_SCL_PH2,
71 TEGRA_PIN_GEN1_I2C_SDA_PH3,
72 TEGRA_PIN_CPU_PWR_REQ_PH4,
73 TEGRA_PIN_SOC_GPIO07_PH5,
74 TEGRA_PIN_DAP3_CLK_PJ0,
75 TEGRA_PIN_DAP3_DOUT_PJ1,
76 TEGRA_PIN_DAP3_DIN_PJ2,
77 TEGRA_PIN_DAP3_FS_PJ3,
78 TEGRA_PIN_SOC_GPIO57_PJ4,
79 TEGRA_PIN_SOC_GPIO58_PJ5,
80 TEGRA_PIN_SOC_GPIO59_PJ6,
81 TEGRA_PIN_SOC_GPIO60_PJ7,
82 TEGRA_PIN_SOC_GPIO45_PK0,
83 TEGRA_PIN_SOC_GPIO46_PK1,
84 TEGRA_PIN_SOC_GPIO47_PK2,
85 TEGRA_PIN_SOC_GPIO48_PK3,
86 TEGRA_PIN_QSPI0_SCK_PL0,
87 TEGRA_PIN_QSPI0_IO0_PL1,
88 TEGRA_PIN_QSPI0_IO1_PL2,
89 TEGRA_PIN_QSPI0_CS_N_PL3,
90 TEGRA_PIN_SOC_GPIO152_PL4,
91 TEGRA_PIN_SOC_GPIO153_PL5,
92 TEGRA_PIN_SOC_GPIO154_PL6,
93 TEGRA_PIN_SOC_GPIO155_PL7,
94 TEGRA_PIN_SOC_GPIO156_PM0,
95 TEGRA_PIN_SOC_GPIO157_PM1,
96 TEGRA_PIN_SOC_GPIO158_PM2,
97 TEGRA_PIN_SOC_GPIO159_PM3,
98 TEGRA_PIN_SOC_GPIO160_PM4,
99 TEGRA_PIN_SOC_GPIO161_PM5,
100 TEGRA_PIN_SOC_GPIO162_PM6,
101 TEGRA_PIN_UART7_TX_PM7,
102 TEGRA_PIN_UART7_RX_PN0,
103 TEGRA_PIN_UART7_RTS_PN1,
104 TEGRA_PIN_UART7_CTS_PN2,
105 TEGRA_PIN_SOC_GPIO167_PP0,
106 TEGRA_PIN_SOC_GPIO168_PP1,
107 TEGRA_PIN_SOC_GPIO169_PP2,
108 TEGRA_PIN_SOC_GPIO170_PP3,
109 TEGRA_PIN_DAP4_SCLK_PP4,
110 TEGRA_PIN_DAP4_DOUT_PP5,
111 TEGRA_PIN_DAP4_DIN_PP6,
112 TEGRA_PIN_DAP4_FS_PP7,
113 TEGRA_PIN_SOC_GPIO171_PQ0,
114 TEGRA_PIN_SOC_GPIO172_PQ1,
115 TEGRA_PIN_SOC_GPIO173_PQ2,
116 TEGRA_PIN_SOC_GPIO61_PR0,
117 TEGRA_PIN_SOC_GPIO62_PR1,
118 TEGRA_PIN_SOC_GPIO63_PR2,
119 TEGRA_PIN_SOC_GPIO64_PR3,
120 TEGRA_PIN_SOC_GPIO65_PR4,
121 TEGRA_PIN_SOC_GPIO66_PR5,
122 TEGRA_PIN_SOC_GPIO67_PR6,
123 TEGRA_PIN_SOC_GPIO68_PR7,
124 TEGRA_PIN_GEN4_I2C_SCL_PS0,
125 TEGRA_PIN_GEN4_I2C_SDA_PS1,
126 TEGRA_PIN_SOC_GPIO75_PS2,
127 TEGRA_PIN_GEN7_I2C_SCL_PS3,
128 TEGRA_PIN_GEN7_I2C_SDA_PS4,
129 TEGRA_PIN_SOC_GPIO78_PS5,
130 TEGRA_PIN_GEN9_I2C_SCL_PS6,
131 TEGRA_PIN_GEN9_I2C_SDA_PS7,
132 TEGRA_PIN_SOC_GPIO81_PT0,
133 TEGRA_PIN_SOC_GPIO36_PT1,
134 TEGRA_PIN_SOC_GPIO53_PT2,
135 TEGRA_PIN_SOC_GPIO38_PT3,
136 TEGRA_PIN_SOC_GPIO40_PT4,
137 TEGRA_PIN_SOC_GPIO34_PT5,
138 TEGRA_PIN_USB_VBUS_EN0_PT6,
139 TEGRA_PIN_USB_VBUS_EN1_PT7,
140 TEGRA_PIN_SDMMC1_CLK_PU0,
141 TEGRA_PIN_SDMMC1_CMD_PU1,
142 TEGRA_PIN_SDMMC1_DAT0_PU2,
143 TEGRA_PIN_SDMMC1_DAT1_PU3,
144 TEGRA_PIN_SDMMC1_DAT2_PU4,
145 TEGRA_PIN_SDMMC1_DAT3_PU5,
146 TEGRA_PIN_UFS0_REF_CLK_PV0,
147 TEGRA_PIN_UFS0_RST_N_PV1,
148 TEGRA_PIN_PEX_L0_CLKREQ_N_PW0,
149 TEGRA_PIN_PEX_L0_RST_N_PW1,
150 TEGRA_PIN_PEX_L1_CLKREQ_N_PW2,
151 TEGRA_PIN_PEX_L1_RST_N_PW3,
152 TEGRA_PIN_PEX_L2_CLKREQ_N_PW4,
153 TEGRA_PIN_PEX_L2_RST_N_PW5,
154 TEGRA_PIN_PEX_L3_CLKREQ_N_PW6,
155 TEGRA_PIN_PEX_L3_RST_N_PW7,
156 TEGRA_PIN_PEX_WAKE_N_PX0,
157 TEGRA_PIN_DP_AUX_CH0_HPD_PX1,
158 TEGRA_PIN_SDMMC1_COMP,
159};
160
161enum {
162 TEGRA_PIN_BOOTV_CTL_N_PAA0,
163 TEGRA_PIN_SOC_GPIO00_PAA1,
164 TEGRA_PIN_VCOMP_ALERT_PAA2,
165 TEGRA_PIN_PWM1_PAA3,
166 TEGRA_PIN_BATT_OC_PAA4,
167 TEGRA_PIN_SOC_GPIO04_PAA5,
168 TEGRA_PIN_SOC_GPIO25_PAA6,
169 TEGRA_PIN_SOC_GPIO26_PAA7,
170 TEGRA_PIN_HDMI_CEC_PBB0,
171 TEGRA_PIN_SPI2_SCK_PCC0,
172 TEGRA_PIN_SPI2_MISO_PCC1,
173 TEGRA_PIN_SPI2_MOSI_PCC2,
174 TEGRA_PIN_SPI2_CS0_PCC3,
175 TEGRA_PIN_SPI2_CS1_PCC4,
176 TEGRA_PIN_UART3_TX_PCC5,
177 TEGRA_PIN_UART3_RX_PCC6,
178 TEGRA_PIN_GEN2_I2C_SCL_PCC7,
179 TEGRA_PIN_GEN2_I2C_SDA_PDD0,
180 TEGRA_PIN_GEN8_I2C_SCL_PDD1,
181 TEGRA_PIN_GEN8_I2C_SDA_PDD2,
182 TEGRA_PIN_TOUCH_CLK_PDD3,
183 TEGRA_PIN_DMIC1_CLK_PDD4,
184 TEGRA_PIN_DMIC1_DAT_PDD5,
185 TEGRA_PIN_SOC_GPIO19_PDD6,
186 TEGRA_PIN_PWM2_PDD7,
187 TEGRA_PIN_PWM3_PEE0,
188 TEGRA_PIN_PWM7_PEE1,
189 TEGRA_PIN_SOC_GPIO49_PEE2,
190 TEGRA_PIN_SOC_GPIO82_PEE3,
191 TEGRA_PIN_SOC_GPIO50_PEE4,
192 TEGRA_PIN_SOC_GPIO83_PEE5,
193 TEGRA_PIN_SOC_GPIO69_PFF0,
194 TEGRA_PIN_SOC_GPIO70_PFF1,
195 TEGRA_PIN_SOC_GPIO71_PFF2,
196 TEGRA_PIN_SOC_GPIO72_PFF3,
197 TEGRA_PIN_SOC_GPIO73_PFF4,
198 TEGRA_PIN_SOC_GPIO74_PFF5,
199 TEGRA_PIN_SOC_GPIO80_PFF6,
200 TEGRA_PIN_SOC_GPIO76_PFF7,
201 TEGRA_PIN_SOC_GPIO77_PGG0,
202 TEGRA_PIN_SOC_GPIO84_PGG1,
203 TEGRA_PIN_UART2_TX_PGG2,
204 TEGRA_PIN_UART2_RX_PGG3,
205 TEGRA_PIN_UART2_RTS_PGG4,
206 TEGRA_PIN_UART2_CTS_PGG5,
207 TEGRA_PIN_SOC_GPIO85_PGG6,
208 TEGRA_PIN_UART5_TX_PGG7,
209 TEGRA_PIN_UART5_RX_PHH0,
210 TEGRA_PIN_UART5_RTS_PHH1,
211 TEGRA_PIN_UART5_CTS_PHH2,
212 TEGRA_PIN_SOC_GPIO86_PHH3,
213};
214
215/* Table for pin descriptor */
216static const struct pinctrl_pin_desc tegra238_pins[] = {
217 PINCTRL_PIN(TEGRA_PIN_GPU_PWR_REQ_PA0, "GPU_PWR_REQ_PA0"),
218 PINCTRL_PIN(TEGRA_PIN_GP_PWM5_PA1, "GP_PWM5_PA1"),
219 PINCTRL_PIN(TEGRA_PIN_GP_PWM6_PA2, "GP_PWM6_PA2"),
220 PINCTRL_PIN(TEGRA_PIN_SPI3_SCK_PA3, "SPI3_SCK_PA3"),
221 PINCTRL_PIN(TEGRA_PIN_SPI3_MISO_PA4, "SPI3_MISO_PA4"),
222 PINCTRL_PIN(TEGRA_PIN_SPI3_MOSI_PA5, "SPI3_MOSI_PA5"),
223 PINCTRL_PIN(TEGRA_PIN_SPI3_CS0_PA6, "SPI3_CS0_PA6"),
224 PINCTRL_PIN(TEGRA_PIN_SPI3_CS1_PA7, "SPI3_CS1_PA7"),
225 PINCTRL_PIN(TEGRA_PIN_SPI1_SCK_PB0, "SPI1_SCK_PB0"),
226 PINCTRL_PIN(TEGRA_PIN_SPI1_MISO_PB1, "SPI1_MISO_PB1"),
227 PINCTRL_PIN(TEGRA_PIN_SPI1_MOSI_PB2, "SPI1_MOSI_PB2"),
228 PINCTRL_PIN(TEGRA_PIN_SPI1_CS0_PB3, "SPI1_CS0_PB3"),
229 PINCTRL_PIN(TEGRA_PIN_SPI1_CS1_PB4, "SPI1_CS1_PB4"),
230 PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SCL_PC0, "PWR_I2C_SCL_PC0"),
231 PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SDA_PC1, "PWR_I2C_SDA_PC1"),
232 PINCTRL_PIN(TEGRA_PIN_EXTPERIPH1_CLK_PC2, "EXTPERIPH1_CLK_PC2"),
233 PINCTRL_PIN(TEGRA_PIN_EXTPERIPH2_CLK_PC3, "EXTPERIPH2_CLK_PC3"),
234 PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SCL_PC4, "CAM_I2C_SCL_PC4"),
235 PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SDA_PC5, "CAM_I2C_SDA_PC5"),
236 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO23_PC6, "SOC_GPIO23_PC6"),
237 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO24_PC7, "SOC_GPIO24_PC7"),
238 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO27_PD0, "SOC_GPIO27_PD0"),
239 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO55_PD1, "SOC_GPIO55_PD1"),
240 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO29_PD2, "SOC_GPIO29_PD2"),
241 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO33_PD3, "SOC_GPIO33_PD3"),
242 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO32_PD4, "SOC_GPIO32_PD4"),
243 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO35_PD5, "SOC_GPIO35_PD5"),
244 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO37_PD6, "SOC_GPIO37_PD6"),
245 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO56_PD7, "SOC_GPIO56_PD7"),
246 PINCTRL_PIN(TEGRA_PIN_UART1_TX_PE0, "UART1_TX_PE0"),
247 PINCTRL_PIN(TEGRA_PIN_UART1_RX_PE1, "UART1_RX_PE1"),
248 PINCTRL_PIN(TEGRA_PIN_UART1_RTS_PE2, "UART1_RTS_PE2"),
249 PINCTRL_PIN(TEGRA_PIN_UART1_CTS_PE3, "UART1_CTS_PE3"),
250 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO13_PF0, "SOC_GPIO13_PF0"),
251 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO14_PF1, "SOC_GPIO14_PF1"),
252 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO15_PF2, "SOC_GPIO15_PF2"),
253 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO16_PF3, "SOC_GPIO16_PF3"),
254 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO17_PF4, "SOC_GPIO17_PF4"),
255 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO18_PF5, "SOC_GPIO18_PF5"),
256 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO20_PF6, "SOC_GPIO20_PF6"),
257 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO21_PF7, "SOC_GPIO21_PF7"),
258 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO22_PG0, "SOC_GPIO22_PG0"),
259 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO06_PG1, "SOC_GPIO06_PG1"),
260 PINCTRL_PIN(TEGRA_PIN_UART4_TX_PG2, "UART4_TX_PG2"),
261 PINCTRL_PIN(TEGRA_PIN_UART4_RX_PG3, "UART4_RX_PG3"),
262 PINCTRL_PIN(TEGRA_PIN_UART4_RTS_PG4, "UART4_RTS_PG4"),
263 PINCTRL_PIN(TEGRA_PIN_UART4_CTS_PG5, "UART4_CTS_PG5"),
264 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO41_PG6, "SOC_GPIO41_PG6"),
265 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO42_PG7, "SOC_GPIO42_PG7"),
266 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO43_PH0, "SOC_GPIO43_PH0"),
267 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO44_PH1, "SOC_GPIO44_PH1"),
268 PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SCL_PH2, "GEN1_I2C_SCL_PH2"),
269 PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SDA_PH3, "GEN1_I2C_SDA_PH3"),
270 PINCTRL_PIN(TEGRA_PIN_CPU_PWR_REQ_PH4, "CPU_PWR_REQ_PH4"),
271 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO07_PH5, "SOC_GPIO07_PH5"),
272 PINCTRL_PIN(TEGRA_PIN_DAP3_CLK_PJ0, "DAP3_CLK_PJ0"),
273 PINCTRL_PIN(TEGRA_PIN_DAP3_DOUT_PJ1, "DAP3_DOUT_PJ1"),
274 PINCTRL_PIN(TEGRA_PIN_DAP3_DIN_PJ2, "DAP3_DIN_PJ2"),
275 PINCTRL_PIN(TEGRA_PIN_DAP3_FS_PJ3, "DAP3_FS_PJ3"),
276 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO57_PJ4, "SOC_GPIO57_PJ4"),
277 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO58_PJ5, "SOC_GPIO58_PJ5"),
278 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO59_PJ6, "SOC_GPIO59_PJ6"),
279 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO60_PJ7, "SOC_GPIO60_PJ7"),
280 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO45_PK0, "SOC_GPIO45_PK0"),
281 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO46_PK1, "SOC_GPIO46_PK1"),
282 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO47_PK2, "SOC_GPIO47_PK2"),
283 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO48_PK3, "SOC_GPIO48_PK3"),
284 PINCTRL_PIN(TEGRA_PIN_QSPI0_SCK_PL0, "QSPI0_SCK_PL0"),
285 PINCTRL_PIN(TEGRA_PIN_QSPI0_IO0_PL1, "QSPI0_IO0_PL1"),
286 PINCTRL_PIN(TEGRA_PIN_QSPI0_IO1_PL2, "QSPI0_IO1_PL2"),
287 PINCTRL_PIN(TEGRA_PIN_QSPI0_CS_N_PL3, "QSPI0_CS_N_PL3"),
288 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO152_PL4, "SOC_GPIO152_PL4"),
289 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO153_PL5, "SOC_GPIO153_PL5"),
290 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO154_PL6, "SOC_GPIO154_PL6"),
291 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO155_PL7, "SOC_GPIO155_PL7"),
292 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO156_PM0, "SOC_GPIO156_PM0"),
293 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO157_PM1, "SOC_GPIO157_PM1"),
294 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO158_PM2, "SOC_GPIO158_PM2"),
295 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO159_PM3, "SOC_GPIO159_PM3"),
296 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO160_PM4, "SOC_GPIO160_PM4"),
297 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO161_PM5, "SOC_GPIO161_PM5"),
298 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO162_PM6, "SOC_GPIO162_PM6"),
299 PINCTRL_PIN(TEGRA_PIN_UART7_TX_PM7, "UART7_TX_PM7"),
300 PINCTRL_PIN(TEGRA_PIN_UART7_RX_PN0, "UART7_RX_PN0"),
301 PINCTRL_PIN(TEGRA_PIN_UART7_RTS_PN1, "UART7_RTS_PN1"),
302 PINCTRL_PIN(TEGRA_PIN_UART7_CTS_PN2, "UART7_CTS_PN2"),
303 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO167_PP0, "SOC_GPIO167_PP0"),
304 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO168_PP1, "SOC_GPIO168_PP1"),
305 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO169_PP2, "SOC_GPIO169_PP2"),
306 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO170_PP3, "SOC_GPIO170_PP3"),
307 PINCTRL_PIN(TEGRA_PIN_DAP4_SCLK_PP4, "DAP4_SCLK_PP4"),
308 PINCTRL_PIN(TEGRA_PIN_DAP4_DOUT_PP5, "DAP4_DOUT_PP5"),
309 PINCTRL_PIN(TEGRA_PIN_DAP4_DIN_PP6, "DAP4_DIN_PP6"),
310 PINCTRL_PIN(TEGRA_PIN_DAP4_FS_PP7, "DAP4_FS_PP7"),
311 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO171_PQ0, "SOC_GPIO171_PQ0"),
312 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO172_PQ1, "SOC_GPIO172_PQ1"),
313 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO173_PQ2, "SOC_GPIO173_PQ2"),
314 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO61_PR0, "SOC_GPIO61_PR0"),
315 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO62_PR1, "SOC_GPIO62_PR1"),
316 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO63_PR2, "SOC_GPIO63_PR2"),
317 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO64_PR3, "SOC_GPIO64_PR3"),
318 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO65_PR4, "SOC_GPIO65_PR4"),
319 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO66_PR5, "SOC_GPIO66_PR5"),
320 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO67_PR6, "SOC_GPIO67_PR6"),
321 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO68_PR7, "SOC_GPIO68_PR7"),
322 PINCTRL_PIN(TEGRA_PIN_GEN4_I2C_SCL_PS0, "GEN4_I2C_SCL_PS0"),
323 PINCTRL_PIN(TEGRA_PIN_GEN4_I2C_SDA_PS1, "GEN4_I2C_SDA_PS1"),
324 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO75_PS2, "SOC_GPIO75_PS2"),
325 PINCTRL_PIN(TEGRA_PIN_GEN7_I2C_SCL_PS3, "GEN7_I2C_SCL_PS3"),
326 PINCTRL_PIN(TEGRA_PIN_GEN7_I2C_SDA_PS4, "GEN7_I2C_SDA_PS4"),
327 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO78_PS5, "SOC_GPIO78_PS5"),
328 PINCTRL_PIN(TEGRA_PIN_GEN9_I2C_SCL_PS6, "GEN9_I2C_SCL_PS6"),
329 PINCTRL_PIN(TEGRA_PIN_GEN9_I2C_SDA_PS7, "GEN9_I2C_SDA_PS7"),
330 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO81_PT0, "SOC_GPIO81_PT0"),
331 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO36_PT1, "SOC_GPIO36_PT1"),
332 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO53_PT2, "SOC_GPIO53_PT2"),
333 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO38_PT3, "SOC_GPIO38_PT3"),
334 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO40_PT4, "SOC_GPIO40_PT4"),
335 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO34_PT5, "SOC_GPIO34_PT5"),
336 PINCTRL_PIN(TEGRA_PIN_USB_VBUS_EN0_PT6, "USB_VBUS_EN0_PT6"),
337 PINCTRL_PIN(TEGRA_PIN_USB_VBUS_EN1_PT7, "USB_VBUS_EN1_PT7"),
338 PINCTRL_PIN(TEGRA_PIN_SDMMC1_CLK_PU0, "SDMMC1_CLK_PU0"),
339 PINCTRL_PIN(TEGRA_PIN_SDMMC1_CMD_PU1, "SDMMC1_CMD_PU1"),
340 PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT0_PU2, "SDMMC1_DAT0_PU2"),
341 PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT1_PU3, "SDMMC1_DAT1_PU3"),
342 PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT2_PU4, "SDMMC1_DAT2_PU4"),
343 PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT3_PU5, "SDMMC1_DAT3_PU5"),
344 PINCTRL_PIN(TEGRA_PIN_UFS0_REF_CLK_PV0, "UFS0_REF_CLK_PV0"),
345 PINCTRL_PIN(TEGRA_PIN_UFS0_RST_N_PV1, "UFS0_RST_N_PV1"),
346 PINCTRL_PIN(TEGRA_PIN_PEX_L0_CLKREQ_N_PW0, "PEX_L0_CLKREQ_N_PW0"),
347 PINCTRL_PIN(TEGRA_PIN_PEX_L0_RST_N_PW1, "PEX_L0_RST_N_PW1"),
348 PINCTRL_PIN(TEGRA_PIN_PEX_L1_CLKREQ_N_PW2, "PEX_L1_CLKREQ_N_PW2"),
349 PINCTRL_PIN(TEGRA_PIN_PEX_L1_RST_N_PW3, "PEX_L1_RST_N_PW3"),
350 PINCTRL_PIN(TEGRA_PIN_PEX_L2_CLKREQ_N_PW4, "PEX_L2_CLKREQ_N_PW4"),
351 PINCTRL_PIN(TEGRA_PIN_PEX_L2_RST_N_PW5, "PEX_L2_RST_N_PW5"),
352 PINCTRL_PIN(TEGRA_PIN_PEX_L3_CLKREQ_N_PW6, "PEX_L3_CLKREQ_N_PW6"),
353 PINCTRL_PIN(TEGRA_PIN_PEX_L3_RST_N_PW7, "PEX_L3_RST_N_PW7"),
354 PINCTRL_PIN(TEGRA_PIN_PEX_WAKE_N_PX0, "PEX_WAKE_N_PX0"),
355 PINCTRL_PIN(TEGRA_PIN_DP_AUX_CH0_HPD_PX1, "DP_AUX_CH0_HPD_PX1"),
356 PINCTRL_PIN(TEGRA_PIN_SDMMC1_COMP, "SDMMC1_COMP"),
357};
358
359static const struct pinctrl_pin_desc tegra238_aon_pins[] = {
360 PINCTRL_PIN(TEGRA_PIN_BOOTV_CTL_N_PAA0, "BOOTV_CTL_N_PAA0"),
361 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO00_PAA1, "SOC_GPIO00_PAA1"),
362 PINCTRL_PIN(TEGRA_PIN_VCOMP_ALERT_PAA2, "VCOMP_ALERT_PAA2"),
363 PINCTRL_PIN(TEGRA_PIN_PWM1_PAA3, "PWM1_PAA3"),
364 PINCTRL_PIN(TEGRA_PIN_BATT_OC_PAA4, "BATT_OC_PAA4"),
365 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO04_PAA5, "SOC_GPIO04_PAA5"),
366 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO25_PAA6, "SOC_GPIO25_PAA6"),
367 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO26_PAA7, "SOC_GPIO26_PAA7"),
368 PINCTRL_PIN(TEGRA_PIN_HDMI_CEC_PBB0, "HDMI_CEC_PBB0"),
369 PINCTRL_PIN(TEGRA_PIN_SPI2_SCK_PCC0, "SPI2_SCK_PCC0"),
370 PINCTRL_PIN(TEGRA_PIN_SPI2_MISO_PCC1, "SPI2_MISO_PCC1"),
371 PINCTRL_PIN(TEGRA_PIN_SPI2_MOSI_PCC2, "SPI2_MOSI_PCC2"),
372 PINCTRL_PIN(TEGRA_PIN_SPI2_CS0_PCC3, "SPI2_CS0_PCC3"),
373 PINCTRL_PIN(TEGRA_PIN_SPI2_CS1_PCC4, "SPI2_CS1_PCC4"),
374 PINCTRL_PIN(TEGRA_PIN_UART3_TX_PCC5, "UART3_TX_PCC5"),
375 PINCTRL_PIN(TEGRA_PIN_UART3_RX_PCC6, "UART3_RX_PCC6"),
376 PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SCL_PCC7, "GEN2_I2C_SCL_PCC7"),
377 PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SDA_PDD0, "GEN2_I2C_SDA_PDD0"),
378 PINCTRL_PIN(TEGRA_PIN_GEN8_I2C_SCL_PDD1, "GEN8_I2C_SCL_PDD1"),
379 PINCTRL_PIN(TEGRA_PIN_GEN8_I2C_SDA_PDD2, "GEN8_I2C_SDA_PDD2"),
380 PINCTRL_PIN(TEGRA_PIN_TOUCH_CLK_PDD3, "TOUCH_CLK_PDD3"),
381 PINCTRL_PIN(TEGRA_PIN_DMIC1_CLK_PDD4, "DMIC1_CLK_PDD4"),
382 PINCTRL_PIN(TEGRA_PIN_DMIC1_DAT_PDD5, "DMIC1_DAT_PDD5"),
383 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO19_PDD6, "SOC_GPIO19_PDD6"),
384 PINCTRL_PIN(TEGRA_PIN_PWM2_PDD7, "PWM2_PDD7"),
385 PINCTRL_PIN(TEGRA_PIN_PWM3_PEE0, "PWM3_PEE0"),
386 PINCTRL_PIN(TEGRA_PIN_PWM7_PEE1, "PWM7_PEE1"),
387 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO49_PEE2, "SOC_GPIO49_PEE2"),
388 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO82_PEE3, "SOC_GPIO82_PEE3"),
389 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO50_PEE4, "SOC_GPIO50_PEE4"),
390 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO83_PEE5, "SOC_GPIO83_PEE5"),
391 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO69_PFF0, "SOC_GPIO69_PFF0"),
392 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO70_PFF1, "SOC_GPIO70_PFF1"),
393 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO71_PFF2, "SOC_GPIO71_PFF2"),
394 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO72_PFF3, "SOC_GPIO72_PFF3"),
395 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO73_PFF4, "SOC_GPIO73_PFF4"),
396 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO74_PFF5, "SOC_GPIO74_PFF5"),
397 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO80_PFF6, "SOC_GPIO80_PFF6"),
398 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO76_PFF7, "SOC_GPIO76_PFF7"),
399 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO77_PGG0, "SOC_GPIO77_PGG0"),
400 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO84_PGG1, "SOC_GPIO84_PGG1"),
401 PINCTRL_PIN(TEGRA_PIN_UART2_TX_PGG2, "UART2_TX_PGG2"),
402 PINCTRL_PIN(TEGRA_PIN_UART2_RX_PGG3, "UART2_RX_PGG3"),
403 PINCTRL_PIN(TEGRA_PIN_UART2_RTS_PGG4, "UART2_RTS_PGG4"),
404 PINCTRL_PIN(TEGRA_PIN_UART2_CTS_PGG5, "UART2_CTS_PGG5"),
405 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO85_PGG6, "SOC_GPIO85_PGG6"),
406 PINCTRL_PIN(TEGRA_PIN_UART5_TX_PGG7, "UART5_TX_PGG7"),
407 PINCTRL_PIN(TEGRA_PIN_UART5_RX_PHH0, "UART5_RX_PHH0"),
408 PINCTRL_PIN(TEGRA_PIN_UART5_RTS_PHH1, "UART5_RTS_PHH1"),
409 PINCTRL_PIN(TEGRA_PIN_UART5_CTS_PHH2, "UART5_CTS_PHH2"),
410 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO86_PHH3, "SOC_GPIO86_PHH3"),
411};
412
413static const unsigned int gpu_pwr_req_pa0_pins[] = {
414 TEGRA_PIN_GPU_PWR_REQ_PA0,
415};
416
417static const unsigned int gp_pwm5_pa1_pins[] = {
418 TEGRA_PIN_GP_PWM5_PA1,
419};
420
421static const unsigned int gp_pwm6_pa2_pins[] = {
422 TEGRA_PIN_GP_PWM6_PA2,
423};
424
425static const unsigned int spi3_sck_pa3_pins[] = {
426 TEGRA_PIN_SPI3_SCK_PA3,
427};
428
429static const unsigned int spi3_miso_pa4_pins[] = {
430 TEGRA_PIN_SPI3_MISO_PA4,
431};
432
433static const unsigned int spi3_mosi_pa5_pins[] = {
434 TEGRA_PIN_SPI3_MOSI_PA5,
435};
436
437static const unsigned int spi3_cs0_pa6_pins[] = {
438 TEGRA_PIN_SPI3_CS0_PA6,
439};
440
441static const unsigned int spi3_cs1_pa7_pins[] = {
442 TEGRA_PIN_SPI3_CS1_PA7,
443};
444
445static const unsigned int spi1_sck_pb0_pins[] = {
446 TEGRA_PIN_SPI1_SCK_PB0,
447};
448
449static const unsigned int spi1_miso_pb1_pins[] = {
450 TEGRA_PIN_SPI1_MISO_PB1,
451};
452
453static const unsigned int spi1_mosi_pb2_pins[] = {
454 TEGRA_PIN_SPI1_MOSI_PB2,
455};
456
457static const unsigned int spi1_cs0_pb3_pins[] = {
458 TEGRA_PIN_SPI1_CS0_PB3,
459};
460
461static const unsigned int spi1_cs1_pb4_pins[] = {
462 TEGRA_PIN_SPI1_CS1_PB4,
463};
464
465static const unsigned int pwr_i2c_scl_pc0_pins[] = {
466 TEGRA_PIN_PWR_I2C_SCL_PC0,
467};
468
469static const unsigned int pwr_i2c_sda_pc1_pins[] = {
470 TEGRA_PIN_PWR_I2C_SDA_PC1,
471};
472
473static const unsigned int extperiph1_clk_pc2_pins[] = {
474 TEGRA_PIN_EXTPERIPH1_CLK_PC2,
475};
476
477static const unsigned int extperiph2_clk_pc3_pins[] = {
478 TEGRA_PIN_EXTPERIPH2_CLK_PC3,
479};
480
481static const unsigned int cam_i2c_scl_pc4_pins[] = {
482 TEGRA_PIN_CAM_I2C_SCL_PC4,
483};
484
485static const unsigned int cam_i2c_sda_pc5_pins[] = {
486 TEGRA_PIN_CAM_I2C_SDA_PC5,
487};
488
489static const unsigned int soc_gpio23_pc6_pins[] = {
490 TEGRA_PIN_SOC_GPIO23_PC6,
491};
492
493static const unsigned int soc_gpio24_pc7_pins[] = {
494 TEGRA_PIN_SOC_GPIO24_PC7,
495};
496
497static const unsigned int soc_gpio27_pd0_pins[] = {
498 TEGRA_PIN_SOC_GPIO27_PD0,
499};
500
501static const unsigned int soc_gpio55_pd1_pins[] = {
502 TEGRA_PIN_SOC_GPIO55_PD1,
503};
504
505static const unsigned int soc_gpio29_pd2_pins[] = {
506 TEGRA_PIN_SOC_GPIO29_PD2,
507};
508
509static const unsigned int soc_gpio33_pd3_pins[] = {
510 TEGRA_PIN_SOC_GPIO33_PD3,
511};
512
513static const unsigned int soc_gpio32_pd4_pins[] = {
514 TEGRA_PIN_SOC_GPIO32_PD4,
515};
516
517static const unsigned int soc_gpio35_pd5_pins[] = {
518 TEGRA_PIN_SOC_GPIO35_PD5,
519};
520
521static const unsigned int soc_gpio37_pd6_pins[] = {
522 TEGRA_PIN_SOC_GPIO37_PD6,
523};
524
525static const unsigned int soc_gpio56_pd7_pins[] = {
526 TEGRA_PIN_SOC_GPIO56_PD7,
527};
528
529static const unsigned int uart1_tx_pe0_pins[] = {
530 TEGRA_PIN_UART1_TX_PE0,
531};
532
533static const unsigned int uart1_rx_pe1_pins[] = {
534 TEGRA_PIN_UART1_RX_PE1,
535};
536
537static const unsigned int uart1_rts_pe2_pins[] = {
538 TEGRA_PIN_UART1_RTS_PE2,
539};
540
541static const unsigned int uart1_cts_pe3_pins[] = {
542 TEGRA_PIN_UART1_CTS_PE3,
543};
544
545static const unsigned int soc_gpio13_pf0_pins[] = {
546 TEGRA_PIN_SOC_GPIO13_PF0,
547};
548
549static const unsigned int soc_gpio14_pf1_pins[] = {
550 TEGRA_PIN_SOC_GPIO14_PF1,
551};
552
553static const unsigned int soc_gpio15_pf2_pins[] = {
554 TEGRA_PIN_SOC_GPIO15_PF2,
555};
556
557static const unsigned int soc_gpio16_pf3_pins[] = {
558 TEGRA_PIN_SOC_GPIO16_PF3,
559};
560
561static const unsigned int soc_gpio17_pf4_pins[] = {
562 TEGRA_PIN_SOC_GPIO17_PF4,
563};
564
565static const unsigned int soc_gpio18_pf5_pins[] = {
566 TEGRA_PIN_SOC_GPIO18_PF5,
567};
568
569static const unsigned int soc_gpio20_pf6_pins[] = {
570 TEGRA_PIN_SOC_GPIO20_PF6,
571};
572
573static const unsigned int soc_gpio21_pf7_pins[] = {
574 TEGRA_PIN_SOC_GPIO21_PF7,
575};
576
577static const unsigned int soc_gpio22_pg0_pins[] = {
578 TEGRA_PIN_SOC_GPIO22_PG0,
579};
580
581static const unsigned int soc_gpio06_pg1_pins[] = {
582 TEGRA_PIN_SOC_GPIO06_PG1,
583};
584
585static const unsigned int uart4_tx_pg2_pins[] = {
586 TEGRA_PIN_UART4_TX_PG2,
587};
588
589static const unsigned int uart4_rx_pg3_pins[] = {
590 TEGRA_PIN_UART4_RX_PG3,
591};
592
593static const unsigned int uart4_rts_pg4_pins[] = {
594 TEGRA_PIN_UART4_RTS_PG4,
595};
596
597static const unsigned int uart4_cts_pg5_pins[] = {
598 TEGRA_PIN_UART4_CTS_PG5,
599};
600
601static const unsigned int soc_gpio41_pg6_pins[] = {
602 TEGRA_PIN_SOC_GPIO41_PG6,
603};
604
605static const unsigned int soc_gpio42_pg7_pins[] = {
606 TEGRA_PIN_SOC_GPIO42_PG7,
607};
608
609static const unsigned int soc_gpio43_ph0_pins[] = {
610 TEGRA_PIN_SOC_GPIO43_PH0,
611};
612
613static const unsigned int soc_gpio44_ph1_pins[] = {
614 TEGRA_PIN_SOC_GPIO44_PH1,
615};
616
617static const unsigned int gen1_i2c_scl_ph2_pins[] = {
618 TEGRA_PIN_GEN1_I2C_SCL_PH2,
619};
620
621static const unsigned int gen1_i2c_sda_ph3_pins[] = {
622 TEGRA_PIN_GEN1_I2C_SDA_PH3,
623};
624
625static const unsigned int cpu_pwr_req_ph4_pins[] = {
626 TEGRA_PIN_CPU_PWR_REQ_PH4,
627};
628
629static const unsigned int soc_gpio07_ph5_pins[] = {
630 TEGRA_PIN_SOC_GPIO07_PH5,
631};
632
633static const unsigned int dap3_clk_pj0_pins[] = {
634 TEGRA_PIN_DAP3_CLK_PJ0,
635};
636
637static const unsigned int dap3_dout_pj1_pins[] = {
638 TEGRA_PIN_DAP3_DOUT_PJ1,
639};
640
641static const unsigned int dap3_din_pj2_pins[] = {
642 TEGRA_PIN_DAP3_DIN_PJ2,
643};
644
645static const unsigned int dap3_fs_pj3_pins[] = {
646 TEGRA_PIN_DAP3_FS_PJ3,
647};
648
649static const unsigned int soc_gpio57_pj4_pins[] = {
650 TEGRA_PIN_SOC_GPIO57_PJ4,
651};
652
653static const unsigned int soc_gpio58_pj5_pins[] = {
654 TEGRA_PIN_SOC_GPIO58_PJ5,
655};
656
657static const unsigned int soc_gpio59_pj6_pins[] = {
658 TEGRA_PIN_SOC_GPIO59_PJ6,
659};
660
661static const unsigned int soc_gpio60_pj7_pins[] = {
662 TEGRA_PIN_SOC_GPIO60_PJ7,
663};
664
665static const unsigned int soc_gpio45_pk0_pins[] = {
666 TEGRA_PIN_SOC_GPIO45_PK0,
667};
668
669static const unsigned int soc_gpio46_pk1_pins[] = {
670 TEGRA_PIN_SOC_GPIO46_PK1,
671};
672
673static const unsigned int soc_gpio47_pk2_pins[] = {
674 TEGRA_PIN_SOC_GPIO47_PK2,
675};
676
677static const unsigned int soc_gpio48_pk3_pins[] = {
678 TEGRA_PIN_SOC_GPIO48_PK3,
679};
680
681static const unsigned int qspi0_sck_pl0_pins[] = {
682 TEGRA_PIN_QSPI0_SCK_PL0,
683};
684
685static const unsigned int qspi0_io0_pl1_pins[] = {
686 TEGRA_PIN_QSPI0_IO0_PL1,
687};
688
689static const unsigned int qspi0_io1_pl2_pins[] = {
690 TEGRA_PIN_QSPI0_IO1_PL2,
691};
692
693static const unsigned int qspi0_cs_n_pl3_pins[] = {
694 TEGRA_PIN_QSPI0_CS_N_PL3,
695};
696
697static const unsigned int soc_gpio152_pl4_pins[] = {
698 TEGRA_PIN_SOC_GPIO152_PL4,
699};
700
701static const unsigned int soc_gpio153_pl5_pins[] = {
702 TEGRA_PIN_SOC_GPIO153_PL5,
703};
704
705static const unsigned int soc_gpio154_pl6_pins[] = {
706 TEGRA_PIN_SOC_GPIO154_PL6,
707};
708
709static const unsigned int soc_gpio155_pl7_pins[] = {
710 TEGRA_PIN_SOC_GPIO155_PL7,
711};
712
713static const unsigned int soc_gpio156_pm0_pins[] = {
714 TEGRA_PIN_SOC_GPIO156_PM0,
715};
716
717static const unsigned int soc_gpio157_pm1_pins[] = {
718 TEGRA_PIN_SOC_GPIO157_PM1,
719};
720
721static const unsigned int soc_gpio158_pm2_pins[] = {
722 TEGRA_PIN_SOC_GPIO158_PM2,
723};
724
725static const unsigned int soc_gpio159_pm3_pins[] = {
726 TEGRA_PIN_SOC_GPIO159_PM3,
727};
728
729static const unsigned int soc_gpio160_pm4_pins[] = {
730 TEGRA_PIN_SOC_GPIO160_PM4,
731};
732
733static const unsigned int soc_gpio161_pm5_pins[] = {
734 TEGRA_PIN_SOC_GPIO161_PM5,
735};
736
737static const unsigned int soc_gpio162_pm6_pins[] = {
738 TEGRA_PIN_SOC_GPIO162_PM6,
739};
740
741static const unsigned int uart7_tx_pm7_pins[] = {
742 TEGRA_PIN_UART7_TX_PM7,
743};
744
745static const unsigned int uart7_rx_pn0_pins[] = {
746 TEGRA_PIN_UART7_RX_PN0,
747};
748
749static const unsigned int uart7_rts_pn1_pins[] = {
750 TEGRA_PIN_UART7_RTS_PN1,
751};
752
753static const unsigned int uart7_cts_pn2_pins[] = {
754 TEGRA_PIN_UART7_CTS_PN2,
755};
756
757static const unsigned int soc_gpio167_pp0_pins[] = {
758 TEGRA_PIN_SOC_GPIO167_PP0,
759};
760
761static const unsigned int soc_gpio168_pp1_pins[] = {
762 TEGRA_PIN_SOC_GPIO168_PP1,
763};
764
765static const unsigned int soc_gpio169_pp2_pins[] = {
766 TEGRA_PIN_SOC_GPIO169_PP2,
767};
768
769static const unsigned int soc_gpio170_pp3_pins[] = {
770 TEGRA_PIN_SOC_GPIO170_PP3,
771};
772
773static const unsigned int dap4_sclk_pp4_pins[] = {
774 TEGRA_PIN_DAP4_SCLK_PP4,
775};
776
777static const unsigned int dap4_dout_pp5_pins[] = {
778 TEGRA_PIN_DAP4_DOUT_PP5,
779};
780
781static const unsigned int dap4_din_pp6_pins[] = {
782 TEGRA_PIN_DAP4_DIN_PP6,
783};
784
785static const unsigned int dap4_fs_pp7_pins[] = {
786 TEGRA_PIN_DAP4_FS_PP7,
787};
788
789static const unsigned int soc_gpio171_pq0_pins[] = {
790 TEGRA_PIN_SOC_GPIO171_PQ0,
791};
792
793static const unsigned int soc_gpio172_pq1_pins[] = {
794 TEGRA_PIN_SOC_GPIO172_PQ1,
795};
796
797static const unsigned int soc_gpio173_pq2_pins[] = {
798 TEGRA_PIN_SOC_GPIO173_PQ2,
799};
800
801static const unsigned int soc_gpio61_pr0_pins[] = {
802 TEGRA_PIN_SOC_GPIO61_PR0,
803};
804
805static const unsigned int soc_gpio62_pr1_pins[] = {
806 TEGRA_PIN_SOC_GPIO62_PR1,
807};
808
809static const unsigned int soc_gpio63_pr2_pins[] = {
810 TEGRA_PIN_SOC_GPIO63_PR2,
811};
812
813static const unsigned int soc_gpio64_pr3_pins[] = {
814 TEGRA_PIN_SOC_GPIO64_PR3,
815};
816
817static const unsigned int soc_gpio65_pr4_pins[] = {
818 TEGRA_PIN_SOC_GPIO65_PR4,
819};
820
821static const unsigned int soc_gpio66_pr5_pins[] = {
822 TEGRA_PIN_SOC_GPIO66_PR5,
823};
824
825static const unsigned int soc_gpio67_pr6_pins[] = {
826 TEGRA_PIN_SOC_GPIO67_PR6,
827};
828
829static const unsigned int soc_gpio68_pr7_pins[] = {
830 TEGRA_PIN_SOC_GPIO68_PR7,
831};
832
833static const unsigned int gen4_i2c_scl_ps0_pins[] = {
834 TEGRA_PIN_GEN4_I2C_SCL_PS0,
835};
836
837static const unsigned int gen4_i2c_sda_ps1_pins[] = {
838 TEGRA_PIN_GEN4_I2C_SDA_PS1,
839};
840
841static const unsigned int soc_gpio75_ps2_pins[] = {
842 TEGRA_PIN_SOC_GPIO75_PS2,
843};
844
845static const unsigned int gen7_i2c_scl_ps3_pins[] = {
846 TEGRA_PIN_GEN7_I2C_SCL_PS3,
847};
848
849static const unsigned int gen7_i2c_sda_ps4_pins[] = {
850 TEGRA_PIN_GEN7_I2C_SDA_PS4,
851};
852
853static const unsigned int soc_gpio78_ps5_pins[] = {
854 TEGRA_PIN_SOC_GPIO78_PS5,
855};
856
857static const unsigned int gen9_i2c_scl_ps6_pins[] = {
858 TEGRA_PIN_GEN9_I2C_SCL_PS6,
859};
860
861static const unsigned int gen9_i2c_sda_ps7_pins[] = {
862 TEGRA_PIN_GEN9_I2C_SDA_PS7,
863};
864
865static const unsigned int soc_gpio81_pt0_pins[] = {
866 TEGRA_PIN_SOC_GPIO81_PT0,
867};
868
869static const unsigned int soc_gpio36_pt1_pins[] = {
870 TEGRA_PIN_SOC_GPIO36_PT1,
871};
872
873static const unsigned int soc_gpio53_pt2_pins[] = {
874 TEGRA_PIN_SOC_GPIO53_PT2,
875};
876
877static const unsigned int soc_gpio38_pt3_pins[] = {
878 TEGRA_PIN_SOC_GPIO38_PT3,
879};
880
881static const unsigned int soc_gpio40_pt4_pins[] = {
882 TEGRA_PIN_SOC_GPIO40_PT4,
883};
884
885static const unsigned int soc_gpio34_pt5_pins[] = {
886 TEGRA_PIN_SOC_GPIO34_PT5,
887};
888
889static const unsigned int usb_vbus_en0_pt6_pins[] = {
890 TEGRA_PIN_USB_VBUS_EN0_PT6,
891};
892
893static const unsigned int usb_vbus_en1_pt7_pins[] = {
894 TEGRA_PIN_USB_VBUS_EN1_PT7,
895};
896
897static const unsigned int sdmmc1_clk_pu0_pins[] = {
898 TEGRA_PIN_SDMMC1_CLK_PU0,
899};
900
901static const unsigned int sdmmc1_cmd_pu1_pins[] = {
902 TEGRA_PIN_SDMMC1_CMD_PU1,
903};
904
905static const unsigned int sdmmc1_dat0_pu2_pins[] = {
906 TEGRA_PIN_SDMMC1_DAT0_PU2,
907};
908
909static const unsigned int sdmmc1_dat1_pu3_pins[] = {
910 TEGRA_PIN_SDMMC1_DAT1_PU3,
911};
912
913static const unsigned int sdmmc1_dat2_pu4_pins[] = {
914 TEGRA_PIN_SDMMC1_DAT2_PU4,
915};
916
917static const unsigned int sdmmc1_dat3_pu5_pins[] = {
918 TEGRA_PIN_SDMMC1_DAT3_PU5,
919};
920
921static const unsigned int ufs0_ref_clk_pv0_pins[] = {
922 TEGRA_PIN_UFS0_REF_CLK_PV0,
923};
924
925static const unsigned int ufs0_rst_n_pv1_pins[] = {
926 TEGRA_PIN_UFS0_RST_N_PV1,
927};
928
929static const unsigned int pex_l0_clkreq_n_pw0_pins[] = {
930 TEGRA_PIN_PEX_L0_CLKREQ_N_PW0,
931};
932
933static const unsigned int pex_l0_rst_n_pw1_pins[] = {
934 TEGRA_PIN_PEX_L0_RST_N_PW1,
935};
936
937static const unsigned int pex_l1_clkreq_n_pw2_pins[] = {
938 TEGRA_PIN_PEX_L1_CLKREQ_N_PW2,
939};
940
941static const unsigned int pex_l1_rst_n_pw3_pins[] = {
942 TEGRA_PIN_PEX_L1_RST_N_PW3,
943};
944
945static const unsigned int pex_l2_clkreq_n_pw4_pins[] = {
946 TEGRA_PIN_PEX_L2_CLKREQ_N_PW4,
947};
948
949static const unsigned int pex_l2_rst_n_pw5_pins[] = {
950 TEGRA_PIN_PEX_L2_RST_N_PW5,
951};
952
953static const unsigned int pex_l3_clkreq_n_pw6_pins[] = {
954 TEGRA_PIN_PEX_L3_CLKREQ_N_PW6,
955};
956
957static const unsigned int pex_l3_rst_n_pw7_pins[] = {
958 TEGRA_PIN_PEX_L3_RST_N_PW7,
959};
960
961static const unsigned int pex_wake_n_px0_pins[] = {
962 TEGRA_PIN_PEX_WAKE_N_PX0,
963};
964
965static const unsigned int dp_aux_ch0_hpd_px1_pins[] = {
966 TEGRA_PIN_DP_AUX_CH0_HPD_PX1,
967};
968
969static const unsigned int bootv_ctl_n_paa0_pins[] = {
970 TEGRA_PIN_BOOTV_CTL_N_PAA0,
971};
972
973static const unsigned int soc_gpio00_paa1_pins[] = {
974 TEGRA_PIN_SOC_GPIO00_PAA1,
975};
976
977static const unsigned int vcomp_alert_paa2_pins[] = {
978 TEGRA_PIN_VCOMP_ALERT_PAA2,
979};
980
981static const unsigned int pwm1_paa3_pins[] = {
982 TEGRA_PIN_PWM1_PAA3,
983};
984
985static const unsigned int batt_oc_paa4_pins[] = {
986 TEGRA_PIN_BATT_OC_PAA4,
987};
988
989static const unsigned int soc_gpio04_paa5_pins[] = {
990 TEGRA_PIN_SOC_GPIO04_PAA5,
991};
992
993static const unsigned int soc_gpio25_paa6_pins[] = {
994 TEGRA_PIN_SOC_GPIO25_PAA6,
995};
996
997static const unsigned int soc_gpio26_paa7_pins[] = {
998 TEGRA_PIN_SOC_GPIO26_PAA7,
999};
1000
1001static const unsigned int hdmi_cec_pbb0_pins[] = {
1002 TEGRA_PIN_HDMI_CEC_PBB0,
1003};
1004
1005static const unsigned int spi2_sck_pcc0_pins[] = {
1006 TEGRA_PIN_SPI2_SCK_PCC0,
1007};
1008
1009static const unsigned int spi2_miso_pcc1_pins[] = {
1010 TEGRA_PIN_SPI2_MISO_PCC1,
1011};
1012
1013static const unsigned int spi2_mosi_pcc2_pins[] = {
1014 TEGRA_PIN_SPI2_MOSI_PCC2,
1015};
1016
1017static const unsigned int spi2_cs0_pcc3_pins[] = {
1018 TEGRA_PIN_SPI2_CS0_PCC3,
1019};
1020
1021static const unsigned int spi2_cs1_pcc4_pins[] = {
1022 TEGRA_PIN_SPI2_CS1_PCC4,
1023};
1024
1025static const unsigned int uart3_tx_pcc5_pins[] = {
1026 TEGRA_PIN_UART3_TX_PCC5,
1027};
1028
1029static const unsigned int uart3_rx_pcc6_pins[] = {
1030 TEGRA_PIN_UART3_RX_PCC6,
1031};
1032
1033static const unsigned int gen2_i2c_scl_pcc7_pins[] = {
1034 TEGRA_PIN_GEN2_I2C_SCL_PCC7,
1035};
1036
1037static const unsigned int gen2_i2c_sda_pdd0_pins[] = {
1038 TEGRA_PIN_GEN2_I2C_SDA_PDD0,
1039};
1040
1041static const unsigned int gen8_i2c_scl_pdd1_pins[] = {
1042 TEGRA_PIN_GEN8_I2C_SCL_PDD1,
1043};
1044
1045static const unsigned int gen8_i2c_sda_pdd2_pins[] = {
1046 TEGRA_PIN_GEN8_I2C_SDA_PDD2,
1047};
1048
1049static const unsigned int touch_clk_pdd3_pins[] = {
1050 TEGRA_PIN_TOUCH_CLK_PDD3,
1051};
1052
1053static const unsigned int dmic1_clk_pdd4_pins[] = {
1054 TEGRA_PIN_DMIC1_CLK_PDD4,
1055};
1056
1057static const unsigned int dmic1_dat_pdd5_pins[] = {
1058 TEGRA_PIN_DMIC1_DAT_PDD5,
1059};
1060
1061static const unsigned int soc_gpio19_pdd6_pins[] = {
1062 TEGRA_PIN_SOC_GPIO19_PDD6,
1063};
1064
1065static const unsigned int pwm2_pdd7_pins[] = {
1066 TEGRA_PIN_PWM2_PDD7,
1067};
1068
1069static const unsigned int pwm3_pee0_pins[] = {
1070 TEGRA_PIN_PWM3_PEE0,
1071};
1072
1073static const unsigned int pwm7_pee1_pins[] = {
1074 TEGRA_PIN_PWM7_PEE1,
1075};
1076
1077static const unsigned int soc_gpio49_pee2_pins[] = {
1078 TEGRA_PIN_SOC_GPIO49_PEE2,
1079};
1080
1081static const unsigned int soc_gpio82_pee3_pins[] = {
1082 TEGRA_PIN_SOC_GPIO82_PEE3,
1083};
1084
1085static const unsigned int soc_gpio50_pee4_pins[] = {
1086 TEGRA_PIN_SOC_GPIO50_PEE4,
1087};
1088
1089static const unsigned int soc_gpio83_pee5_pins[] = {
1090 TEGRA_PIN_SOC_GPIO83_PEE5,
1091};
1092
1093static const unsigned int soc_gpio69_pff0_pins[] = {
1094 TEGRA_PIN_SOC_GPIO69_PFF0,
1095};
1096
1097static const unsigned int soc_gpio70_pff1_pins[] = {
1098 TEGRA_PIN_SOC_GPIO70_PFF1,
1099};
1100
1101static const unsigned int soc_gpio71_pff2_pins[] = {
1102 TEGRA_PIN_SOC_GPIO71_PFF2,
1103};
1104
1105static const unsigned int soc_gpio72_pff3_pins[] = {
1106 TEGRA_PIN_SOC_GPIO72_PFF3,
1107};
1108
1109static const unsigned int soc_gpio73_pff4_pins[] = {
1110 TEGRA_PIN_SOC_GPIO73_PFF4,
1111};
1112
1113static const unsigned int soc_gpio74_pff5_pins[] = {
1114 TEGRA_PIN_SOC_GPIO74_PFF5,
1115};
1116
1117static const unsigned int soc_gpio80_pff6_pins[] = {
1118 TEGRA_PIN_SOC_GPIO80_PFF6,
1119};
1120
1121static const unsigned int soc_gpio76_pff7_pins[] = {
1122 TEGRA_PIN_SOC_GPIO76_PFF7,
1123};
1124
1125static const unsigned int soc_gpio77_pgg0_pins[] = {
1126 TEGRA_PIN_SOC_GPIO77_PGG0,
1127};
1128
1129static const unsigned int soc_gpio84_pgg1_pins[] = {
1130 TEGRA_PIN_SOC_GPIO84_PGG1,
1131};
1132
1133static const unsigned int uart2_tx_pgg2_pins[] = {
1134 TEGRA_PIN_UART2_TX_PGG2,
1135};
1136
1137static const unsigned int uart2_rx_pgg3_pins[] = {
1138 TEGRA_PIN_UART2_RX_PGG3,
1139};
1140
1141static const unsigned int uart2_rts_pgg4_pins[] = {
1142 TEGRA_PIN_UART2_RTS_PGG4,
1143};
1144
1145static const unsigned int uart2_cts_pgg5_pins[] = {
1146 TEGRA_PIN_UART2_CTS_PGG5,
1147};
1148
1149static const unsigned int soc_gpio85_pgg6_pins[] = {
1150 TEGRA_PIN_SOC_GPIO85_PGG6,
1151};
1152
1153static const unsigned int uart5_tx_pgg7_pins[] = {
1154 TEGRA_PIN_UART5_TX_PGG7,
1155};
1156
1157static const unsigned int uart5_rx_phh0_pins[] = {
1158 TEGRA_PIN_UART5_RX_PHH0,
1159};
1160
1161static const unsigned int uart5_rts_phh1_pins[] = {
1162 TEGRA_PIN_UART5_RTS_PHH1,
1163};
1164
1165static const unsigned int uart5_cts_phh2_pins[] = {
1166 TEGRA_PIN_UART5_CTS_PHH2,
1167};
1168
1169static const unsigned int soc_gpio86_phh3_pins[] = {
1170 TEGRA_PIN_SOC_GPIO86_PHH3,
1171};
1172
1173static const unsigned int sdmmc1_comp_pins[] = {
1174 TEGRA_PIN_SDMMC1_COMP,
1175};
1176
1177/* Define unique ID for each function */
1178enum tegra_mux_dt {
1179 TEGRA_MUX_DCA_VSYNC,
1180 TEGRA_MUX_DCA_HSYNC,
1181 TEGRA_MUX_DISPLAYA,
1182 TEGRA_MUX_RSVD0,
1183 TEGRA_MUX_I2C7_CLK,
1184 TEGRA_MUX_I2C7_DAT,
1185 TEGRA_MUX_I2C4_DAT,
1186 TEGRA_MUX_I2C4_CLK,
1187 TEGRA_MUX_I2C9_DAT,
1188 TEGRA_MUX_I2C9_CLK,
1189 TEGRA_MUX_USB_VBUS_EN0,
1190 TEGRA_MUX_USB_VBUS_EN1,
1191 TEGRA_MUX_SPI3_DIN,
1192 TEGRA_MUX_SPI1_CS0,
1193 TEGRA_MUX_SPI3_CS0,
1194 TEGRA_MUX_SPI1_DIN,
1195 TEGRA_MUX_SPI3_CS1,
1196 TEGRA_MUX_SPI1_SCK,
1197 TEGRA_MUX_SPI3_SCK,
1198 TEGRA_MUX_SPI1_CS1,
1199 TEGRA_MUX_SPI1_DOUT,
1200 TEGRA_MUX_SPI3_DOUT,
1201 TEGRA_MUX_GP_PWM5,
1202 TEGRA_MUX_GP_PWM6,
1203 TEGRA_MUX_EXTPERIPH2_CLK,
1204 TEGRA_MUX_EXTPERIPH1_CLK,
1205 TEGRA_MUX_I2C3_DAT,
1206 TEGRA_MUX_I2C3_CLK,
1207 TEGRA_MUX_EXTPERIPH4_CLK,
1208 TEGRA_MUX_EXTPERIPH3_CLK,
1209 TEGRA_MUX_DMIC2_DAT,
1210 TEGRA_MUX_DMIC2_CLK,
1211 TEGRA_MUX_UARTA_CTS,
1212 TEGRA_MUX_UARTA_RTS,
1213 TEGRA_MUX_UARTA_RXD,
1214 TEGRA_MUX_UARTA_TXD,
1215 TEGRA_MUX_I2C5_CLK,
1216 TEGRA_MUX_I2C5_DAT,
1217 TEGRA_MUX_UARTD_CTS,
1218 TEGRA_MUX_UARTD_RTS,
1219 TEGRA_MUX_UARTD_RXD,
1220 TEGRA_MUX_UARTD_TXD,
1221 TEGRA_MUX_I2C1_CLK,
1222 TEGRA_MUX_I2C1_DAT,
1223 TEGRA_MUX_SDMMC1_CD,
1224 TEGRA_MUX_I2S2_SCLK,
1225 TEGRA_MUX_I2S2_SDATA_OUT,
1226 TEGRA_MUX_I2S2_SDATA_IN,
1227 TEGRA_MUX_I2S2_LRCK,
1228 TEGRA_MUX_I2S4_SCLK,
1229 TEGRA_MUX_I2S4_SDATA_OUT,
1230 TEGRA_MUX_I2S4_SDATA_IN,
1231 TEGRA_MUX_I2S4_LRCK,
1232 TEGRA_MUX_I2S1_SCLK,
1233 TEGRA_MUX_I2S1_SDATA_OUT,
1234 TEGRA_MUX_I2S1_SDATA_IN,
1235 TEGRA_MUX_I2S1_LRCK,
1236 TEGRA_MUX_AUD_MCLK,
1237 TEGRA_MUX_I2S3_LRCK,
1238 TEGRA_MUX_I2S3_SCLK,
1239 TEGRA_MUX_I2S3_SDATA_IN,
1240 TEGRA_MUX_I2S3_SDATA_OUT,
1241 TEGRA_MUX_PE2_CLKREQ_L,
1242 TEGRA_MUX_PE1_CLKREQ_L,
1243 TEGRA_MUX_PE1_RST_L,
1244 TEGRA_MUX_PE0_CLKREQ_L,
1245 TEGRA_MUX_PE0_RST_L,
1246 TEGRA_MUX_PE2_RST_L,
1247 TEGRA_MUX_PE3_CLKREQ_L,
1248 TEGRA_MUX_PE3_RST_L,
1249 TEGRA_MUX_DP_AUX_CH0_HPD,
1250 TEGRA_MUX_QSPI0_IO0,
1251 TEGRA_MUX_QSPI0_IO1,
1252 TEGRA_MUX_QSPI0_SCK,
1253 TEGRA_MUX_QSPI0_CS_N,
1254 TEGRA_MUX_UARTG_CTS,
1255 TEGRA_MUX_UARTG_RTS,
1256 TEGRA_MUX_UARTG_TXD,
1257 TEGRA_MUX_UARTG_RXD,
1258 TEGRA_MUX_SDMMC1_CLK,
1259 TEGRA_MUX_SDMMC1_CMD,
1260 TEGRA_MUX_SDMMC1_COMP,
1261 TEGRA_MUX_SDMMC1_DAT3,
1262 TEGRA_MUX_SDMMC1_DAT2,
1263 TEGRA_MUX_SDMMC1_DAT1,
1264 TEGRA_MUX_SDMMC1_DAT0,
1265 TEGRA_MUX_UFS0,
1266 TEGRA_MUX_SOC_THERM_OC1,
1267 TEGRA_MUX_HDMI_CEC,
1268 TEGRA_MUX_GP_PWM4,
1269 TEGRA_MUX_UARTC_RXD,
1270 TEGRA_MUX_UARTC_TXD,
1271 TEGRA_MUX_I2C8_DAT,
1272 TEGRA_MUX_I2C8_CLK,
1273 TEGRA_MUX_SPI2_DOUT,
1274 TEGRA_MUX_I2C2_CLK,
1275 TEGRA_MUX_SPI2_CS0,
1276 TEGRA_MUX_I2C2_DAT,
1277 TEGRA_MUX_SPI2_SCK,
1278 TEGRA_MUX_SPI2_DIN,
1279 TEGRA_MUX_PPC_MODE_1,
1280 TEGRA_MUX_PPC_READY,
1281 TEGRA_MUX_PPC_MODE_2,
1282 TEGRA_MUX_PPC_CC,
1283 TEGRA_MUX_PPC_MODE_0,
1284 TEGRA_MUX_PPC_INT_N,
1285 TEGRA_MUX_UARTE_TXD,
1286 TEGRA_MUX_UARTE_RXD,
1287 TEGRA_MUX_UARTB_TXD,
1288 TEGRA_MUX_UARTB_RXD,
1289 TEGRA_MUX_UARTB_CTS,
1290 TEGRA_MUX_UARTB_RTS,
1291 TEGRA_MUX_UARTE_CTS,
1292 TEGRA_MUX_UARTE_RTS,
1293 TEGRA_MUX_GP_PWM7,
1294 TEGRA_MUX_GP_PWM2,
1295 TEGRA_MUX_GP_PWM3,
1296 TEGRA_MUX_GP_PWM1,
1297 TEGRA_MUX_SPI2_CS1,
1298 TEGRA_MUX_DMIC1_CLK,
1299 TEGRA_MUX_DMIC1_DAT,
1300 TEGRA_MUX_RSVD1,
1301 TEGRA_MUX_DCB_HSYNC,
1302 TEGRA_MUX_DCB_VSYNC,
1303 TEGRA_MUX_SOC_THERM_OC4,
1304 TEGRA_MUX_GP_PWM8,
1305 TEGRA_MUX_NV_THERM_FAN_TACH0,
1306 TEGRA_MUX_WDT_RESET_OUTA,
1307 TEGRA_MUX_CCLA_LA_TRIGGER_MUX,
1308 TEGRA_MUX_DSPK1_DAT,
1309 TEGRA_MUX_DSPK1_CLK,
1310 TEGRA_MUX_NV_THERM_FAN_TACH1,
1311 TEGRA_MUX_DSPK0_DAT,
1312 TEGRA_MUX_DSPK0_CLK,
1313 TEGRA_MUX_I2S5_SCLK,
1314 TEGRA_MUX_I2S6_LRCK,
1315 TEGRA_MUX_I2S6_SDATA_IN,
1316 TEGRA_MUX_I2S6_SCLK,
1317 TEGRA_MUX_I2S6_SDATA_OUT,
1318 TEGRA_MUX_I2S5_LRCK,
1319 TEGRA_MUX_I2S5_SDATA_OUT,
1320 TEGRA_MUX_I2S5_SDATA_IN,
1321 TEGRA_MUX_SDMMC1_PE3_RST_L,
1322 TEGRA_MUX_SDMMC1_PE3_CLKREQ_L,
1323 TEGRA_MUX_TOUCH_CLK,
1324 TEGRA_MUX_PPC_I2C_DAT,
1325 TEGRA_MUX_WDT_RESET_OUTB,
1326 TEGRA_MUX_SPI5_CS1,
1327 TEGRA_MUX_PPC_RST_N,
1328 TEGRA_MUX_PPC_I2C_CLK,
1329 TEGRA_MUX_SPI4_CS1,
1330 TEGRA_MUX_SOC_THERM_OC3,
1331 TEGRA_MUX_SPI5_SCK,
1332 TEGRA_MUX_SPI5_MISO,
1333 TEGRA_MUX_SPI4_SCK,
1334 TEGRA_MUX_SPI4_MISO,
1335 TEGRA_MUX_SPI4_CS0,
1336 TEGRA_MUX_SPI4_MOSI,
1337 TEGRA_MUX_SPI5_CS0,
1338 TEGRA_MUX_SPI5_MOSI,
1339 TEGRA_MUX_LED_BLINK,
1340 TEGRA_MUX_RSVD2,
1341 TEGRA_MUX_DMIC3_CLK,
1342 TEGRA_MUX_DMIC3_DAT,
1343 TEGRA_MUX_DMIC4_CLK,
1344 TEGRA_MUX_DMIC4_DAT,
1345 TEGRA_MUX_TSC_EDGE_OUT0,
1346 TEGRA_MUX_TSC_EDGE_OUT3,
1347 TEGRA_MUX_TSC_EDGE_OUT1,
1348 TEGRA_MUX_TSC_EDGE_OUT2,
1349 TEGRA_MUX_DMIC5_CLK,
1350 TEGRA_MUX_DMIC5_DAT,
1351 TEGRA_MUX_RSVD3,
1352 TEGRA_MUX_SDMMC1_WP,
1353 TEGRA_MUX_TSC_EDGE_OUT0A,
1354 TEGRA_MUX_TSC_EDGE_OUT0D,
1355 TEGRA_MUX_TSC_EDGE_OUT0B,
1356 TEGRA_MUX_TSC_EDGE_OUT0C,
1357 TEGRA_MUX_SOC_THERM_OC2,
1358};
1359
1360/* Make list of each function name */
1361#define TEGRA_PIN_FUNCTION(lid) #lid
1362
1363static const char * const tegra238_functions[] = {
1364 TEGRA_PIN_FUNCTION(dca_vsync),
1365 TEGRA_PIN_FUNCTION(dca_hsync),
1366 TEGRA_PIN_FUNCTION(displaya),
1367 TEGRA_PIN_FUNCTION(rsvd0),
1368 TEGRA_PIN_FUNCTION(i2c7_clk),
1369 TEGRA_PIN_FUNCTION(i2c7_dat),
1370 TEGRA_PIN_FUNCTION(i2c4_dat),
1371 TEGRA_PIN_FUNCTION(i2c4_clk),
1372 TEGRA_PIN_FUNCTION(i2c9_dat),
1373 TEGRA_PIN_FUNCTION(i2c9_clk),
1374 TEGRA_PIN_FUNCTION(usb_vbus_en0),
1375 TEGRA_PIN_FUNCTION(usb_vbus_en1),
1376 TEGRA_PIN_FUNCTION(spi3_din),
1377 TEGRA_PIN_FUNCTION(spi1_cs0),
1378 TEGRA_PIN_FUNCTION(spi3_cs0),
1379 TEGRA_PIN_FUNCTION(spi1_din),
1380 TEGRA_PIN_FUNCTION(spi3_cs1),
1381 TEGRA_PIN_FUNCTION(spi1_sck),
1382 TEGRA_PIN_FUNCTION(spi3_sck),
1383 TEGRA_PIN_FUNCTION(spi1_cs1),
1384 TEGRA_PIN_FUNCTION(spi1_dout),
1385 TEGRA_PIN_FUNCTION(spi3_dout),
1386 TEGRA_PIN_FUNCTION(gp_pwm5),
1387 TEGRA_PIN_FUNCTION(gp_pwm6),
1388 TEGRA_PIN_FUNCTION(extperiph2_clk),
1389 TEGRA_PIN_FUNCTION(extperiph1_clk),
1390 TEGRA_PIN_FUNCTION(i2c3_dat),
1391 TEGRA_PIN_FUNCTION(i2c3_clk),
1392 TEGRA_PIN_FUNCTION(extperiph4_clk),
1393 TEGRA_PIN_FUNCTION(extperiph3_clk),
1394 TEGRA_PIN_FUNCTION(dmic2_dat),
1395 TEGRA_PIN_FUNCTION(dmic2_clk),
1396 TEGRA_PIN_FUNCTION(uarta_cts),
1397 TEGRA_PIN_FUNCTION(uarta_rts),
1398 TEGRA_PIN_FUNCTION(uarta_rxd),
1399 TEGRA_PIN_FUNCTION(uarta_txd),
1400 TEGRA_PIN_FUNCTION(i2c5_clk),
1401 TEGRA_PIN_FUNCTION(i2c5_dat),
1402 TEGRA_PIN_FUNCTION(uartd_cts),
1403 TEGRA_PIN_FUNCTION(uartd_rts),
1404 TEGRA_PIN_FUNCTION(uartd_rxd),
1405 TEGRA_PIN_FUNCTION(uartd_txd),
1406 TEGRA_PIN_FUNCTION(i2c1_clk),
1407 TEGRA_PIN_FUNCTION(i2c1_dat),
1408 TEGRA_PIN_FUNCTION(sdmmc1_cd),
1409 TEGRA_PIN_FUNCTION(i2s2_sclk),
1410 TEGRA_PIN_FUNCTION(i2s2_sdata_out),
1411 TEGRA_PIN_FUNCTION(i2s2_sdata_in),
1412 TEGRA_PIN_FUNCTION(i2s2_lrck),
1413 TEGRA_PIN_FUNCTION(i2s4_sclk),
1414 TEGRA_PIN_FUNCTION(i2s4_sdata_out),
1415 TEGRA_PIN_FUNCTION(i2s4_sdata_in),
1416 TEGRA_PIN_FUNCTION(i2s4_lrck),
1417 TEGRA_PIN_FUNCTION(i2s1_sclk),
1418 TEGRA_PIN_FUNCTION(i2s1_sdata_out),
1419 TEGRA_PIN_FUNCTION(i2s1_sdata_in),
1420 TEGRA_PIN_FUNCTION(i2s1_lrck),
1421 TEGRA_PIN_FUNCTION(aud_mclk),
1422 TEGRA_PIN_FUNCTION(i2s3_lrck),
1423 TEGRA_PIN_FUNCTION(i2s3_sclk),
1424 TEGRA_PIN_FUNCTION(i2s3_sdata_in),
1425 TEGRA_PIN_FUNCTION(i2s3_sdata_out),
1426 TEGRA_PIN_FUNCTION(pe2_clkreq_l),
1427 TEGRA_PIN_FUNCTION(pe1_clkreq_l),
1428 TEGRA_PIN_FUNCTION(pe1_rst_l),
1429 TEGRA_PIN_FUNCTION(pe0_clkreq_l),
1430 TEGRA_PIN_FUNCTION(pe0_rst_l),
1431 TEGRA_PIN_FUNCTION(pe2_rst_l),
1432 TEGRA_PIN_FUNCTION(pe3_clkreq_l),
1433 TEGRA_PIN_FUNCTION(pe3_rst_l),
1434 TEGRA_PIN_FUNCTION(dp_aux_ch0_hpd),
1435 TEGRA_PIN_FUNCTION(qspi0_io0),
1436 TEGRA_PIN_FUNCTION(qspi0_io1),
1437 TEGRA_PIN_FUNCTION(qspi0_sck),
1438 TEGRA_PIN_FUNCTION(qspi0_cs_n),
1439 TEGRA_PIN_FUNCTION(uartg_cts),
1440 TEGRA_PIN_FUNCTION(uartg_rts),
1441 TEGRA_PIN_FUNCTION(uartg_txd),
1442 TEGRA_PIN_FUNCTION(uartg_rxd),
1443 TEGRA_PIN_FUNCTION(sdmmc1_clk),
1444 TEGRA_PIN_FUNCTION(sdmmc1_cmd),
1445 TEGRA_PIN_FUNCTION(sdmmc1_comp),
1446 TEGRA_PIN_FUNCTION(sdmmc1_dat3),
1447 TEGRA_PIN_FUNCTION(sdmmc1_dat2),
1448 TEGRA_PIN_FUNCTION(sdmmc1_dat1),
1449 TEGRA_PIN_FUNCTION(sdmmc1_dat0),
1450 TEGRA_PIN_FUNCTION(ufs0),
1451 TEGRA_PIN_FUNCTION(soc_therm_oc1),
1452 TEGRA_PIN_FUNCTION(hdmi_cec),
1453 TEGRA_PIN_FUNCTION(gp_pwm4),
1454 TEGRA_PIN_FUNCTION(uartc_rxd),
1455 TEGRA_PIN_FUNCTION(uartc_txd),
1456 TEGRA_PIN_FUNCTION(i2c8_dat),
1457 TEGRA_PIN_FUNCTION(i2c8_clk),
1458 TEGRA_PIN_FUNCTION(spi2_dout),
1459 TEGRA_PIN_FUNCTION(i2c2_clk),
1460 TEGRA_PIN_FUNCTION(spi2_cs0),
1461 TEGRA_PIN_FUNCTION(i2c2_dat),
1462 TEGRA_PIN_FUNCTION(spi2_sck),
1463 TEGRA_PIN_FUNCTION(spi2_din),
1464 TEGRA_PIN_FUNCTION(ppc_mode_1),
1465 TEGRA_PIN_FUNCTION(ppc_ready),
1466 TEGRA_PIN_FUNCTION(ppc_mode_2),
1467 TEGRA_PIN_FUNCTION(ppc_cc),
1468 TEGRA_PIN_FUNCTION(ppc_mode_0),
1469 TEGRA_PIN_FUNCTION(ppc_int_n),
1470 TEGRA_PIN_FUNCTION(uarte_txd),
1471 TEGRA_PIN_FUNCTION(uarte_rxd),
1472 TEGRA_PIN_FUNCTION(uartb_txd),
1473 TEGRA_PIN_FUNCTION(uartb_rxd),
1474 TEGRA_PIN_FUNCTION(uartb_cts),
1475 TEGRA_PIN_FUNCTION(uartb_rts),
1476 TEGRA_PIN_FUNCTION(uarte_cts),
1477 TEGRA_PIN_FUNCTION(uarte_rts),
1478 TEGRA_PIN_FUNCTION(gp_pwm7),
1479 TEGRA_PIN_FUNCTION(gp_pwm2),
1480 TEGRA_PIN_FUNCTION(gp_pwm3),
1481 TEGRA_PIN_FUNCTION(gp_pwm1),
1482 TEGRA_PIN_FUNCTION(spi2_cs1),
1483 TEGRA_PIN_FUNCTION(dmic1_clk),
1484 TEGRA_PIN_FUNCTION(dmic1_dat),
1485 TEGRA_PIN_FUNCTION(rsvd1),
1486 TEGRA_PIN_FUNCTION(dcb_hsync),
1487 TEGRA_PIN_FUNCTION(dcb_vsync),
1488 TEGRA_PIN_FUNCTION(soc_therm_oc4),
1489 TEGRA_PIN_FUNCTION(gp_pwm8),
1490 TEGRA_PIN_FUNCTION(nv_therm_fan_tach0),
1491 TEGRA_PIN_FUNCTION(wdt_reset_outa),
1492 TEGRA_PIN_FUNCTION(ccla_la_trigger_mux),
1493 TEGRA_PIN_FUNCTION(dspk1_dat),
1494 TEGRA_PIN_FUNCTION(dspk1_clk),
1495 TEGRA_PIN_FUNCTION(nv_therm_fan_tach1),
1496 TEGRA_PIN_FUNCTION(dspk0_dat),
1497 TEGRA_PIN_FUNCTION(dspk0_clk),
1498 TEGRA_PIN_FUNCTION(i2s5_sclk),
1499 TEGRA_PIN_FUNCTION(i2s6_lrck),
1500 TEGRA_PIN_FUNCTION(i2s6_sdata_in),
1501 TEGRA_PIN_FUNCTION(i2s6_sclk),
1502 TEGRA_PIN_FUNCTION(i2s6_sdata_out),
1503 TEGRA_PIN_FUNCTION(i2s5_lrck),
1504 TEGRA_PIN_FUNCTION(i2s5_sdata_out),
1505 TEGRA_PIN_FUNCTION(i2s5_sdata_in),
1506 TEGRA_PIN_FUNCTION(sdmmc1_pe3_rst_l),
1507 TEGRA_PIN_FUNCTION(sdmmc1_pe3_clkreq_l),
1508 TEGRA_PIN_FUNCTION(touch_clk),
1509 TEGRA_PIN_FUNCTION(ppc_i2c_dat),
1510 TEGRA_PIN_FUNCTION(wdt_reset_outb),
1511 TEGRA_PIN_FUNCTION(spi5_cs1),
1512 TEGRA_PIN_FUNCTION(ppc_rst_n),
1513 TEGRA_PIN_FUNCTION(ppc_i2c_clk),
1514 TEGRA_PIN_FUNCTION(spi4_cs1),
1515 TEGRA_PIN_FUNCTION(soc_therm_oc3),
1516 TEGRA_PIN_FUNCTION(spi5_sck),
1517 TEGRA_PIN_FUNCTION(spi5_miso),
1518 TEGRA_PIN_FUNCTION(spi4_sck),
1519 TEGRA_PIN_FUNCTION(spi4_miso),
1520 TEGRA_PIN_FUNCTION(spi4_cs0),
1521 TEGRA_PIN_FUNCTION(spi4_mosi),
1522 TEGRA_PIN_FUNCTION(spi5_cs0),
1523 TEGRA_PIN_FUNCTION(spi5_mosi),
1524 TEGRA_PIN_FUNCTION(led_blink),
1525 TEGRA_PIN_FUNCTION(rsvd2),
1526 TEGRA_PIN_FUNCTION(dmic3_clk),
1527 TEGRA_PIN_FUNCTION(dmic3_dat),
1528 TEGRA_PIN_FUNCTION(dmic4_clk),
1529 TEGRA_PIN_FUNCTION(dmic4_dat),
1530 TEGRA_PIN_FUNCTION(tsc_edge_out0),
1531 TEGRA_PIN_FUNCTION(tsc_edge_out3),
1532 TEGRA_PIN_FUNCTION(tsc_edge_out1),
1533 TEGRA_PIN_FUNCTION(tsc_edge_out2),
1534 TEGRA_PIN_FUNCTION(dmic5_clk),
1535 TEGRA_PIN_FUNCTION(dmic5_dat),
1536 TEGRA_PIN_FUNCTION(rsvd3),
1537 TEGRA_PIN_FUNCTION(sdmmc1_wp),
1538 TEGRA_PIN_FUNCTION(tsc_edge_out0a),
1539 TEGRA_PIN_FUNCTION(tsc_edge_out0d),
1540 TEGRA_PIN_FUNCTION(tsc_edge_out0b),
1541 TEGRA_PIN_FUNCTION(tsc_edge_out0c),
1542 TEGRA_PIN_FUNCTION(soc_therm_oc2),
1543};
1544
1545#define PINGROUP_REG_Y(r) ((r))
1546#define PINGROUP_REG_N(r) -1
1547
1548#define DRV_PINGROUP_Y(r) ((r))
1549
1550#define DRV_PINGROUP_ENTRY_N \
1551 .drv_reg = -1, \
1552 .drv_bank = -1, \
1553 .drvdn_bit = -1, \
1554 .drvup_bit = -1, \
1555 .slwr_bit = -1, \
1556 .slwf_bit = -1
1557
1558#define DRV_PINGROUP_ENTRY_Y(r, drvdn_b, drvdn_w, drvup_b, \
1559 drvup_w, slwr_b, slwr_w, slwf_b, \
1560 slwf_w, bank) \
1561 .drv_reg = DRV_PINGROUP_Y(r), \
1562 .drv_bank = bank, \
1563 .drvdn_bit = drvdn_b, \
1564 .drvdn_width = drvdn_w, \
1565 .drvup_bit = drvup_b, \
1566 .drvup_width = drvup_w, \
1567 .slwr_bit = slwr_b, \
1568 .slwr_width = slwr_w, \
1569 .slwf_bit = slwf_b, \
1570 .slwf_width = slwf_w
1571
1572#define PIN_PINGROUP_ENTRY_N \
1573 .mux_reg = -1, \
1574 .pupd_reg = -1, \
1575 .tri_reg = -1, \
1576 .einput_bit = -1, \
1577 .e_io_hv_bit = -1, \
1578 .odrain_bit = -1, \
1579 .lock_bit = -1, \
1580 .parked_bit = -1, \
1581 .lpmd_bit = -1, \
1582 .drvtype_bit = -1, \
1583 .lpdr_bit = -1, \
1584 .pbias_buf_bit = -1, \
1585 .preemp_bit = -1, \
1586 .rfu_in_bit = -1
1587
1588#define PIN_PINGROUP_ENTRY_Y(r, bank, pupd, e_io_hv, e_lpbk, e_input, \
1589 e_lpdr, e_pbias_buf, gpio_sfio_sel, \
1590 schmitt_b) \
1591 .mux_reg = PINGROUP_REG_Y(r), \
1592 .lpmd_bit = -1, \
1593 .lock_bit = -1, \
1594 .hsm_bit = -1, \
1595 .mux_bank = bank, \
1596 .mux_bit = 0, \
1597 .pupd_reg = PINGROUP_REG_##pupd(r), \
1598 .pupd_bank = bank, \
1599 .pupd_bit = 2, \
1600 .tri_reg = PINGROUP_REG_Y(r), \
1601 .tri_bank = bank, \
1602 .tri_bit = 4, \
1603 .einput_bit = e_input, \
1604 .sfsel_bit = gpio_sfio_sel, \
1605 .schmitt_bit = schmitt_b, \
1606 .drvtype_bit = 13, \
1607 .lpdr_bit = e_lpdr,
1608
1609#define drive_soc_gpio36_pt1 DRV_PINGROUP_ENTRY_Y(0x10004, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1610#define drive_soc_gpio53_pt2 DRV_PINGROUP_ENTRY_Y(0x1000c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1611#define drive_soc_gpio38_pt3 DRV_PINGROUP_ENTRY_Y(0x1001c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1612#define drive_soc_gpio40_pt4 DRV_PINGROUP_ENTRY_Y(0x1002c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1613#define drive_soc_gpio75_ps2 DRV_PINGROUP_ENTRY_Y(0x10034, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1614#define drive_soc_gpio81_pt0 DRV_PINGROUP_ENTRY_Y(0x1003c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1615#define drive_soc_gpio78_ps5 DRV_PINGROUP_ENTRY_Y(0x10044, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1616#define drive_soc_gpio34_pt5 DRV_PINGROUP_ENTRY_Y(0x1004c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1617#define drive_gen7_i2c_scl_ps3 DRV_PINGROUP_ENTRY_Y(0x100a4, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1618#define drive_gen7_i2c_sda_ps4 DRV_PINGROUP_ENTRY_Y(0x100ac, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1619#define drive_gen4_i2c_sda_ps1 DRV_PINGROUP_ENTRY_Y(0x100b4, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1620#define drive_gen4_i2c_scl_ps0 DRV_PINGROUP_ENTRY_Y(0x100bc, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1621#define drive_gen9_i2c_sda_ps7 DRV_PINGROUP_ENTRY_Y(0x100c4, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1622#define drive_gen9_i2c_scl_ps6 DRV_PINGROUP_ENTRY_Y(0x100cc, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1623#define drive_usb_vbus_en0_pt6 DRV_PINGROUP_ENTRY_Y(0x100d4, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1624#define drive_usb_vbus_en1_pt7 DRV_PINGROUP_ENTRY_Y(0x100dc, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1625#define drive_soc_gpio61_pr0 DRV_PINGROUP_ENTRY_Y(0x1f004, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1626#define drive_soc_gpio62_pr1 DRV_PINGROUP_ENTRY_Y(0x1f00c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1627#define drive_soc_gpio63_pr2 DRV_PINGROUP_ENTRY_Y(0x1f014, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1628#define drive_soc_gpio64_pr3 DRV_PINGROUP_ENTRY_Y(0x1f01c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1629#define drive_soc_gpio65_pr4 DRV_PINGROUP_ENTRY_Y(0x1f024, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1630#define drive_soc_gpio66_pr5 DRV_PINGROUP_ENTRY_Y(0x1f02c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1631#define drive_soc_gpio67_pr6 DRV_PINGROUP_ENTRY_Y(0x1f034, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1632#define drive_soc_gpio68_pr7 DRV_PINGROUP_ENTRY_Y(0x1f03c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1633#define drive_spi3_miso_pa4 DRV_PINGROUP_ENTRY_Y(0xd004, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1634#define drive_spi1_cs0_pb3 DRV_PINGROUP_ENTRY_Y(0xd00c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1635#define drive_spi3_cs0_pa6 DRV_PINGROUP_ENTRY_Y(0xd014, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1636#define drive_spi1_miso_pb1 DRV_PINGROUP_ENTRY_Y(0xd01c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1637#define drive_spi3_cs1_pa7 DRV_PINGROUP_ENTRY_Y(0xd024, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1638#define drive_spi1_sck_pb0 DRV_PINGROUP_ENTRY_Y(0xd02c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1639#define drive_spi3_sck_pa3 DRV_PINGROUP_ENTRY_Y(0xd034, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1640#define drive_spi1_cs1_pb4 DRV_PINGROUP_ENTRY_Y(0xd03c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1641#define drive_spi1_mosi_pb2 DRV_PINGROUP_ENTRY_Y(0xd044, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1642#define drive_spi3_mosi_pa5 DRV_PINGROUP_ENTRY_Y(0xd04c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1643#define drive_gpu_pwr_req_pa0 DRV_PINGROUP_ENTRY_Y(0xd054, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1644#define drive_gp_pwm5_pa1 DRV_PINGROUP_ENTRY_Y(0xd05c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1645#define drive_gp_pwm6_pa2 DRV_PINGROUP_ENTRY_Y(0xd064, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1646#define drive_extperiph2_clk_pc3 DRV_PINGROUP_ENTRY_Y(0x4, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1647#define drive_extperiph1_clk_pc2 DRV_PINGROUP_ENTRY_Y(0xc, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1648#define drive_cam_i2c_sda_pc5 DRV_PINGROUP_ENTRY_Y(0x14, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1649#define drive_cam_i2c_scl_pc4 DRV_PINGROUP_ENTRY_Y(0x1c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1650#define drive_soc_gpio23_pc6 DRV_PINGROUP_ENTRY_Y(0x24, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1651#define drive_soc_gpio24_pc7 DRV_PINGROUP_ENTRY_Y(0x2c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1652#define drive_soc_gpio27_pd0 DRV_PINGROUP_ENTRY_Y(0x44, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1653#define drive_soc_gpio29_pd2 DRV_PINGROUP_ENTRY_Y(0x54, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1654#define drive_soc_gpio32_pd4 DRV_PINGROUP_ENTRY_Y(0x6c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1655#define drive_soc_gpio33_pd3 DRV_PINGROUP_ENTRY_Y(0x74, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1656#define drive_soc_gpio35_pd5 DRV_PINGROUP_ENTRY_Y(0x7c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1657#define drive_soc_gpio37_pd6 DRV_PINGROUP_ENTRY_Y(0x84, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1658#define drive_soc_gpio56_pd7 DRV_PINGROUP_ENTRY_Y(0x8c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1659#define drive_soc_gpio55_pd1 DRV_PINGROUP_ENTRY_Y(0x94, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1660#define drive_uart1_cts_pe3 DRV_PINGROUP_ENTRY_Y(0x9c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1661#define drive_uart1_rts_pe2 DRV_PINGROUP_ENTRY_Y(0xa4, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1662#define drive_uart1_rx_pe1 DRV_PINGROUP_ENTRY_Y(0xac, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1663#define drive_uart1_tx_pe0 DRV_PINGROUP_ENTRY_Y(0xb4, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1664#define drive_pwr_i2c_scl_pc0 DRV_PINGROUP_ENTRY_Y(0xbc, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1665#define drive_pwr_i2c_sda_pc1 DRV_PINGROUP_ENTRY_Y(0xc4, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1666#define drive_cpu_pwr_req_ph4 DRV_PINGROUP_ENTRY_Y(0x4004, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1667#define drive_uart4_cts_pg5 DRV_PINGROUP_ENTRY_Y(0x400c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1668#define drive_uart4_rts_pg4 DRV_PINGROUP_ENTRY_Y(0x4014, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1669#define drive_uart4_rx_pg3 DRV_PINGROUP_ENTRY_Y(0x401c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1670#define drive_uart4_tx_pg2 DRV_PINGROUP_ENTRY_Y(0x4024, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1671#define drive_gen1_i2c_scl_ph2 DRV_PINGROUP_ENTRY_Y(0x402c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1672#define drive_gen1_i2c_sda_ph3 DRV_PINGROUP_ENTRY_Y(0x4034, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1673#define drive_soc_gpio20_pf6 DRV_PINGROUP_ENTRY_Y(0x403c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1674#define drive_soc_gpio21_pf7 DRV_PINGROUP_ENTRY_Y(0x4044, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1675#define drive_soc_gpio22_pg0 DRV_PINGROUP_ENTRY_Y(0x404c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1676#define drive_soc_gpio13_pf0 DRV_PINGROUP_ENTRY_Y(0x4054, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1677#define drive_soc_gpio14_pf1 DRV_PINGROUP_ENTRY_Y(0x405c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1678#define drive_soc_gpio15_pf2 DRV_PINGROUP_ENTRY_Y(0x4064, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1679#define drive_soc_gpio16_pf3 DRV_PINGROUP_ENTRY_Y(0x406c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1680#define drive_soc_gpio17_pf4 DRV_PINGROUP_ENTRY_Y(0x4074, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1681#define drive_soc_gpio18_pf5 DRV_PINGROUP_ENTRY_Y(0x407c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1682#define drive_soc_gpio41_pg6 DRV_PINGROUP_ENTRY_Y(0x408c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1683#define drive_soc_gpio42_pg7 DRV_PINGROUP_ENTRY_Y(0x4094, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1684#define drive_soc_gpio43_ph0 DRV_PINGROUP_ENTRY_Y(0x409c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1685#define drive_soc_gpio44_ph1 DRV_PINGROUP_ENTRY_Y(0x40a4, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1686#define drive_soc_gpio06_pg1 DRV_PINGROUP_ENTRY_Y(0x40ac, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1687#define drive_soc_gpio07_ph5 DRV_PINGROUP_ENTRY_Y(0x40b4, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1688#define drive_dap4_sclk_pp4 DRV_PINGROUP_ENTRY_Y(0x2004, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1689#define drive_dap4_dout_pp5 DRV_PINGROUP_ENTRY_Y(0x200c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1690#define drive_dap4_din_pp6 DRV_PINGROUP_ENTRY_Y(0x2014, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1691#define drive_dap4_fs_pp7 DRV_PINGROUP_ENTRY_Y(0x201c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1692#define drive_soc_gpio167_pp0 DRV_PINGROUP_ENTRY_Y(0x2044, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1693#define drive_soc_gpio168_pp1 DRV_PINGROUP_ENTRY_Y(0x204c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1694#define drive_soc_gpio169_pp2 DRV_PINGROUP_ENTRY_Y(0x2054, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1695#define drive_soc_gpio170_pp3 DRV_PINGROUP_ENTRY_Y(0x205c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1696#define drive_soc_gpio171_pq0 DRV_PINGROUP_ENTRY_Y(0x2064, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1697#define drive_soc_gpio172_pq1 DRV_PINGROUP_ENTRY_Y(0x206c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1698#define drive_soc_gpio173_pq2 DRV_PINGROUP_ENTRY_Y(0x2074, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1699#define drive_soc_gpio45_pk0 DRV_PINGROUP_ENTRY_Y(0x18004, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1700#define drive_soc_gpio46_pk1 DRV_PINGROUP_ENTRY_Y(0x1800c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1701#define drive_soc_gpio47_pk2 DRV_PINGROUP_ENTRY_Y(0x18014, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1702#define drive_soc_gpio48_pk3 DRV_PINGROUP_ENTRY_Y(0x1801c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1703#define drive_soc_gpio57_pj4 DRV_PINGROUP_ENTRY_Y(0x18024, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1704#define drive_soc_gpio58_pj5 DRV_PINGROUP_ENTRY_Y(0x1802c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1705#define drive_soc_gpio59_pj6 DRV_PINGROUP_ENTRY_Y(0x18034, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1706#define drive_soc_gpio60_pj7 DRV_PINGROUP_ENTRY_Y(0x1803c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1707#define drive_dap3_fs_pj3 DRV_PINGROUP_ENTRY_Y(0x18064, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1708#define drive_dap3_clk_pj0 DRV_PINGROUP_ENTRY_Y(0x1806c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1709#define drive_dap3_din_pj2 DRV_PINGROUP_ENTRY_Y(0x18074, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1710#define drive_dap3_dout_pj1 DRV_PINGROUP_ENTRY_Y(0x1807c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1711#define drive_pex_l2_clkreq_n_pw4 DRV_PINGROUP_ENTRY_Y(0x7004, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1712#define drive_pex_wake_n_px0 DRV_PINGROUP_ENTRY_Y(0x700c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1713#define drive_pex_l1_clkreq_n_pw2 DRV_PINGROUP_ENTRY_Y(0x7014, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1714#define drive_pex_l1_rst_n_pw3 DRV_PINGROUP_ENTRY_Y(0x701c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1715#define drive_pex_l0_clkreq_n_pw0 DRV_PINGROUP_ENTRY_Y(0x7024, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1716#define drive_pex_l0_rst_n_pw1 DRV_PINGROUP_ENTRY_Y(0x702c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1717#define drive_pex_l2_rst_n_pw5 DRV_PINGROUP_ENTRY_Y(0x7034, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1718#define drive_pex_l3_clkreq_n_pw6 DRV_PINGROUP_ENTRY_Y(0x703c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1719#define drive_pex_l3_rst_n_pw7 DRV_PINGROUP_ENTRY_Y(0x7044, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1720#define drive_dp_aux_ch0_hpd_px1 DRV_PINGROUP_ENTRY_Y(0x704c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1721#define drive_qspi0_io0_pl1 DRV_PINGROUP_ENTRY_Y(0xb004, 12, 5, 24, 5, -1, -1, -1, -1, 0)
1722#define drive_qspi0_io1_pl2 DRV_PINGROUP_ENTRY_Y(0xb00c, 12, 5, 24, 5, -1, -1, -1, -1, 0)
1723#define drive_qspi0_sck_pl0 DRV_PINGROUP_ENTRY_Y(0xb014, 12, 5, 24, 5, -1, -1, -1, -1, 0)
1724#define drive_qspi0_cs_n_pl3 DRV_PINGROUP_ENTRY_Y(0xb01c, 12, 5, 24, 5, -1, -1, -1, -1, 0)
1725#define drive_soc_gpio156_pm0 DRV_PINGROUP_ENTRY_Y(0xb024, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1726#define drive_soc_gpio155_pl7 DRV_PINGROUP_ENTRY_Y(0xb02c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1727#define drive_soc_gpio160_pm4 DRV_PINGROUP_ENTRY_Y(0xb034, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1728#define drive_soc_gpio154_pl6 DRV_PINGROUP_ENTRY_Y(0xb03c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1729#define drive_soc_gpio152_pl4 DRV_PINGROUP_ENTRY_Y(0xb044, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1730#define drive_soc_gpio153_pl5 DRV_PINGROUP_ENTRY_Y(0xb04c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1731#define drive_soc_gpio161_pm5 DRV_PINGROUP_ENTRY_Y(0xb054, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1732#define drive_soc_gpio162_pm6 DRV_PINGROUP_ENTRY_Y(0xb05c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1733#define drive_soc_gpio159_pm3 DRV_PINGROUP_ENTRY_Y(0xb064, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1734#define drive_soc_gpio157_pm1 DRV_PINGROUP_ENTRY_Y(0xb06c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1735#define drive_soc_gpio158_pm2 DRV_PINGROUP_ENTRY_Y(0xb074, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1736#define drive_uart7_cts_pn2 DRV_PINGROUP_ENTRY_Y(0xb07c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1737#define drive_uart7_rts_pn1 DRV_PINGROUP_ENTRY_Y(0xb084, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1738#define drive_uart7_tx_pm7 DRV_PINGROUP_ENTRY_Y(0xb08c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1739#define drive_uart7_rx_pn0 DRV_PINGROUP_ENTRY_Y(0xb094, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1740#define drive_sdmmc1_clk_pu0 DRV_PINGROUP_ENTRY_Y(0x8004, 28, 2, 30, 2, -1, -1, -1, -1, 0)
1741#define drive_sdmmc1_cmd_pu1 DRV_PINGROUP_ENTRY_Y(0x800c, 28, 2, 30, 2, -1, -1, -1, -1, 0)
1742#define drive_sdmmc1_dat3_pu5 DRV_PINGROUP_ENTRY_Y(0x801c, 28, 2, 30, 2, -1, -1, -1, -1, 0)
1743#define drive_sdmmc1_dat2_pu4 DRV_PINGROUP_ENTRY_Y(0x8024, 28, 2, 30, 2, -1, -1, -1, -1, 0)
1744#define drive_sdmmc1_dat1_pu3 DRV_PINGROUP_ENTRY_Y(0x802c, 28, 2, 30, 2, -1, -1, -1, -1, 0)
1745#define drive_sdmmc1_dat0_pu2 DRV_PINGROUP_ENTRY_Y(0x8034, 28, 2, 30, 2, -1, -1, -1, -1, 0)
1746#define drive_ufs0_rst_n_pv1 DRV_PINGROUP_ENTRY_Y(0x11004, 12, 5, 24, 5, -1, -1, -1, -1, 0)
1747#define drive_ufs0_ref_clk_pv0 DRV_PINGROUP_ENTRY_Y(0x1100c, 12, 5, 24, 5, -1, -1, -1, -1, 0)
1748#define drive_batt_oc_paa4 DRV_PINGROUP_ENTRY_Y(0x1024, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1749#define drive_bootv_ctl_n_paa0 DRV_PINGROUP_ENTRY_Y(0x102c, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1750#define drive_vcomp_alert_paa2 DRV_PINGROUP_ENTRY_Y(0x105c, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1751#define drive_hdmi_cec_pbb0 DRV_PINGROUP_ENTRY_Y(0x1064, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1752#define drive_touch_clk_pdd3 DRV_PINGROUP_ENTRY_Y(0x106c, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1753#define drive_uart3_rx_pcc6 DRV_PINGROUP_ENTRY_Y(0x1074, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1754#define drive_uart3_tx_pcc5 DRV_PINGROUP_ENTRY_Y(0x107c, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1755#define drive_gen8_i2c_sda_pdd2 DRV_PINGROUP_ENTRY_Y(0x1084, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1756#define drive_gen8_i2c_scl_pdd1 DRV_PINGROUP_ENTRY_Y(0x108c, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1757#define drive_spi2_mosi_pcc2 DRV_PINGROUP_ENTRY_Y(0x1094, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1758#define drive_gen2_i2c_scl_pcc7 DRV_PINGROUP_ENTRY_Y(0x109c, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1759#define drive_spi2_cs0_pcc3 DRV_PINGROUP_ENTRY_Y(0x10a4, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1760#define drive_gen2_i2c_sda_pdd0 DRV_PINGROUP_ENTRY_Y(0x10ac, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1761#define drive_spi2_sck_pcc0 DRV_PINGROUP_ENTRY_Y(0x10b4, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1762#define drive_spi2_miso_pcc1 DRV_PINGROUP_ENTRY_Y(0x10bc, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1763#define drive_soc_gpio49_pee2 DRV_PINGROUP_ENTRY_Y(0x10c4, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1764#define drive_soc_gpio50_pee4 DRV_PINGROUP_ENTRY_Y(0x10cc, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1765#define drive_soc_gpio82_pee3 DRV_PINGROUP_ENTRY_Y(0x10d4, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1766#define drive_soc_gpio71_pff2 DRV_PINGROUP_ENTRY_Y(0x10dc, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1767#define drive_soc_gpio76_pff7 DRV_PINGROUP_ENTRY_Y(0x10e4, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1768#define drive_soc_gpio74_pff5 DRV_PINGROUP_ENTRY_Y(0x10ec, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1769#define drive_soc_gpio00_paa1 DRV_PINGROUP_ENTRY_Y(0x10f4, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1770#define drive_soc_gpio19_pdd6 DRV_PINGROUP_ENTRY_Y(0x10fc, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1771#define drive_soc_gpio86_phh3 DRV_PINGROUP_ENTRY_Y(0x1104, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1772#define drive_soc_gpio72_pff3 DRV_PINGROUP_ENTRY_Y(0x110c, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1773#define drive_soc_gpio77_pgg0 DRV_PINGROUP_ENTRY_Y(0x1114, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1774#define drive_soc_gpio80_pff6 DRV_PINGROUP_ENTRY_Y(0x111c, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1775#define drive_soc_gpio84_pgg1 DRV_PINGROUP_ENTRY_Y(0x1124, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1776#define drive_soc_gpio83_pee5 DRV_PINGROUP_ENTRY_Y(0x112c, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1777#define drive_soc_gpio73_pff4 DRV_PINGROUP_ENTRY_Y(0x1134, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1778#define drive_soc_gpio70_pff1 DRV_PINGROUP_ENTRY_Y(0x113c, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1779#define drive_soc_gpio04_paa5 DRV_PINGROUP_ENTRY_Y(0x1144, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1780#define drive_soc_gpio85_pgg6 DRV_PINGROUP_ENTRY_Y(0x114c, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1781#define drive_soc_gpio69_pff0 DRV_PINGROUP_ENTRY_Y(0x1154, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1782#define drive_soc_gpio25_paa6 DRV_PINGROUP_ENTRY_Y(0x115c, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1783#define drive_soc_gpio26_paa7 DRV_PINGROUP_ENTRY_Y(0x1164, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1784#define drive_uart5_tx_pgg7 DRV_PINGROUP_ENTRY_Y(0x116c, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1785#define drive_uart5_rx_phh0 DRV_PINGROUP_ENTRY_Y(0x1174, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1786#define drive_uart2_tx_pgg2 DRV_PINGROUP_ENTRY_Y(0x117c, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1787#define drive_uart2_rx_pgg3 DRV_PINGROUP_ENTRY_Y(0x1184, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1788#define drive_uart2_cts_pgg5 DRV_PINGROUP_ENTRY_Y(0x118c, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1789#define drive_uart2_rts_pgg4 DRV_PINGROUP_ENTRY_Y(0x1194, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1790#define drive_uart5_cts_phh2 DRV_PINGROUP_ENTRY_Y(0x119c, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1791#define drive_uart5_rts_phh1 DRV_PINGROUP_ENTRY_Y(0x11a4, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1792#define drive_pwm7_pee1 DRV_PINGROUP_ENTRY_Y(0x11ac, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1793#define drive_pwm2_pdd7 DRV_PINGROUP_ENTRY_Y(0x11b4, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1794#define drive_pwm3_pee0 DRV_PINGROUP_ENTRY_Y(0x11bc, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1795#define drive_pwm1_paa3 DRV_PINGROUP_ENTRY_Y(0x11c4, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1796#define drive_spi2_cs1_pcc4 DRV_PINGROUP_ENTRY_Y(0x11cc, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1797#define drive_dmic1_clk_pdd4 DRV_PINGROUP_ENTRY_Y(0x11d4, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1798#define drive_dmic1_dat_pdd5 DRV_PINGROUP_ENTRY_Y(0x11dc, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1799
1800#define drive_sdmmc1_comp DRV_PINGROUP_ENTRY_N
1801
1802#define PINGROUP(pg_name, f0, f1, f2, f3, r, bank, pupd, e_io_hv, e_lpbk, e_input, e_lpdr, e_pbias_buf, \
1803 gpio_sfio_sel, schmitt_b) \
1804 { \
1805 .name = #pg_name, \
1806 .pins = pg_name##_pins, \
1807 .npins = ARRAY_SIZE(pg_name##_pins), \
1808 .funcs = { \
1809 TEGRA_MUX_##f0, \
1810 TEGRA_MUX_##f1, \
1811 TEGRA_MUX_##f2, \
1812 TEGRA_MUX_##f3, \
1813 }, \
1814 PIN_PINGROUP_ENTRY_Y(r, bank, pupd, e_io_hv, e_lpbk, \
1815 e_input, e_lpdr, e_pbias_buf, \
1816 gpio_sfio_sel, schmitt_b) \
1817 drive_##pg_name, \
1818 }
1819
1820static const struct tegra_pingroup tegra238_groups[] = {
1821 PINGROUP(soc_gpio36_pt1, DCA_VSYNC, RSVD1, RSVD2, RSVD3, 0x10000, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1822 PINGROUP(soc_gpio53_pt2, DCA_HSYNC, RSVD1, RSVD2, RSVD3, 0x10008, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1823 PINGROUP(soc_gpio38_pt3, DISPLAYA, DCB_HSYNC, RSVD2, RSVD3, 0x10018, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1824 PINGROUP(soc_gpio40_pt4, RSVD0, DCB_VSYNC, RSVD2, RSVD3, 0x10028, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1825 PINGROUP(soc_gpio75_ps2, RSVD0, RSVD1, RSVD2, RSVD3, 0x10030, 0, Y, 5, 7, 6, 8, -1, 10, 12),
1826 PINGROUP(soc_gpio81_pt0, RSVD0, RSVD1, RSVD2, RSVD3, 0x10038, 0, Y, 5, 7, 6, 8, -1, 10, 12),
1827 PINGROUP(soc_gpio78_ps5, RSVD0, RSVD1, RSVD2, RSVD3, 0x10040, 0, Y, 5, 7, 6, 8, -1, 10, 12),
1828 PINGROUP(soc_gpio34_pt5, RSVD0, RSVD1, RSVD2, RSVD3, 0x10048, 0, Y, 5, 7, 6, 8, -1, 10, 12),
1829 PINGROUP(gen7_i2c_scl_ps3, I2C7_CLK, RSVD1, RSVD2, RSVD3, 0x100a0, 0, Y, 5, 7, 6, 8, -1, 10, 12),
1830 PINGROUP(gen7_i2c_sda_ps4, I2C7_DAT, RSVD1, RSVD2, RSVD3, 0x100a8, 0, Y, 5, 7, 6, 8, -1, 10, 12),
1831 PINGROUP(gen4_i2c_sda_ps1, I2C4_DAT, RSVD1, RSVD2, RSVD3, 0x100b0, 0, Y, 5, 7, 6, 8, -1, 10, 12),
1832 PINGROUP(gen4_i2c_scl_ps0, I2C4_CLK, RSVD1, RSVD2, RSVD3, 0x100b8, 0, Y, 5, 7, 6, 8, -1, 10, 12),
1833 PINGROUP(gen9_i2c_sda_ps7, I2C9_DAT, RSVD1, RSVD2, RSVD3, 0x100c0, 0, Y, 5, 7, 6, 8, -1, 10, 12),
1834 PINGROUP(gen9_i2c_scl_ps6, I2C9_CLK, RSVD1, RSVD2, RSVD3, 0x100c8, 0, Y, 5, 7, 6, 8, -1, 10, 12),
1835 PINGROUP(usb_vbus_en0_pt6, USB_VBUS_EN0, RSVD1, RSVD2, RSVD3, 0x100d0, 0, Y, 5, 7, 6, 8, -1, 10, 12),
1836 PINGROUP(usb_vbus_en1_pt7, USB_VBUS_EN1, RSVD1, RSVD2, RSVD3, 0x100d8, 0, Y, 5, 7, 6, 8, -1, 10, 12),
1837 PINGROUP(soc_gpio61_pr0, RSVD0, SOC_THERM_OC4, RSVD2, RSVD3, 0x1f000, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1838 PINGROUP(soc_gpio62_pr1, RSVD0, RSVD1, RSVD2, RSVD3, 0x1f008, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1839 PINGROUP(soc_gpio63_pr2, RSVD0, RSVD1, RSVD2, RSVD3, 0x1f010, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1840 PINGROUP(soc_gpio64_pr3, RSVD0, RSVD1, RSVD2, RSVD3, 0x1f018, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1841 PINGROUP(soc_gpio65_pr4, RSVD0, RSVD1, RSVD2, RSVD3, 0x1f020, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1842 PINGROUP(soc_gpio66_pr5, RSVD0, RSVD1, RSVD2, RSVD3, 0x1f028, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1843 PINGROUP(soc_gpio67_pr6, RSVD0, RSVD1, RSVD2, RSVD3, 0x1f030, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1844 PINGROUP(soc_gpio68_pr7, RSVD0, RSVD1, RSVD2, RSVD3, 0x1f038, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1845 PINGROUP(spi3_miso_pa4, SPI3_DIN, RSVD1, RSVD2, RSVD3, 0xd000, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1846 PINGROUP(spi1_cs0_pb3, SPI1_CS0, RSVD1, RSVD2, RSVD3, 0xd008, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1847 PINGROUP(spi3_cs0_pa6, SPI3_CS0, RSVD1, RSVD2, RSVD3, 0xd010, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1848 PINGROUP(spi1_miso_pb1, SPI1_DIN, RSVD1, RSVD2, RSVD3, 0xd018, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1849 PINGROUP(spi3_cs1_pa7, SPI3_CS1, RSVD1, RSVD2, RSVD3, 0xd020, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1850 PINGROUP(spi1_sck_pb0, SPI1_SCK, RSVD1, RSVD2, RSVD3, 0xd028, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1851 PINGROUP(spi3_sck_pa3, SPI3_SCK, RSVD1, RSVD2, RSVD3, 0xd030, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1852 PINGROUP(spi1_cs1_pb4, SPI1_CS1, RSVD1, RSVD2, RSVD3, 0xd038, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1853 PINGROUP(spi1_mosi_pb2, SPI1_DOUT, RSVD1, RSVD2, RSVD3, 0xd040, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1854 PINGROUP(spi3_mosi_pa5, SPI3_DOUT, RSVD1, RSVD2, RSVD3, 0xd048, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1855 PINGROUP(gpu_pwr_req_pa0, RSVD0, RSVD1, RSVD2, RSVD3, 0xd050, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1856 PINGROUP(gp_pwm5_pa1, GP_PWM5, RSVD1, RSVD2, RSVD3, 0xd058, 0, Y, 5, 7, 6, 8, -1, 10, 12),
1857 PINGROUP(gp_pwm6_pa2, GP_PWM6, RSVD1, RSVD2, RSVD3, 0xd060, 0, Y, 5, 7, 6, 8, -1, 10, 12),
1858 PINGROUP(extperiph2_clk_pc3, EXTPERIPH2_CLK, RSVD1, RSVD2, RSVD3, 0x0000, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1859 PINGROUP(extperiph1_clk_pc2, EXTPERIPH1_CLK, RSVD1, RSVD2, RSVD3, 0x0008, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1860 PINGROUP(cam_i2c_sda_pc5, I2C3_DAT, RSVD1, RSVD2, RSVD3, 0x0010, 0, Y, 5, 7, 6, 8, -1, 10, 12),
1861 PINGROUP(cam_i2c_scl_pc4, I2C3_CLK, RSVD1, RSVD2, RSVD3, 0x0018, 0, Y, 5, 7, 6, 8, -1, 10, 12),
1862 PINGROUP(soc_gpio23_pc6, RSVD0, RSVD1, RSVD2, RSVD3, 0x0020, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1863 PINGROUP(soc_gpio24_pc7, RSVD0, RSVD1, RSVD2, RSVD3, 0x0028, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1864 PINGROUP(soc_gpio27_pd0, RSVD0, GP_PWM8, RSVD2, RSVD3, 0x0040, 0, Y, 5, 7, 6, 8, -1, 10, 12),
1865 PINGROUP(soc_gpio29_pd2, RSVD0, NV_THERM_FAN_TACH0, RSVD2, RSVD3, 0x0050, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1866 PINGROUP(soc_gpio32_pd4, EXTPERIPH4_CLK, RSVD1, RSVD2, RSVD3, 0x0068, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1867 PINGROUP(soc_gpio33_pd3, EXTPERIPH3_CLK, RSVD1, RSVD2, RSVD3, 0x0070, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1868 PINGROUP(soc_gpio35_pd5, RSVD0, RSVD1, RSVD2, RSVD3, 0x0078, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1869 PINGROUP(soc_gpio37_pd6, DMIC2_DAT, RSVD1, RSVD2, RSVD3, 0x0080, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1870 PINGROUP(soc_gpio56_pd7, DMIC2_CLK, RSVD1, RSVD2, RSVD3, 0x0088, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1871 PINGROUP(soc_gpio55_pd1, RSVD0, WDT_RESET_OUTA, RSVD2, RSVD3, 0x0090, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1872 PINGROUP(uart1_cts_pe3, UARTA_CTS, RSVD1, RSVD2, RSVD3, 0x0098, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1873 PINGROUP(uart1_rts_pe2, UARTA_RTS, RSVD1, RSVD2, RSVD3, 0x00a0, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1874 PINGROUP(uart1_rx_pe1, UARTA_RXD, RSVD1, RSVD2, RSVD3, 0x00a8, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1875 PINGROUP(uart1_tx_pe0, UARTA_TXD, RSVD1, RSVD2, RSVD3, 0x00b0, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1876 PINGROUP(pwr_i2c_scl_pc0, I2C5_CLK, RSVD1, RSVD2, RSVD3, 0x00b8, 0, Y, 5, 7, 6, 8, -1, 10, 12),
1877 PINGROUP(pwr_i2c_sda_pc1, I2C5_DAT, RSVD1, RSVD2, RSVD3, 0x00c0, 0, Y, 5, 7, 6, 8, -1, 10, 12),
1878 PINGROUP(cpu_pwr_req_ph4, RSVD0, RSVD1, RSVD2, RSVD3, 0x4000, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1879 PINGROUP(uart4_cts_pg5, UARTD_CTS, RSVD1, RSVD2, RSVD3, 0x4008, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1880 PINGROUP(uart4_rts_pg4, UARTD_RTS, RSVD1, RSVD2, RSVD3, 0x4010, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1881 PINGROUP(uart4_rx_pg3, UARTD_RXD, RSVD1, RSVD2, RSVD3, 0x4018, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1882 PINGROUP(uart4_tx_pg2, UARTD_TXD, RSVD1, RSVD2, RSVD3, 0x4020, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1883 PINGROUP(gen1_i2c_scl_ph2, I2C1_CLK, RSVD1, RSVD2, RSVD3, 0x4028, 0, Y, 5, 7, 6, 8, -1, 10, 12),
1884 PINGROUP(gen1_i2c_sda_ph3, I2C1_DAT, RSVD1, RSVD2, RSVD3, 0x4030, 0, Y, 5, 7, 6, 8, -1, 10, 12),
1885 PINGROUP(soc_gpio20_pf6, SDMMC1_CD, RSVD1, RSVD2, RSVD3, 0x4038, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1886 PINGROUP(soc_gpio21_pf7, RSVD0, RSVD1, RSVD2, RSVD3, 0x4040, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1887 PINGROUP(soc_gpio22_pg0, RSVD0, RSVD1, RSVD2, RSVD3, 0x4048, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1888 PINGROUP(soc_gpio13_pf0, RSVD0, RSVD1, RSVD2, RSVD3, 0x4050, 0, Y, 5, 7, 6, 8, -1, 10, 12),
1889 PINGROUP(soc_gpio14_pf1, RSVD0, RSVD1, RSVD2, RSVD3, 0x4058, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1890 PINGROUP(soc_gpio15_pf2, RSVD0, RSVD1, RSVD2, RSVD3, 0x4060, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1891 PINGROUP(soc_gpio16_pf3, RSVD0, RSVD1, RSVD2, RSVD3, 0x4068, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1892 PINGROUP(soc_gpio17_pf4, RSVD0, CCLA_LA_TRIGGER_MUX, RSVD2, RSVD3, 0x4070, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1893 PINGROUP(soc_gpio18_pf5, RSVD0, RSVD1, RSVD2, RSVD3, 0x4078, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1894 PINGROUP(soc_gpio41_pg6, I2S2_SCLK, RSVD1, RSVD2, RSVD3, 0x4088, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1895 PINGROUP(soc_gpio42_pg7, I2S2_SDATA_OUT, RSVD1, RSVD2, RSVD3, 0x4090, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1896 PINGROUP(soc_gpio43_ph0, I2S2_SDATA_IN, RSVD1, RSVD2, RSVD3, 0x4098, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1897 PINGROUP(soc_gpio44_ph1, I2S2_LRCK, RSVD1, RSVD2, RSVD3, 0x40a0, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1898 PINGROUP(soc_gpio06_pg1, RSVD0, RSVD1, RSVD2, RSVD3, 0x40a8, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1899 PINGROUP(soc_gpio07_ph5, RSVD0, RSVD1, RSVD2, RSVD3, 0x40b0, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1900 PINGROUP(dap4_sclk_pp4, I2S4_SCLK, RSVD1, RSVD2, RSVD3, 0x2000, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1901 PINGROUP(dap4_dout_pp5, I2S4_SDATA_OUT, RSVD1, RSVD2, RSVD3, 0x2008, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1902 PINGROUP(dap4_din_pp6, I2S4_SDATA_IN, RSVD1, RSVD2, RSVD3, 0x2010, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1903 PINGROUP(dap4_fs_pp7, I2S4_LRCK, RSVD1, RSVD2, RSVD3, 0x2018, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1904 PINGROUP(soc_gpio167_pp0, RSVD0, RSVD1, RSVD2, RSVD3, 0x2040, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1905 PINGROUP(soc_gpio168_pp1, RSVD0, RSVD1, RSVD2, RSVD3, 0x2048, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1906 PINGROUP(soc_gpio169_pp2, RSVD0, RSVD1, RSVD2, RSVD3, 0x2050, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1907 PINGROUP(soc_gpio170_pp3, RSVD0, RSVD1, RSVD2, RSVD3, 0x2058, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1908 PINGROUP(soc_gpio171_pq0, RSVD0, RSVD1, RSVD2, RSVD3, 0x2060, 0, Y, 5, 7, 6, 8, -1, 10, 12),
1909 PINGROUP(soc_gpio172_pq1, RSVD0, RSVD1, RSVD2, RSVD3, 0x2068, 0, Y, 5, 7, 6, 8, -1, 10, 12),
1910 PINGROUP(soc_gpio173_pq2, RSVD0, RSVD1, RSVD2, RSVD3, 0x2070, 0, Y, 5, 7, 6, 8, -1, 10, 12),
1911 PINGROUP(soc_gpio45_pk0, I2S1_SCLK, DSPK1_DAT, DMIC3_CLK, RSVD3, 0x18000, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1912 PINGROUP(soc_gpio46_pk1, I2S1_SDATA_OUT, DSPK1_CLK, DMIC3_DAT, RSVD3, 0x18008, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1913 PINGROUP(soc_gpio47_pk2, I2S1_SDATA_IN, RSVD1, RSVD2, RSVD3, 0x18010, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1914 PINGROUP(soc_gpio48_pk3, I2S1_LRCK, RSVD1, RSVD2, RSVD3, 0x18018, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1915 PINGROUP(soc_gpio57_pj4, RSVD0, RSVD1, RSVD2, SDMMC1_WP, 0x18020, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1916 PINGROUP(soc_gpio58_pj5, RSVD0, RSVD1, RSVD2, RSVD3, 0x18028, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1917 PINGROUP(soc_gpio59_pj6, AUD_MCLK, RSVD1, RSVD2, RSVD3, 0x18030, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1918 PINGROUP(soc_gpio60_pj7, RSVD0, NV_THERM_FAN_TACH1, RSVD2, RSVD3, 0x18038, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1919 PINGROUP(dap3_fs_pj3, I2S3_LRCK, RSVD1, RSVD2, RSVD3, 0x18060, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1920 PINGROUP(dap3_clk_pj0, I2S3_SCLK, DSPK0_DAT, DMIC4_CLK, RSVD3, 0x18068, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1921 PINGROUP(dap3_din_pj2, I2S3_SDATA_IN, RSVD1, RSVD2, RSVD3, 0x18070, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1922 PINGROUP(dap3_dout_pj1, I2S3_SDATA_OUT, DSPK0_CLK, DMIC4_DAT, RSVD3, 0x18078, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1923 PINGROUP(pex_l2_clkreq_n_pw4, PE2_CLKREQ_L, RSVD1, RSVD2, RSVD3, 0x7000, 0, Y, 5, 7, 6, 8, -1, 10, 12),
1924 PINGROUP(pex_wake_n_px0, RSVD0, RSVD1, RSVD2, RSVD3, 0x7008, 0, Y, 5, 7, 6, 8, -1, 10, 12),
1925 PINGROUP(pex_l1_clkreq_n_pw2, PE1_CLKREQ_L, RSVD1, RSVD2, RSVD3, 0x7010, 0, Y, 5, 7, 6, 8, -1, 10, 12),
1926 PINGROUP(pex_l1_rst_n_pw3, PE1_RST_L, RSVD1, RSVD2, RSVD3, 0x7018, 0, Y, 5, 7, 6, 8, -1, 10, 12),
1927 PINGROUP(pex_l0_clkreq_n_pw0, PE0_CLKREQ_L, RSVD1, RSVD2, RSVD3, 0x7020, 0, Y, 5, 7, 6, 8, -1, 10, 12),
1928 PINGROUP(pex_l0_rst_n_pw1, PE0_RST_L, RSVD1, RSVD2, RSVD3, 0x7028, 0, Y, 5, 7, 6, 8, -1, 10, 12),
1929 PINGROUP(pex_l2_rst_n_pw5, PE2_RST_L, RSVD1, RSVD2, RSVD3, 0x7030, 0, Y, 5, 7, 6, 8, -1, 10, 12),
1930 PINGROUP(pex_l3_clkreq_n_pw6, PE3_CLKREQ_L, RSVD1, RSVD2, RSVD3, 0x7038, 0, Y, 5, 7, 6, 8, -1, 10, 12),
1931 PINGROUP(pex_l3_rst_n_pw7, PE3_RST_L, RSVD1, RSVD2, RSVD3, 0x7040, 0, Y, 5, 7, 6, 8, -1, 10, 12),
1932 PINGROUP(dp_aux_ch0_hpd_px1, DP_AUX_CH0_HPD, RSVD1, RSVD2, RSVD3, 0x7048, 0, Y, 5, 7, 6, 8, -1, 10, 12),
1933 PINGROUP(qspi0_io0_pl1, QSPI0_IO0, RSVD1, RSVD2, RSVD3, 0xb000, 0, Y, -1, 5, 6, -1, -1, 10, 12),
1934 PINGROUP(qspi0_io1_pl2, QSPI0_IO1, RSVD1, RSVD2, RSVD3, 0xb008, 0, Y, -1, 5, 6, -1, -1, 10, 12),
1935 PINGROUP(qspi0_sck_pl0, QSPI0_SCK, RSVD1, RSVD2, RSVD3, 0xb010, 0, Y, -1, 5, 6, -1, -1, 10, 12),
1936 PINGROUP(qspi0_cs_n_pl3, QSPI0_CS_N, RSVD1, RSVD2, RSVD3, 0xb018, 0, Y, -1, 5, 6, -1, -1, 10, 12),
1937 PINGROUP(soc_gpio156_pm0, RSVD0, I2S5_SCLK, RSVD2, RSVD3, 0xb020, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1938 PINGROUP(soc_gpio155_pl7, RSVD0, I2S6_LRCK, RSVD2, RSVD3, 0xb028, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1939 PINGROUP(soc_gpio160_pm4, RSVD0, RSVD1, RSVD2, RSVD3, 0xb030, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1940 PINGROUP(soc_gpio154_pl6, RSVD0, I2S6_SDATA_IN, RSVD2, RSVD3, 0xb038, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1941 PINGROUP(soc_gpio152_pl4, RSVD0, I2S6_SCLK, RSVD2, RSVD3, 0xb040, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1942 PINGROUP(soc_gpio153_pl5, RSVD0, I2S6_SDATA_OUT, RSVD2, RSVD3, 0xb048, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1943 PINGROUP(soc_gpio161_pm5, RSVD0, RSVD1, RSVD2, RSVD3, 0xb050, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1944 PINGROUP(soc_gpio162_pm6, RSVD0, RSVD1, RSVD2, RSVD3, 0xb058, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1945 PINGROUP(soc_gpio159_pm3, RSVD0, I2S5_LRCK, RSVD2, RSVD3, 0xb060, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1946 PINGROUP(soc_gpio157_pm1, RSVD0, I2S5_SDATA_OUT, RSVD2, RSVD3, 0xb068, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1947 PINGROUP(soc_gpio158_pm2, RSVD0, I2S5_SDATA_IN, RSVD2, RSVD3, 0xb070, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1948 PINGROUP(uart7_cts_pn2, UARTG_CTS, RSVD1, RSVD2, RSVD3, 0xb078, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1949 PINGROUP(uart7_rts_pn1, UARTG_RTS, RSVD1, RSVD2, RSVD3, 0xb080, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1950 PINGROUP(uart7_tx_pm7, UARTG_TXD, RSVD1, RSVD2, RSVD3, 0xb088, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1951 PINGROUP(uart7_rx_pn0, UARTG_RXD, RSVD1, RSVD2, RSVD3, 0xb090, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1952 PINGROUP(sdmmc1_clk_pu0, SDMMC1_CLK, RSVD1, RSVD2, RSVD3, 0x8000, 0, Y, -1, 5, 6, -1, 9, 10, 12),
1953 PINGROUP(sdmmc1_cmd_pu1, SDMMC1_CMD, RSVD1, RSVD2, RSVD3, 0x8008, 0, Y, -1, 5, 6, -1, 9, 10, 12),
1954 PINGROUP(sdmmc1_comp, SDMMC1_COMP, RSVD1, RSVD2, RSVD3, 0x8010, 0, N, -1, -1, -1, -1, -1, -1, -1),
1955 PINGROUP(sdmmc1_dat3_pu5, SDMMC1_DAT3, SDMMC1_PE3_RST_L, RSVD2, RSVD3, 0x8018, 0, Y, -1, 5, 6, -1, 9, 10, 12),
1956 PINGROUP(sdmmc1_dat2_pu4, SDMMC1_DAT2, SDMMC1_PE3_CLKREQ_L, RSVD2, RSVD3, 0x8020, 0, Y, -1, 5, 6, -1, 9, 10, 12),
1957 PINGROUP(sdmmc1_dat1_pu3, SDMMC1_DAT1, RSVD1, RSVD2, RSVD3, 0x8028, 0, Y, -1, 5, 6, -1, 9, 10, 12),
1958 PINGROUP(sdmmc1_dat0_pu2, SDMMC1_DAT0, RSVD1, RSVD2, RSVD3, 0x8030, 0, Y, -1, 5, 6, -1, 9, 10, 12),
1959 PINGROUP(ufs0_rst_n_pv1, UFS0, RSVD1, RSVD2, RSVD3, 0x11000, 0, Y, -1, 5, 6, -1, -1, 10, 12),
1960 PINGROUP(ufs0_ref_clk_pv0, UFS0, RSVD1, RSVD2, RSVD3, 0x11008, 0, Y, -1, 5, 6, -1, -1, 10, 12),
1961
1962};
1963
1964static const struct tegra_pingroup tegra238_aon_groups[] = {
1965 PINGROUP(bootv_ctl_n_paa0, RSVD0, RSVD1, RSVD2, RSVD3, 0x1028, 1, Y, -1, 7, 6, 8, -1, 10, 12),
1966 PINGROUP(soc_gpio00_paa1, RSVD0, RSVD1, RSVD2, RSVD3, 0x10f0, 1, Y, 5, 7, 6, 8, -1, 10, 12),
1967 PINGROUP(vcomp_alert_paa2, SOC_THERM_OC1, RSVD1, RSVD2, RSVD3, 0x1058, 1, Y, 5, 7, 6, 8, -1, 10, 12),
1968 PINGROUP(pwm1_paa3, GP_PWM1, RSVD1, RSVD2, RSVD3, 0x11c0, 1, Y, 5, 7, 6, 8, -1, 10, 12),
1969 PINGROUP(batt_oc_paa4, SOC_THERM_OC2, RSVD1, RSVD2, RSVD3, 0x1020, 1, Y, 5, 7, 6, 8, -1, 10, 12),
1970 PINGROUP(soc_gpio04_paa5, RSVD0, RSVD1, RSVD2, RSVD3, 0x1140, 1, Y, 5, 7, 6, 8, -1, 10, 12),
1971 PINGROUP(soc_gpio25_paa6, RSVD0, RSVD1, RSVD2, RSVD3, 0x1158, 1, Y, -1, 7, 6, 8, -1, 10, 12),
1972 PINGROUP(soc_gpio26_paa7, RSVD0, SOC_THERM_OC3, RSVD2, RSVD3, 0x1160, 1, Y, -1, 7, 6, 8, -1, 10, 12),
1973 PINGROUP(hdmi_cec_pbb0, HDMI_CEC, RSVD1, RSVD2, RSVD3, 0x1060, 1, Y, 5, 7, 6, 8, -1, 10, 12),
1974 PINGROUP(spi2_sck_pcc0, SPI2_SCK, RSVD1, RSVD2, RSVD3, 0x10b0, 1, Y, -1, 7, 6, 8, -1, 10, 12),
1975 PINGROUP(spi2_miso_pcc1, SPI2_DIN, RSVD1, RSVD2, RSVD3, 0x10b8, 1, Y, -1, 7, 6, 8, -1, 10, 12),
1976 PINGROUP(spi2_mosi_pcc2, SPI2_DOUT, RSVD1, RSVD2, RSVD3, 0x1090, 1, Y, -1, 7, 6, 8, -1, 10, 12),
1977 PINGROUP(spi2_cs0_pcc3, SPI2_CS0, RSVD1, RSVD2, RSVD3, 0x10a0, 1, Y, -1, 7, 6, 8, -1, 10, 12),
1978 PINGROUP(spi2_cs1_pcc4, SPI2_CS1, RSVD1, RSVD2, RSVD3, 0x11c8, 1, Y, -1, 7, 6, 8, -1, 10, 12),
1979 PINGROUP(uart3_tx_pcc5, UARTC_TXD, RSVD1, RSVD2, RSVD3, 0x1078, 1, Y, 5, 7, 6, 8, -1, 10, 12),
1980 PINGROUP(uart3_rx_pcc6, UARTC_RXD, RSVD1, RSVD2, RSVD3, 0x1070, 1, Y, 5, 7, 6, 8, -1, 10, 12),
1981 PINGROUP(gen2_i2c_scl_pcc7, I2C2_CLK, RSVD1, RSVD2, RSVD3, 0x1098, 1, Y, 5, 7, 6, 8, -1, 10, 12),
1982 PINGROUP(gen2_i2c_sda_pdd0, I2C2_DAT, RSVD1, RSVD2, RSVD3, 0x10a8, 1, Y, 5, 7, 6, 8, -1, 10, 12),
1983 PINGROUP(gen8_i2c_scl_pdd1, I2C8_CLK, RSVD1, RSVD2, RSVD3, 0x1088, 1, Y, 5, 7, 6, 8, -1, 10, 12),
1984 PINGROUP(gen8_i2c_sda_pdd2, I2C8_DAT, RSVD1, RSVD2, RSVD3, 0x1080, 1, Y, 5, 7, 6, 8, -1, 10, 12),
1985 PINGROUP(touch_clk_pdd3, GP_PWM4, TOUCH_CLK, RSVD2, RSVD3, 0x1068, 1, Y, 5, 7, 6, 8, -1, 10, 12),
1986 PINGROUP(dmic1_clk_pdd4, DMIC1_CLK, RSVD1, DMIC5_CLK, RSVD3, 0x11d0, 1, Y, -1, 7, 6, 8, -1, 10, 12),
1987 PINGROUP(dmic1_dat_pdd5, DMIC1_DAT, RSVD1, DMIC5_DAT, RSVD3, 0x11d8, 1, Y, -1, 7, 6, 8, -1, 10, 12),
1988 PINGROUP(soc_gpio19_pdd6, RSVD0, WDT_RESET_OUTB, RSVD2, RSVD3, 0x10f8, 1, Y, -1, 7, 6, 8, -1, 10, 12),
1989 PINGROUP(soc_gpio49_pee2, RSVD0, RSVD1, RSVD2, RSVD3, 0x10c0, 1, Y, -1, 7, 6, 8, -1, 10, 12),
1990 PINGROUP(soc_gpio50_pee4, RSVD0, RSVD1, RSVD2, RSVD3, 0x10c8, 1, Y, -1, 7, 6, 8, -1, 10, 12),
1991 PINGROUP(soc_gpio82_pee3, RSVD0, RSVD1, RSVD2, RSVD3, 0x10d0, 1, Y, -1, 7, 6, 8, -1, 10, 12),
1992 PINGROUP(soc_gpio71_pff2, PPC_MODE_1, RSVD1, RSVD2, RSVD3, 0x10d8, 1, Y, 5, 7, 6, 8, -1, 10, 12),
1993 PINGROUP(soc_gpio76_pff7, RSVD0, RSVD1, TSC_EDGE_OUT0, TSC_EDGE_OUT0A, 0x10e0, 1, Y, -1, 7, 6, 8, -1, 10, 12),
1994 PINGROUP(soc_gpio74_pff5, PPC_READY, PPC_I2C_DAT, RSVD2, RSVD3, 0x10e8, 1, Y, 5, 7, 6, 8, -1, 10, 12),
1995 PINGROUP(soc_gpio86_phh3, RSVD0, SPI5_CS1, TSC_EDGE_OUT3, TSC_EDGE_OUT0D, 0x1100, 1, Y, 5, 7, 6, 8, -1, 10, 12),
1996 PINGROUP(soc_gpio72_pff3, PPC_MODE_2, RSVD1, RSVD2, RSVD3, 0x1108, 1, Y, 5, 7, 6, 8, -1, 10, 12),
1997 PINGROUP(soc_gpio77_pgg0, RSVD0, RSVD1, TSC_EDGE_OUT1, TSC_EDGE_OUT0B, 0x1110, 1, Y, -1, 7, 6, 8, -1, 10, 12),
1998 PINGROUP(soc_gpio80_pff6, RSVD0, PPC_RST_N, RSVD2, RSVD3, 0x1118, 1, Y, 5, 7, 6, 8, -1, 10, 12),
1999 PINGROUP(soc_gpio84_pgg1, RSVD0, RSVD1, TSC_EDGE_OUT2, TSC_EDGE_OUT0C, 0x1120, 1, Y, -1, 7, 6, 8, -1, 10, 12),
2000 PINGROUP(soc_gpio83_pee5, RSVD0, RSVD1, RSVD2, RSVD3, 0x1128, 1, Y, -1, 7, 6, 8, -1, 10, 12),
2001 PINGROUP(soc_gpio73_pff4, PPC_CC, PPC_I2C_CLK, RSVD2, RSVD3, 0x1130, 1, Y, 5, 7, 6, 8, -1, 10, 12),
2002 PINGROUP(soc_gpio70_pff1, PPC_MODE_0, RSVD1, RSVD2, RSVD3, 0x1138, 1, Y, 5, 7, 6, 8, -1, 10, 12),
2003 PINGROUP(soc_gpio85_pgg6, RSVD0, SPI4_CS1, RSVD2, RSVD3, 0x1148, 1, Y, 5, 7, 6, 8, -1, 10, 12),
2004 PINGROUP(soc_gpio69_pff0, PPC_INT_N, RSVD1, RSVD2, RSVD3, 0x1150, 1, Y, 5, 7, 6, 8, -1, 10, 12),
2005 PINGROUP(uart5_tx_pgg7, UARTE_TXD, SPI5_SCK, RSVD2, RSVD3, 0x1168, 1, Y, 5, 7, 6, 8, -1, 10, 12),
2006 PINGROUP(uart5_rx_phh0, UARTE_RXD, SPI5_MISO, RSVD2, RSVD3, 0x1170, 1, Y, 5, 7, 6, 8, -1, 10, 12),
2007 PINGROUP(uart2_tx_pgg2, UARTB_TXD, SPI4_SCK, RSVD2, RSVD3, 0x1178, 1, Y, 5, 7, 6, 8, -1, 10, 12),
2008 PINGROUP(uart2_rx_pgg3, UARTB_RXD, SPI4_MISO, RSVD2, RSVD3, 0x1180, 1, Y, 5, 7, 6, 8, -1, 10, 12),
2009 PINGROUP(uart2_cts_pgg5, UARTB_CTS, SPI4_CS0, RSVD2, RSVD3, 0x1188, 1, Y, 5, 7, 6, 8, -1, 10, 12),
2010 PINGROUP(uart2_rts_pgg4, UARTB_RTS, SPI4_MOSI, RSVD2, RSVD3, 0x1190, 1, Y, 5, 7, 6, 8, -1, 10, 12),
2011 PINGROUP(uart5_cts_phh2, UARTE_CTS, SPI5_CS0, RSVD2, RSVD3, 0x1198, 1, Y, 5, 7, 6, 8, -1, 10, 12),
2012 PINGROUP(uart5_rts_phh1, UARTE_RTS, SPI5_MOSI, RSVD2, RSVD3, 0x11a0, 1, Y, 5, 7, 6, 8, -1, 10, 12),
2013 PINGROUP(pwm2_pdd7, GP_PWM2, LED_BLINK, RSVD2, RSVD3, 0x11b0, 1, Y, 5, 7, 6, 8, -1, 10, 12),
2014 PINGROUP(pwm3_pee0, GP_PWM3, RSVD1, RSVD2, RSVD3, 0x11b8, 1, Y, 5, 7, 6, 8, -1, 10, 12),
2015 PINGROUP(pwm7_pee1, GP_PWM7, RSVD1, RSVD2, RSVD3, 0x11a8, 1, Y, 5, 7, 6, 8, -1, 10, 12),
2016};
2017
2018static const struct tegra_pinctrl_soc_data tegra238_pinctrl_aon = {
2019 .pins = tegra238_aon_pins,
2020 .npins = ARRAY_SIZE(tegra238_aon_pins),
2021 .functions = tegra238_functions,
2022 .nfunctions = ARRAY_SIZE(tegra238_functions),
2023 .groups = tegra238_aon_groups,
2024 .ngroups = ARRAY_SIZE(tegra238_aon_groups),
2025 .hsm_in_mux = false,
2026 .schmitt_in_mux = true,
2027 .drvtype_in_mux = true,
2028 .sfsel_in_mux = true,
2029};
2030
2031static const struct tegra_pinctrl_soc_data tegra238_pinctrl = {
2032 .pins = tegra238_pins,
2033 .npins = ARRAY_SIZE(tegra238_pins),
2034 .functions = tegra238_functions,
2035 .nfunctions = ARRAY_SIZE(tegra238_functions),
2036 .groups = tegra238_groups,
2037 .ngroups = ARRAY_SIZE(tegra238_groups),
2038 .hsm_in_mux = false,
2039 .schmitt_in_mux = true,
2040 .drvtype_in_mux = true,
2041 .sfsel_in_mux = true,
2042};
2043
2044static int tegra238_pinctrl_probe(struct platform_device *pdev)
2045{
2046 const struct tegra_pinctrl_soc_data *soc = device_get_match_data(&pdev->dev);
2047
2048 return tegra_pinctrl_probe(pdev, soc);
2049}
2050
2051static const struct of_device_id tegra238_pinctrl_of_match[] = {
2052 { .compatible = "nvidia,tegra238-pinmux", .data = &tegra238_pinctrl },
2053 { .compatible = "nvidia,tegra238-pinmux-aon", .data = &tegra238_pinctrl_aon },
2054 { }
2055};
2056MODULE_DEVICE_TABLE(of, tegra238_pinctrl_of_match);
2057
2058static struct platform_driver tegra238_pinctrl_driver = {
2059 .driver = {
2060 .name = "tegra238-pinctrl",
2061 .of_match_table = tegra238_pinctrl_of_match,
2062 },
2063 .probe = tegra238_pinctrl_probe,
2064};
2065
2066static int __init tegra238_pinctrl_init(void)
2067{
2068 return platform_driver_register(&tegra238_pinctrl_driver);
2069}
2070module_init(tegra238_pinctrl_init);
2071
2072static void __exit tegra238_pinctrl_exit(void)
2073{
2074 platform_driver_unregister(&tegra238_pinctrl_driver);
2075}
2076module_exit(tegra238_pinctrl_exit);
2077
2078MODULE_LICENSE("GPL");
2079MODULE_AUTHOR("NVIDIA Corporation");
2080MODULE_DESCRIPTION("NVIDIA Tegra238 pinctrl driver");
drivers/pinctrl/tegra/pinctrl-tegra264.c+2216−0
@@ -0,0 +1,2216 @@
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Pinctrl data for the NVIDIA Tegra264 pinmux
4 *
5 * Copyright (c) 2024-2026, NVIDIA CORPORATION. All rights reserved.
6 */
7
8#include <linux/mod_devicetable.h>
9#include <linux/module.h>
10#include <linux/platform_device.h>
11#include <linux/property.h>
12#include <linux/pinctrl/pinctrl.h>
13#include <linux/pinctrl/pinmux.h>
14
15#include "pinctrl-tegra.h"
16
17/* Define unique ID for each pins */
18enum {
19 TEGRA_PIN_PEX_L4_CLKREQ_N_PD0,
20 TEGRA_PIN_PEX_L4_RST_N_PD1,
21 TEGRA_PIN_PEX_L5_CLKREQ_N_PD2,
22 TEGRA_PIN_PEX_L5_RST_N_PD3,
23 TEGRA_PIN_ETH0_MDIO_PD4,
24 TEGRA_PIN_ETH0_MDC_PD5,
25 TEGRA_PIN_ETH3_MDIO_PD6,
26 TEGRA_PIN_ETH3_MDC_PD7,
27 TEGRA_PIN_ETH1_MDIO_PE0,
28 TEGRA_PIN_ETH1_MDC_PE1,
29 TEGRA_PIN_ETH2_MDIO_PE2,
30 TEGRA_PIN_ETH2_MDC_PE3,
31 TEGRA_PIN_PEX_L1_CLKREQ_N_PB0,
32 TEGRA_PIN_PEX_L1_RST_N_PB1,
33 TEGRA_PIN_PEX_L2_CLKREQ_N_PB2,
34 TEGRA_PIN_PEX_L2_RST_N_PB3,
35 TEGRA_PIN_PEX_L3_CLKREQ_N_PB4,
36 TEGRA_PIN_PEX_L3_RST_N_PB5,
37 TEGRA_PIN_SOC_GPIO113_PB6,
38 TEGRA_PIN_SOC_GPIO114_PB7,
39 TEGRA_PIN_SGMII0_SMA_MDIO_PC0,
40 TEGRA_PIN_SGMII0_SMA_MDC_PC1,
41 TEGRA_PIN_PEX_WAKE_N_PC2,
42 TEGRA_PIN_PWM1_PA0,
43 TEGRA_PIN_PWM6_PA1,
44 TEGRA_PIN_PWM7_PA2,
45 TEGRA_PIN_PWM8_PA3,
46 TEGRA_PIN_UFS0_REF_CLK_PA4,
47 TEGRA_PIN_UFS0_RST_N_PA5,
48};
49
50enum {
51 TEGRA_PIN_SOC_GPIO250_PF0,
52 TEGRA_PIN_SOC_GPIO251_PF1,
53 TEGRA_PIN_SOC_GPIO252_PF2,
54 TEGRA_PIN_DP_AUX_CH0_HPD_PF3,
55 TEGRA_PIN_DP_AUX_CH1_HPD_PF4,
56 TEGRA_PIN_DP_AUX_CH2_HPD_PF5,
57 TEGRA_PIN_DP_AUX_CH3_HPD_PF6,
58 TEGRA_PIN_PWM2_PF7,
59 TEGRA_PIN_PWM3_PG0,
60 TEGRA_PIN_GEN7_I2C_SCL_PG1,
61 TEGRA_PIN_GEN7_I2C_SDA_PG2,
62 TEGRA_PIN_GEN9_I2C_SCL_PG3,
63 TEGRA_PIN_GEN9_I2C_SDA_PG4,
64 TEGRA_PIN_SDMMC1_CLK_PX0,
65 TEGRA_PIN_SDMMC1_CMD_PX1,
66 TEGRA_PIN_SDMMC1_DAT0_PX2,
67 TEGRA_PIN_SDMMC1_DAT1_PX3,
68 TEGRA_PIN_SDMMC1_DAT2_PX4,
69 TEGRA_PIN_SDMMC1_DAT3_PX5,
70 TEGRA_PIN_SDMMC1_COMP,
71 TEGRA_PIN_SOC_GPIO124_PL0,
72 TEGRA_PIN_SOC_GPIO125_PL1,
73 TEGRA_PIN_FAN_TACH0_PL2,
74 TEGRA_PIN_SOC_GPIO127_PL3,
75 TEGRA_PIN_SOC_GPIO128_PL4,
76 TEGRA_PIN_SOC_GPIO129_PL5,
77 TEGRA_PIN_SOC_GPIO130_PL6,
78 TEGRA_PIN_SOC_GPIO131_PL7,
79 TEGRA_PIN_GP_PWM9_PM0,
80 TEGRA_PIN_SOC_GPIO133_PM1,
81 TEGRA_PIN_UART9_TX_PM2,
82 TEGRA_PIN_UART9_RX_PM3,
83 TEGRA_PIN_UART9_RTS_N_PM4,
84 TEGRA_PIN_UART9_CTS_N_PM5,
85 TEGRA_PIN_SOC_GPIO170_PU0,
86 TEGRA_PIN_SOC_GPIO171_PU1,
87 TEGRA_PIN_SOC_GPIO172_PU2,
88 TEGRA_PIN_SOC_GPIO173_PU3,
89 TEGRA_PIN_SOC_GPIO174_PU4,
90 TEGRA_PIN_SOC_GPIO175_PU5,
91 TEGRA_PIN_SOC_GPIO176_PU6,
92 TEGRA_PIN_SOC_GPIO177_PU7,
93 TEGRA_PIN_SOC_GPIO178_PV0,
94 TEGRA_PIN_PWM10_PV1,
95 TEGRA_PIN_UART4_TX_PV2,
96 TEGRA_PIN_UART4_RX_PV3,
97 TEGRA_PIN_UART4_RTS_N_PV4,
98 TEGRA_PIN_UART4_CTS_N_PV5,
99 TEGRA_PIN_DAP2_CLK_PV6,
100 TEGRA_PIN_DAP2_DIN_PV7,
101 TEGRA_PIN_DAP2_DOUT_PW0,
102 TEGRA_PIN_DAP2_FS_PW1,
103 TEGRA_PIN_GEN1_I2C_SCL_PW2,
104 TEGRA_PIN_GEN1_I2C_SDA_PW3,
105 TEGRA_PIN_GEN0_I2C_SCL_PW4,
106 TEGRA_PIN_GEN0_I2C_SDA_PW5,
107 TEGRA_PIN_PWR_I2C_SCL_PW6,
108 TEGRA_PIN_PWR_I2C_SDA_PW7,
109 TEGRA_PIN_SOC_GPIO138_PP0,
110 TEGRA_PIN_SOC_GPIO139_PP1,
111 TEGRA_PIN_DAP6_SCLK_PP2,
112 TEGRA_PIN_DAP6_DOUT_PP3,
113 TEGRA_PIN_DAP6_DIN_PP4,
114 TEGRA_PIN_DAP6_FS_PP5,
115 TEGRA_PIN_DAP4_SCLK_PP6,
116 TEGRA_PIN_DAP4_DOUT_PP7,
117 TEGRA_PIN_DAP4_DIN_PQ0,
118 TEGRA_PIN_DAP4_FS_PQ1,
119 TEGRA_PIN_SPI5_SCK_PQ2,
120 TEGRA_PIN_SPI5_MISO_PQ3,
121 TEGRA_PIN_SPI5_MOSI_PQ4,
122 TEGRA_PIN_SPI5_CS0_PQ5,
123 TEGRA_PIN_SOC_GPIO152_PQ6,
124 TEGRA_PIN_SOC_GPIO153_PQ7,
125 TEGRA_PIN_AUD_MCLK_PR0,
126 TEGRA_PIN_SOC_GPIO155_PR1,
127 TEGRA_PIN_DAP1_SCLK_PR2,
128 TEGRA_PIN_DAP1_OUT_PR3,
129 TEGRA_PIN_DAP1_IN_PR4,
130 TEGRA_PIN_DAP1_FS_PR5,
131 TEGRA_PIN_GEN11_I2C_SCL_PR6,
132 TEGRA_PIN_GEN11_I2C_SDA_PR7,
133 TEGRA_PIN_SOC_GPIO350_PS0,
134 TEGRA_PIN_SOC_GPIO351_PS1,
135 TEGRA_PIN_QSPI0_SCK_PT0,
136 TEGRA_PIN_QSPI0_CS_N_PT1,
137 TEGRA_PIN_QSPI0_IO0_PT2,
138 TEGRA_PIN_QSPI0_IO1_PT3,
139 TEGRA_PIN_QSPI0_IO2_PT4,
140 TEGRA_PIN_QSPI0_IO3_PT5,
141 TEGRA_PIN_SOC_GPIO192_PT6,
142 TEGRA_PIN_SOC_GPIO270_PY0,
143 TEGRA_PIN_SOC_GPIO271_PY1,
144 TEGRA_PIN_SOC_GPIO272_PY2,
145 TEGRA_PIN_SOC_GPIO273_PY3,
146 TEGRA_PIN_SOC_GPIO274_PY4,
147 TEGRA_PIN_SOC_GPIO275_PY5,
148 TEGRA_PIN_SOC_GPIO276_PY6,
149 TEGRA_PIN_SOC_GPIO277_PY7,
150 TEGRA_PIN_SOC_GPIO278_PZ0,
151 TEGRA_PIN_SOC_GPIO279_PZ1,
152 TEGRA_PIN_XHALT_TRIG_PZ2,
153 TEGRA_PIN_SOC_GPIO281_PZ3,
154 TEGRA_PIN_SOC_GPIO282_PZ4,
155 TEGRA_PIN_SOC_GPIO283_PZ5,
156 TEGRA_PIN_SOC_GPIO284_PZ6,
157 TEGRA_PIN_SOC_GPIO285_PZ7,
158 TEGRA_PIN_SOC_GPIO286_PAL0,
159 TEGRA_PIN_SOC_GPIO287_PAL1,
160 TEGRA_PIN_SOC_GPIO288_PAL2,
161 TEGRA_PIN_CPU_PWR_REQ_PH0,
162 TEGRA_PIN_GPU_PWR_REQ_PH1,
163 TEGRA_PIN_UART10_TX_PH2,
164 TEGRA_PIN_UART10_RX_PH3,
165 TEGRA_PIN_UART10_RTS_N_PH4,
166 TEGRA_PIN_UART10_CTS_N_PH5,
167 TEGRA_PIN_SPI3_SCK_PH6,
168 TEGRA_PIN_SPI3_MISO_PH7,
169 TEGRA_PIN_SPI3_MOSI_PJ0,
170 TEGRA_PIN_SPI3_CS0_PJ1,
171 TEGRA_PIN_SPI3_CS3_PJ2,
172 TEGRA_PIN_UART5_TX_PJ3,
173 TEGRA_PIN_UART5_RX_PJ4,
174 TEGRA_PIN_UART5_RTS_N_PJ5,
175 TEGRA_PIN_UART5_CTS_N_PJ6,
176 TEGRA_PIN_SPI1_SCK_PJ7,
177 TEGRA_PIN_SPI1_MISO_PK0,
178 TEGRA_PIN_SPI1_MOSI_PK1,
179 TEGRA_PIN_SPI1_CS0_PK2,
180 TEGRA_PIN_SPI1_CS1_PK3,
181 TEGRA_PIN_EXTPERIPH1_CLK_PK4,
182 TEGRA_PIN_EXTPERIPH2_CLK_PK5,
183 TEGRA_PIN_GEN12_I2C_SCL_PK6,
184 TEGRA_PIN_GEN12_I2C_SDA_PK7,
185};
186
187enum {
188 TEGRA_PIN_SOC_GPIO00_PAA0,
189 TEGRA_PIN_VCOMP_ALERT_PAA1,
190 TEGRA_PIN_AO_RETENTION_N_PAA2,
191 TEGRA_PIN_BATT_OC_PAA3,
192 TEGRA_PIN_BOOTV_CTL_N_PAA4,
193 TEGRA_PIN_POWER_ON_PAA5,
194 TEGRA_PIN_HDMI_CEC_PAA6,
195 TEGRA_PIN_SOC_GPIO07_PAA7,
196 TEGRA_PIN_SOC_GPIO08_PBB0,
197 TEGRA_PIN_SOC_GPIO09_PBB1,
198 TEGRA_PIN_GEN2_I2C_SCL_PCC0,
199 TEGRA_PIN_GEN2_I2C_SDA_PCC1,
200 TEGRA_PIN_GEN3_I2C_SCL_PCC2,
201 TEGRA_PIN_GEN3_I2C_SDA_PCC3,
202 TEGRA_PIN_GP_PWM4_PCC4,
203 TEGRA_PIN_UART0_TX_PCC5,
204 TEGRA_PIN_UART0_RX_PCC6,
205 TEGRA_PIN_SPI2_SCK_PCC7,
206 TEGRA_PIN_SPI2_MISO_PDD0,
207 TEGRA_PIN_SPI2_MOSI_PDD1,
208 TEGRA_PIN_SPI2_CS0_N_PDD2,
209 TEGRA_PIN_SOC_GPIO21_PDD3,
210 TEGRA_PIN_SOC_GPIO22_PDD4,
211 TEGRA_PIN_SOC_GPIO23_PDD5,
212 TEGRA_PIN_SOC_GPIO24_PDD6,
213 TEGRA_PIN_SOC_GPIO25_PDD7,
214 TEGRA_PIN_SOC_GPIO26_PEE0,
215 TEGRA_PIN_SOC_GPIO27_PEE1,
216 TEGRA_PIN_SOC_GPIO28_PEE2,
217 TEGRA_PIN_SOC_GPIO29_PEE3,
218};
219
220static const struct pinctrl_pin_desc tegra264_uphy_pins[] = {
221 PINCTRL_PIN(TEGRA_PIN_PEX_L4_CLKREQ_N_PD0, "PEX_L4_CLKREQ_N_PD0"),
222 PINCTRL_PIN(TEGRA_PIN_PEX_L4_RST_N_PD1, "PEX_L4_RST_N_PD1"),
223 PINCTRL_PIN(TEGRA_PIN_PEX_L5_CLKREQ_N_PD2, "PEX_L5_CLKREQ_N_PD2"),
224 PINCTRL_PIN(TEGRA_PIN_PEX_L5_RST_N_PD3, "PEX_L5_RST_N_PD3"),
225 PINCTRL_PIN(TEGRA_PIN_ETH0_MDIO_PD4, "ETH0_MDIO_PD4"),
226 PINCTRL_PIN(TEGRA_PIN_ETH0_MDC_PD5, "ETH0_MDC_PD5"),
227 PINCTRL_PIN(TEGRA_PIN_ETH3_MDIO_PD6, "ETH3_MDIO_PD6"),
228 PINCTRL_PIN(TEGRA_PIN_ETH3_MDC_PD7, "ETH3_MDC_PD7"),
229 PINCTRL_PIN(TEGRA_PIN_ETH1_MDIO_PE0, "ETH1_MDIO_PE0"),
230 PINCTRL_PIN(TEGRA_PIN_ETH1_MDC_PE1, "ETH1_MDC_PE1"),
231 PINCTRL_PIN(TEGRA_PIN_ETH2_MDIO_PE2, "ETH2_MDIO_PE2"),
232 PINCTRL_PIN(TEGRA_PIN_ETH2_MDC_PE3, "ETH2_MDC_PE3"),
233 PINCTRL_PIN(TEGRA_PIN_PEX_L1_CLKREQ_N_PB0, "PEX_L1_CLKREQ_N_PB0"),
234 PINCTRL_PIN(TEGRA_PIN_PEX_L1_RST_N_PB1, "PEX_L1_RST_N_PB1"),
235 PINCTRL_PIN(TEGRA_PIN_PEX_L2_CLKREQ_N_PB2, "PEX_L2_CLKREQ_N_PB2"),
236 PINCTRL_PIN(TEGRA_PIN_PEX_L2_RST_N_PB3, "PEX_L2_RST_N_PB3"),
237 PINCTRL_PIN(TEGRA_PIN_PEX_L3_CLKREQ_N_PB4, "PEX_L3_CLKREQ_N_PB4"),
238 PINCTRL_PIN(TEGRA_PIN_PEX_L3_RST_N_PB5, "PEX_L3_RST_N_PB5"),
239 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO113_PB6, "SOC_GPIO113_PB6"),
240 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO114_PB7, "SOC_GPIO114_PB7"),
241 PINCTRL_PIN(TEGRA_PIN_SGMII0_SMA_MDIO_PC0, "SGMII0_SMA_MDIO_PC0"),
242 PINCTRL_PIN(TEGRA_PIN_SGMII0_SMA_MDC_PC1, "SGMII0_SMA_MDC_PC1"),
243 PINCTRL_PIN(TEGRA_PIN_PEX_WAKE_N_PC2, "PEX_WAKE_N_PC2"),
244 PINCTRL_PIN(TEGRA_PIN_PWM1_PA0, "PWM1_PA0"),
245 PINCTRL_PIN(TEGRA_PIN_PWM6_PA1, "PWM6_PA1"),
246 PINCTRL_PIN(TEGRA_PIN_PWM7_PA2, "PWM7_PA2"),
247 PINCTRL_PIN(TEGRA_PIN_PWM8_PA3, "PWM8_PA3"),
248 PINCTRL_PIN(TEGRA_PIN_UFS0_REF_CLK_PA4, "UFS0_REF_CLK_PA4"),
249 PINCTRL_PIN(TEGRA_PIN_UFS0_RST_N_PA5, "UFS0_RST_N_PA5"),
250};
251
252static const struct pinctrl_pin_desc tegra264_main_pins[] = {
253 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO250_PF0, "SOC_GPIO250_PF0"),
254 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO251_PF1, "SOC_GPIO251_PF1"),
255 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO252_PF2, "SOC_GPIO252_PF2"),
256 PINCTRL_PIN(TEGRA_PIN_DP_AUX_CH0_HPD_PF3, "DP_AUX_CH0_HPD_PF3"),
257 PINCTRL_PIN(TEGRA_PIN_DP_AUX_CH1_HPD_PF4, "DP_AUX_CH1_HPD_PF4"),
258 PINCTRL_PIN(TEGRA_PIN_DP_AUX_CH2_HPD_PF5, "DP_AUX_CH2_HPD_PF5"),
259 PINCTRL_PIN(TEGRA_PIN_DP_AUX_CH3_HPD_PF6, "DP_AUX_CH3_HPD_PF6"),
260 PINCTRL_PIN(TEGRA_PIN_PWM2_PF7, "PWM2_PF7"),
261 PINCTRL_PIN(TEGRA_PIN_PWM3_PG0, "PWM3_PG0"),
262 PINCTRL_PIN(TEGRA_PIN_GEN7_I2C_SCL_PG1, "GEN7_I2C_SCL_PG1"),
263 PINCTRL_PIN(TEGRA_PIN_GEN7_I2C_SDA_PG2, "GEN7_I2C_SDA_PG2"),
264 PINCTRL_PIN(TEGRA_PIN_GEN9_I2C_SCL_PG3, "GEN9_I2C_SCL_PG3"),
265 PINCTRL_PIN(TEGRA_PIN_GEN9_I2C_SDA_PG4, "GEN9_I2C_SDA_PG4"),
266 PINCTRL_PIN(TEGRA_PIN_SDMMC1_CLK_PX0, "SDMMC1_CLK_PX0"),
267 PINCTRL_PIN(TEGRA_PIN_SDMMC1_CMD_PX1, "SDMMC1_CMD_PX1"),
268 PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT0_PX2, "SDMMC1_DAT0_PX2"),
269 PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT1_PX3, "SDMMC1_DAT1_PX3"),
270 PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT2_PX4, "SDMMC1_DAT2_PX4"),
271 PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT3_PX5, "SDMMC1_DAT3_PX5"),
272 PINCTRL_PIN(TEGRA_PIN_SDMMC1_COMP, "SDMMC1_COMP"),
273 PINCTRL_PIN(TEGRA_PIN_CPU_PWR_REQ_PH0, "CPU_PWR_REQ_PH0"),
274 PINCTRL_PIN(TEGRA_PIN_GPU_PWR_REQ_PH1, "GPU_PWR_REQ_PH1"),
275 PINCTRL_PIN(TEGRA_PIN_UART10_TX_PH2, "UART10_TX_PH2"),
276 PINCTRL_PIN(TEGRA_PIN_UART10_RX_PH3, "UART10_RX_PH3"),
277 PINCTRL_PIN(TEGRA_PIN_UART10_RTS_N_PH4, "UART10_RTS_N_PH4"),
278 PINCTRL_PIN(TEGRA_PIN_UART10_CTS_N_PH5, "UART10_CTS_N_PH5"),
279 PINCTRL_PIN(TEGRA_PIN_SPI3_SCK_PH6, "SPI3_SCK_PH6"),
280 PINCTRL_PIN(TEGRA_PIN_SPI3_MISO_PH7, "SPI3_MISO_PH7"),
281 PINCTRL_PIN(TEGRA_PIN_SPI3_MOSI_PJ0, "SPI3_MOSI_PJ0"),
282 PINCTRL_PIN(TEGRA_PIN_SPI3_CS0_PJ1, "SPI3_CS0_PJ1"),
283 PINCTRL_PIN(TEGRA_PIN_SPI3_CS3_PJ2, "SPI3_CS3_PJ2"),
284 PINCTRL_PIN(TEGRA_PIN_UART5_TX_PJ3, "UART5_TX_PJ3"),
285 PINCTRL_PIN(TEGRA_PIN_UART5_RX_PJ4, "UART5_RX_PJ4"),
286 PINCTRL_PIN(TEGRA_PIN_UART5_RTS_N_PJ5, "UART5_RTS_N_PJ5"),
287 PINCTRL_PIN(TEGRA_PIN_UART5_CTS_N_PJ6, "UART5_CTS_N_PJ6"),
288 PINCTRL_PIN(TEGRA_PIN_SPI1_SCK_PJ7, "SPI1_SCK_PJ7"),
289 PINCTRL_PIN(TEGRA_PIN_SPI1_MISO_PK0, "SPI1_MISO_PK0"),
290 PINCTRL_PIN(TEGRA_PIN_SPI1_MOSI_PK1, "SPI1_MOSI_PK1"),
291 PINCTRL_PIN(TEGRA_PIN_SPI1_CS0_PK2, "SPI1_CS0_PK2"),
292 PINCTRL_PIN(TEGRA_PIN_SPI1_CS1_PK3, "SPI1_CS1_PK3"),
293 PINCTRL_PIN(TEGRA_PIN_EXTPERIPH1_CLK_PK4, "EXTPERIPH1_CLK_PK4"),
294 PINCTRL_PIN(TEGRA_PIN_EXTPERIPH2_CLK_PK5, "EXTPERIPH2_CLK_PK5"),
295 PINCTRL_PIN(TEGRA_PIN_GEN12_I2C_SCL_PK6, "GEN12_I2C_SCL_PK6"),
296 PINCTRL_PIN(TEGRA_PIN_GEN12_I2C_SDA_PK7, "GEN12_I2C_SDA_PK7"),
297 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO124_PL0, "SOC_GPIO124_PL0"),
298 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO125_PL1, "SOC_GPIO125_PL1"),
299 PINCTRL_PIN(TEGRA_PIN_FAN_TACH0_PL2, "FAN_TACH0_PL2"),
300 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO127_PL3, "SOC_GPIO127_PL3"),
301 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO128_PL4, "SOC_GPIO128_PL4"),
302 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO129_PL5, "SOC_GPIO129_PL5"),
303 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO130_PL6, "SOC_GPIO130_PL6"),
304 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO131_PL7, "SOC_GPIO131_PL7"),
305 PINCTRL_PIN(TEGRA_PIN_GP_PWM9_PM0, "GP_PWM9_PM0"),
306 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO133_PM1, "SOC_GPIO133_PM1"),
307 PINCTRL_PIN(TEGRA_PIN_UART9_TX_PM2, "UART9_TX_PM2"),
308 PINCTRL_PIN(TEGRA_PIN_UART9_RX_PM3, "UART9_RX_PM3"),
309 PINCTRL_PIN(TEGRA_PIN_UART9_RTS_N_PM4, "UART9_RTS_N_PM4"),
310 PINCTRL_PIN(TEGRA_PIN_UART9_CTS_N_PM5, "UART9_CTS_N_PM5"),
311 PINCTRL_PIN(TEGRA_PIN_QSPI0_SCK_PT0, "QSPI0_SCK_PT0"),
312 PINCTRL_PIN(TEGRA_PIN_QSPI0_CS_N_PT1, "QSPI0_CS_N_PT1"),
313 PINCTRL_PIN(TEGRA_PIN_QSPI0_IO0_PT2, "QSPI0_IO0_PT2"),
314 PINCTRL_PIN(TEGRA_PIN_QSPI0_IO1_PT3, "QSPI0_IO1_PT3"),
315 PINCTRL_PIN(TEGRA_PIN_QSPI0_IO2_PT4, "QSPI0_IO2_PT4"),
316 PINCTRL_PIN(TEGRA_PIN_QSPI0_IO3_PT5, "QSPI0_IO3_PT5"),
317 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO192_PT6, "SOC_GPIO192_PT6"),
318 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO170_PU0, "SOC_GPIO170_PU0"),
319 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO171_PU1, "SOC_GPIO171_PU1"),
320 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO172_PU2, "SOC_GPIO172_PU2"),
321 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO173_PU3, "SOC_GPIO173_PU3"),
322 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO174_PU4, "SOC_GPIO174_PU4"),
323 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO175_PU5, "SOC_GPIO175_PU5"),
324 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO176_PU6, "SOC_GPIO176_PU6"),
325 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO177_PU7, "SOC_GPIO177_PU7"),
326 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO178_PV0, "SOC_GPIO178_PV0"),
327 PINCTRL_PIN(TEGRA_PIN_PWM10_PV1, "PWM10_PV1"),
328 PINCTRL_PIN(TEGRA_PIN_UART4_TX_PV2, "UART4_TX_PV2"),
329 PINCTRL_PIN(TEGRA_PIN_UART4_RX_PV3, "UART4_RX_PV3"),
330 PINCTRL_PIN(TEGRA_PIN_UART4_RTS_N_PV4, "UART4_RTS_N_PV4"),
331 PINCTRL_PIN(TEGRA_PIN_UART4_CTS_N_PV5, "UART4_CTS_N_PV5"),
332 PINCTRL_PIN(TEGRA_PIN_DAP2_CLK_PV6, "DAP2_CLK_PV6"),
333 PINCTRL_PIN(TEGRA_PIN_DAP2_DIN_PV7, "DAP2_DIN_PV7"),
334 PINCTRL_PIN(TEGRA_PIN_DAP2_DOUT_PW0, "DAP2_DOUT_PW0"),
335 PINCTRL_PIN(TEGRA_PIN_DAP2_FS_PW1, "DAP2_FS_PW1"),
336 PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SCL_PW2, "GEN1_I2C_SCL_PW2"),
337 PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SDA_PW3, "GEN1_I2C_SDA_PW3"),
338 PINCTRL_PIN(TEGRA_PIN_GEN0_I2C_SCL_PW4, "GEN0_I2C_SCL_PW4"),
339 PINCTRL_PIN(TEGRA_PIN_GEN0_I2C_SDA_PW5, "GEN0_I2C_SDA_PW5"),
340 PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SCL_PW6, "PWR_I2C_SCL_PW6"),
341 PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SDA_PW7, "PWR_I2C_SDA_PW7"),
342 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO270_PY0, "SOC_GPIO270_PY0"),
343 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO271_PY1, "SOC_GPIO271_PY1"),
344 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO272_PY2, "SOC_GPIO272_PY2"),
345 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO273_PY3, "SOC_GPIO273_PY3"),
346 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO274_PY4, "SOC_GPIO274_PY4"),
347 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO275_PY5, "SOC_GPIO275_PY5"),
348 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO276_PY6, "SOC_GPIO276_PY6"),
349 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO277_PY7, "SOC_GPIO277_PY7"),
350 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO278_PZ0, "SOC_GPIO278_PZ0"),
351 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO279_PZ1, "SOC_GPIO279_PZ1"),
352 PINCTRL_PIN(TEGRA_PIN_XHALT_TRIG_PZ2, "XHALT_TRIG_PZ2"),
353 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO281_PZ3, "SOC_GPIO281_PZ3"),
354 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO282_PZ4, "SOC_GPIO282_PZ4"),
355 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO283_PZ5, "SOC_GPIO283_PZ5"),
356 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO284_PZ6, "SOC_GPIO284_PZ6"),
357 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO285_PZ7, "SOC_GPIO285_PZ7"),
358 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO286_PAL0, "SOC_GPIO286_PAL0"),
359 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO287_PAL1, "SOC_GPIO287_PAL1"),
360 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO288_PAL2, "SOC_GPIO288_PAL2"),
361 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO138_PP0, "SOC_GPIO138_PP0"),
362 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO139_PP1, "SOC_GPIO139_PP1"),
363 PINCTRL_PIN(TEGRA_PIN_DAP6_SCLK_PP2, "DAP6_SCLK_PP2"),
364 PINCTRL_PIN(TEGRA_PIN_DAP6_DOUT_PP3, "DAP6_DOUT_PP3"),
365 PINCTRL_PIN(TEGRA_PIN_DAP6_DIN_PP4, "DAP6_DIN_PP4"),
366 PINCTRL_PIN(TEGRA_PIN_DAP6_FS_PP5, "DAP6_FS_PP5"),
367 PINCTRL_PIN(TEGRA_PIN_DAP4_SCLK_PP6, "DAP4_SCLK_PP6"),
368 PINCTRL_PIN(TEGRA_PIN_DAP4_DOUT_PP7, "DAP4_DOUT_PP7"),
369 PINCTRL_PIN(TEGRA_PIN_DAP4_DIN_PQ0, "DAP4_DIN_PQ0"),
370 PINCTRL_PIN(TEGRA_PIN_DAP4_FS_PQ1, "DAP4_FS_PQ1"),
371 PINCTRL_PIN(TEGRA_PIN_SPI5_SCK_PQ2, "SPI5_SCK_PQ2"),
372 PINCTRL_PIN(TEGRA_PIN_SPI5_MISO_PQ3, "SPI5_MISO_PQ3"),
373 PINCTRL_PIN(TEGRA_PIN_SPI5_MOSI_PQ4, "SPI5_MOSI_PQ4"),
374 PINCTRL_PIN(TEGRA_PIN_SPI5_CS0_PQ5, "SPI5_CS0_PQ5"),
375 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO152_PQ6, "SOC_GPIO152_PQ6"),
376 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO153_PQ7, "SOC_GPIO153_PQ7"),
377 PINCTRL_PIN(TEGRA_PIN_AUD_MCLK_PR0, "AUD_MCLK_PR0"),
378 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO155_PR1, "SOC_GPIO155_PR1"),
379 PINCTRL_PIN(TEGRA_PIN_DAP1_SCLK_PR2, "DAP1_SCLK_PR2"),
380 PINCTRL_PIN(TEGRA_PIN_DAP1_OUT_PR3, "DAP1_OUT_PR3"),
381 PINCTRL_PIN(TEGRA_PIN_DAP1_IN_PR4, "DAP1_IN_PR4"),
382 PINCTRL_PIN(TEGRA_PIN_DAP1_FS_PR5, "DAP1_FS_PR5"),
383 PINCTRL_PIN(TEGRA_PIN_GEN11_I2C_SCL_PR6, "GEN11_I2C_SCL_PR6"),
384 PINCTRL_PIN(TEGRA_PIN_GEN11_I2C_SDA_PR7, "GEN11_I2C_SDA_PR7"),
385 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO350_PS0, "SOC_GPIO350_PS0"),
386 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO351_PS1, "SOC_GPIO351_PS1"),
387
388};
389
390static const struct pinctrl_pin_desc tegra264_aon_pins[] = {
391 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO00_PAA0, "SOC_GPIO00_PAA0"),
392 PINCTRL_PIN(TEGRA_PIN_VCOMP_ALERT_PAA1, "VCOMP_ALERT_PAA1"),
393 PINCTRL_PIN(TEGRA_PIN_AO_RETENTION_N_PAA2, "AO_RETENTION_N_PAA2"),
394 PINCTRL_PIN(TEGRA_PIN_BATT_OC_PAA3, "BATT_OC_PAA3"),
395 PINCTRL_PIN(TEGRA_PIN_BOOTV_CTL_N_PAA4, "BOOTV_CTL_N_PAA4"),
396 PINCTRL_PIN(TEGRA_PIN_POWER_ON_PAA5, "POWER_ON_PAA5"),
397 PINCTRL_PIN(TEGRA_PIN_HDMI_CEC_PAA6, "HDMI_CEC_PAA6"),
398 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO07_PAA7, "SOC_GPIO07_PAA7"),
399 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO08_PBB0, "SOC_GPIO08_PBB0"),
400 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO09_PBB1, "SOC_GPIO09_PBB1"),
401 PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SCL_PCC0, "GEN2_I2C_SCL_PCC0"),
402 PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SDA_PCC1, "GEN2_I2C_SDA_PCC1"),
403 PINCTRL_PIN(TEGRA_PIN_GEN3_I2C_SCL_PCC2, "GEN3_I2C_SCL_PCC2"),
404 PINCTRL_PIN(TEGRA_PIN_GEN3_I2C_SDA_PCC3, "GEN3_I2C_SDA_PCC3"),
405 PINCTRL_PIN(TEGRA_PIN_GP_PWM4_PCC4, "GP_PWM4_PCC4"),
406 PINCTRL_PIN(TEGRA_PIN_UART0_TX_PCC5, "UART0_TX_PCC5"),
407 PINCTRL_PIN(TEGRA_PIN_UART0_RX_PCC6, "UART0_RX_PCC6"),
408 PINCTRL_PIN(TEGRA_PIN_SPI2_SCK_PCC7, "SPI2_SCK_PCC7"),
409 PINCTRL_PIN(TEGRA_PIN_SPI2_MISO_PDD0, "SPI2_MISO_PDD0"),
410 PINCTRL_PIN(TEGRA_PIN_SPI2_MOSI_PDD1, "SPI2_MOSI_PDD1"),
411 PINCTRL_PIN(TEGRA_PIN_SPI2_CS0_N_PDD2, "SPI2_CS0_N_PDD2"),
412 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO21_PDD3, "SOC_GPIO21_PDD3"),
413 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO22_PDD4, "SOC_GPIO22_PDD4"),
414 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO23_PDD5, "SOC_GPIO23_PDD5"),
415 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO24_PDD6, "SOC_GPIO24_PDD6"),
416 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO25_PDD7, "SOC_GPIO25_PDD7"),
417 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO26_PEE0, "SOC_GPIO26_PEE0"),
418 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO27_PEE1, "SOC_GPIO27_PEE1"),
419 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO28_PEE2, "SOC_GPIO28_PEE2"),
420 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO29_PEE3, "SOC_GPIO29_PEE3"),
421};
422
423static const unsigned int soc_gpio250_pf0_pins[] = {
424 TEGRA_PIN_SOC_GPIO250_PF0,
425};
426
427static const unsigned int soc_gpio251_pf1_pins[] = {
428 TEGRA_PIN_SOC_GPIO251_PF1,
429};
430
431static const unsigned int soc_gpio252_pf2_pins[] = {
432 TEGRA_PIN_SOC_GPIO252_PF2,
433};
434
435static const unsigned int dp_aux_ch0_hpd_pf3_pins[] = {
436 TEGRA_PIN_DP_AUX_CH0_HPD_PF3,
437};
438
439static const unsigned int dp_aux_ch1_hpd_pf4_pins[] = {
440 TEGRA_PIN_DP_AUX_CH1_HPD_PF4,
441};
442
443static const unsigned int dp_aux_ch2_hpd_pf5_pins[] = {
444 TEGRA_PIN_DP_AUX_CH2_HPD_PF5,
445};
446
447static const unsigned int dp_aux_ch3_hpd_pf6_pins[] = {
448 TEGRA_PIN_DP_AUX_CH3_HPD_PF6,
449};
450
451static const unsigned int pwm2_pf7_pins[] = {
452 TEGRA_PIN_PWM2_PF7,
453};
454
455static const unsigned int pwm3_pg0_pins[] = {
456 TEGRA_PIN_PWM3_PG0,
457};
458
459static const unsigned int gen7_i2c_scl_pg1_pins[] = {
460 TEGRA_PIN_GEN7_I2C_SCL_PG1,
461};
462
463static const unsigned int gen7_i2c_sda_pg2_pins[] = {
464 TEGRA_PIN_GEN7_I2C_SDA_PG2,
465};
466
467static const unsigned int gen9_i2c_scl_pg3_pins[] = {
468 TEGRA_PIN_GEN9_I2C_SCL_PG3,
469};
470
471static const unsigned int gen9_i2c_sda_pg4_pins[] = {
472 TEGRA_PIN_GEN9_I2C_SDA_PG4,
473};
474
475static const unsigned int pwm1_pa0_pins[] = {
476 TEGRA_PIN_PWM1_PA0,
477};
478
479static const unsigned int pwm6_pa1_pins[] = {
480 TEGRA_PIN_PWM6_PA1,
481};
482
483static const unsigned int pwm7_pa2_pins[] = {
484 TEGRA_PIN_PWM7_PA2,
485};
486
487static const unsigned int pwm8_pa3_pins[] = {
488 TEGRA_PIN_PWM8_PA3,
489};
490
491static const unsigned int ufs0_ref_clk_pa4_pins[] = {
492 TEGRA_PIN_UFS0_REF_CLK_PA4,
493};
494
495static const unsigned int ufs0_rst_n_pa5_pins[] = {
496 TEGRA_PIN_UFS0_RST_N_PA5,
497};
498
499static const unsigned int pex_l1_clkreq_n_pb0_pins[] = {
500 TEGRA_PIN_PEX_L1_CLKREQ_N_PB0,
501};
502
503static const unsigned int pex_l1_rst_n_pb1_pins[] = {
504 TEGRA_PIN_PEX_L1_RST_N_PB1,
505};
506
507static const unsigned int pex_l2_clkreq_n_pb2_pins[] = {
508 TEGRA_PIN_PEX_L2_CLKREQ_N_PB2,
509};
510
511static const unsigned int pex_l2_rst_n_pb3_pins[] = {
512 TEGRA_PIN_PEX_L2_RST_N_PB3,
513};
514
515static const unsigned int pex_l3_clkreq_n_pb4_pins[] = {
516 TEGRA_PIN_PEX_L3_CLKREQ_N_PB4,
517};
518
519static const unsigned int pex_l3_rst_n_pb5_pins[] = {
520 TEGRA_PIN_PEX_L3_RST_N_PB5,
521};
522
523static const unsigned int soc_gpio113_pb6_pins[] = {
524 TEGRA_PIN_SOC_GPIO113_PB6,
525};
526
527static const unsigned int soc_gpio114_pb7_pins[] = {
528 TEGRA_PIN_SOC_GPIO114_PB7,
529};
530
531static const unsigned int sgmii0_sma_mdio_pc0_pins[] = {
532 TEGRA_PIN_SGMII0_SMA_MDIO_PC0,
533};
534
535static const unsigned int sgmii0_sma_mdc_pc1_pins[] = {
536 TEGRA_PIN_SGMII0_SMA_MDC_PC1,
537};
538
539static const unsigned int pex_wake_n_pc2_pins[] = {
540 TEGRA_PIN_PEX_WAKE_N_PC2,
541};
542
543static const unsigned int pex_l4_clkreq_n_pd0_pins[] = {
544 TEGRA_PIN_PEX_L4_CLKREQ_N_PD0,
545};
546
547static const unsigned int pex_l4_rst_n_pd1_pins[] = {
548 TEGRA_PIN_PEX_L4_RST_N_PD1,
549};
550
551static const unsigned int pex_l5_clkreq_n_pd2_pins[] = {
552 TEGRA_PIN_PEX_L5_CLKREQ_N_PD2,
553};
554
555static const unsigned int pex_l5_rst_n_pd3_pins[] = {
556 TEGRA_PIN_PEX_L5_RST_N_PD3,
557};
558
559static const unsigned int eth0_mdio_pd4_pins[] = {
560 TEGRA_PIN_ETH0_MDIO_PD4,
561};
562
563static const unsigned int eth0_mdc_pd5_pins[] = {
564 TEGRA_PIN_ETH0_MDC_PD5,
565};
566
567static const unsigned int eth3_mdio_pd6_pins[] = {
568 TEGRA_PIN_ETH3_MDIO_PD6,
569};
570
571static const unsigned int eth3_mdc_pd7_pins[] = {
572 TEGRA_PIN_ETH3_MDC_PD7,
573};
574
575static const unsigned int eth1_mdio_pe0_pins[] = {
576 TEGRA_PIN_ETH1_MDIO_PE0,
577};
578
579static const unsigned int eth1_mdc_pe1_pins[] = {
580 TEGRA_PIN_ETH1_MDC_PE1,
581};
582
583static const unsigned int eth2_mdio_pe2_pins[] = {
584 TEGRA_PIN_ETH2_MDIO_PE2,
585};
586
587static const unsigned int eth2_mdc_pe3_pins[] = {
588 TEGRA_PIN_ETH2_MDC_PE3,
589};
590
591static const unsigned int sdmmc1_clk_px0_pins[] = {
592 TEGRA_PIN_SDMMC1_CLK_PX0,
593};
594
595static const unsigned int sdmmc1_cmd_px1_pins[] = {
596 TEGRA_PIN_SDMMC1_CMD_PX1,
597};
598
599static const unsigned int sdmmc1_dat0_px2_pins[] = {
600 TEGRA_PIN_SDMMC1_DAT0_PX2,
601};
602
603static const unsigned int sdmmc1_dat1_px3_pins[] = {
604 TEGRA_PIN_SDMMC1_DAT1_PX3,
605};
606
607static const unsigned int sdmmc1_dat2_px4_pins[] = {
608 TEGRA_PIN_SDMMC1_DAT2_PX4,
609};
610
611static const unsigned int sdmmc1_dat3_px5_pins[] = {
612 TEGRA_PIN_SDMMC1_DAT3_PX5,
613};
614
615static const unsigned int sdmmc1_comp_pins[] = {
616 TEGRA_PIN_SDMMC1_COMP,
617};
618
619static const unsigned int cpu_pwr_req_ph0_pins[] = {
620 TEGRA_PIN_CPU_PWR_REQ_PH0,
621};
622
623static const unsigned int gpu_pwr_req_ph1_pins[] = {
624 TEGRA_PIN_GPU_PWR_REQ_PH1,
625};
626
627static const unsigned int uart10_tx_ph2_pins[] = {
628 TEGRA_PIN_UART10_TX_PH2,
629};
630
631static const unsigned int uart10_rx_ph3_pins[] = {
632 TEGRA_PIN_UART10_RX_PH3,
633};
634
635static const unsigned int uart10_rts_n_ph4_pins[] = {
636 TEGRA_PIN_UART10_RTS_N_PH4,
637};
638
639static const unsigned int uart10_cts_n_ph5_pins[] = {
640 TEGRA_PIN_UART10_CTS_N_PH5,
641};
642
643static const unsigned int spi3_sck_ph6_pins[] = {
644 TEGRA_PIN_SPI3_SCK_PH6,
645};
646
647static const unsigned int spi3_miso_ph7_pins[] = {
648 TEGRA_PIN_SPI3_MISO_PH7,
649};
650
651static const unsigned int spi3_mosi_pj0_pins[] = {
652 TEGRA_PIN_SPI3_MOSI_PJ0,
653};
654
655static const unsigned int spi3_cs0_pj1_pins[] = {
656 TEGRA_PIN_SPI3_CS0_PJ1,
657};
658
659static const unsigned int spi3_cs3_pj2_pins[] = {
660 TEGRA_PIN_SPI3_CS3_PJ2,
661};
662
663static const unsigned int uart5_tx_pj3_pins[] = {
664 TEGRA_PIN_UART5_TX_PJ3,
665};
666
667static const unsigned int uart5_rx_pj4_pins[] = {
668 TEGRA_PIN_UART5_RX_PJ4,
669};
670
671static const unsigned int uart5_rts_n_pj5_pins[] = {
672 TEGRA_PIN_UART5_RTS_N_PJ5,
673};
674
675static const unsigned int uart5_cts_n_pj6_pins[] = {
676 TEGRA_PIN_UART5_CTS_N_PJ6,
677};
678
679static const unsigned int spi1_sck_pj7_pins[] = {
680 TEGRA_PIN_SPI1_SCK_PJ7,
681};
682
683static const unsigned int spi1_miso_pk0_pins[] = {
684 TEGRA_PIN_SPI1_MISO_PK0,
685};
686
687static const unsigned int spi1_mosi_pk1_pins[] = {
688 TEGRA_PIN_SPI1_MOSI_PK1,
689};
690
691static const unsigned int spi1_cs0_pk2_pins[] = {
692 TEGRA_PIN_SPI1_CS0_PK2,
693};
694
695static const unsigned int spi1_cs1_pk3_pins[] = {
696 TEGRA_PIN_SPI1_CS1_PK3,
697};
698
699static const unsigned int extperiph1_clk_pk4_pins[] = {
700 TEGRA_PIN_EXTPERIPH1_CLK_PK4,
701};
702
703static const unsigned int extperiph2_clk_pk5_pins[] = {
704 TEGRA_PIN_EXTPERIPH2_CLK_PK5,
705};
706
707static const unsigned int gen12_i2c_scl_pk6_pins[] = {
708 TEGRA_PIN_GEN12_I2C_SCL_PK6,
709};
710
711static const unsigned int gen12_i2c_sda_pk7_pins[] = {
712 TEGRA_PIN_GEN12_I2C_SDA_PK7,
713};
714
715static const unsigned int soc_gpio124_pl0_pins[] = {
716 TEGRA_PIN_SOC_GPIO124_PL0,
717};
718
719static const unsigned int soc_gpio125_pl1_pins[] = {
720 TEGRA_PIN_SOC_GPIO125_PL1,
721};
722
723static const unsigned int fan_tach0_pl2_pins[] = {
724 TEGRA_PIN_FAN_TACH0_PL2,
725};
726
727static const unsigned int soc_gpio127_pl3_pins[] = {
728 TEGRA_PIN_SOC_GPIO127_PL3,
729};
730
731static const unsigned int soc_gpio128_pl4_pins[] = {
732 TEGRA_PIN_SOC_GPIO128_PL4,
733};
734
735static const unsigned int soc_gpio129_pl5_pins[] = {
736 TEGRA_PIN_SOC_GPIO129_PL5,
737};
738
739static const unsigned int soc_gpio130_pl6_pins[] = {
740 TEGRA_PIN_SOC_GPIO130_PL6,
741};
742
743static const unsigned int soc_gpio131_pl7_pins[] = {
744 TEGRA_PIN_SOC_GPIO131_PL7,
745};
746
747static const unsigned int gp_pwm9_pm0_pins[] = {
748 TEGRA_PIN_GP_PWM9_PM0,
749};
750
751static const unsigned int soc_gpio133_pm1_pins[] = {
752 TEGRA_PIN_SOC_GPIO133_PM1,
753};
754
755static const unsigned int uart9_tx_pm2_pins[] = {
756 TEGRA_PIN_UART9_TX_PM2,
757};
758
759static const unsigned int uart9_rx_pm3_pins[] = {
760 TEGRA_PIN_UART9_RX_PM3,
761};
762
763static const unsigned int uart9_rts_n_pm4_pins[] = {
764 TEGRA_PIN_UART9_RTS_N_PM4,
765};
766
767static const unsigned int uart9_cts_n_pm5_pins[] = {
768 TEGRA_PIN_UART9_CTS_N_PM5,
769};
770
771static const unsigned int soc_gpio170_pu0_pins[] = {
772 TEGRA_PIN_SOC_GPIO170_PU0,
773};
774
775static const unsigned int soc_gpio171_pu1_pins[] = {
776 TEGRA_PIN_SOC_GPIO171_PU1,
777};
778
779static const unsigned int soc_gpio172_pu2_pins[] = {
780 TEGRA_PIN_SOC_GPIO172_PU2,
781};
782
783static const unsigned int soc_gpio173_pu3_pins[] = {
784 TEGRA_PIN_SOC_GPIO173_PU3,
785};
786
787static const unsigned int soc_gpio174_pu4_pins[] = {
788 TEGRA_PIN_SOC_GPIO174_PU4,
789};

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drivers/pinctrl/ultrarisc/Kconfig+20−0

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drivers/pinctrl/ultrarisc/Makefile+4−0

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drivers/pinctrl/ultrarisc/pinctrl-dp1000.c+168−0

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drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c+517−0

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drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.h+63−0

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drivers/pinctrl/vt8500/Kconfig+7−6

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include/dt-bindings/pinctrl/mediatek,mt6392-pinfunc.h+39−0

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include/linux/mux/consumer.h+7−1

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include/linux/pinctrl/pinmux.h+5−0

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