Pull pin control updates from Linus Walleij: "Core changes: - Add new generic callbacks to populate per-pin pin controllers creating groups and functions from the device tree building out pinctrl_generic_to_map() and move the Spacemit driver over to use this - Generic board-level pin control driver using the mux framework New pin controller drivers: - Amlogic (meson) A9 SoC - Aspeed AST2700 SoC0 and SoC1 - nVidia Tegra264 and Tegra238 - Qualcomm Nord TLMM, Shikra TLMM, SM6350 LPASS LPI, and IPQ9650 TLMM - Renesas RZ/G3L SoC - UltraRISC DP1000 Improvements: - Handle pull up/pull down properly in the Renesas RZG2L driver - Fix up nVidia Tegra 234 DT bindings - Fix up pin definitions in the Qualcomm Eliza driver - Qualcomm PM8010 GPIO support in the PM8010 - Qualcomm SM6115 EGPIO support in the SM6115 - Switch Qualcomm LPASS LPI drivers to use runtime PM for power management - Clean up the Qualcomm Kconfig business a bit to include the necessary drivers for each subarch - Fix output glitch in the Amlogic (meson) A4 pin controller - Move the Airoha driver from the Mediatek directory to its own directory. It is too different from other Mediatek hardware - A slew of fixes to the Airoha AN7581 and AN7583 drivers" * tag 'pinctrl-v7.2-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (151 commits) pinctrl: Export pinctrl_get_group_selector() pinctrl: Match DT helper types pinctrl: qcom: Register functions before enabling pinctrl pinctrl: meson: amlogic-a4: use nolock get range pinctrl: ultrarisc: Add UltraRISC DP1000 pinctrl driver dt-bindings: pinctrl: Add UltraRISC DP1000 pinctrl controller pinctrl: qcom: Remove unused macro definitions pinctrl: tegra: PINCTRL_TEGRA264 should depend on ARCH_TEGRA pinctrl: tegra: PINCTRL_TEGRA238 should depend on ARCH_TEGRA pinctrl: tegra238: add missing AON pin groups dt-bindings: pinctrl: tegra238: add missing AON pin groups pinctrl: airoha: an7583: remove undefined groups from pcm_spi pin function pinctrl: airoha: an7583: fix phy1_led1 pin function pinctrl: airoha: an7583: add missed gpio22 pin group pinctrl: airoha: an7583: fix gpio21 pin group pinctrl: airoha: fix pwm pin function for an7581 and an7583 pinctrl: airoha: an7583: fix incorrect led mapping in phy4_led1 pin function pinctrl: airoha: an7581: fix incorrect led mapping in phy4_led1 pin function pinctrl: airoha: an7583: fix misprint in gpio19 pinconf pinctrl: airoha: an7581: fix misprint in gpio19 pinconf ...
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| @@ -0,0 +1,39 @@ | ||
| 1 | +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ | |
| 2 | +#ifndef __DTS_MT6392_PINFUNC_H | |
| 3 | +#define __DTS_MT6392_PINFUNC_H | |
| 4 | + | |
| 5 | +#include <dt-bindings/pinctrl/mt65xx.h> | |
| 6 | + | |
| 7 | +#define MT6392_PIN_0_INT__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) | |
| 8 | +#define MT6392_PIN_0_INT__FUNC_INT (MTK_PIN_NO(0) | 1) | |
| 9 | +#define MT6392_PIN_0_INT__FUNC_TEST_CK2 (MTK_PIN_NO(0) | 5) | |
| 10 | +#define MT6392_PIN_0_INT__FUNC_TEST_IN1 (MTK_PIN_NO(0) | 6) | |
| 11 | +#define MT6392_PIN_0_INT__FUNC_TEST_OUT1 (MTK_PIN_NO(0) | 7) | |
| 12 | + | |
| 13 | +#define MT6392_PIN_1_SRCLKEN__FUNC_GPIO1 (MTK_PIN_NO(1) | 0) | |
| 14 | +#define MT6392_PIN_1_SRCLKEN__FUNC_SRCLKEN (MTK_PIN_NO(1) | 1) | |
| 15 | +#define MT6392_PIN_1_SRCLKEN__FUNC_TEST_CK0 (MTK_PIN_NO(1) | 5) | |
| 16 | +#define MT6392_PIN_1_SRCLKEN__FUNC_TEST_IN2 (MTK_PIN_NO(1) | 6) | |
| 17 | +#define MT6392_PIN_1_SRCLKEN__FUNC_TEST_OUT2 (MTK_PIN_NO(1) | 7) | |
| 18 | + | |
| 19 | +#define MT6392_PIN_2_RTC_32K1V8__FUNC_GPIO2 (MTK_PIN_NO(2) | 0) | |
| 20 | +#define MT6392_PIN_2_RTC_32K1V8__FUNC_RTC_32K1V8 (MTK_PIN_NO(2) | 1) | |
| 21 | +#define MT6392_PIN_2_RTC_32K1V8__FUNC_TEST_CK1 (MTK_PIN_NO(2) | 5) | |
| 22 | +#define MT6392_PIN_2_RTC_32K1V8__FUNC_TEST_IN3 (MTK_PIN_NO(2) | 6) | |
| 23 | +#define MT6392_PIN_2_RTC_32K1V8__FUNC_TEST_OUT3 (MTK_PIN_NO(2) | 7) | |
| 24 | + | |
| 25 | +#define MT6392_PIN_3_SPI_CLK__FUNC_GPIO3 (MTK_PIN_NO(3) | 0) | |
| 26 | +#define MT6392_PIN_3_SPI_CLK__FUNC_SPI_CLK (MTK_PIN_NO(3) | 1) | |
| 27 | + | |
| 28 | +#define MT6392_PIN_4_SPI_CSN__FUNC_GPIO4 (MTK_PIN_NO(4) | 0) | |
| 29 | +#define MT6392_PIN_4_SPI_CSN__FUNC_SPI_CSN (MTK_PIN_NO(4) | 1) | |
| 30 | + | |
| 31 | +#define MT6392_PIN_5_SPI_MOSI__FUNC_GPIO5 (MTK_PIN_NO(5) | 0) | |
| 32 | +#define MT6392_PIN_5_SPI_MOSI__FUNC_SPI_MOSI (MTK_PIN_NO(5) | 1) | |
| 33 | + | |
| 34 | +#define MT6392_PIN_6_SPI_MISO__FUNC_GPIO6 (MTK_PIN_NO(6) | 0) | |
| 35 | +#define MT6392_PIN_6_SPI_MISO__FUNC_SPI_MISO (MTK_PIN_NO(6) | 1) | |
| 36 | +#define MT6392_PIN_6_SPI_MISO__FUNC_TEST_IN4 (MTK_PIN_NO(6) | 6) | |
| 37 | +#define MT6392_PIN_6_SPI_MISO__FUNC_TEST_OUT4 (MTK_PIN_NO(6) | 7) | |
| 38 | + | |
| 39 | +#endif /* __DTS_MT6392_PINFUNC_H */ | |
| @@ -60,7 +60,10 @@ struct mux_control *mux_control_get_optional(struct device *dev, const char *mux · 59 unmodified lines | ||
| 60 | 60 | void mux_control_put(struct mux_control *mux); |
| 61 | 61 | |
| 62 | 62 | struct mux_control *devm_mux_control_get(struct device *dev, const char *mux_name); |
| 63 | −struct mux_state *devm_mux_state_get(struct device *dev, const char *mux_name); | |
| 63 | + | |
| 64 | +struct mux_state * | |
| 65 | +devm_mux_state_get_from_np(struct device *dev, const char *mux_name, struct device_node *np); | |
| 66 | + | |
| 64 | 67 | struct mux_state *devm_mux_state_get_optional(struct device *dev, const char *mux_name); |
| 65 | 68 | struct mux_state *devm_mux_state_get_selected(struct device *dev, const char *mux_name); |
| 66 | 69 | struct mux_state *devm_mux_state_get_optional_selected(struct device *dev, const char *mux_name); |
| @@ -161,4 +164,7 @@ static inline struct mux_state *devm_mux_state_get_optional_selected(struct devi · 94 unmodified lines | ||
| 161 | 164 | |
| 162 | 165 | #endif /* CONFIG_MULTIPLEXER */ |
| 163 | 166 | |
| 167 | +#define devm_mux_state_get(dev, mux_name) \ | |
| 168 | + devm_mux_state_get_from_np(dev, mux_name, NULL) | |
| 169 | + | |
| 164 | 170 | #endif /* _LINUX_MUX_CONSUMER_H */ |
| @@ -51,6 +51,8 @@ struct pinctrl_gpio_range; · 50 unmodified lines | ||
| 51 | 51 | * are handled by the pinmux subsystem. The @func_selector selects a |
| 52 | 52 | * certain function whereas @group_selector selects a certain set of pins |
| 53 | 53 | * to be used. On simple controllers the latter argument may be ignored |
| 54 | + * @release_mux: Release software resources acquired by @set_mux. This callback | |
| 55 | + * must not change hardware state to avoid glitches when switching mux. | |
| 54 | 56 | * @gpio_request_enable: requests and enables GPIO on a certain pin. |
| 55 | 57 | * Implement this only if you can mux every pin individually as GPIO. The |
| 56 | 58 | * affected GPIO range is passed along with an offset(pin number) into that |
| @@ -80,6 +82,9 @@ struct pinmux_ops { · 23 unmodified lines | ||
| 80 | 82 | unsigned int selector); |
| 81 | 83 | int (*set_mux) (struct pinctrl_dev *pctldev, unsigned int func_selector, |
| 82 | 84 | unsigned int group_selector); |
| 85 | + void (*release_mux) (struct pinctrl_dev *pctldev, | |
| 86 | + unsigned int func_selector, | |
| 87 | + unsigned int group_selector); | |
| 83 | 88 | int (*gpio_request_enable) (struct pinctrl_dev *pctldev, |
| 84 | 89 | struct pinctrl_gpio_range *range, |
| 85 | 90 | unsigned int offset); |