Pull ARM fixes from Russell King: "A few ARM fixes: - Robin Murphy noticed that the non-secure privileged entry was relying on undefined behaviour, which needed to be fixed. - Vladimir Murzin noticed that prov-v7 fails to build for MMUless configurations because a required header file wasn't included. - A bunch of fixes for StrongARM regressions found while testing 4.8-rc on such platforms" * 'fixes' of git://git.armlinux.org.uk/~rmk/linux-arm: ARM: sa1100: clear reset status prior to reboot ARM: 8600/1: Enforce some NS-SVC initialisation ARM: 8599/1: mm: pull asm/memory.h explicitly ARM: sa1100: register clocks early ARM: sa1100: fix 3.6864MHz clock
Unified · Split
| @@ -142,6 +142,19 @@ ARM_BE8(orr r7, r7, #(1 << 25)) @ HSCTLR.EE · 141 unmodified lines | ||
| 142 | 142 | and r7, #0x1f @ Preserve HPMN |
| 143 | 143 | mcr p15, 4, r7, c1, c1, 1 @ HDCR |
| 144 | 144 | |
| 145 | + @ Make sure NS-SVC is initialised appropriately | |
| 146 | + mrc p15, 0, r7, c1, c0, 0 @ SCTLR | |
| 147 | + orr r7, #(1 << 5) @ CP15 barriers enabled | |
| 148 | + bic r7, #(3 << 7) @ Clear SED/ITD for v8 (RES0 for v7) | |
| 149 | + bic r7, #(3 << 19) @ WXN and UWXN disabled | |
| 150 | + mcr p15, 0, r7, c1, c0, 0 @ SCTLR | |
| 151 | + | |
| 152 | + mrc p15, 0, r7, c0, c0, 0 @ MIDR | |
| 153 | + mcr p15, 4, r7, c0, c0, 0 @ VPIDR | |
| 154 | + | |
| 155 | + mrc p15, 0, r7, c0, c0, 5 @ MPIDR | |
| 156 | + mcr p15, 4, r7, c0, c0, 5 @ VMPIDR | |
| 157 | + | |
| 145 | 158 | #if !defined(ZIMAGE) && defined(CONFIG_ARM_ARCH_TIMER) |
| 146 | 159 | @ make CNTP_* and CNTPCT accessible from PL1 |
| 147 | 160 | mrc p15, 0, r7, c0, c1, 1 @ ID_PFR1 |
| @@ -125,6 +125,8 @@ static unsigned long clk_36864_get_rate(struct clk *clk) · 124 unmodified lines | ||
| 125 | 125 | } |
| 126 | 126 | |
| 127 | 127 | static struct clkops clk_36864_ops = { |
| 128 | + .enable = clk_cpu_enable, | |
| 129 | + .disable = clk_cpu_disable, | |
| 128 | 130 | .get_rate = clk_36864_get_rate, |
| 129 | 131 | }; |
| 130 | 132 | |
| @@ -140,9 +142,8 @@ static struct clk_lookup sa11xx_clkregs[] = { · 9 unmodified lines | ||
| 140 | 142 | CLKDEV_INIT(NULL, "OSTIMER0", &clk_36864), |
| 141 | 143 | }; |
| 142 | 144 | |
| 143 | −static int __init sa11xx_clk_init(void) | |
| 145 | +int __init sa11xx_clk_init(void) | |
| 144 | 146 | { |
| 145 | 147 | clkdev_add_table(sa11xx_clkregs, ARRAY_SIZE(sa11xx_clkregs)); |
| 146 | 148 | return 0; |
| 147 | 149 | } |
| 148 | −core_initcall(sa11xx_clk_init); | |
| @@ -34,6 +34,7 @@ · 33 unmodified lines | ||
| 34 | 34 | |
| 35 | 35 | #include <mach/hardware.h> |
| 36 | 36 | #include <mach/irqs.h> |
| 37 | +#include <mach/reset.h> | |
| 37 | 38 | |
| 38 | 39 | #include "generic.h" |
| 39 | 40 | #include <clocksource/pxa.h> |
| @@ -95,6 +96,8 @@ static void sa1100_power_off(void) · 55 unmodified lines | ||
| 95 | 96 | |
| 96 | 97 | void sa11x0_restart(enum reboot_mode mode, const char *cmd) |
| 97 | 98 | { |
| 99 | + clear_reset_status(RESET_STATUS_ALL); | |
| 100 | + | |
| 98 | 101 | if (mode == REBOOT_SOFT) { |
| 99 | 102 | /* Jump into ROM at address 0 */ |
| 100 | 103 | soft_restart(0); |
| @@ -388,6 +391,7 @@ void __init sa1100_init_irq(void) · 287 unmodified lines | ||
| 388 | 391 | sa11x0_init_irq_nodt(IRQ_GPIO0_SC, irq_resource.start); |
| 389 | 392 | |
| 390 | 393 | sa1100_init_gpio(); |
| 394 | + sa11xx_clk_init(); | |
| 391 | 395 | } |
| 392 | 396 | |
| 393 | 397 | /* |
| @@ -44,3 +44,5 @@ int sa11x0_pm_init(void); · 43 unmodified lines | ||
| 44 | 44 | #else |
| 45 | 45 | static inline int sa11x0_pm_init(void) { return 0; } |
| 46 | 46 | #endif |
| 47 | + | |
| 48 | +int sa11xx_clk_init(void); | |
| @@ -16,6 +16,7 @@ · 15 unmodified lines | ||
| 16 | 16 | #include <asm/hwcap.h> |
| 17 | 17 | #include <asm/pgtable-hwdef.h> |
| 18 | 18 | #include <asm/pgtable.h> |
| 19 | +#include <asm/memory.h> | |
| 19 | 20 | |
| 20 | 21 | #include "proc-macros.S" |
| 21 | 22 | |