The table describes how each bit in the u64 value is used. Explicitly state which values a field can take if we have defines for them. Also add a note when a field isn't always populated. Forcing people to update the table when changing the bit layout should make it more obvious when there's a mistake, I hope. If we get to the point where the bit layout gets more complicated, it might be worth it to split the table into multiple tables (e.g. one for GFX8, one for GFX9+, and so on).
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| @@ -1114,6 +1114,25 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier) · 1113 unmodified lines | |||
| 1114 | * | 1114 | * |
| 1115 | * For multi-plane formats the above surfaces get merged into one plane for | 1115 | * For multi-plane formats the above surfaces get merged into one plane for |
| 1116 | * each format plane, based on the required alignment only. | 1116 | * each format plane, based on the required alignment only. |
| 1117 | * | ||
| 1118 | * Bits Parameter Notes | ||
| 1119 | * ----- ------------------------ --------------------------------------------- | ||
| 1120 | * | ||
| 1121 | * 7:0 TILE_VERSION Values are AMD_FMT_MOD_TILE_VER_* | ||
| 1122 | * 12:8 TILE Values are AMD_FMT_MOD_TILE_<version>_* | ||
| 1123 | * 13 DCC | ||
| 1124 | * 14 DCC_RETILE | ||
| 1125 | * 15 DCC_PIPE_ALIGN | ||
| 1126 | * 16 DCC_INDEPENDENT_64B | ||
| 1127 | * 17 DCC_INDEPENDENT_128B | ||
| 1128 | * 19:18 DCC_MAX_COMPRESSED_BLOCK Values are AMD_FMT_MOD_DCC_BLOCK_* | ||
| 1129 | * 20 DCC_CONSTANT_ENCODE | ||
| 1130 | * 23:21 PIPE_XOR_BITS Only for some chips | ||
| 1131 | * 26:24 BANK_XOR_BITS Only for some chips | ||
| 1132 | * 29:27 PACKERS Only for some chips | ||
| 1133 | * 32:30 RB Only for some chips | ||
| 1134 | * 35:33 PIPE Only for some chips | ||
| 1135 | * 55:36 - Reserved for future use, must be zero | ||
| 1117 | */ | 1136 | */ |
| 1118 | #define AMD_FMT_MOD fourcc_mod_code(AMD, 0) | 1137 | #define AMD_FMT_MOD fourcc_mod_code(AMD, 0) |
| 1119 | 1138 | ||