lael-labs/linux

.mailmap+4−0

 Felix Moeller <felix@derklecks.de>
 Filipe Lautert <filipe@icewall.org>
 Franck Bui-Huu <vagabon.xyz@gmail.com>
+Frank Rowand <frowand.list@gmail.com> <frowand@mvista.com>
+Frank Rowand <frowand.list@gmail.com> <frank.rowand@am.sony.com>
+Frank Rowand <frowand.list@gmail.com> <frank.rowand@sonymobile.com>
 Frank Zago <fzago@systemfabricworks.com>
 Greg Kroah-Hartman <greg@echidna.(none)>
 Greg Kroah-Hartman <gregkh@suse.de>
 Kenneth W Chen <kenneth.w.chen@intel.com>
 Konstantin Khlebnikov <koct9i@gmail.com> <k.khlebnikov@samsung.com>
 Koushik <raghavendra.koushik@neterion.com>
+Krzysztof Kozlowski <krzk@kernel.org> <k.kozlowski.k@gmail.com>
 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
 Leonid I Ananiev <leonid.i.ananiev@intel.com>
 Linas Vepstas <linas@austin.ibm.com>

Documentation/devicetree/bindings/arc/archs-pct.txt+1−1

@@ -2,7 +2,7 @@ · 1 unmodified line
2		2
3	The ARC HS can be configured with a pipeline performance monitor for counting	3	The ARC HS can be configured with a pipeline performance monitor for counting
4	CPU and cache events like cache misses and hits. Like conventional PCT there	4	CPU and cache events like cache misses and hits. Like conventional PCT there
5	are 100+ hardware conditions dynamically mapped to upto 32 counters.	5	are 100+ hardware conditions dynamically mapped to up to 32 counters.
6	It also supports overflow interrupts.	6	It also supports overflow interrupts.
7		7
8	Required properties:	8	Required properties:

Documentation/devicetree/bindings/arc/pct.txt+1−1

@@ -2,7 +2,7 @@ · 1 unmodified line
2		2
3	The ARC700 can be configured with a pipeline performance monitor for counting	3	The ARC700 can be configured with a pipeline performance monitor for counting
4	CPU and cache events like cache misses and hits. Like conventional PCT there	4	CPU and cache events like cache misses and hits. Like conventional PCT there
5	are 100+ hardware conditions dynamically mapped to upto 32 counters	5	are 100+ hardware conditions dynamically mapped to up to 32 counters
6		6
7	Note that:	7	Note that:
8	* The ARC 700 PCT does not support interrupts; although HW events may be	8	* The ARC 700 PCT does not support interrupts; although HW events may be

Documentation/devicetree/bindings/arm/cpus.txt+0−1

@@ -192,7 +192,6 @@ nodes to be present and contain the properties described below. · 191 unmodified lines
192	can be one of:	192	can be one of:
193	"allwinner,sun6i-a31"	193	"allwinner,sun6i-a31"
194	"allwinner,sun8i-a23"	194	"allwinner,sun8i-a23"
195	"arm,psci"
196	"arm,realview-smp"	195	"arm,realview-smp"
197	"brcm,bcm-nsp-smp"	196	"brcm,bcm-nsp-smp"
198	"brcm,brahma-b15"	197	"brcm,brahma-b15"

Documentation/devicetree/bindings/i2c/i2c-rk3x.txt+2−2

@@ -6,8 +6,8 @@ RK3xxx SoCs. · 5 unmodified lines
6	Required properties :	6	Required properties :
7		7
8	- reg : Offset and length of the register set for the device	8	- reg : Offset and length of the register set for the device
9	- compatible : should be "rockchip,rk3066-i2c", "rockchip,rk3188-i2c" or	9	- compatible : should be "rockchip,rk3066-i2c", "rockchip,rk3188-i2c",
10	"rockchip,rk3288-i2c".	10	"rockchip,rk3228-i2c" or "rockchip,rk3288-i2c".
11	- interrupts : interrupt number	11	- interrupts : interrupt number
12	- clocks : parent clock	12	- clocks : parent clock
13		13

Documentation/sysctl/vm.txt+10−9

@@ -581,15 +581,16 @@ Specify "[Nn]ode" for node order · 580 unmodified lines
581	"Zone Order" orders the zonelists by zone type, then by node within each	581	"Zone Order" orders the zonelists by zone type, then by node within each
582	zone. Specify "[Zz]one" for zone order.	582	zone. Specify "[Zz]one" for zone order.
583		583
584	Specify "[Dd]efault" to request automatic configuration. Autoconfiguration	584	Specify "[Dd]efault" to request automatic configuration.
585	will select "node" order in following case.	585
586	(1) if the DMA zone does not exist or	586	On 32-bit, the Normal zone needs to be preserved for allocations accessible
587	(2) if the DMA zone comprises greater than 50% of the available memory or	587	by the kernel, so "zone" order will be selected.
588	(3) if any node's DMA zone comprises greater than 70% of its local memory and	588
589	the amount of local memory is big enough.	589	On 64-bit, devices that require DMA32/DMA are relatively rare, so "node"
590		590	order will be selected.
591	Otherwise, "zone" order will be selected. Default order is recommended unless	591
592	this is causing problems for your system/application.	592	Default order is recommended unless this is causing problems for your
		593	system/application.
593		594
594	==============================================================	595	==============================================================
595		596

MAINTAINERS+12−3

 ISCSI EXTENSIONS FOR RDMA (ISER) INITIATOR
 M:	Or Gerlitz <ogerlitz@mellanox.com>
-M:	Sagi Grimberg <sagig@mellanox.com>
+M:	Sagi Grimberg <sagi@grimberg.me>
 M:	Roi Dayan <roid@mellanox.com>
 L:	linux-rdma@vger.kernel.org
 S:	Supported
 F:	drivers/infiniband/ulp/iser/
 ISCSI EXTENSIONS FOR RDMA (ISER) TARGET
-M:	Sagi Grimberg <sagig@mellanox.com>
+M:	Sagi Grimberg <sagi@grimberg.me>
 T:	git git://git.kernel.org/pub/scm/linux/kernel/git/nab/target-pending.git master
 L:	linux-rdma@vger.kernel.org
 L:	target-devel@vger.kernel.org
 F:	mm/kmemleak-test.c
 KPROBES
-M:	Ananth N Mavinakayanahalli <ananth@in.ibm.com>
+M:	Ananth N Mavinakayanahalli <ananth@linux.vnet.ibm.com>
 M:	Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
 M:	"David S. Miller" <davem@davemloft.net>
 M:	Masami Hiramatsu <mhiramat@kernel.org>
 F:	drivers/clk/ti/
 F:	include/linux/clk/ti.h
+TI ETHERNET SWITCH DRIVER (CPSW)
+M:	Mugunthan V N <mugunthanvnm@ti.com>
+R:	Grygorii Strashko <grygorii.strashko@ti.com>
+L:	linux-omap@vger.kernel.org
+L:	netdev@vger.kernel.org
+S:	Maintained
+F:	drivers/net/ethernet/ti/cpsw*
+F:	drivers/net/ethernet/ti/davinci*
 TI FLASH MEDIA INTERFACE DRIVER
 M:	Alex Dubov <oakad@yahoo.com>
 S:	Maintained

Makefile+2−2

@@ -1,8 +1,8 @@
1	VERSION = 4	1	VERSION = 4
2	PATCHLEVEL = 6	2	PATCHLEVEL = 6
3	SUBLEVEL = 0	3	SUBLEVEL = 0
4	EXTRAVERSION = -rc5	4	EXTRAVERSION = -rc6
5	NAME = Blurry Fish Butt	5	NAME = Charred Weasel
6		6
7	# DOCUMENTATION	7	# DOCUMENTATION
8	# To see a list of typical targets execute "make help"	8	# To see a list of typical targets execute "make help"

arch/arc/Kconfig+2−0

 	select NO_BOOTMEM
 	select OF
 	select OF_EARLY_FLATTREE
+	select OF_RESERVED_MEM
 	select PERF_USE_VMALLOC
 	select HAVE_DEBUG_STACKOVERFLOW
+	select HAVE_GENERIC_DMA_COHERENT
 config MIGHT_HAVE_PCI
 	bool

arch/arc/include/asm/irqflags-arcv2.h+35−1

@@ -18,6 +18,12 @@ · 17 unmodified lines
18	#define STATUS_AD_MASK (1<<STATUS_AD_BIT)	18	#define STATUS_AD_MASK (1<<STATUS_AD_BIT)
19	#define STATUS_IE_MASK (1<<STATUS_IE_BIT)	19	#define STATUS_IE_MASK (1<<STATUS_IE_BIT)
20		20
		21	/* status32 Bits as encoded/expected by CLRI/SETI */
		22	#define CLRI_STATUS_IE_BIT 4
		23
		24	#define CLRI_STATUS_E_MASK 0xF
		25	#define CLRI_STATUS_IE_MASK (1 << CLRI_STATUS_IE_BIT)
		26
21	#define AUX_USER_SP 0x00D	27	#define AUX_USER_SP 0x00D
22	#define AUX_IRQ_CTRL 0x00E	28	#define AUX_IRQ_CTRL 0x00E
23	#define AUX_IRQ_ACT 0x043 /* Active Intr across all levels */	29	#define AUX_IRQ_ACT 0x043 /* Active Intr across all levels */
@@ -100,6 +106,13 @@ static inline long arch_local_save_flags(void) · 76 unmodified lines
100	:	106	:
101	: "memory");	107	: "memory");
102		108
		109	/* To be compatible with irq_save()/irq_restore()
		110	* encode the irq bits as expected by CLRI/SETI
		111	* (this was needed to make CONFIG_TRACE_IRQFLAGS work)
		112	*/
		113	temp = (1 << 5) \|
		114	((!!(temp & STATUS_IE_MASK)) << CLRI_STATUS_IE_BIT) \|
		115	(temp & CLRI_STATUS_E_MASK);
103	return temp;	116	return temp;
104	}	117	}
105		118
@@ -108,7 +121,7 @@ static inline long arch_local_save_flags(void) · 2 unmodified lines
108	*/	121	*/
109	static inline int arch_irqs_disabled_flags(unsigned long flags)	122	static inline int arch_irqs_disabled_flags(unsigned long flags)
110	{	123	{
111	return !(flags & (STATUS_IE_MASK));	124	return !(flags & CLRI_STATUS_IE_MASK);
112	}	125	}
113		126
114	static inline int arch_irqs_disabled(void)	127	static inline int arch_irqs_disabled(void)
@@ -128,11 +141,32 @@ static inline void arc_softirq_clear(int irq) · 13 unmodified lines
128		141
129	#else	142	#else
130		143
		144	#ifdef CONFIG_TRACE_IRQFLAGS
		145
		146	.macro TRACE_ASM_IRQ_DISABLE
		147	bl trace_hardirqs_off
		148	.endm
		149
		150	.macro TRACE_ASM_IRQ_ENABLE
		151	bl trace_hardirqs_on
		152	.endm
		153
		154	#else
		155
		156	.macro TRACE_ASM_IRQ_DISABLE
		157	.endm
		158
		159	.macro TRACE_ASM_IRQ_ENABLE
		160	.endm
		161
		162	#endif
131	.macro IRQ_DISABLE scratch	163	.macro IRQ_DISABLE scratch
132	clri	164	clri
		165	TRACE_ASM_IRQ_DISABLE
133	.endm	166	.endm
134		167
135	.macro IRQ_ENABLE scratch	168	.macro IRQ_ENABLE scratch
		169	TRACE_ASM_IRQ_ENABLE
136	seti	170	seti
137	.endm	171	.endm
138		172

arch/arc/kernel/entry-arcv2.S+9−1

 	clri		; To make status32.IE agree with CPU internal state
-	lr  r0, [ICAUSE]
+#ifdef CONFIG_TRACE_IRQFLAGS
+	TRACE_ASM_IRQ_DISABLE
+#endif
+	lr  r0, [ICAUSE]
 	mov   blink, ret_from_exception
 	b.d  arch_do_IRQ
 .Lrestore_regs:
+	# Interrpts are actually disabled from this point on, but will get
+	# reenabled after we return from interrupt/exception.
+	# But irq tracer needs to be told now...
+	TRACE_ASM_IRQ_ENABLE
 	ld	r0, [sp, PT_status32]	; U/K mode at time of entry
 	lr	r10, [AUX_IRQ_ACT]

arch/arc/kernel/entry-compact.S+3−0

@@ -341,6 +341,9 @@ END(call_do_page_fault) · 340 unmodified lines
341		341
342	.Lrestore_regs:	342	.Lrestore_regs:
343		343
		344	# Interrpts are actually disabled from this point on, but will get
		345	# reenabled after we return from interrupt/exception.
		346	# But irq tracer needs to be told now...
344	TRACE_ASM_IRQ_ENABLE	347	TRACE_ASM_IRQ_ENABLE
345		348
346	lr r10, [status32]	349	lr r10, [status32]

arch/arc/mm/init.c+4−0

 #ifdef CONFIG_BLK_DEV_INITRD
 #include <linux/initrd.h>
 #endif
+#include <linux/of_fdt.h>
 #include <linux/swap.h>
 #include <linux/module.h>
 #include <linux/highmem.h>
 		memblock_reserve(__pa(initrd_start), initrd_end - initrd_start);
 #endif
+	early_init_fdt_reserve_self();
+	early_init_fdt_scan_reserved_mem();
 	memblock_dump_all();
 	/*----------------- node/zones setup --------------------------*/

arch/arm/boot/dts/am33xx.dtsi+1−1

@@ -860,7 +860,7 @@ · 859 unmodified lines
860	ti,no-idle-on-init;	860	ti,no-idle-on-init;
861	reg = <0x50000000 0x2000>;	861	reg = <0x50000000 0x2000>;
862	interrupts = <100>;	862	interrupts = <100>;
863	dmas = <&edma 52>;	863	dmas = <&edma 52 0>;
864	dma-names = "rxtx";	864	dma-names = "rxtx";
865	gpmc,num-cs = <7>;	865	gpmc,num-cs = <7>;
866	gpmc,num-waitpins = <2>;	866	gpmc,num-waitpins = <2>;

arch/arm/boot/dts/am4372.dtsi+1−1

@@ -884,7 +884,7 @@ · 883 unmodified lines
884	gpmc: gpmc@50000000 {	884	gpmc: gpmc@50000000 {
885	compatible = "ti,am3352-gpmc";	885	compatible = "ti,am3352-gpmc";
886	ti,hwmods = "gpmc";	886	ti,hwmods = "gpmc";
887	dmas = <&edma 52>;	887	dmas = <&edma 52 0>;
888	dma-names = "rxtx";	888	dma-names = "rxtx";
889	clocks = <&l3s_gclk>;	889	clocks = <&l3s_gclk>;
890	clock-names = "fck";	890	clock-names = "fck";

arch/arm/boot/dts/am57xx-beagle-x15.dts+0−17

 		#cooling-cells = <2>;
 	};
-	extcon_usb1: extcon_usb1 {
-		compatible = "linux,extcon-usb-gpio";
-		id-gpio = <&gpio7 25 GPIO_ACTIVE_HIGH>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&extcon_usb1_pins>;
-	};
 	hdmi0: connector {
 		compatible = "hdmi-connector";
 		label = "hdmi";
 		>;
 	};
-	extcon_usb1_pins: extcon_usb1_pins {
-		pinctrl-single,pins = <
-			DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MUX_MODE14) /* uart1_rtsn.gpio7_25 */
-		>;
-	};
 	tpd12s015_pins: pinmux_tpd12s015_pins {
 		pinctrl-single,pins = <
 			DRA7XX_CORE_IOPAD(0x37b0, PIN_OUTPUT | MUX_MODE14)		/* gpio7_10 CT_CP_HPD */
 	pinctrl-0 = <&usb1_pins>;
 };
-&omap_dwc3_1 {
-	extcon = <&extcon_usb1>;
-};
 &omap_dwc3_2 {
 	extcon = <&extcon_usb2>;
 };

arch/arm/boot/dts/dm814x-clocks.dtsi+212−31

@@ -4,6 +4,157 @@ · 3 unmodified lines
4	* published by the Free Software Foundation.	4	* published by the Free Software Foundation.
5	*/	5	*/
6		6
		7	&pllss {
		8	/*
		9	* See TRM "2.6.10 Connected outputso DPLLS" and
		10	* "2.6.11 Connected Outputs of DPLLJ". Only clkout is
		11	* connected except for hdmi and usb.
		12	*/
		13	adpll_mpu_ck: adpll@40 {
		14	#clock-cells = <1>;
		15	compatible = "ti,dm814-adpll-s-clock";
		16	reg = <0x40 0x40>;
		17	clocks = <&devosc_ck &devosc_ck &devosc_ck>;
		18	clock-names = "clkinp", "clkinpulow", "clkinphif";
		19	clock-output-names = "481c5040.adpll.dcoclkldo",
		20	"481c5040.adpll.clkout",
		21	"481c5040.adpll.clkoutx2",
		22	"481c5040.adpll.clkouthif";
		23	};
		24
		25	adpll_dsp_ck: adpll@80 {
		26	#clock-cells = <1>;
		27	compatible = "ti,dm814-adpll-lj-clock";
		28	reg = <0x80 0x30>;
		29	clocks = <&devosc_ck &devosc_ck>;
		30	clock-names = "clkinp", "clkinpulow";
		31	clock-output-names = "481c5080.adpll.dcoclkldo",
		32	"481c5080.adpll.clkout",
		33	"481c5080.adpll.clkoutldo";
		34	};
		35
		36	adpll_sgx_ck: adpll@b0 {
		37	#clock-cells = <1>;
		38	compatible = "ti,dm814-adpll-lj-clock";
		39	reg = <0xb0 0x30>;
		40	clocks = <&devosc_ck &devosc_ck>;
		41	clock-names = "clkinp", "clkinpulow";
		42	clock-output-names = "481c50b0.adpll.dcoclkldo",
		43	"481c50b0.adpll.clkout",
		44	"481c50b0.adpll.clkoutldo";
		45	};
		46
		47	adpll_hdvic_ck: adpll@e0 {
		48	#clock-cells = <1>;
		49	compatible = "ti,dm814-adpll-lj-clock";
		50	reg = <0xe0 0x30>;
		51	clocks = <&devosc_ck &devosc_ck>;
		52	clock-names = "clkinp", "clkinpulow";
		53	clock-output-names = "481c50e0.adpll.dcoclkldo",
		54	"481c50e0.adpll.clkout",
		55	"481c50e0.adpll.clkoutldo";
		56	};
		57
		58	adpll_l3_ck: adpll@110 {
		59	#clock-cells = <1>;
		60	compatible = "ti,dm814-adpll-lj-clock";
		61	reg = <0x110 0x30>;
		62	clocks = <&devosc_ck &devosc_ck>;
		63	clock-names = "clkinp", "clkinpulow";
		64	clock-output-names = "481c5110.adpll.dcoclkldo",
		65	"481c5110.adpll.clkout",
		66	"481c5110.adpll.clkoutldo";
		67	};
		68
		69	adpll_isp_ck: adpll@140 {
		70	#clock-cells = <1>;
		71	compatible = "ti,dm814-adpll-lj-clock";
		72	reg = <0x140 0x30>;
		73	clocks = <&devosc_ck &devosc_ck>;
		74	clock-names = "clkinp", "clkinpulow";
		75	clock-output-names = "481c5140.adpll.dcoclkldo",
		76	"481c5140.adpll.clkout",
		77	"481c5140.adpll.clkoutldo";
		78	};
		79
		80	adpll_dss_ck: adpll@170 {
		81	#clock-cells = <1>;
		82	compatible = "ti,dm814-adpll-lj-clock";
		83	reg = <0x170 0x30>;
		84	clocks = <&devosc_ck &devosc_ck>;
		85	clock-names = "clkinp", "clkinpulow";
		86	clock-output-names = "481c5170.adpll.dcoclkldo",
		87	"481c5170.adpll.clkout",
		88	"481c5170.adpll.clkoutldo";
		89	};
		90
		91	adpll_video0_ck: adpll@1a0 {
		92	#clock-cells = <1>;
		93	compatible = "ti,dm814-adpll-lj-clock";
		94	reg = <0x1a0 0x30>;
		95	clocks = <&devosc_ck &devosc_ck>;
		96	clock-names = "clkinp", "clkinpulow";
		97	clock-output-names = "481c51a0.adpll.dcoclkldo",
		98	"481c51a0.adpll.clkout",
		99	"481c51a0.adpll.clkoutldo";
		100	};
		101
		102	adpll_video1_ck: adpll@1d0 {
		103	#clock-cells = <1>;
		104	compatible = "ti,dm814-adpll-lj-clock";
		105	reg = <0x1d0 0x30>;
		106	clocks = <&devosc_ck &devosc_ck>;
		107	clock-names = "clkinp", "clkinpulow";
		108	clock-output-names = "481c51d0.adpll.dcoclkldo",
		109	"481c51d0.adpll.clkout",
		110	"481c51d0.adpll.clkoutldo";
		111	};
		112
		113	adpll_hdmi_ck: adpll@200 {
		114	#clock-cells = <1>;
		115	compatible = "ti,dm814-adpll-lj-clock";
		116	reg = <0x200 0x30>;
		117	clocks = <&devosc_ck &devosc_ck>;
		118	clock-names = "clkinp", "clkinpulow";
		119	clock-output-names = "481c5200.adpll.dcoclkldo",
		120	"481c5200.adpll.clkout",
		121	"481c5200.adpll.clkoutldo";
		122	};
		123
		124	adpll_audio_ck: adpll@230 {
		125	#clock-cells = <1>;
		126	compatible = "ti,dm814-adpll-lj-clock";
		127	reg = <0x230 0x30>;
		128	clocks = <&devosc_ck &devosc_ck>;
		129	clock-names = "clkinp", "clkinpulow";
		130	clock-output-names = "481c5230.adpll.dcoclkldo",
		131	"481c5230.adpll.clkout",
		132	"481c5230.adpll.clkoutldo";
		133	};
		134
		135	adpll_usb_ck: adpll@260 {
		136	#clock-cells = <1>;
		137	compatible = "ti,dm814-adpll-lj-clock";
		138	reg = <0x260 0x30>;
		139	clocks = <&devosc_ck &devosc_ck>;
		140	clock-names = "clkinp", "clkinpulow";
		141	clock-output-names = "481c5260.adpll.dcoclkldo",
		142	"481c5260.adpll.clkout",
		143	"481c5260.adpll.clkoutldo";
		144	};
		145
		146	adpll_ddr_ck: adpll@290 {
		147	#clock-cells = <1>;
		148	compatible = "ti,dm814-adpll-lj-clock";
		149	reg = <0x290 0x30>;
		150	clocks = <&devosc_ck &devosc_ck>;
		151	clock-names = "clkinp", "clkinpulow";
		152	clock-output-names = "481c5290.adpll.dcoclkldo",
		153	"481c5290.adpll.clkout",
		154	"481c5290.adpll.clkoutldo";
		155	};
		156	};
		157
7	&pllss_clocks {	158	&pllss_clocks {
8	timer1_fck: timer1_fck {	159	timer1_fck: timer1_fck {
9	#clock-cells = <0>;	160	#clock-cells = <0>;
@@ -23,6 +174,24 @@ · 13 unmodified lines
23	reg = <0x2e0>;	174	reg = <0x2e0>;
24	};	175	};
25		176
		177	/* CPTS_RFT_CLK in RMII_REFCLK_SRC, usually sourced from auiod */
		178	cpsw_cpts_rft_clk: cpsw_cpts_rft_clk {
		179	#clock-cells = <0>;
		180	compatible = "ti,mux-clock";
		181	clocks = <&adpll_video0_ck 1
		182	&adpll_video1_ck 1
		183	&adpll_audio_ck 1>;
		184	ti,bit-shift = <1>;
		185	reg = <0x2e8>;
		186	};
		187
		188	/* REVISIT: Set up with a proper mux using RMII_REFCLK_SRC */
		189	cpsw_125mhz_gclk: cpsw_125mhz_gclk {
		190	#clock-cells = <0>;
		191	compatible = "fixed-clock";
		192	clock-frequency = <125000000>;
		193	};
		194
26	sysclk18_ck: sysclk18_ck {	195	sysclk18_ck: sysclk18_ck {
27	#clock-cells = <0>;	196	#clock-cells = <0>;
28	compatible = "ti,mux-clock";	197	compatible = "ti,mux-clock";
@@ -79,37 +248,6 @@ · 50 unmodified lines
79	compatible = "fixed-clock";	248	compatible = "fixed-clock";
80	clock-frequency = <1000000000>;	249	clock-frequency = <1000000000>;
81	};	250	};
82
83	sysclk4_ck: sysclk4_ck {
84	#clock-cells = <0>;
85	compatible = "fixed-clock";
86	clock-frequency = <222000000>;
87	};
88
89	sysclk6_ck: sysclk6_ck {
90	#clock-cells = <0>;
91	compatible = "fixed-clock";
92	clock-frequency = <100000000>;
93	};
94
95	sysclk10_ck: sysclk10_ck {
96	#clock-cells = <0>;
97	compatible = "fixed-clock";
98	clock-frequency = <48000000>;
99	};
100
101	cpsw_125mhz_gclk: cpsw_125mhz_gclk {
102	#clock-cells = <0>;
103	compatible = "fixed-clock";
104	clock-frequency = <125000000>;
105	};
106
107	cpsw_cpts_rft_clk: cpsw_cpts_rft_clk {
108	#clock-cells = <0>;
109	compatible = "fixed-clock";
110	clock-frequency = <250000000>;
111	};
112
113	};	251	};
114		252
115	&prcm_clocks {	253	&prcm_clocks {
@@ -138,6 +276,49 @@ · 22 unmodified lines
138	clock-div = <78125>;	276	clock-div = <78125>;
139	};	277	};
140		278
		279	/* L4_HS 220 MHz*/
		280	sysclk4_ck: sysclk4_ck {
		281	#clock-cells = <0>;
		282	compatible = "ti,fixed-factor-clock";
		283	clocks = <&adpll_l3_ck 1>;
		284	ti,clock-mult = <1>;
		285	ti,clock-div = <1>;
		286	};
		287
		288	/* L4_FWCFG */
		289	sysclk5_ck: sysclk5_ck {
		290	#clock-cells = <0>;
		291	compatible = "ti,fixed-factor-clock";
		292	clocks = <&adpll_l3_ck 1>;
		293	ti,clock-mult = <1>;
		294	ti,clock-div = <2>;
		295	};
		296
		297	/* L4_LS 110 MHz */
		298	sysclk6_ck: sysclk6_ck {
		299	#clock-cells = <0>;
		300	compatible = "ti,fixed-factor-clock";
		301	clocks = <&adpll_l3_ck 1>;
		302	ti,clock-mult = <1>;
		303	ti,clock-div = <2>;
		304	};
		305
		306	sysclk8_ck: sysclk8_ck {
		307	#clock-cells = <0>;
		308	compatible = "ti,fixed-factor-clock";
		309	clocks = <&adpll_usb_ck 1>;
		310	ti,clock-mult = <1>;
		311	ti,clock-div = <1>;
		312	};
		313
		314	sysclk10_ck: sysclk10_ck {
		315	compatible = "ti,divider-clock";
		316	reg = <0x324>;
		317	ti,max-div = <7>;
		318	#clock-cells = <0>;
		319	clocks = <&adpll_usb_ck 1>;
		320	};
		321
141	aud_clkin0_ck: aud_clkin0_ck {	322	aud_clkin0_ck: aud_clkin0_ck {
142	#clock-cells = <0>;	323	#clock-cells = <0>;
143	compatible = "fixed-clock";	324	compatible = "fixed-clock";

arch/arm/boot/dts/dra62x-clocks.dtsi+26−0

@@ -6,6 +6,32 @@ · 5 unmodified lines
6		6
7	#include "dm814x-clocks.dtsi"	7	#include "dm814x-clocks.dtsi"
8		8
		9	/* Compared to dm814x, dra62x does not have hdic, l3 or dss PLLs */
		10	&adpll_hdvic_ck {
		11	status = "disabled";
		12	};
		13
		14	&adpll_l3_ck {
		15	status = "disabled";
		16	};
		17
		18	&adpll_dss_ck {
		19	status = "disabled";
		20	};
		21
		22	/* Compared to dm814x, dra62x has interconnect clocks on isp PLL */
		23	&sysclk4_ck {
		24	clocks = <&adpll_isp_ck 1>;
		25	};
		26
		27	&sysclk5_ck {
		28	clocks = <&adpll_isp_ck 1>;
		29	};
		30
		31	&sysclk6_ck {
		32	clocks = <&adpll_isp_ck 1>;
		33	};
		34
9	/*	35	/*
10	* Compared to dm814x, dra62x has different shifts and more mux options.	36	* Compared to dm814x, dra62x has different shifts and more mux options.
11	* Please add the extra options for ysclk_14 and 16 if really needed.	37	* Please add the extra options for ysclk_14 and 16 if really needed.

arch/arm/boot/dts/dra7xx-clocks.dtsi+17−1

 		clock-frequency = <32768>;
 	};
-	sys_32k_ck: sys_32k_ck {
+	sys_clk32_crystal_ck: sys_clk32_crystal_ck {
 		#clock-cells = <0>;
 		compatible = "fixed-clock";
 		clock-frequency = <32768>;
 	};
+	sys_clk32_pseudo_ck: sys_clk32_pseudo_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&sys_clkin1>;
+		clock-mult = <1>;
+		clock-div = <610>;
+	};
 	virt_12000000_ck: virt_12000000_ck {
 		#clock-cells = <0>;
 		compatible = "fixed-clock";
 		ti,bit-shift = <22>;
 		reg = <0x0558>;
 	};
+	sys_32k_ck: sys_32k_ck {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&sys_clk32_crystal_ck>, <&sys_clk32_pseudo_ck>, <&sys_clk32_pseudo_ck>, <&sys_clk32_pseudo_ck>;
+		ti,bit-shift = <8>;
+		reg = <0x6c4>;
+	};
 };

arch/arm/boot/dts/qcom-msm8974.dtsi+1−13

 /dts-v1/;
-#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/clock/qcom,gcc-msm8974.h>
 #include "skeleton.dtsi"
 			clock-names = "core", "iface";
 			#address-cells = <1>;
 			#size-cells = <0>;
-			dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
-			dma-names = "tx", "rx";
 		};
 		spmi_bus: spmi@fc4cf000 {
 			interrupt-controller;
 			#interrupt-cells = <4>;
 		};
-		blsp2_dma: dma-controller@f9944000 {
-			compatible = "qcom,bam-v1.4.0";
-			reg = <0xf9944000 0x19000>;
-			interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&gcc GCC_BLSP2_AHB_CLK>;
-			clock-names = "bam_clk";
-			#dma-cells = <1>;
-			qcom,ee = <0>;
-		};
 	};
 	smd {

arch/arm/boot/dts/r8a7791-koelsch.dts+1−0

@@ -661,6 +661,7 @@ · 660 unmodified lines
661	};	661	};
662		662
663	&pcie_bus_clk {	663	&pcie_bus_clk {
		664	clock-frequency = <100000000>;
664	status = "okay";	665	status = "okay";
665	};	666	};
666		667

arch/arm/boot/dts/r8a7791-porter.dts+1−13

 };
 &pfc {
-	pinctrl-0 = <&scif_clk_pins>;
-	pinctrl-names = "default";
 	scif0_pins: serial0 {
 		renesas,groups = "scif0_data_d";
 		renesas,function = "scif0";
 	};
-	scif_clk_pins: scif_clk {
-		renesas,groups = "scif_clk";
-		renesas,function = "scif_clk";
-	};
 	ether_pins: ether {
 		renesas,groups = "eth_link", "eth_mdio", "eth_rmii";
 		renesas,function = "eth";
 	status = "okay";
 };
-&scif_clk {
-	clock-frequency = <14745600>;
-	status = "okay";
-};
 &ether {
 	pinctrl-0 = <&ether_pins &phy1_pins>;
 	pinctrl-names = "default";
 };
 &pcie_bus_clk {
+	clock-frequency = <100000000>;
 	status = "okay";
 };

arch/arm/boot/dts/r8a7791.dtsi+1−4

 		pcie_bus_clk: pcie_bus_clk {
 			compatible = "fixed-clock";
 			#clock-cells = <0>;
-			clock-frequency = <100000000>;
+			clock-frequency = <0>;
 			clock-output-names = "pcie_bus";
-			status = "disabled";
 		};
 		/* External SCIF clock */
 			#clock-cells = <0>;
 			/* This value must be overridden by the board. */
 			clock-frequency = <0>;
-			status = "disabled";
 		};
 		/* External USB clock - can be overridden by the board */
 			/* This value must be overridden by the board. */
 			clock-frequency = <0>;
 			clock-output-names = "can_clk";
-			status = "disabled";
 		};
 		/* Special CPG clocks */

arch/arm/mach-imx/devices/platform-sdhci-esdhc-imx.c+3−2

@@ -71,6 +71,7 @@ struct platform_device *__init imx_add_sdhci_esdhc_imx( · 70 unmodified lines
71	if (!pdata)	71	if (!pdata)
72	pdata = &default_esdhc_pdata;	72	pdata = &default_esdhc_pdata;
73		73
74	return imx_add_platform_device(data->devid, data->id, res,	74	return imx_add_platform_device_dmamask(data->devid, data->id, res,
75	ARRAY_SIZE(res), pdata, sizeof(*pdata));	75	ARRAY_SIZE(res), pdata, sizeof(*pdata),
		76	DMA_BIT_MASK(32));
76	}	77	}

arch/arm/mach-omap2/clockdomains7xx_data.c+1−1

@@ -461,7 +461,7 @@ static struct clockdomain ipu_7xx_clkdm = { · 460 unmodified lines
461	.cm_inst = DRA7XX_CM_CORE_AON_IPU_INST,	461	.cm_inst = DRA7XX_CM_CORE_AON_IPU_INST,
462	.clkdm_offs = DRA7XX_CM_CORE_AON_IPU_IPU_CDOFFS,	462	.clkdm_offs = DRA7XX_CM_CORE_AON_IPU_IPU_CDOFFS,
463	.dep_bit = DRA7XX_IPU_STATDEP_SHIFT,	463	.dep_bit = DRA7XX_IPU_STATDEP_SHIFT,
464	.flags = CLKDM_CAN_HWSUP_SWSUP,	464	.flags = CLKDM_CAN_SWSUP,
465	};	465	};
466		466
467	static struct clockdomain mpu1_7xx_clkdm = {	467	static struct clockdomain mpu1_7xx_clkdm = {

arch/arm/mach-omap2/io.c+2−1

 #ifdef CONFIG_SOC_DRA7XX
 void __init dra7xx_init_early(void)
 {
-	omap2_set_globals_tap(-1, OMAP2_L4_IO_ADDRESS(DRA7XX_TAP_BASE));
+	omap2_set_globals_tap(DRA7XX_CLASS,
+			      OMAP2_L4_IO_ADDRESS(DRA7XX_TAP_BASE));
 	omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
 	omap2_control_base_init();
 	omap4_pm_init_early();

arch/arm/mach-omap2/omap-wakeupgen.c+7−0

  */
 static void irq_save_context(void)
 {
+	/* DRA7 has no SAR to save */
+	if (soc_is_dra7xx())
+		return;
 	if (!sar_base)
 		sar_base = omap4_get_sar_ram_base();
 {
 	u32 val;
 	u32 offset = SAR_BACKUP_STATUS_OFFSET;
+	/* DRA7 has no SAR to save */
+	if (soc_is_dra7xx())
+		return;
 	if (soc_is_omap54xx())
 		offset = OMAP5_SAR_BACKUP_STATUS_OFFSET;

arch/arm/mach-omap2/pm34xx.c+13−10

 	int per_next_state = PWRDM_POWER_ON;
 	int core_next_state = PWRDM_POWER_ON;
 	int per_going_off;
-	int core_prev_state;
 	u32 sdrc_pwr = 0;
 	mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
 		sdrc_write_reg(sdrc_pwr, SDRC_POWER);
 	/* CORE */
-	if (core_next_state < PWRDM_POWER_ON) {
+	if (core_next_state < PWRDM_POWER_ON &&
-		core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm);
+	    pwrdm_read_prev_pwrst(core_pwrdm) == PWRDM_POWER_OFF) {
-		if (core_prev_state == PWRDM_POWER_OFF) {
+		omap3_core_restore_context();
-			omap3_core_restore_context();
+		omap3_cm_restore_context();
-			omap3_cm_restore_context();
+		omap3_sram_restore_context();
-			omap3_sram_restore_context();
+		omap2_sms_restore_context();
-			omap2_sms_restore_context();
+	} else {
-		}
+		/*
+		 * In off-mode resume path above, omap3_core_restore_context
+		 * also handles the INTC autoidle restore done here so limit
+		 * this to non-off mode resume paths so we don't do it twice.
+		 */
+		omap3_intc_resume_idle();
 	}
-	omap3_intc_resume_idle();
 	pwrdm_post_transition(NULL);

arch/arm/mach-shmobile/timer.c+11−17

 void __init shmobile_init_delay(void)
 {
 	struct device_node *np, *cpus;
-	bool is_a7_a8_a9 = false;
+	unsigned int div = 0;
-	bool is_a15 = false;
 	bool has_arch_timer = false;
 	u32 max_freq = 0;
 		if (!of_property_read_u32(np, "clock-frequency", &freq))
 			max_freq = max(max_freq, freq);
-		if (of_device_is_compatible(np, "arm,cortex-a8") ||
+		if (of_device_is_compatible(np, "arm,cortex-a8")) {
-		    of_device_is_compatible(np, "arm,cortex-a9")) {
+			div = 2;
-			is_a7_a8_a9 = true;
+		} else if (of_device_is_compatible(np, "arm,cortex-a9")) {
-		} else if (of_device_is_compatible(np, "arm,cortex-a7")) {
+			div = 1;
-			is_a7_a8_a9 = true;
+		} else if (of_device_is_compatible(np, "arm,cortex-a7") ||
-			has_arch_timer = true;
+			 of_device_is_compatible(np, "arm,cortex-a15")) {
-		} else if (of_device_is_compatible(np, "arm,cortex-a15")) {
+			div = 1;
-			is_a15 = true;
 			has_arch_timer = true;
 		}
 	}
 	of_node_put(cpus);
-	if (!max_freq)
+	if (!max_freq || !div)
 		return;
-	if (!has_arch_timer || !IS_ENABLED(CONFIG_ARM_ARCH_TIMER)) {
+	if (!has_arch_timer || !IS_ENABLED(CONFIG_ARM_ARCH_TIMER))
-		if (is_a7_a8_a9)
+		shmobile_setup_delay_hz(max_freq, 1, div);
-			shmobile_setup_delay_hz(max_freq, 1, 3);
-		else if (is_a15)
-			shmobile_setup_delay_hz(max_freq, 2, 4);
-	}
 }

arch/arm64/boot/dts/socionext/uniphier-ph1-ld20-ref.dts+0−1

@@ -70,7 +70,6 @@ · 69 unmodified lines
70	i2c3 = &i2c3;	70	i2c3 = &i2c3;
71	i2c4 = &i2c4;	71	i2c4 = &i2c4;
72	i2c5 = &i2c5;	72	i2c5 = &i2c5;
73	i2c6 = &i2c6;
74	};	73	};
75	};	74	};
76		75

arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi+5−15

 		i2c2: i2c@58782000 {
 			compatible = "socionext,uniphier-fi2c";
-			status = "disabled";
 			reg = <0x58782000 0x80>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			interrupts = <0 43 4>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&pinctrl_i2c2>;
 			clocks = <&i2c_clk>;
-			clock-frequency = <100000>;
+			clock-frequency = <400000>;
 		};
 		i2c3: i2c@58783000 {
 		i2c4: i2c@58784000 {
 			compatible = "socionext,uniphier-fi2c";
+			status = "disabled";
 			reg = <0x58784000 0x80>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			interrupts = <0 45 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_i2c4>;
 			clocks = <&i2c_clk>;
-			clock-frequency = <400000>;
+			clock-frequency = <100000>;
 		};
 		i2c5: i2c@58785000 {
 			clock-frequency = <400000>;
 		};
-		i2c6: i2c@58786000 {
-			compatible = "socionext,uniphier-fi2c";
-			reg = <0x58786000 0x80>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			interrupts = <0 26 4>;
-			clocks = <&i2c_clk>;
-			clock-frequency = <400000>;
-		};
 		system_bus: system-bus@58c00000 {
 			compatible = "socionext,uniphier-system-bus";
 			status = "disabled";

arch/nios2/lib/memset.c+1−1

@@ -68,7 +68,7 @@ void memset(void s, int c, size_t count) · 67 unmodified lines
68	"=r" (charcnt), /* %1 Output */	68	"=r" (charcnt), /* %1 Output */
69	"=r" (dwordcnt), /* %2 Output */	69	"=r" (dwordcnt), /* %2 Output */
70	"=r" (fill8reg), /* %3 Output */	70	"=r" (fill8reg), /* %3 Output */
71	"=r" (wrkrega) /* %4 Output */	71	"=&r" (wrkrega) /* %4 Output only */
72	: "r" (c), /* %5 Input */	72	: "r" (c), /* %5 Input */
73	"0" (s), /* %0 Input/Output */	73	"0" (s), /* %0 Input/Output */
74	"1" (count) /* %1 Input/Output */	74	"1" (count) /* %1 Input/Output */

arch/powerpc/include/asm/systbl.h+2−0

@@ -384,3 +384,5 @@ SYSCALL(ni_syscall) · 383 unmodified lines
384	SYSCALL(ni_syscall)	384	SYSCALL(ni_syscall)
385	SYSCALL(mlock2)	385	SYSCALL(mlock2)
386	SYSCALL(copy_file_range)	386	SYSCALL(copy_file_range)
		387	COMPAT_SYS_SPU(preadv2)
		388	COMPAT_SYS_SPU(pwritev2)

arch/powerpc/include/asm/unistd.h+1−1

@@ -12,7 +12,7 @@ · 11 unmodified lines
12	#include <uapi/asm/unistd.h>	12	#include <uapi/asm/unistd.h>
13		13
14		14
15	#define NR_syscalls 380	15	#define NR_syscalls 382
16		16
17	#define __NR__exit __NR_exit	17	#define __NR__exit __NR_exit
18		18

arch/powerpc/include/uapi/asm/unistd.h+2−0

@@ -390,5 +390,7 @@ · 389 unmodified lines
390	#define __NR_membarrier 365	390	#define __NR_membarrier 365
391	#define __NR_mlock2 378	391	#define __NR_mlock2 378
392	#define __NR_copy_file_range 379	392	#define __NR_copy_file_range 379
		393	#define __NR_preadv2 380
		394	#define __NR_pwritev2 381
393		395
394	#endif /* _UAPI_ASM_POWERPC_UNISTD_H_ */	396	#endif /* _UAPI_ASM_POWERPC_UNISTD_H_ */

arch/s390/include/asm/mmu.h+1−1

@@ -11,7 +11,7 @@ typedef struct { · 10 unmodified lines
11	spinlock_t list_lock;	11	spinlock_t list_lock;
12	struct list_head pgtable_list;	12	struct list_head pgtable_list;
13	struct list_head gmap_list;	13	struct list_head gmap_list;
14	unsigned long asce_bits;	14	unsigned long asce;
15	unsigned long asce_limit;	15	unsigned long asce_limit;
16	unsigned long vdso_base;	16	unsigned long vdso_base;
17	/* The mmu context allocates 4K page tables. */	17	/* The mmu context allocates 4K page tables. */

arch/s390/include/asm/mmu_context.h+22−6

 	mm->context.has_pgste = 0;
 	mm->context.use_skey = 0;
 #endif
-	if (mm->context.asce_limit == 0) {
+	switch (mm->context.asce_limit) {
+	case 1UL << 42:
+		/*
+		 * forked 3-level task, fall through to set new asce with new
+		 * mm->pgd
+		 */
+	case 0:
 		/* context created by exec, set asce limit to 4TB */
-		mm->context.asce_bits = _ASCE_TABLE_LENGTH |
-			_ASCE_USER_BITS | _ASCE_TYPE_REGION3;
 		mm->context.asce_limit = STACK_TOP_MAX;
-	} else if (mm->context.asce_limit == (1UL << 31)) {
+		mm->context.asce = __pa(mm->pgd) | _ASCE_TABLE_LENGTH |
+				   _ASCE_USER_BITS | _ASCE_TYPE_REGION3;
+		break;
+	case 1UL << 53:
+		/* forked 4-level task, set new asce with new mm->pgd */
+		mm->context.asce = __pa(mm->pgd) | _ASCE_TABLE_LENGTH |
+				   _ASCE_USER_BITS | _ASCE_TYPE_REGION2;
+		break;
+	case 1UL << 31:
+		/* forked 2-level compat task, set new asce with new mm->pgd */
+		mm->context.asce = __pa(mm->pgd) | _ASCE_TABLE_LENGTH |
+				   _ASCE_USER_BITS | _ASCE_TYPE_SEGMENT;
+		/* pgd_alloc() did not increase mm->nr_pmds */
 		mm_inc_nr_pmds(mm);
 	}
 	crst_table_init((unsigned long *) mm->pgd, pgd_entry_type(mm));
 static inline void set_user_asce(struct mm_struct *mm)
 {
-	S390_lowcore.user_asce = mm->context.asce_bits | __pa(mm->pgd);
+	S390_lowcore.user_asce = mm->context.asce;
 	if (current->thread.mm_segment.ar4)
 		__ctl_load(S390_lowcore.user_asce, 7, 7);
 	set_cpu_flag(CIF_ASCE);
 {
 	int cpu = smp_processor_id();
-	S390_lowcore.user_asce = next->context.asce_bits | __pa(next->pgd);
+	S390_lowcore.user_asce = next->context.asce;
 	if (prev == next)
 		return;
 	if (MACHINE_HAS_TLB_LC)

arch/s390/include/asm/pgalloc.h+2−2

@@ -52,8 +52,8 @@ static inline unsigned long pgd_entry_type(struct mm_struct *mm) · 51 unmodified lines
52	return _REGION2_ENTRY_EMPTY;	52	return _REGION2_ENTRY_EMPTY;
53	}	53	}
54		54
55	int crst_table_upgrade(struct mm_struct *, unsigned long limit);	55	int crst_table_upgrade(struct mm_struct *);
56	void crst_table_downgrade(struct mm_struct *, unsigned long limit);	56	void crst_table_downgrade(struct mm_struct *);
57		57
58	static inline pud_t pud_alloc_one(struct mm_struct mm, unsigned long address)	58	static inline pud_t pud_alloc_one(struct mm_struct mm, unsigned long address)
59	{	59	{

arch/s390/include/asm/processor.h+1−1

@@ -175,7 +175,7 @@ extern __vector128 init_task_fpu_regs[__NUM_VXRS]; · 174 unmodified lines
175	regs->psw.mask = PSW_USER_BITS \| PSW_MASK_BA; \	175	regs->psw.mask = PSW_USER_BITS \| PSW_MASK_BA; \
176	regs->psw.addr = new_psw; \	176	regs->psw.addr = new_psw; \
177	regs->gprs[15] = new_stackp; \	177	regs->gprs[15] = new_stackp; \
178	crst_table_downgrade(current->mm, 1UL << 31); \	178	crst_table_downgrade(current->mm); \
179	execve_tail(); \	179	execve_tail(); \
180	} while (0)	180	} while (0)
181		181

arch/s390/include/asm/tlbflush.h+3−6

 static inline void __tlb_flush_kernel(void)
 {
 	if (MACHINE_HAS_IDTE)
-		__tlb_flush_idte((unsigned long) init_mm.pgd |
+		__tlb_flush_idte(init_mm.context.asce);
-				 init_mm.context.asce_bits);
 	else
 		__tlb_flush_global();
 }
 static inline void __tlb_flush_kernel(void)
 {
 	if (MACHINE_HAS_TLB_LC)
-		__tlb_flush_idte_local((unsigned long) init_mm.pgd |
+		__tlb_flush_idte_local(init_mm.context.asce);
-				       init_mm.context.asce_bits);
 	else
 		__tlb_flush_local();
 }
 	 * only ran on the local cpu.
 	 */
 	if (MACHINE_HAS_IDTE && list_empty(&mm->context.gmap_list))
-		__tlb_flush_asce(mm, (unsigned long) mm->pgd |
+		__tlb_flush_asce(mm, mm->context.asce);
-				 mm->context.asce_bits);
 	else
 		__tlb_flush_full(mm);
 }

arch/s390/mm/init.c+2−1

 		asce_bits = _ASCE_TYPE_REGION3 | _ASCE_TABLE_LENGTH;
 		pgd_type = _REGION3_ENTRY_EMPTY;
 	}
-	S390_lowcore.kernel_asce = (__pa(init_mm.pgd) & PAGE_MASK) | asce_bits;
+	init_mm.context.asce = (__pa(init_mm.pgd) & PAGE_MASK) | asce_bits;
+	S390_lowcore.kernel_asce = init_mm.context.asce;
 	clear_table((unsigned long *) init_mm.pgd, pgd_type,
 		    sizeof(unsigned long)*2048);
 	vmem_map_init();

arch/s390/mm/mmap.c+3−3

@@ -174,7 +174,7 @@ int s390_mmap_check(unsigned long addr, unsigned long len, unsigned long flags) · 173 unmodified lines
174	if (!(flags & MAP_FIXED))	174	if (!(flags & MAP_FIXED))
175	addr = 0;	175	addr = 0;
176	if ((addr + len) >= TASK_SIZE)	176	if ((addr + len) >= TASK_SIZE)
177	return crst_table_upgrade(current->mm, TASK_MAX_SIZE);	177	return crst_table_upgrade(current->mm);
178	return 0;	178	return 0;
179	}	179	}
180		180
@@ -191,7 +191,7 @@ s390_get_unmapped_area(struct file *filp, unsigned long addr, · 10 unmodified lines
191	return area;	191	return area;
192	if (area == -ENOMEM && !is_compat_task() && TASK_SIZE < TASK_MAX_SIZE) {	192	if (area == -ENOMEM && !is_compat_task() && TASK_SIZE < TASK_MAX_SIZE) {
193	/* Upgrade the page table to 4 levels and retry. */	193	/* Upgrade the page table to 4 levels and retry. */
194	rc = crst_table_upgrade(mm, TASK_MAX_SIZE);	194	rc = crst_table_upgrade(mm);
195	if (rc)	195	if (rc)
196	return (unsigned long) rc;	196	return (unsigned long) rc;
197	area = arch_get_unmapped_area(filp, addr, len, pgoff, flags);	197	area = arch_get_unmapped_area(filp, addr, len, pgoff, flags);
@@ -213,7 +213,7 @@ s390_get_unmapped_area_topdown(struct file *filp, const unsigned long addr, · 15 unmodified lines
213	return area;	213	return area;
214	if (area == -ENOMEM && !is_compat_task() && TASK_SIZE < TASK_MAX_SIZE) {	214	if (area == -ENOMEM && !is_compat_task() && TASK_SIZE < TASK_MAX_SIZE) {
215	/* Upgrade the page table to 4 levels and retry. */	215	/* Upgrade the page table to 4 levels and retry. */
216	rc = crst_table_upgrade(mm, TASK_MAX_SIZE);	216	rc = crst_table_upgrade(mm);
217	if (rc)	217	if (rc)
218	return (unsigned long) rc;	218	return (unsigned long) rc;
219	area = arch_get_unmapped_area_topdown(filp, addr, len,	219	area = arch_get_unmapped_area_topdown(filp, addr, len,

arch/s390/mm/pgalloc.c+28−57

@@ -76,81 +76,52 @@ static void __crst_table_upgrade(void *arg) · 75 unmodified lines
76	__tlb_flush_local();	76	__tlb_flush_local();
77	}	77	}
78		78
79	int crst_table_upgrade(struct mm_struct *mm, unsigned long limit)	79	int crst_table_upgrade(struct mm_struct *mm)
80	{	80	{
81	unsigned long table, pgd;	81	unsigned long table, pgd;
82	unsigned long entry;
83	int flush;
84		82
85	BUG_ON(limit > TASK_MAX_SIZE);	83	/* upgrade should only happen from 3 to 4 levels */
86	flush = 0;	84	BUG_ON(mm->context.asce_limit != (1UL << 42));
87	repeat:	85
88	table = crst_table_alloc(mm);	86	table = crst_table_alloc(mm);
89	if (!table)	87	if (!table)
90	return -ENOMEM;	88	return -ENOMEM;
		89
91	spin_lock_bh(&mm->page_table_lock);	90	spin_lock_bh(&mm->page_table_lock);
92	if (mm->context.asce_limit < limit) {	91	pgd = (unsigned long *) mm->pgd;
93	pgd = (unsigned long *) mm->pgd;	92	crst_table_init(table, _REGION2_ENTRY_EMPTY);
94	if (mm->context.asce_limit <= (1UL << 31)) {	93	pgd_populate(mm, (pgd_t ) table, (pud_t ) pgd);
95	entry = _REGION3_ENTRY_EMPTY;	94	mm->pgd = (pgd_t *) table;
96	mm->context.asce_limit = 1UL << 42;	95	mm->context.asce_limit = 1UL << 53;
97	mm->context.asce_bits = _ASCE_TABLE_LENGTH \|	96	mm->context.asce = __pa(mm->pgd) \| _ASCE_TABLE_LENGTH \|
98	_ASCE_USER_BITS \|	97	_ASCE_USER_BITS \| _ASCE_TYPE_REGION2;
99	_ASCE_TYPE_REGION3;	98	mm->task_size = mm->context.asce_limit;
100	} else {
101	entry = _REGION2_ENTRY_EMPTY;
102	mm->context.asce_limit = 1UL << 53;
103	mm->context.asce_bits = _ASCE_TABLE_LENGTH \|
104	_ASCE_USER_BITS \|
105	_ASCE_TYPE_REGION2;
106	}
107	crst_table_init(table, entry);
108	pgd_populate(mm, (pgd_t ) table, (pud_t ) pgd);
109	mm->pgd = (pgd_t *) table;
110	mm->task_size = mm->context.asce_limit;
111	table = NULL;
112	flush = 1;
113	}
114	spin_unlock_bh(&mm->page_table_lock);	99	spin_unlock_bh(&mm->page_table_lock);
115	if (table)	100
116	crst_table_free(mm, table);	101	on_each_cpu(__crst_table_upgrade, mm, 0);
117	if (mm->context.asce_limit < limit)
118	goto repeat;
119	if (flush)
120	on_each_cpu(__crst_table_upgrade, mm, 0);
121	return 0;	102	return 0;
122	}	103	}
123		104
124	void crst_table_downgrade(struct mm_struct *mm, unsigned long limit)	105	void crst_table_downgrade(struct mm_struct *mm)
125	{	106	{
126	pgd_t *pgd;	107	pgd_t *pgd;
127		108
		109	/* downgrade should only happen from 3 to 2 levels (compat only) */
		110	BUG_ON(mm->context.asce_limit != (1UL << 42));
		111
128	if (current->active_mm == mm) {	112	if (current->active_mm == mm) {
129	clear_user_asce();	113	clear_user_asce();
130	__tlb_flush_mm(mm);	114	__tlb_flush_mm(mm);
131	}	115	}
132	while (mm->context.asce_limit > limit) {	116
133	pgd = mm->pgd;	117	pgd = mm->pgd;
134	switch (pgd_val(*pgd) & _REGION_ENTRY_TYPE_MASK) {	118	mm->pgd = (pgd_t ) (pgd_val(pgd) & _REGION_ENTRY_ORIGIN);
135	case _REGION_ENTRY_TYPE_R2:	119	mm->context.asce_limit = 1UL << 31;
136	mm->context.asce_limit = 1UL << 42;	120	mm->context.asce = __pa(mm->pgd) \| _ASCE_TABLE_LENGTH \|
137	mm->context.asce_bits = _ASCE_TABLE_LENGTH \|	121	_ASCE_USER_BITS \| _ASCE_TYPE_SEGMENT;
138	_ASCE_USER_BITS \|	122	mm->task_size = mm->context.asce_limit;
139	_ASCE_TYPE_REGION3;	123	crst_table_free(mm, (unsigned long *) pgd);
140	break;	124
141	case _REGION_ENTRY_TYPE_R3:
142	mm->context.asce_limit = 1UL << 31;
143	mm->context.asce_bits = _ASCE_TABLE_LENGTH \|
144	_ASCE_USER_BITS \|
145	_ASCE_TYPE_SEGMENT;
146	break;
147	default:
148	BUG();
149	}
150	mm->pgd = (pgd_t ) (pgd_val(pgd) & _REGION_ENTRY_ORIGIN);
151	mm->task_size = mm->context.asce_limit;
152	crst_table_free(mm, (unsigned long *) pgd);
153	}
154	if (current->active_mm == mm)	125	if (current->active_mm == mm)
155	set_user_asce(mm);	126	set_user_asce(mm);
156	}	127	}

arch/s390/pci/pci_dma.c+10−6

 	zdev->dma_table = dma_alloc_cpu_table();
 	if (!zdev->dma_table) {
 		rc = -ENOMEM;
-		goto out_clean;
+		goto out;
 	}
 	/*
 	zdev->iommu_bitmap = vzalloc(zdev->iommu_pages / 8);
 	if (!zdev->iommu_bitmap) {
 		rc = -ENOMEM;
-		goto out_reg;
+		goto free_dma_table;
 	}
 	rc = zpci_register_ioat(zdev, 0, zdev->start_dma, zdev->end_dma,
 				(u64) zdev->dma_table);
 	if (rc)
-		goto out_reg;
+		goto free_bitmap;
-	return 0;
-out_reg:
+	return 0;
+free_bitmap:
+	vfree(zdev->iommu_bitmap);
+	zdev->iommu_bitmap = NULL;
+free_dma_table:
 	dma_free_cpu_table(zdev->dma_table);
-out_clean:
+	zdev->dma_table = NULL;
+out:
 	return rc;
 }

arch/x86/events/amd/core.c+1−1

@@ -115,7 +115,7 @@ static __initconst const u64 amd_hw_cache_event_ids · 114 unmodified lines
115	/*	115	/*
116	* AMD Performance Monitor K7 and later.	116	* AMD Performance Monitor K7 and later.
117	*/	117	*/
118	static const u64 amd_perfmon_event_map[] =	118	static const u64 amd_perfmon_event_map[PERF_COUNT_HW_MAX] =
119	{	119	{
120	[PERF_COUNT_HW_CPU_CYCLES] = 0x0076,	120	[PERF_COUNT_HW_CPU_CYCLES] = 0x0076,
121	[PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0,	121	[PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0,

arch/x86/events/intel/core.c+1−0

@@ -3639,6 +3639,7 @@ __init int intel_pmu_init(void) · 3638 unmodified lines
3639		3639
3640	case 78: /* 14nm Skylake Mobile */	3640	case 78: /* 14nm Skylake Mobile */
3641	case 94: /* 14nm Skylake Desktop */	3641	case 94: /* 14nm Skylake Desktop */
		3642	case 85: /* 14nm Skylake Server */
3642	x86_pmu.late_ack = true;	3643	x86_pmu.late_ack = true;
3643	memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids));	3644	memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids));
3644	memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));	3645	memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));

arch/x86/events/intel/lbr.c+4−2

 #define LBR_PLM (LBR_KERNEL | LBR_USER)
-#define LBR_SEL_MASK	0x1ff	/* valid bits in LBR_SELECT */
+#define LBR_SEL_MASK	0x3ff	/* valid bits in LBR_SELECT */
 #define LBR_NOT_SUPP	-1	/* LBR filter not supported */
 #define LBR_IGN		0	/* ignored */
 	 * The first 9 bits (LBR_SEL_MASK) in LBR_SELECT operate
 	 * in suppress mode. So LBR_SELECT should be set to
 	 * (~mask & LBR_SEL_MASK) | (mask & ~LBR_SEL_MASK)
+	 * But the 10th bit LBR_CALL_STACK does not operate
+	 * in suppress mode.
 	 */
-	reg->config = mask ^ x86_pmu.lbr_sel_mask;
+	reg->config = mask ^ (x86_pmu.lbr_sel_mask & ~LBR_CALL_STACK);
 	if ((br_type & PERF_SAMPLE_BRANCH_NO_CYCLES) &&
 	    (br_type & PERF_SAMPLE_BRANCH_NO_FLAGS) &&

arch/x86/events/intel/pt.c+64−11

@@ -136,9 +136,21 @@ static int __init pt_pmu_hw_init(void) · 135 unmodified lines
136	struct dev_ext_attribute *de_attrs;	136	struct dev_ext_attribute *de_attrs;
137	struct attribute **attrs;	137	struct attribute **attrs;
138	size_t size;	138	size_t size;
		139	u64 reg;
139	int ret;	140	int ret;
140	long i;	141	long i;
141		142
		143	if (boot_cpu_has(X86_FEATURE_VMX)) {
		144	/*
		145	* Intel SDM, 36.5 "Tracing post-VMXON" says that
		146	* "IA32_VMX_MISC[bit 14]" being 1 means PT can trace
		147	* post-VMXON.
		148	*/
		149	rdmsrl(MSR_IA32_VMX_MISC, reg);
		150	if (reg & BIT(14))
		151	pt_pmu.vmx = true;
		152	}
		153
142	attrs = NULL;	154	attrs = NULL;
143		155
144	for (i = 0; i < PT_CPUID_LEAVES; i++) {	156	for (i = 0; i < PT_CPUID_LEAVES; i++) {
@@ -269,20 +281,23 @@ static void pt_config(struct perf_event *event) · 124 unmodified lines
269		281
270	reg \|= (event->attr.config & PT_CONFIG_MASK);	282	reg \|= (event->attr.config & PT_CONFIG_MASK);
271		283
		284	event->hw.config = reg;
272	wrmsrl(MSR_IA32_RTIT_CTL, reg);	285	wrmsrl(MSR_IA32_RTIT_CTL, reg);
273	}	286	}
274		287
275	static void pt_config_start(bool start)	288	static void pt_config_stop(struct perf_event *event)
276	{	289	{
277	u64 ctl;	290	u64 ctl = READ_ONCE(event->hw.config);
		291
		292	/* may be already stopped by a PMI */
		293	if (!(ctl & RTIT_CTL_TRACEEN))
		294	return;
278		295
279	rdmsrl(MSR_IA32_RTIT_CTL, ctl);	296	ctl &= ~RTIT_CTL_TRACEEN;
280	if (start)
281	ctl \|= RTIT_CTL_TRACEEN;
282	else
283	ctl &= ~RTIT_CTL_TRACEEN;
284	wrmsrl(MSR_IA32_RTIT_CTL, ctl);	297	wrmsrl(MSR_IA32_RTIT_CTL, ctl);
285		298
		299	WRITE_ONCE(event->hw.config, ctl);
		300
286	/*	301	/*
287	* A wrmsr that disables trace generation serializes other PT	302	* A wrmsr that disables trace generation serializes other PT
288	* registers and causes all data packets to be written to memory,	303	* registers and causes all data packets to be written to memory,
@@ -291,8 +306,7 @@ static void pt_config_start(bool start) · 2 unmodified lines
291	* The below WMB, separating data store and aux_head store matches	306	* The below WMB, separating data store and aux_head store matches
292	* the consumer's RMB that separates aux_head load and data load.	307	* the consumer's RMB that separates aux_head load and data load.
293	*/	308	*/
294	if (!start)	309	wmb();
295	wmb();
296	}	310	}
297		311
298	static void pt_config_buffer(void *buf, unsigned int topa_idx,	312	static void pt_config_buffer(void *buf, unsigned int topa_idx,
@@ -942,11 +956,17 @@ void intel_pt_interrupt(void) · 643 unmodified lines
942	if (!ACCESS_ONCE(pt->handle_nmi))	956	if (!ACCESS_ONCE(pt->handle_nmi))
943	return;	957	return;
944		958
945	pt_config_start(false);	959	/*
		960	* If VMX is on and PT does not support it, don't touch anything.
		961	*/
		962	if (READ_ONCE(pt->vmx_on))
		963	return;
946		964
947	if (!event)	965	if (!event)
948	return;	966	return;
949		967
		968	pt_config_stop(event);
		969
950	buf = perf_get_aux(&pt->handle);	970	buf = perf_get_aux(&pt->handle);
951	if (!buf)	971	if (!buf)
952	return;	972	return;
@@ -983,6 +1003,35 @@ void intel_pt_interrupt(void) · 30 unmodified lines
983	}	1003	}
984	}	1004	}
985		1005
		1006	void intel_pt_handle_vmx(int on)
		1007	{
		1008	struct pt *pt = this_cpu_ptr(&pt_ctx);
		1009	struct perf_event *event;
		1010	unsigned long flags;
		1011
		1012	/* PT plays nice with VMX, do nothing */
		1013	if (pt_pmu.vmx)
		1014	return;
		1015
		1016	/*
		1017	* VMXON will clear RTIT_CTL.TraceEn; we need to make
		1018	* sure to not try to set it while VMX is on. Disable
		1019	* interrupts to avoid racing with pmu callbacks;
		1020	* concurrent PMI should be handled fine.
		1021	*/
		1022	local_irq_save(flags);
		1023	WRITE_ONCE(pt->vmx_on, on);
		1024
		1025	if (on) {
		1026	/* prevent pt_config_stop() from writing RTIT_CTL */
		1027	event = pt->handle.event;
		1028	if (event)
		1029	event->hw.config = 0;
		1030	}
		1031	local_irq_restore(flags);
		1032	}
		1033	EXPORT_SYMBOL_GPL(intel_pt_handle_vmx);
		1034
986	/*	1035	/*
987	* PMU callbacks	1036	* PMU callbacks
988	*/	1037	*/
@@ -992,6 +1041,9 @@ static void pt_event_start(struct perf_event *event, int mode) · 3 unmodified lines
992	struct pt *pt = this_cpu_ptr(&pt_ctx);	1041	struct pt *pt = this_cpu_ptr(&pt_ctx);
993	struct pt_buffer *buf = perf_get_aux(&pt->handle);	1042	struct pt_buffer *buf = perf_get_aux(&pt->handle);
994		1043
		1044	if (READ_ONCE(pt->vmx_on))
		1045	return;
		1046
995	if (!buf \|\| pt_buffer_is_full(buf, pt)) {	1047	if (!buf \|\| pt_buffer_is_full(buf, pt)) {
996	event->hw.state = PERF_HES_STOPPED;	1048	event->hw.state = PERF_HES_STOPPED;
997	return;	1049	return;
@@ -1014,7 +1066,8 @@ static void pt_event_stop(struct perf_event *event, int mode) · 16 unmodified lines
1014	* see comment in intel_pt_interrupt().	1066	* see comment in intel_pt_interrupt().
1015	*/	1067	*/
1016	ACCESS_ONCE(pt->handle_nmi) = 0;	1068	ACCESS_ONCE(pt->handle_nmi) = 0;
1017	pt_config_start(false);	1069
		1070	pt_config_stop(event);
1018		1071
1019	if (event->hw.state == PERF_HES_STOPPED)	1072	if (event->hw.state == PERF_HES_STOPPED)
1020	return;	1073	return;

arch/x86/events/intel/pt.h+3−0

 struct pt_pmu {
 	struct pmu		pmu;
 	u32			caps[PT_CPUID_REGS_NUM * PT_CPUID_LEAVES];
+	bool			vmx;
 };
 /**
  * struct pt - per-cpu pt context
  * @handle:	perf output handle
  * @handle_nmi:	do handle PT PMI on this cpu, there's an active event
+ * @vmx_on:	1 if VMX is ON on this cpu
  */
 struct pt {
 	struct perf_output_handle handle;
 	int			handle_nmi;
+	int			vmx_on;
 };
 #endif /* __INTEL_PT_H__ */

arch/x86/events/intel/rapl.c+1−0

@@ -718,6 +718,7 @@ static int __init rapl_pmu_init(void) · 717 unmodified lines
718	break;	718	break;
719	case 60: /* Haswell */	719	case 60: /* Haswell */
720	case 69: /* Haswell-Celeron */	720	case 69: /* Haswell-Celeron */
		721	case 70: /* Haswell GT3e */
721	case 61: /* Broadwell */	722	case 61: /* Broadwell */
722	case 71: /* Broadwell-H */	723	case 71: /* Broadwell-H */
723	rapl_cntr_mask = RAPL_IDX_HSW;	724	rapl_cntr_mask = RAPL_IDX_HSW;

arch/x86/include/asm/perf_event.h+4−0

 static inline void perf_check_microcode(void) { }
 #endif
+#ifdef CONFIG_CPU_SUP_INTEL
+ extern void intel_pt_handle_vmx(int on);
+#endif
 #if defined(CONFIG_PERF_EVENTS) && defined(CONFIG_CPU_SUP_AMD)
  extern void amd_pmu_enable_virt(void);
  extern void amd_pmu_disable_virt(void);

arch/x86/kernel/apic/vector.c+2−1

@@ -256,7 +256,8 @@ static void clear_irq_vector(int irq, struct apic_chip_data *data) · 255 unmodified lines
256	struct irq_desc *desc;	256	struct irq_desc *desc;
257	int cpu, vector;	257	int cpu, vector;
258		258
259	BUG_ON(!data->cfg.vector);	259	if (!data->cfg.vector)
		260	return;
260		261
261	vector = data->cfg.vector;	262	vector = data->cfg.vector;
262	for_each_cpu_and(cpu, data->domain, cpu_online_mask)	263	for_each_cpu_and(cpu, data->domain, cpu_online_mask)

arch/x86/kernel/head_32.S+0−6

 	/* Make changes effective */
 	wrmsr
-	/*
-	 * And make sure that all the mappings we set up have NX set from
-	 * the beginning.
-	 */
-	orl $(1 << (_PAGE_BIT_NX - 32)), pa(__supported_pte_mask + 4)
 enable_paging:
 /*

arch/x86/kvm/vmx.c+4−0

 static void kvm_cpu_vmxon(u64 addr)
 {
+	intel_pt_handle_vmx(1);
 	asm volatile (ASM_VMX_VMXON_RAX
 			: : "a"(&addr), "m"(addr)
 			: "memory", "cc");
 static void kvm_cpu_vmxoff(void)
 {
 	asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
+	intel_pt_handle_vmx(0);
 }
 static void hardware_disable(void)

arch/x86/mm/setup_nx.c+3−2

@@ -32,8 +32,9 @@ early_param("noexec", noexec_setup); · 31 unmodified lines
32		32
33	void x86_configure_nx(void)	33	void x86_configure_nx(void)
34	{	34	{
35	/* If disable_nx is set, clear NX on all new mappings going forward. */	35	if (boot_cpu_has(X86_FEATURE_NX) && !disable_nx)
36	if (disable_nx)	36	__supported_pte_mask \|= _PAGE_NX;
		37	else
37	__supported_pte_mask &= ~_PAGE_NX;	38	__supported_pte_mask &= ~_PAGE_NX;
38	}	39	}
39		40

arch/x86/xen/spinlock.c+6−0

 static void xen_qlock_kick(int cpu)
 {
+	int irq = per_cpu(lock_kicker_irq, cpu);
+	/* Don't kick if the target's kicker interrupt is not initialized. */
+	if (irq == -1)
+		return;
 	xen_send_IPI_one(cpu, XEN_SPIN_UNLOCK_VECTOR);
 }

drivers/block/rbd.c+25−27

 				u8 *order, u64 *snap_size);
 static int _rbd_dev_v2_snap_features(struct rbd_device *rbd_dev, u64 snap_id,
 		u64 *snap_features);
-static u64 rbd_snap_id_by_name(struct rbd_device *rbd_dev, const char *name);
 static int rbd_open(struct block_device *bdev, fmode_t mode)
 {
 	struct rbd_device *rbd_dev = (struct rbd_device *)data;
 	int ret;
-	if (!rbd_dev)
-		return;
 	dout("%s: \"%s\" notify_id %llu opcode %u\n", __func__,
 		rbd_dev->header_name, (unsigned long long)notify_id,
 		(unsigned int)opcode);
 	ceph_osdc_cancel_event(rbd_dev->watch_event);
 	rbd_dev->watch_event = NULL;
+	dout("%s flushing notifies\n", __func__);
+	ceph_osdc_flush_notifies(&rbd_dev->rbd_client->client->osdc);
 }
 /*
 static void rbd_dev_update_size(struct rbd_device *rbd_dev)
 {
 	sector_t size;
-	bool removing;
 	/*
-	 * Don't hold the lock while doing disk operations,
+	 * If EXISTS is not set, rbd_dev->disk may be NULL, so don't
-	 * or lock ordering will conflict with the bdev mutex via:
+	 * try to update its size.  If REMOVING is set, updating size
-	 * rbd_add() -> blkdev_get() -> rbd_open()
+	 * is just useless work since the device can't be opened.
 	 */
-	spin_lock_irq(&rbd_dev->lock);
+	if (test_bit(RBD_DEV_FLAG_EXISTS, &rbd_dev->flags) &&
-	removing = test_bit(RBD_DEV_FLAG_REMOVING, &rbd_dev->flags);
+	    !test_bit(RBD_DEV_FLAG_REMOVING, &rbd_dev->flags)) {
-	spin_unlock_irq(&rbd_dev->lock);
-	/*
-	 * If the device is being removed, rbd_dev->disk has
-	 * been destroyed, so don't try to update its size
-	 */
-	if (!removing) {
 		size = (sector_t)rbd_dev->mapping.size / SECTOR_SIZE;
 		dout("setting size to %llu sectors", (unsigned long long)size);
 		set_capacity(rbd_dev->disk, size);
 		__le64 features;
 		__le64 incompat;
 	} __attribute__ ((packed)) features_buf = { 0 };
-	u64 incompat;
+	u64 unsup;
 	int ret;
 	ret = rbd_obj_method_sync(rbd_dev, rbd_dev->header_name,
 	if (ret < sizeof (features_buf))
 		return -ERANGE;
-	incompat = le64_to_cpu(features_buf.incompat);
+	unsup = le64_to_cpu(features_buf.incompat) & ~RBD_FEATURES_SUPPORTED;
-	if (incompat & ~RBD_FEATURES_SUPPORTED)
+	if (unsup) {
+		rbd_warn(rbd_dev, "image uses unsupported features: 0x%llx",
+			 unsup);
 		return -ENXIO;
+	}
 	*snap_features = le64_to_cpu(features_buf.features);
 	return ret;
 }
+/*
+ * rbd_dev->header_rwsem must be locked for write and will be unlocked
+ * upon return.
+ */
 static int rbd_dev_device_setup(struct rbd_device *rbd_dev)
 {
 	int ret;
 	ret = rbd_dev_id_get(rbd_dev);
 	if (ret)
-		return ret;
+		goto err_out_unlock;
 	BUILD_BUG_ON(DEV_NAME_LEN
 			< sizeof (RBD_DRV_NAME) + MAX_INT_FORMAT_WIDTH);
 	/* Everything's ready.  Announce the disk to the world. */
 	set_bit(RBD_DEV_FLAG_EXISTS, &rbd_dev->flags);
-	add_disk(rbd_dev->disk);
+	up_write(&rbd_dev->header_rwsem);
+	add_disk(rbd_dev->disk);
 	pr_info("%s: added with size 0x%llx\n", rbd_dev->disk->disk_name,
 		(unsigned long long) rbd_dev->mapping.size);
 		unregister_blkdev(rbd_dev->major, rbd_dev->name);
 err_out_id:
 	rbd_dev_id_put(rbd_dev);
+err_out_unlock:
+	up_write(&rbd_dev->header_rwsem);
 	return ret;
 }
 	spec = NULL;		/* rbd_dev now owns this */
 	rbd_opts = NULL;	/* rbd_dev now owns this */
+	down_write(&rbd_dev->header_rwsem);
 	rc = rbd_dev_image_probe(rbd_dev, 0);
 	if (rc < 0)
 		goto err_out_rbd_dev;
 	return rc;
 err_out_rbd_dev:
+	up_write(&rbd_dev->header_rwsem);
 	rbd_dev_destroy(rbd_dev);
 err_out_client:
 	rbd_put_client(rbdc);
 		return ret;
 	rbd_dev_header_unwatch_sync(rbd_dev);
-	/*
-	 * flush remaining watch callbacks - these must be complete
-	 * before the osd_client is shutdown
-	 */
-	dout("%s: flushing notifies", __func__);
-	ceph_osdc_flush_notifies(&rbd_dev->rbd_client->client->osdc);
 	/*
 	 * Don't free anything from rbd_dev->disk until after all

drivers/cpufreq/cpufreq_governor.c+2−6

 		wall_time = cur_wall_time - j_cdbs->prev_cpu_wall;
 		j_cdbs->prev_cpu_wall = cur_wall_time;
-		if (cur_idle_time <= j_cdbs->prev_cpu_idle) {
+		idle_time = cur_idle_time - j_cdbs->prev_cpu_idle;
-			idle_time = 0;
+		j_cdbs->prev_cpu_idle = cur_idle_time;
-		} else {
-			idle_time = cur_idle_time - j_cdbs->prev_cpu_idle;
-			j_cdbs->prev_cpu_idle = cur_idle_time;
-		}
 		if (ignore_nice) {
 			u64 cur_nice = kcpustat_cpu(j).cpustat[CPUTIME_NICE];

drivers/cpufreq/intel_pstate.c+5−0

 			if (err)
 				goto skip_tar;
+			/* For level 1 and 2, bits[23:16] contain the ratio */
+			if (tdp_ctrl)
+				tdp_ratio >>= 16;
+			tdp_ratio &= 0xff; /* ratios are only 8 bits long */
 			if (tdp_ratio - 1 == tar) {
 				max_pstate = tar;
 				pr_debug("max_pstate=TAC %x\n", max_pstate);

drivers/crypto/talitos.c+57−30

 		ptr->eptr = upper_32_bits(dma_addr);
 }
+static void copy_talitos_ptr(struct talitos_ptr *dst_ptr,
+			     struct talitos_ptr *src_ptr, bool is_sec1)
+{
+	dst_ptr->ptr = src_ptr->ptr;
+	if (!is_sec1)
+		dst_ptr->eptr = src_ptr->eptr;
+}
 static void to_talitos_ptr_len(struct talitos_ptr *ptr, unsigned int len,
 			       bool is_sec1)
 {
 	sg_count = dma_map_sg(dev, areq->src, edesc->src_nents ?: 1,
 			      (areq->src == areq->dst) ? DMA_BIDIRECTIONAL
 							   : DMA_TO_DEVICE);
 	/* hmac data */
 	desc->ptr[1].len = cpu_to_be16(areq->assoclen);
 	if (sg_count > 1 &&
 	    (ret = sg_to_link_tbl_offset(areq->src, sg_count, 0,
 					 areq->assoclen,
 					 &edesc->link_tbl[tbl_off])) > 1) {
-		tbl_off += ret;
 		to_talitos_ptr(&desc->ptr[1], edesc->dma_link_tbl + tbl_off *
 			       sizeof(struct talitos_ptr), 0);
 		desc->ptr[1].j_extent = DESC_PTR_LNKTBL_JUMP;
 		dma_sync_single_for_device(dev, edesc->dma_link_tbl,
 					   edesc->dma_len, DMA_BIDIRECTIONAL);
+		tbl_off += ret;
 	} else {
 		to_talitos_ptr(&desc->ptr[1], sg_dma_address(areq->src), 0);
 		desc->ptr[1].j_extent = 0;
 	if (edesc->desc.hdr & DESC_HDR_MODE1_MDEU_CICV)
 		sg_link_tbl_len += authsize;
-	if (sg_count > 1 &&
+	if (sg_count == 1) {
-	    (ret = sg_to_link_tbl_offset(areq->src, sg_count, areq->assoclen,
+		to_talitos_ptr(&desc->ptr[4], sg_dma_address(areq->src) +
-					 sg_link_tbl_len,
+			       areq->assoclen, 0);
-					 &edesc->link_tbl[tbl_off])) > 1) {
+	} else if ((ret = sg_to_link_tbl_offset(areq->src, sg_count,
-		tbl_off += ret;
+						areq->assoclen, sg_link_tbl_len,
+						&edesc->link_tbl[tbl_off])) >
+		   1) {
 		desc->ptr[4].j_extent |= DESC_PTR_LNKTBL_JUMP;
 		to_talitos_ptr(&desc->ptr[4], edesc->dma_link_tbl +
 					      tbl_off *
 		dma_sync_single_for_device(dev, edesc->dma_link_tbl,
 					   edesc->dma_len,
 					   DMA_BIDIRECTIONAL);
-	} else
+		tbl_off += ret;
-		to_talitos_ptr(&desc->ptr[4], sg_dma_address(areq->src), 0);
+	} else {
+		copy_talitos_ptr(&desc->ptr[4], &edesc->link_tbl[tbl_off], 0);
+	}
 	/* cipher out */
 	desc->ptr[5].len = cpu_to_be16(cryptlen);
 	edesc->icv_ool = false;
-	if (sg_count > 1 &&
+	if (sg_count == 1) {
-	    (sg_count = sg_to_link_tbl_offset(areq->dst, sg_count,
+		to_talitos_ptr(&desc->ptr[5], sg_dma_address(areq->dst) +
+			       areq->assoclen, 0);
+	} else if ((sg_count =
+			sg_to_link_tbl_offset(areq->dst, sg_count,
 					      areq->assoclen, cryptlen,
-					      &edesc->link_tbl[tbl_off])) >
+					      &edesc->link_tbl[tbl_off])) > 1) {
-	    1) {
 		struct talitos_ptr *tbl_ptr = &edesc->link_tbl[tbl_off];
 		to_talitos_ptr(&desc->ptr[5], edesc->dma_link_tbl +
 					   edesc->dma_len, DMA_BIDIRECTIONAL);
 		edesc->icv_ool = true;
-	} else
+	} else {
-		to_talitos_ptr(&desc->ptr[5], sg_dma_address(areq->dst), 0);
+		copy_talitos_ptr(&desc->ptr[5], &edesc->link_tbl[tbl_off], 0);
+	}
 	/* iv out */
 	map_single_talitos_ptr(dev, &desc->ptr[6], ivsize, ctx->iv,
 	struct talitos_alg_template algt;
 };
-static int talitos_cra_init(struct crypto_tfm *tfm)
+static int talitos_init_common(struct talitos_ctx *ctx,
+			       struct talitos_crypto_alg *talitos_alg)
 {
-	struct crypto_alg *alg = tfm->__crt_alg;
-	struct talitos_crypto_alg *talitos_alg;
-	struct talitos_ctx *ctx = crypto_tfm_ctx(tfm);
 	struct talitos_private *priv;
-	if ((alg->cra_flags & CRYPTO_ALG_TYPE_MASK) == CRYPTO_ALG_TYPE_AHASH)
-		talitos_alg = container_of(__crypto_ahash_alg(alg),
-					   struct talitos_crypto_alg,
-					   algt.alg.hash);
-	else
-		talitos_alg = container_of(alg, struct talitos_crypto_alg,
-					   algt.alg.crypto);
 	/* update context with ptr to dev */
 	ctx->dev = talitos_alg->dev;
 	return 0;
 }
+static int talitos_cra_init(struct crypto_tfm *tfm)
+{
+	struct crypto_alg *alg = tfm->__crt_alg;
+	struct talitos_crypto_alg *talitos_alg;
+	struct talitos_ctx *ctx = crypto_tfm_ctx(tfm);
+	if ((alg->cra_flags & CRYPTO_ALG_TYPE_MASK) == CRYPTO_ALG_TYPE_AHASH)
+		talitos_alg = container_of(__crypto_ahash_alg(alg),
+					   struct talitos_crypto_alg,
+					   algt.alg.hash);
+	else
+		talitos_alg = container_of(alg, struct talitos_crypto_alg,
+					   algt.alg.crypto);
+	return talitos_init_common(ctx, talitos_alg);
+}
 static int talitos_cra_init_aead(struct crypto_aead *tfm)
 {
-	talitos_cra_init(crypto_aead_tfm(tfm));
+	struct aead_alg *alg = crypto_aead_alg(tfm);
-	return 0;
+	struct talitos_crypto_alg *talitos_alg;
+	struct talitos_ctx *ctx = crypto_aead_ctx(tfm);
+	talitos_alg = container_of(alg, struct talitos_crypto_alg,
+				   algt.alg.aead);
+	return talitos_init_common(ctx, talitos_alg);
 }
 static int talitos_cra_init_ahash(struct crypto_tfm *tfm)

drivers/edac/i7core_edac.c+1−1

@@ -1866,7 +1866,7 @@ static int i7core_mce_check_error(struct notifier_block *nb, unsigned long val, · 1865 unmodified lines
1866		1866
1867	i7_dev = get_i7core_dev(mce->socketid);	1867	i7_dev = get_i7core_dev(mce->socketid);
1868	if (!i7_dev)	1868	if (!i7_dev)
1869	return NOTIFY_BAD;	1869	return NOTIFY_DONE;
1870		1870
1871	mci = i7_dev->mci;	1871	mci = i7_dev->mci;
1872	pvt = mci->pvt_info;	1872	pvt = mci->pvt_info;

drivers/edac/sb_edac.c+1−1

@@ -3168,7 +3168,7 @@ static int sbridge_mce_check_error(struct notifier_block *nb, unsigned long val, · 3167 unmodified lines
3168		3168
3169	mci = get_mci_for_node_id(mce->socketid);	3169	mci = get_mci_for_node_id(mce->socketid);
3170	if (!mci)	3170	if (!mci)
3171	return NOTIFY_BAD;	3171	return NOTIFY_DONE;
3172	pvt = mci->pvt_info;	3172	pvt = mci->pvt_info;
3173		3173
3174	/*	3174	/*

drivers/firmware/efi/vars.c+26−11

@@ -202,29 +202,44 @@ static const struct variable_validate variable_validate[] = { · 201 unmodified lines
202	{ NULL_GUID, "", NULL },	202	{ NULL_GUID, "", NULL },
203	};	203	};
204		204
		205	/*
		206	* Check if @var_name matches the pattern given in @match_name.
		207	*
		208	* @var_name: an array of @len non-NUL characters.
		209	* @match_name: a NUL-terminated pattern string, optionally ending in "*". A
		210	* final "*" character matches any trailing characters @var_name,
		211	* including the case when there are none left in @var_name.
		212	* @match: on output, the number of non-wildcard characters in @match_name
		213	* that @var_name matches, regardless of the return value.
		214	* @return: whether @var_name fully matches @match_name.
		215	*/
205	static bool	216	static bool
206	variable_matches(const char var_name, size_t len, const char match_name,	217	variable_matches(const char var_name, size_t len, const char match_name,
207	int *match)	218	int *match)
208	{	219	{
209	for (match = 0; ; (match)++) {	220	for (match = 0; ; (match)++) {
210	char c = match_name[*match];	221	char c = match_name[*match];
211	char u = var_name[*match];
212		222
213	/* Wildcard in the matching name means we've matched */	223	switch (c) {
214	if (c == '*')	224	case '*':
		225	/* Wildcard in @match_name means we've matched. */
215	return true;	226	return true;
216		227
217	/* Case sensitive match */	228	case '\0':
218	if (!c && *match == len)	229	/* @match_name has ended. Has @var_name too? */
219	return true;	230	return (*match == len);
220		231
221	if (c != u)	232	default:
		233	/*
		234	* We've reached a non-wildcard char in @match_name.
		235	* Continue only if there's an identical character in
		236	* @var_name.
		237	*/
		238	if (match < len && c == var_name[match])
		239	continue;
222	return false;	240	return false;
223		241	}
224	if (!c)
225	return true;
226	}	242	}
227	return true;
228	}	243	}
229		244
230	bool	245	bool

drivers/firmware/psci.c+1−1

@@ -360,7 +360,7 @@ static struct cpuidle_ops psci_cpuidle_ops __initdata = { · 359 unmodified lines
360	.init = psci_dt_cpu_init_idle,	360	.init = psci_dt_cpu_init_idle,
361	};	361	};
362		362
363	CPUIDLE_METHOD_OF_DECLARE(psci, "arm,psci", &psci_cpuidle_ops);	363	CPUIDLE_METHOD_OF_DECLARE(psci, "psci", &psci_cpuidle_ops);
364	#endif	364	#endif
365	#endif	365	#endif
366		366

drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c+7−4

 	return amdgpu_atpx_priv.atpx_detected;
 }
-bool amdgpu_has_atpx_dgpu_power_cntl(void) {
-	return amdgpu_atpx_priv.atpx.functions.power_cntl;
-}
 /**
  * amdgpu_atpx_call - call an ATPX method
  *
  */
 static int amdgpu_atpx_validate(struct amdgpu_atpx *atpx)
 {
+	/* make sure required functions are enabled */
+	/* dGPU power control is required */
+	if (atpx->functions.power_cntl == false) {
+		printk("ATPX dGPU power cntl not present, forcing\n");
+		atpx->functions.power_cntl = true;
+	}
 	if (atpx->functions.px_params) {
 		union acpi_object *info;
 		struct atpx_px_params output;

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c+1−7

 	"LAST",
 };
-#if defined(CONFIG_VGA_SWITCHEROO)
-bool amdgpu_has_atpx_dgpu_power_cntl(void);
-#else
-static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; }
-#endif
 bool amdgpu_device_is_px(struct drm_device *dev)
 {
 	struct amdgpu_device *adev = dev->dev_private;
 	if (amdgpu_runtime_pm == 1)
 		runtime = true;
-	if (amdgpu_device_is_px(ddev) && amdgpu_has_atpx_dgpu_power_cntl())
+	if (amdgpu_device_is_px(ddev))
 		runtime = true;
 	vga_switcheroo_register_client(adev->pdev, &amdgpu_switcheroo_ops, runtime);
 	if (runtime)

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c+4−1

 {
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-	return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0);
+	if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS)
+		return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0);
+	else
+		return 0;
 }
 static int gmc_v7_0_sw_init(void *handle)

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c+4−1

 {
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-	return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0);
+	if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS)
+		return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0);
+	else
+		return 0;
 }
 #define mmMC_SEQ_MISC0_FIJI 0xA71

drivers/gpu/drm/drm_dp_mst_topology.c+20−0

 		req_payload.start_slot = cur_slots;
 		if (mgr->proposed_vcpis[i]) {
 			port = container_of(mgr->proposed_vcpis[i], struct drm_dp_mst_port, vcpi);
+			port = drm_dp_get_validated_port_ref(mgr, port);
+			if (!port) {
+				mutex_unlock(&mgr->payload_lock);
+				return -EINVAL;
+			}
 			req_payload.num_slots = mgr->proposed_vcpis[i]->num_slots;
 			req_payload.vcpi = mgr->proposed_vcpis[i]->vcpi;
 		} else {
 			mgr->payloads[i].payload_state = req_payload.payload_state;
 		}
 		cur_slots += req_payload.num_slots;
+		if (port)
+			drm_dp_put_port(port);
 	}
 	for (i = 0; i < mgr->max_payloads; i++) {
 	if (mgr->mst_primary) {
 		int sret;
+		u8 guid[16];
 		sret = drm_dp_dpcd_read(mgr->aux, DP_DPCD_REV, mgr->dpcd, DP_RECEIVER_CAP_SIZE);
 		if (sret != DP_RECEIVER_CAP_SIZE) {
 			DRM_DEBUG_KMS("dpcd read failed - undocked during suspend?\n");
 			ret = -1;
 			goto out_unlock;
 		}
+		/* Some hubs forget their guids after they resume */
+		sret = drm_dp_dpcd_read(mgr->aux, DP_GUID, guid, 16);
+		if (sret != 16) {
+			DRM_DEBUG_KMS("dpcd read failed - undocked during suspend?\n");
+			ret = -1;
+			goto out_unlock;
+		}
+		drm_dp_check_mstb_guid(mgr->mst_primary, guid);
 		ret = 0;
 	} else
 		ret = -1;

drivers/gpu/drm/etnaviv/etnaviv_gpu.c+18−13

 		goto fail;
 	}
+	/*
+	 * Set the GPU linear window to be at the end of the DMA window, where
+	 * the CMA area is likely to reside. This ensures that we are able to
+	 * map the command buffers while having the linear window overlap as
+	 * much RAM as possible, so we can optimize mappings for other buffers.
+	 *
+	 * For 3D cores only do this if MC2.0 is present, as with MC1.0 it leads
+	 * to different views of the memory on the individual engines.
+	 */
+	if (!(gpu->identity.features & chipFeatures_PIPE_3D) ||
+	    (gpu->identity.minor_features0 & chipMinorFeatures0_MC20)) {
+		u32 dma_mask = (u32)dma_get_required_mask(gpu->dev);
+		if (dma_mask < PHYS_OFFSET + SZ_2G)
+			gpu->memory_base = PHYS_OFFSET;
+		else
+			gpu->memory_base = dma_mask - SZ_2G + 1;
+	}
 	ret = etnaviv_hw_reset(gpu);
 	if (ret)
 		goto fail;
 {
 	struct device *dev = &pdev->dev;
 	struct etnaviv_gpu *gpu;
-	u32 dma_mask;
 	int err = 0;
 	gpu = devm_kzalloc(dev, sizeof(*gpu), GFP_KERNEL);
 	gpu->dev = &pdev->dev;
 	mutex_init(&gpu->lock);
-	/*
-	 * Set the GPU linear window to be at the end of the DMA window, where
-	 * the CMA area is likely to reside. This ensures that we are able to
-	 * map the command buffers while having the linear window overlap as
-	 * much RAM as possible, so we can optimize mappings for other buffers.
-	 */
-	dma_mask = (u32)dma_get_required_mask(dev);
-	if (dma_mask < PHYS_OFFSET + SZ_2G)
-		gpu->memory_base = PHYS_OFFSET;
-	else
-		gpu->memory_base = dma_mask - SZ_2G + 1;
 	/* Map registers: */
 	gpu->mmio = etnaviv_ioremap(pdev, NULL, dev_name(gpu->dev));
 	if (IS_ERR(gpu->mmio))

drivers/gpu/drm/radeon/evergreen.c+153−1

@@ -2608,10 +2608,152 @@ static void evergreen_agp_enable(struct radeon_device *rdev) · 2607 unmodified lines
2608	WREG32(VM_CONTEXT1_CNTL, 0);	2608	WREG32(VM_CONTEXT1_CNTL, 0);
2609	}	2609	}
2610		2610
		2611	static const unsigned ni_dig_offsets[] =
		2612	{
		2613	NI_DIG0_REGISTER_OFFSET,
		2614	NI_DIG1_REGISTER_OFFSET,
		2615	NI_DIG2_REGISTER_OFFSET,
		2616	NI_DIG3_REGISTER_OFFSET,
		2617	NI_DIG4_REGISTER_OFFSET,
		2618	NI_DIG5_REGISTER_OFFSET
		2619	};
		2620
		2621	static const unsigned ni_tx_offsets[] =
		2622	{
		2623	NI_DCIO_UNIPHY0_UNIPHY_TX_CONTROL1,
		2624	NI_DCIO_UNIPHY1_UNIPHY_TX_CONTROL1,
		2625	NI_DCIO_UNIPHY2_UNIPHY_TX_CONTROL1,
		2626	NI_DCIO_UNIPHY3_UNIPHY_TX_CONTROL1,
		2627	NI_DCIO_UNIPHY4_UNIPHY_TX_CONTROL1,
		2628	NI_DCIO_UNIPHY5_UNIPHY_TX_CONTROL1
		2629	};
		2630
		2631	static const unsigned evergreen_dp_offsets[] =
		2632	{
		2633	EVERGREEN_DP0_REGISTER_OFFSET,
		2634	EVERGREEN_DP1_REGISTER_OFFSET,
		2635	EVERGREEN_DP2_REGISTER_OFFSET,
		2636	EVERGREEN_DP3_REGISTER_OFFSET,
		2637	EVERGREEN_DP4_REGISTER_OFFSET,
		2638	EVERGREEN_DP5_REGISTER_OFFSET
		2639	};
		2640
		2641
		2642	/*
		2643	* Assumption is that EVERGREEN_CRTC_MASTER_EN enable for requested crtc
		2644	* We go from crtc to connector and it is not relible since it
		2645	* should be an opposite direction .If crtc is enable then
		2646	* find the dig_fe which selects this crtc and insure that it enable.
		2647	* if such dig_fe is found then find dig_be which selects found dig_be and
		2648	* insure that it enable and in DP_SST mode.
		2649	* if UNIPHY_PLL_CONTROL1.enable then we should disconnect timing
		2650	* from dp symbols clocks .
		2651	*/
		2652	static bool evergreen_is_dp_sst_stream_enabled(struct radeon_device *rdev,
		2653	unsigned crtc_id, unsigned *ret_dig_fe)
		2654	{
		2655	unsigned i;
		2656	unsigned dig_fe;
		2657	unsigned dig_be;
		2658	unsigned dig_en_be;
		2659	unsigned uniphy_pll;
		2660	unsigned digs_fe_selected;
		2661	unsigned dig_be_mode;
		2662	unsigned dig_fe_mask;
		2663	bool is_enabled = false;
		2664	bool found_crtc = false;
		2665
		2666	/* loop through all running dig_fe to find selected crtc */
		2667	for (i = 0; i < ARRAY_SIZE(ni_dig_offsets); i++) {
		2668	dig_fe = RREG32(NI_DIG_FE_CNTL + ni_dig_offsets[i]);
		2669	if (dig_fe & NI_DIG_FE_CNTL_SYMCLK_FE_ON &&
		2670	crtc_id == NI_DIG_FE_CNTL_SOURCE_SELECT(dig_fe)) {
		2671	/* found running pipe */
		2672	found_crtc = true;
		2673	dig_fe_mask = 1 << i;
		2674	dig_fe = i;
		2675	break;
		2676	}
		2677	}
		2678
		2679	if (found_crtc) {
		2680	/* loop through all running dig_be to find selected dig_fe */
		2681	for (i = 0; i < ARRAY_SIZE(ni_dig_offsets); i++) {
		2682	dig_be = RREG32(NI_DIG_BE_CNTL + ni_dig_offsets[i]);
		2683	/* if dig_fe_selected by dig_be? */
		2684	digs_fe_selected = NI_DIG_BE_CNTL_FE_SOURCE_SELECT(dig_be);
		2685	dig_be_mode = NI_DIG_FE_CNTL_MODE(dig_be);
		2686	if (dig_fe_mask & digs_fe_selected &&
		2687	/* if dig_be in sst mode? */
		2688	dig_be_mode == NI_DIG_BE_DPSST) {
		2689	dig_en_be = RREG32(NI_DIG_BE_EN_CNTL +
		2690	ni_dig_offsets[i]);
		2691	uniphy_pll = RREG32(NI_DCIO_UNIPHY0_PLL_CONTROL1 +
		2692	ni_tx_offsets[i]);
		2693	/* dig_be enable and tx is running */
		2694	if (dig_en_be & NI_DIG_BE_EN_CNTL_ENABLE &&
		2695	dig_en_be & NI_DIG_BE_EN_CNTL_SYMBCLK_ON &&
		2696	uniphy_pll & NI_DCIO_UNIPHY0_PLL_CONTROL1_ENABLE) {
		2697	is_enabled = true;
		2698	*ret_dig_fe = dig_fe;
		2699	break;
		2700	}
		2701	}
		2702	}
		2703	}
		2704
		2705	return is_enabled;
		2706	}
		2707
		2708	/*
		2709	* Blank dig when in dp sst mode
		2710	* Dig ignores crtc timing
		2711	*/
		2712	static void evergreen_blank_dp_output(struct radeon_device *rdev,
		2713	unsigned dig_fe)
		2714	{
		2715	unsigned stream_ctrl;
		2716	unsigned fifo_ctrl;
		2717	unsigned counter = 0;
		2718
		2719	if (dig_fe >= ARRAY_SIZE(evergreen_dp_offsets)) {
		2720	DRM_ERROR("invalid dig_fe %d\n", dig_fe);
		2721	return;
		2722	}
		2723
		2724	stream_ctrl = RREG32(EVERGREEN_DP_VID_STREAM_CNTL +
		2725	evergreen_dp_offsets[dig_fe]);
		2726	if (!(stream_ctrl & EVERGREEN_DP_VID_STREAM_CNTL_ENABLE)) {
		2727	DRM_ERROR("dig %d , should be enable\n", dig_fe);
		2728	return;
		2729	}
		2730
		2731	stream_ctrl &=~EVERGREEN_DP_VID_STREAM_CNTL_ENABLE;
		2732	WREG32(EVERGREEN_DP_VID_STREAM_CNTL +
		2733	evergreen_dp_offsets[dig_fe], stream_ctrl);
		2734
		2735	stream_ctrl = RREG32(EVERGREEN_DP_VID_STREAM_CNTL +
		2736	evergreen_dp_offsets[dig_fe]);
		2737	while (counter < 32 && stream_ctrl & EVERGREEN_DP_VID_STREAM_STATUS) {
		2738	msleep(1);
		2739	counter++;
		2740	stream_ctrl = RREG32(EVERGREEN_DP_VID_STREAM_CNTL +
		2741	evergreen_dp_offsets[dig_fe]);
		2742	}
		2743	if (counter >= 32 )
		2744	DRM_ERROR("counter exceeds %d\n", counter);
		2745
		2746	fifo_ctrl = RREG32(EVERGREEN_DP_STEER_FIFO + evergreen_dp_offsets[dig_fe]);
		2747	fifo_ctrl \|= EVERGREEN_DP_STEER_FIFO_RESET;
		2748	WREG32(EVERGREEN_DP_STEER_FIFO + evergreen_dp_offsets[dig_fe], fifo_ctrl);
		2749
		2750	}
		2751
2611	void evergreen_mc_stop(struct radeon_device rdev, struct evergreen_mc_save save)	2752	void evergreen_mc_stop(struct radeon_device rdev, struct evergreen_mc_save save)
2612	{	2753	{
2613	u32 crtc_enabled, tmp, frame_count, blackout;	2754	u32 crtc_enabled, tmp, frame_count, blackout;
2614	int i, j;	2755	int i, j;
		2756	unsigned dig_fe;
2615		2757
2616	if (!ASIC_IS_NODCE(rdev)) {	2758	if (!ASIC_IS_NODCE(rdev)) {
2617	save->vga_render_control = RREG32(VGA_RENDER_CONTROL);	2759	save->vga_render_control = RREG32(VGA_RENDER_CONTROL);
@@ -2651,7 +2793,17 @@ void evergreen_mc_stop(struct radeon_device rdev, struct evergreen_mc_save sav · 33 unmodified lines
2651	break;	2793	break;
2652	udelay(1);	2794	udelay(1);
2653	}	2795	}
2654		2796	/we should disable dig if it drives dp sst/
		2797	/but we are in radeon_device_init and the topology is unknown/
		2798	/and it is available after radeon_modeset_init/
		2799	/the following method radeon_atom_encoder_dpms_dig/
		2800	/does the job if we initialize it properly/
		2801	/for now we do it this manually/
		2802	/**/
		2803	if (ASIC_IS_DCE5(rdev) &&
		2804	evergreen_is_dp_sst_stream_enabled(rdev, i ,&dig_fe))
		2805	evergreen_blank_dp_output(rdev, dig_fe);
		2806	/we could remove 6 lines below/
2655	/* XXX this is a hack to avoid strange behavior with EFI on certain systems */	2807	/* XXX this is a hack to avoid strange behavior with EFI on certain systems */
2656	WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);	2808	WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
2657	tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);	2809	tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);

drivers/gpu/drm/radeon/evergreen_reg.h+46−0

@@ -250,8 +250,43 @@ · 249 unmodified lines
250		250
251	/* HDMI blocks at 0x7030, 0x7c30, 0x10830, 0x11430, 0x12030, 0x12c30 */	251	/* HDMI blocks at 0x7030, 0x7c30, 0x10830, 0x11430, 0x12030, 0x12c30 */
252	#define EVERGREEN_HDMI_BASE 0x7030	252	#define EVERGREEN_HDMI_BASE 0x7030
		253	/DIG block/
		254	#define NI_DIG0_REGISTER_OFFSET (0x7000 - 0x7000)
		255	#define NI_DIG1_REGISTER_OFFSET (0x7C00 - 0x7000)
		256	#define NI_DIG2_REGISTER_OFFSET (0x10800 - 0x7000)
		257	#define NI_DIG3_REGISTER_OFFSET (0x11400 - 0x7000)
		258	#define NI_DIG4_REGISTER_OFFSET (0x12000 - 0x7000)
		259	#define NI_DIG5_REGISTER_OFFSET (0x12C00 - 0x7000)
		260
		261
		262	#define NI_DIG_FE_CNTL 0x7000
		263	# define NI_DIG_FE_CNTL_SOURCE_SELECT(x) ((x) & 0x3)
		264	# define NI_DIG_FE_CNTL_SYMCLK_FE_ON (1<<24)
		265
		266
		267	#define NI_DIG_BE_CNTL 0x7140
		268	# define NI_DIG_BE_CNTL_FE_SOURCE_SELECT(x) (((x) >> 8 ) & 0x3F)
		269	# define NI_DIG_FE_CNTL_MODE(x) (((x) >> 16) & 0x7 )
		270
		271	#define NI_DIG_BE_EN_CNTL 0x7144
		272	# define NI_DIG_BE_EN_CNTL_ENABLE (1 << 0)
		273	# define NI_DIG_BE_EN_CNTL_SYMBCLK_ON (1 << 8)
		274	# define NI_DIG_BE_DPSST 0
253		275
254	/* Display Port block */	276	/* Display Port block */
		277	#define EVERGREEN_DP0_REGISTER_OFFSET (0x730C - 0x730C)
		278	#define EVERGREEN_DP1_REGISTER_OFFSET (0x7F0C - 0x730C)
		279	#define EVERGREEN_DP2_REGISTER_OFFSET (0x10B0C - 0x730C)
		280	#define EVERGREEN_DP3_REGISTER_OFFSET (0x1170C - 0x730C)
		281	#define EVERGREEN_DP4_REGISTER_OFFSET (0x1230C - 0x730C)
		282	#define EVERGREEN_DP5_REGISTER_OFFSET (0x12F0C - 0x730C)
		283
		284
		285	#define EVERGREEN_DP_VID_STREAM_CNTL 0x730C
		286	# define EVERGREEN_DP_VID_STREAM_CNTL_ENABLE (1 << 0)
		287	# define EVERGREEN_DP_VID_STREAM_STATUS (1 <<16)
		288	#define EVERGREEN_DP_STEER_FIFO 0x7310
		289	# define EVERGREEN_DP_STEER_FIFO_RESET (1 << 0)
255	#define EVERGREEN_DP_SEC_CNTL 0x7280	290	#define EVERGREEN_DP_SEC_CNTL 0x7280
256	# define EVERGREEN_DP_SEC_STREAM_ENABLE (1 << 0)	291	# define EVERGREEN_DP_SEC_STREAM_ENABLE (1 << 0)
257	# define EVERGREEN_DP_SEC_ASP_ENABLE (1 << 4)	292	# define EVERGREEN_DP_SEC_ASP_ENABLE (1 << 4)
@@ -266,4 +301,15 @@ · 8 unmodified lines
266	# define EVERGREEN_DP_SEC_N_BASE_MULTIPLE(x) (((x) & 0xf) << 24)	301	# define EVERGREEN_DP_SEC_N_BASE_MULTIPLE(x) (((x) & 0xf) << 24)
267	# define EVERGREEN_DP_SEC_SS_EN (1 << 28)	302	# define EVERGREEN_DP_SEC_SS_EN (1 << 28)
268		303
		304	/DCIO_UNIPHY block/
		305	#define NI_DCIO_UNIPHY0_UNIPHY_TX_CONTROL1 (0x6600 -0x6600)
		306	#define NI_DCIO_UNIPHY1_UNIPHY_TX_CONTROL1 (0x6640 -0x6600)
		307	#define NI_DCIO_UNIPHY2_UNIPHY_TX_CONTROL1 (0x6680 - 0x6600)
		308	#define NI_DCIO_UNIPHY3_UNIPHY_TX_CONTROL1 (0x66C0 - 0x6600)
		309	#define NI_DCIO_UNIPHY4_UNIPHY_TX_CONTROL1 (0x6700 - 0x6600)
		310	#define NI_DCIO_UNIPHY5_UNIPHY_TX_CONTROL1 (0x6740 - 0x6600)
		311
		312	#define NI_DCIO_UNIPHY0_PLL_CONTROL1 0x6618
		313	# define NI_DCIO_UNIPHY0_PLL_CONTROL1_ENABLE (1 << 0)
		314
269	#endif	315	#endif

drivers/gpu/drm/ttm/ttm_bo.c+4−13

 void ttm_bo_move_to_lru_tail(struct ttm_buffer_object *bo)
 {
-	struct ttm_bo_device *bdev = bo->bdev;
+	int put_count = 0;
-	struct ttm_mem_type_manager *man;
 	lockdep_assert_held(&bo->resv->lock.base);
-	if (bo->mem.placement & TTM_PL_FLAG_NO_EVICT) {
+	put_count = ttm_bo_del_from_lru(bo);
-		list_del_init(&bo->swap);
+	ttm_bo_list_ref_sub(bo, put_count, true);
-		list_del_init(&bo->lru);
+	ttm_bo_add_to_lru(bo);
-	} else {
-		if (bo->ttm && !(bo->ttm->page_flags & TTM_PAGE_FLAG_SG))
-			list_move_tail(&bo->swap, &bo->glob->swap_lru);
-		man = &bdev->man[bo->mem.mem_type];
-		list_move_tail(&bo->lru, &man->lru);
-	}
 }
 EXPORT_SYMBOL(ttm_bo_move_to_lru_tail);

drivers/gpu/drm/virtio/virtgpu_display.c+12−0

@@ -267,11 +267,23 @@ static int virtio_gpu_crtc_atomic_check(struct drm_crtc *crtc, · 266 unmodified lines
267	return 0;	267	return 0;
268	}	268	}
269		269
		270	static void virtio_gpu_crtc_atomic_flush(struct drm_crtc *crtc,
		271	struct drm_crtc_state *old_state)
		272	{
		273	unsigned long flags;
		274
		275	spin_lock_irqsave(&crtc->dev->event_lock, flags);
		276	if (crtc->state->event)
		277	drm_crtc_send_vblank_event(crtc, crtc->state->event);
		278	spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
		279	}
		280
270	static const struct drm_crtc_helper_funcs virtio_gpu_crtc_helper_funcs = {	281	static const struct drm_crtc_helper_funcs virtio_gpu_crtc_helper_funcs = {
271	.enable = virtio_gpu_crtc_enable,	282	.enable = virtio_gpu_crtc_enable,
272	.disable = virtio_gpu_crtc_disable,	283	.disable = virtio_gpu_crtc_disable,
273	.mode_set_nofb = virtio_gpu_crtc_mode_set_nofb,	284	.mode_set_nofb = virtio_gpu_crtc_mode_set_nofb,
274	.atomic_check = virtio_gpu_crtc_atomic_check,	285	.atomic_check = virtio_gpu_crtc_atomic_check,
		286	.atomic_flush = virtio_gpu_crtc_atomic_flush,
275	};	287	};
276		288
277	static void virtio_gpu_enc_mode_set(struct drm_encoder *encoder,	289	static void virtio_gpu_enc_mode_set(struct drm_encoder *encoder,

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c+5−5

@@ -3293,19 +3293,19 @@ static const struct vmw_cmd_entry vmw_cmd_entries[SVGA_3D_CMD_MAX] = { · 3292 unmodified lines
3293	&vmw_cmd_dx_cid_check, true, false, true),	3293	&vmw_cmd_dx_cid_check, true, false, true),
3294	VMW_CMD_DEF(SVGA_3D_CMD_DX_DEFINE_QUERY, &vmw_cmd_dx_define_query,	3294	VMW_CMD_DEF(SVGA_3D_CMD_DX_DEFINE_QUERY, &vmw_cmd_dx_define_query,
3295	true, false, true),	3295	true, false, true),
3296	VMW_CMD_DEF(SVGA_3D_CMD_DX_DESTROY_QUERY, &vmw_cmd_ok,	3296	VMW_CMD_DEF(SVGA_3D_CMD_DX_DESTROY_QUERY, &vmw_cmd_dx_cid_check,
3297	true, false, true),	3297	true, false, true),
3298	VMW_CMD_DEF(SVGA_3D_CMD_DX_BIND_QUERY, &vmw_cmd_dx_bind_query,	3298	VMW_CMD_DEF(SVGA_3D_CMD_DX_BIND_QUERY, &vmw_cmd_dx_bind_query,
3299	true, false, true),	3299	true, false, true),
3300	VMW_CMD_DEF(SVGA_3D_CMD_DX_SET_QUERY_OFFSET,	3300	VMW_CMD_DEF(SVGA_3D_CMD_DX_SET_QUERY_OFFSET,
3301	&vmw_cmd_ok, true, false, true),	3301	&vmw_cmd_dx_cid_check, true, false, true),
3302	VMW_CMD_DEF(SVGA_3D_CMD_DX_BEGIN_QUERY, &vmw_cmd_ok,	3302	VMW_CMD_DEF(SVGA_3D_CMD_DX_BEGIN_QUERY, &vmw_cmd_dx_cid_check,
3303	true, false, true),	3303	true, false, true),
3304	VMW_CMD_DEF(SVGA_3D_CMD_DX_END_QUERY, &vmw_cmd_ok,	3304	VMW_CMD_DEF(SVGA_3D_CMD_DX_END_QUERY, &vmw_cmd_dx_cid_check,
3305	true, false, true),	3305	true, false, true),
3306	VMW_CMD_DEF(SVGA_3D_CMD_DX_READBACK_QUERY, &vmw_cmd_invalid,	3306	VMW_CMD_DEF(SVGA_3D_CMD_DX_READBACK_QUERY, &vmw_cmd_invalid,
3307	true, false, true),	3307	true, false, true),
3308	VMW_CMD_DEF(SVGA_3D_CMD_DX_SET_PREDICATION, &vmw_cmd_invalid,	3308	VMW_CMD_DEF(SVGA_3D_CMD_DX_SET_PREDICATION, &vmw_cmd_dx_cid_check,
3309	true, false, true),	3309	true, false, true),
3310	VMW_CMD_DEF(SVGA_3D_CMD_DX_SET_VIEWPORTS, &vmw_cmd_dx_cid_check,	3310	VMW_CMD_DEF(SVGA_3D_CMD_DX_SET_VIEWPORTS, &vmw_cmd_dx_cid_check,
3311	true, false, true),	3311	true, false, true),

drivers/gpu/drm/vmwgfx/vmwgfx_fb.c+3−3

@@ -573,9 +573,9 @@ static int vmw_fb_set_par(struct fb_info *info) · 572 unmodified lines
573	mode = old_mode;	573	mode = old_mode;
574	old_mode = NULL;	574	old_mode = NULL;
575	} else if (!vmw_kms_validate_mode_vram(vmw_priv,	575	} else if (!vmw_kms_validate_mode_vram(vmw_priv,
576	mode->hdisplay *	576	mode->hdisplay *
577	(var->bits_per_pixel + 7) / 8,	577	DIV_ROUND_UP(var->bits_per_pixel, 8),
578	mode->vdisplay)) {	578	mode->vdisplay)) {
579	drm_mode_destroy(vmw_priv->dev, mode);	579	drm_mode_destroy(vmw_priv->dev, mode);
580	return -EINVAL;	580	return -EINVAL;
581	}	581	}

drivers/i2c/busses/Kconfig+2−2

@@ -975,10 +975,10 @@ config I2C_XLR · 974 unmodified lines
975		975
976	config I2C_XLP9XX	976	config I2C_XLP9XX
977	tristate "XLP9XX I2C support"	977	tristate "XLP9XX I2C support"
978	depends on CPU_XLP \|\| COMPILE_TEST	978	depends on CPU_XLP \|\| ARCH_VULCAN \|\| COMPILE_TEST
979	help	979	help
980	This driver enables support for the on-chip I2C interface of	980	This driver enables support for the on-chip I2C interface of
981	the Broadcom XLP9xx/XLP5xx MIPS processors.	981	the Broadcom XLP9xx/XLP5xx MIPS and Vulcan ARM64 processors.
982		982
983	This driver can also be built as a module. If so, the module will	983	This driver can also be built as a module. If so, the module will
984	be called i2c-xlp9xx.	984	be called i2c-xlp9xx.

drivers/i2c/busses/i2c-cpm.c+2−2

@@ -116,8 +116,8 @@ struct cpm_i2c { · 115 unmodified lines
116	cbd_t __iomem *rbase;	116	cbd_t __iomem *rbase;
117	u_char *txbuf[CPM_MAXBD];	117	u_char *txbuf[CPM_MAXBD];
118	u_char *rxbuf[CPM_MAXBD];	118	u_char *rxbuf[CPM_MAXBD];
119	u32 txdma[CPM_MAXBD];	119	dma_addr_t txdma[CPM_MAXBD];
120	u32 rxdma[CPM_MAXBD];	120	dma_addr_t rxdma[CPM_MAXBD];
121	};	121	};
122		122
123	static irqreturn_t cpm_i2c_interrupt(int irq, void *dev_id)	123	static irqreturn_t cpm_i2c_interrupt(int irq, void *dev_id)

drivers/i2c/busses/i2c-exynos5.c+19−5

 		return -EIO;
 	}
-	clk_prepare_enable(i2c->clk);
+	ret = clk_enable(i2c->clk);
+	if (ret)
+		return ret;
 	for (i = 0; i < num; i++, msgs++) {
 		stop = (i == num - 1);
 	}
  out:
-	clk_disable_unprepare(i2c->clk);
+	clk_disable(i2c->clk);
 	return ret;
 }
 		return -ENOENT;
 	}
-	clk_prepare_enable(i2c->clk);
+	ret = clk_prepare_enable(i2c->clk);
+	if (ret)
+		return ret;
 	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	i2c->regs = devm_ioremap_resource(&pdev->dev, mem);
 	platform_set_drvdata(pdev, i2c);
+	clk_disable(i2c->clk);
+	return 0;
  err_clk:
 	clk_disable_unprepare(i2c->clk);
 	return ret;
 	i2c_del_adapter(&i2c->adap);
+	clk_unprepare(i2c->clk);
 	return 0;
 }
 	i2c->suspended = 1;
+	clk_unprepare(i2c->clk);
 	return 0;
 }
 	struct exynos5_i2c *i2c = platform_get_drvdata(pdev);
 	int ret = 0;
-	clk_prepare_enable(i2c->clk);
+	ret = clk_prepare_enable(i2c->clk);
+	if (ret)
+		return ret;
 	ret = exynos5_hsi2c_clock_setup(i2c);
 	if (ret) {
 	}
 	exynos5_i2c_init(i2c);
-	clk_disable_unprepare(i2c->clk);
+	clk_disable(i2c->clk);
 	i2c->suspended = 0;
 	return 0;

drivers/i2c/busses/i2c-ismt.c+2−0

 /* PCI DIDs for the Intel SMBus Message Transport (SMT) Devices */
 #define PCI_DEVICE_ID_INTEL_S1200_SMT0	0x0c59
 #define PCI_DEVICE_ID_INTEL_S1200_SMT1	0x0c5a
+#define PCI_DEVICE_ID_INTEL_DNV_SMT	0x19ac
 #define PCI_DEVICE_ID_INTEL_AVOTON_SMT	0x1f15
 #define ISMT_DESC_ENTRIES	2	/* number of descriptor entries */
 static const struct pci_device_id ismt_ids[] = {
 	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_S1200_SMT0) },
 	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_S1200_SMT1) },
+	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DNV_SMT) },
 	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_AVOTON_SMT) },
 	{ 0, }
 };

drivers/i2c/busses/i2c-rk3x.c+1−0

@@ -855,6 +855,7 @@ static struct rk3x_i2c_soc_data soc_data[3] = { · 854 unmodified lines
855	static const struct of_device_id rk3x_i2c_match[] = {	855	static const struct of_device_id rk3x_i2c_match[] = {
856	{ .compatible = "rockchip,rk3066-i2c", .data = (void *)&soc_data[0] },	856	{ .compatible = "rockchip,rk3066-i2c", .data = (void *)&soc_data[0] },
857	{ .compatible = "rockchip,rk3188-i2c", .data = (void *)&soc_data[1] },	857	{ .compatible = "rockchip,rk3188-i2c", .data = (void *)&soc_data[1] },
		858	{ .compatible = "rockchip,rk3228-i2c", .data = (void *)&soc_data[2] },
858	{ .compatible = "rockchip,rk3288-i2c", .data = (void *)&soc_data[2] },	859	{ .compatible = "rockchip,rk3288-i2c", .data = (void *)&soc_data[2] },
859	{},	860	{},
860	};	861	};

drivers/infiniband/core/cache.c+2−1

@@ -691,7 +691,8 @@ void ib_cache_gid_set_default_gid(struct ib_device *ib_dev, u8 port, · 690 unmodified lines
691	NULL);	691	NULL);
692		692
693	/* Coudn't find default GID location */	693	/* Coudn't find default GID location */
694	WARN_ON(ix < 0);	694	if (WARN_ON(ix < 0))
		695	goto release;
695		696
696	zattr_type.gid_type = gid_type;	697	zattr_type.gid_type = gid_type;
697		698

drivers/infiniband/core/ucm.c+4−0

 #include <asm/uaccess.h>
+#include <rdma/ib.h>
 #include <rdma/ib_cm.h>
 #include <rdma/ib_user_cm.h>
 #include <rdma/ib_marshall.h>
 	struct ib_ucm_cmd_hdr hdr;
 	ssize_t result;
+	if (WARN_ON_ONCE(!ib_safe_file_access(filp)))
+		return -EACCES;
 	if (len < sizeof(hdr))
 		return -EINVAL;

drivers/infiniband/core/ucma.c+3−0

@@ -1574,6 +1574,9 @@ static ssize_t ucma_write(struct file filp, const char __user buf, · 1573 unmodified lines
1574	struct rdma_ucm_cmd_hdr hdr;	1574	struct rdma_ucm_cmd_hdr hdr;
1575	ssize_t ret;	1575	ssize_t ret;
1576		1576
		1577	if (WARN_ON_ONCE(!ib_safe_file_access(filp)))
		1578	return -EACCES;
		1579
1577	if (len < sizeof(hdr))	1580	if (len < sizeof(hdr))
1578	return -EINVAL;	1581	return -EINVAL;
1579		1582

drivers/infiniband/core/uverbs_main.c+5−0

 #include <asm/uaccess.h>
+#include <rdma/ib.h>
 #include "uverbs.h"
 MODULE_AUTHOR("Roland Dreier");
 	int srcu_key;
 	ssize_t ret;
+	if (WARN_ON_ONCE(!ib_safe_file_access(filp)))
+		return -EACCES;
 	if (count < sizeof hdr)
 		return -EINVAL;

drivers/infiniband/core/verbs.c+2−1

@@ -1860,6 +1860,7 @@ EXPORT_SYMBOL(ib_drain_rq); · 1859 unmodified lines
1860	void ib_drain_qp(struct ib_qp *qp)	1860	void ib_drain_qp(struct ib_qp *qp)
1861	{	1861	{
1862	ib_drain_sq(qp);	1862	ib_drain_sq(qp);
1863	ib_drain_rq(qp);	1863	if (!qp->srq)
		1864	ib_drain_rq(qp);
1864	}	1865	}
1865	EXPORT_SYMBOL(ib_drain_qp);	1866	EXPORT_SYMBOL(ib_drain_qp);

drivers/infiniband/hw/cxgb3/iwch_provider.c+2−0

@@ -1390,6 +1390,8 @@ int iwch_register_device(struct iwch_dev *dev) · 1389 unmodified lines
1390	dev->ibdev.iwcm->add_ref = iwch_qp_add_ref;	1390	dev->ibdev.iwcm->add_ref = iwch_qp_add_ref;
1391	dev->ibdev.iwcm->rem_ref = iwch_qp_rem_ref;	1391	dev->ibdev.iwcm->rem_ref = iwch_qp_rem_ref;
1392	dev->ibdev.iwcm->get_qp = iwch_get_qp;	1392	dev->ibdev.iwcm->get_qp = iwch_get_qp;
		1393	memcpy(dev->ibdev.iwcm->ifname, dev->rdev.t3cdev_p->lldev->name,
		1394	sizeof(dev->ibdev.iwcm->ifname));
1393		1395
1394	ret = ib_register_device(&dev->ibdev, NULL);	1396	ret = ib_register_device(&dev->ibdev, NULL);
1395	if (ret)	1397	if (ret)

drivers/infiniband/hw/cxgb4/cq.c+1−1

@@ -162,7 +162,7 @@ static int create_cq(struct c4iw_rdev rdev, struct t4_cq cq, · 161 unmodified lines
162	cq->bar2_va = c4iw_bar2_addrs(rdev, cq->cqid, T4_BAR2_QTYPE_INGRESS,	162	cq->bar2_va = c4iw_bar2_addrs(rdev, cq->cqid, T4_BAR2_QTYPE_INGRESS,
163	&cq->bar2_qid,	163	&cq->bar2_qid,
164	user ? &cq->bar2_pa : NULL);	164	user ? &cq->bar2_pa : NULL);
165	if (user && !cq->bar2_va) {	165	if (user && !cq->bar2_pa) {
166	pr_warn(MOD "%s: cqid %u not in BAR2 range.\n",	166	pr_warn(MOD "%s: cqid %u not in BAR2 range.\n",
167	pci_name(rdev->lldi.pdev), cq->cqid);	167	pci_name(rdev->lldi.pdev), cq->cqid);
168	ret = -EINVAL;	168	ret = -EINVAL;

drivers/infiniband/hw/cxgb4/provider.c+2−0

@@ -580,6 +580,8 @@ int c4iw_register_device(struct c4iw_dev *dev) · 579 unmodified lines
580	dev->ibdev.iwcm->add_ref = c4iw_qp_add_ref;	580	dev->ibdev.iwcm->add_ref = c4iw_qp_add_ref;
581	dev->ibdev.iwcm->rem_ref = c4iw_qp_rem_ref;	581	dev->ibdev.iwcm->rem_ref = c4iw_qp_rem_ref;
582	dev->ibdev.iwcm->get_qp = c4iw_get_qp;	582	dev->ibdev.iwcm->get_qp = c4iw_get_qp;
		583	memcpy(dev->ibdev.iwcm->ifname, dev->rdev.lldi.ports[0]->name,
		584	sizeof(dev->ibdev.iwcm->ifname));
583		585
584	ret = ib_register_device(&dev->ibdev, NULL);	586	ret = ib_register_device(&dev->ibdev, NULL);
585	if (ret)	587	if (ret)

drivers/infiniband/hw/cxgb4/qp.c+21−3

 	if (pbar2_pa)
 		*pbar2_pa = (rdev->bar2_pa + bar2_qoffset) & PAGE_MASK;
+	if (is_t4(rdev->lldi.adapter_type))
+		return NULL;
 	return rdev->bar2_kva + bar2_qoffset;
 }
 	/*
 	 * User mode must have bar2 access.
 	 */
-	if (user && (!wq->sq.bar2_va || !wq->rq.bar2_va)) {
+	if (user && (!wq->sq.bar2_pa || !wq->rq.bar2_pa)) {
 		pr_warn(MOD "%s: sqid %u or rqid %u not in BAR2 range.\n",
 			pci_name(rdev->lldi.pdev), wq->sq.qid, wq->rq.qid);
 		goto free_dma;
 void c4iw_drain_sq(struct ib_qp *ibqp)
 {
 	struct c4iw_qp *qp = to_c4iw_qp(ibqp);
+	unsigned long flag;
+	bool need_to_wait;
-	wait_for_completion(&qp->sq_drained);
+	spin_lock_irqsave(&qp->lock, flag);
+	need_to_wait = !t4_sq_empty(&qp->wq);
+	spin_unlock_irqrestore(&qp->lock, flag);
+	if (need_to_wait)
+		wait_for_completion(&qp->sq_drained);
 }
 void c4iw_drain_rq(struct ib_qp *ibqp)
 {
 	struct c4iw_qp *qp = to_c4iw_qp(ibqp);
+	unsigned long flag;
+	bool need_to_wait;
+	spin_lock_irqsave(&qp->lock, flag);
+	need_to_wait = !t4_rq_empty(&qp->wq);
+	spin_unlock_irqrestore(&qp->lock, flag);
-	wait_for_completion(&qp->rq_drained);
+	if (need_to_wait)
+		wait_for_completion(&qp->rq_drained);
 }

drivers/infiniband/hw/mlx5/main.c+3−3

@@ -530,7 +530,7 @@ static int mlx5_ib_query_device(struct ib_device *ibdev, · 529 unmodified lines
530	sizeof(struct mlx5_wqe_ctrl_seg)) /	530	sizeof(struct mlx5_wqe_ctrl_seg)) /
531	sizeof(struct mlx5_wqe_data_seg);	531	sizeof(struct mlx5_wqe_data_seg);
532	props->max_sge = min(max_rq_sg, max_sq_sg);	532	props->max_sge = min(max_rq_sg, max_sq_sg);
533	props->max_sge_rd = props->max_sge;	533	props->max_sge_rd = MLX5_MAX_SGE_RD;
534	props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq);	534	props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
535	props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1;	535	props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1;
536	props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);	536	props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
@@ -671,8 +671,8 @@ static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port, · 134 unmodified lines
671	struct mlx5_ib_dev *dev = to_mdev(ibdev);	671	struct mlx5_ib_dev *dev = to_mdev(ibdev);
672	struct mlx5_core_dev *mdev = dev->mdev;	672	struct mlx5_core_dev *mdev = dev->mdev;
673	struct mlx5_hca_vport_context *rep;	673	struct mlx5_hca_vport_context *rep;
674	int max_mtu;	674	u16 max_mtu;
675	int oper_mtu;	675	u16 oper_mtu;
676	int err;	676	int err;
677	u8 ib_link_width_oper;	677	u8 ib_link_width_oper;
678	u8 vl_hw_cap;	678	u8 vl_hw_cap;

drivers/infiniband/hw/nes/nes_nic.c+0−3

@@ -500,9 +500,6 @@ static int nes_netdev_start_xmit(struct sk_buff skb, struct net_device netdev) · 499 unmodified lines
500	* skb_shinfo(skb)->nr_frags, skb_is_gso(skb));	500	* skb_shinfo(skb)->nr_frags, skb_is_gso(skb));
501	*/	501	*/
502		502
503	if (!netif_carrier_ok(netdev))
504	return NETDEV_TX_OK;
505
506	if (netif_queue_stopped(netdev))	503	if (netif_queue_stopped(netdev))
507	return NETDEV_TX_BUSY;	504	return NETDEV_TX_BUSY;
508		505

drivers/infiniband/hw/qib/qib_file_ops.c+5−0

 #include <linux/export.h>
 #include <linux/uio.h>
+#include <rdma/ib.h>
 #include "qib.h"
 #include "qib_common.h"
 #include "qib_user_sdma.h"
 	ssize_t ret = 0;
 	void *dest;
+	if (WARN_ON_ONCE(!ib_safe_file_access(fp)))
+		return -EACCES;
 	if (count < sizeof(cmd.type)) {
 		ret = -EINVAL;
 		goto bail;

drivers/infiniband/sw/rdmavt/qp.c+2−2

 	spin_unlock_irqrestore(&qp->s_hlock, flags);
 	if (nreq) {
 		if (call_send)
-			rdi->driver_f.schedule_send_no_lock(qp);
-		else
 			rdi->driver_f.do_send(qp);
+		else
+			rdi->driver_f.schedule_send_no_lock(qp);
 	}
 	return err;
 }

drivers/media/usb/usbvision/usbvision-video.c+0−7

@@ -1452,13 +1452,6 @@ static int usbvision_probe(struct usb_interface *intf, · 1451 unmodified lines
1452	printk(KERN_INFO "%s: %s found\n", __func__,	1452	printk(KERN_INFO "%s: %s found\n", __func__,
1453	usbvision_device_data[model].model_string);	1453	usbvision_device_data[model].model_string);
1454		1454
1455	/*
1456	* this is a security check.
1457	* an exploit using an incorrect bInterfaceNumber is known
1458	*/
1459	if (ifnum >= USB_MAXINTERFACES \|\| !dev->actconfig->interface[ifnum])
1460	return -ENODEV;
1461
1462	if (usbvision_device_data[model].interface >= 0)	1455	if (usbvision_device_data[model].interface >= 0)
1463	interface = &dev->actconfig->interface[usbvision_device_data[model].interface]->altsetting[0];	1456	interface = &dev->actconfig->interface[usbvision_device_data[model].interface]->altsetting[0];
1464	else if (ifnum < dev->actconfig->desc.bNumInterfaces)	1457	else if (ifnum < dev->actconfig->desc.bNumInterfaces)

drivers/media/v4l2-core/videobuf2-core.c+15−5

  * Will sleep if required for nonblocking == false.
  */
 static int __vb2_get_done_vb(struct vb2_queue *q, struct vb2_buffer **vb,
-				int nonblocking)
+			     void *pb, int nonblocking)
 {
 	unsigned long flags;
 	int ret;
 	/*
 	 * Only remove the buffer from done_list if v4l2_buffer can handle all
 	 * the planes.
-	 * Verifying planes is NOT necessary since it already has been checked
-	 * before the buffer is queued/prepared. So it can never fail.
 	 */
-	list_del(&(*vb)->done_entry);
+	ret = call_bufop(q, verify_planes_array, *vb, pb);
+	if (!ret)
+		list_del(&(*vb)->done_entry);
 	spin_unlock_irqrestore(&q->done_lock, flags);
 	return ret;
 	struct vb2_buffer *vb = NULL;
 	int ret;
-	ret = __vb2_get_done_vb(q, &vb, nonblocking);
+	ret = __vb2_get_done_vb(q, &vb, pb, nonblocking);
 	if (ret < 0)
 		return ret;
 	if (!vb2_is_streaming(q) || q->error)
 		return POLLERR;
+	/*
+	 * If this quirk is set and QBUF hasn't been called yet then
+	 * return POLLERR as well. This only affects capture queues, output
+	 * queues will always initialize waiting_for_buffers to false.
+	 * This quirk is set by V4L2 for backwards compatibility reasons.
+	 */
+	if (q->quirk_poll_must_check_waiting_for_buffers &&
+	    q->waiting_for_buffers && (req_events & (POLLIN | POLLRDNORM)))
+		return POLLERR;
 	/*
 	 * For output streams you can call write() as long as there are fewer
 	 * buffers queued than there are buffers available.

drivers/media/v4l2-core/videobuf2-memops.c+1−1

@@ -49,7 +49,7 @@ struct frame_vector *vb2_create_framevec(unsigned long start, · 48 unmodified lines
49	vec = frame_vector_create(nr);	49	vec = frame_vector_create(nr);
50	if (!vec)	50	if (!vec)
51	return ERR_PTR(-ENOMEM);	51	return ERR_PTR(-ENOMEM);
52	ret = get_vaddr_frames(start, nr, write, 1, vec);	52	ret = get_vaddr_frames(start & PAGE_MASK, nr, write, true, vec);
53	if (ret < 0)	53	if (ret < 0)
54	goto out_destroy;	54	goto out_destroy;
55	/* We accept only complete set of PFNs */	55	/* We accept only complete set of PFNs */

drivers/media/v4l2-core/videobuf2-v4l2.c+12−8

 	return 0;
 }
+static int __verify_planes_array_core(struct vb2_buffer *vb, const void *pb)
+{
+	return __verify_planes_array(vb, pb);
+}
 /**
  * __verify_length() - Verify that the bytesused value for each plane fits in
  * the plane length and that the data offset doesn't exceed the bytesused value.
 }
 static const struct vb2_buf_ops v4l2_buf_ops = {
+	.verify_planes_array	= __verify_planes_array_core,
 	.fill_user_buffer	= __fill_v4l2_buffer,
 	.fill_vb2_buffer	= __fill_vb2_buffer,
 	.copy_timestamp		= __copy_timestamp,
 	q->is_output = V4L2_TYPE_IS_OUTPUT(q->type);
 	q->copy_timestamp = (q->timestamp_flags & V4L2_BUF_FLAG_TIMESTAMP_MASK)
 			== V4L2_BUF_FLAG_TIMESTAMP_COPY;
+	/*
+	 * For compatibility with vb1: if QBUF hasn't been called yet, then
+	 * return POLLERR as well. This only affects capture queues, output
+	 * queues will always initialize waiting_for_buffers to false.
+	 */
+	q->quirk_poll_must_check_waiting_for_buffers = true;
 	return vb2_core_queue_init(q);
 }
 			poll_wait(file, &fh->wait, wait);
 	}
-	/*
-	 * For compatibility with vb1: if QBUF hasn't been called yet, then
-	 * return POLLERR as well. This only affects capture queues, output
-	 * queues will always initialize waiting_for_buffers to false.
-	 */
-	if (q->waiting_for_buffers && (req_events & (POLLIN | POLLRDNORM)))
-		return POLLERR;
 	return res | vb2_core_poll(q, file, wait);
 }
 EXPORT_SYMBOL_GPL(vb2_poll);

drivers/misc/cxl/context.c+7−0

@@ -223,6 +223,13 @@ int __detach_context(struct cxl_context *ctx) · 222 unmodified lines
223	cxl_ops->link_ok(ctx->afu->adapter, ctx->afu));	223	cxl_ops->link_ok(ctx->afu->adapter, ctx->afu));
224	flush_work(&ctx->fault_work); /* Only needed for dedicated process */	224	flush_work(&ctx->fault_work); /* Only needed for dedicated process */
225		225
		226	/*
		227	* Wait until no further interrupts are presented by the PSL
		228	* for this context.
		229	*/
		230	if (cxl_ops->irq_wait)
		231	cxl_ops->irq_wait(ctx);
		232
226	/* release the reference to the group leader and mm handling pid */	233	/* release the reference to the group leader and mm handling pid */
227	put_pid(ctx->pid);	234	put_pid(ctx->pid);
228	put_pid(ctx->glpid);	235	put_pid(ctx->glpid);

drivers/misc/cxl/cxl.h+2−0

 #define CXL_PSL_DSISR_An_PE (1ull << (63-4))  /* PSL Error (implementation specific) */
 #define CXL_PSL_DSISR_An_AE (1ull << (63-5))  /* AFU Error */
 #define CXL_PSL_DSISR_An_OC (1ull << (63-6))  /* OS Context Warning */
+#define CXL_PSL_DSISR_PENDING (CXL_PSL_DSISR_TRANS | CXL_PSL_DSISR_An_PE | CXL_PSL_DSISR_An_AE | CXL_PSL_DSISR_An_OC)
 /* NOTE: Bits 32:63 are undefined if DSISR[DS] = 1 */
 #define CXL_PSL_DSISR_An_M  DSISR_NOHPTE      /* PTE not found */
 #define CXL_PSL_DSISR_An_P  DSISR_PROTFAULT   /* Storage protection violation */
 					u64 dsisr, u64 errstat);
 	irqreturn_t (*psl_interrupt)(int irq, void *data);
 	int (*ack_irq)(struct cxl_context *ctx, u64 tfc, u64 psl_reset_mask);
+	void (*irq_wait)(struct cxl_context *ctx);
 	int (*attach_process)(struct cxl_context *ctx, bool kernel,
 			u64 wed, u64 amr);
 	int (*detach_process)(struct cxl_context *ctx);

drivers/misc/cxl/irq.c+0−1

@@ -203,7 +203,6 @@ unsigned int cxl_map_irq(struct cxl *adapter, irq_hw_number_t hwirq, · 202 unmodified lines
203	void cxl_unmap_irq(unsigned int virq, void *cookie)	203	void cxl_unmap_irq(unsigned int virq, void *cookie)
204	{	204	{
205	free_irq(virq, cookie);	205	free_irq(virq, cookie);
206	irq_dispose_mapping(virq);
207	}	206	}
208		207
209	int cxl_register_one_irq(struct cxl *adapter,	208	int cxl_register_one_irq(struct cxl *adapter,

drivers/misc/cxl/native.c+31−0

@@ -14,6 +14,7 @@ · 13 unmodified lines
14	#include <linux/mutex.h>	14	#include <linux/mutex.h>
15	#include <linux/mm.h>	15	#include <linux/mm.h>
16	#include <linux/uaccess.h>	16	#include <linux/uaccess.h>
		17	#include <linux/delay.h>
17	#include <asm/synch.h>	18	#include <asm/synch.h>
18	#include <misc/cxl-base.h>	19	#include <misc/cxl-base.h>
19		20
@@ -797,6 +798,35 @@ static irqreturn_t native_irq_multiplexed(int irq, void *data) · 777 unmodified lines
797	return fail_psl_irq(afu, &irq_info);	798	return fail_psl_irq(afu, &irq_info);
798	}	799	}
799		800
		801	void native_irq_wait(struct cxl_context *ctx)
		802	{
		803	u64 dsisr;
		804	int timeout = 1000;
		805	int ph;
		806
		807	/*
		808	* Wait until no further interrupts are presented by the PSL
		809	* for this context.
		810	*/
		811	while (timeout--) {
		812	ph = cxl_p2n_read(ctx->afu, CXL_PSL_PEHandle_An) & 0xffff;
		813	if (ph != ctx->pe)
		814	return;
		815	dsisr = cxl_p2n_read(ctx->afu, CXL_PSL_DSISR_An);
		816	if ((dsisr & CXL_PSL_DSISR_PENDING) == 0)
		817	return;
		818	/*
		819	* We are waiting for the workqueue to process our
		820	* irq, so need to let that run here.
		821	*/
		822	msleep(1);
		823	}
		824
		825	dev_warn(&ctx->afu->dev, "WARNING: waiting on DSI for PE %i"
		826	" DSISR %016llx!\n", ph, dsisr);
		827	return;
		828	}
		829
800	static irqreturn_t native_slice_irq_err(int irq, void *data)	830	static irqreturn_t native_slice_irq_err(int irq, void *data)
801	{	831	{
802	struct cxl_afu *afu = data;	832	struct cxl_afu *afu = data;
@@ -1076,6 +1106,7 @@ const struct cxl_backend_ops cxl_native_ops = { · 273 unmodified lines
1076	.handle_psl_slice_error = native_handle_psl_slice_error,	1106	.handle_psl_slice_error = native_handle_psl_slice_error,
1077	.psl_interrupt = NULL,	1107	.psl_interrupt = NULL,
1078	.ack_irq = native_ack_irq,	1108	.ack_irq = native_ack_irq,
		1109	.irq_wait = native_irq_wait,
1079	.attach_process = native_attach_process,	1110	.attach_process = native_attach_process,
1080	.detach_process = native_detach_process,	1111	.detach_process = native_detach_process,
1081	.support_attributes = native_support_attributes,	1112	.support_attributes = native_support_attributes,

drivers/mmc/host/Kconfig+1−0

@@ -97,6 +97,7 @@ config MMC_RICOH_MMC · 96 unmodified lines
97	config MMC_SDHCI_ACPI	97	config MMC_SDHCI_ACPI
98	tristate "SDHCI support for ACPI enumerated SDHCI controllers"	98	tristate "SDHCI support for ACPI enumerated SDHCI controllers"
99	depends on MMC_SDHCI && ACPI	99	depends on MMC_SDHCI && ACPI
		100	select IOSF_MBI if X86
100	help	101	help
101	This selects support for ACPI enumerated SDHCI controllers,	102	This selects support for ACPI enumerated SDHCI controllers,
102	identified by ACPI Compatibility ID PNP0D40 or specific	103	identified by ACPI Compatibility ID PNP0D40 or specific

drivers/mmc/host/sdhci-acpi.c+81−0

@@ -41,6 +41,11 @@ · 40 unmodified lines
41	#include <linux/mmc/pm.h>	41	#include <linux/mmc/pm.h>
42	#include <linux/mmc/slot-gpio.h>	42	#include <linux/mmc/slot-gpio.h>
43		43
		44	#ifdef CONFIG_X86
		45	#include <asm/cpu_device_id.h>
		46	#include <asm/iosf_mbi.h>
		47	#endif
		48
44	#include "sdhci.h"	49	#include "sdhci.h"
45		50
46	enum {	51	enum {
@@ -116,6 +121,75 @@ static const struct sdhci_acpi_chip sdhci_acpi_chip_int = { · 69 unmodified lines
116	.ops = &sdhci_acpi_ops_int,	121	.ops = &sdhci_acpi_ops_int,
117	};	122	};
118		123
		124	#ifdef CONFIG_X86
		125
		126	static bool sdhci_acpi_byt(void)
		127	{
		128	static const struct x86_cpu_id byt[] = {
		129	{ X86_VENDOR_INTEL, 6, 0x37 },
		130	{}
		131	};
		132
		133	return x86_match_cpu(byt);
		134	}
		135
		136	#define BYT_IOSF_SCCEP 0x63
		137	#define BYT_IOSF_OCP_NETCTRL0 0x1078
		138	#define BYT_IOSF_OCP_TIMEOUT_BASE GENMASK(10, 8)
		139
		140	static void sdhci_acpi_byt_setting(struct device *dev)
		141	{
		142	u32 val = 0;
		143
		144	if (!sdhci_acpi_byt())
		145	return;
		146
		147	if (iosf_mbi_read(BYT_IOSF_SCCEP, MBI_CR_READ, BYT_IOSF_OCP_NETCTRL0,
		148	&val)) {
		149	dev_err(dev, "%s read error\n", __func__);
		150	return;
		151	}
		152
		153	if (!(val & BYT_IOSF_OCP_TIMEOUT_BASE))
		154	return;
		155
		156	val &= ~BYT_IOSF_OCP_TIMEOUT_BASE;
		157
		158	if (iosf_mbi_write(BYT_IOSF_SCCEP, MBI_CR_WRITE, BYT_IOSF_OCP_NETCTRL0,
		159	val)) {
		160	dev_err(dev, "%s write error\n", __func__);
		161	return;
		162	}
		163
		164	dev_dbg(dev, "%s completed\n", __func__);
		165	}
		166
		167	static bool sdhci_acpi_byt_defer(struct device *dev)
		168	{
		169	if (!sdhci_acpi_byt())
		170	return false;
		171
		172	if (!iosf_mbi_available())
		173	return true;
		174
		175	sdhci_acpi_byt_setting(dev);
		176
		177	return false;
		178	}
		179
		180	#else
		181
		182	static inline void sdhci_acpi_byt_setting(struct device *dev)
		183	{
		184	}
		185
		186	static inline bool sdhci_acpi_byt_defer(struct device *dev)
		187	{
		188	return false;
		189	}
		190
		191	#endif
		192
119	static int bxt_get_cd(struct mmc_host *mmc)	193	static int bxt_get_cd(struct mmc_host *mmc)
120	{	194	{
121	int gpio_cd = mmc_gpio_get_cd(mmc);	195	int gpio_cd = mmc_gpio_get_cd(mmc);
@@ -322,6 +396,9 @@ static int sdhci_acpi_probe(struct platform_device *pdev) · 200 unmodified lines
322	if (acpi_bus_get_status(device) \|\| !device->status.present)	396	if (acpi_bus_get_status(device) \|\| !device->status.present)
323	return -ENODEV;	397	return -ENODEV;
324		398
		399	if (sdhci_acpi_byt_defer(dev))
		400	return -EPROBE_DEFER;
		401
325	hid = acpi_device_hid(device);	402	hid = acpi_device_hid(device);
326	uid = device->pnp.unique_id;	403	uid = device->pnp.unique_id;
327		404
@@ -447,6 +524,8 @@ static int sdhci_acpi_resume(struct device *dev) · 119 unmodified lines
447	{	524	{
448	struct sdhci_acpi_host *c = dev_get_drvdata(dev);	525	struct sdhci_acpi_host *c = dev_get_drvdata(dev);
449		526
		527	sdhci_acpi_byt_setting(&c->pdev->dev);
		528
450	return sdhci_resume_host(c->host);	529	return sdhci_resume_host(c->host);
451	}	530	}
452		531
@@ -470,6 +549,8 @@ static int sdhci_acpi_runtime_resume(struct device *dev) · 17 unmodified lines
470	{	549	{
471	struct sdhci_acpi_host *c = dev_get_drvdata(dev);	550	struct sdhci_acpi_host *c = dev_get_drvdata(dev);
472		551
		552	sdhci_acpi_byt_setting(&c->pdev->dev);
		553
473	return sdhci_runtime_resume_host(c->host);	554	return sdhci_runtime_resume_host(c->host);
474	}	555	}
475		556

drivers/mmc/host/sunxi-mmc.c+5−0

 				  MMC_CAP_1_8V_DDR |
 				  MMC_CAP_ERASE | MMC_CAP_SDIO_IRQ;
+	/* TODO MMC DDR is not working on A80 */
+	if (of_device_is_compatible(pdev->dev.of_node,
+				    "allwinner,sun9i-a80-mmc"))
+		mmc->caps &= ~MMC_CAP_1_8V_DDR;
 	ret = mmc_of_parse(mmc);
 	if (ret)
 		goto error_free_dma;

drivers/net/Kconfig+2−3

 	  this device is consigned into oblivion) with a configurable IP
 	  address. It is most commonly used in order to make your currently
 	  inactive SLIP address seem like a real address for local programs.
-	  If you use SLIP or PPP, you might want to say Y here. Since this
+	  If you use SLIP or PPP, you might want to say Y here. It won't
-	  thing often comes in handy, the default is Y. It won't enlarge your
+	  enlarge your kernel. What a deal. Read about it in the Network
-	  kernel either. What a deal. Read about it in the Network
 	  Administrator's Guide, available from
 	  <http://www.tldp.org/docs.html#guide>.

drivers/net/ethernet/mellanox/mlx4/en_tx.c+4−2

@@ -405,7 +405,6 @@ static bool mlx4_en_process_tx_cq(struct net_device *dev, · 404 unmodified lines
405	u32 packets = 0;	405	u32 packets = 0;
406	u32 bytes = 0;	406	u32 bytes = 0;
407	int factor = priv->cqe_factor;	407	int factor = priv->cqe_factor;
408	u64 timestamp = 0;
409	int done = 0;	408	int done = 0;
410	int budget = priv->tx_work_limit;	409	int budget = priv->tx_work_limit;
411	u32 last_nr_txbb;	410	u32 last_nr_txbb;
@@ -445,9 +444,12 @@ static bool mlx4_en_process_tx_cq(struct net_device *dev, · 33 unmodified lines
445	new_index = be16_to_cpu(cqe->wqe_index) & size_mask;	444	new_index = be16_to_cpu(cqe->wqe_index) & size_mask;
446		445
447	do {	446	do {
		447	u64 timestamp = 0;
		448
448	txbbs_skipped += last_nr_txbb;	449	txbbs_skipped += last_nr_txbb;
449	ring_index = (ring_index + last_nr_txbb) & size_mask;	450	ring_index = (ring_index + last_nr_txbb) & size_mask;
450	if (ring->tx_info[ring_index].ts_requested)	451
		452	if (unlikely(ring->tx_info[ring_index].ts_requested))
451	timestamp = mlx4_en_get_cqe_ts(cqe);	453	timestamp = mlx4_en_get_cqe_ts(cqe);
452		454
453	/* free next descriptor */	455	/* free next descriptor */

drivers/net/ethernet/mellanox/mlx5/core/en.h+1−1

@@ -609,7 +609,7 @@ enum mlx5e_link_mode { · 608 unmodified lines
609	MLX5E_100GBASE_KR4 = 22,	609	MLX5E_100GBASE_KR4 = 22,
610	MLX5E_100GBASE_LR4 = 23,	610	MLX5E_100GBASE_LR4 = 23,
611	MLX5E_100BASE_TX = 24,	611	MLX5E_100BASE_TX = 24,
612	MLX5E_100BASE_T = 25,	612	MLX5E_1000BASE_T = 25,
613	MLX5E_10GBASE_T = 26,	613	MLX5E_10GBASE_T = 26,
614	MLX5E_25GBASE_CR = 27,	614	MLX5E_25GBASE_CR = 27,
615	MLX5E_25GBASE_KR = 28,	615	MLX5E_25GBASE_KR = 28,

drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c+4−4

@@ -138,10 +138,10 @@ static const struct { · 137 unmodified lines
138	[MLX5E_100BASE_TX] = {	138	[MLX5E_100BASE_TX] = {
139	.speed = 100,	139	.speed = 100,
140	},	140	},
141	[MLX5E_100BASE_T] = {	141	[MLX5E_1000BASE_T] = {
142	.supported = SUPPORTED_100baseT_Full,	142	.supported = SUPPORTED_1000baseT_Full,
143	.advertised = ADVERTISED_100baseT_Full,	143	.advertised = ADVERTISED_1000baseT_Full,
144	.speed = 100,	144	.speed = 1000,
145	},	145	},
146	[MLX5E_10GBASE_T] = {	146	[MLX5E_10GBASE_T] = {
147	.supported = SUPPORTED_10000baseT_Full,	147	.supported = SUPPORTED_10000baseT_Full,

drivers/net/ethernet/mellanox/mlx5/core/en_main.c+57−15

@@ -1404,24 +1404,50 @@ static int mlx5e_refresh_tirs_self_loopback_enable(struct mlx5e_priv *priv) · 1403 unmodified lines
1404	return 0;	1404	return 0;
1405	}	1405	}
1406		1406
1407	static int mlx5e_set_dev_port_mtu(struct net_device *netdev)	1407	static int mlx5e_set_mtu(struct mlx5e_priv *priv, u16 mtu)
1408	{	1408	{
1409	struct mlx5e_priv *priv = netdev_priv(netdev);
1410	struct mlx5_core_dev *mdev = priv->mdev;	1409	struct mlx5_core_dev *mdev = priv->mdev;
1411	int hw_mtu;	1410	u16 hw_mtu = MLX5E_SW2HW_MTU(mtu);
1412	int err;	1411	int err;
1413		1412
1414	err = mlx5_set_port_mtu(mdev, MLX5E_SW2HW_MTU(netdev->mtu), 1);	1413	err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
1415	if (err)	1414	if (err)
1416	return err;	1415	return err;
1417		1416
1418	mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);	1417	/* Update vport context MTU */
		1418	mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
		1419	return 0;
		1420	}
1419		1421
1420	if (MLX5E_HW2SW_MTU(hw_mtu) != netdev->mtu)	1422	static void mlx5e_query_mtu(struct mlx5e_priv priv, u16 mtu)
1421	netdev_warn(netdev, "%s: Port MTU %d is different than netdev mtu %d\n",	1423	{
1422	__func__, MLX5E_HW2SW_MTU(hw_mtu), netdev->mtu);	1424	struct mlx5_core_dev *mdev = priv->mdev;
		1425	u16 hw_mtu = 0;
		1426	int err;
1423		1427
1424	netdev->mtu = MLX5E_HW2SW_MTU(hw_mtu);	1428	err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
		1429	if (err \|\| !hw_mtu) /* fallback to port oper mtu */
		1430	mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
		1431
		1432	*mtu = MLX5E_HW2SW_MTU(hw_mtu);
		1433	}
		1434
		1435	static int mlx5e_set_dev_port_mtu(struct net_device *netdev)
		1436	{
		1437	struct mlx5e_priv *priv = netdev_priv(netdev);
		1438	u16 mtu;
		1439	int err;
		1440
		1441	err = mlx5e_set_mtu(priv, netdev->mtu);
		1442	if (err)
		1443	return err;
		1444
		1445	mlx5e_query_mtu(priv, &mtu);
		1446	if (mtu != netdev->mtu)
		1447	netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
		1448	__func__, mtu, netdev->mtu);
		1449
		1450	netdev->mtu = mtu;
1425	return 0;	1451	return 0;
1426	}	1452	}
1427		1453
@@ -1999,22 +2025,27 @@ static int mlx5e_set_features(struct net_device *netdev, · 571 unmodified lines
1999	return err;	2025	return err;
2000	}	2026	}
2001		2027
		2028	#define MXL5_HW_MIN_MTU 64
		2029	#define MXL5E_MIN_MTU (MXL5_HW_MIN_MTU + ETH_FCS_LEN)
		2030
2002	static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu)	2031	static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu)
2003	{	2032	{
2004	struct mlx5e_priv *priv = netdev_priv(netdev);	2033	struct mlx5e_priv *priv = netdev_priv(netdev);
2005	struct mlx5_core_dev *mdev = priv->mdev;	2034	struct mlx5_core_dev *mdev = priv->mdev;
2006	bool was_opened;	2035	bool was_opened;
2007	int max_mtu;	2036	u16 max_mtu;
		2037	u16 min_mtu;
2008	int err = 0;	2038	int err = 0;
2009		2039
2010	mlx5_query_port_max_mtu(mdev, &max_mtu, 1);	2040	mlx5_query_port_max_mtu(mdev, &max_mtu, 1);
2011		2041
2012	max_mtu = MLX5E_HW2SW_MTU(max_mtu);	2042	max_mtu = MLX5E_HW2SW_MTU(max_mtu);
		2043	min_mtu = MLX5E_HW2SW_MTU(MXL5E_MIN_MTU);
2013		2044
2014	if (new_mtu > max_mtu) {	2045	if (new_mtu > max_mtu \|\| new_mtu < min_mtu) {
2015	netdev_err(netdev,	2046	netdev_err(netdev,
2016	"%s: Bad MTU (%d) > (%d) Max\n",	2047	"%s: Bad MTU (%d), valid range is: [%d..%d]\n",
2017	__func__, new_mtu, max_mtu);	2048	__func__, new_mtu, min_mtu, max_mtu);
2018	return -EINVAL;	2049	return -EINVAL;
2019	}	2050	}
2020		2051
@@ -2602,7 +2633,16 @@ static void mlx5e_destroy_netdev(struct mlx5_core_dev mdev, void vpriv) · 581 unmodified lines
2602	schedule_work(&priv->set_rx_mode_work);	2633	schedule_work(&priv->set_rx_mode_work);
2603	mlx5e_disable_async_events(priv);	2634	mlx5e_disable_async_events(priv);
2604	flush_scheduled_work();	2635	flush_scheduled_work();
2605	unregister_netdev(netdev);	2636	if (test_bit(MLX5_INTERFACE_STATE_SHUTDOWN, &mdev->intf_state)) {
		2637	netif_device_detach(netdev);
		2638	mutex_lock(&priv->state_lock);
		2639	if (test_bit(MLX5E_STATE_OPENED, &priv->state))
		2640	mlx5e_close_locked(netdev);
		2641	mutex_unlock(&priv->state_lock);
		2642	} else {
		2643	unregister_netdev(netdev);
		2644	}
		2645
2606	mlx5e_tc_cleanup(priv);	2646	mlx5e_tc_cleanup(priv);
2607	mlx5e_vxlan_cleanup(priv);	2647	mlx5e_vxlan_cleanup(priv);
2608	mlx5e_destroy_flow_tables(priv);	2648	mlx5e_destroy_flow_tables(priv);
@@ -2615,7 +2655,9 @@ static void mlx5e_destroy_netdev(struct mlx5_core_dev mdev, void vpriv) · 6 unmodified lines
2615	mlx5_core_dealloc_transport_domain(priv->mdev, priv->tdn);	2655	mlx5_core_dealloc_transport_domain(priv->mdev, priv->tdn);
2616	mlx5_core_dealloc_pd(priv->mdev, priv->pdn);	2656	mlx5_core_dealloc_pd(priv->mdev, priv->pdn);
2617	mlx5_unmap_free_uar(priv->mdev, &priv->cq_uar);	2657	mlx5_unmap_free_uar(priv->mdev, &priv->cq_uar);
2618	free_netdev(netdev);	2658
		2659	if (!test_bit(MLX5_INTERFACE_STATE_SHUTDOWN, &mdev->intf_state))
		2660	free_netdev(netdev);
2619	}	2661	}
2620		2662
2621	static void mlx5e_get_netdev(void vpriv)	2663	static void mlx5e_get_netdev(void vpriv)

drivers/net/ethernet/mellanox/mlx5/core/fs_core.c+18−30

 	return rule;
 }
-static struct mlx5_flow_rule *add_rule_to_auto_fg(struct mlx5_flow_table *ft,
-						  u8 match_criteria_enable,
-						  u32 *match_criteria,
-						  u32 *match_value,
-						  u8 action,
-						  u32 flow_tag,
-						  struct mlx5_flow_destination *dest)
-{
-	struct mlx5_flow_rule *rule;
-	struct mlx5_flow_group *g;
-	g = create_autogroup(ft, match_criteria_enable, match_criteria);
-	if (IS_ERR(g))
-		return (void *)g;
-	rule = add_rule_fg(g, match_value,
-			   action, flow_tag, dest);
-	if (IS_ERR(rule)) {
-		/* Remove assumes refcount > 0 and autogroup creates a group
-		 * with a refcount = 0.
-		 */
-		tree_get_node(&g->node);
-		tree_remove_node(&g->node);
-	}
-	return rule;
-}
 static struct mlx5_flow_rule *
 _mlx5_add_flow_rule(struct mlx5_flow_table *ft,
 		    u8 match_criteria_enable,
 				goto unlock;
 		}
-	rule = add_rule_to_auto_fg(ft, match_criteria_enable, match_criteria,
+	g = create_autogroup(ft, match_criteria_enable, match_criteria);
-				   match_value, action, flow_tag, dest);
+	if (IS_ERR(g)) {
+		rule = (void *)g;
+		goto unlock;
+	}
+	rule = add_rule_fg(g, match_value,
+			   action, flow_tag, dest);
+	if (IS_ERR(rule)) {
+		/* Remove assumes refcount > 0 and autogroup creates a group
+		 * with a refcount = 0.
+		 */
+		unlock_ref_node(&ft->node);
+		tree_get_node(&g->node);
+		tree_remove_node(&g->node);
+		return rule;
+	}
 unlock:
 	unlock_ref_node(&ft->node);
 	return rule;
 {
 	struct mlx5_flow_root_namespace *root_ns = dev->priv.root_ns;
 	int prio;
-	static struct fs_prio *fs_prio;
+	struct fs_prio *fs_prio;
 	struct mlx5_flow_namespace *ns;
 	if (!root_ns)

drivers/net/ethernet/mellanox/mlx5/core/main.c+21−4

 	int err;
 	mutex_lock(&dev->intf_state_mutex);
-	if (dev->interface_state == MLX5_INTERFACE_STATE_UP) {
+	if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
 		dev_warn(&dev->pdev->dev, "%s: interface is up, NOP\n",
 			 __func__);
 		goto out;
 	if (err)
 		pr_info("failed request module on %s\n", MLX5_IB_MOD);
-	dev->interface_state = MLX5_INTERFACE_STATE_UP;
+	clear_bit(MLX5_INTERFACE_STATE_DOWN, &dev->intf_state);
+	set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
 out:
 	mutex_unlock(&dev->intf_state_mutex);
 	}
 	mutex_lock(&dev->intf_state_mutex);
-	if (dev->interface_state == MLX5_INTERFACE_STATE_DOWN) {
+	if (test_bit(MLX5_INTERFACE_STATE_DOWN, &dev->intf_state)) {
 		dev_warn(&dev->pdev->dev, "%s: interface is down, NOP\n",
 			 __func__);
 		goto out;
 	mlx5_cmd_cleanup(dev);
 out:
-	dev->interface_state = MLX5_INTERFACE_STATE_DOWN;
+	clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
+	set_bit(MLX5_INTERFACE_STATE_DOWN, &dev->intf_state);
 	mutex_unlock(&dev->intf_state_mutex);
 	return err;
 }
 	.resume		= mlx5_pci_resume
 };
+static void shutdown(struct pci_dev *pdev)
+{
+	struct mlx5_core_dev *dev  = pci_get_drvdata(pdev);
+	struct mlx5_priv *priv = &dev->priv;
+	dev_info(&pdev->dev, "Shutdown was called\n");
+	/* Notify mlx5 clients that the kernel is being shut down */
+	set_bit(MLX5_INTERFACE_STATE_SHUTDOWN, &dev->intf_state);
+	mlx5_unload_one(dev, priv);
+	mlx5_pci_disable_device(dev);
+}
 static const struct pci_device_id mlx5_core_pci_table[] = {
 	{ PCI_VDEVICE(MELLANOX, 0x1011) },			/* Connect-IB */
 	{ PCI_VDEVICE(MELLANOX, 0x1012), MLX5_PCI_DEV_IS_VF},	/* Connect-IB VF */
 	{ PCI_VDEVICE(MELLANOX, 0x1014), MLX5_PCI_DEV_IS_VF},	/* ConnectX-4 VF */
 	{ PCI_VDEVICE(MELLANOX, 0x1015) },			/* ConnectX-4LX */
 	{ PCI_VDEVICE(MELLANOX, 0x1016), MLX5_PCI_DEV_IS_VF},	/* ConnectX-4LX VF */
+	{ PCI_VDEVICE(MELLANOX, 0x1017) },			/* ConnectX-5 */
+	{ PCI_VDEVICE(MELLANOX, 0x1018), MLX5_PCI_DEV_IS_VF},	/* ConnectX-5 VF */
 	{ 0, }
 };
 	.id_table       = mlx5_core_pci_table,
 	.probe          = init_one,
 	.remove         = remove_one,
+	.shutdown	= shutdown,
 	.err_handler	= &mlx5_err_handler,
 	.sriov_configure   = mlx5_core_sriov_configure,
 };

drivers/net/ethernet/mellanox/mlx5/core/port.c+5−5

drivers/net/ethernet/mellanox/mlx5/core/vport.c+40−0

@@ -196,6 +196,46 @@ int mlx5_modify_nic_vport_mac_address(struct mlx5_core_dev *mdev, · 195 unmodified lines
196	}	196	}
197	EXPORT_SYMBOL_GPL(mlx5_modify_nic_vport_mac_address);	197	EXPORT_SYMBOL_GPL(mlx5_modify_nic_vport_mac_address);
198		198
		199	int mlx5_query_nic_vport_mtu(struct mlx5_core_dev mdev, u16 mtu)
		200	{
		201	int outlen = MLX5_ST_SZ_BYTES(query_nic_vport_context_out);
		202	u32 *out;
		203	int err;
		204
		205	out = mlx5_vzalloc(outlen);
		206	if (!out)
		207	return -ENOMEM;
		208
		209	err = mlx5_query_nic_vport_context(mdev, 0, out, outlen);
		210	if (!err)
		211	*mtu = MLX5_GET(query_nic_vport_context_out, out,
		212	nic_vport_context.mtu);
		213
		214	kvfree(out);
		215	return err;
		216	}
		217	EXPORT_SYMBOL_GPL(mlx5_query_nic_vport_mtu);
		218
		219	int mlx5_modify_nic_vport_mtu(struct mlx5_core_dev *mdev, u16 mtu)
		220	{
		221	int inlen = MLX5_ST_SZ_BYTES(modify_nic_vport_context_in);
		222	void *in;
		223	int err;
		224
		225	in = mlx5_vzalloc(inlen);
		226	if (!in)
		227	return -ENOMEM;
		228
		229	MLX5_SET(modify_nic_vport_context_in, in, field_select.mtu, 1);
		230	MLX5_SET(modify_nic_vport_context_in, in, nic_vport_context.mtu, mtu);
		231
		232	err = mlx5_modify_nic_vport_context(mdev, in, inlen);
		233
		234	kvfree(in);
		235	return err;
		236	}
		237	EXPORT_SYMBOL_GPL(mlx5_modify_nic_vport_mtu);
		238
199	int mlx5_query_nic_vport_mac_list(struct mlx5_core_dev *dev,	239	int mlx5_query_nic_vport_mac_list(struct mlx5_core_dev *dev,
200	u32 vport,	240	u32 vport,
201	enum mlx5_list_type list_type,	241	enum mlx5_list_type list_type,

drivers/net/ethernet/qlogic/qlcnic/qlcnic.h+2−2

@@ -37,8 +37,8 @@ · 36 unmodified lines
37		37
38	#define _QLCNIC_LINUX_MAJOR 5	38	#define _QLCNIC_LINUX_MAJOR 5
39	#define _QLCNIC_LINUX_MINOR 3	39	#define _QLCNIC_LINUX_MINOR 3
40	#define _QLCNIC_LINUX_SUBVERSION 63	40	#define _QLCNIC_LINUX_SUBVERSION 64
41	#define QLCNIC_LINUX_VERSIONID "5.3.63"	41	#define QLCNIC_LINUX_VERSIONID "5.3.64"
42	#define QLCNIC_DRV_IDC_VER 0x01	42	#define QLCNIC_DRV_IDC_VER 0x01
43	#define QLCNIC_DRIVER_VERSION ((_QLCNIC_LINUX_MAJOR << 16) \|\	43	#define QLCNIC_DRIVER_VERSION ((_QLCNIC_LINUX_MAJOR << 16) \|\
44	(_QLCNIC_LINUX_MINOR << 8) \| (_QLCNIC_LINUX_SUBVERSION))	44	(_QLCNIC_LINUX_MINOR << 8) \| (_QLCNIC_LINUX_SUBVERSION))

drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c+16−34

 	u32	reg_shift;
 	struct	device *dev;
 	struct regmap *sys_mgr_base_addr;
-	struct reset_control *stmmac_rst;
 	void __iomem *splitter_base;
 	bool f2h_ptp_ref_clk;
 };
 	struct device_node *np_splitter;
 	struct resource res_splitter;
-	dwmac->stmmac_rst = devm_reset_control_get(dev,
-						  STMMAC_RESOURCE_NAME);
-	if (IS_ERR(dwmac->stmmac_rst)) {
-		dev_info(dev, "Could not get reset control!\n");
-		if (PTR_ERR(dwmac->stmmac_rst) == -EPROBE_DEFER)
-			return -EPROBE_DEFER;
-		dwmac->stmmac_rst = NULL;
-	}
 	dwmac->interface = of_get_phy_mode(np);
 	sys_mgr_base_addr = syscon_regmap_lookup_by_phandle(np, "altr,sysmgr-syscon");
 	return 0;
 }
-static void socfpga_dwmac_exit(struct platform_device *pdev, void *priv)
-{
-	struct socfpga_dwmac	*dwmac = priv;
-	/* On socfpga platform exit, assert and hold reset to the
-	 * enet controller - the default state after a hard reset.
-	 */
-	if (dwmac->stmmac_rst)
-		reset_control_assert(dwmac->stmmac_rst);
-}
 static int socfpga_dwmac_init(struct platform_device *pdev, void *priv)
 {
-	struct socfpga_dwmac	*dwmac = priv;
+	struct socfpga_dwmac *dwmac = priv;
 	struct net_device *ndev = platform_get_drvdata(pdev);
 	struct stmmac_priv *stpriv = NULL;
 	int ret = 0;
-	if (ndev)
+	if (!ndev)
-		stpriv = netdev_priv(ndev);
+		return -EINVAL;
+	stpriv = netdev_priv(ndev);
+	if (!stpriv)
+		return -EINVAL;
 	/* Assert reset to the enet controller before changing the phy mode */
-	if (dwmac->stmmac_rst)
+	if (stpriv->stmmac_rst)
-		reset_control_assert(dwmac->stmmac_rst);
+		reset_control_assert(stpriv->stmmac_rst);
 	/* Setup the phy mode in the system manager registers according to
 	 * devicetree configuration
 	/* Deassert reset for the phy configuration to be sampled by
 	 * the enet controller, and operation to start in requested mode
 	 */
-	if (dwmac->stmmac_rst)
+	if (stpriv->stmmac_rst)
-		reset_control_deassert(dwmac->stmmac_rst);
+		reset_control_deassert(stpriv->stmmac_rst);
 	/* Before the enet controller is suspended, the phy is suspended.
 	 * This causes the phy clock to be gated. The enet controller is
 	 * control register 0, and can be modified by the phy driver
 	 * framework.
 	 */
-	if (stpriv && stpriv->phydev)
+	if (stpriv->phydev)
 		phy_resume(stpriv->phydev);
 	return ret;
 	plat_dat->bsp_priv = dwmac;
 	plat_dat->init = socfpga_dwmac_init;
-	plat_dat->exit = socfpga_dwmac_exit;
 	plat_dat->fix_mac_speed = socfpga_dwmac_fix_mac_speed;
-	ret = socfpga_dwmac_init(pdev, plat_dat->bsp_priv);
+	ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res);
-	if (ret)
+	if (!ret)
-		return ret;
+		ret = socfpga_dwmac_init(pdev, dwmac);
-	return stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res);
+	return ret;
 }
 static const struct of_device_id socfpga_dwmac_match[] = {

drivers/net/macsec.c+42−23

 	macsec_skb_cb(skb)->valid = false;
 	skb = skb_share_check(skb, GFP_ATOMIC);
 	if (!skb)
-		return NULL;
+		return ERR_PTR(-ENOMEM);
 	req = aead_request_alloc(rx_sa->key.tfm, GFP_ATOMIC);
 	if (!req) {
 		kfree_skb(skb);
-		return NULL;
+		return ERR_PTR(-ENOMEM);
 	}
 	hdr = (struct macsec_eth_header *)skb->data;
 		skb = skb_unshare(skb, GFP_ATOMIC);
 		if (!skb) {
 			aead_request_free(req);
-			return NULL;
+			return ERR_PTR(-ENOMEM);
 		}
 	} else {
 		/* integrity only: all headers + data authenticated */
 	dev_hold(dev);
 	ret = crypto_aead_decrypt(req);
 	if (ret == -EINPROGRESS) {
-		return NULL;
+		return ERR_PTR(ret);
 	} else if (ret != 0) {
 		/* decryption/authentication failed
 		 * 10.6 if validateFrames is disabled, deliver anyway
 		 */
 		if (ret != -EBADMSG) {
 			kfree_skb(skb);
-			skb = NULL;
+			skb = ERR_PTR(ret);
 		}
 	} else {
 		macsec_skb_cb(skb)->valid = true;
 	    secy->validate_frames != MACSEC_VALIDATE_DISABLED)
 		skb = macsec_decrypt(skb, dev, rx_sa, sci, secy);
-	if (!skb) {
+	if (IS_ERR(skb)) {
-		macsec_rxsa_put(rx_sa);
+		/* the decrypt callback needs the reference */
+		if (PTR_ERR(skb) != -EINPROGRESS)
+			macsec_rxsa_put(rx_sa);
 		rcu_read_unlock();
 		*pskb = NULL;
 		return RX_HANDLER_CONSUMED;
 			    macsec_extra_len(macsec_skb_cb(skb)->has_sci));
 	macsec_reset_skb(skb, secy->netdev);
-	macsec_rxsa_put(rx_sa);
+	if (rx_sa)
+		macsec_rxsa_put(rx_sa);
 	count_rx(dev, skb->len);
 	rcu_read_unlock();
 	}
 	rx_sa = kmalloc(sizeof(*rx_sa), GFP_KERNEL);
-	if (init_rx_sa(rx_sa, nla_data(tb_sa[MACSEC_SA_ATTR_KEY]), secy->key_len,
+	if (!rx_sa || init_rx_sa(rx_sa, nla_data(tb_sa[MACSEC_SA_ATTR_KEY]),
-		       secy->icv_len)) {
+				 secy->key_len, secy->icv_len)) {
+		kfree(rx_sa);
 		rtnl_unlock();
 		return -ENOMEM;
 	}
 	tx_sa = kmalloc(sizeof(*tx_sa), GFP_KERNEL);
 	if (!tx_sa || init_tx_sa(tx_sa, nla_data(tb_sa[MACSEC_SA_ATTR_KEY]),
 				 secy->key_len, secy->icv_len)) {
+		kfree(tx_sa);
 		rtnl_unlock();
 		return -ENOMEM;
 	}
 		return 1;
 	if (nla_put_sci(skb, MACSEC_SECY_ATTR_SCI, secy->sci) ||
-	    nla_put_u64(skb, MACSEC_SECY_ATTR_CIPHER_SUITE, DEFAULT_CIPHER_ID) ||
+	    nla_put_u64(skb, MACSEC_SECY_ATTR_CIPHER_SUITE,
+			MACSEC_DEFAULT_CIPHER_ID) ||
 	    nla_put_u8(skb, MACSEC_SECY_ATTR_ICV_LEN, secy->icv_len) ||
 	    nla_put_u8(skb, MACSEC_SECY_ATTR_OPER, secy->operational) ||
 	    nla_put_u8(skb, MACSEC_SECY_ATTR_PROTECT, secy->protect_frames) ||
 	if (!hdr)
 		return -EMSGSIZE;
-	rtnl_lock();
+	genl_dump_check_consistent(cb, hdr, &macsec_fam);
 	if (nla_put_u32(skb, MACSEC_ATTR_IFINDEX, dev->ifindex))
 		goto nla_put_failure;
 	nla_nest_end(skb, rxsc_list);
-	rtnl_unlock();
 	genlmsg_end(skb, hdr);
 	return 0;
 nla_put_failure:
-	rtnl_unlock();
 	genlmsg_cancel(skb, hdr);
 	return -EMSGSIZE;
 }
+static int macsec_generation = 1; /* protected by RTNL */
 static int macsec_dump_txsc(struct sk_buff *skb, struct netlink_callback *cb)
 {
 	struct net *net = sock_net(skb->sk);
 	dev_idx = cb->args[0];
 	d = 0;
+	rtnl_lock();
+	cb->seq = macsec_generation;
 	for_each_netdev(net, dev) {
 		struct macsec_secy *secy;
 	}
 done:
+	rtnl_unlock();
 	cb->args[0] = d;
 	return skb->len;
 }
 	struct net_device *real_dev = macsec->real_dev;
 	struct macsec_rxh_data *rxd = macsec_data_rtnl(real_dev);
+	macsec_generation++;
 	unregister_netdevice_queue(dev, head);
 	list_del_rcu(&macsec->secys);
-	if (list_empty(&rxd->secys))
+	if (list_empty(&rxd->secys)) {
 		netdev_rx_handler_unregister(real_dev);
+		kfree(rxd);
+	}
 	macsec_del_dev(macsec);
 }
 		err = netdev_rx_handler_register(real_dev, macsec_handle_frame,
 						 rxd);
-		if (err < 0)
+		if (err < 0) {
+			kfree(rxd);
 			return err;
+		}
 	}
 	list_add_tail_rcu(&macsec->secys, &rxd->secys);
 	if (err < 0)
 		goto del_dev;
+	macsec_generation++;
 	dev_hold(real_dev);
 	return 0;
 static int macsec_validate_attr(struct nlattr *tb[], struct nlattr *data[])
 {
-	u64 csid = DEFAULT_CIPHER_ID;
+	u64 csid = MACSEC_DEFAULT_CIPHER_ID;
 	u8 icv_len = DEFAULT_ICV_LEN;
 	int flag;
 	bool es, scb, sci;
 		icv_len = nla_get_u8(data[IFLA_MACSEC_ICV_LEN]);
 	switch (csid) {
-	case DEFAULT_CIPHER_ID:
+	case MACSEC_DEFAULT_CIPHER_ID:
-	case DEFAULT_CIPHER_ALT:
+	case MACSEC_DEFAULT_CIPHER_ALT:
 		if (icv_len < MACSEC_MIN_ICV_LEN ||
 		    icv_len > MACSEC_MAX_ICV_LEN)
 			return -EINVAL;
 	    nla_get_u8(data[IFLA_MACSEC_VALIDATION]) > MACSEC_VALIDATE_MAX)
 		return -EINVAL;
-	if ((data[IFLA_MACSEC_PROTECT] &&
+	if ((data[IFLA_MACSEC_REPLAY_PROTECT] &&
-	     nla_get_u8(data[IFLA_MACSEC_PROTECT])) &&
+	     nla_get_u8(data[IFLA_MACSEC_REPLAY_PROTECT])) &&
 	    !data[IFLA_MACSEC_WINDOW])
 		return -EINVAL;
 	if (nla_put_sci(skb, IFLA_MACSEC_SCI, secy->sci) ||
 	    nla_put_u8(skb, IFLA_MACSEC_ICV_LEN, secy->icv_len) ||
-	    nla_put_u64(skb, IFLA_MACSEC_CIPHER_SUITE, DEFAULT_CIPHER_ID) ||
+	    nla_put_u64(skb, IFLA_MACSEC_CIPHER_SUITE,
+			MACSEC_DEFAULT_CIPHER_ID) ||
 	    nla_put_u8(skb, IFLA_MACSEC_ENCODING_SA, tx_sc->encoding_sa) ||
 	    nla_put_u8(skb, IFLA_MACSEC_ENCRYPT, tx_sc->encrypt) ||
 	    nla_put_u8(skb, IFLA_MACSEC_PROTECT, secy->protect_frames) ||

drivers/platform/x86/toshiba_acpi.c+1−1

@@ -135,7 +135,7 @@ MODULE_LICENSE("GPL"); · 134 unmodified lines
135	/* Field definitions */	135	/* Field definitions */
136	#define HCI_ACCEL_MASK 0x7fff	136	#define HCI_ACCEL_MASK 0x7fff
137	#define HCI_HOTKEY_DISABLE 0x0b	137	#define HCI_HOTKEY_DISABLE 0x0b
138	#define HCI_HOTKEY_ENABLE 0x01	138	#define HCI_HOTKEY_ENABLE 0x09
139	#define HCI_HOTKEY_SPECIAL_FUNCTIONS 0x10	139	#define HCI_HOTKEY_SPECIAL_FUNCTIONS 0x10
140	#define HCI_LCD_BRIGHTNESS_BITS 3	140	#define HCI_LCD_BRIGHTNESS_BITS 3
141	#define HCI_LCD_BRIGHTNESS_SHIFT (16-HCI_LCD_BRIGHTNESS_BITS)	141	#define HCI_LCD_BRIGHTNESS_SHIFT (16-HCI_LCD_BRIGHTNESS_BITS)

drivers/rapidio/devices/rio_mport_cdev.c+2−2

@@ -2669,9 +2669,9 @@ static int __init mport_init(void) · 2668 unmodified lines
2669		2669
2670	/* Create device class needed by udev */	2670	/* Create device class needed by udev */
2671	dev_class = class_create(THIS_MODULE, DRV_NAME);	2671	dev_class = class_create(THIS_MODULE, DRV_NAME);
2672	if (!dev_class) {	2672	if (IS_ERR(dev_class)) {
2673	rmcd_error("Unable to create " DRV_NAME " class");	2673	rmcd_error("Unable to create " DRV_NAME " class");
2674	return -EINVAL;	2674	return PTR_ERR(dev_class);
2675	}	2675	}
2676		2676
2677	ret = alloc_chrdev_region(&dev_number, 0, RIO_MAX_MPORTS, DRV_NAME);	2677	ret = alloc_chrdev_region(&dev_number, 0, RIO_MAX_MPORTS, DRV_NAME);

drivers/s390/char/sclp_ctl.c+7−5

 {
 	struct sclp_ctl_sccb ctl_sccb;
 	struct sccb_header *sccb;
+	unsigned long copied;
 	int rc;
 	if (copy_from_user(&ctl_sccb, user_area, sizeof(ctl_sccb)))
 	sccb = (void *) get_zeroed_page(GFP_KERNEL | GFP_DMA);
 	if (!sccb)
 		return -ENOMEM;
-	if (copy_from_user(sccb, u64_to_uptr(ctl_sccb.sccb), sizeof(*sccb))) {
+	copied = PAGE_SIZE -
+		copy_from_user(sccb, u64_to_uptr(ctl_sccb.sccb), PAGE_SIZE);
+	if (offsetof(struct sccb_header, length) +
+	    sizeof(sccb->length) > copied || sccb->length > copied) {
 		rc = -EFAULT;
 		goto out_free;
 	}
-	if (sccb->length > PAGE_SIZE || sccb->length < 8)
+	if (sccb->length < 8) {
-		return -EINVAL;
+		rc = -EINVAL;
-	if (copy_from_user(sccb, u64_to_uptr(ctl_sccb.sccb), sccb->length)) {
-		rc = -EFAULT;
 		goto out_free;
 	}
 	rc = sclp_sync_request(ctl_sccb.cmdw, sccb);

drivers/scsi/cxgbi/libcxgbi.c+1−0

@@ -688,6 +688,7 @@ static struct rt6_info find_route_ipv6(const struct in6_addr saddr, · 687 unmodified lines
688	{	688	{
689	struct flowi6 fl;	689	struct flowi6 fl;
690		690
		691	memset(&fl, 0, sizeof(fl));
691	if (saddr)	692	if (saddr)
692	memcpy(&fl.saddr, saddr, sizeof(struct in6_addr));	693	memcpy(&fl.saddr, saddr, sizeof(struct in6_addr));
693	if (daddr)	694	if (daddr)

drivers/soc/mediatek/mtk-scpsys.c+6−5

 		genpd->dev_ops.active_wakeup = scpsys_active_wakeup;
 		/*
-		 * With CONFIG_PM disabled turn on all domains to make the
+		 * Initially turn on all domains to make the domains usable
-		 * hardware usable.
+		 * with !CONFIG_PM and to get the hardware in sync with the
+		 * software.  The unused domains will be switched off during
+		 * late_init time.
 		 */
-		if (!IS_ENABLED(CONFIG_PM))
+		genpd->power_on(genpd);
-			genpd->power_on(genpd);
-		pm_genpd_init(genpd, NULL, true);
+		pm_genpd_init(genpd, NULL, false);
 	}
 	/*

drivers/staging/media/davinci_vpfe/vpfe_video.c+34−20

 static int vpfe_update_pipe_state(struct vpfe_video_device *video)
 {
 	struct vpfe_pipeline *pipe = &video->pipe;
+	int ret;
-	if (vpfe_prepare_pipeline(video))
+	ret = vpfe_prepare_pipeline(video);
-		return vpfe_prepare_pipeline(video);
+	if (ret)
+		return ret;
 	/*
 	 * Find out if there is any input video
 	 */
 	if (pipe->input_num == 0) {
 		pipe->state = VPFE_PIPELINE_STREAM_CONTINUOUS;
-		if (vpfe_update_current_ext_subdev(video)) {
+		ret = vpfe_update_current_ext_subdev(video);
+		if (ret) {
 			pr_err("Invalid external subdev\n");
-			return vpfe_update_current_ext_subdev(video);
+			return ret;
 		}
 	} else {
 		pipe->state = VPFE_PIPELINE_STREAM_SINGLESHOT;
 	struct v4l2_subdev *subdev;
 	struct v4l2_format format;
 	struct media_pad *remote;
+	int ret;
 	v4l2_dbg(1, debug, &vpfe_dev->v4l2_dev, "vpfe_enum_fmt\n");
 	sd_fmt.pad = remote->index;
 	sd_fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE;
 	/* get output format of remote subdev */
-	if (v4l2_subdev_call(subdev, pad, get_fmt, NULL, &sd_fmt)) {
+	ret = v4l2_subdev_call(subdev, pad, get_fmt, NULL, &sd_fmt);
+	if (ret) {
 		v4l2_err(&vpfe_dev->v4l2_dev,
 			 "invalid remote subdev for video node\n");
-		return v4l2_subdev_call(subdev, pad, get_fmt, NULL, &sd_fmt);
+		return ret;
 	}
 	/* convert to pix format */
 	mbus.code = sd_fmt.format.code;
 	struct vpfe_video_device *video = video_drvdata(file);
 	struct vpfe_device *vpfe_dev = video->vpfe_dev;
 	struct v4l2_format format;
+	int ret;
 	v4l2_dbg(1, debug, &vpfe_dev->v4l2_dev, "vpfe_s_fmt\n");
 	/* If streaming is started, return error */
 		return -EBUSY;
 	}
 	/* get adjacent subdev's output pad format */
-	if (__vpfe_video_get_format(video, &format))
+	ret = __vpfe_video_get_format(video, &format);
-		return __vpfe_video_get_format(video, &format);
+	if (ret)
+		return ret;
 	*fmt = format;
 	video->fmt = *fmt;
 	return 0;
 	struct vpfe_video_device *video = video_drvdata(file);
 	struct vpfe_device *vpfe_dev = video->vpfe_dev;
 	struct v4l2_format format;
+	int ret;
 	v4l2_dbg(1, debug, &vpfe_dev->v4l2_dev, "vpfe_try_fmt\n");
 	/* get adjacent subdev's output pad format */
-	if (__vpfe_video_get_format(video, &format))
+	ret = __vpfe_video_get_format(video, &format);
-		return __vpfe_video_get_format(video, &format);
+	if (ret)
+		return ret;
 	*fmt = format;
 	return 0;
 	v4l2_dbg(1, debug, &vpfe_dev->v4l2_dev, "vpfe_s_input\n");
-	if (mutex_lock_interruptible(&video->lock))
+	ret = mutex_lock_interruptible(&video->lock);
-		return mutex_lock_interruptible(&video->lock);
+	if (ret)
+		return ret;
 	/*
 	 * If streaming is started return device busy
 	 * error
 	v4l2_dbg(1, debug, &vpfe_dev->v4l2_dev, "vpfe_s_std\n");
 	/* Call decoder driver function to set the standard */
-	if (mutex_lock_interruptible(&video->lock))
+	ret = mutex_lock_interruptible(&video->lock);
-		return mutex_lock_interruptible(&video->lock);
+	if (ret)
+		return ret;
 	sdinfo = video->current_ext_subdev;
 	/* If streaming is started, return device busy error */
 	if (video->started) {
 		return -EINVAL;
 	}
-	if (mutex_lock_interruptible(&video->lock))
+	ret = mutex_lock_interruptible(&video->lock);
-		return mutex_lock_interruptible(&video->lock);
+	if (ret)
+		return ret;
 	if (video->io_usrs != 0) {
 		v4l2_err(&vpfe_dev->v4l2_dev, "Only one IO user allowed\n");
 	q->buf_struct_size = sizeof(struct vpfe_cap_buffer);
 	q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
-	if (vb2_queue_init(q)) {
+	ret = vb2_queue_init(q);
+	if (ret) {
 		v4l2_err(&vpfe_dev->v4l2_dev, "vb2_queue_init() failed\n");
 		vb2_dma_contig_cleanup_ctx(vpfe_dev->pdev);
-		return vb2_queue_init(q);
+		return ret;
 	}
 	fh->io_allowed = 1;
 		return -EINVAL;
 	}
-	if (mutex_lock_interruptible(&video->lock))
+	ret = mutex_lock_interruptible(&video->lock);
-		return mutex_lock_interruptible(&video->lock);
+	if (ret)
+		return ret;
 	vpfe_stop_capture(video);
 	ret = vb2_streamoff(&video->buffer_queue, buf_type);

drivers/staging/rdma/hfi1/TODO+1−1

@@ -3,4 +3,4 @@ July, 2015 · 2 unmodified lines
3	- Remove unneeded file entries in sysfs	3	- Remove unneeded file entries in sysfs
4	- Remove software processing of IB protocol and place in library for use	4	- Remove software processing of IB protocol and place in library for use
5	by qib, ipath (if still present), hfi1, and eventually soft-roce	5	by qib, ipath (if still present), hfi1, and eventually soft-roce
6		6	- Replace incorrect uAPI

drivers/staging/rdma/hfi1/file_ops.c+35−56

 #include <linux/vmalloc.h>
 #include <linux/io.h>
+#include <rdma/ib.h>
 #include "hfi.h"
 #include "pio.h"
 #include "device.h"
 	int uctxt_required = 1;
 	int must_be_root = 0;
+	/* FIXME: This interface cannot continue out of staging */
+	if (WARN_ON_ONCE(!ib_safe_file_access(fp)))
+		return -EACCES;
 	if (count < sizeof(cmd)) {
 		ret = -EINVAL;
 		goto bail;
 	spin_unlock_irqrestore(&dd->uctxt_lock, flags);
 	dd->rcd[uctxt->ctxt] = NULL;
+	hfi1_user_exp_rcv_free(fdata);
+	hfi1_clear_ctxt_pkey(dd, uctxt->ctxt);
 	uctxt->rcvwait_to = 0;
 	uctxt->piowait_to = 0;
 	uctxt->rcvnowait = 0;
 	uctxt->pionowait = 0;
 	uctxt->event_flags = 0;
-	hfi1_user_exp_rcv_free(fdata);
-	hfi1_clear_ctxt_pkey(dd, uctxt->ctxt);
 	hfi1_stats.sps_ctxts--;
 	if (++dd->freectxts == dd->num_user_contexts)
 		aspm_enable_all(dd);
 static int user_init(struct file *fp)
 {
-	int ret;
 	unsigned int rcvctrl_ops = 0;
 	struct hfi1_filedata *fd = fp->private_data;
 	struct hfi1_ctxtdata *uctxt = fd->uctxt;
 	/* make sure that the context has already been setup */
-	if (!test_bit(HFI1_CTXT_SETUP_DONE, &uctxt->event_flags)) {
+	if (!test_bit(HFI1_CTXT_SETUP_DONE, &uctxt->event_flags))
-		ret = -EFAULT;
+		return -EFAULT;
-		goto done;
-	}
-	/*
-	 * Subctxts don't need to initialize anything since master
-	 * has done it.
-	 */
-	if (fd->subctxt) {
-		ret = wait_event_interruptible(uctxt->wait, !test_bit(
-					       HFI1_CTXT_MASTER_UNINIT,
-					       &uctxt->event_flags));
-		goto expected;
-	}
 	/* initialize poll variables... */
 	uctxt->urgent = 0;
 		wake_up(&uctxt->wait);
 	}
-expected:
+	return 0;
-	/*
-	 * Expected receive has to be setup for all processes (including
-	 * shared contexts). However, it has to be done after the master
-	 * context has been fully configured as it depends on the
-	 * eager/expected split of the RcvArray entries.
-	 * Setting it up here ensures that the subcontexts will be waiting
-	 * (due to the above wait_event_interruptible() until the master
-	 * is setup.
-	 */
-	ret = hfi1_user_exp_rcv_init(fp);
-done:
-	return ret;
 }
 static int get_ctxt_info(struct file *fp, void __user *ubase, __u32 len)
 	int ret = 0;
 	/*
-	 * Context should be set up only once (including allocation and
+	 * Context should be set up only once, including allocation and
 	 * programming of eager buffers. This is done if context sharing
 	 * is not requested or by the master process.
 	 */
 			if (ret)
 				goto done;
 		}
+	} else {
+		ret = wait_event_interruptible(uctxt->wait, !test_bit(
+					       HFI1_CTXT_MASTER_UNINIT,
+					       &uctxt->event_flags));
+		if (ret)
+			goto done;
 	}
 	ret = hfi1_user_sdma_alloc_queues(uctxt, fp);
+	if (ret)
+		goto done;
+	/*
+	 * Expected receive has to be setup for all processes (including
+	 * shared contexts). However, it has to be done after the master
+	 * context has been fully configured as it depends on the
+	 * eager/expected split of the RcvArray entries.
+	 * Setting it up here ensures that the subcontexts will be waiting
+	 * (due to the above wait_event_interruptible() until the master
+	 * is setup.
+	 */
+	ret = hfi1_user_exp_rcv_init(fp);
 	if (ret)
 		goto done;
 {
 	struct hfi1_devdata *dd = filp->private_data;
-	switch (whence) {
+	return fixed_size_llseek(filp, offset, whence,
-	case SEEK_SET:
+		(dd->kregend - dd->kregbase) + DC8051_DATA_MEM_SIZE);
-		break;
-	case SEEK_CUR:
-		offset += filp->f_pos;
-		break;
-	case SEEK_END:
-		offset = ((dd->kregend - dd->kregbase) + DC8051_DATA_MEM_SIZE) -
-			offset;
-		break;
-	default:
-		return -EINVAL;
-	}
-	if (offset < 0)
-		return -EINVAL;
-	if (offset >= (dd->kregend - dd->kregbase) + DC8051_DATA_MEM_SIZE)
-		return -EINVAL;
-	filp->f_pos = offset;
-	return filp->f_pos;
 }
 /* NOTE: assumes unsigned long is 8 bytes */

drivers/staging/rdma/hfi1/mmu_rb.c+25−15

 					    struct mm_struct *,
 					    unsigned long, unsigned long);
 static void mmu_notifier_mem_invalidate(struct mmu_notifier *,
+					struct mm_struct *,
 					unsigned long, unsigned long);
 static struct mmu_rb_node *__mmu_rb_search(struct mmu_rb_handler *,
 					   unsigned long, unsigned long);
 			rbnode = rb_entry(node, struct mmu_rb_node, node);
 			rb_erase(node, root);
 			if (handler->ops->remove)
-				handler->ops->remove(root, rbnode, false);
+				handler->ops->remove(root, rbnode, NULL);
 		}
 	}
 	return ret;
 }
-/* Caller must host handler lock */
+/* Caller must hold handler lock */
 static struct mmu_rb_node *__mmu_rb_search(struct mmu_rb_handler *handler,
 					   unsigned long addr,
 					   unsigned long len)
 	return node;
 }
+/* Caller must *not* hold handler lock. */
 static void __mmu_rb_remove(struct mmu_rb_handler *handler,
-			    struct mmu_rb_node *node, bool arg)
+			    struct mmu_rb_node *node, struct mm_struct *mm)
 {
+	unsigned long flags;
 	/* Validity of handler and node pointers has been checked by caller. */
 	hfi1_cdbg(MMU, "Removing node addr 0x%llx, len %u", node->addr,
 		  node->len);
+	spin_lock_irqsave(&handler->lock, flags);
 	__mmu_int_rb_remove(node, handler->root);
+	spin_unlock_irqrestore(&handler->lock, flags);
 	if (handler->ops->remove)
-		handler->ops->remove(handler->root, node, arg);
+		handler->ops->remove(handler->root, node, mm);
 }
 struct mmu_rb_node *hfi1_mmu_rb_search(struct rb_root *root, unsigned long addr,
 void hfi1_mmu_rb_remove(struct rb_root *root, struct mmu_rb_node *node)
 {
 	struct mmu_rb_handler *handler = find_mmu_handler(root);
-	unsigned long flags;
 	if (!handler || !node)
 		return;
-	spin_lock_irqsave(&handler->lock, flags);
+	__mmu_rb_remove(handler, node, NULL);
-	__mmu_rb_remove(handler, node, false);
-	spin_unlock_irqrestore(&handler->lock, flags);
 }
 static struct mmu_rb_handler *find_mmu_handler(struct rb_root *root)
 static inline void mmu_notifier_page(struct mmu_notifier *mn,
 				     struct mm_struct *mm, unsigned long addr)
 {
-	mmu_notifier_mem_invalidate(mn, addr, addr + PAGE_SIZE);
+	mmu_notifier_mem_invalidate(mn, mm, addr, addr + PAGE_SIZE);
 }
 static inline void mmu_notifier_range_start(struct mmu_notifier *mn,
 					    unsigned long start,
 					    unsigned long end)
 {
-	mmu_notifier_mem_invalidate(mn, start, end);
+	mmu_notifier_mem_invalidate(mn, mm, start, end);
 }
 static void mmu_notifier_mem_invalidate(struct mmu_notifier *mn,
+					struct mm_struct *mm,
 					unsigned long start, unsigned long end)
 {
 	struct mmu_rb_handler *handler =
 		container_of(mn, struct mmu_rb_handler, mn);
 	struct rb_root *root = handler->root;
-	struct mmu_rb_node *node;
+	struct mmu_rb_node *node, *ptr = NULL;
 	unsigned long flags;
 	spin_lock_irqsave(&handler->lock, flags);
-	for (node = __mmu_int_rb_iter_first(root, start, end - 1); node;
+	for (node = __mmu_int_rb_iter_first(root, start, end - 1);
-	     node = __mmu_int_rb_iter_next(node, start, end - 1)) {
+	     node; node = ptr) {
+		/* Guard against node removal. */
+		ptr = __mmu_int_rb_iter_next(node, start, end - 1);
 		hfi1_cdbg(MMU, "Invalidating node addr 0x%llx, len %u",
 			  node->addr, node->len);
-		if (handler->ops->invalidate(root, node))
+		if (handler->ops->invalidate(root, node)) {
-			__mmu_rb_remove(handler, node, true);
+			spin_unlock_irqrestore(&handler->lock, flags);
+			__mmu_rb_remove(handler, node, mm);
+			spin_lock_irqsave(&handler->lock, flags);
+		}
 	}
 	spin_unlock_irqrestore(&handler->lock, flags);
 }

drivers/staging/rdma/hfi1/mmu_rb.h+2−1

@@ -59,7 +59,8 @@ struct mmu_rb_node { · 58 unmodified lines
59	struct mmu_rb_ops {	59	struct mmu_rb_ops {
60	bool (filter)(struct mmu_rb_node , unsigned long, unsigned long);	60	bool (filter)(struct mmu_rb_node , unsigned long, unsigned long);
61	int (insert)(struct rb_root , struct mmu_rb_node *);	61	int (insert)(struct rb_root , struct mmu_rb_node *);
62	void (remove)(struct rb_root , struct mmu_rb_node *, bool);	62	void (remove)(struct rb_root , struct mmu_rb_node *,
		63	struct mm_struct *);
63	int (invalidate)(struct rb_root , struct mmu_rb_node *);	64	int (invalidate)(struct rb_root , struct mmu_rb_node *);
64	};	65	};
65		66

drivers/staging/rdma/hfi1/qp.c+2−0

 	 * do the flush work until that QP's
 	 * sdma work has finished.
 	 */
+	spin_lock(&qp->s_lock);
 	if (qp->s_flags & RVT_S_WAIT_DMA) {
 		qp->s_flags &= ~RVT_S_WAIT_DMA;
 		hfi1_schedule_send(qp);
 	}
+	spin_unlock(&qp->s_lock);
 }
 /**

drivers/staging/rdma/hfi1/user_exp_rcv.c+7−4

 static int set_rcvarray_entry(struct file *, unsigned long, u32,
 			      struct tid_group *, struct page **, unsigned);
 static int mmu_rb_insert(struct rb_root *, struct mmu_rb_node *);
-static void mmu_rb_remove(struct rb_root *, struct mmu_rb_node *, bool);
+static void mmu_rb_remove(struct rb_root *, struct mmu_rb_node *,
+			  struct mm_struct *);
 static int mmu_rb_invalidate(struct rb_root *, struct mmu_rb_node *);
 static int program_rcvarray(struct file *, unsigned long, struct tid_group *,
 			    struct tid_pageset *, unsigned, u16, struct page **,
 	struct hfi1_ctxtdata *uctxt = fd->uctxt;
 	struct tid_group *grp, *gptr;
+	if (!test_bit(HFI1_CTXT_SETUP_DONE, &uctxt->event_flags))
+		return 0;
 	/*
 	 * The notifier would have been removed when the process'es mm
 	 * was freed.
 	if (!node || node->rcventry != (uctxt->expected_base + rcventry))
 		return -EBADF;
 	if (HFI1_CAP_IS_USET(TID_UNMAP))
-		mmu_rb_remove(&fd->tid_rb_root, &node->mmu, false);
+		mmu_rb_remove(&fd->tid_rb_root, &node->mmu, NULL);
 	else
 		hfi1_mmu_rb_remove(&fd->tid_rb_root, &node->mmu);
 					continue;
 				if (HFI1_CAP_IS_USET(TID_UNMAP))
 					mmu_rb_remove(&fd->tid_rb_root,
-						      &node->mmu, false);
+						      &node->mmu, NULL);
 				else
 					hfi1_mmu_rb_remove(&fd->tid_rb_root,
 							   &node->mmu);
 }
 static void mmu_rb_remove(struct rb_root *root, struct mmu_rb_node *node,
-			  bool notifier)
+			  struct mm_struct *mm)
 {
 	struct hfi1_filedata *fdata =
 		container_of(root, struct hfi1_filedata, tid_rb_root);

drivers/staging/rdma/hfi1/user_sdma.c+22−11

 static void user_sdma_free_request(struct user_sdma_request *, bool);
 static int pin_vector_pages(struct user_sdma_request *,
 			    struct user_sdma_iovec *);
-static void unpin_vector_pages(struct mm_struct *, struct page **, unsigned);
+static void unpin_vector_pages(struct mm_struct *, struct page **, unsigned,
+			       unsigned);
 static int check_header_template(struct user_sdma_request *,
 				 struct hfi1_pkt_header *, u32, u32);
 static int set_txreq_header(struct user_sdma_request *,
 static void activate_packet_queue(struct iowait *, int);
 static bool sdma_rb_filter(struct mmu_rb_node *, unsigned long, unsigned long);
 static int sdma_rb_insert(struct rb_root *, struct mmu_rb_node *);
-static void sdma_rb_remove(struct rb_root *, struct mmu_rb_node *, bool);
+static void sdma_rb_remove(struct rb_root *, struct mmu_rb_node *,
+			   struct mm_struct *);
 static int sdma_rb_invalidate(struct rb_root *, struct mmu_rb_node *);
 static struct mmu_rb_ops sdma_rb_ops = {
 	rb_node = hfi1_mmu_rb_search(&pq->sdma_rb_root,
 				     (unsigned long)iovec->iov.iov_base,
 				     iovec->iov.iov_len);
-	if (rb_node)
+	if (rb_node && !IS_ERR(rb_node))
 		node = container_of(rb_node, struct sdma_mmu_node, rb);
+	else
+		rb_node = NULL;
 	if (!node) {
 		node = kzalloc(sizeof(*node), GFP_KERNEL);
 			goto bail;
 		}
 		if (pinned != npages) {
-			unpin_vector_pages(current->mm, pages, pinned);
+			unpin_vector_pages(current->mm, pages, node->npages,
+					   pinned);
 			ret = -EFAULT;
 			goto bail;
 		}
 }
 static void unpin_vector_pages(struct mm_struct *mm, struct page **pages,
-			       unsigned npages)
+			       unsigned start, unsigned npages)
 {
-	hfi1_release_user_pages(mm, pages, npages, 0);
+	hfi1_release_user_pages(mm, pages + start, npages, 0);
 	kfree(pages);
 }
 				&req->pq->sdma_rb_root,
 				(unsigned long)req->iovs[i].iov.iov_base,
 				req->iovs[i].iov.iov_len);
-			if (!mnode)
+			if (!mnode || IS_ERR(mnode))
 				continue;
 			node = container_of(mnode, struct sdma_mmu_node, rb);
 }
 static void sdma_rb_remove(struct rb_root *root, struct mmu_rb_node *mnode,
-			   bool notifier)
+			   struct mm_struct *mm)
 {
 	struct sdma_mmu_node *node =
 		container_of(mnode, struct sdma_mmu_node, rb);
 	node->pq->n_locked -= node->npages;
 	spin_unlock(&node->pq->evict_lock);
-	unpin_vector_pages(notifier ? NULL : current->mm, node->pages,
+	/*
+	 * If mm is set, we are being called by the MMU notifier and we
+	 * should not pass a mm_struct to unpin_vector_page(). This is to
+	 * prevent a deadlock when hfi1_release_user_pages() attempts to
+	 * take the mmap_sem, which the MMU notifier has already taken.
+	 */
+	unpin_vector_pages(mm ? NULL : current->mm, node->pages, 0,
 			   node->npages);
 	/*
 	 * If called by the MMU notifier, we have to adjust the pinned
 	 * page count ourselves.
 	 */
-	if (notifier)
+	if (mm)
-		current->mm->pinned_vm -= node->npages;
+		mm->pinned_vm -= node->npages;
 	kfree(node);
 }

drivers/thermal/hisi_thermal.c+2−2

@@ -68,12 +68,12 @@ static inline int _step_to_temp(int step) · 67 unmodified lines
68	* Every step equals (1 * 200) / 255 celsius, and finally	68	* Every step equals (1 * 200) / 255 celsius, and finally
69	* need convert to millicelsius.	69	* need convert to millicelsius.
70	*/	70	*/
71	return (HISI_TEMP_BASE + (step * 200 / 255)) * 1000;	71	return (HISI_TEMP_BASE * 1000 + (step * 200000 / 255));
72	}	72	}
73		73
74	static inline long _temp_to_step(long temp)	74	static inline long _temp_to_step(long temp)
75	{	75	{
76	return ((temp / 1000 - HISI_TEMP_BASE) * 255 / 200);	76	return ((temp - HISI_TEMP_BASE * 1000) * 255) / 200000;
77	}	77	}
78		78
79	static long hisi_thermal_get_sensor_temp(struct hisi_thermal_data *data,	79	static long hisi_thermal_get_sensor_temp(struct hisi_thermal_data *data,

drivers/thermal/thermal_core.c+1−1

@@ -959,7 +959,7 @@ static DEVICE_ATTR(sustainable_power, S_IWUSR \| S_IRUGO, sustainable_power_show, · 958 unmodified lines
959	struct thermal_zone_device *tz = to_thermal_zone(dev); \	959	struct thermal_zone_device *tz = to_thermal_zone(dev); \
960	\	960	\
961	if (tz->tzp) \	961	if (tz->tzp) \
962	return sprintf(buf, "%u\n", tz->tzp->name); \	962	return sprintf(buf, "%d\n", tz->tzp->name); \
963	else \	963	else \
964	return -EIO; \	964	return -EIO; \
965	} \	965	} \

drivers/tty/pty.c+8−10

  */
 static struct tty_struct *ptm_unix98_lookup(struct tty_driver *driver,
-		struct inode *ptm_inode, int idx)
+		struct file *file, int idx)
 {
 	/* Master must be open via /dev/ptmx */
 	return ERR_PTR(-EIO);
  */
 static struct tty_struct *pts_unix98_lookup(struct tty_driver *driver,
-		struct inode *pts_inode, int idx)
+		struct file *file, int idx)
 {
 	struct tty_struct *tty;
 	mutex_lock(&devpts_mutex);
-	tty = devpts_get_priv(pts_inode);
+	tty = devpts_get_priv(file->f_path.dentry);
 	mutex_unlock(&devpts_mutex);
 	/* Master must be open before slave */
 	if (!tty)
 {
 	struct pts_fs_info *fsi;
 	struct tty_struct *tty;
-	struct inode *slave_inode;
+	struct dentry *dentry;
 	int retval;
 	int index;
 	tty_add_file(tty, filp);
-	slave_inode = devpts_pty_new(fsi,
+	dentry = devpts_pty_new(fsi, index, tty->link);
-			MKDEV(UNIX98_PTY_SLAVE_MAJOR, index), index,
+	if (IS_ERR(dentry)) {
-			tty->link);
+		retval = PTR_ERR(dentry);
-	if (IS_ERR(slave_inode)) {
-		retval = PTR_ERR(slave_inode);
 		goto err_release;
 	}
-	tty->link->driver_data = slave_inode;
+	tty->link->driver_data = dentry;
 	retval = ptm_driver->ops->open(tty, filp);
 	if (retval)

drivers/tty/tty_io.c+3−3

@@ -1367,12 +1367,12 @@ static ssize_t tty_line_name(struct tty_driver driver, int index, char p) · 1366 unmodified lines
1367	* Locking: tty_mutex must be held. If the tty is found, bump the tty kref.	1367	* Locking: tty_mutex must be held. If the tty is found, bump the tty kref.
1368	*/	1368	*/
1369	static struct tty_struct tty_driver_lookup_tty(struct tty_driver driver,	1369	static struct tty_struct tty_driver_lookup_tty(struct tty_driver driver,
1370	struct inode *inode, int idx)	1370	struct file *file, int idx)
1371	{	1371	{
1372	struct tty_struct *tty;	1372	struct tty_struct *tty;
1373		1373
1374	if (driver->ops->lookup)	1374	if (driver->ops->lookup)
1375	tty = driver->ops->lookup(driver, inode, idx);	1375	tty = driver->ops->lookup(driver, file, idx);
1376	else	1376	else
1377	tty = driver->ttys[idx];	1377	tty = driver->ttys[idx];
1378		1378
@@ -2040,7 +2040,7 @@ static struct tty_struct tty_open_by_driver(dev_t device, struct inode inode, · 661 unmodified lines
2040	}	2040	}
2041		2041
2042	/* check whether we're reopening an existing tty */	2042	/* check whether we're reopening an existing tty */
2043	tty = tty_driver_lookup_tty(driver, inode, index);	2043	tty = tty_driver_lookup_tty(driver, filp, index);
2044	if (IS_ERR(tty)) {	2044	if (IS_ERR(tty)) {
2045	mutex_unlock(&tty_mutex);	2045	mutex_unlock(&tty_mutex);
2046	goto out;	2046	goto out;

drivers/usb/serial/option.c+148−7

@@ -375,18 +375,22 @@ static void option_instat_callback(struct urb *urb); · 374 unmodified lines
375	#define HAIER_PRODUCT_CE81B 0x10f8	375	#define HAIER_PRODUCT_CE81B 0x10f8
376	#define HAIER_PRODUCT_CE100 0x2009	376	#define HAIER_PRODUCT_CE100 0x2009
377		377
378	/* Cinterion (formerly Siemens) products */	378	/* Gemalto's Cinterion products (formerly Siemens) */
379	#define SIEMENS_VENDOR_ID 0x0681	379	#define SIEMENS_VENDOR_ID 0x0681
380	#define CINTERION_VENDOR_ID 0x1e2d	380	#define CINTERION_VENDOR_ID 0x1e2d
		381	#define CINTERION_PRODUCT_HC25_MDMNET 0x0040
381	#define CINTERION_PRODUCT_HC25_MDM 0x0047	382	#define CINTERION_PRODUCT_HC25_MDM 0x0047
382	#define CINTERION_PRODUCT_HC25_MDMNET 0x0040	383	#define CINTERION_PRODUCT_HC28_MDMNET 0x004A /* same for HC28J */
383	#define CINTERION_PRODUCT_HC28_MDM 0x004C	384	#define CINTERION_PRODUCT_HC28_MDM 0x004C
384	#define CINTERION_PRODUCT_HC28_MDMNET 0x004A /* same for HC28J */
385	#define CINTERION_PRODUCT_EU3_E 0x0051	385	#define CINTERION_PRODUCT_EU3_E 0x0051
386	#define CINTERION_PRODUCT_EU3_P 0x0052	386	#define CINTERION_PRODUCT_EU3_P 0x0052
387	#define CINTERION_PRODUCT_PH8 0x0053	387	#define CINTERION_PRODUCT_PH8 0x0053
388	#define CINTERION_PRODUCT_AHXX 0x0055	388	#define CINTERION_PRODUCT_AHXX 0x0055
389	#define CINTERION_PRODUCT_PLXX 0x0060	389	#define CINTERION_PRODUCT_PLXX 0x0060
		390	#define CINTERION_PRODUCT_PH8_2RMNET 0x0082
		391	#define CINTERION_PRODUCT_PH8_AUDIO 0x0083
		392	#define CINTERION_PRODUCT_AHXX_2RMNET 0x0084
		393	#define CINTERION_PRODUCT_AHXX_AUDIO 0x0085
390		394
391	/* Olivetti products */	395	/* Olivetti products */
392	#define OLIVETTI_VENDOR_ID 0x0b3c	396	#define OLIVETTI_VENDOR_ID 0x0b3c
@@ -633,6 +637,10 @@ static const struct option_blacklist_info telit_le922_blacklist_usbcfg3 = { · 240 unmodified lines
633	.reserved = BIT(1) \| BIT(2) \| BIT(3),	637	.reserved = BIT(1) \| BIT(2) \| BIT(3),
634	};	638	};
635		639
		640	static const struct option_blacklist_info cinterion_rmnet2_blacklist = {
		641	.reserved = BIT(4) \| BIT(5),
		642	};
		643
636	static const struct usb_device_id option_ids[] = {	644	static const struct usb_device_id option_ids[] = {
637	{ USB_DEVICE(OPTION_VENDOR_ID, OPTION_PRODUCT_COLT) },	645	{ USB_DEVICE(OPTION_VENDOR_ID, OPTION_PRODUCT_COLT) },
638	{ USB_DEVICE(OPTION_VENDOR_ID, OPTION_PRODUCT_RICOLA) },	646	{ USB_DEVICE(OPTION_VENDOR_ID, OPTION_PRODUCT_RICOLA) },
@@ -1602,7 +1610,79 @@ static const struct usb_device_id option_ids[] = { · 963 unmodified lines
1602	.driver_info = (kernel_ulong_t)&net_intf3_blacklist },	1610	.driver_info = (kernel_ulong_t)&net_intf3_blacklist },
1603	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0x0178, 0xff, 0xff, 0xff),	1611	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0x0178, 0xff, 0xff, 0xff),
1604	.driver_info = (kernel_ulong_t)&net_intf3_blacklist },	1612	.driver_info = (kernel_ulong_t)&net_intf3_blacklist },
1605	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xffe9, 0xff, 0xff, 0xff) },	1613	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xff42, 0xff, 0xff, 0xff) },
		1614	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xff43, 0xff, 0xff, 0xff) },
		1615	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xff44, 0xff, 0xff, 0xff) },
		1616	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xff45, 0xff, 0xff, 0xff) },
		1617	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xff46, 0xff, 0xff, 0xff) },
		1618	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xff47, 0xff, 0xff, 0xff) },
		1619	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xff48, 0xff, 0xff, 0xff) },
		1620	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xff49, 0xff, 0xff, 0xff) },
		1621	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xff4a, 0xff, 0xff, 0xff) },
		1622	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xff4b, 0xff, 0xff, 0xff) },
		1623	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xff4c, 0xff, 0xff, 0xff) },
		1624	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xff4d, 0xff, 0xff, 0xff) },
		1625	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xff4e, 0xff, 0xff, 0xff) },
		1626	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xff4f, 0xff, 0xff, 0xff) },
		1627	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xff50, 0xff, 0xff, 0xff) },
		1628	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xff51, 0xff, 0xff, 0xff) },
		1629	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xff52, 0xff, 0xff, 0xff) },
		1630	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xff53, 0xff, 0xff, 0xff) },
		1631	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xff54, 0xff, 0xff, 0xff) },
		1632	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xff55, 0xff, 0xff, 0xff) },
		1633	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xff56, 0xff, 0xff, 0xff) },
		1634	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xff57, 0xff, 0xff, 0xff) },
		1635	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xff58, 0xff, 0xff, 0xff) },
		1636	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xff59, 0xff, 0xff, 0xff) },
		1637	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xff5a, 0xff, 0xff, 0xff) },
		1638	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xff5b, 0xff, 0xff, 0xff) },
		1639	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xff5c, 0xff, 0xff, 0xff) },
		1640	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xff5d, 0xff, 0xff, 0xff) },
		1641	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xff5e, 0xff, 0xff, 0xff) },
		1642	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xff5f, 0xff, 0xff, 0xff) },
		1643	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xff60, 0xff, 0xff, 0xff) },
		1644	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xff61, 0xff, 0xff, 0xff) },
		1645	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xff62, 0xff, 0xff, 0xff) },
		1646	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xff63, 0xff, 0xff, 0xff) },
		1647	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xff64, 0xff, 0xff, 0xff) },
		1648	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xff65, 0xff, 0xff, 0xff) },
		1649	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xff66, 0xff, 0xff, 0xff) },
		1650	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xff67, 0xff, 0xff, 0xff) },
		1651	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xff68, 0xff, 0xff, 0xff) },
		1652	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xff69, 0xff, 0xff, 0xff) },
		1653	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xff6a, 0xff, 0xff, 0xff) },
		1654	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xff6b, 0xff, 0xff, 0xff) },
		1655	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xff6c, 0xff, 0xff, 0xff) },
		1656	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xff6d, 0xff, 0xff, 0xff) },
		1657	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xff6e, 0xff, 0xff, 0xff) },
		1658	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xff6f, 0xff, 0xff, 0xff) },
		1659	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xff70, 0xff, 0xff, 0xff) },
		1660	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xff71, 0xff, 0xff, 0xff) },
		1661	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xff72, 0xff, 0xff, 0xff) },
		1662	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xff73, 0xff, 0xff, 0xff) },
		1663	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xff74, 0xff, 0xff, 0xff) },
		1664	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xff75, 0xff, 0xff, 0xff) },
		1665	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xff76, 0xff, 0xff, 0xff) },
		1666	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xff77, 0xff, 0xff, 0xff) },
		1667	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xff78, 0xff, 0xff, 0xff) },
		1668	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xff79, 0xff, 0xff, 0xff) },
		1669	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xff7a, 0xff, 0xff, 0xff) },
		1670	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xff7b, 0xff, 0xff, 0xff) },
		1671	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xff7c, 0xff, 0xff, 0xff) },
		1672	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xff7d, 0xff, 0xff, 0xff) },
		1673	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xff7e, 0xff, 0xff, 0xff) },
		1674	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xff7f, 0xff, 0xff, 0xff) },
		1675	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xff80, 0xff, 0xff, 0xff) },
		1676	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xff81, 0xff, 0xff, 0xff) },
		1677	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xff82, 0xff, 0xff, 0xff) },
		1678	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xff83, 0xff, 0xff, 0xff) },
		1679	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xff84, 0xff, 0xff, 0xff) },
		1680	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xff85, 0xff, 0xff, 0xff) },
		1681	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xff86, 0xff, 0xff, 0xff) },
		1682	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xff87, 0xff, 0xff, 0xff) },
		1683	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xff88, 0xff, 0xff, 0xff) },
		1684	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xff89, 0xff, 0xff, 0xff) },
		1685	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xff8a, 0xff, 0xff, 0xff) },
1606	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xff8b, 0xff, 0xff, 0xff) },	1686	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xff8b, 0xff, 0xff, 0xff) },
1607	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xff8c, 0xff, 0xff, 0xff) },	1687	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xff8c, 0xff, 0xff, 0xff) },
1608	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xff8d, 0xff, 0xff, 0xff) },	1688	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xff8d, 0xff, 0xff, 0xff) },
@@ -1613,6 +1693,61 @@ static const struct usb_device_id option_ids[] = { · 4 unmodified lines
1613	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xff92, 0xff, 0xff, 0xff) },	1693	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xff92, 0xff, 0xff, 0xff) },
1614	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xff93, 0xff, 0xff, 0xff) },	1694	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xff93, 0xff, 0xff, 0xff) },
1615	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xff94, 0xff, 0xff, 0xff) },	1695	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xff94, 0xff, 0xff, 0xff) },
		1696	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xff9f, 0xff, 0xff, 0xff) },
		1697	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xffa0, 0xff, 0xff, 0xff) },
		1698	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xffa1, 0xff, 0xff, 0xff) },
		1699	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xffa2, 0xff, 0xff, 0xff) },
		1700	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xffa3, 0xff, 0xff, 0xff) },
		1701	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xffa4, 0xff, 0xff, 0xff) },
		1702	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xffa5, 0xff, 0xff, 0xff) },
		1703	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xffa6, 0xff, 0xff, 0xff) },
		1704	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xffa7, 0xff, 0xff, 0xff) },
		1705	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xffa8, 0xff, 0xff, 0xff) },
		1706	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xffa9, 0xff, 0xff, 0xff) },
		1707	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xffaa, 0xff, 0xff, 0xff) },
		1708	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xffab, 0xff, 0xff, 0xff) },
		1709	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xffac, 0xff, 0xff, 0xff) },
		1710	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xffae, 0xff, 0xff, 0xff) },
		1711	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xffaf, 0xff, 0xff, 0xff) },
		1712	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xffb0, 0xff, 0xff, 0xff) },
		1713	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xffb1, 0xff, 0xff, 0xff) },
		1714	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xffb2, 0xff, 0xff, 0xff) },
		1715	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xffb3, 0xff, 0xff, 0xff) },
		1716	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xffb4, 0xff, 0xff, 0xff) },
		1717	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xffb5, 0xff, 0xff, 0xff) },
		1718	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xffb6, 0xff, 0xff, 0xff) },
		1719	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xffb7, 0xff, 0xff, 0xff) },
		1720	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xffb8, 0xff, 0xff, 0xff) },
		1721	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xffb9, 0xff, 0xff, 0xff) },
		1722	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xffba, 0xff, 0xff, 0xff) },
		1723	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xffbb, 0xff, 0xff, 0xff) },
		1724	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xffbc, 0xff, 0xff, 0xff) },
		1725	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xffbd, 0xff, 0xff, 0xff) },
		1726	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xffbe, 0xff, 0xff, 0xff) },
		1727	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xffbf, 0xff, 0xff, 0xff) },
		1728	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xffc0, 0xff, 0xff, 0xff) },
		1729	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xffc1, 0xff, 0xff, 0xff) },
		1730	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xffc2, 0xff, 0xff, 0xff) },
		1731	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xffc3, 0xff, 0xff, 0xff) },
		1732	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xffc4, 0xff, 0xff, 0xff) },
		1733	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xffc5, 0xff, 0xff, 0xff) },
		1734	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xffc6, 0xff, 0xff, 0xff) },
		1735	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xffc7, 0xff, 0xff, 0xff) },
		1736	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xffc8, 0xff, 0xff, 0xff) },
		1737	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xffc9, 0xff, 0xff, 0xff) },
		1738	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xffca, 0xff, 0xff, 0xff) },
		1739	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xffcb, 0xff, 0xff, 0xff) },
		1740	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xffcc, 0xff, 0xff, 0xff) },
		1741	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xffcd, 0xff, 0xff, 0xff) },
		1742	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xffce, 0xff, 0xff, 0xff) },
		1743	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xffcf, 0xff, 0xff, 0xff) },
		1744	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xffd0, 0xff, 0xff, 0xff) },
		1745	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xffd1, 0xff, 0xff, 0xff) },
		1746	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xffd2, 0xff, 0xff, 0xff) },
		1747	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xffd3, 0xff, 0xff, 0xff) },
		1748	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xffd4, 0xff, 0xff, 0xff) },
		1749	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xffd5, 0xff, 0xff, 0xff) },
		1750	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xffe9, 0xff, 0xff, 0xff) },
1616	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xffec, 0xff, 0xff, 0xff) },	1751	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xffec, 0xff, 0xff, 0xff) },
1617	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xffee, 0xff, 0xff, 0xff) },	1752	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xffee, 0xff, 0xff, 0xff) },
1618	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xfff6, 0xff, 0xff, 0xff) },	1753	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xfff6, 0xff, 0xff, 0xff) },
@@ -1712,7 +1847,13 @@ static const struct usb_device_id option_ids[] = { · 93 unmodified lines
1712	{ USB_DEVICE_INTERFACE_CLASS(CINTERION_VENDOR_ID, CINTERION_PRODUCT_AHXX, 0xff) },	1847	{ USB_DEVICE_INTERFACE_CLASS(CINTERION_VENDOR_ID, CINTERION_PRODUCT_AHXX, 0xff) },
1713	{ USB_DEVICE(CINTERION_VENDOR_ID, CINTERION_PRODUCT_PLXX),	1848	{ USB_DEVICE(CINTERION_VENDOR_ID, CINTERION_PRODUCT_PLXX),
1714	.driver_info = (kernel_ulong_t)&net_intf4_blacklist },	1849	.driver_info = (kernel_ulong_t)&net_intf4_blacklist },
1715	{ USB_DEVICE(CINTERION_VENDOR_ID, CINTERION_PRODUCT_HC28_MDM) },	1850	{ USB_DEVICE_INTERFACE_CLASS(CINTERION_VENDOR_ID, CINTERION_PRODUCT_PH8_2RMNET, 0xff),
		1851	.driver_info = (kernel_ulong_t)&cinterion_rmnet2_blacklist },
		1852	{ USB_DEVICE_INTERFACE_CLASS(CINTERION_VENDOR_ID, CINTERION_PRODUCT_PH8_AUDIO, 0xff),
		1853	.driver_info = (kernel_ulong_t)&net_intf4_blacklist },
		1854	{ USB_DEVICE_INTERFACE_CLASS(CINTERION_VENDOR_ID, CINTERION_PRODUCT_AHXX_2RMNET, 0xff) },
		1855	{ USB_DEVICE_INTERFACE_CLASS(CINTERION_VENDOR_ID, CINTERION_PRODUCT_AHXX_AUDIO, 0xff) },
		1856	{ USB_DEVICE(CINTERION_VENDOR_ID, CINTERION_PRODUCT_HC28_MDM) },
1716	{ USB_DEVICE(CINTERION_VENDOR_ID, CINTERION_PRODUCT_HC28_MDMNET) },	1857	{ USB_DEVICE(CINTERION_VENDOR_ID, CINTERION_PRODUCT_HC28_MDMNET) },
1717	{ USB_DEVICE(SIEMENS_VENDOR_ID, CINTERION_PRODUCT_HC25_MDM) },	1858	{ USB_DEVICE(SIEMENS_VENDOR_ID, CINTERION_PRODUCT_HC25_MDM) },
1718	{ USB_DEVICE(SIEMENS_VENDOR_ID, CINTERION_PRODUCT_HC25_MDMNET) },	1859	{ USB_DEVICE(SIEMENS_VENDOR_ID, CINTERION_PRODUCT_HC25_MDMNET) },

fs/ceph/mds_client.c+2−4

 	     atomic_read(&s->s_ref), atomic_read(&s->s_ref)-1);
 	if (atomic_dec_and_test(&s->s_ref)) {
 		if (s->s_auth.authorizer)
-			ceph_auth_destroy_authorizer(
+			ceph_auth_destroy_authorizer(s->s_auth.authorizer);
-				s->s_mdsc->fsc->client->monc.auth,
-				s->s_auth.authorizer);
 		kfree(s);
 	}
 }
 	struct ceph_auth_handshake *auth = &s->s_auth;
 	if (force_new && auth->authorizer) {
-		ceph_auth_destroy_authorizer(ac, auth->authorizer);
+		ceph_auth_destroy_authorizer(auth->authorizer);
 		auth->authorizer = NULL;
 	}
 	if (!auth->authorizer) {

fs/devpts/inode.c+12−41

@@ -604,8 +604,7 @@ void devpts_put_ref(struct pts_fs_info *fsi) · 603 unmodified lines
604	*	604	*
605	* The created inode is returned. Remove it from /dev/pts/ by devpts_pty_kill.	605	* The created inode is returned. Remove it from /dev/pts/ by devpts_pty_kill.
606	*/	606	*/
607	struct inode devpts_pty_new(struct pts_fs_info fsi, dev_t device, int index,	607	struct dentry devpts_pty_new(struct pts_fs_info fsi, int index, void *priv)
608	void *priv)
609	{	608	{
610	struct dentry *dentry;	609	struct dentry *dentry;
611	struct super_block *sb;	610	struct super_block *sb;
@@ -629,25 +628,21 @@ struct inode devpts_pty_new(struct pts_fs_info fsi, dev_t device, int index, · 17 unmodified lines
629	inode->i_uid = opts->setuid ? opts->uid : current_fsuid();	628	inode->i_uid = opts->setuid ? opts->uid : current_fsuid();
630	inode->i_gid = opts->setgid ? opts->gid : current_fsgid();	629	inode->i_gid = opts->setgid ? opts->gid : current_fsgid();
631	inode->i_mtime = inode->i_atime = inode->i_ctime = CURRENT_TIME;	630	inode->i_mtime = inode->i_atime = inode->i_ctime = CURRENT_TIME;
632	init_special_inode(inode, S_IFCHR\|opts->mode, device);	631	init_special_inode(inode, S_IFCHR\|opts->mode, MKDEV(UNIX98_PTY_SLAVE_MAJOR, index));
633	inode->i_private = priv;
634		632
635	sprintf(s, "%d", index);	633	sprintf(s, "%d", index);
636		634
637	inode_lock(d_inode(root));
638
639	dentry = d_alloc_name(root, s);	635	dentry = d_alloc_name(root, s);
640	if (dentry) {	636	if (dentry) {
		637	dentry->d_fsdata = priv;
641	d_add(dentry, inode);	638	d_add(dentry, inode);
642	fsnotify_create(d_inode(root), dentry);	639	fsnotify_create(d_inode(root), dentry);
643	} else {	640	} else {
644	iput(inode);	641	iput(inode);
645	inode = ERR_PTR(-ENOMEM);	642	dentry = ERR_PTR(-ENOMEM);
646	}	643	}
647		644
648	inode_unlock(d_inode(root));	645	return dentry;
649
650	return inode;
651	}	646	}
652		647
653	/**	648	/**
@@ -656,24 +651,10 @@ struct inode devpts_pty_new(struct pts_fs_info fsi, dev_t device, int index, · 2 unmodified lines
656	*	651	*
657	* Returns whatever was passed as priv in devpts_pty_new for a given inode.	652	* Returns whatever was passed as priv in devpts_pty_new for a given inode.
658	*/	653	*/
659	void devpts_get_priv(struct inode pts_inode)	654	void devpts_get_priv(struct dentry dentry)
660	{	655	{
661	struct dentry *dentry;	656	WARN_ON_ONCE(dentry->d_sb->s_magic != DEVPTS_SUPER_MAGIC);
662	void *priv = NULL;	657	return dentry->d_fsdata;
663
664	BUG_ON(pts_inode->i_rdev == MKDEV(TTYAUX_MAJOR, PTMX_MINOR));
665
666	/* Ensure dentry has not been deleted by devpts_pty_kill() */
667	dentry = d_find_alias(pts_inode);
668	if (!dentry)
669	return NULL;
670
671	if (pts_inode->i_sb->s_magic == DEVPTS_SUPER_MAGIC)
672	priv = pts_inode->i_private;
673
674	dput(dentry);
675
676	return priv;
677	}	658	}
678		659
679	/**	660	/**
@@ -682,24 +663,14 @@ void devpts_get_priv(struct inode pts_inode) · 2 unmodified lines
682	*	663	*
683	* This is an inverse operation of devpts_pty_new.	664	* This is an inverse operation of devpts_pty_new.
684	*/	665	*/
685	void devpts_pty_kill(struct inode *inode)	666	void devpts_pty_kill(struct dentry *dentry)
686	{	667	{
687	struct super_block *sb = pts_sb_from_inode(inode);	668	WARN_ON_ONCE(dentry->d_sb->s_magic != DEVPTS_SUPER_MAGIC);
688	struct dentry *root = sb->s_root;
689	struct dentry *dentry;
690		669
691	BUG_ON(inode->i_rdev == MKDEV(TTYAUX_MAJOR, PTMX_MINOR));	670	dentry->d_fsdata = NULL;
692		671	drop_nlink(dentry->d_inode);
693	inode_lock(d_inode(root));
694
695	dentry = d_find_alias(inode);
696
697	drop_nlink(inode);
698	d_delete(dentry);	672	d_delete(dentry);
699	dput(dentry); /* d_alloc_name() in devpts_pty_new() */	673	dput(dentry); /* d_alloc_name() in devpts_pty_new() */
700	dput(dentry); /* d_find_alias above */
701
702	inode_unlock(d_inode(root));
703	}	674	}
704		675
705	static int __init init_devpts_fs(void)	676	static int __init init_devpts_fs(void)

fs/ocfs2/dlm/dlmmaster.c+2−0

@@ -2455,6 +2455,8 @@ int dlm_deref_lockres_done_handler(struct o2net_msg msg, u32 len, void data, · 2454 unmodified lines
2455		2455
2456	spin_unlock(&dlm->spinlock);	2456	spin_unlock(&dlm->spinlock);
2457		2457
		2458	ret = 0;
		2459
2458	done:	2460	done:
2459	dlm_put(dlm);	2461	dlm_put(dlm);
2460	return ret;	2462	return ret;

fs/proc/task_mmu.c+30−3

@@ -1518,6 +1518,32 @@ static struct page can_gather_numa_stats(pte_t pte, struct vm_area_struct vma, · 1517 unmodified lines
1518	return page;	1518	return page;
1519	}	1519	}
1520		1520
		1521	#ifdef CONFIG_TRANSPARENT_HUGEPAGE
		1522	static struct page *can_gather_numa_stats_pmd(pmd_t pmd,
		1523	struct vm_area_struct *vma,
		1524	unsigned long addr)
		1525	{
		1526	struct page *page;
		1527	int nid;
		1528
		1529	if (!pmd_present(pmd))
		1530	return NULL;
		1531
		1532	page = vm_normal_page_pmd(vma, addr, pmd);
		1533	if (!page)
		1534	return NULL;
		1535
		1536	if (PageReserved(page))
		1537	return NULL;
		1538
		1539	nid = page_to_nid(page);
		1540	if (!node_isset(nid, node_states[N_MEMORY]))
		1541	return NULL;
		1542
		1543	return page;
		1544	}
		1545	#endif
		1546
1521	static int gather_pte_stats(pmd_t *pmd, unsigned long addr,	1547	static int gather_pte_stats(pmd_t *pmd, unsigned long addr,
1522	unsigned long end, struct mm_walk *walk)	1548	unsigned long end, struct mm_walk *walk)
1523	{	1549	{
@@ -1527,14 +1553,14 @@ static int gather_pte_stats(pmd_t *pmd, unsigned long addr, · 3 unmodified lines
1527	pte_t *orig_pte;	1553	pte_t *orig_pte;
1528	pte_t *pte;	1554	pte_t *pte;
1529		1555
		1556	#ifdef CONFIG_TRANSPARENT_HUGEPAGE
1530	ptl = pmd_trans_huge_lock(pmd, vma);	1557	ptl = pmd_trans_huge_lock(pmd, vma);
1531	if (ptl) {	1558	if (ptl) {
1532	pte_t huge_pte = (pte_t )pmd;
1533	struct page *page;	1559	struct page *page;
1534		1560
1535	page = can_gather_numa_stats(huge_pte, vma, addr);	1561	page = can_gather_numa_stats_pmd(*pmd, vma, addr);
1536	if (page)	1562	if (page)
1537	gather_stats(page, md, pte_dirty(huge_pte),	1563	gather_stats(page, md, pmd_dirty(*pmd),
1538	HPAGE_PMD_SIZE/PAGE_SIZE);	1564	HPAGE_PMD_SIZE/PAGE_SIZE);
1539	spin_unlock(ptl);	1565	spin_unlock(ptl);
1540	return 0;	1566	return 0;
@@ -1542,6 +1568,7 @@ static int gather_pte_stats(pmd_t *pmd, unsigned long addr, · 1 unmodified line
1542		1568
1543	if (pmd_trans_unstable(pmd))	1569	if (pmd_trans_unstable(pmd))
1544	return 0;	1570	return 0;
		1571	#endif
1545	orig_pte = pte = pte_offset_map_lock(walk->mm, pmd, addr, &ptl);	1572	orig_pte = pte = pte_offset_map_lock(walk->mm, pmd, addr, &ptl);
1546	do {	1573	do {
1547	struct page page = can_gather_numa_stats(pte, vma, addr);	1574	struct page page = can_gather_numa_stats(pte, vma, addr);

include/linux/ceph/auth.h+5−5

  */
 struct ceph_auth_client;
-struct ceph_authorizer;
 struct ceph_msg;
+struct ceph_authorizer {
+	void (*destroy)(struct ceph_authorizer *);
+};
 struct ceph_auth_handshake {
 	struct ceph_authorizer *authorizer;
 	void *authorizer_buf;
 				 struct ceph_auth_handshake *auth);
 	int (*verify_authorizer_reply)(struct ceph_auth_client *ac,
 				       struct ceph_authorizer *a, size_t len);
-	void (*destroy_authorizer)(struct ceph_auth_client *ac,
-				   struct ceph_authorizer *a);
 	void (*invalidate_authorizer)(struct ceph_auth_client *ac,
 				      int peer_type);
 extern int ceph_auth_create_authorizer(struct ceph_auth_client *ac,
 				       int peer_type,
 				       struct ceph_auth_handshake *auth);
-extern void ceph_auth_destroy_authorizer(struct ceph_auth_client *ac,
+void ceph_auth_destroy_authorizer(struct ceph_authorizer *a);
-					 struct ceph_authorizer *a);
 extern int ceph_auth_update_authorizer(struct ceph_auth_client *ac,
 				       int peer_type,
 				       struct ceph_auth_handshake *a);

include/linux/ceph/osd_client.h+0−1

@@ -16,7 +16,6 @@ struct ceph_msg; · 15 unmodified lines
16	struct ceph_snap_context;	16	struct ceph_snap_context;
17	struct ceph_osd_request;	17	struct ceph_osd_request;
18	struct ceph_osd_client;	18	struct ceph_osd_client;
19	struct ceph_authorizer;
20		19
21	/*	20	/*
22	* completion callback for async writepages	21	* completion callback for async writepages

include/linux/cgroup-defs.h+1−0

@@ -444,6 +444,7 @@ struct cgroup_subsys { · 443 unmodified lines
444	int (can_attach)(struct cgroup_taskset tset);	444	int (can_attach)(struct cgroup_taskset tset);
445	void (cancel_attach)(struct cgroup_taskset tset);	445	void (cancel_attach)(struct cgroup_taskset tset);
446	void (attach)(struct cgroup_taskset tset);	446	void (attach)(struct cgroup_taskset tset);
		447	void (*post_attach)(void);
447	int (can_fork)(struct task_struct task);	448	int (can_fork)(struct task_struct task);
448	void (cancel_fork)(struct task_struct task);	449	void (cancel_fork)(struct task_struct task);
449	void (fork)(struct task_struct task);	450	void (fork)(struct task_struct task);

include/linux/cpuset.h+0−6

 	task_unlock(current);
 }
-extern void cpuset_post_attach_flush(void);
 #else /* !CONFIG_CPUSETS */
 static inline bool cpusets_enabled(void) { return false; }
 	return false;
 }
-static inline void cpuset_post_attach_flush(void)
-{
-}
 #endif /* !CONFIG_CPUSETS */
 #endif /* _LINUX_CPUSET_H */

include/linux/devpts_fs.h+3−3

@@ -27,11 +27,11 @@ int devpts_new_index(struct pts_fs_info *); · 26 unmodified lines
27	void devpts_kill_index(struct pts_fs_info *, int);	27	void devpts_kill_index(struct pts_fs_info *, int);
28		28
29	/* mknod in devpts */	29	/* mknod in devpts */
30	struct inode devpts_pty_new(struct pts_fs_info , dev_t, int, void *);	30	struct dentry devpts_pty_new(struct pts_fs_info , int, void *);
31	/* get private structure */	31	/* get private structure */
32	void devpts_get_priv(struct inode pts_inode);	32	void devpts_get_priv(struct dentry );
33	/* unlink */	33	/* unlink */
34	void devpts_pty_kill(struct inode *inode);	34	void devpts_pty_kill(struct dentry *);
35		35
36	#endif	36	#endif
37		37

include/linux/huge_mm.h+5−0

 }
 struct page *get_huge_zero_page(void);
+void put_huge_zero_page(void);
 #else /* CONFIG_TRANSPARENT_HUGEPAGE */
 #define HPAGE_PMD_SHIFT ({ BUILD_BUG(); 0; })
 	return false;
 }
+static inline void put_huge_zero_page(void)
+{
+	BUILD_BUG();
+}
 static inline struct page *follow_devmap_pmd(struct vm_area_struct *vma,
 		unsigned long addr, pmd_t *pmd, int flags)

include/linux/lockdep.h+5−3

  * We record lock dependency chains, so that we can cache them:
  */
 struct lock_chain {
-	u8				irq_context;
+	/* see BUILD_BUG_ON()s in lookup_chain_cache() */
-	u8				depth;
+	unsigned int			irq_context :  2,
-	u16				base;
+					depth       :  6,
+					base	    : 24;
+	/* 4 byte hole */
 	struct hlist_node		entry;
 	u64				chain_key;
 };

include/linux/mlx5/device.h+11−0

@@ -392,6 +392,17 @@ enum { · 391 unmodified lines
392	MLX5_CAP_OFF_CMDIF_CSUM = 46,	392	MLX5_CAP_OFF_CMDIF_CSUM = 46,
393	};	393	};
394		394
		395	enum {
		396	/*
		397	* Max wqe size for rdma read is 512 bytes, so this
		398	* limits our max_sge_rd as the wqe needs to fit:
		399	* - ctrl segment (16 bytes)
		400	* - rdma segment (16 bytes)
		401	* - scatter elements (16 bytes each)
		402	*/
		403	MLX5_MAX_SGE_RD = (512 - 16 - 16) / 16
		404	};
		405
395	struct mlx5_inbox_hdr {	406	struct mlx5_inbox_hdr {
396	__be16 opcode;	407	__be16 opcode;
397	u8 rsvd[4];	408	u8 rsvd[4];

include/linux/mlx5/driver.h+4−3

 };
 enum mlx5_interface_state {
-	MLX5_INTERFACE_STATE_DOWN,
+	MLX5_INTERFACE_STATE_DOWN = BIT(0),
-	MLX5_INTERFACE_STATE_UP,
+	MLX5_INTERFACE_STATE_UP = BIT(1),
+	MLX5_INTERFACE_STATE_SHUTDOWN = BIT(2),
 };
 enum mlx5_pci_status {
 	enum mlx5_device_state	state;
 	/* sync interface state */
 	struct mutex		intf_state_mutex;
-	enum mlx5_interface_state interface_state;
+	unsigned long		intf_state;
 	void			(*event) (struct mlx5_core_dev *dev,
 					  enum mlx5_dev_event event,
 					  unsigned long param);

include/linux/mlx5/port.h+3−3

@@ -54,9 +54,9 @@ int mlx5_set_port_admin_status(struct mlx5_core_dev *dev, · 53 unmodified lines
54	int mlx5_query_port_admin_status(struct mlx5_core_dev *dev,	54	int mlx5_query_port_admin_status(struct mlx5_core_dev *dev,
55	enum mlx5_port_status *status);	55	enum mlx5_port_status *status);
56		56
57	int mlx5_set_port_mtu(struct mlx5_core_dev *dev, int mtu, u8 port);	57	int mlx5_set_port_mtu(struct mlx5_core_dev *dev, u16 mtu, u8 port);
58	void mlx5_query_port_max_mtu(struct mlx5_core_dev dev, int max_mtu, u8 port);	58	void mlx5_query_port_max_mtu(struct mlx5_core_dev dev, u16 max_mtu, u8 port);
59	void mlx5_query_port_oper_mtu(struct mlx5_core_dev dev, int oper_mtu,	59	void mlx5_query_port_oper_mtu(struct mlx5_core_dev dev, u16 oper_mtu,
60	u8 port);	60	u8 port);
61		61
62	int mlx5_query_port_vl_hw_cap(struct mlx5_core_dev *dev,	62	int mlx5_query_port_vl_hw_cap(struct mlx5_core_dev *dev,

include/linux/mlx5/vport.h+2−0

 				     u16 vport, u8 *addr);
 int mlx5_modify_nic_vport_mac_address(struct mlx5_core_dev *dev,
 				      u16 vport, u8 *addr);
+int mlx5_query_nic_vport_mtu(struct mlx5_core_dev *mdev, u16 *mtu);
+int mlx5_modify_nic_vport_mtu(struct mlx5_core_dev *mdev, u16 mtu);
 int mlx5_query_nic_vport_system_image_guid(struct mlx5_core_dev *mdev,
 					   u64 *system_image_guid);
 int mlx5_query_nic_vport_node_guid(struct mlx5_core_dev *mdev, u64 *node_guid);

include/linux/mm.h+4−0

 	page = compound_head(page);
 	if (atomic_read(compound_mapcount_ptr(page)) >= 0)
 		return true;
+	if (PageHuge(page))
+		return false;
 	for (i = 0; i < hpage_nr_pages(page); i++) {
 		if (atomic_read(&page[i]._mapcount) >= 0)
 			return true;
 struct page *vm_normal_page(struct vm_area_struct *vma, unsigned long addr,
 		pte_t pte);
+struct page *vm_normal_page_pmd(struct vm_area_struct *vma, unsigned long addr,
+				pmd_t pmd);
 int zap_vma_ptes(struct vm_area_struct *vma, unsigned long address,
 		unsigned long size);

include/linux/tty_driver.h+2−2

@@ -7,7 +7,7 @@ · 6 unmodified lines
7	* defined; unless noted otherwise, they are optional, and can be	7	* defined; unless noted otherwise, they are optional, and can be
8	* filled in with a null pointer.	8	* filled in with a null pointer.
9	*	9	*
10	* struct tty_struct * (lookup)(struct tty_driver self, int idx)	10	* struct tty_struct * (lookup)(struct tty_driver self, struct file *, int idx)
11	*	11	*
12	* Return the tty device corresponding to idx, NULL if there is not	12	* Return the tty device corresponding to idx, NULL if there is not
13	* one currently in use and an ERR_PTR value on error. Called under	13	* one currently in use and an ERR_PTR value on error. Called under
@@ -250,7 +250,7 @@ struct serial_icounter_struct; · 236 unmodified lines
250		250
251	struct tty_operations {	251	struct tty_operations {
252	struct tty_struct * (lookup)(struct tty_driver driver,	252	struct tty_struct * (lookup)(struct tty_driver driver,
253	struct inode *inode, int idx);	253	struct file *filp, int idx);
254	int (install)(struct tty_driver driver, struct tty_struct *tty);	254	int (install)(struct tty_driver driver, struct tty_struct *tty);
255	void (remove)(struct tty_driver driver, struct tty_struct *tty);	255	void (remove)(struct tty_driver driver, struct tty_struct *tty);
256	int (open)(struct tty_struct tty, struct file * filp);	256	int (open)(struct tty_struct tty, struct file * filp);

include/media/videobuf2-core.h+8−0

 /**
  * struct vb2_ops - driver-specific callbacks
  *
+ * @verify_planes_array: Verify that a given user space structure contains
+ *			enough planes for the buffer. This is called
+ *			for each dequeued buffer.
  * @fill_user_buffer:	given a vb2_buffer fill in the userspace structure.
  *			For V4L2 this is a struct v4l2_buffer.
  * @fill_vb2_buffer:	given a userspace structure, fill in the vb2_buffer.
  *			the vb2_buffer struct.
  */
 struct vb2_buf_ops {
+	int (*verify_planes_array)(struct vb2_buffer *vb, const void *pb);
 	void (*fill_user_buffer)(struct vb2_buffer *vb, void *pb);
 	int (*fill_vb2_buffer)(struct vb2_buffer *vb, const void *pb,
 				struct vb2_plane *planes);
  * @fileio_read_once:		report EOF after reading the first buffer
  * @fileio_write_immediately:	queue buffer after each write() call
  * @allow_zero_bytesused:	allow bytesused == 0 to be passed to the driver
+ * @quirk_poll_must_check_waiting_for_buffers: Return POLLERR at poll when QBUF
+ *              has not been called. This is a vb1 idiom that has been adopted
+ *              also by vb2.
  * @lock:	pointer to a mutex that protects the vb2_queue struct. The
  *		driver can set this to a mutex to let the v4l2 core serialize
  *		the queuing ioctls. If the driver wants to handle locking
 	unsigned			fileio_read_once:1;
 	unsigned			fileio_write_immediately:1;
 	unsigned			allow_zero_bytesused:1;
+	unsigned		   quirk_poll_must_check_waiting_for_buffers:1;
 	struct mutex			*lock;
 	void				*owner;

include/net/switchdev.h+4−0

 	struct net_device *orig_dev;
 	enum switchdev_attr_id id;
 	u32 flags;
+	void *complete_priv;
+	void (*complete)(struct net_device *dev, int err, void *priv);
 	union {
 		struct netdev_phys_item_id ppid;	/* PORT_PARENT_ID */
 		u8 stp_state;				/* PORT_STP_STATE */
 	struct net_device *orig_dev;
 	enum switchdev_obj_id id;
 	u32 flags;
+	void *complete_priv;
+	void (*complete)(struct net_device *dev, int err, void *priv);
 };
 /* SWITCHDEV_OBJ_ID_PORT_VLAN */

include/rdma/ib.h+16−0

@@ -34,6 +34,7 @@ · 33 unmodified lines
34	#define _RDMA_IB_H	34	#define _RDMA_IB_H
35		35
36	#include <linux/types.h>	36	#include <linux/types.h>
		37	#include <linux/sched.h>
37		38
38	struct ib_addr {	39	struct ib_addr {
39	union {	40	union {
@@ -86,4 +87,19 @@ struct sockaddr_ib { · 46 unmodified lines
86	__u64 sib_scope_id;	87	__u64 sib_scope_id;
87	};	88	};
88		89
		90	/*
		91	* The IB interfaces that use write() as bi-directional ioctl() are
		92	* fundamentally unsafe, since there are lots of ways to trigger "write()"
		93	* calls from various contexts with elevated privileges. That includes the
		94	* traditional suid executable error message writes, but also various kernel
		95	* interfaces that can write to file descriptors.
		96	*
		97	* This function provides protection for the legacy API by restricting the
		98	* calling context.
		99	*/
		100	static inline bool ib_safe_file_access(struct file *filp)
		101	{
		102	return filp->f_cred == current_cred() && segment_eq(get_fs(), USER_DS);
		103	}
		104
89	#endif /* _RDMA_IB_H */	105	#endif /* _RDMA_IB_H */

include/sound/hda_i915.h+2−3

 #ifdef CONFIG_SND_HDA_I915
 int snd_hdac_set_codec_wakeup(struct hdac_bus *bus, bool enable);
 int snd_hdac_display_power(struct hdac_bus *bus, bool enable);
-int snd_hdac_get_display_clk(struct hdac_bus *bus);
+void snd_hdac_i915_set_bclk(struct hdac_bus *bus);
 int snd_hdac_sync_audio_rate(struct hdac_bus *bus, hda_nid_t nid, int rate);
 int snd_hdac_acomp_get_eld(struct hdac_bus *bus, hda_nid_t nid,
 			   bool *audio_enabled, char *buffer, int max_bytes);
 {
 	return 0;
 }
-static inline int snd_hdac_get_display_clk(struct hdac_bus *bus)
+static inline void snd_hdac_i915_set_bclk(struct hdac_bus *bus)
 {
-	return 0;
 }
 static inline int snd_hdac_sync_audio_rate(struct hdac_bus *bus, hda_nid_t nid,
 					   int rate)

include/uapi/linux/if_macsec.h+2−2

@@ -19,8 +19,8 @@ · 18 unmodified lines
19		19
20	#define MACSEC_MAX_KEY_LEN 128	20	#define MACSEC_MAX_KEY_LEN 128
21		21
22	#define DEFAULT_CIPHER_ID 0x0080020001000001ULL	22	#define MACSEC_DEFAULT_CIPHER_ID 0x0080020001000001ULL
23	#define DEFAULT_CIPHER_ALT 0x0080C20001000001ULL	23	#define MACSEC_DEFAULT_CIPHER_ALT 0x0080C20001000001ULL
24		24
25	#define MACSEC_MIN_ICV_LEN 8	25	#define MACSEC_MIN_ICV_LEN 8
26	#define MACSEC_MAX_ICV_LEN 32	26	#define MACSEC_MAX_ICV_LEN 32

include/uapi/linux/v4l2-dv-timings.h+20−10

 #define V4L2_DV_BT_CEA_3840X2160P24 { \
 	.type = V4L2_DV_BT_656_1120, \
-	V4L2_INIT_BT_TIMINGS(3840, 2160, 0, V4L2_DV_HSYNC_POS_POL, \
+	V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \
+		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
 		297000000, 1276, 88, 296, 8, 10, 72, 0, 0, 0, \
 		V4L2_DV_BT_STD_CEA861, \
 		V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO) \
 #define V4L2_DV_BT_CEA_3840X2160P25 { \
 	.type = V4L2_DV_BT_656_1120, \
-	V4L2_INIT_BT_TIMINGS(3840, 2160, 0, V4L2_DV_HSYNC_POS_POL, \
+	V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \
+		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
 		297000000, 1056, 88, 296, 8, 10, 72, 0, 0, 0, \
 		V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_IS_CE_VIDEO) \
 }
 #define V4L2_DV_BT_CEA_3840X2160P30 { \
 	.type = V4L2_DV_BT_656_1120, \
-	V4L2_INIT_BT_TIMINGS(3840, 2160, 0, V4L2_DV_HSYNC_POS_POL, \
+	V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \
+		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
 		297000000, 176, 88, 296, 8, 10, 72, 0, 0, 0, \
 		V4L2_DV_BT_STD_CEA861, \
 		V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO) \
 #define V4L2_DV_BT_CEA_3840X2160P50 { \
 	.type = V4L2_DV_BT_656_1120, \
-	V4L2_INIT_BT_TIMINGS(3840, 2160, 0, V4L2_DV_HSYNC_POS_POL, \
+	V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \
+		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
 		594000000, 1056, 88, 296, 8, 10, 72, 0, 0, 0, \
 		V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_IS_CE_VIDEO) \
 }
 #define V4L2_DV_BT_CEA_3840X2160P60 { \
 	.type = V4L2_DV_BT_656_1120, \
-	V4L2_INIT_BT_TIMINGS(3840, 2160, 0, V4L2_DV_HSYNC_POS_POL, \
+	V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \
+		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
 		594000000, 176, 88, 296, 8, 10, 72, 0, 0, 0, \
 		V4L2_DV_BT_STD_CEA861, \
 		V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO) \
 #define V4L2_DV_BT_CEA_4096X2160P24 { \
 	.type = V4L2_DV_BT_656_1120, \
-	V4L2_INIT_BT_TIMINGS(4096, 2160, 0, V4L2_DV_HSYNC_POS_POL, \
+	V4L2_INIT_BT_TIMINGS(4096, 2160, 0, \
+		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
 		297000000, 1020, 88, 296, 8, 10, 72, 0, 0, 0, \
 		V4L2_DV_BT_STD_CEA861, \
 		V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO) \
 #define V4L2_DV_BT_CEA_4096X2160P25 { \
 	.type = V4L2_DV_BT_656_1120, \
-	V4L2_INIT_BT_TIMINGS(4096, 2160, 0, V4L2_DV_HSYNC_POS_POL, \
+	V4L2_INIT_BT_TIMINGS(4096, 2160, 0, \
+		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
 		297000000, 968, 88, 128, 8, 10, 72, 0, 0, 0, \
 		V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_IS_CE_VIDEO) \
 }
 #define V4L2_DV_BT_CEA_4096X2160P30 { \
 	.type = V4L2_DV_BT_656_1120, \
-	V4L2_INIT_BT_TIMINGS(4096, 2160, 0, V4L2_DV_HSYNC_POS_POL, \
+	V4L2_INIT_BT_TIMINGS(4096, 2160, 0, \
+		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
 		297000000, 88, 88, 128, 8, 10, 72, 0, 0, 0, \
 		V4L2_DV_BT_STD_CEA861, \
 		V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO) \
 #define V4L2_DV_BT_CEA_4096X2160P50 { \
 	.type = V4L2_DV_BT_656_1120, \
-	V4L2_INIT_BT_TIMINGS(4096, 2160, 0, V4L2_DV_HSYNC_POS_POL, \
+	V4L2_INIT_BT_TIMINGS(4096, 2160, 0, \
+		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
 		594000000, 968, 88, 128, 8, 10, 72, 0, 0, 0, \
 		V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_IS_CE_VIDEO) \
 }
 #define V4L2_DV_BT_CEA_4096X2160P60 { \
 	.type = V4L2_DV_BT_656_1120, \
-	V4L2_INIT_BT_TIMINGS(4096, 2160, 0, V4L2_DV_HSYNC_POS_POL, \
+	V4L2_INIT_BT_TIMINGS(4096, 2160, 0, \
+		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
 		594000000, 88, 88, 128, 8, 10, 72, 0, 0, 0, \
 		V4L2_DV_BT_STD_CEA861, \
 		V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO) \

kernel/bpf/verifier.c+0−1

@@ -2030,7 +2030,6 @@ static int replace_map_fd_with_map_ptr(struct verifier_env *env) · 2029 unmodified lines
2030	if (IS_ERR(map)) {	2030	if (IS_ERR(map)) {
2031	verbose("fd %d is not pointing to valid bpf_map\n",	2031	verbose("fd %d is not pointing to valid bpf_map\n",
2032	insn->imm);	2032	insn->imm);
2033	fdput(f);
2034	return PTR_ERR(map);	2033	return PTR_ERR(map);
2035	}	2034	}
2036		2035

kernel/cgroup.c+5−2

 				    size_t nbytes, loff_t off, bool threadgroup)
 {
 	struct task_struct *tsk;
+	struct cgroup_subsys *ss;
 	struct cgroup *cgrp;
 	pid_t pid;
-	int ret;
+	int ssid, ret;
 	if (kstrtoint(strstrip(buf), 0, &pid) || pid < 0)
 		return -EINVAL;
 	rcu_read_unlock();
 out_unlock_threadgroup:
 	percpu_up_write(&cgroup_threadgroup_rwsem);
+	for_each_subsys(ss, ssid)
+		if (ss->post_attach)
+			ss->post_attach();
 	cgroup_kn_unlock(of->kn);
-	cpuset_post_attach_flush();
 	return ret ?: nbytes;
 }

kernel/cpuset.c+2−2

 #include <asm/uaccess.h>
 #include <linux/atomic.h>
 #include <linux/mutex.h>
-#include <linux/workqueue.h>
 #include <linux/cgroup.h>
 #include <linux/wait.h>
 	}
 }
-void cpuset_post_attach_flush(void)
+static void cpuset_post_attach(void)
 {
 	flush_workqueue(cpuset_migrate_mm_wq);
 }
 	.can_attach	= cpuset_can_attach,
 	.cancel_attach	= cpuset_cancel_attach,
 	.attach		= cpuset_attach,
+	.post_attach	= cpuset_post_attach,
 	.bind		= cpuset_bind,
 	.legacy_cftypes	= files,
 	.early_init	= true,

kernel/events/core.c+38−17

 	if (ret || !write)
 		return ret;
-	if (sysctl_perf_cpu_time_max_percent == 100) {
+	if (sysctl_perf_cpu_time_max_percent == 100 ||
+	    sysctl_perf_cpu_time_max_percent == 0) {
 		printk(KERN_WARNING
 		       "perf: Dynamic interrupt throttling disabled, can hang your system!\n");
 		WRITE_ONCE(perf_sample_allowed_ns, 0);
  * function.
  *
  * Lock order:
+ *    cred_guard_mutex
  *	task_struct::perf_event_mutex
  *	  perf_event_context::mutex
  *	    perf_event::child_mutex;
 find_lively_task_by_vpid(pid_t vpid)
 {
 	struct task_struct *task;
-	int err;
 	rcu_read_lock();
 	if (!vpid)
 	if (!task)
 		return ERR_PTR(-ESRCH);
-	/* Reuse ptrace permission checks for now. */
-	err = -EACCES;
-	if (!ptrace_may_access(task, PTRACE_MODE_READ_REALCREDS))
-		goto errout;
 	return task;
-errout:
-	put_task_struct(task);
-	return ERR_PTR(err);
 }
 /*
 	get_online_cpus();
+	if (task) {
+		err = mutex_lock_interruptible(&task->signal->cred_guard_mutex);
+		if (err)
+			goto err_cpus;
+		/*
+		 * Reuse ptrace permission checks for now.
+		 *
+		 * We must hold cred_guard_mutex across this and any potential
+		 * perf_install_in_context() call for this new event to
+		 * serialize against exec() altering our credentials (and the
+		 * perf_event_exit_task() that could imply).
+		 */
+		err = -EACCES;
+		if (!ptrace_may_access(task, PTRACE_MODE_READ_REALCREDS))
+			goto err_cred;
+	}
 	if (flags & PERF_FLAG_PID_CGROUP)
 		cgroup_fd = pid;
 				 NULL, NULL, cgroup_fd);
 	if (IS_ERR(event)) {
 		err = PTR_ERR(event);
-		goto err_cpus;
+		goto err_cred;
 	}
 	if (is_sampling_event(event)) {
 		goto err_context;
 	}
-	if (task) {
-		put_task_struct(task);
-		task = NULL;
-	}
 	/*
 	 * Look up the group leader (we will attach this event to it):
 	 */
 	WARN_ON_ONCE(ctx->parent_ctx);
+	/*
+	 * This is the point on no return; we cannot fail hereafter. This is
+	 * where we start modifying current state.
+	 */
 	if (move_group) {
 		/*
 		 * See perf_event_ctx_lock() for comments on the details
 		mutex_unlock(&gctx->mutex);
 	mutex_unlock(&ctx->mutex);
+	if (task) {
+		mutex_unlock(&task->signal->cred_guard_mutex);
+		put_task_struct(task);
+	}
 	put_online_cpus();
 	mutex_lock(&current->perf_event_mutex);
 	 */
 	if (!event_file)
 		free_event(event);
+err_cred:
+	if (task)
+		mutex_unlock(&task->signal->cred_guard_mutex);
 err_cpus:
 	put_online_cpus();
 err_task:
 /*
  * When a child task exits, feed back event values to parent events.
+ *
+ * Can be called with cred_guard_mutex held when called from
+ * install_exec_creds().
  */
 void perf_event_exit_task(struct task_struct *child)
 {

kernel/kcov.c+2−1

 #define pr_fmt(fmt) "kcov: " fmt
+#define DISABLE_BRANCH_PROFILING
 #include <linux/compiler.h>
 #include <linux/types.h>
 #include <linux/file.h>
  * Entry point from instrumented code.
  * This is called once per basic-block/edge.
  */
-void __sanitizer_cov_trace_pc(void)
+void notrace __sanitizer_cov_trace_pc(void)
 {
 	struct task_struct *t;
 	enum kcov_mode mode;

kernel/kexec_core.c+5−2

 	VMCOREINFO_OFFSET(page, lru);
 	VMCOREINFO_OFFSET(page, _mapcount);
 	VMCOREINFO_OFFSET(page, private);
+	VMCOREINFO_OFFSET(page, compound_dtor);
+	VMCOREINFO_OFFSET(page, compound_order);
+	VMCOREINFO_OFFSET(page, compound_head);
 	VMCOREINFO_OFFSET(pglist_data, node_zones);
 	VMCOREINFO_OFFSET(pglist_data, nr_zones);
 #ifdef CONFIG_FLAT_NODE_MEM_MAP
 #ifdef CONFIG_X86
 	VMCOREINFO_NUMBER(KERNEL_IMAGE_SIZE);
 #endif
-#ifdef CONFIG_HUGETLBFS
+#ifdef CONFIG_HUGETLB_PAGE
-	VMCOREINFO_SYMBOL(free_huge_page);
+	VMCOREINFO_NUMBER(HUGETLB_PAGE_DTOR);
 #endif
 	arch_crash_save_vmcoreinfo();

kernel/locking/lockdep.c+34−3

 	chain->irq_context = hlock->irq_context;
 	i = get_first_held_lock(curr, hlock);
 	chain->depth = curr->lockdep_depth + 1 - i;
+	BUILD_BUG_ON((1UL << 24) <= ARRAY_SIZE(chain_hlocks));
+	BUILD_BUG_ON((1UL << 6)  <= ARRAY_SIZE(curr->held_locks));
+	BUILD_BUG_ON((1UL << 8*sizeof(chain_hlocks[0])) <= ARRAY_SIZE(lock_classes));
 	if (likely(nr_chain_hlocks + chain->depth <= MAX_LOCKDEP_CHAIN_HLOCKS)) {
 		chain->base = nr_chain_hlocks;
-		nr_chain_hlocks += chain->depth;
 		for (j = 0; j < chain->depth - 1; j++, i++) {
 			int lock_id = curr->held_locks[i].class_idx - 1;
 			chain_hlocks[chain->base + j] = lock_id;
 		}
 		chain_hlocks[chain->base + j] = class - lock_classes;
 	}
+	if (nr_chain_hlocks < MAX_LOCKDEP_CHAIN_HLOCKS)
+		nr_chain_hlocks += chain->depth;
+#ifdef CONFIG_DEBUG_LOCKDEP
+	/*
+	 * Important for check_no_collision().
+	 */
+	if (unlikely(nr_chain_hlocks > MAX_LOCKDEP_CHAIN_HLOCKS)) {
+		if (debug_locks_off_graph_unlock())
+			return 0;
+		print_lockdep_off("BUG: MAX_LOCKDEP_CHAIN_HLOCKS too low!");
+		dump_stack();
+		return 0;
+	}
+#endif
 	hlist_add_head_rcu(&chain->entry, hash_head);
 	debug_atomic_inc(chain_lookup_misses);
 	inc_chains();
 	return 1;
 }
+static inline unsigned int task_irq_context(struct task_struct *task)
+{
+	return 2 * !!task->hardirq_context + !!task->softirq_context;
+}
 static int separate_irq_context(struct task_struct *curr,
 		struct held_lock *hlock)
 {
 	/*
 	 * Keep track of points where we cross into an interrupt context:
 	 */
-	hlock->irq_context = 2*(curr->hardirq_context ? 1 : 0) +
-				curr->softirq_context;
 	if (depth) {
 		struct held_lock *prev_hlock;
 	return 1;
 }
+static inline unsigned int task_irq_context(struct task_struct *task)
+{
+	return 0;
+}
 static inline int separate_irq_context(struct task_struct *curr,
 		struct held_lock *hlock)
 {
 	hlock->acquire_ip = ip;
 	hlock->instance = lock;
 	hlock->nest_lock = nest_lock;
+	hlock->irq_context = task_irq_context(curr);
 	hlock->trylock = trylock;
 	hlock->read = read;
 	hlock->check = check;

kernel/locking/lockdep_proc.c+2−0

@@ -141,6 +141,8 @@ static int lc_show(struct seq_file m, void v) · 140 unmodified lines
141	int i;	141	int i;
142		142
143	if (v == SEQ_START_TOKEN) {	143	if (v == SEQ_START_TOKEN) {
		144	if (nr_chain_hlocks > MAX_LOCKDEP_CHAIN_HLOCKS)
		145	seq_printf(m, "(buggered) ");
144	seq_printf(m, "all lock chains:\n");	146	seq_printf(m, "all lock chains:\n");
145	return 0;	147	return 0;
146	}	148	}

kernel/workqueue.c+29−0

@@ -666,6 +666,35 @@ static void set_work_pool_and_clear_pending(struct work_struct *work, · 665 unmodified lines
666	*/	666	*/
667	smp_wmb();	667	smp_wmb();
668	set_work_data(work, (unsigned long)pool_id << WORK_OFFQ_POOL_SHIFT, 0);	668	set_work_data(work, (unsigned long)pool_id << WORK_OFFQ_POOL_SHIFT, 0);
		669	/*
		670	* The following mb guarantees that previous clear of a PENDING bit
		671	* will not be reordered with any speculative LOADS or STORES from
		672	* work->current_func, which is executed afterwards. This possible
		673	* reordering can lead to a missed execution on attempt to qeueue
		674	* the same @work. E.g. consider this case:
		675	*
		676	* CPU#0 CPU#1
		677	* ---------------------------- --------------------------------
		678	*
		679	* 1 STORE event_indicated
		680	* 2 queue_work_on() {
		681	* 3 test_and_set_bit(PENDING)
		682	* 4 } set_..._and_clear_pending() {
		683	* 5 set_work_data() # clear bit
		684	* 6 smp_mb()
		685	* 7 work->current_func() {
		686	* 8 LOAD event_indicated
		687	* }
		688	*
		689	* Without an explicit full barrier speculative LOAD on line 8 can
		690	* be executed before CPU#0 does STORE on line 1. If that happens,
		691	* CPU#0 observes the PENDING bit is still set and new execution of
		692	* a @work is not queued in a hope, that CPU#1 will eventually
		693	* finish the queued @work. Meanwhile CPU#1 does not see
		694	* event_indicated is set, because speculative LOAD was executed
		695	* before actual STORE.
		696	*/
		697	smp_mb();
669	}	698	}
670		699
671	static void clear_work_data(struct work_struct *work)	700	static void clear_work_data(struct work_struct *work)

lib/stackdepot.c+0−4

@@ -210,10 +210,6 @@ depot_stack_handle_t depot_save_stack(struct stack_trace *trace, · 209 unmodified lines
210	goto fast_exit;	210	goto fast_exit;
211		211
212	hash = hash_stack(trace->entries, trace->nr_entries);	212	hash = hash_stack(trace->entries, trace->nr_entries);
213	/* Bad luck, we won't store this stack. */
214	if (hash == 0)
215	goto exit;
216
217	bucket = &stack_table[hash & STACK_HASH_MASK];	213	bucket = &stack_table[hash & STACK_HASH_MASK];
218		214
219	/*	215	/*

mm/huge_memory.c+5−7

 	return READ_ONCE(huge_zero_page);
 }
-static void put_huge_zero_page(void)
+void put_huge_zero_page(void)
 {
 	/*
 	 * Counter should never go to zero here. Only shrinker can put
 	if (vma_is_dax(vma)) {
 		spin_unlock(ptl);
 		if (is_huge_zero_pmd(orig_pmd))
-			put_huge_zero_page();
+			tlb_remove_page(tlb, pmd_page(orig_pmd));
 	} else if (is_huge_zero_pmd(orig_pmd)) {
 		pte_free(tlb->mm, pgtable_trans_huge_withdraw(tlb->mm, pmd));
 		atomic_long_dec(&tlb->mm->nr_ptes);
 		spin_unlock(ptl);
-		put_huge_zero_page();
+		tlb_remove_page(tlb, pmd_page(orig_pmd));
 	} else {
 		struct page *page = pmd_page(orig_pmd);
 		page_remove_rmap(page, true);
 		 * page fault if needed.
 		 */
 		return 0;
-	if (vma->vm_ops)
+	if (vma->vm_ops || (vm_flags & VM_NO_THP))
 		/* khugepaged not yet working on file or special mappings */
 		return 0;
-	VM_BUG_ON_VMA(vm_flags & VM_NO_THP, vma);
 	hstart = (vma->vm_start + ~HPAGE_PMD_MASK) & HPAGE_PMD_MASK;
 	hend = vma->vm_end & HPAGE_PMD_MASK;
 	if (hstart < hend)
 		return false;
 	if (is_vma_temporary_stack(vma))
 		return false;
-	VM_BUG_ON_VMA(vma->vm_flags & VM_NO_THP, vma);
+	return !(vma->vm_flags & VM_NO_THP);
-	return true;
 }
 static void collapse_huge_page(struct mm_struct *mm,

mm/memcontrol.c+19−18

 /* "mc" and its members are protected by cgroup_mutex */
 static struct move_charge_struct {
 	spinlock_t	  lock; /* for from, to */
+	struct mm_struct  *mm;
 	struct mem_cgroup *from;
 	struct mem_cgroup *to;
 	unsigned long flags;
 static void mem_cgroup_clear_mc(void)
 {
+	struct mm_struct *mm = mc.mm;
 	/*
 	 * we must clear moving_task before waking up waiters at the end of
 	 * task migration.
 	spin_lock(&mc.lock);
 	mc.from = NULL;
 	mc.to = NULL;
+	mc.mm = NULL;
 	spin_unlock(&mc.lock);
+	mmput(mm);
 }
 static int mem_cgroup_can_attach(struct cgroup_taskset *tset)
 		VM_BUG_ON(mc.moved_swap);
 		spin_lock(&mc.lock);
+		mc.mm = mm;
 		mc.from = from;
 		mc.to = memcg;
 		mc.flags = move_flags;
 		ret = mem_cgroup_precharge_mc(mm);
 		if (ret)
 			mem_cgroup_clear_mc();
+	} else {
+		mmput(mm);
 	}
-	mmput(mm);
 	return ret;
 }
 	return ret;
 }
-static void mem_cgroup_move_charge(struct mm_struct *mm)
+static void mem_cgroup_move_charge(void)
 {
 	struct mm_walk mem_cgroup_move_charge_walk = {
 		.pmd_entry = mem_cgroup_move_charge_pte_range,
-		.mm = mm,
+		.mm = mc.mm,
 	};
 	lru_add_drain_all();
 	atomic_inc(&mc.from->moving_account);
 	synchronize_rcu();
 retry:
-	if (unlikely(!down_read_trylock(&mm->mmap_sem))) {
+	if (unlikely(!down_read_trylock(&mc.mm->mmap_sem))) {
 		/*
 		 * Someone who are holding the mmap_sem might be waiting in
 		 * waitq. So we cancel all extra charges, wake up all waiters,
 	 * additional charge, the page walk just aborts.
 	 */
 	walk_page_range(0, ~0UL, &mem_cgroup_move_charge_walk);
-	up_read(&mm->mmap_sem);
+	up_read(&mc.mm->mmap_sem);
 	atomic_dec(&mc.from->moving_account);
 }
-static void mem_cgroup_move_task(struct cgroup_taskset *tset)
+static void mem_cgroup_move_task(void)
 {
-	struct cgroup_subsys_state *css;
+	if (mc.to) {
-	struct task_struct *p = cgroup_taskset_first(tset, &css);
+		mem_cgroup_move_charge();
-	struct mm_struct *mm = get_task_mm(p);
-	if (mm) {
-		if (mc.to)
-			mem_cgroup_move_charge(mm);
-		mmput(mm);
-	}
-	if (mc.to)
 		mem_cgroup_clear_mc();
+	}
 }
 #else	/* !CONFIG_MMU */
 static int mem_cgroup_can_attach(struct cgroup_taskset *tset)
 static void mem_cgroup_cancel_attach(struct cgroup_taskset *tset)
 {
 }
-static void mem_cgroup_move_task(struct cgroup_taskset *tset)
+static void mem_cgroup_move_task(void)
 {
 }
 #endif
 	.css_reset = mem_cgroup_css_reset,
 	.can_attach = mem_cgroup_can_attach,
 	.cancel_attach = mem_cgroup_cancel_attach,
-	.attach = mem_cgroup_move_task,
+	.post_attach = mem_cgroup_move_task,
 	.bind = mem_cgroup_bind,
 	.dfl_cftypes = memory_files,
 	.legacy_cftypes = mem_cgroup_legacy_files,

mm/memory-failure.c+9−1

@@ -888,7 +888,15 @@ int get_hwpoison_page(struct page *page) · 887 unmodified lines
888	}	888	}
889	}	889	}
890		890
891	return get_page_unless_zero(head);	891	if (get_page_unless_zero(head)) {
		892	if (head == compound_head(page))
		893	return 1;
		894
		895	pr_info("MCE: %#lx cannot catch tail\n", page_to_pfn(page));
		896	put_page(head);
		897	}
		898
		899	return 0;
892	}	900	}
893	EXPORT_SYMBOL_GPL(get_hwpoison_page);	901	EXPORT_SYMBOL_GPL(get_hwpoison_page);
894		902

mm/memory.c+40−0

@@ -789,6 +789,46 @@ out: · 788 unmodified lines
789	return pfn_to_page(pfn);	789	return pfn_to_page(pfn);
790	}	790	}
791		791
		792	#ifdef CONFIG_TRANSPARENT_HUGEPAGE
		793	struct page vm_normal_page_pmd(struct vm_area_struct vma, unsigned long addr,
		794	pmd_t pmd)
		795	{
		796	unsigned long pfn = pmd_pfn(pmd);
		797
		798	/*
		799	* There is no pmd_special() but there may be special pmds, e.g.
		800	* in a direct-access (dax) mapping, so let's just replicate the
		801	* !HAVE_PTE_SPECIAL case from vm_normal_page() here.
		802	*/
		803	if (unlikely(vma->vm_flags & (VM_PFNMAP\|VM_MIXEDMAP))) {
		804	if (vma->vm_flags & VM_MIXEDMAP) {
		805	if (!pfn_valid(pfn))
		806	return NULL;
		807	goto out;
		808	} else {
		809	unsigned long off;
		810	off = (addr - vma->vm_start) >> PAGE_SHIFT;
		811	if (pfn == vma->vm_pgoff + off)
		812	return NULL;
		813	if (!is_cow_mapping(vma->vm_flags))
		814	return NULL;
		815	}
		816	}
		817
		818	if (is_zero_pfn(pfn))
		819	return NULL;
		820	if (unlikely(pfn > highest_memmap_pfn))
		821	return NULL;
		822
		823	/*
		824	* NOTE! We still have PageReserved() pages in the page tables.
		825	* eg. VDSO mappings can cause them to exist.
		826	*/
		827	out:
		828	return pfn_to_page(pfn);
		829	}
		830	#endif
		831
792	/*	832	/*
793	* copy one vm_area from one task to the other. Assumes the page tables	833	* copy one vm_area from one task to the other. Assumes the page tables
794	* already present in the new task to be cleared in the whole range	834	* already present in the new task to be cleared in the whole range

mm/migrate.c+7−1

 		dec_zone_page_state(page, NR_ISOLATED_ANON +
 				page_is_file_cache(page));
 		/* Soft-offlined page shouldn't go through lru cache list */
-		if (reason == MR_MEMORY_FAILURE) {
+		if (reason == MR_MEMORY_FAILURE && rc == MIGRATEPAGE_SUCCESS) {
+			/*
+			 * With this release, we free successfully migrated
+			 * page and set PG_HWPoison on just freed page
+			 * intentionally. Although it's rather weird, it's how
+			 * HWPoison flag works at the moment.
+			 */
 			put_page(page);
 			if (!test_set_page_hwpoison(page))
 				num_poisoned_pages_inc();

mm/page_io.c+5−1

 	ret = bdev_read_page(sis->bdev, swap_page_sector(page), page);
 	if (!ret) {
-		swap_slot_free_notify(page);
+		if (trylock_page(page)) {
+			swap_slot_free_notify(page);
+			unlock_page(page);
+		}
 		count_vm_event(PSWPIN);
 		return 0;
 	}

mm/swap.c+5−0

 			zone = NULL;
 		}
+		if (is_huge_zero_page(page)) {
+			put_huge_zero_page();
+			continue;
+		}
 		page = compound_head(page);
 		if (!put_page_testzero(page))
 			continue;

mm/vmscan.c+15−15

 		sc->gfp_mask |= __GFP_HIGHMEM;
 	for_each_zone_zonelist_nodemask(zone, z, zonelist,
-					requested_highidx, sc->nodemask) {
+					gfp_zone(sc->gfp_mask), sc->nodemask) {
 		enum zone_type classzone_idx;
 		if (!populated_zone(zone))
 	/* Try to sleep for a short interval */
 	if (prepare_kswapd_sleep(pgdat, order, remaining,
 						balanced_classzone_idx)) {
+		/*
+		 * Compaction records what page blocks it recently failed to
+		 * isolate pages from and skips them in the future scanning.
+		 * When kswapd is going to sleep, it is reasonable to assume
+		 * that pages and compaction may succeed so reset the cache.
+		 */
+		reset_isolation_suitable(pgdat);
+		/*
+		 * We have freed the memory, now we should compact it to make
+		 * allocation of the requested order possible.
+		 */
+		wakeup_kcompactd(pgdat, order, classzone_idx);
 		remaining = schedule_timeout(HZ/10);
 		finish_wait(&pgdat->kswapd_wait, &wait);
 		prepare_to_wait(&pgdat->kswapd_wait, &wait, TASK_INTERRUPTIBLE);
 		 */
 		set_pgdat_percpu_threshold(pgdat, calculate_normal_threshold);
-		/*
-		 * Compaction records what page blocks it recently failed to
-		 * isolate pages from and skips them in the future scanning.
-		 * When kswapd is going to sleep, it is reasonable to assume
-		 * that pages and compaction may succeed so reset the cache.
-		 */
-		reset_isolation_suitable(pgdat);
-		/*
-		 * We have freed the memory, now we should compact it to make
-		 * allocation of the requested order possible.
-		 */
-		wakeup_kcompactd(pgdat, order, classzone_idx);
 		if (!kthread_should_stop())
 			schedule();

net/bridge/br_mdb.c+79−45

 		e->flags |= MDB_FLAGS_OFFLOAD;
 }
+static void __mdb_entry_to_br_ip(struct br_mdb_entry *entry, struct br_ip *ip)
+{
+	memset(ip, 0, sizeof(struct br_ip));
+	ip->vid = entry->vid;
+	ip->proto = entry->addr.proto;
+	if (ip->proto == htons(ETH_P_IP))
+		ip->u.ip4 = entry->addr.u.ip4;
+#if IS_ENABLED(CONFIG_IPV6)
+	else
+		ip->u.ip6 = entry->addr.u.ip6;
+#endif
+}
 static int br_mdb_fill_info(struct sk_buff *skb, struct netlink_callback *cb,
 			    struct net_device *dev)
 {
 		+ nla_total_size(sizeof(struct br_mdb_entry));
 }
-static void __br_mdb_notify(struct net_device *dev, struct br_mdb_entry *entry,
+struct br_mdb_complete_info {
-			    int type, struct net_bridge_port_group *pg)
+	struct net_bridge_port *port;
+	struct br_ip ip;
+};
+static void br_mdb_complete(struct net_device *dev, int err, void *priv)
 {
+	struct br_mdb_complete_info *data = priv;
+	struct net_bridge_port_group __rcu **pp;
+	struct net_bridge_port_group *p;
+	struct net_bridge_mdb_htable *mdb;
+	struct net_bridge_mdb_entry *mp;
+	struct net_bridge_port *port = data->port;
+	struct net_bridge *br = port->br;
+	if (err)
+		goto err;
+	spin_lock_bh(&br->multicast_lock);
+	mdb = mlock_dereference(br->mdb, br);
+	mp = br_mdb_ip_get(mdb, &data->ip);
+	if (!mp)
+		goto out;
+	for (pp = &mp->ports; (p = mlock_dereference(*pp, br)) != NULL;
+	     pp = &p->next) {
+		if (p->port != port)
+			continue;
+		p->flags |= MDB_PG_FLAGS_OFFLOAD;
+	}
+out:
+	spin_unlock_bh(&br->multicast_lock);
+err:
+	kfree(priv);
+}
+static void __br_mdb_notify(struct net_device *dev, struct net_bridge_port *p,
+			    struct br_mdb_entry *entry, int type)
+{
+	struct br_mdb_complete_info *complete_info;
 	struct switchdev_obj_port_mdb mdb = {
 		.obj = {
 			.id = SWITCHDEV_OBJ_ID_PORT_MDB,
 	mdb.obj.orig_dev = port_dev;
 	if (port_dev && type == RTM_NEWMDB) {
-		err = switchdev_port_obj_add(port_dev, &mdb.obj);
+		complete_info = kmalloc(sizeof(*complete_info), GFP_ATOMIC);
-		if (!err && pg)
+		if (complete_info) {
-			pg->flags |= MDB_PG_FLAGS_OFFLOAD;
+			complete_info->port = p;
+			__mdb_entry_to_br_ip(entry, &complete_info->ip);
+			mdb.obj.complete_priv = complete_info;
+			mdb.obj.complete = br_mdb_complete;
+			switchdev_port_obj_add(port_dev, &mdb.obj);
+		}
 	} else if (port_dev && type == RTM_DELMDB) {
 		switchdev_port_obj_del(port_dev, &mdb.obj);
 	}
 	rtnl_set_sk_err(net, RTNLGRP_MDB, err);
 }
-void br_mdb_notify(struct net_device *dev, struct net_bridge_port_group *pg,
+void br_mdb_notify(struct net_device *dev, struct net_bridge_port *port,
-		   int type)
+		   struct br_ip *group, int type, u8 flags)
 {
 	struct br_mdb_entry entry;
 	memset(&entry, 0, sizeof(entry));
-	entry.ifindex = pg->port->dev->ifindex;
+	entry.ifindex = port->dev->ifindex;
-	entry.addr.proto = pg->addr.proto;
+	entry.addr.proto = group->proto;
-	entry.addr.u.ip4 = pg->addr.u.ip4;
+	entry.addr.u.ip4 = group->u.ip4;
 #if IS_ENABLED(CONFIG_IPV6)
-	entry.addr.u.ip6 = pg->addr.u.ip6;
+	entry.addr.u.ip6 = group->u.ip6;
 #endif
-	entry.vid = pg->addr.vid;
+	entry.vid = group->vid;
-	__mdb_entry_fill_flags(&entry, pg->flags);
+	__mdb_entry_fill_flags(&entry, flags);
-	__br_mdb_notify(dev, &entry, type, pg);
+	__br_mdb_notify(dev, port, &entry, type);
 }
 static int nlmsg_populate_rtr_fill(struct sk_buff *skb,
 }
 static int br_mdb_add_group(struct net_bridge *br, struct net_bridge_port *port,
-			    struct br_ip *group, unsigned char state,
+			    struct br_ip *group, unsigned char state)
-			    struct net_bridge_port_group **pg)
 {
 	struct net_bridge_mdb_entry *mp;
 	struct net_bridge_port_group *p;
 	if (unlikely(!p))
 		return -ENOMEM;
 	rcu_assign_pointer(*pp, p);
-	*pg = p;
 	if (state == MDB_TEMPORARY)
 		mod_timer(&p->timer, now + br->multicast_membership_interval);
 }
 static int __br_mdb_add(struct net *net, struct net_bridge *br,
-			struct br_mdb_entry *entry,
+			struct br_mdb_entry *entry)
-			struct net_bridge_port_group **pg)
 {
 	struct br_ip ip;
 	struct net_device *dev;
 	if (!p || p->br != br || p->state == BR_STATE_DISABLED)
 		return -EINVAL;
-	memset(&ip, 0, sizeof(ip));
+	__mdb_entry_to_br_ip(entry, &ip);
-	ip.vid = entry->vid;
-	ip.proto = entry->addr.proto;
-	if (ip.proto == htons(ETH_P_IP))
-		ip.u.ip4 = entry->addr.u.ip4;
-#if IS_ENABLED(CONFIG_IPV6)
-	else
-		ip.u.ip6 = entry->addr.u.ip6;
-#endif
 	spin_lock_bh(&br->multicast_lock);
-	ret = br_mdb_add_group(br, p, &ip, entry->state, pg);
+	ret = br_mdb_add_group(br, p, &ip, entry->state);
 	spin_unlock_bh(&br->multicast_lock);
 	return ret;
 }
 static int br_mdb_add(struct sk_buff *skb, struct nlmsghdr *nlh)
 {
 	struct net *net = sock_net(skb->sk);
-	struct net_bridge_port_group *pg;
 	struct net_bridge_vlan_group *vg;
 	struct net_device *dev, *pdev;
 	struct br_mdb_entry *entry;
 	if (br_vlan_enabled(br) && vg && entry->vid == 0) {
 		list_for_each_entry(v, &vg->vlan_list, vlist) {
 			entry->vid = v->vid;
-			err = __br_mdb_add(net, br, entry, &pg);
+			err = __br_mdb_add(net, br, entry);
 			if (err)
 				break;
-			__br_mdb_notify(dev, entry, RTM_NEWMDB, pg);
+			__br_mdb_notify(dev, p, entry, RTM_NEWMDB);
 		}
 	} else {
-		err = __br_mdb_add(net, br, entry, &pg);
+		err = __br_mdb_add(net, br, entry);
 		if (!err)
-			__br_mdb_notify(dev, entry, RTM_NEWMDB, pg);
+			__br_mdb_notify(dev, p, entry, RTM_NEWMDB);
 	}
 	return err;
 	if (!netif_running(br->dev) || br->multicast_disabled)
 		return -EINVAL;
-	memset(&ip, 0, sizeof(ip));
+	__mdb_entry_to_br_ip(entry, &ip);
-	ip.vid = entry->vid;
-	ip.proto = entry->addr.proto;
-	if (ip.proto == htons(ETH_P_IP))
-		ip.u.ip4 = entry->addr.u.ip4;
-#if IS_ENABLED(CONFIG_IPV6)
-	else
-		ip.u.ip6 = entry->addr.u.ip6;
-#endif
 	spin_lock_bh(&br->multicast_lock);
 	mdb = mlock_dereference(br->mdb, br);
 			entry->vid = v->vid;
 			err = __br_mdb_del(br, entry);
 			if (!err)
-				__br_mdb_notify(dev, entry, RTM_DELMDB, NULL);
+				__br_mdb_notify(dev, p, entry, RTM_DELMDB);
 		}
 	} else {
 		err = __br_mdb_del(br, entry);
 		if (!err)
-			__br_mdb_notify(dev, entry, RTM_DELMDB, NULL);
+			__br_mdb_notify(dev, p, entry, RTM_DELMDB);
 	}
 	return err;

net/bridge/br_multicast.c+5−3

 		rcu_assign_pointer(*pp, p->next);
 		hlist_del_init(&p->mglist);
 		del_timer(&p->timer);
-		br_mdb_notify(br->dev, p, RTM_DELMDB);
+		br_mdb_notify(br->dev, p->port, &pg->addr, RTM_DELMDB,
+			      p->flags);
 		call_rcu_bh(&p->rcu, br_multicast_free_pg);
 		if (!mp->ports && !mp->mglist &&
 	if (unlikely(!p))
 		goto err;
 	rcu_assign_pointer(*pp, p);
-	br_mdb_notify(br->dev, p, RTM_NEWMDB);
+	br_mdb_notify(br->dev, port, group, RTM_NEWMDB, 0);
 found:
 	mod_timer(&p->timer, now + br->multicast_membership_interval);
 			hlist_del_init(&p->mglist);
 			del_timer(&p->timer);
 			call_rcu_bh(&p->rcu, br_multicast_free_pg);
-			br_mdb_notify(br->dev, p, RTM_DELMDB);
+			br_mdb_notify(br->dev, port, group, RTM_DELMDB,
+				      p->flags);
 			if (!mp->ports && !mp->mglist &&
 			    netif_running(br->dev))

net/bridge/br_private.h+2−2

@@ -560,8 +560,8 @@ br_multicast_new_port_group(struct net_bridge_port port, struct br_ip group, · 559 unmodified lines
560	unsigned char flags);	560	unsigned char flags);
561	void br_mdb_init(void);	561	void br_mdb_init(void);
562	void br_mdb_uninit(void);	562	void br_mdb_uninit(void);
563	void br_mdb_notify(struct net_device dev, struct net_bridge_port_group pg,	563	void br_mdb_notify(struct net_device dev, struct net_bridge_port port,
564	int type);	564	struct br_ip *group, int type, u8 flags);
565	void br_rtr_notify(struct net_device dev, struct net_bridge_port port,	565	void br_rtr_notify(struct net_device dev, struct net_bridge_port port,
566	int type);	566	int type);
567		567

net/ceph/auth.c+2−6

 }
 EXPORT_SYMBOL(ceph_auth_create_authorizer);
-void ceph_auth_destroy_authorizer(struct ceph_auth_client *ac,
+void ceph_auth_destroy_authorizer(struct ceph_authorizer *a)
-				  struct ceph_authorizer *a)
 {
-	mutex_lock(&ac->mutex);
+	a->destroy(a);
-	if (ac->ops && ac->ops->destroy_authorizer)
-		ac->ops->destroy_authorizer(ac, a);
-	mutex_unlock(&ac->mutex);
 }
 EXPORT_SYMBOL(ceph_auth_destroy_authorizer);

net/ceph/auth_none.c+39−32

@@ -16,7 +16,6 @@ static void reset(struct ceph_auth_client *ac) · 15 unmodified lines
16	struct ceph_auth_none_info *xi = ac->private;	16	struct ceph_auth_none_info *xi = ac->private;
17		17
18	xi->starting = true;	18	xi->starting = true;
19	xi->built_authorizer = false;
20	}	19	}
21		20
22	static void destroy(struct ceph_auth_client *ac)	21	static void destroy(struct ceph_auth_client *ac)
@@ -39,6 +38,27 @@ static int should_authenticate(struct ceph_auth_client *ac) · 16 unmodified lines
39	return xi->starting;	38	return xi->starting;
40	}	39	}
41		40
		41	static int ceph_auth_none_build_authorizer(struct ceph_auth_client *ac,
		42	struct ceph_none_authorizer *au)
		43	{
		44	void *p = au->buf;
		45	void *const end = p + sizeof(au->buf);
		46	int ret;
		47
		48	ceph_encode_8_safe(&p, end, 1, e_range);
		49	ret = ceph_entity_name_encode(ac->name, &p, end);
		50	if (ret < 0)
		51	return ret;
		52
		53	ceph_encode_64_safe(&p, end, ac->global_id, e_range);
		54	au->buf_len = p - (void *)au->buf;
		55	dout("%s built authorizer len %d\n", __func__, au->buf_len);
		56	return 0;
		57
		58	e_range:
		59	return -ERANGE;
		60	}
		61
42	static int build_request(struct ceph_auth_client ac, void buf, void *end)	62	static int build_request(struct ceph_auth_client ac, void buf, void *end)
43	{	63	{
44	return 0;	64	return 0;
@@ -57,32 +77,32 @@ static int handle_reply(struct ceph_auth_client *ac, int result, · 12 unmodified lines
57	return result;	77	return result;
58	}	78	}
59		79
		80	static void ceph_auth_none_destroy_authorizer(struct ceph_authorizer *a)
		81	{
		82	kfree(a);
		83	}
		84
60	/*	85	/*
61	* build an 'authorizer' with our entity_name and global_id. we can	86	* build an 'authorizer' with our entity_name and global_id. it is
62	* reuse a single static copy since it is identical for all services	87	* identical for all services we connect to.
63	* we connect to.
64	*/	88	*/
65	static int ceph_auth_none_create_authorizer(	89	static int ceph_auth_none_create_authorizer(
66	struct ceph_auth_client *ac, int peer_type,	90	struct ceph_auth_client *ac, int peer_type,
67	struct ceph_auth_handshake *auth)	91	struct ceph_auth_handshake *auth)
68	{	92	{
69	struct ceph_auth_none_info *ai = ac->private;	93	struct ceph_none_authorizer *au;
70	struct ceph_none_authorizer *au = &ai->au;
71	void p, end;
72	int ret;	94	int ret;
73		95
74	if (!ai->built_authorizer) {	96	au = kmalloc(sizeof(*au), GFP_NOFS);
75	p = au->buf;	97	if (!au)
76	end = p + sizeof(au->buf);	98	return -ENOMEM;
77	ceph_encode_8(&p, 1);	99
78	ret = ceph_entity_name_encode(ac->name, &p, end - 8);	100	au->base.destroy = ceph_auth_none_destroy_authorizer;
79	if (ret < 0)	101
80	goto bad;	102	ret = ceph_auth_none_build_authorizer(ac, au);
81	ceph_decode_need(&p, end, sizeof(u64), bad2);	103	if (ret) {
82	ceph_encode_64(&p, ac->global_id);	104	kfree(au);
83	au->buf_len = p - (void *)au->buf;	105	return ret;
84	ai->built_authorizer = true;
85	dout("built authorizer len %d\n", au->buf_len);
86	}	106	}
87		107
88	auth->authorizer = (struct ceph_authorizer *) au;	108	auth->authorizer = (struct ceph_authorizer *) au;
@@ -92,17 +112,6 @@ static int ceph_auth_none_create_authorizer( · 3 unmodified lines
92	auth->authorizer_reply_buf_len = sizeof (au->reply_buf);	112	auth->authorizer_reply_buf_len = sizeof (au->reply_buf);
93		113
94	return 0;	114	return 0;
95
96	bad2:
97	ret = -ERANGE;
98	bad:
99	return ret;
100	}
101
102	static void ceph_auth_none_destroy_authorizer(struct ceph_auth_client *ac,
103	struct ceph_authorizer *a)
104	{
105	/* nothing to do */
106	}	115	}
107		116
108	static const struct ceph_auth_client_ops ceph_auth_none_ops = {	117	static const struct ceph_auth_client_ops ceph_auth_none_ops = {
@@ -114,7 +123,6 @@ static const struct ceph_auth_client_ops ceph_auth_none_ops = { · 5 unmodified lines
114	.build_request = build_request,	123	.build_request = build_request,
115	.handle_reply = handle_reply,	124	.handle_reply = handle_reply,
116	.create_authorizer = ceph_auth_none_create_authorizer,	125	.create_authorizer = ceph_auth_none_create_authorizer,
117	.destroy_authorizer = ceph_auth_none_destroy_authorizer,
118	};	126	};
119		127
120	int ceph_auth_none_init(struct ceph_auth_client *ac)	128	int ceph_auth_none_init(struct ceph_auth_client *ac)
@@ -127,7 +135,6 @@ int ceph_auth_none_init(struct ceph_auth_client *ac) · 6 unmodified lines
127	return -ENOMEM;	135	return -ENOMEM;
128		136
129	xi->starting = true;	137	xi->starting = true;
130	xi->built_authorizer = false;
131		138
132	ac->protocol = CEPH_AUTH_NONE;	139	ac->protocol = CEPH_AUTH_NONE;
133	ac->private = xi;	140	ac->private = xi;

net/ceph/auth_none.h+1−2

  */
 struct ceph_none_authorizer {
+	struct ceph_authorizer base;
 	char buf[128];
 	int buf_len;
 	char reply_buf[0];
 struct ceph_auth_none_info {
 	bool starting;
-	bool built_authorizer;
-	struct ceph_none_authorizer au;   /* we only need one; it's static */
 };
 int ceph_auth_none_init(struct ceph_auth_client *ac);

net/ceph/auth_x.c+10−11

 	return -EAGAIN;
 }
+static void ceph_x_destroy_authorizer(struct ceph_authorizer *a)
+{
+	struct ceph_x_authorizer *au = (void *)a;
+	ceph_x_authorizer_cleanup(au);
+	kfree(au);
+}
 static int ceph_x_create_authorizer(
 	struct ceph_auth_client *ac, int peer_type,
 	struct ceph_auth_handshake *auth)
 	if (!au)
 		return -ENOMEM;
+	au->base.destroy = ceph_x_destroy_authorizer;
 	ret = ceph_x_build_authorizer(ac, th, au);
 	if (ret) {
 		kfree(au);
 	return ret;
 }
-static void ceph_x_destroy_authorizer(struct ceph_auth_client *ac,
-				      struct ceph_authorizer *a)
-{
-	struct ceph_x_authorizer *au = (void *)a;
-	ceph_x_authorizer_cleanup(au);
-	kfree(au);
-}
 static void ceph_x_reset(struct ceph_auth_client *ac)
 {
 	struct ceph_x_info *xi = ac->private;
 	.create_authorizer = ceph_x_create_authorizer,
 	.update_authorizer = ceph_x_update_authorizer,
 	.verify_authorizer_reply = ceph_x_verify_authorizer_reply,
-	.destroy_authorizer = ceph_x_destroy_authorizer,
 	.invalidate_authorizer = ceph_x_invalidate_authorizer,
 	.reset =  ceph_x_reset,
 	.destroy = ceph_x_destroy,

net/ceph/auth_x.h+1−0

@@ -26,6 +26,7 @@ struct ceph_x_ticket_handler { · 25 unmodified lines
26		26
27		27
28	struct ceph_x_authorizer {	28	struct ceph_x_authorizer {
		29	struct ceph_authorizer base;
29	struct ceph_crypto_key session_key;	30	struct ceph_crypto_key session_key;
30	struct ceph_buffer *buf;	31	struct ceph_buffer *buf;
31	unsigned int service;	32	unsigned int service;

net/ceph/osd_client.c+2−4

 	dout("put_osd %p %d -> %d\n", osd, atomic_read(&osd->o_ref),
 	     atomic_read(&osd->o_ref) - 1);
 	if (atomic_dec_and_test(&osd->o_ref)) {
-		struct ceph_auth_client *ac = osd->o_osdc->client->monc.auth;
 		if (osd->o_auth.authorizer)
-			ceph_auth_destroy_authorizer(ac, osd->o_auth.authorizer);
+			ceph_auth_destroy_authorizer(osd->o_auth.authorizer);
 		kfree(osd);
 	}
 }
 	struct ceph_auth_handshake *auth = &o->o_auth;
 	if (force_new && auth->authorizer) {
-		ceph_auth_destroy_authorizer(ac, auth->authorizer);
+		ceph_auth_destroy_authorizer(auth->authorizer);
 		auth->authorizer = NULL;
 	}
 	if (!auth->authorizer) {

net/ipv4/fib_frontend.c+5−1

 	if (ifa->ifa_flags & IFA_F_SECONDARY) {
 		prim = inet_ifa_byprefix(in_dev, any, ifa->ifa_mask);
 		if (!prim) {
-			pr_warn("%s: bug: prim == NULL\n", __func__);
+			/* if the device has been deleted, we don't perform
+			 * address promotion
+			 */
+			if (!in_dev->dead)
+				pr_warn("%s: bug: prim == NULL\n", __func__);
 			return;
 		}
 		if (iprim && iprim != prim) {

net/ipv6/addrconf.c+15−33

@@ -3176,35 +3176,9 @@ static void addrconf_gre_config(struct net_device *dev) · 3175 unmodified lines
3176	}	3176	}
3177	#endif	3177	#endif
3178		3178
3179	#if IS_ENABLED(CONFIG_NET_L3_MASTER_DEV)
3180	/* If the host route is cached on the addr struct make sure it is associated
3181	* with the proper table. e.g., enslavement can change and if so the cached
3182	* host route needs to move to the new table.
3183	*/
3184	static void l3mdev_check_host_rt(struct inet6_dev *idev,
3185	struct inet6_ifaddr *ifp)
3186	{
3187	if (ifp->rt) {
3188	u32 tb_id = l3mdev_fib_table(idev->dev) ? : RT6_TABLE_LOCAL;
3189
3190	if (tb_id != ifp->rt->rt6i_table->tb6_id) {
3191	ip6_del_rt(ifp->rt);
3192	ifp->rt = NULL;
3193	}
3194	}
3195	}
3196	#else
3197	static void l3mdev_check_host_rt(struct inet6_dev *idev,
3198	struct inet6_ifaddr *ifp)
3199	{
3200	}
3201	#endif
3202
3203	static int fixup_permanent_addr(struct inet6_dev *idev,	3179	static int fixup_permanent_addr(struct inet6_dev *idev,
3204	struct inet6_ifaddr *ifp)	3180	struct inet6_ifaddr *ifp)
3205	{	3181	{
3206	l3mdev_check_host_rt(idev, ifp);
3207
3208	if (!ifp->rt) {	3182	if (!ifp->rt) {
3209	struct rt6_info *rt;	3183	struct rt6_info *rt;
3210		3184
@@ -3304,6 +3278,9 @@ static int addrconf_notify(struct notifier_block *this, unsigned long event, · 93 unmodified lines
3304	break;	3278	break;
3305		3279
3306	if (event == NETDEV_UP) {	3280	if (event == NETDEV_UP) {
		3281	/* restore routes for permanent addresses */
		3282	addrconf_permanent_addr(dev);
		3283
3307	if (!addrconf_qdisc_ok(dev)) {	3284	if (!addrconf_qdisc_ok(dev)) {
3308	/* device is not ready yet. */	3285	/* device is not ready yet. */
3309	pr_info("ADDRCONF(NETDEV_UP): %s: link is not ready\n",	3286	pr_info("ADDRCONF(NETDEV_UP): %s: link is not ready\n",
@@ -3337,9 +3314,6 @@ static int addrconf_notify(struct notifier_block *this, unsigned long event, · 27 unmodified lines
3337	run_pending = 1;	3314	run_pending = 1;
3338	}	3315	}
3339		3316
3340	/* restore routes for permanent addresses */
3341	addrconf_permanent_addr(dev);
3342
3343	switch (dev->type) {	3317	switch (dev->type) {
3344	#if IS_ENABLED(CONFIG_IPV6_SIT)	3318	#if IS_ENABLED(CONFIG_IPV6_SIT)
3345	case ARPHRD_SIT:	3319	case ARPHRD_SIT:
@@ -3556,6 +3530,8 @@ restart: · 210 unmodified lines
3556		3530
3557	INIT_LIST_HEAD(&del_list);	3531	INIT_LIST_HEAD(&del_list);
3558	list_for_each_entry_safe(ifa, tmp, &idev->addr_list, if_list) {	3532	list_for_each_entry_safe(ifa, tmp, &idev->addr_list, if_list) {
		3533	struct rt6_info *rt = NULL;
		3534
3559	addrconf_del_dad_work(ifa);	3535	addrconf_del_dad_work(ifa);
3560		3536
3561	write_unlock_bh(&idev->lock);	3537	write_unlock_bh(&idev->lock);
@@ -3568,6 +3544,9 @@ restart: · 6 unmodified lines
3568	ifa->state = 0;	3544	ifa->state = 0;
3569	if (!(ifa->flags & IFA_F_NODAD))	3545	if (!(ifa->flags & IFA_F_NODAD))
3570	ifa->flags \|= IFA_F_TENTATIVE;	3546	ifa->flags \|= IFA_F_TENTATIVE;
		3547
		3548	rt = ifa->rt;
		3549	ifa->rt = NULL;
3571	} else {	3550	} else {
3572	state = ifa->state;	3551	state = ifa->state;
3573	ifa->state = INET6_IFADDR_STATE_DEAD;	3552	ifa->state = INET6_IFADDR_STATE_DEAD;
@@ -3578,6 +3557,9 @@ restart: · 4 unmodified lines
3578		3557
3579	spin_unlock_bh(&ifa->lock);	3558	spin_unlock_bh(&ifa->lock);
3580		3559
		3560	if (rt)
		3561	ip6_del_rt(rt);
		3562
3581	if (state != INET6_IFADDR_STATE_DEAD) {	3563	if (state != INET6_IFADDR_STATE_DEAD) {
3582	__ipv6_ifa_notify(RTM_DELADDR, ifa);	3564	__ipv6_ifa_notify(RTM_DELADDR, ifa);
3583	inet6addr_notifier_call_chain(NETDEV_DOWN, ifa);	3565	inet6addr_notifier_call_chain(NETDEV_DOWN, ifa);
@@ -5343,10 +5325,10 @@ static void __ipv6_ifa_notify(int event, struct inet6_ifaddr *ifp) · 1759 unmodified lines
5343	if (rt)	5325	if (rt)
5344	ip6_del_rt(rt);	5326	ip6_del_rt(rt);
5345	}	5327	}
5346	dst_hold(&ifp->rt->dst);	5328	if (ifp->rt) {
5347		5329	dst_hold(&ifp->rt->dst);
5348	ip6_del_rt(ifp->rt);	5330	ip6_del_rt(ifp->rt);
5349		5331	}
5350	rt_genid_bump_ipv6(net);	5332	rt_genid_bump_ipv6(net);
5351	break;	5333	break;
5352	}	5334	}

net/switchdev/switchdev.c+6−0

 	if (err && err != -EOPNOTSUPP)
 		netdev_err(dev, "failed (err=%d) to set attribute (id=%d)\n",
 			   err, attr->id);
+	if (attr->complete)
+		attr->complete(dev, err, attr->complete_priv);
 }
 static int switchdev_port_attr_set_defer(struct net_device *dev,
 	if (err && err != -EOPNOTSUPP)
 		netdev_err(dev, "failed (err=%d) to add object (id=%d)\n",
 			   err, obj->id);
+	if (obj->complete)
+		obj->complete(dev, err, obj->complete_priv);
 }
 static int switchdev_port_obj_add_defer(struct net_device *dev,
 	if (err && err != -EOPNOTSUPP)
 		netdev_err(dev, "failed (err=%d) to del object (id=%d)\n",
 			   err, obj->id);
+	if (obj->complete)
+		obj->complete(dev, err, obj->complete_priv);
 }
 static int switchdev_port_obj_del_defer(struct net_device *dev,

sound/hda/ext/hdac_ext_stream.c+2−3

  */
 void snd_hdac_stream_free_all(struct hdac_ext_bus *ebus)
 {
-	struct hdac_stream *s;
+	struct hdac_stream *s, *_s;
 	struct hdac_ext_stream *stream;
 	struct hdac_bus *bus = ebus_to_hbus(ebus);
-	while (!list_empty(&bus->stream_list)) {
+	list_for_each_entry_safe(s, _s, &bus->stream_list, list) {
-		s = list_first_entry(&bus->stream_list, struct hdac_stream, list);
 		stream = stream_to_hdac_ext_stream(s);
 		snd_hdac_ext_stream_decouple(ebus, stream, false);
 		list_del(&s->list);

sound/hda/hdac_i915.c+51−11

@@ -20,6 +20,7 @@ · 19 unmodified lines
20	#include <sound/core.h>	20	#include <sound/core.h>
21	#include <sound/hdaudio.h>	21	#include <sound/hdaudio.h>
22	#include <sound/hda_i915.h>	22	#include <sound/hda_i915.h>
		23	#include <sound/hda_register.h>
23		24
24	static struct i915_audio_component *hdac_acomp;	25	static struct i915_audio_component *hdac_acomp;
25		26
@@ -97,26 +98,65 @@ int snd_hdac_display_power(struct hdac_bus *bus, bool enable) · 71 unmodified lines
97	}	98	}
98	EXPORT_SYMBOL_GPL(snd_hdac_display_power);	99	EXPORT_SYMBOL_GPL(snd_hdac_display_power);
99		100
		101	#define CONTROLLER_IN_GPU(pci) (((pci)->device == 0x0a0c) \|\| \
		102	((pci)->device == 0x0c0c) \|\| \
		103	((pci)->device == 0x0d0c) \|\| \
		104	((pci)->device == 0x160c))
		105
100	/**	106	/**
101	* snd_hdac_get_display_clk - Get CDCLK in kHz	107	* snd_hdac_i915_set_bclk - Reprogram BCLK for HSW/BDW
102	* @bus: HDA core bus	108	* @bus: HDA core bus
103	*	109	*
104	* This function is supposed to be used only by a HD-audio controller	110	* Intel HSW/BDW display HDA controller is in GPU. Both its power and link BCLK
105	* driver that needs the interaction with i915 graphics.	111	* depends on GPU. Two Extended Mode registers EM4 (M value) and EM5 (N Value)
		112	* are used to convert CDClk (Core Display Clock) to 24MHz BCLK:
		113	* BCLK = CDCLK * M / N
		114	* The values will be lost when the display power well is disabled and need to
		115	* be restored to avoid abnormal playback speed.
106	*	116	*
107	* This function queries CDCLK value in kHz from the graphics driver and	117	* Call this function at initializing and changing power well, as well as
108	* returns the value. A negative code is returned in error.	118	* at ELD notifier for the hotplug.
109	*/	119	*/
110	int snd_hdac_get_display_clk(struct hdac_bus *bus)	120	void snd_hdac_i915_set_bclk(struct hdac_bus *bus)
111	{	121	{
112	struct i915_audio_component *acomp = bus->audio_component;	122	struct i915_audio_component *acomp = bus->audio_component;
		123	struct pci_dev *pci = to_pci_dev(bus->dev);
		124	int cdclk_freq;
		125	unsigned int bclk_m, bclk_n;
		126
		127	if (!acomp \|\| !acomp->ops \|\| !acomp->ops->get_cdclk_freq)
		128	return; /* only for i915 binding */
		129	if (!CONTROLLER_IN_GPU(pci))
		130	return; /* only HSW/BDW */
		131
		132	cdclk_freq = acomp->ops->get_cdclk_freq(acomp->dev);
		133	switch (cdclk_freq) {
		134	case 337500:
		135	bclk_m = 16;
		136	bclk_n = 225;
		137	break;
		138
		139	case 450000:
		140	default: /* default CDCLK 450MHz */
		141	bclk_m = 4;
		142	bclk_n = 75;
		143	break;
		144
		145	case 540000:
		146	bclk_m = 4;
		147	bclk_n = 90;
		148	break;
		149
		150	case 675000:
		151	bclk_m = 8;
		152	bclk_n = 225;
		153	break;
		154	}
113		155
114	if (!acomp \|\| !acomp->ops)	156	snd_hdac_chip_writew(bus, HSW_EM4, bclk_m);
115	return -ENODEV;	157	snd_hdac_chip_writew(bus, HSW_EM5, bclk_n);
116
117	return acomp->ops->get_cdclk_freq(acomp->dev);
118	}	158	}
119	EXPORT_SYMBOL_GPL(snd_hdac_get_display_clk);	159	EXPORT_SYMBOL_GPL(snd_hdac_i915_set_bclk);
120		160
121	/* There is a fixed mapping between audio pin node and display port	161	/* There is a fixed mapping between audio pin node and display port
122	* on current Intel platforms:	162	* on current Intel platforms:

sound/pci/hda/hda_intel.c+4−52

@@ -857,50 +857,6 @@ static int param_set_xint(const char val, const struct kernel_param kp) · 856 unmodified lines
857	#define azx_del_card_list(chip) /* NOP */	857	#define azx_del_card_list(chip) /* NOP */
858	#endif /* CONFIG_PM */	858	#endif /* CONFIG_PM */
859		859
860	/* Intel HSW/BDW display HDA controller is in GPU. Both its power and link BCLK
861	* depends on GPU. Two Extended Mode registers EM4 (M value) and EM5 (N Value)
862	* are used to convert CDClk (Core Display Clock) to 24MHz BCLK:
863	* BCLK = CDCLK * M / N
864	* The values will be lost when the display power well is disabled and need to
865	* be restored to avoid abnormal playback speed.
866	*/
867	static void haswell_set_bclk(struct hda_intel *hda)
868	{
869	struct azx *chip = &hda->chip;
870	int cdclk_freq;
871	unsigned int bclk_m, bclk_n;
872
873	if (!hda->need_i915_power)
874	return;
875
876	cdclk_freq = snd_hdac_get_display_clk(azx_bus(chip));
877	switch (cdclk_freq) {
878	case 337500:
879	bclk_m = 16;
880	bclk_n = 225;
881	break;
882
883	case 450000:
884	default: /* default CDCLK 450MHz */
885	bclk_m = 4;
886	bclk_n = 75;
887	break;
888
889	case 540000:
890	bclk_m = 4;
891	bclk_n = 90;
892	break;
893
894	case 675000:
895	bclk_m = 8;
896	bclk_n = 225;
897	break;
898	}
899
900	azx_writew(chip, HSW_EM4, bclk_m);
901	azx_writew(chip, HSW_EM5, bclk_n);
902	}
903
904	#if defined(CONFIG_PM_SLEEP) \|\| defined(SUPPORT_VGA_SWITCHEROO)	860	#if defined(CONFIG_PM_SLEEP) \|\| defined(SUPPORT_VGA_SWITCHEROO)
905	/*	861	/*
906	* power management	862	* power management
@@ -958,7 +914,7 @@ static int azx_resume(struct device *dev) · 51 unmodified lines
958	if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL	914	if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
959	&& hda->need_i915_power) {	915	&& hda->need_i915_power) {
960	snd_hdac_display_power(azx_bus(chip), true);	916	snd_hdac_display_power(azx_bus(chip), true);
961	haswell_set_bclk(hda);	917	snd_hdac_i915_set_bclk(azx_bus(chip));
962	}	918	}
963	if (chip->msi)	919	if (chip->msi)
964	if (pci_enable_msi(pci) < 0)	920	if (pci_enable_msi(pci) < 0)
@@ -1058,7 +1014,7 @@ static int azx_runtime_resume(struct device *dev) · 93 unmodified lines
1058	bus = azx_bus(chip);	1014	bus = azx_bus(chip);
1059	if (hda->need_i915_power) {	1015	if (hda->need_i915_power) {
1060	snd_hdac_display_power(bus, true);	1016	snd_hdac_display_power(bus, true);
1061	haswell_set_bclk(hda);	1017	snd_hdac_i915_set_bclk(bus);
1062	} else {	1018	} else {
1063	/* toggle codec wakeup bit for STATESTS read */	1019	/* toggle codec wakeup bit for STATESTS read */
1064	snd_hdac_set_codec_wakeup(bus, true);	1020	snd_hdac_set_codec_wakeup(bus, true);
@@ -1796,12 +1752,8 @@ static int azx_first_init(struct azx *chip) · 731 unmodified lines
1796	/* initialize chip */	1752	/* initialize chip */
1797	azx_init_pci(chip);	1753	azx_init_pci(chip);
1798		1754
1799	if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {	1755	if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
1800	struct hda_intel *hda;	1756	snd_hdac_i915_set_bclk(bus);
1801
1802	hda = container_of(chip, struct hda_intel, chip);
1803	haswell_set_bclk(hda);
1804	}
1805		1757
1806	hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0);	1758	hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0);
1807		1759

sound/pci/hda/patch_hdmi.c+1−0

@@ -2232,6 +2232,7 @@ static void intel_pin_eld_notify(void *audio_ptr, int port) · 2231 unmodified lines
2232	if (atomic_read(&(codec)->core.in_pm))	2232	if (atomic_read(&(codec)->core.in_pm))
2233	return;	2233	return;
2234		2234
		2235	snd_hdac_i915_set_bclk(&codec->bus->core);
2235	check_presence_and_report(codec, pin_nid);	2236	check_presence_and_report(codec, pin_nid);
2236	}	2237	}
2237		2238

sound/pci/hda/patch_realtek.c+1−0

@@ -5584,6 +5584,7 @@ static const struct snd_pci_quirk alc269_fixup_tbl[] = { · 5583 unmodified lines
5584	SND_PCI_QUIRK(0x17aa, 0x5034, "Thinkpad T450", ALC292_FIXUP_TPT440_DOCK),	5584	SND_PCI_QUIRK(0x17aa, 0x5034, "Thinkpad T450", ALC292_FIXUP_TPT440_DOCK),
5585	SND_PCI_QUIRK(0x17aa, 0x5036, "Thinkpad T450s", ALC292_FIXUP_TPT440_DOCK),	5585	SND_PCI_QUIRK(0x17aa, 0x5036, "Thinkpad T450s", ALC292_FIXUP_TPT440_DOCK),
5586	SND_PCI_QUIRK(0x17aa, 0x503c, "Thinkpad L450", ALC292_FIXUP_TPT440_DOCK),	5586	SND_PCI_QUIRK(0x17aa, 0x503c, "Thinkpad L450", ALC292_FIXUP_TPT440_DOCK),
		5587	SND_PCI_QUIRK(0x17aa, 0x504a, "ThinkPad X260", ALC292_FIXUP_TPT440_DOCK),
5587	SND_PCI_QUIRK(0x17aa, 0x504b, "Thinkpad", ALC293_FIXUP_LENOVO_SPK_NOISE),	5588	SND_PCI_QUIRK(0x17aa, 0x504b, "Thinkpad", ALC293_FIXUP_LENOVO_SPK_NOISE),
5588	SND_PCI_QUIRK(0x17aa, 0x5109, "Thinkpad", ALC269_FIXUP_LIMIT_INT_MIC_BOOST),	5589	SND_PCI_QUIRK(0x17aa, 0x5109, "Thinkpad", ALC269_FIXUP_LIMIT_INT_MIC_BOOST),
5589	SND_PCI_QUIRK(0x17aa, 0x3bf8, "Quanta FL1", ALC269_FIXUP_PCM_44K),	5590	SND_PCI_QUIRK(0x17aa, 0x3bf8, "Quanta FL1", ALC269_FIXUP_PCM_44K),

sound/soc/codecs/Kconfig+1−0

@@ -629,6 +629,7 @@ config SND_SOC_RT5514 · 628 unmodified lines
629		629
630	config SND_SOC_RT5616	630	config SND_SOC_RT5616
631	tristate "Realtek RT5616 CODEC"	631	tristate "Realtek RT5616 CODEC"
		632	depends on I2C
632		633
633	config SND_SOC_RT5631	634	config SND_SOC_RT5631
634	tristate "Realtek ALC5631/RT5631 CODEC"	635	tristate "Realtek ALC5631/RT5631 CODEC"

sound/soc/codecs/arizona.c+12−0

@@ -249,6 +249,18 @@ int arizona_init_spk(struct snd_soc_codec *codec) · 248 unmodified lines
249	}	249	}
250	EXPORT_SYMBOL_GPL(arizona_init_spk);	250	EXPORT_SYMBOL_GPL(arizona_init_spk);
251		251
		252	int arizona_free_spk(struct snd_soc_codec *codec)
		253	{
		254	struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
		255	struct arizona *arizona = priv->arizona;
		256
		257	arizona_free_irq(arizona, ARIZONA_IRQ_SPK_OVERHEAT_WARN, arizona);
		258	arizona_free_irq(arizona, ARIZONA_IRQ_SPK_OVERHEAT, arizona);
		259
		260	return 0;
		261	}
		262	EXPORT_SYMBOL_GPL(arizona_free_spk);
		263
252	static const struct snd_soc_dapm_route arizona_mono_routes[] = {	264	static const struct snd_soc_dapm_route arizona_mono_routes[] = {
253	{ "OUT1R", NULL, "OUT1L" },	265	{ "OUT1R", NULL, "OUT1L" },
254	{ "OUT2R", NULL, "OUT2L" },	266	{ "OUT2R", NULL, "OUT2L" },

sound/soc/codecs/arizona.h+2−0

@@ -307,6 +307,8 @@ extern int arizona_init_spk(struct snd_soc_codec *codec); · 306 unmodified lines
307	extern int arizona_init_gpio(struct snd_soc_codec *codec);	307	extern int arizona_init_gpio(struct snd_soc_codec *codec);
308	extern int arizona_init_mono(struct snd_soc_codec *codec);	308	extern int arizona_init_mono(struct snd_soc_codec *codec);
309		309
		310	extern int arizona_free_spk(struct snd_soc_codec *codec);
		311
310	extern int arizona_init_dai(struct arizona_priv *priv, int dai);	312	extern int arizona_init_dai(struct arizona_priv *priv, int dai);
311		313
312	int arizona_set_output_mode(struct snd_soc_codec *codec, int output,	314	int arizona_set_output_mode(struct snd_soc_codec *codec, int output,

sound/soc/codecs/cs35l32.c+13−4

 	if (of_property_read_u32(np, "cirrus,sdout-share", &val) >= 0)
 		pdata->sdout_share = val;
-	of_property_read_u32(np, "cirrus,boost-manager", &val);
+	if (of_property_read_u32(np, "cirrus,boost-manager", &val))
+		val = -1u;
 	switch (val) {
 	case CS35L32_BOOST_MGR_AUTO:
 	case CS35L32_BOOST_MGR_AUTO_AUDIO:
 	case CS35L32_BOOST_MGR_FIXED:
 		pdata->boost_mng = val;
 		break;
+	case -1u:
 	default:
 		dev_err(&i2c_client->dev,
 			"Wrong cirrus,boost-manager DT value %d\n", val);
 		pdata->boost_mng = CS35L32_BOOST_MGR_BYPASS;
 	}
-	of_property_read_u32(np, "cirrus,sdout-datacfg", &val);
+	if (of_property_read_u32(np, "cirrus,sdout-datacfg", &val))
+		val = -1u;
 	switch (val) {
 	case CS35L32_DATA_CFG_LR_VP:
 	case CS35L32_DATA_CFG_LR_STAT:
 	case CS35L32_DATA_CFG_LR_VPSTAT:
 		pdata->sdout_datacfg = val;
 		break;
+	case -1u:
 	default:
 		dev_err(&i2c_client->dev,
 			"Wrong cirrus,sdout-datacfg DT value %d\n", val);
 		pdata->sdout_datacfg = CS35L32_DATA_CFG_LR;
 	}
-	of_property_read_u32(np, "cirrus,battery-threshold", &val);
+	if (of_property_read_u32(np, "cirrus,battery-threshold", &val))
+		val = -1u;
 	switch (val) {
 	case CS35L32_BATT_THRESH_3_1V:
 	case CS35L32_BATT_THRESH_3_2V:
 	case CS35L32_BATT_THRESH_3_4V:
 		pdata->batt_thresh = val;
 		break;
+	case -1u:
 	default:
 		dev_err(&i2c_client->dev,
 			"Wrong cirrus,battery-threshold DT value %d\n", val);
 		pdata->batt_thresh = CS35L32_BATT_THRESH_3_3V;
 	}
-	of_property_read_u32(np, "cirrus,battery-recovery", &val);
+	if (of_property_read_u32(np, "cirrus,battery-recovery", &val))
+		val = -1u;
 	switch (val) {
 	case CS35L32_BATT_RECOV_3_1V:
 	case CS35L32_BATT_RECOV_3_2V:
 	case CS35L32_BATT_RECOV_3_6V:
 		pdata->batt_recov = val;
 		break;
+	case -1u:
 	default:
 		dev_err(&i2c_client->dev,
 			"Wrong cirrus,battery-recovery DT value %d\n", val);

sound/soc/codecs/cs47l24.c+3−0

@@ -1108,6 +1108,9 @@ static int cs47l24_codec_remove(struct snd_soc_codec *codec) · 1107 unmodified lines
1108	priv->core.arizona->dapm = NULL;	1108	priv->core.arizona->dapm = NULL;
1109		1109
1110	arizona_free_irq(arizona, ARIZONA_IRQ_DSP_IRQ1, priv);	1110	arizona_free_irq(arizona, ARIZONA_IRQ_DSP_IRQ1, priv);
		1111
		1112	arizona_free_spk(codec);
		1113
1111	return 0;	1114	return 0;
1112	}	1115	}
1113		1116

sound/soc/codecs/hdac_hdmi.c+42−52

@@ -1420,32 +1420,39 @@ static int hdmi_codec_remove(struct snd_soc_codec *codec) · 1419 unmodified lines
1420	}	1420	}
1421		1421
1422	#ifdef CONFIG_PM	1422	#ifdef CONFIG_PM
1423	static int hdmi_codec_resume(struct snd_soc_codec *codec)	1423	static int hdmi_codec_prepare(struct device *dev)
1424	{	1424	{
1425	struct hdac_ext_device *edev = snd_soc_codec_get_drvdata(codec);	1425	struct hdac_ext_device *edev = to_hda_ext_device(dev);
		1426	struct hdac_device *hdac = &edev->hdac;
		1427
		1428	pm_runtime_get_sync(&edev->hdac.dev);
		1429
		1430	/*
		1431	* Power down afg.
		1432	* codec_read is preferred over codec_write to set the power state.
		1433	* This way verb is send to set the power state and response
		1434	* is received. So setting power state is ensured without using loop
		1435	* to read the state.
		1436	*/
		1437	snd_hdac_codec_read(hdac, hdac->afg, 0, AC_VERB_SET_POWER_STATE,
		1438	AC_PWRST_D3);
		1439
		1440	return 0;
		1441	}
		1442
		1443	static void hdmi_codec_complete(struct device *dev)
		1444	{
		1445	struct hdac_ext_device *edev = to_hda_ext_device(dev);
1426	struct hdac_hdmi_priv *hdmi = edev->private_data;	1446	struct hdac_hdmi_priv *hdmi = edev->private_data;
1427	struct hdac_hdmi_pin *pin;	1447	struct hdac_hdmi_pin *pin;
1428	struct hdac_device *hdac = &edev->hdac;	1448	struct hdac_device *hdac = &edev->hdac;
1429	struct hdac_bus *bus = hdac->bus;
1430	int err;
1431	unsigned long timeout;
1432
1433	hdac_hdmi_skl_enable_all_pins(&edev->hdac);
1434	hdac_hdmi_skl_enable_dp12(&edev->hdac);
1435		1449
1436	/* Power up afg */	1450	/* Power up afg */
1437	if (!snd_hdac_check_power_state(hdac, hdac->afg, AC_PWRST_D0)) {	1451	snd_hdac_codec_read(hdac, hdac->afg, 0, AC_VERB_SET_POWER_STATE,
1438		1452	AC_PWRST_D0);
1439	snd_hdac_codec_write(hdac, hdac->afg, 0,
1440	AC_VERB_SET_POWER_STATE, AC_PWRST_D0);
1441		1453
1442	/* Wait till power state is set to D0 */	1454	hdac_hdmi_skl_enable_all_pins(&edev->hdac);
1443	timeout = jiffies + msecs_to_jiffies(1000);	1455	hdac_hdmi_skl_enable_dp12(&edev->hdac);
1444	while (!snd_hdac_check_power_state(hdac, hdac->afg, AC_PWRST_D0)
1445	&& time_before(jiffies, timeout)) {
1446	msleep(50);
1447	}
1448	}
1449		1456
1450	/*	1457	/*
1451	* As the ELD notify callback request is not entertained while the	1458	* As the ELD notify callback request is not entertained while the
@@ -1455,28 +1462,16 @@ static int hdmi_codec_resume(struct snd_soc_codec *codec) · 3 unmodified lines
1455	list_for_each_entry(pin, &hdmi->pin_list, head)	1462	list_for_each_entry(pin, &hdmi->pin_list, head)
1456	hdac_hdmi_present_sense(pin, 1);	1463	hdac_hdmi_present_sense(pin, 1);
1457		1464
1458	/*	1465	pm_runtime_put_sync(&edev->hdac.dev);
1459	* Codec power is turned ON during controller resume.
1460	* Turn it OFF here
1461	*/
1462	err = snd_hdac_display_power(bus, false);
1463	if (err < 0) {
1464	dev_err(bus->dev,
1465	"Cannot turn OFF display power on i915, err: %d\n",
1466	err);
1467	return err;
1468	}
1469
1470	return 0;
1471	}	1466	}
1472	#else	1467	#else
1473	#define hdmi_codec_resume NULL	1468	#define hdmi_codec_prepare NULL
		1469	#define hdmi_codec_complete NULL
1474	#endif	1470	#endif
1475		1471
1476	static struct snd_soc_codec_driver hdmi_hda_codec = {	1472	static struct snd_soc_codec_driver hdmi_hda_codec = {
1477	.probe = hdmi_codec_probe,	1473	.probe = hdmi_codec_probe,
1478	.remove = hdmi_codec_remove,	1474	.remove = hdmi_codec_remove,
1479	.resume = hdmi_codec_resume,
1480	.idle_bias_off = true,	1475	.idle_bias_off = true,
1481	};	1476	};
1482		1477
@@ -1561,7 +1556,6 @@ static int hdac_hdmi_runtime_suspend(struct device *dev) · 78 unmodified lines
1561	struct hdac_ext_device *edev = to_hda_ext_device(dev);	1556	struct hdac_ext_device *edev = to_hda_ext_device(dev);
1562	struct hdac_device *hdac = &edev->hdac;	1557	struct hdac_device *hdac = &edev->hdac;
1563	struct hdac_bus *bus = hdac->bus;	1558	struct hdac_bus *bus = hdac->bus;
1564	unsigned long timeout;
1565	int err;	1559	int err;
1566		1560
1567	dev_dbg(dev, "Enter: %s\n", __func__);	1561	dev_dbg(dev, "Enter: %s\n", __func__);
@@ -1570,20 +1564,15 @@ static int hdac_hdmi_runtime_suspend(struct device *dev) · 2 unmodified lines
1570	if (!bus)	1564	if (!bus)
1571	return 0;	1565	return 0;
1572		1566
1573	/* Power down afg */	1567	/*
1574	if (!snd_hdac_check_power_state(hdac, hdac->afg, AC_PWRST_D3)) {	1568	* Power down afg.
1575	snd_hdac_codec_write(hdac, hdac->afg, 0,	1569	* codec_read is preferred over codec_write to set the power state.
1576	AC_VERB_SET_POWER_STATE, AC_PWRST_D3);	1570	* This way verb is send to set the power state and response
1577		1571	* is received. So setting power state is ensured without using loop
1578	/* Wait till power state is set to D3 */	1572	* to read the state.
1579	timeout = jiffies + msecs_to_jiffies(1000);	1573	*/
1580	while (!snd_hdac_check_power_state(hdac, hdac->afg, AC_PWRST_D3)	1574	snd_hdac_codec_read(hdac, hdac->afg, 0, AC_VERB_SET_POWER_STATE,
1581	&& time_before(jiffies, timeout)) {	1575	AC_PWRST_D3);
1582
1583	msleep(50);
1584	}
1585	}
1586
1587	err = snd_hdac_display_power(bus, false);	1576	err = snd_hdac_display_power(bus, false);
1588	if (err < 0) {	1577	if (err < 0) {
1589	dev_err(bus->dev, "Cannot turn on display power on i915\n");	1578	dev_err(bus->dev, "Cannot turn on display power on i915\n");
@@ -1616,9 +1605,8 @@ static int hdac_hdmi_runtime_resume(struct device *dev) · 26 unmodified lines
1616	hdac_hdmi_skl_enable_dp12(&edev->hdac);	1605	hdac_hdmi_skl_enable_dp12(&edev->hdac);
1617		1606
1618	/* Power up afg */	1607	/* Power up afg */
1619	if (!snd_hdac_check_power_state(hdac, hdac->afg, AC_PWRST_D0))	1608	snd_hdac_codec_read(hdac, hdac->afg, 0, AC_VERB_SET_POWER_STATE,
1620	snd_hdac_codec_write(hdac, hdac->afg, 0,	1609	AC_PWRST_D0);
1621	AC_VERB_SET_POWER_STATE, AC_PWRST_D0);
1622		1610
1623	return 0;	1611	return 0;
1624	}	1612	}
@@ -1629,6 +1617,8 @@ static int hdac_hdmi_runtime_resume(struct device *dev) · 4 unmodified lines
1629		1617
1630	static const struct dev_pm_ops hdac_hdmi_pm = {	1618	static const struct dev_pm_ops hdac_hdmi_pm = {
1631	SET_RUNTIME_PM_OPS(hdac_hdmi_runtime_suspend, hdac_hdmi_runtime_resume, NULL)	1619	SET_RUNTIME_PM_OPS(hdac_hdmi_runtime_suspend, hdac_hdmi_runtime_resume, NULL)
		1620	.prepare = hdmi_codec_prepare,
		1621	.complete = hdmi_codec_complete,
1632	};	1622	};
1633		1623
1634	static const struct hda_device_id hdmi_list[] = {	1624	static const struct hda_device_id hdmi_list[] = {

sound/soc/codecs/nau8825.c+71−55

 	SND_SOC_DAPM_SUPPLY("ADC Power", NAU8825_REG_ANALOG_ADC_2, 6, 0, NULL,
 		0),
-	/* ADC for button press detection */
+	/* ADC for button press detection. A dapm supply widget is used to
-	SND_SOC_DAPM_ADC("SAR", NULL, NAU8825_REG_SAR_CTRL,
+	 * prevent dapm_power_widgets keeping the codec at SND_SOC_BIAS_ON
-		NAU8825_SAR_ADC_EN_SFT, 0),
+	 * during suspend.
+	 */
+	SND_SOC_DAPM_SUPPLY("SAR", NAU8825_REG_SAR_CTRL,
+		NAU8825_SAR_ADC_EN_SFT, 0, NULL, 0),
 	SND_SOC_DAPM_PGA_S("ADACL", 2, NAU8825_REG_RDAC, 12, 0, NULL, 0),
 	SND_SOC_DAPM_PGA_S("ADACR", 2, NAU8825_REG_RDAC, 13, 0, NULL, 0),
 static void nau8825_restart_jack_detection(struct regmap *regmap)
 {
+	/* Chip needs one FSCLK cycle in order to generate interrupts,
+	 * as we cannot guarantee one will be provided by the system. Turning
+	 * master mode on then off enables us to generate that FSCLK cycle
+	 * with a minimum of contention on the clock bus.
+	 */
+	regmap_update_bits(regmap, NAU8825_REG_I2S_PCM_CTRL2,
+		NAU8825_I2S_MS_MASK, NAU8825_I2S_MS_MASTER);
+	regmap_update_bits(regmap, NAU8825_REG_I2S_PCM_CTRL2,
+		NAU8825_I2S_MS_MASK, NAU8825_I2S_MS_SLAVE);
 	/* this will restart the entire jack detection process including MIC/GND
 	 * switching and create interrupts. We have to go from 0 to 1 and back
 	 * to 0 to restart.
 	struct regmap *regmap = nau8825->regmap;
 	int active_irq, clear_irq = 0, event = 0, event_mask = 0;
-	regmap_read(regmap, NAU8825_REG_IRQ_STATUS, &active_irq);
+	if (regmap_read(regmap, NAU8825_REG_IRQ_STATUS, &active_irq)) {
+		dev_err(nau8825->dev, "failed to read irq status\n");
+		return IRQ_NONE;
+	}
 	if ((active_irq & NAU8825_JACK_EJECTION_IRQ_MASK) ==
 		NAU8825_JACK_EJECTION_DETECTED) {
 					return ret;
 				}
 			}
-			ret = regcache_sync(nau8825->regmap);
-			if (ret) {
-				dev_err(codec->dev,
-					"Failed to sync cache: %d\n", ret);
-				return ret;
-			}
 		}
 		break;
 	case SND_SOC_BIAS_OFF:
 		if (nau8825->mclk_freq)
 			clk_disable_unprepare(nau8825->mclk);
-		regcache_mark_dirty(nau8825->regmap);
 		break;
 	}
 	return 0;
 }
+#ifdef CONFIG_PM
+static int nau8825_suspend(struct snd_soc_codec *codec)
+{
+	struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
+	disable_irq(nau8825->irq);
+	regcache_cache_only(nau8825->regmap, true);
+	regcache_mark_dirty(nau8825->regmap);
+	return 0;
+}
+static int nau8825_resume(struct snd_soc_codec *codec)
+{
+	struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
+	/* The chip may lose power and reset in S3. regcache_sync restores
+	 * register values including configurations for sysclk, irq, and
+	 * jack/button detection.
+	 */
+	regcache_cache_only(nau8825->regmap, false);
+	regcache_sync(nau8825->regmap);
+	/* Check the jack plug status directly. If the headset is unplugged
+	 * during S3 when the chip has no power, there will be no jack
+	 * detection irq even after the nau8825_restart_jack_detection below,
+	 * because the chip just thinks no headset has ever been plugged in.
+	 */
+	if (!nau8825_is_jack_inserted(nau8825->regmap)) {
+		nau8825_eject_jack(nau8825);
+		snd_soc_jack_report(nau8825->jack, 0, SND_JACK_HEADSET);
+	}
+	enable_irq(nau8825->irq);
+	/* Run jack detection to check the type (OMTP or CTIA) of the headset
+	 * if there is one. This handles the case where a different type of
+	 * headset is plugged in during S3. This triggers an IRQ iff a headset
+	 * is already plugged in.
+	 */
+	nau8825_restart_jack_detection(nau8825->regmap);
+	return 0;
+}
+#else
+#define nau8825_suspend NULL
+#define nau8825_resume NULL
+#endif
 static struct snd_soc_codec_driver nau8825_codec_driver = {
 	.probe = nau8825_codec_probe,
 	.set_sysclk = nau8825_set_sysclk,
 	.set_pll = nau8825_set_pll,
 	.set_bias_level = nau8825_set_bias_level,
 	.suspend_bias_off = true,
+	.suspend = nau8825_suspend,
+	.resume = nau8825_resume,
 	.controls = nau8825_controls,
 	.num_controls = ARRAY_SIZE(nau8825_controls),
 	regmap_update_bits(regmap, NAU8825_REG_ENA_CTRL,
 		NAU8825_ENABLE_DACR, NAU8825_ENABLE_DACR);
-	/* Chip needs one FSCLK cycle in order to generate interrupts,
-	 * as we cannot guarantee one will be provided by the system. Turning
-	 * master mode on then off enables us to generate that FSCLK cycle
-	 * with a minimum of contention on the clock bus.
-	 */
-	regmap_update_bits(regmap, NAU8825_REG_I2S_PCM_CTRL2,
-		NAU8825_I2S_MS_MASK, NAU8825_I2S_MS_MASTER);
-	regmap_update_bits(regmap, NAU8825_REG_I2S_PCM_CTRL2,
-		NAU8825_I2S_MS_MASK, NAU8825_I2S_MS_SLAVE);
 	ret = devm_request_threaded_irq(nau8825->dev, nau8825->irq, NULL,
 		nau8825_interrupt, IRQF_TRIGGER_LOW | IRQF_ONESHOT,
 		"nau8825", nau8825);
 	return 0;
 }
-#ifdef CONFIG_PM_SLEEP
-static int nau8825_suspend(struct device *dev)
-{
-	struct i2c_client *client = to_i2c_client(dev);
-	struct nau8825 *nau8825 = dev_get_drvdata(dev);
-	disable_irq(client->irq);
-	regcache_cache_only(nau8825->regmap, true);
-	regcache_mark_dirty(nau8825->regmap);
-	return 0;
-}
-static int nau8825_resume(struct device *dev)
-{
-	struct i2c_client *client = to_i2c_client(dev);
-	struct nau8825 *nau8825 = dev_get_drvdata(dev);
-	regcache_cache_only(nau8825->regmap, false);
-	regcache_sync(nau8825->regmap);
-	enable_irq(client->irq);
-	return 0;
-}
-#endif
-static const struct dev_pm_ops nau8825_pm = {
-	SET_SYSTEM_SLEEP_PM_OPS(nau8825_suspend, nau8825_resume)
-};
 static const struct i2c_device_id nau8825_i2c_ids[] = {
 	{ "nau8825", 0 },
 	{ }
 		.name = "nau8825",
 		.of_match_table = of_match_ptr(nau8825_of_ids),
 		.acpi_match_table = ACPI_PTR(nau8825_acpi_match),
-		.pm = &nau8825_pm,
 	},
 	.probe = nau8825_i2c_probe,
 	.remove = nau8825_i2c_remove,

sound/soc/codecs/rt5640.c+1−1

@@ -359,7 +359,7 @@ static const DECLARE_TLV_DB_RANGE(bst_tlv, · 358 unmodified lines
359		359
360	/* Interface data select */	360	/* Interface data select */
361	static const char * const rt5640_data_select[] = {	361	static const char * const rt5640_data_select[] = {
362	"Normal", "left copy to right", "right copy to left", "Swap"};	362	"Normal", "Swap", "left copy to right", "right copy to left"};
363		363
364	static SOC_ENUM_SINGLE_DECL(rt5640_if1_dac_enum, RT5640_DIG_INF_DATA,	364	static SOC_ENUM_SINGLE_DECL(rt5640_if1_dac_enum, RT5640_DIG_INF_DATA,
365	RT5640_IF1_DAC_SEL_SFT, rt5640_data_select);	365	RT5640_IF1_DAC_SEL_SFT, rt5640_data_select);

sound/soc/codecs/rt5640.h+18−18

@@ -443,39 +443,39 @@ · 442 unmodified lines
443	#define RT5640_IF1_DAC_SEL_MASK (0x3 << 14)	443	#define RT5640_IF1_DAC_SEL_MASK (0x3 << 14)
444	#define RT5640_IF1_DAC_SEL_SFT 14	444	#define RT5640_IF1_DAC_SEL_SFT 14
445	#define RT5640_IF1_DAC_SEL_NOR (0x0 << 14)	445	#define RT5640_IF1_DAC_SEL_NOR (0x0 << 14)
446	#define RT5640_IF1_DAC_SEL_L2R (0x1 << 14)	446	#define RT5640_IF1_DAC_SEL_SWAP (0x1 << 14)
447	#define RT5640_IF1_DAC_SEL_R2L (0x2 << 14)	447	#define RT5640_IF1_DAC_SEL_L2R (0x2 << 14)
448	#define RT5640_IF1_DAC_SEL_SWAP (0x3 << 14)	448	#define RT5640_IF1_DAC_SEL_R2L (0x3 << 14)
449	#define RT5640_IF1_ADC_SEL_MASK (0x3 << 12)	449	#define RT5640_IF1_ADC_SEL_MASK (0x3 << 12)
450	#define RT5640_IF1_ADC_SEL_SFT 12	450	#define RT5640_IF1_ADC_SEL_SFT 12
451	#define RT5640_IF1_ADC_SEL_NOR (0x0 << 12)	451	#define RT5640_IF1_ADC_SEL_NOR (0x0 << 12)
452	#define RT5640_IF1_ADC_SEL_L2R (0x1 << 12)	452	#define RT5640_IF1_ADC_SEL_SWAP (0x1 << 12)
453	#define RT5640_IF1_ADC_SEL_R2L (0x2 << 12)	453	#define RT5640_IF1_ADC_SEL_L2R (0x2 << 12)
454	#define RT5640_IF1_ADC_SEL_SWAP (0x3 << 12)	454	#define RT5640_IF1_ADC_SEL_R2L (0x3 << 12)
455	#define RT5640_IF2_DAC_SEL_MASK (0x3 << 10)	455	#define RT5640_IF2_DAC_SEL_MASK (0x3 << 10)
456	#define RT5640_IF2_DAC_SEL_SFT 10	456	#define RT5640_IF2_DAC_SEL_SFT 10
457	#define RT5640_IF2_DAC_SEL_NOR (0x0 << 10)	457	#define RT5640_IF2_DAC_SEL_NOR (0x0 << 10)
458	#define RT5640_IF2_DAC_SEL_L2R (0x1 << 10)	458	#define RT5640_IF2_DAC_SEL_SWAP (0x1 << 10)
459	#define RT5640_IF2_DAC_SEL_R2L (0x2 << 10)	459	#define RT5640_IF2_DAC_SEL_L2R (0x2 << 10)
460	#define RT5640_IF2_DAC_SEL_SWAP (0x3 << 10)	460	#define RT5640_IF2_DAC_SEL_R2L (0x3 << 10)
461	#define RT5640_IF2_ADC_SEL_MASK (0x3 << 8)	461	#define RT5640_IF2_ADC_SEL_MASK (0x3 << 8)
462	#define RT5640_IF2_ADC_SEL_SFT 8	462	#define RT5640_IF2_ADC_SEL_SFT 8
463	#define RT5640_IF2_ADC_SEL_NOR (0x0 << 8)	463	#define RT5640_IF2_ADC_SEL_NOR (0x0 << 8)
464	#define RT5640_IF2_ADC_SEL_L2R (0x1 << 8)	464	#define RT5640_IF2_ADC_SEL_SWAP (0x1 << 8)
465	#define RT5640_IF2_ADC_SEL_R2L (0x2 << 8)	465	#define RT5640_IF2_ADC_SEL_L2R (0x2 << 8)
466	#define RT5640_IF2_ADC_SEL_SWAP (0x3 << 8)	466	#define RT5640_IF2_ADC_SEL_R2L (0x3 << 8)
467	#define RT5640_IF3_DAC_SEL_MASK (0x3 << 6)	467	#define RT5640_IF3_DAC_SEL_MASK (0x3 << 6)
468	#define RT5640_IF3_DAC_SEL_SFT 6	468	#define RT5640_IF3_DAC_SEL_SFT 6
469	#define RT5640_IF3_DAC_SEL_NOR (0x0 << 6)	469	#define RT5640_IF3_DAC_SEL_NOR (0x0 << 6)
470	#define RT5640_IF3_DAC_SEL_L2R (0x1 << 6)	470	#define RT5640_IF3_DAC_SEL_SWAP (0x1 << 6)
471	#define RT5640_IF3_DAC_SEL_R2L (0x2 << 6)	471	#define RT5640_IF3_DAC_SEL_L2R (0x2 << 6)
472	#define RT5640_IF3_DAC_SEL_SWAP (0x3 << 6)	472	#define RT5640_IF3_DAC_SEL_R2L (0x3 << 6)
473	#define RT5640_IF3_ADC_SEL_MASK (0x3 << 4)	473	#define RT5640_IF3_ADC_SEL_MASK (0x3 << 4)
474	#define RT5640_IF3_ADC_SEL_SFT 4	474	#define RT5640_IF3_ADC_SEL_SFT 4
475	#define RT5640_IF3_ADC_SEL_NOR (0x0 << 4)	475	#define RT5640_IF3_ADC_SEL_NOR (0x0 << 4)
476	#define RT5640_IF3_ADC_SEL_L2R (0x1 << 4)	476	#define RT5640_IF3_ADC_SEL_SWAP (0x1 << 4)
477	#define RT5640_IF3_ADC_SEL_R2L (0x2 << 4)	477	#define RT5640_IF3_ADC_SEL_L2R (0x2 << 4)
478	#define RT5640_IF3_ADC_SEL_SWAP (0x3 << 4)	478	#define RT5640_IF3_ADC_SEL_R2L (0x3 << 4)
479		479
480	/* REC Left Mixer Control 1 (0x3b) */	480	/* REC Left Mixer Control 1 (0x3b) */
481	#define RT5640_G_HP_L_RM_L_MASK (0x7 << 13)	481	#define RT5640_G_HP_L_RM_L_MASK (0x7 << 13)

sound/soc/codecs/wm5102.c+5−0

 static int wm5102_codec_remove(struct snd_soc_codec *codec)
 {
 	struct wm5102_priv *priv = snd_soc_codec_get_drvdata(codec);
+	struct arizona *arizona = priv->core.arizona;
 	wm_adsp2_codec_remove(&priv->core.adsp[0], codec);
 	priv->core.arizona->dapm = NULL;
+	arizona_free_irq(arizona, ARIZONA_IRQ_DSP_IRQ1, priv);
+	arizona_free_spk(codec);
 	return 0;
 }

sound/soc/codecs/wm5110.c+2−0

@@ -2298,6 +2298,8 @@ static int wm5110_codec_remove(struct snd_soc_codec *codec) · 2297 unmodified lines
2298		2298
2299	arizona_free_irq(arizona, ARIZONA_IRQ_DSP_IRQ1, priv);	2299	arizona_free_irq(arizona, ARIZONA_IRQ_DSP_IRQ1, priv);
2300		2300
		2301	arizona_free_spk(codec);
		2302
2301	return 0;	2303	return 0;
2302	}	2304	}
2303		2305

sound/soc/codecs/wm8962.c+1−1

@@ -2471,7 +2471,7 @@ static void wm8962_configure_bclk(struct snd_soc_codec *codec) · 2470 unmodified lines
2471	break;	2471	break;
2472	default:	2472	default:
2473	dev_warn(codec->dev, "Unknown DSPCLK divisor read back\n");	2473	dev_warn(codec->dev, "Unknown DSPCLK divisor read back\n");
2474	dspclk = wm8962->sysclk;	2474	dspclk = wm8962->sysclk_rate;
2475	}	2475	}
2476		2476
2477	dev_dbg(codec->dev, "DSPCLK is %dHz, BCLK %d\n", dspclk, wm8962->bclk);	2477	dev_dbg(codec->dev, "DSPCLK is %dHz, BCLK %d\n", dspclk, wm8962->bclk);

sound/soc/codecs/wm8997.c+2−0

@@ -1072,6 +1072,8 @@ static int wm8997_codec_remove(struct snd_soc_codec *codec) · 1071 unmodified lines
1072		1072
1073	priv->core.arizona->dapm = NULL;	1073	priv->core.arizona->dapm = NULL;
1074		1074
		1075	arizona_free_spk(codec);
		1076
1075	return 0;	1077	return 0;
1076	}	1078	}
1077		1079

sound/soc/codecs/wm8998.c+2−0

@@ -1324,6 +1324,8 @@ static int wm8998_codec_remove(struct snd_soc_codec *codec) · 1323 unmodified lines
1324		1324
1325	priv->core.arizona->dapm = NULL;	1325	priv->core.arizona->dapm = NULL;
1326		1326
		1327	arizona_free_spk(codec);
		1328
1327	return 0;	1329	return 0;
1328	}	1330	}
1329		1331

sound/soc/intel/Kconfig+0−1

@@ -163,7 +163,6 @@ config SND_SOC_INTEL_SKYLAKE · 162 unmodified lines
163	tristate	163	tristate
164	select SND_HDA_EXT_CORE	164	select SND_HDA_EXT_CORE
165	select SND_SOC_TOPOLOGY	165	select SND_SOC_TOPOLOGY
166	select SND_HDA_I915
167	select SND_SOC_INTEL_SST	166	select SND_SOC_INTEL_SST
168		167
169	config SND_SOC_INTEL_SKL_RT286_MACH	168	config SND_SOC_INTEL_SKL_RT286_MACH

sound/soc/intel/haswell/sst-haswell-ipc.c+1−1

@@ -1345,7 +1345,7 @@ int sst_hsw_stream_reset(struct sst_hsw hsw, struct sst_hsw_stream stream) · 1344 unmodified lines
1345	return 0;	1345	return 0;
1346		1346
1347	/* wait for pause to complete before we reset the stream */	1347	/* wait for pause to complete before we reset the stream */
1348	while (stream->running && tries--)	1348	while (stream->running && --tries)
1349	msleep(1);	1349	msleep(1);
1350	if (!tries) {	1350	if (!tries) {
1351	dev_err(hsw->dev, "error: reset stream %d still running\n",	1351	dev_err(hsw->dev, "error: reset stream %d still running\n",

sound/soc/intel/skylake/skl-sst-dsp.c+5−0

 	skl_ipc_int_disable(dsp);
 	free_irq(dsp->irq, dsp);
+	dsp->cl_dev.ops.cl_cleanup_controller(dsp);
+	skl_cldma_int_disable(dsp);
+	skl_ipc_op_int_disable(dsp);
+	skl_ipc_int_disable(dsp);
 	skl_dsp_disable_core(dsp);
 }
 EXPORT_SYMBOL_GPL(skl_dsp_free);

sound/soc/intel/skylake/skl-topology.c+28−14

@@ -239,6 +239,7 @@ static void skl_tplg_update_buffer_size(struct skl_sst *ctx, · 238 unmodified lines
239	{	239	{
240	int multiplier = 1;	240	int multiplier = 1;
241	struct skl_module_fmt in_fmt, out_fmt;	241	struct skl_module_fmt in_fmt, out_fmt;
		242	int in_rate, out_rate;
242		243
243		244
244	/* Since fixups is applied to pin 0 only, ibs, obs needs	245	/* Since fixups is applied to pin 0 only, ibs, obs needs
@@ -249,15 +250,24 @@ static void skl_tplg_update_buffer_size(struct skl_sst *ctx, · 4 unmodified lines
249		250
250	if (mcfg->m_type == SKL_MODULE_TYPE_SRCINT)	251	if (mcfg->m_type == SKL_MODULE_TYPE_SRCINT)
251	multiplier = 5;	252	multiplier = 5;
252	mcfg->ibs = (in_fmt->s_freq / 1000) *	253
253	(mcfg->in_fmt->channels) *	254	if (in_fmt->s_freq % 1000)
254	(mcfg->in_fmt->bit_depth >> 3) *	255	in_rate = (in_fmt->s_freq / 1000) + 1;
255	multiplier;	256	else
256		257	in_rate = (in_fmt->s_freq / 1000);
257	mcfg->obs = (mcfg->out_fmt->s_freq / 1000) *	258
258	(mcfg->out_fmt->channels) *	259	mcfg->ibs = in_rate * (mcfg->in_fmt->channels) *
259	(mcfg->out_fmt->bit_depth >> 3) *	260	(mcfg->in_fmt->bit_depth >> 3) *
260	multiplier;	261	multiplier;
		262
		263	if (mcfg->out_fmt->s_freq % 1000)
		264	out_rate = (mcfg->out_fmt->s_freq / 1000) + 1;
		265	else
		266	out_rate = (mcfg->out_fmt->s_freq / 1000);
		267
		268	mcfg->obs = out_rate * (mcfg->out_fmt->channels) *
		269	(mcfg->out_fmt->bit_depth >> 3) *
		270	multiplier;
261	}	271	}
262		272
263	static int skl_tplg_update_be_blob(struct snd_soc_dapm_widget *w,	273	static int skl_tplg_update_be_blob(struct snd_soc_dapm_widget *w,
@@ -485,11 +495,15 @@ skl_tplg_init_pipe_modules(struct skl skl, struct skl_pipe pipe) · 221 unmodified lines
485	if (!skl_is_pipe_mcps_avail(skl, mconfig))	495	if (!skl_is_pipe_mcps_avail(skl, mconfig))
486	return -ENOMEM;	496	return -ENOMEM;
487		497
		498	skl_tplg_alloc_pipe_mcps(skl, mconfig);
		499
488	if (mconfig->is_loadable && ctx->dsp->fw_ops.load_mod) {	500	if (mconfig->is_loadable && ctx->dsp->fw_ops.load_mod) {
489	ret = ctx->dsp->fw_ops.load_mod(ctx->dsp,	501	ret = ctx->dsp->fw_ops.load_mod(ctx->dsp,
490	mconfig->id.module_id, mconfig->guid);	502	mconfig->id.module_id, mconfig->guid);
491	if (ret < 0)	503	if (ret < 0)
492	return ret;	504	return ret;
		505
		506	mconfig->m_state = SKL_MODULE_LOADED;
493	}	507	}
494		508
495	/* update blob if blob is null for be with default value */	509	/* update blob if blob is null for be with default value */
@@ -509,7 +523,6 @@ skl_tplg_init_pipe_modules(struct skl skl, struct skl_pipe pipe) · 13 unmodified lines
509	ret = skl_tplg_set_module_params(w, ctx);	523	ret = skl_tplg_set_module_params(w, ctx);
510	if (ret < 0)	524	if (ret < 0)
511	return ret;	525	return ret;
512	skl_tplg_alloc_pipe_mcps(skl, mconfig);
513	}	526	}
514		527
515	return 0;	528	return 0;
@@ -524,7 +537,8 @@ static int skl_tplg_unload_pipe_modules(struct skl_sst *ctx, · 8 unmodified lines
524	list_for_each_entry(w_module, &pipe->w_list, node) {	537	list_for_each_entry(w_module, &pipe->w_list, node) {
525	mconfig = w_module->w->priv;	538	mconfig = w_module->w->priv;
526		539
527	if (mconfig->is_loadable && ctx->dsp->fw_ops.unload_mod)	540	if (mconfig->is_loadable && ctx->dsp->fw_ops.unload_mod &&
		541	mconfig->m_state > SKL_MODULE_UNINIT)
528	return ctx->dsp->fw_ops.unload_mod(ctx->dsp,	542	return ctx->dsp->fw_ops.unload_mod(ctx->dsp,
529	mconfig->id.module_id);	543	mconfig->id.module_id);
530	}	544	}
@@ -558,6 +572,9 @@ static int skl_tplg_mixer_dapm_pre_pmu_event(struct snd_soc_dapm_widget *w, · 27 unmodified lines
558	if (!skl_is_pipe_mem_avail(skl, mconfig))	572	if (!skl_is_pipe_mem_avail(skl, mconfig))
559	return -ENOMEM;	573	return -ENOMEM;
560		574
		575	skl_tplg_alloc_pipe_mem(skl, mconfig);
		576	skl_tplg_alloc_pipe_mcps(skl, mconfig);
		577
561	/*	578	/*
562	* Create a list of modules for pipe.	579	* Create a list of modules for pipe.
563	* This list contains modules from source to sink	580	* This list contains modules from source to sink
@@ -601,9 +618,6 @@ static int skl_tplg_mixer_dapm_pre_pmu_event(struct snd_soc_dapm_widget *w, · 37 unmodified lines
601	src_module = dst_module;	618	src_module = dst_module;
602	}	619	}
603		620
604	skl_tplg_alloc_pipe_mem(skl, mconfig);
605	skl_tplg_alloc_pipe_mcps(skl, mconfig);
606
607	return 0;	621	return 0;
608	}	622	}
609		623

sound/soc/intel/skylake/skl-topology.h+4−4

@@ -274,10 +274,10 @@ struct skl_pipe { · 273 unmodified lines
274		274
275	enum skl_module_state {	275	enum skl_module_state {
276	SKL_MODULE_UNINIT = 0,	276	SKL_MODULE_UNINIT = 0,
277	SKL_MODULE_INIT_DONE = 1,	277	SKL_MODULE_LOADED = 1,
278	SKL_MODULE_LOADED = 2,	278	SKL_MODULE_INIT_DONE = 2,
279	SKL_MODULE_UNLOADED = 3,	279	SKL_MODULE_BIND_DONE = 3,
280	SKL_MODULE_BIND_DONE = 4	280	SKL_MODULE_UNLOADED = 4,
281	};	281	};
282		282
283	struct skl_module_cfg {	283	struct skl_module_cfg {

sound/soc/intel/skylake/skl.c+23−9

@@ -222,6 +222,7 @@ static int skl_suspend(struct device *dev) · 221 unmodified lines
222	struct hdac_ext_bus *ebus = pci_get_drvdata(pci);	222	struct hdac_ext_bus *ebus = pci_get_drvdata(pci);
223	struct skl *skl = ebus_to_skl(ebus);	223	struct skl *skl = ebus_to_skl(ebus);
224	struct hdac_bus *bus = ebus_to_hbus(ebus);	224	struct hdac_bus *bus = ebus_to_hbus(ebus);
		225	int ret = 0;
225		226
226	/*	227	/*
227	* Do not suspend if streams which are marked ignore suspend are	228	* Do not suspend if streams which are marked ignore suspend are
@@ -232,10 +233,20 @@ static int skl_suspend(struct device *dev) · 4 unmodified lines
232	enable_irq_wake(bus->irq);	233	enable_irq_wake(bus->irq);
233	pci_save_state(pci);	234	pci_save_state(pci);
234	pci_disable_device(pci);	235	pci_disable_device(pci);
235	return 0;
236	} else {	236	} else {
237	return _skl_suspend(ebus);	237	ret = _skl_suspend(ebus);
		238	if (ret < 0)
		239	return ret;
		240	}
		241
		242	if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) {
		243	ret = snd_hdac_display_power(bus, false);
		244	if (ret < 0)
		245	dev_err(bus->dev,
		246	"Cannot turn OFF display power on i915\n");
238	}	247	}
		248
		249	return ret;
239	}	250	}
240		251
241	static int skl_resume(struct device *dev)	252	static int skl_resume(struct device *dev)
@@ -316,17 +327,20 @@ static int skl_free(struct hdac_ext_bus *ebus) · 74 unmodified lines
316		327
317	if (bus->irq >= 0)	328	if (bus->irq >= 0)
318	free_irq(bus->irq, (void *)bus);	329	free_irq(bus->irq, (void *)bus);
319	if (bus->remap_addr)
320	iounmap(bus->remap_addr);
321
322	snd_hdac_bus_free_stream_pages(bus);	330	snd_hdac_bus_free_stream_pages(bus);
323	snd_hdac_stream_free_all(ebus);	331	snd_hdac_stream_free_all(ebus);
324	snd_hdac_link_free_all(ebus);	332	snd_hdac_link_free_all(ebus);
		333
		334	if (bus->remap_addr)
		335	iounmap(bus->remap_addr);
		336
325	pci_release_regions(skl->pci);	337	pci_release_regions(skl->pci);
326	pci_disable_device(skl->pci);	338	pci_disable_device(skl->pci);
327		339
328	snd_hdac_ext_bus_exit(ebus);	340	snd_hdac_ext_bus_exit(ebus);
329		341
		342	if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI))
		343	snd_hdac_i915_exit(&ebus->bus);
330	return 0;	344	return 0;
331	}	345	}
332		346
@@ -719,12 +733,12 @@ static void skl_remove(struct pci_dev *pci) · 386 unmodified lines
719	if (skl->tplg)	733	if (skl->tplg)
720	release_firmware(skl->tplg);	734	release_firmware(skl->tplg);
721		735
722	if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI))
723	snd_hdac_i915_exit(&ebus->bus);
724
725	if (pci_dev_run_wake(pci))	736	if (pci_dev_run_wake(pci))
726	pm_runtime_get_noresume(&pci->dev);	737	pm_runtime_get_noresume(&pci->dev);
727	pci_dev_put(pci);	738
		739	/* codec removal, invoke bus_device_remove */
		740	snd_hdac_ext_bus_device_remove(ebus);
		741
728	skl_platform_unregister(&pci->dev);	742	skl_platform_unregister(&pci->dev);
729	skl_free_dsp(skl);	743	skl_free_dsp(skl);
730	skl_machine_device_unregister(skl);	744	skl_machine_device_unregister(skl);

sound/soc/soc-dapm.c+7−0

@@ -2188,6 +2188,13 @@ static ssize_t dapm_widget_show_component(struct snd_soc_component *cmpnt, · 2187 unmodified lines
2188	int count = 0;	2188	int count = 0;
2189	char *state = "not set";	2189	char *state = "not set";
2190		2190
		2191	/* card won't be set for the dummy component, as a spot fix
		2192	* we're checking for that case specifically here but in future
		2193	* we will ensure that the dummy component looks like others.
		2194	*/
		2195	if (!cmpnt->card)
		2196	return 0;
		2197
2191	list_for_each_entry(w, &cmpnt->card->widgets, list) {	2198	list_for_each_entry(w, &cmpnt->card->widgets, list) {
2192	if (w->dapm != dapm)	2199	if (w->dapm != dapm)
2193	continue;	2200	continue;

@@ -247,8 +247,8 @@ int mlx5_query_port_admin_status(struct mlx5_core_dev *dev, · 246 unmodified lines
247	}	247	}
248	EXPORT_SYMBOL_GPL(mlx5_query_port_admin_status);	248	EXPORT_SYMBOL_GPL(mlx5_query_port_admin_status);
249		249
250	static void mlx5_query_port_mtu(struct mlx5_core_dev dev, int admin_mtu,	250	static void mlx5_query_port_mtu(struct mlx5_core_dev dev, u16 admin_mtu,
251	int max_mtu, int oper_mtu, u8 port)	251	u16 max_mtu, u16 oper_mtu, u8 port)
252	{	252	{
253	u32 in[MLX5_ST_SZ_DW(pmtu_reg)];	253	u32 in[MLX5_ST_SZ_DW(pmtu_reg)];
254	u32 out[MLX5_ST_SZ_DW(pmtu_reg)];	254	u32 out[MLX5_ST_SZ_DW(pmtu_reg)];
@@ -268,7 +268,7 @@ static void mlx5_query_port_mtu(struct mlx5_core_dev dev, int admin_mtu, · 13 unmodified lines
268	*admin_mtu = MLX5_GET(pmtu_reg, out, admin_mtu);	268	*admin_mtu = MLX5_GET(pmtu_reg, out, admin_mtu);
269	}	269	}
270		270
271	int mlx5_set_port_mtu(struct mlx5_core_dev *dev, int mtu, u8 port)	271	int mlx5_set_port_mtu(struct mlx5_core_dev *dev, u16 mtu, u8 port)
272	{	272	{
273	u32 in[MLX5_ST_SZ_DW(pmtu_reg)];	273	u32 in[MLX5_ST_SZ_DW(pmtu_reg)];
274	u32 out[MLX5_ST_SZ_DW(pmtu_reg)];	274	u32 out[MLX5_ST_SZ_DW(pmtu_reg)];
@@ -283,14 +283,14 @@ int mlx5_set_port_mtu(struct mlx5_core_dev *dev, int mtu, u8 port) · 8 unmodified lines
283	}	283	}
284	EXPORT_SYMBOL_GPL(mlx5_set_port_mtu);	284	EXPORT_SYMBOL_GPL(mlx5_set_port_mtu);
285		285
286	void mlx5_query_port_max_mtu(struct mlx5_core_dev dev, int max_mtu,	286	void mlx5_query_port_max_mtu(struct mlx5_core_dev dev, u16 max_mtu,
287	u8 port)	287	u8 port)
288	{	288	{
289	mlx5_query_port_mtu(dev, NULL, max_mtu, NULL, port);	289	mlx5_query_port_mtu(dev, NULL, max_mtu, NULL, port);
290	}	290	}
291	EXPORT_SYMBOL_GPL(mlx5_query_port_max_mtu);	291	EXPORT_SYMBOL_GPL(mlx5_query_port_max_mtu);
292		292
293	void mlx5_query_port_oper_mtu(struct mlx5_core_dev dev, int oper_mtu,	293	void mlx5_query_port_oper_mtu(struct mlx5_core_dev dev, u16 oper_mtu,
294	u8 port)	294	u8 port)
295	{	295	{
296	mlx5_query_port_mtu(dev, NULL, NULL, oper_mtu, port);	296	mlx5_query_port_mtu(dev, NULL, NULL, oper_mtu, port);