Gen-12 has a new compression format, add a new modifier to indicate that.
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| @@ -410,6 +410,17 @@ extern "C" { · 409 unmodified lines | ||
| 410 | 410 | #define I915_FORMAT_MOD_Y_TILED_CCS fourcc_mod_code(INTEL, 4) |
| 411 | 411 | #define I915_FORMAT_MOD_Yf_TILED_CCS fourcc_mod_code(INTEL, 5) |
| 412 | 412 | |
| 413 | +/* | |
| 414 | + * Intel color control surfaces (CCS) for Gen-12 render compression. | |
| 415 | + * | |
| 416 | + * The main surface is Y-tiled and at plane index 0, the CCS is linear and | |
| 417 | + * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in | |
| 418 | + * main surface. In other words, 4 bits in CCS map to a main surface cache | |
| 419 | + * line pair. The main surface pitch is required to be a multiple of four | |
| 420 | + * Y-tile widths. | |
| 421 | + */ | |
| 422 | +#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS fourcc_mod_code(INTEL, 6) | |
| 423 | + | |
| 413 | 424 | /* |
| 414 | 425 | * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks |
| 415 | 426 | * |