Add missing PCI bus link speed 8.0 GT/s and bus link widths of x1, x2, x4 and x8.
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| @@ -489,7 +489,12 @@ · 488 unmodified lines | ||
| 489 | 489 | #define PCI_EXP_LNKSTA_CLS 0x000f /* Current Link Speed */ |
| 490 | 490 | #define PCI_EXP_LNKSTA_CLS_2_5GB 0x0001 /* Current Link Speed 2.5GT/s */ |
| 491 | 491 | #define PCI_EXP_LNKSTA_CLS_5_0GB 0x0002 /* Current Link Speed 5.0GT/s */ |
| 492 | +#define PCI_EXP_LNKSTA_CLS_8_0GB 0x0003 /* Current Link Speed 8.0GT/s */ | |
| 492 | 493 | #define PCI_EXP_LNKSTA_NLW 0x03f0 /* Negotiated Link Width */ |
| 494 | +#define PCI_EXP_LNKSTA_NLW_X1 0x0010 /* Current Link Width x1 */ | |
| 495 | +#define PCI_EXP_LNKSTA_NLW_X2 0x0020 /* Current Link Width x2 */ | |
| 496 | +#define PCI_EXP_LNKSTA_NLW_X4 0x0040 /* Current Link Width x4 */ | |
| 497 | +#define PCI_EXP_LNKSTA_NLW_X8 0x0080 /* Current Link Width x8 */ | |
| 493 | 498 | #define PCI_EXP_LNKSTA_NLW_SHIFT 4 /* start of NLW mask in link status */ |
| 494 | 499 | #define PCI_EXP_LNKSTA_LT 0x0800 /* Link Training */ |
| 495 | 500 | #define PCI_EXP_LNKSTA_SLC 0x1000 /* Slot Clock Configuration */ |