Merge mlx5-next into rdma for-next

From git://git.kernel.org/pub/scm/linux/kernel/git/mellanox/linux Required for dependencies in the next patches. * mlx5-next: net/mlx5: Add rts2rts_qp_counters_set_id field in hca cap net/mlx5: Properly name the generic WQE control field net/mlx5: Introduce TLS TX offload hardware bits and structures net/mlx5: Refactor mlx5_esw_query_functions for modularity net/mlx5: E-Switch prepare functions change handler to be modular net/mlx5: Introduce and use mlx5_eswitch_get_total_vports()

Jason Gunthorpe committed 7 years ago

Commit 5600a412 parents bcde9a8 f8efee013 files · +235 −62Browse files

Unified · Split

13 files

drivers/infiniband/hw/mlx5/ib_rep.c +1 −1
drivers/net/ethernet/mellanox/mlx5/core/eswitch.c +33 −9
drivers/net/ethernet/mellanox/mlx5/core/eswitch.h +3 −4
drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c +28 −18
drivers/net/ethernet/mellanox/mlx5/core/fs_core.c +15 −11
drivers/net/ethernet/mellanox/mlx5/core/sriov.c +9 −6
drivers/net/ethernet/mellanox/mlx5/core/vport.c +15 −0
include/linux/mlx5/device.h +14 −0
include/linux/mlx5/driver.h +5 −4
include/linux/mlx5/eswitch.h +3 −0
include/linux/mlx5/mlx5_ifc.h +103 −5
include/linux/mlx5/qp.h +6 −1
include/linux/mlx5/vport.h +0 −3

drivers/infiniband/hw/mlx5/ib_rep.c+1−1

@@ -29,7 +29,7 @@ mlx5_ib_set_vport_rep(struct mlx5_core_dev dev, struct mlx5_eswitch_rep rep) · 28 unmodified lines
29	29	static int
30	30	mlx5_ib_vport_rep_load(struct mlx5_core_dev dev, struct mlx5_eswitch_rep rep)
31	31	{
32		− int num_ports = MLX5_TOTAL_VPORTS(dev);
	32	+ int num_ports = mlx5_eswitch_get_total_vports(dev);
33	33	const struct mlx5_ib_profile *profile;
34	34	struct mlx5_ib_dev *ibdev;
35	35	int vport_index;

drivers/net/ethernet/mellanox/mlx5/core/eswitch.c+33−9

@@ -1715,14 +1715,34 @@ static int eswitch_vport_event(struct notifier_block *nb, · 1714 unmodified lines
1715	1715	return NOTIFY_OK;
1716	1716	}
1717	1717
1718		−int mlx5_esw_query_functions(struct mlx5_core_dev dev, u32 out, int outlen)
	1718	+/**
	1719	+ * mlx5_esw_query_functions - Returns raw output about functions state
	1720	+ * @dev: Pointer to device to query
	1721	+ *
	1722	+ * mlx5_esw_query_functions() allocates and returns functions changed
	1723	+ * raw output memory pointer from device on success. Otherwise returns ERR_PTR.
	1724	+ * Caller must free the memory using kvfree() when valid pointer is returned.
	1725	+ */
	1726	+const u32 mlx5_esw_query_functions(struct mlx5_core_dev dev)
1719	1727	{
	1728	+ int outlen = MLX5_ST_SZ_BYTES(query_esw_functions_out);
1720	1729	u32 in[MLX5_ST_SZ_DW(query_esw_functions_in)] = {};
	1730	+ u32 *out;
	1731	+ int err;
	1732	+
	1733	+ out = kvzalloc(outlen, GFP_KERNEL);
	1734	+ if (!out)
	1735	+ return ERR_PTR(-ENOMEM);
1721	1736
1722	1737	MLX5_SET(query_esw_functions_in, in, opcode,
1723	1738	MLX5_CMD_OP_QUERY_ESW_FUNCTIONS);
1724	1739
1725		− return mlx5_cmd_exec(dev, in, sizeof(in), out, outlen);
	1740	+ err = mlx5_cmd_exec(dev, in, sizeof(in), out, outlen);
	1741	+ if (!err)
	1742	+ return out;
	1743	+
	1744	+ kvfree(out);
	1745	+ return ERR_PTR(err);
1726	1746	}
1727	1747
1728	1748	static void mlx5_eswitch_event_handlers_register(struct mlx5_eswitch *esw)
@@ -1868,14 +1888,16 @@ void mlx5_eswitch_disable(struct mlx5_eswitch *esw) · 139 unmodified lines
1868	1888
1869	1889	int mlx5_eswitch_init(struct mlx5_core_dev *dev)
1870	1890	{
1871		− int total_vports = MLX5_TOTAL_VPORTS(dev);
1872	1891	struct mlx5_eswitch *esw;
1873	1892	struct mlx5_vport *vport;
	1893	+ int total_vports;
1874	1894	int err, i;
1875	1895
1876	1896	if (!MLX5_VPORT_MANAGER(dev))
1877	1897	return 0;
1878	1898
	1899	+ total_vports = mlx5_eswitch_get_total_vports(dev);
	1900	+
1879	1901	esw_info(dev,
1880	1902	"Total vports %d, per vport: max uc(%d) max mc(%d)\n",
1881	1903	total_vports,
@@ -2525,8 +2547,7 @@ bool mlx5_esw_multipath_prereq(struct mlx5_core_dev *dev0, · 643 unmodified lines
2525	2547
2526	2548	void mlx5_eswitch_update_num_of_vfs(struct mlx5_eswitch *esw, const int num_vfs)
2527	2549	{
2528		− u32 out[MLX5_ST_SZ_DW(query_esw_functions_out)] = {};
2529		− int err;
	2550	+ const u32 *out;
2530	2551
2531	2552	WARN_ON_ONCE(esw->mode != MLX5_ESWITCH_NONE);
2532	2553
@@ -2535,8 +2556,11 @@ void mlx5_eswitch_update_num_of_vfs(struct mlx5_eswitch *esw, const int num_vfs) · 2 unmodified lines
2535	2556	return;
2536	2557	}
2537	2558
2538		− err = mlx5_esw_query_functions(esw->dev, out, sizeof(out));
2539		− if (!err)
2540		− esw->esw_funcs.num_vfs = MLX5_GET(query_esw_functions_out, out,
2541		− host_params_context.host_num_of_vfs);
	2559	+ out = mlx5_esw_query_functions(esw->dev);
	2560	+ if (IS_ERR(out))
	2561	+ return;
	2562	+
	2563	+ esw->esw_funcs.num_vfs = MLX5_GET(query_esw_functions_out, out,
	2564	+ host_params_context.host_num_of_vfs);
	2565	+ kvfree(out);
2542	2566	}

drivers/net/ethernet/mellanox/mlx5/core/eswitch.h+3−4

@@ -403,7 +403,7 @@ bool mlx5_esw_lag_prereq(struct mlx5_core_dev *dev0, · 402 unmodified lines
403	403	bool mlx5_esw_multipath_prereq(struct mlx5_core_dev *dev0,
404	404	struct mlx5_core_dev *dev1);
405	405
406		−int mlx5_esw_query_functions(struct mlx5_core_dev dev, u32 out, int outlen);
	406	+const u32 mlx5_esw_query_functions(struct mlx5_core_dev dev);
407	407
408	408	#define MLX5_DEBUG_ESWITCH_MASK BIT(3)
409	409
@@ -560,10 +560,9 @@ static inline int mlx5_eswitch_enable(struct mlx5_eswitch *esw, int mode) { ret · 150 unmodified lines
560	560	static inline void mlx5_eswitch_disable(struct mlx5_eswitch *esw) {}
561	561	static inline bool mlx5_esw_lag_prereq(struct mlx5_core_dev dev0, struct mlx5_core_dev dev1) { return true; }
562	562	static inline bool mlx5_eswitch_is_funcs_handler(struct mlx5_core_dev *dev) { return false; }
563		−static inline int
564		−mlx5_esw_query_functions(struct mlx5_core_dev dev, u32 out, int outlen)
	563	+static inline const u32 mlx5_esw_query_functions(struct mlx5_core_dev dev)
565	564	{
566		− return -EOPNOTSUPP;
	565	+ return ERR_PTR(-EOPNOTSUPP);
567	566	}
568	567
569	568	static inline void mlx5_eswitch_update_num_of_vfs(struct mlx5_eswitch *esw, const int num_vfs) {}

drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c+28−18

@@ -1395,7 +1395,7 @@ void esw_offloads_cleanup_reps(struct mlx5_eswitch *esw) · 1394 unmodified lines
1395	1395
1396	1396	int esw_offloads_init_reps(struct mlx5_eswitch *esw)
1397	1397	{
1398		− int total_vports = MLX5_TOTAL_VPORTS(esw->dev);
	1398	+ int total_vports = esw->total_vports;
1399	1399	struct mlx5_core_dev *dev = esw->dev;
1400	1400	struct mlx5_eswitch_rep *rep;
1401	1401	u8 hw_id[ETH_ALEN], rep_type;
@@ -2047,38 +2047,48 @@ static void esw_offloads_steering_cleanup(struct mlx5_eswitch *esw) · 645 unmodified lines
2047	2047	esw_destroy_offloads_acl_tables(esw);
2048	2048	}
2049	2049
2050		−static void esw_functions_changed_event_handler(struct work_struct *work)
	2050	+static void
	2051	+esw_vfs_changed_event_handler(struct mlx5_eswitch esw, const u32 out)
2051	2052	{
2052		− u32 out[MLX5_ST_SZ_DW(query_esw_functions_out)] = {};
2053		− struct mlx5_host_work *host_work;
2054		− struct mlx5_eswitch *esw;
2055	2053	bool host_pf_disabled;
2056		− u16 num_vfs = 0;
2057		− int err;
	2054	+ u16 new_num_vfs;
2058	2055
2059		− host_work = container_of(work, struct mlx5_host_work, work);
2060		− esw = host_work->esw;
2061		−
2062		− err = mlx5_esw_query_functions(esw->dev, out, sizeof(out));
2063		− num_vfs = MLX5_GET(query_esw_functions_out, out,
2064		− host_params_context.host_num_of_vfs);
	2056	+ new_num_vfs = MLX5_GET(query_esw_functions_out, out,
	2057	+ host_params_context.host_num_of_vfs);
2065	2058	host_pf_disabled = MLX5_GET(query_esw_functions_out, out,
2066	2059	host_params_context.host_pf_disabled);
2067		− if (err \|\| host_pf_disabled \|\| num_vfs == esw->esw_funcs.num_vfs)
2068		− goto out;
	2060	+
	2061	+ if (new_num_vfs == esw->esw_funcs.num_vfs \|\| host_pf_disabled)
	2062	+ return;
2069	2063
2070	2064	/* Number of VFs can only change from "0 to x" or "x to 0". */
2071	2065	if (esw->esw_funcs.num_vfs > 0) {
2072	2066	esw_offloads_unload_vf_reps(esw, esw->esw_funcs.num_vfs);
2073	2067	} else {
2074		− err = esw_offloads_load_vf_reps(esw, num_vfs);
	2068	+ int err;
2075	2069
	2070	+ err = esw_offloads_load_vf_reps(esw, new_num_vfs);
2076	2071	if (err)
2077		− goto out;
	2072	+ return;
2078	2073	}
	2074	+ esw->esw_funcs.num_vfs = new_num_vfs;
	2075	+}
2079	2076
2080		− esw->esw_funcs.num_vfs = num_vfs;
	2077	+static void esw_functions_changed_event_handler(struct work_struct *work)
	2078	+{
	2079	+ struct mlx5_host_work *host_work;
	2080	+ struct mlx5_eswitch *esw;
	2081	+ const u32 *out;
	2082	+
	2083	+ host_work = container_of(work, struct mlx5_host_work, work);
	2084	+ esw = host_work->esw;
	2085	+
	2086	+ out = mlx5_esw_query_functions(esw->dev);
	2087	+ if (IS_ERR(out))
	2088	+ goto out;
2081	2089
	2090	+ esw_vfs_changed_event_handler(esw, out);
	2091	+ kvfree(out);
2082	2092	out:
2083	2093	kfree(host_work);
2084	2094	}

drivers/net/ethernet/mellanox/mlx5/core/fs_core.c+15−11

@@ -2092,7 +2092,7 @@ struct mlx5_flow_namespace *mlx5_get_flow_vport_acl_namespace(struct mlx5_core_d · 2091 unmodified lines
2092	2092	{
2093	2093	struct mlx5_flow_steering *steering = dev->priv.steering;
2094	2094
2095		− if (!steering \|\| vport >= MLX5_TOTAL_VPORTS(dev))
	2095	+ if (!steering \|\| vport >= mlx5_eswitch_get_total_vports(dev))
2096	2096	return NULL;
2097	2097
2098	2098	switch (type) {
@@ -2423,7 +2423,7 @@ static void cleanup_egress_acls_root_ns(struct mlx5_core_dev *dev) · 324 unmodified lines
2423	2423	if (!steering->esw_egress_root_ns)
2424	2424	return;
2425	2425
2426		− for (i = 0; i < MLX5_TOTAL_VPORTS(dev); i++)
	2426	+ for (i = 0; i < mlx5_eswitch_get_total_vports(dev); i++)
2427	2427	cleanup_root_ns(steering->esw_egress_root_ns[i]);
2428	2428
2429	2429	kfree(steering->esw_egress_root_ns);
@@ -2438,7 +2438,7 @@ static void cleanup_ingress_acls_root_ns(struct mlx5_core_dev *dev) · 8 unmodified lines
2438	2438	if (!steering->esw_ingress_root_ns)
2439	2439	return;
2440	2440
2441		− for (i = 0; i < MLX5_TOTAL_VPORTS(dev); i++)
	2441	+ for (i = 0; i < mlx5_eswitch_get_total_vports(dev); i++)
2442	2442	cleanup_root_ns(steering->esw_ingress_root_ns[i]);
2443	2443
2444	2444	kfree(steering->esw_ingress_root_ns);
@@ -2606,16 +2606,18 @@ static int init_ingress_acl_root_ns(struct mlx5_flow_steering *steering, int vpo · 161 unmodified lines
2606	2606	static int init_egress_acls_root_ns(struct mlx5_core_dev *dev)
2607	2607	{
2608	2608	struct mlx5_flow_steering *steering = dev->priv.steering;
	2609	+ int total_vports = mlx5_eswitch_get_total_vports(dev);
2609	2610	int err;
2610	2611	int i;
2611	2612
2612		− steering->esw_egress_root_ns = kcalloc(MLX5_TOTAL_VPORTS(dev),
2613		− sizeof(*steering->esw_egress_root_ns),
2614		− GFP_KERNEL);
	2613	+ steering->esw_egress_root_ns =
	2614	+ kcalloc(total_vports,
	2615	+ sizeof(*steering->esw_egress_root_ns),
	2616	+ GFP_KERNEL);
2615	2617	if (!steering->esw_egress_root_ns)
2616	2618	return -ENOMEM;
2617	2619
2618		− for (i = 0; i < MLX5_TOTAL_VPORTS(dev); i++) {
	2620	+ for (i = 0; i < total_vports; i++) {
2619	2621	err = init_egress_acl_root_ns(steering, i);
2620	2622	if (err)
2621	2623	goto cleanup_root_ns;
@@ -2634,16 +2636,18 @@ cleanup_root_ns: · 12 unmodified lines
2634	2636	static int init_ingress_acls_root_ns(struct mlx5_core_dev *dev)
2635	2637	{
2636	2638	struct mlx5_flow_steering *steering = dev->priv.steering;
	2639	+ int total_vports = mlx5_eswitch_get_total_vports(dev);
2637	2640	int err;
2638	2641	int i;
2639	2642
2640		− steering->esw_ingress_root_ns = kcalloc(MLX5_TOTAL_VPORTS(dev),
2641		− sizeof(*steering->esw_ingress_root_ns),
2642		− GFP_KERNEL);
	2643	+ steering->esw_ingress_root_ns =
	2644	+ kcalloc(total_vports,
	2645	+ sizeof(*steering->esw_ingress_root_ns),
	2646	+ GFP_KERNEL);
2643	2647	if (!steering->esw_ingress_root_ns)
2644	2648	return -ENOMEM;
2645	2649
2646		− for (i = 0; i < MLX5_TOTAL_VPORTS(dev); i++) {
	2650	+ for (i = 0; i < total_vports; i++) {
2647	2651	err = init_ingress_acl_root_ns(steering, i);
2648	2652	if (err)
2649	2653	goto cleanup_root_ns;

drivers/net/ethernet/mellanox/mlx5/core/sriov.c+9−6

@@ -197,22 +197,25 @@ void mlx5_sriov_detach(struct mlx5_core_dev *dev) · 196 unmodified lines
197	197
198	198	static u16 mlx5_get_max_vfs(struct mlx5_core_dev *dev)
199	199	{
200		− u32 out[MLX5_ST_SZ_DW(query_esw_functions_out)] = {};
201	200	u16 host_total_vfs;
202		− int err;
	201	+ const u32 *out;
203	202
204	203	if (mlx5_core_is_ecpf_esw_manager(dev)) {
205		− err = mlx5_esw_query_functions(dev, out, sizeof(out));
206		− host_total_vfs = MLX5_GET(query_esw_functions_out, out,
207		− host_params_context.host_total_vfs);
	204	+ out = mlx5_esw_query_functions(dev);
208	205
209	206	/* Old FW doesn't support getting total_vfs from esw func
210	207	* but supports getting it from pci_sriov.
211	208	*/
212		− if (!err && host_total_vfs)
	209	+ if (IS_ERR(out))
	210	+ goto done;
	211	+ host_total_vfs = MLX5_GET(query_esw_functions_out, out,
	212	+ host_params_context.host_total_vfs);
	213	+ kvfree(out);
	214	+ if (host_total_vfs)
213	215	return host_total_vfs;
214	216	}
215	217
	218	+done:
216	219	return pci_sriov_get_totalvfs(dev->pdev);
217	220	}
218	221

drivers/net/ethernet/mellanox/mlx5/core/vport.c+15−0

@@ -34,6 +34,7 @@ · 33 unmodified lines
34	34	#include <linux/etherdevice.h>
35	35	#include <linux/mlx5/driver.h>
36	36	#include <linux/mlx5/vport.h>
	37	+#include <linux/mlx5/eswitch.h>
37	38	#include "mlx5_core.h"
38	39
39	40	/* Mutex to hold while enabling or disabling RoCE */
@@ -1165,3 +1166,17 @@ u64 mlx5_query_nic_system_image_guid(struct mlx5_core_dev *mdev) · 1125 unmodified lines
1165	1166	return tmp;
1166	1167	}
1167	1168	EXPORT_SYMBOL_GPL(mlx5_query_nic_system_image_guid);
	1169	+
	1170	+/**
	1171	+ * mlx5_eswitch_get_total_vports - Get total vports of the eswitch
	1172	+ *
	1173	+ * @dev: Pointer to core device
	1174	+ *
	1175	+ * mlx5_eswitch_get_total_vports returns total number of vports for
	1176	+ * the eswitch.
	1177	+ */
	1178	+u16 mlx5_eswitch_get_total_vports(const struct mlx5_core_dev *dev)
	1179	+{
	1180	+ return MLX5_SPECIAL_VPORTS(dev) + mlx5_core_max_vfs(dev);
	1181	+}
	1182	+EXPORT_SYMBOL(mlx5_eswitch_get_total_vports);

include/linux/mlx5/device.h+14−0

@@ -437,6 +437,7 @@ enum { · 436 unmodified lines
437	437	MLX5_OPCODE_SET_PSV = 0x20,
438	438	MLX5_OPCODE_GET_PSV = 0x21,
439	439	MLX5_OPCODE_CHECK_PSV = 0x22,
	440	+ MLX5_OPCODE_DUMP = 0x23,
440	441	MLX5_OPCODE_RGET_PSV = 0x26,
441	442	MLX5_OPCODE_RCHECK_PSV = 0x27,
442	443
@@ -444,6 +445,14 @@ enum { · 1 unmodified line
444	445
445	446	};
446	447
	448	+enum {
	449	+ MLX5_OPC_MOD_TLS_TIS_STATIC_PARAMS = 0x20,
	450	+};
	451	+
	452	+enum {
	453	+ MLX5_OPC_MOD_TLS_TIS_PROGRESS_PARAMS = 0x20,
	454	+};
	455	+
447	456	enum {
448	457	MLX5_SET_PORT_RESET_QKEY = 0,
449	458	MLX5_SET_PORT_GUID0 = 16,
@@ -1077,6 +1086,8 @@ enum mlx5_cap_type { · 627 unmodified lines
1077	1086	MLX5_CAP_DEBUG,
1078	1087	MLX5_CAP_RESERVED_14,
1079	1088	MLX5_CAP_DEV_MEM,
	1089	+ MLX5_CAP_RESERVED_16,
	1090	+ MLX5_CAP_TLS,
1080	1091	MLX5_CAP_DEV_EVENT = 0x14,
1081	1092	/* NUM OF CAP Types */
1082	1093	MLX5_CAP_NUM
@@ -1256,6 +1267,9 @@ enum mlx5_qcam_feature_groups { · 173 unmodified lines
1256	1267	#define MLX5_CAP64_DEV_MEM(mdev, cap)\
1257	1268	MLX5_GET64(device_mem_cap, mdev->caps.hca_cur[MLX5_CAP_DEV_MEM], cap)
1258	1269
	1270	+#define MLX5_CAP_TLS(mdev, cap) \
	1271	+ MLX5_GET(tls_cap, (mdev)->caps.hca_cur[MLX5_CAP_TLS], cap)
	1272	+
1259	1273	#define MLX5_CAP_DEV_EVENT(mdev, cap)\
1260	1274	MLX5_ADDR_OF(device_event_cap, (mdev)->caps.hca_cur[MLX5_CAP_DEV_EVENT], cap)
1261	1275

include/linux/mlx5/driver.h+5−4

@@ -1085,7 +1085,7 @@ enum { · 1084 unmodified lines
1085	1085	MLX5_PCI_DEV_IS_VF = 1 << 0,
1086	1086	};
1087	1087
1088		−static inline bool mlx5_core_is_pf(struct mlx5_core_dev *dev)
	1088	+static inline bool mlx5_core_is_pf(const struct mlx5_core_dev *dev)
1089	1089	{
1090	1090	return dev->coredev_type == MLX5_COREDEV_PF;
1091	1091	}
@@ -1095,17 +1095,18 @@ static inline bool mlx5_core_is_ecpf(struct mlx5_core_dev *dev) · 3 unmodified lines
1095	1095	return dev->caps.embedded_cpu;
1096	1096	}
1097	1097
1098		−static inline bool mlx5_core_is_ecpf_esw_manager(struct mlx5_core_dev *dev)
	1098	+static inline bool
	1099	+mlx5_core_is_ecpf_esw_manager(const struct mlx5_core_dev *dev)
1099	1100	{
1100	1101	return dev->caps.embedded_cpu && MLX5_CAP_GEN(dev, eswitch_manager);
1101	1102	}
1102	1103
1103		−static inline bool mlx5_ecpf_vport_exists(struct mlx5_core_dev *dev)
	1104	+static inline bool mlx5_ecpf_vport_exists(const struct mlx5_core_dev *dev)
1104	1105	{
1105	1106	return mlx5_core_is_pf(dev) && MLX5_CAP_ESW(dev, ecpf_vport_exists);
1106	1107	}
1107	1108
1108		−static inline u16 mlx5_core_max_vfs(struct mlx5_core_dev *dev)
	1109	+static inline u16 mlx5_core_max_vfs(const struct mlx5_core_dev *dev)
1109	1110	{
1110	1111	return dev->priv.sriov.max_vfs;
1111	1112	}

include/linux/mlx5/eswitch.h+3−0

@@ -66,6 +66,8 @@ struct mlx5_flow_handle * · 65 unmodified lines
66	66	mlx5_eswitch_add_send_to_vport_rule(struct mlx5_eswitch *esw,
67	67	u16 vport_num, u32 sqn);
68	68
	69	+u16 mlx5_eswitch_get_total_vports(const struct mlx5_core_dev *dev);
	70	+
69	71	#ifdef CONFIG_MLX5_ESWITCH
70	72	enum devlink_eswitch_encap_mode
71	73	mlx5_eswitch_get_encap_mode(const struct mlx5_core_dev *dev);
@@ -93,4 +95,5 @@ mlx5_eswitch_get_vport_metadata_for_match(const struct mlx5_eswitch *esw, · 21 unmodified lines
93	95	return 0;
94	96	};
95	97	#endif /* CONFIG_MLX5_ESWITCH */
	98	+
96	99	#endif

include/linux/mlx5/mlx5_ifc.h+103−5

@@ -973,6 +973,16 @@ struct mlx5_ifc_vector_calc_cap_bits { · 972 unmodified lines
973	973	u8 reserved_at_c0[0x720];
974	974	};
975	975
	976	+struct mlx5_ifc_tls_cap_bits {
	977	+ u8 tls_1_2_aes_gcm_128[0x1];
	978	+ u8 tls_1_3_aes_gcm_128[0x1];
	979	+ u8 tls_1_2_aes_gcm_256[0x1];
	980	+ u8 tls_1_3_aes_gcm_256[0x1];
	981	+ u8 reserved_at_4[0x1c];
	982	+
	983	+ u8 reserved_at_20[0x7e0];
	984	+};
	985	+
976	986	enum {
977	987	MLX5_WQ_TYPE_LINKED_LIST = 0x0,
978	988	MLX5_WQ_TYPE_CYCLIC = 0x1,
@@ -1086,7 +1096,9 @@ struct mlx5_ifc_cmd_hca_cap_bits { · 107 unmodified lines
1086	1096	u8 cc_modify_allowed[0x1];
1087	1097	u8 start_pad[0x1];
1088	1098	u8 cache_line_128byte[0x1];
1089		− u8 reserved_at_165[0xa];
	1099	+ u8 reserved_at_165[0x4];
	1100	+ u8 rts2rts_qp_counters_set_id[0x1];
	1101	+ u8 reserved_at_16a[0x5];
1090	1102	u8 qcam_reg[0x1];
1091	1103	u8 gid_table_size[0x10];
1092	1104
@@ -1303,7 +1315,8 @@ struct mlx5_ifc_cmd_hca_cap_bits { · 210 unmodified lines
1303	1315
1304	1316	u8 reserved_at_440[0x20];
1305	1317
1306		− u8 reserved_at_460[0x3];
	1318	+ u8 tls[0x1];
	1319	+ u8 reserved_at_461[0x2];
1307	1320	u8 log_max_uctx[0x5];
1308	1321	u8 reserved_at_468[0x3];
1309	1322	u8 log_max_umem[0x5];
@@ -1328,7 +1341,9 @@ struct mlx5_ifc_cmd_hca_cap_bits { · 18 unmodified lines
1328	1341	u8 max_geneve_tlv_option_data_len[0x5];
1329	1342	u8 reserved_at_570[0x10];
1330	1343
1331		− u8 reserved_at_580[0x3c];
	1344	+ u8 reserved_at_580[0x33];
	1345	+ u8 log_max_dek[0x5];
	1346	+ u8 reserved_at_5b8[0x4];
1332	1347	u8 mini_cqe_resp_stride_index[0x1];
1333	1348	u8 cqe_128_always[0x1];
1334	1349	u8 cqe_compression_128[0x1];
@@ -2607,6 +2622,7 @@ union mlx5_ifc_hca_cap_union_bits { · 1272 unmodified lines
2607	2622	struct mlx5_ifc_qos_cap_bits qos_cap;
2608	2623	struct mlx5_ifc_debug_cap_bits debug_cap;
2609	2624	struct mlx5_ifc_fpga_cap_bits fpga_cap;
	2625	+ struct mlx5_ifc_tls_cap_bits tls_cap;
2610	2626	u8 reserved_at_0[0x8000];
2611	2627	};
2612	2628
@@ -2746,7 +2762,8 @@ struct mlx5_ifc_traffic_counter_bits { · 133 unmodified lines
2746	2762
2747	2763	struct mlx5_ifc_tisc_bits {
2748	2764	u8 strict_lag_tx_port_affinity[0x1];
2749		− u8 reserved_at_1[0x3];
	2765	+ u8 tls_en[0x1];
	2766	+ u8 reserved_at_1[0x2];
2750	2767	u8 lag_tx_port_affinity[0x04];
2751	2768
2752	2769	u8 reserved_at_8[0x4];
@@ -2760,7 +2777,11 @@ struct mlx5_ifc_tisc_bits { · 7 unmodified lines
2760	2777
2761	2778	u8 reserved_at_140[0x8];
2762	2779	u8 underlay_qpn[0x18];
2763		− u8 reserved_at_160[0x3a0];
	2780	+
	2781	+ u8 reserved_at_160[0x8];
	2782	+ u8 pd[0x18];
	2783	+
	2784	+ u8 reserved_at_180[0x380];
2764	2785	};
2765	2786
2766	2787	enum {
@@ -9965,4 +9986,81 @@ struct mlx5_ifc_affiliated_event_header_bits { · 7198 unmodified lines
9965	9986	u8 obj_id[0x20];
9966	9987	};
9967	9988
	9989	+enum {
	9990	+ MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT(0xc),
	9991	+};
	9992	+
	9993	+enum {
	9994	+ MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc,
	9995	+};
	9996	+
	9997	+struct mlx5_ifc_encryption_key_obj_bits {
	9998	+ u8 modify_field_select[0x40];
	9999	+
	10000	+ u8 reserved_at_40[0x14];
	10001	+ u8 key_size[0x4];
	10002	+ u8 reserved_at_58[0x4];
	10003	+ u8 key_type[0x4];
	10004	+
	10005	+ u8 reserved_at_60[0x8];
	10006	+ u8 pd[0x18];
	10007	+
	10008	+ u8 reserved_at_80[0x180];
	10009	+ u8 key[8][0x20];
	10010	+
	10011	+ u8 reserved_at_300[0x500];
	10012	+};
	10013	+
	10014	+struct mlx5_ifc_create_encryption_key_in_bits {
	10015	+ struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
	10016	+ struct mlx5_ifc_encryption_key_obj_bits encryption_key_object;
	10017	+};
	10018	+
	10019	+enum {
	10020	+ MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0,
	10021	+ MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1,
	10022	+};
	10023	+
	10024	+enum {
	10025	+ MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_DEK = 0x1,
	10026	+};
	10027	+
	10028	+struct mlx5_ifc_tls_static_params_bits {
	10029	+ u8 const_2[0x2];
	10030	+ u8 tls_version[0x4];
	10031	+ u8 const_1[0x2];
	10032	+ u8 reserved_at_8[0x14];
	10033	+ u8 encryption_standard[0x4];
	10034	+
	10035	+ u8 reserved_at_20[0x20];
	10036	+
	10037	+ u8 initial_record_number[0x40];
	10038	+
	10039	+ u8 resync_tcp_sn[0x20];
	10040	+
	10041	+ u8 gcm_iv[0x20];
	10042	+
	10043	+ u8 implicit_iv[0x40];
	10044	+
	10045	+ u8 reserved_at_100[0x8];
	10046	+ u8 dek_index[0x18];
	10047	+
	10048	+ u8 reserved_at_120[0xe0];
	10049	+};
	10050	+
	10051	+struct mlx5_ifc_tls_progress_params_bits {
	10052	+ u8 valid[0x1];
	10053	+ u8 reserved_at_1[0x7];
	10054	+ u8 pd[0x18];
	10055	+
	10056	+ u8 next_record_tcp_sn[0x20];
	10057	+
	10058	+ u8 hw_resync_tcp_sn[0x20];
	10059	+
	10060	+ u8 record_tracker_state[0x2];
	10061	+ u8 auth_state[0x2];
	10062	+ u8 reserved_at_64[0x4];
	10063	+ u8 hw_offset_record_number[0x18];
	10064	+};
	10065	+
9968	10066	#endif /* MLX5_IFC_H */

include/linux/mlx5/qp.h+6−1

@@ -203,7 +203,12 @@ struct mlx5_wqe_ctrl_seg { · 202 unmodified lines
203	203	u8 signature;
204	204	u8 rsvd[2];
205	205	u8 fm_ce_se;
206		− __be32 imm;
	206	+ union {
	207	+ __be32 general_id;
	208	+ __be32 imm;
	209	+ __be32 umr_mkey;
	210	+ __be32 tisn;
	211	+ };
207	212	};
208	213
209	214	#define MLX5_WQE_CTRL_DS_MASK 0x3f

include/linux/mlx5/vport.h+0−3

@@ -44,9 +44,6 @@ · 43 unmodified lines
44	44	MLX5_VPORT_UPLINK_PLACEHOLDER + \
45	45	MLX5_VPORT_ECPF_PLACEHOLDER(mdev))
46	46
47		−#define MLX5_TOTAL_VPORTS(mdev) (MLX5_SPECIAL_VPORTS(mdev) + \
48		− mlx5_core_max_vfs(mdev))
49		−
50	47	#define MLX5_VPORT_MANAGER(mdev) \
51	48	(MLX5_CAP_GEN(mdev, vport_group_manager) && \
52	49	(MLX5_CAP_GEN(mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) && \

Merge mlx5-next into rdma for-next

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