First feature request for 4.19. Highlights: - Add initial amdgpu documentation - Add initial GPU scheduler documention - GPU scheduler fixes for dying processes - Add support for the JPEG engine on VCN - Switch CI to use powerplay by default - EDC support for CZ - More powerplay cleanups - Misc DC fixes Signed-off-by: Dave Airlie <airlied@redhat.com>
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| @@ -72,6 +72,29 @@ extern "C" { · 71 unmodified lines | |||
| 72 | #define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle) | 72 | #define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle) |
| 73 | #define DRM_IOCTL_AMDGPU_SCHED DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched) | 73 | #define DRM_IOCTL_AMDGPU_SCHED DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched) |
| 74 | 74 | ||
| 75 | /** | ||
| 76 | * DOC: memory domains | ||
| 77 | * | ||
| 78 | * %AMDGPU_GEM_DOMAIN_CPU System memory that is not GPU accessible. | ||
| 79 | * Memory in this pool could be swapped out to disk if there is pressure. | ||
| 80 | * | ||
| 81 | * %AMDGPU_GEM_DOMAIN_GTT GPU accessible system memory, mapped into the | ||
| 82 | * GPU's virtual address space via gart. Gart memory linearizes non-contiguous | ||
| 83 | * pages of system memory, allows GPU access system memory in a linezrized | ||
| 84 | * fashion. | ||
| 85 | * | ||
| 86 | * %AMDGPU_GEM_DOMAIN_VRAM Local video memory. For APUs, it is memory | ||
| 87 | * carved out by the BIOS. | ||
| 88 | * | ||
| 89 | * %AMDGPU_GEM_DOMAIN_GDS Global on-chip data storage used to share data | ||
| 90 | * across shader threads. | ||
| 91 | * | ||
| 92 | * %AMDGPU_GEM_DOMAIN_GWS Global wave sync, used to synchronize the | ||
| 93 | * execution of all the waves on a device. | ||
| 94 | * | ||
| 95 | * %AMDGPU_GEM_DOMAIN_OA Ordered append, used by 3D or Compute engines | ||
| 96 | * for appending data. | ||
| 97 | */ | ||
| 75 | #define AMDGPU_GEM_DOMAIN_CPU 0x1 | 98 | #define AMDGPU_GEM_DOMAIN_CPU 0x1 |
| 76 | #define AMDGPU_GEM_DOMAIN_GTT 0x2 | 99 | #define AMDGPU_GEM_DOMAIN_GTT 0x2 |
| 77 | #define AMDGPU_GEM_DOMAIN_VRAM 0x4 | 100 | #define AMDGPU_GEM_DOMAIN_VRAM 0x4 |
| @@ -483,7 +506,8 @@ struct drm_amdgpu_gem_va { · 405 unmodified lines | |||
| 483 | #define AMDGPU_HW_IP_UVD_ENC 5 | 506 | #define AMDGPU_HW_IP_UVD_ENC 5 |
| 484 | #define AMDGPU_HW_IP_VCN_DEC 6 | 507 | #define AMDGPU_HW_IP_VCN_DEC 6 |
| 485 | #define AMDGPU_HW_IP_VCN_ENC 7 | 508 | #define AMDGPU_HW_IP_VCN_ENC 7 |
| 486 | #define AMDGPU_HW_IP_NUM 8 | 509 | #define AMDGPU_HW_IP_VCN_JPEG 8 |
| 510 | #define AMDGPU_HW_IP_NUM 9 | ||
| 487 | 511 | ||
| 488 | #define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1 | 512 | #define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1 |
| 489 | 513 | ||