Pull drm updates from Dave Airlie: "Summary below. i915 starts to add support for DG2 GPUs, enables DG1 and ADL-S support by default, lots of work to enable DisplayPort 2.0 across drivers. Lots of documentation updates and fixes across the board. core: - improve dma_fence, lease and resv documentation - shmem-helpers: allocate WC pages on x86, use vmf_insert_pin - sched fixes/improvements - allow empty drm leases - add dma resv iterator - add more DP 2.0 headers - DP MST helper improvements for DP2.0 dma-buf: - avoid warnings, remove fence trace macros bridge: - new helper to get rid of panels - probe improvements for it66121 - enable DSI EOTP for anx7625 fbdev: - efifb: release runtime PM on destroy ttm: - kerneldoc switch - helper to clear all DMA mappings - pool shrinker optimizaton - remove ttm_tt_destroy_common - update ttm_move_memcpy for async use panel: - add new panel-edp driver amdgpu: - Initial DP 2.0 support - Initial USB4 DP tunnelling support - Aldebaran MCE support - Modifier support for DCC image stores for GFX 10.3 - Display rework for better FP code handling - Yellow Carp/Cyan Skillfish updates - Cyan Skillfish display support - convert vega/navi to IP discovery asic enumeration - validate IP discovery table - RAS improvements - Lots of fixes i915: - DG1 PCI IDs + LMEM discovery/placement - DG1 GuC submission by default - ADL-S PCI IDs updated + enabled by default - ADL-P (XE_LPD) fixed and updates - DG2 display fixes - PXP protected object support for Gen12 integrated - expose multi-LRC submission interface for GuC - export logical engine instance to user - Disable engine bonding on Gen12+ - PSR cleanup - PSR2 selective fetch by default - DP 2.0 prep work - VESA vendor block + MSO use of it - FBC refactor - try again to fix fast-narrow vs slow-wide eDP training - use THP when IOMMU enabled - LMEM backup/restore for suspend/resume - locking simplification - GuC major reworking - async flip VT-D workaround changes - DP link training improvements - misc display refactorings bochs: - new PCI ID rcar-du: - Non-contiguious buffer import support for rcar-du - r8a779a0 support prep omapdrm: - COMPILE_TEST fixes sti: - COMPILE_TEST fixes msm: - fence ordering improvements - eDP support in DP sub-driver - dpu irq handling cleanup - CRC support for making igt happy - NO_CONNECTOR bridge support - dsi: 14nm phy support for msm8953 - mdp5: msm8x53, sdm450, sdm632 support stm: - layer alpha + zpo support v3d: - fix Vulkan CTS failure - support multiple sync objects gud: - add R8/RGB332/RGB888 pixel formats vc4: - convert to new bridge helpers vgem: - use shmem helpers virtio: - support mapping exported vram zte: - remove obsolete driver rockchip: - use bridge attach no connector for LVDS/RGB" * tag 'drm-next-2021-11-03' of git://anongit.freedesktop.org/drm/drm: (1259 commits) drm/amdgpu/gmc6: fix DMA mask from 44 to 40 bits drm/amd/display: MST support for DPIA drm/amdgpu: Fix even more out of bound writes from debugfs drm/amdgpu/discovery: add SDMA IP instance info for soc15 parts drm/amdgpu/discovery: add UVD/VCN IP instance info for soc15 parts drm/amdgpu/UAPI: rearrange header to better align related items drm/amd/display: Enable dpia in dmub only for DCN31 B0 drm/amd/display: Fix USB4 hot plug crash issue drm/amd/display: Fix deadlock when falling back to v2 from v3 drm/amd/display: Fallback to clocks which meet requested voltage on DCN31 drm/amd/display: move FPU associated DCN301 code to DML folder drm/amd/display: fix link training regression for 1 or 2 lane drm/amd/display: add two lane settings training options drm/amd/display: decouple hw_lane_settings from dpcd_lane_settings drm/amd/display: implement decide lane settings drm/amd/display: adopt DP2.0 LT SCR revision 8 drm/amd/display: FEC configuration for dpia links in MST mode drm/amd/display: FEC configuration for dpia links drm/amd/display: Add workaround flag for EDID read on certain docks drm/amd/display: Set phy_mux_sel bit in dmub scratch register ...
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| @@ -59,6 +59,11 @@ · 58 unmodified lines | ||
| 59 | 59 | * VIRTIO_GPU_CMD_RESOURCE_CREATE_BLOB |
| 60 | 60 | */ |
| 61 | 61 | #define VIRTIO_GPU_F_RESOURCE_BLOB 3 |
| 62 | +/* | |
| 63 | + * VIRTIO_GPU_CMD_CREATE_CONTEXT with | |
| 64 | + * context_init and multiple timelines | |
| 65 | + */ | |
| 66 | +#define VIRTIO_GPU_F_CONTEXT_INIT 4 | |
| 62 | 67 | |
| 63 | 68 | enum virtio_gpu_ctrl_type { |
| 64 | 69 | VIRTIO_GPU_UNDEFINED = 0, |
| @@ -122,14 +127,20 @@ enum virtio_gpu_shm_id { · 57 unmodified lines | ||
| 122 | 127 | VIRTIO_GPU_SHM_ID_HOST_VISIBLE = 1 |
| 123 | 128 | }; |
| 124 | 129 | |
| 125 | −#define VIRTIO_GPU_FLAG_FENCE (1 << 0) | |
| 130 | +#define VIRTIO_GPU_FLAG_FENCE (1 << 0) | |
| 131 | +/* | |
| 132 | + * If the following flag is set, then ring_idx contains the index | |
| 133 | + * of the command ring that needs to used when creating the fence | |
| 134 | + */ | |
| 135 | +#define VIRTIO_GPU_FLAG_INFO_RING_IDX (1 << 1) | |
| 126 | 136 | |
| 127 | 137 | struct virtio_gpu_ctrl_hdr { |
| 128 | 138 | __le32 type; |
| 129 | 139 | __le32 flags; |
| 130 | 140 | __le64 fence_id; |
| 131 | 141 | __le32 ctx_id; |
| 132 | − __le32 padding; | |
| 142 | + __u8 ring_idx; | |
| 143 | + __u8 padding[3]; | |
| 133 | 144 | }; |
| 134 | 145 | |
| 135 | 146 | /* data passed in the cursor vq */ |
| @@ -269,10 +280,11 @@ struct virtio_gpu_resource_create_3d { · 133 unmodified lines | ||
| 269 | 280 | }; |
| 270 | 281 | |
| 271 | 282 | /* VIRTIO_GPU_CMD_CTX_CREATE */ |
| 283 | +#define VIRTIO_GPU_CONTEXT_INIT_CAPSET_ID_MASK 0x000000ff | |
| 272 | 284 | struct virtio_gpu_ctx_create { |
| 273 | 285 | struct virtio_gpu_ctrl_hdr hdr; |
| 274 | 286 | __le32 nlen; |
| 275 | − __le32 padding; | |
| 287 | + __le32 context_init; | |
| 276 | 288 | char debug_name[64]; |
| 277 | 289 | }; |
| 278 | 290 | |