drm/tegra: Changes for v5.15-rc1 The bulk of these changes is a more modern ABI that can be efficiently used on newer SoCs as well as older ones. The userspace parts for this are available here: - libdrm support: https://gitlab.freedesktop.org/tagr/drm/-/commits/drm-tegra-uabi-v8 - VAAPI driver: https://github.com/cyndis/vaapi-tegra-driver In addition, existing userspace from the grate reverse-engineering project has been updated to use this new ABI: - X11 driver: https://github.com/grate-driver/xf86-video-opentegra - 3D driver: https://github.com/grate-driver/grate Other than that, there's also support for display memory bandwidth management for various generations and a bit of cleanup. Signed-off-by: Dave Airlie <airlied@redhat.com>
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| 1 | −/* | |
| 2 | − * Copyright (c) 2012-2013, NVIDIA CORPORATION. All rights reserved. | |
| 3 | − * | |
| 4 | − * Permission is hereby granted, free of charge, to any person obtaining a | |
| 5 | − * copy of this software and associated documentation files (the "Software"), | |
| 6 | − * to deal in the Software without restriction, including without limitation | |
| 7 | − * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
| 8 | − * and/or sell copies of the Software, and to permit persons to whom the | |
| 9 | − * Software is furnished to do so, subject to the following conditions: | |
| 10 | − * | |
| 11 | − * The above copyright notice and this permission notice shall be included in | |
| 12 | − * all copies or substantial portions of the Software. | |
| 13 | − * | |
| 14 | − * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
| 15 | − * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 16 | − * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 17 | − * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
| 18 | − * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
| 19 | − * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 20 | − * OTHER DEALINGS IN THE SOFTWARE. | |
| 21 | − */ | |
| 1 | +/* SPDX-License-Identifier: MIT */ | |
| 2 | +/* Copyright (c) 2012-2020 NVIDIA Corporation */ | |
| 22 | 3 | |
| 23 | 4 | #ifndef _UAPI_TEGRA_DRM_H_ |
| 24 | 5 | #define _UAPI_TEGRA_DRM_H_ |
| @@ -29,6 +10,8 @@ · 4 unmodified lines | ||
| 29 | 10 | extern "C" { |
| 30 | 11 | #endif |
| 31 | 12 | |
| 13 | +/* Tegra DRM legacy UAPI. Only enabled with STAGING */ | |
| 14 | + | |
| 32 | 15 | #define DRM_TEGRA_GEM_CREATE_TILED (1 << 0) |
| 33 | 16 | #define DRM_TEGRA_GEM_CREATE_BOTTOM_UP (1 << 1) |
| 34 | 17 | |
| @@ -649,8 +632,8 @@ struct drm_tegra_gem_get_flags { · 614 unmodified lines | ||
| 649 | 632 | #define DRM_TEGRA_SYNCPT_READ 0x02 |
| 650 | 633 | #define DRM_TEGRA_SYNCPT_INCR 0x03 |
| 651 | 634 | #define DRM_TEGRA_SYNCPT_WAIT 0x04 |
| 652 | −#define DRM_TEGRA_OPEN_CHANNEL 0x05 | |
| 653 | −#define DRM_TEGRA_CLOSE_CHANNEL 0x06 | |
| 635 | +#define DRM_TEGRA_OPEN_CHANNEL 0x05 | |
| 636 | +#define DRM_TEGRA_CLOSE_CHANNEL 0x06 | |
| 654 | 637 | #define DRM_TEGRA_GET_SYNCPT 0x07 |
| 655 | 638 | #define DRM_TEGRA_SUBMIT 0x08 |
| 656 | 639 | #define DRM_TEGRA_GET_SYNCPT_BASE 0x09 |
| @@ -674,6 +657,402 @@ struct drm_tegra_gem_get_flags { · 17 unmodified lines | ||
| 674 | 657 | #define DRM_IOCTL_TEGRA_GEM_SET_FLAGS DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_SET_FLAGS, struct drm_tegra_gem_set_flags) |
| 675 | 658 | #define DRM_IOCTL_TEGRA_GEM_GET_FLAGS DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_GET_FLAGS, struct drm_tegra_gem_get_flags) |
| 676 | 659 | |
| 660 | +/* New Tegra DRM UAPI */ | |
| 661 | + | |
| 662 | +/* | |
| 663 | + * Reported by the driver in the `capabilities` field. | |
| 664 | + * | |
| 665 | + * DRM_TEGRA_CHANNEL_CAP_CACHE_COHERENT: If set, the engine is cache coherent | |
| 666 | + * with regard to the system memory. | |
| 667 | + */ | |
| 668 | +#define DRM_TEGRA_CHANNEL_CAP_CACHE_COHERENT (1 << 0) | |
| 669 | + | |
| 670 | +struct drm_tegra_channel_open { | |
| 671 | + /** | |
| 672 | + * @host1x_class: [in] | |
| 673 | + * | |
| 674 | + * Host1x class of the engine that will be programmed using this | |
| 675 | + * channel. | |
| 676 | + */ | |
| 677 | + __u32 host1x_class; | |
| 678 | + | |
| 679 | + /** | |
| 680 | + * @flags: [in] | |
| 681 | + * | |
| 682 | + * Flags. | |
| 683 | + */ | |
| 684 | + __u32 flags; | |
| 685 | + | |
| 686 | + /** | |
| 687 | + * @context: [out] | |
| 688 | + * | |
| 689 | + * Opaque identifier corresponding to the opened channel. | |
| 690 | + */ | |
| 691 | + __u32 context; | |
| 692 | + | |
| 693 | + /** | |
| 694 | + * @version: [out] | |
| 695 | + * | |
| 696 | + * Version of the engine hardware. This can be used by userspace | |
| 697 | + * to determine how the engine needs to be programmed. | |
| 698 | + */ | |
| 699 | + __u32 version; | |
| 700 | + | |
| 701 | + /** | |
| 702 | + * @capabilities: [out] | |
| 703 | + * | |
| 704 | + * Flags describing the hardware capabilities. | |
| 705 | + */ | |
| 706 | + __u32 capabilities; | |
| 707 | + __u32 padding; | |
| 708 | +}; | |
| 709 | + | |
| 710 | +struct drm_tegra_channel_close { | |
| 711 | + /** | |
| 712 | + * @context: [in] | |
| 713 | + * | |
| 714 | + * Identifier of the channel to close. | |
| 715 | + */ | |
| 716 | + __u32 context; | |
| 717 | + __u32 padding; | |
| 718 | +}; | |
| 719 | + | |
| 720 | +/* | |
| 721 | + * Mapping flags that can be used to influence how the mapping is created. | |
| 722 | + * | |
| 723 | + * DRM_TEGRA_CHANNEL_MAP_READ: create mapping that allows HW read access | |
| 724 | + * DRM_TEGRA_CHANNEL_MAP_WRITE: create mapping that allows HW write access | |
| 725 | + */ | |
| 726 | +#define DRM_TEGRA_CHANNEL_MAP_READ (1 << 0) | |
| 727 | +#define DRM_TEGRA_CHANNEL_MAP_WRITE (1 << 1) | |
| 728 | +#define DRM_TEGRA_CHANNEL_MAP_READ_WRITE (DRM_TEGRA_CHANNEL_MAP_READ | \ | |
| 729 | + DRM_TEGRA_CHANNEL_MAP_WRITE) | |
| 730 | + | |
| 731 | +struct drm_tegra_channel_map { | |
| 732 | + /** | |
| 733 | + * @context: [in] | |
| 734 | + * | |
| 735 | + * Identifier of the channel to which make memory available for. | |
| 736 | + */ | |
| 737 | + __u32 context; | |
| 738 | + | |
| 739 | + /** | |
| 740 | + * @handle: [in] | |
| 741 | + * | |
| 742 | + * GEM handle of the memory to map. | |
| 743 | + */ | |
| 744 | + __u32 handle; | |
| 745 | + | |
| 746 | + /** | |
| 747 | + * @flags: [in] | |
| 748 | + * | |
| 749 | + * Flags. | |
| 750 | + */ | |
| 751 | + __u32 flags; | |
| 752 | + | |
| 753 | + /** | |
| 754 | + * @mapping: [out] | |
| 755 | + * | |
| 756 | + * Identifier corresponding to the mapping, to be used for | |
| 757 | + * relocations or unmapping later. | |
| 758 | + */ | |
| 759 | + __u32 mapping; | |
| 760 | +}; | |
| 761 | + | |
| 762 | +struct drm_tegra_channel_unmap { | |
| 763 | + /** | |
| 764 | + * @context: [in] | |
| 765 | + * | |
| 766 | + * Channel identifier of the channel to unmap memory from. | |
| 767 | + */ | |
| 768 | + __u32 context; | |
| 769 | + | |
| 770 | + /** | |
| 771 | + * @mapping: [in] | |
| 772 | + * | |
| 773 | + * Mapping identifier of the memory mapping to unmap. | |
| 774 | + */ | |
| 775 | + __u32 mapping; | |
| 776 | +}; | |
| 777 | + | |
| 778 | +/* Submission */ | |
| 779 | + | |
| 780 | +/** | |
| 781 | + * Specify that bit 39 of the patched-in address should be set to switch | |
| 782 | + * swizzling between Tegra and non-Tegra sector layout on systems that store | |
| 783 | + * surfaces in system memory in non-Tegra sector layout. | |
| 784 | + */ | |
| 785 | +#define DRM_TEGRA_SUBMIT_RELOC_SECTOR_LAYOUT (1 << 0) | |
| 786 | + | |
| 787 | +struct drm_tegra_submit_buf { | |
| 788 | + /** | |
| 789 | + * @mapping: [in] | |
| 790 | + * | |
| 791 | + * Identifier of the mapping to use in the submission. | |
| 792 | + */ | |
| 793 | + __u32 mapping; | |
| 794 | + | |
| 795 | + /** | |
| 796 | + * @flags: [in] | |
| 797 | + * | |
| 798 | + * Flags. | |
| 799 | + */ | |
| 800 | + __u32 flags; | |
| 801 | + | |
| 802 | + /** | |
| 803 | + * Information for relocation patching. | |
| 804 | + */ | |
| 805 | + struct { | |
| 806 | + /** | |
| 807 | + * @target_offset: [in] | |
| 808 | + * | |
| 809 | + * Offset from the start of the mapping of the data whose | |
| 810 | + * address is to be patched into the gather. | |
| 811 | + */ | |
| 812 | + __u64 target_offset; | |
| 813 | + | |
| 814 | + /** | |
| 815 | + * @gather_offset_words: [in] | |
| 816 | + * | |
| 817 | + * Offset in words from the start of the gather data to | |
| 818 | + * where the address should be patched into. | |
| 819 | + */ | |
| 820 | + __u32 gather_offset_words; | |
| 821 | + | |
| 822 | + /** | |
| 823 | + * @shift: [in] | |
| 824 | + * | |
| 825 | + * Number of bits the address should be shifted right before | |
| 826 | + * patching in. | |
| 827 | + */ | |
| 828 | + __u32 shift; | |
| 829 | + } reloc; | |
| 830 | +}; | |
| 831 | + | |
| 832 | +/** | |
| 833 | + * Execute `words` words of Host1x opcodes specified in the `gather_data_ptr` | |
| 834 | + * buffer. Each GATHER_UPTR command uses successive words from the buffer. | |
| 835 | + */ | |
| 836 | +#define DRM_TEGRA_SUBMIT_CMD_GATHER_UPTR 0 | |
| 837 | +/** | |
| 838 | + * Wait for a syncpoint to reach a value before continuing with further | |
| 839 | + * commands. | |
| 840 | + */ | |
| 841 | +#define DRM_TEGRA_SUBMIT_CMD_WAIT_SYNCPT 1 | |
| 842 | +/** | |
| 843 | + * Wait for a syncpoint to reach a value before continuing with further | |
| 844 | + * commands. The threshold is calculated relative to the start of the job. | |
| 845 | + */ | |
| 846 | +#define DRM_TEGRA_SUBMIT_CMD_WAIT_SYNCPT_RELATIVE 2 | |
| 847 | + | |
| 848 | +struct drm_tegra_submit_cmd_gather_uptr { | |
| 849 | + __u32 words; | |
| 850 | + __u32 reserved[3]; | |
| 851 | +}; | |
| 852 | + | |
| 853 | +struct drm_tegra_submit_cmd_wait_syncpt { | |
| 854 | + __u32 id; | |
| 855 | + __u32 value; | |
| 856 | + __u32 reserved[2]; | |
| 857 | +}; | |
| 858 | + | |
| 859 | +struct drm_tegra_submit_cmd { | |
| 860 | + /** | |
| 861 | + * @type: [in] | |
| 862 | + * | |
| 863 | + * Command type to execute. One of the DRM_TEGRA_SUBMIT_CMD* | |
| 864 | + * defines. | |
| 865 | + */ | |
| 866 | + __u32 type; | |
| 867 | + | |
| 868 | + /** | |
| 869 | + * @flags: [in] | |
| 870 | + * | |
| 871 | + * Flags. | |
| 872 | + */ | |
| 873 | + __u32 flags; | |
| 874 | + | |
| 875 | + union { | |
| 876 | + struct drm_tegra_submit_cmd_gather_uptr gather_uptr; | |
| 877 | + struct drm_tegra_submit_cmd_wait_syncpt wait_syncpt; | |
| 878 | + __u32 reserved[4]; | |
| 879 | + }; | |
| 880 | +}; | |
| 881 | + | |
| 882 | +struct drm_tegra_submit_syncpt { | |
| 883 | + /** | |
| 884 | + * @id: [in] | |
| 885 | + * | |
| 886 | + * ID of the syncpoint that the job will increment. | |
| 887 | + */ | |
| 888 | + __u32 id; | |
| 889 | + | |
| 890 | + /** | |
| 891 | + * @flags: [in] | |
| 892 | + * | |
| 893 | + * Flags. | |
| 894 | + */ | |
| 895 | + __u32 flags; | |
| 896 | + | |
| 897 | + /** | |
| 898 | + * @increments: [in] | |
| 899 | + * | |
| 900 | + * Number of times the job will increment this syncpoint. | |
| 901 | + */ | |
| 902 | + __u32 increments; | |
| 903 | + | |
| 904 | + /** | |
| 905 | + * @value: [out] | |
| 906 | + * | |
| 907 | + * Value the syncpoint will have once the job has completed all | |
| 908 | + * its specified syncpoint increments. | |
| 909 | + * | |
| 910 | + * Note that the kernel may increment the syncpoint before or after | |
| 911 | + * the job. These increments are not reflected in this field. | |
| 912 | + * | |
| 913 | + * If the job hangs or times out, not all of the increments may | |
| 914 | + * get executed. | |
| 915 | + */ | |
| 916 | + __u32 value; | |
| 917 | +}; | |
| 918 | + | |
| 919 | +struct drm_tegra_channel_submit { | |
| 920 | + /** | |
| 921 | + * @context: [in] | |
| 922 | + * | |
| 923 | + * Identifier of the channel to submit this job to. | |
| 924 | + */ | |
| 925 | + __u32 context; | |
| 926 | + | |
| 927 | + /** | |
| 928 | + * @num_bufs: [in] | |
| 929 | + * | |
| 930 | + * Number of elements in the `bufs_ptr` array. | |
| 931 | + */ | |
| 932 | + __u32 num_bufs; | |
| 933 | + | |
| 934 | + /** | |
| 935 | + * @num_cmds: [in] | |
| 936 | + * | |
| 937 | + * Number of elements in the `cmds_ptr` array. | |
| 938 | + */ | |
| 939 | + __u32 num_cmds; | |
| 940 | + | |
| 941 | + /** | |
| 942 | + * @gather_data_words: [in] | |
| 943 | + * | |
| 944 | + * Number of 32-bit words in the `gather_data_ptr` array. | |
| 945 | + */ | |
| 946 | + __u32 gather_data_words; | |
| 947 | + | |
| 948 | + /** | |
| 949 | + * @bufs_ptr: [in] | |
| 950 | + * | |
| 951 | + * Pointer to an array of drm_tegra_submit_buf structures. | |
| 952 | + */ | |
| 953 | + __u64 bufs_ptr; | |
| 954 | + | |
| 955 | + /** | |
| 956 | + * @cmds_ptr: [in] | |
| 957 | + * | |
| 958 | + * Pointer to an array of drm_tegra_submit_cmd structures. | |
| 959 | + */ | |
| 960 | + __u64 cmds_ptr; | |
| 961 | + | |
| 962 | + /** | |
| 963 | + * @gather_data_ptr: [in] | |
| 964 | + * | |
| 965 | + * Pointer to an array of Host1x opcodes to be used by GATHER_UPTR | |
| 966 | + * commands. | |
| 967 | + */ | |
| 968 | + __u64 gather_data_ptr; | |
| 969 | + | |
| 970 | + /** | |
| 971 | + * @syncobj_in: [in] | |
| 972 | + * | |
| 973 | + * Handle for DRM syncobj that will be waited before submission. | |
| 974 | + * Ignored if zero. | |
| 975 | + */ | |
| 976 | + __u32 syncobj_in; | |
| 977 | + | |
| 978 | + /** | |
| 979 | + * @syncobj_out: [in] | |
| 980 | + * | |
| 981 | + * Handle for DRM syncobj that will have its fence replaced with | |
| 982 | + * the job's completion fence. Ignored if zero. | |
| 983 | + */ | |
| 984 | + __u32 syncobj_out; | |
| 985 | + | |
| 986 | + /** | |
| 987 | + * @syncpt_incr: [in,out] | |
| 988 | + * | |
| 989 | + * Information about the syncpoint the job will increment. | |
| 990 | + */ | |
| 991 | + struct drm_tegra_submit_syncpt syncpt; | |
| 992 | +}; | |
| 993 | + | |
| 994 | +struct drm_tegra_syncpoint_allocate { | |
| 995 | + /** | |
| 996 | + * @id: [out] | |
| 997 | + * | |
| 998 | + * ID of allocated syncpoint. | |
| 999 | + */ | |
| 1000 | + __u32 id; | |
| 1001 | + __u32 padding; | |
| 1002 | +}; | |
| 1003 | + | |
| 1004 | +struct drm_tegra_syncpoint_free { | |
| 1005 | + /** | |
| 1006 | + * @id: [in] | |
| 1007 | + * | |
| 1008 | + * ID of syncpoint to free. | |
| 1009 | + */ | |
| 1010 | + __u32 id; | |
| 1011 | + __u32 padding; | |
| 1012 | +}; | |
| 1013 | + | |
| 1014 | +struct drm_tegra_syncpoint_wait { | |
| 1015 | + /** | |
| 1016 | + * @timeout: [in] | |
| 1017 | + * | |
| 1018 | + * Absolute timestamp at which the wait will time out. | |
| 1019 | + */ | |
| 1020 | + __s64 timeout_ns; | |
| 1021 | + | |
| 1022 | + /** | |
| 1023 | + * @id: [in] | |
| 1024 | + * | |
| 1025 | + * ID of syncpoint to wait on. | |
| 1026 | + */ | |
| 1027 | + __u32 id; | |
| 1028 | + | |
| 1029 | + /** | |
| 1030 | + * @threshold: [in] | |
| 1031 | + * | |
| 1032 | + * Threshold to wait for. | |
| 1033 | + */ | |
| 1034 | + __u32 threshold; | |
| 1035 | + | |
| 1036 | + /** | |
| 1037 | + * @value: [out] | |
| 1038 | + * | |
| 1039 | + * Value of the syncpoint upon wait completion. | |
| 1040 | + */ | |
| 1041 | + __u32 value; | |
| 1042 | + | |
| 1043 | + __u32 padding; | |
| 1044 | +}; | |
| 1045 | + | |
| 1046 | +#define DRM_IOCTL_TEGRA_CHANNEL_OPEN DRM_IOWR(DRM_COMMAND_BASE + 0x10, struct drm_tegra_channel_open) | |
| 1047 | +#define DRM_IOCTL_TEGRA_CHANNEL_CLOSE DRM_IOWR(DRM_COMMAND_BASE + 0x11, struct drm_tegra_channel_close) | |
| 1048 | +#define DRM_IOCTL_TEGRA_CHANNEL_MAP DRM_IOWR(DRM_COMMAND_BASE + 0x12, struct drm_tegra_channel_map) | |
| 1049 | +#define DRM_IOCTL_TEGRA_CHANNEL_UNMAP DRM_IOWR(DRM_COMMAND_BASE + 0x13, struct drm_tegra_channel_unmap) | |
| 1050 | +#define DRM_IOCTL_TEGRA_CHANNEL_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + 0x14, struct drm_tegra_channel_submit) | |
| 1051 | + | |
| 1052 | +#define DRM_IOCTL_TEGRA_SYNCPOINT_ALLOCATE DRM_IOWR(DRM_COMMAND_BASE + 0x20, struct drm_tegra_syncpoint_allocate) | |
| 1053 | +#define DRM_IOCTL_TEGRA_SYNCPOINT_FREE DRM_IOWR(DRM_COMMAND_BASE + 0x21, struct drm_tegra_syncpoint_free) | |
| 1054 | +#define DRM_IOCTL_TEGRA_SYNCPOINT_WAIT DRM_IOWR(DRM_COMMAND_BASE + 0x22, struct drm_tegra_syncpoint_wait) | |
| 1055 | + | |
| 677 | 1056 | #if defined(__cplusplus) |
| 678 | 1057 | } |
| 679 | 1058 | #endif |