amd-drm-next-5.14-2021-06-02: amdgpu: - GC/MM register access macro clean up for SR-IOV - Beige Goby updates - W=1 Fixes - Aldebaran fixes - Misc display fixes - ACPI ATCS/ATIF handling rework - SR-IOV fixes - RAS fixes - 16bpc fixed point format support - Initial smartshift support - RV/PCO power tuning fixes for suspend/resume - More buffer object subclassing work - Add new INFO query for additional vbios information - Add new placement for preemptable SG buffers amdkfd: - Misc fixes radeon: - W=1 Fixes - Misc cleanups UAPI: - Add new INFO query for additional vbios information Useful for debugging vbios related issues. Proposed umr patch: https://patchwork.freedesktop.org/patch/433297/ - 16bpc fixed point format support IGT test: https://lists.freedesktop.org/archives/igt-dev/2021-May/031507.html Proposed Vulkan patch: https://github.com/kleinerm/pal/commit/a25d4802074b13a8d5f7edc96ae45469ecbac3c4 - Add a new GEM flag which is only used internally in the kernel driver. Userspace is not allowed to set it. drm: - 16bpc fixed point format fourcc
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| @@ -136,6 +136,10 @@ extern "C" { · 135 unmodified lines | ||
| 136 | 136 | * accessing it with various hw blocks |
| 137 | 137 | */ |
| 138 | 138 | #define AMDGPU_GEM_CREATE_ENCRYPTED (1 << 10) |
| 139 | +/* Flag that BO will be used only in preemptible context, which does | |
| 140 | + * not require GTT memory accounting | |
| 141 | + */ | |
| 142 | +#define AMDGPU_GEM_CREATE_PREEMPTIBLE (1 << 11) | |
| 139 | 143 | |
| 140 | 144 | struct drm_amdgpu_gem_create_in { |
| 141 | 145 | /** the requested memory size */ |
| @@ -753,6 +757,8 @@ struct drm_amdgpu_cs_chunk_data { · 611 unmodified lines | ||
| 753 | 757 | #define AMDGPU_INFO_VBIOS_SIZE 0x1 |
| 754 | 758 | /* Subquery id: Query vbios image */ |
| 755 | 759 | #define AMDGPU_INFO_VBIOS_IMAGE 0x2 |
| 760 | + /* Subquery id: Query vbios info */ | |
| 761 | + #define AMDGPU_INFO_VBIOS_INFO 0x3 | |
| 756 | 762 | /* Query UVD handles */ |
| 757 | 763 | #define AMDGPU_INFO_NUM_HANDLES 0x1C |
| 758 | 764 | /* Query sensor related information */ |
| @@ -946,6 +952,15 @@ struct drm_amdgpu_info_firmware { · 187 unmodified lines | ||
| 946 | 952 | __u32 feature; |
| 947 | 953 | }; |
| 948 | 954 | |
| 955 | +struct drm_amdgpu_info_vbios { | |
| 956 | + __u8 name[64]; | |
| 957 | + __u8 vbios_pn[64]; | |
| 958 | + __u32 version; | |
| 959 | + __u32 pad; | |
| 960 | + __u8 vbios_ver_str[32]; | |
| 961 | + __u8 date[32]; | |
| 962 | +}; | |
| 963 | + | |
| 949 | 964 | #define AMDGPU_VRAM_TYPE_UNKNOWN 0 |
| 950 | 965 | #define AMDGPU_VRAM_TYPE_GDDR1 1 |
| 951 | 966 | #define AMDGPU_VRAM_TYPE_DDR2 2 |
| @@ -168,6 +168,13 @@ extern "C" { · 167 unmodified lines | ||
| 168 | 168 | #define DRM_FORMAT_RGBA1010102 fourcc_code('R', 'A', '3', '0') /* [31:0] R:G:B:A 10:10:10:2 little endian */ |
| 169 | 169 | #define DRM_FORMAT_BGRA1010102 fourcc_code('B', 'A', '3', '0') /* [31:0] B:G:R:A 10:10:10:2 little endian */ |
| 170 | 170 | |
| 171 | +/* 64 bpp RGB */ | |
| 172 | +#define DRM_FORMAT_XRGB16161616 fourcc_code('X', 'R', '4', '8') /* [63:0] x:R:G:B 16:16:16:16 little endian */ | |
| 173 | +#define DRM_FORMAT_XBGR16161616 fourcc_code('X', 'B', '4', '8') /* [63:0] x:B:G:R 16:16:16:16 little endian */ | |
| 174 | + | |
| 175 | +#define DRM_FORMAT_ARGB16161616 fourcc_code('A', 'R', '4', '8') /* [63:0] A:R:G:B 16:16:16:16 little endian */ | |
| 176 | +#define DRM_FORMAT_ABGR16161616 fourcc_code('A', 'B', '4', '8') /* [63:0] A:B:G:R 16:16:16:16 little endian */ | |
| 177 | + | |
| 171 | 178 | /* |
| 172 | 179 | * Floating point 64bpp RGB |
| 173 | 180 | * IEEE 754-2008 binary16 half-precision float |