History

net: hns3: fix mis-counting IRQ vector numbers issue

Currently, the num_msi_left means the vector numbers of NIC, but if the PF supported RoCE, it contains the vector numbers of NIC and RoCE(Not expected). This may cause interrupts lost in some case, because of the NIC module used the vector resources which belongs to RoCE. This patch adds a new variable num_nic_msi to store the vector numbers of NIC, and adjust the default TQP numbers and rss_size according to the value of num_nic_msi.

Yonglong Liu committed 7 years ago

Commit 580a05f1 parent 38b4fe36 files · +58 −6Browse files

Unified · Split

6 files
  1. drivers/net/ethernet/hisilicon/hns3/hnae3.h +2 −0
  2. drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c +20 −1
  3. drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h +1 −0
  4. drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c +9 −2
  5. drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c +25 −3
  6. drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h +1 −0
drivers/net/ethernet/hisilicon/hns3/hnae3.h+2−0
@@ -32,6 +32,8 @@ · 31 unmodified lines
32 32
33#define HNAE3_MOD_VERSION "1.0"33#define HNAE3_MOD_VERSION "1.0"
34 34
35#define HNAE3_MIN_VECTOR_NUM 2 /* first one for misc, another for IO */
36
35/* Device IDs */37/* Device IDs */
36#define HNAE3_DEV_ID_GE 0xA22038#define HNAE3_DEV_ID_GE 0xA220
37#define HNAE3_DEV_ID_25GE 0xA22139#define HNAE3_DEV_ID_25GE 0xA221
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c+20−1
@@ -906,6 +906,9 @@ static int hclge_query_pf_resource(struct hclge_dev *hdev) · 905 unmodified lines
906 hnae3_get_field(__le16_to_cpu(req->pf_intr_vector_number),906 hnae3_get_field(__le16_to_cpu(req->pf_intr_vector_number),
907 HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S);907 HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S);
908 908
909 /* nic's msix numbers is always equals to the roce's. */
910 hdev->num_nic_msi = hdev->num_roce_msi;
911
909 /* PF should have NIC vectors and Roce vectors,912 /* PF should have NIC vectors and Roce vectors,
910 * NIC vectors are queued before Roce vectors.913 * NIC vectors are queued before Roce vectors.
911 */914 */
@@ -915,6 +918,15 @@ static int hclge_query_pf_resource(struct hclge_dev *hdev) · 3 unmodified lines
915 hdev->num_msi =918 hdev->num_msi =
916 hnae3_get_field(__le16_to_cpu(req->pf_intr_vector_number),919 hnae3_get_field(__le16_to_cpu(req->pf_intr_vector_number),
917 HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S);920 HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S);
921
922 hdev->num_nic_msi = hdev->num_msi;
923 }
924
925 if (hdev->num_nic_msi < HNAE3_MIN_VECTOR_NUM) {
926 dev_err(&hdev->pdev->dev,
927 "Just %u msi resources, not enough for pf(min:2).\n",
928 hdev->num_nic_msi);
929 return -EINVAL;
918 }930 }
919 931
920 return 0;932 return 0;
@@ -1507,6 +1519,10 @@ static int hclge_assign_tqp(struct hclge_vport *vport, u16 num_tqps) · 586 unmodified lines
1507 kinfo->rss_size = min_t(u16, hdev->rss_size_max,1519 kinfo->rss_size = min_t(u16, hdev->rss_size_max,
1508 vport->alloc_tqps / hdev->tm_info.num_tc);1520 vport->alloc_tqps / hdev->tm_info.num_tc);
1509 1521
1522 /* ensure one to one mapping between irq and queue at default */
1523 kinfo->rss_size = min_t(u16, kinfo->rss_size,
1524 (hdev->num_nic_msi - 1) / hdev->tm_info.num_tc);
1525
1510 return 0;1526 return 0;
1511}1527}
1512 1528
@@ -2285,7 +2301,8 @@ static int hclge_init_msi(struct hclge_dev *hdev) · 772 unmodified lines
2285 int vectors;2301 int vectors;
2286 int i;2302 int i;
2287 2303
2288 vectors = pci_alloc_irq_vectors(pdev, 1, hdev->num_msi,2304 vectors = pci_alloc_irq_vectors(pdev, HNAE3_MIN_VECTOR_NUM,
2305 hdev->num_msi,
2289 PCI_IRQ_MSI | PCI_IRQ_MSIX);2306 PCI_IRQ_MSI | PCI_IRQ_MSIX);
2290 if (vectors < 0) {2307 if (vectors < 0) {
2291 dev_err(&pdev->dev,2308 dev_err(&pdev->dev,
@@ -2300,6 +2317,7 @@ static int hclge_init_msi(struct hclge_dev *hdev) · 8 unmodified lines
2300 2317
2301 hdev->num_msi = vectors;2318 hdev->num_msi = vectors;
2302 hdev->num_msi_left = vectors;2319 hdev->num_msi_left = vectors;
2320
2303 hdev->base_msi_vector = pdev->irq;2321 hdev->base_msi_vector = pdev->irq;
2304 hdev->roce_base_vector = hdev->base_msi_vector +2322 hdev->roce_base_vector = hdev->base_msi_vector +
2305 hdev->roce_base_msix_offset;2323 hdev->roce_base_msix_offset;
@@ -3903,6 +3921,7 @@ static int hclge_get_vector(struct hnae3_handle *handle, u16 vector_num, · 1597 unmodified lines
3903 int alloc = 0;3921 int alloc = 0;
3904 int i, j;3922 int i, j;
3905 3923
3924 vector_num = min_t(u16, hdev->num_nic_msi - 1, vector_num);
3906 vector_num = min(hdev->num_msi_left, vector_num);3925 vector_num = min(hdev->num_msi_left, vector_num);
3907 3926
3908 for (j = 0; j < vector_num; j++) {3927 for (j = 0; j < vector_num; j++) {
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h+1−0
@@ -763,6 +763,7 @@ struct hclge_dev { · 762 unmodified lines
763 u32 base_msi_vector;763 u32 base_msi_vector;
764 u16 *vector_status;764 u16 *vector_status;
765 int *vector_irq;765 int *vector_irq;
766 u16 num_nic_msi; /* Num of nic vectors for this PF */
766 u16 num_roce_msi; /* Num of roce vectors for this PF */767 u16 num_roce_msi; /* Num of roce vectors for this PF */
767 int roce_base_vector;768 int roce_base_vector;
768 769
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c+9−2
@@ -537,9 +537,16 @@ static void hclge_tm_vport_tc_info_update(struct hclge_vport *vport) · 536 unmodified lines
537 kinfo->rss_size = kinfo->req_rss_size;537 kinfo->rss_size = kinfo->req_rss_size;
538 } else if (kinfo->rss_size > max_rss_size ||538 } else if (kinfo->rss_size > max_rss_size ||
539 (!kinfo->req_rss_size && kinfo->rss_size < max_rss_size)) {539 (!kinfo->req_rss_size && kinfo->rss_size < max_rss_size)) {
540 /* if user not set rss, the rss_size should compare with the
541 * valid msi numbers to ensure one to one map between tqp and
542 * irq as default.
543 */
544 if (!kinfo->req_rss_size)
545 max_rss_size = min_t(u16, max_rss_size,
546 (hdev->num_nic_msi - 1) /
547 kinfo->num_tc);
548
540 /* Set to the maximum specification value (max_rss_size). */549 /* Set to the maximum specification value (max_rss_size). */
541 dev_info(&hdev->pdev->dev, "rss changes from %d to %d\n",
542 kinfo->rss_size, max_rss_size);
543 kinfo->rss_size = max_rss_size;550 kinfo->rss_size = max_rss_size;
544 }551 }
545 552
drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c+25−3
@@ -411,6 +411,13 @@ static int hclgevf_knic_setup(struct hclgevf_dev *hdev) · 410 unmodified lines
411 kinfo->tqp[i] = &hdev->htqp[i].q;411 kinfo->tqp[i] = &hdev->htqp[i].q;
412 }412 }
413 413
414 /* after init the max rss_size and tqps, adjust the default tqp numbers
415 * and rss size with the actual vector numbers
416 */
417 kinfo->num_tqps = min_t(u16, hdev->num_nic_msix - 1, kinfo->num_tqps);
418 kinfo->rss_size = min_t(u16, kinfo->num_tqps / kinfo->num_tc,
419 kinfo->rss_size);
420
414 return 0;421 return 0;
415}422}
416 423
@@ -502,6 +509,7 @@ static int hclgevf_get_vector(struct hnae3_handle *handle, u16 vector_num, · 85 unmodified lines
502 int alloc = 0;509 int alloc = 0;
503 int i, j;510 int i, j;
504 511
512 vector_num = min_t(u16, hdev->num_nic_msix - 1, vector_num);
505 vector_num = min(hdev->num_msi_left, vector_num);513 vector_num = min(hdev->num_msi_left, vector_num);
506 514
507 for (j = 0; j < vector_num; j++) {515 for (j = 0; j < vector_num; j++) {
@@ -2246,13 +2254,14 @@ static int hclgevf_init_msi(struct hclgevf_dev *hdev) · 1738 unmodified lines
2246 int vectors;2254 int vectors;
2247 int i;2255 int i;
2248 2256
2249 if (hnae3_get_bit(hdev->ae_dev->flag, HNAE3_DEV_SUPPORT_ROCE_B))2257 if (hnae3_dev_roce_supported(hdev))
2250 vectors = pci_alloc_irq_vectors(pdev,2258 vectors = pci_alloc_irq_vectors(pdev,
2251 hdev->roce_base_msix_offset + 1,2259 hdev->roce_base_msix_offset + 1,
2252 hdev->num_msi,2260 hdev->num_msi,
2253 PCI_IRQ_MSIX);2261 PCI_IRQ_MSIX);
2254 else2262 else
2255 vectors = pci_alloc_irq_vectors(pdev, 1, hdev->num_msi,2263 vectors = pci_alloc_irq_vectors(pdev, HNAE3_MIN_VECTOR_NUM,
2264 hdev->num_msi,
2256 PCI_IRQ_MSI | PCI_IRQ_MSIX);2265 PCI_IRQ_MSI | PCI_IRQ_MSIX);
2257 2266
2258 if (vectors < 0) {2267 if (vectors < 0) {
@@ -2268,6 +2277,7 @@ static int hclgevf_init_msi(struct hclgevf_dev *hdev) · 9 unmodified lines
2268 2277
2269 hdev->num_msi = vectors;2278 hdev->num_msi = vectors;
2270 hdev->num_msi_left = vectors;2279 hdev->num_msi_left = vectors;
2280
2271 hdev->base_msi_vector = pdev->irq;2281 hdev->base_msi_vector = pdev->irq;
2272 hdev->roce_base_vector = pdev->irq + hdev->roce_base_msix_offset;2282 hdev->roce_base_vector = pdev->irq + hdev->roce_base_msix_offset;
2273 2283
@@ -2533,7 +2543,7 @@ static int hclgevf_query_vf_resource(struct hclgevf_dev *hdev) · 259 unmodified lines
2533 2543
2534 req = (struct hclgevf_query_res_cmd *)desc.data;2544 req = (struct hclgevf_query_res_cmd *)desc.data;
2535 2545
2536 if (hnae3_get_bit(hdev->ae_dev->flag, HNAE3_DEV_SUPPORT_ROCE_B)) {2546 if (hnae3_dev_roce_supported(hdev)) {
2537 hdev->roce_base_msix_offset =2547 hdev->roce_base_msix_offset =
2538 hnae3_get_field(__le16_to_cpu(req->msixcap_localid_ba_rocee),2548 hnae3_get_field(__le16_to_cpu(req->msixcap_localid_ba_rocee),
2539 HCLGEVF_MSIX_OFT_ROCEE_M,2549 HCLGEVF_MSIX_OFT_ROCEE_M,
@@ -2542,6 +2552,9 @@ static int hclgevf_query_vf_resource(struct hclgevf_dev *hdev) · 2 unmodified lines
2542 hnae3_get_field(__le16_to_cpu(req->vf_intr_vector_number),2552 hnae3_get_field(__le16_to_cpu(req->vf_intr_vector_number),
2543 HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S);2553 HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S);
2544 2554
2555 /* nic's msix numbers is always equals to the roce's. */
2556 hdev->num_nic_msix = hdev->num_roce_msix;
2557
2545 /* VF should have NIC vectors and Roce vectors, NIC vectors2558 /* VF should have NIC vectors and Roce vectors, NIC vectors
2546 * are queued before Roce vectors. The offset is fixed to 64.2559 * are queued before Roce vectors. The offset is fixed to 64.
2547 */2560 */
@@ -2551,6 +2564,15 @@ static int hclgevf_query_vf_resource(struct hclgevf_dev *hdev) · 3 unmodified lines
2551 hdev->num_msi =2564 hdev->num_msi =
2552 hnae3_get_field(__le16_to_cpu(req->vf_intr_vector_number),2565 hnae3_get_field(__le16_to_cpu(req->vf_intr_vector_number),
2553 HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S);2566 HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S);
2567
2568 hdev->num_nic_msix = hdev->num_msi;
2569 }
2570
2571 if (hdev->num_nic_msix < HNAE3_MIN_VECTOR_NUM) {
2572 dev_err(&hdev->pdev->dev,
2573 "Just %u msi resources, not enough for vf(min:2).\n",
2574 hdev->num_nic_msix);
2575 return -EINVAL;
2554 }2576 }
2555 2577
2556 return 0;2578 return 0;
drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h+1−0
@@ -270,6 +270,7 @@ struct hclgevf_dev { · 269 unmodified lines
270 u16 num_msi;270 u16 num_msi;
271 u16 num_msi_left;271 u16 num_msi_left;
272 u16 num_msi_used;272 u16 num_msi_used;
273 u16 num_nic_msix; /* Num of nic vectors for this VF */
273 u16 num_roce_msix; /* Num of roce vectors for this VF */274 u16 num_roce_msix; /* Num of roce vectors for this VF */
274 u16 roce_base_msix_offset;275 u16 roce_base_msix_offset;
275 int roce_base_vector;276 int roce_base_vector;