Merge tag 'drm-next-2025-10-01' of https://gitlab.freedesktop.org/drm/kernel

Pull drm updates from Dave Airlie: "cross-subsystem: - i2c-hid: Make elan touch controllers power on after panel is enabled - dt bindings for STM32MP25 SoC - pci vgaarb: use screen_info helpers - rust pin-init updates - add MEI driver for late binding firmware update/load uapi: - add ioctl for reassigning GEM handles - provide boot_display attribute on boot-up devices core: - document DRM_MODE_PAGE_FLIP_EVENT - add vendor specific recovery method to drm device wedged uevent gem: - Simplify gpuvm locking ttm: - add interface to populate buffers sched: - Fix race condition in trace code atomic: - Reallow no-op async page flips display: - dp: Fix command length video: - Improve pixel-format handling for struct screen_info rust: - drop Opaque<> from ioctl args - Alloc: - BorrowedPage type and AsPageIter traits - Implement Vmalloc::to_page() and VmallocPageIter - DMA/Scatterlist: - Add dma::DataDirection and type alias for dma_addr_t - Abstraction for struct scatterlist and sg_table - DRM: - simplify use of generics - add DriverFile type alias - drop Object::SIZE - Rust: - pin-init tree merge - Various methods for AsBytes and FromBytes traits gpuvm: - Support madvice in Xe driver gpusvm: - fix hmm_pfn_to_map_order usage in gpusvm bridge: - Improve and fix ref counting on bridge management - cdns-dsi: Various improvements to mode setting - Support Solomon SSD2825 plus DT bindings - Support Waveshare DSI2DPI plus DT bindings - Support Content Protection property - display-connector: Improve DP display detection - Add support for Radxa Ra620 plus DT bindings - adv7511: Provide SPD and HDMI infoframes - it6505: Replace crypto_shash with sha() - synopsys: Add support for DW DPTX Controller plus DT bindings - adv7511: Write full Audio infoframe - ite6263: Support vendor-specific infoframes - simple: Add support for Realtek RTD2171 DP-to-HDMI plus DT bindings panel: - panel-edp: Support mt8189 Chromebooks; Support BOE NV140WUM-N64; Support SHP LQ134Z1; Fixes - panel-simple: Support Olimex LCD-OLinuXino-5CTS plus DT bindings - Support Samsung AMS561RA01 - Support Hydis HV101HD1 plus DT bindings - ilitek-ili9881c: Refactor mode setting; Add support for Bestar BSD1218-A101KL68 LCD plus DT bindings - lvds: Add support for Ampire AMP19201200B5TZQW-T03 to DT bindings - edp: Add support for additonal mt8189 Chromebook panels - lvds: Add DT bindings for EDT ETML0700Z8DHA amdgpu: - add CRIU support for gem objects - RAS updates - VCN SRAM load fixes - EDID read fixes - eDP ALPM support - Documentation updates - Rework PTE flag generation - DCE6 fixes - VCN devcoredump cleanup - MMHUB client id fixes - VCN 5.0.1 RAS support - SMU 13.0.x updates - Expanded PCIe DPC support - Expanded VCN reset support - VPE per queue reset support - give kernel jobs unique id for tracing - pre-populate exported buffers - cyan skillfish updates - make vbios build number available in sysfs - userq updates - HDCP updates - support MMIO remap page as ttm pool - JPEG parser updates - DCE6 DC updates - use devm for i2c buses - GPUVM locking updates - Drop non-DC DCE11 code - improve fallback handling for pixel encoding amdkfd: - SVM/page migration fixes - debugfs fixes - add CRIO support for gem objects - SVM updates radeon: - use dev_warn_once in CS parsers xe: - add madvise interface - add DRM_IOCTL_XE_VM_QUERY_MEMORY_RANGE_ATTRS to query VMA count and memory attributes - drop L# bank mask reporting from media GT3 on Xe3+. - add SLPC power_profile sysfs interface - add configs attribs to add post/mid context-switch commands - handle firmware reported hardware errors notifying userspace with device wedged uevent - use same dir structure across sysfs/debugfs - cleanup and future proof vram region init - add G-states and PCI link states to debugfs - Add SRIOV support for CCS surfaces on Xe2+ - Enable SRIOV PF mode by default on supported platforms - move flush to common code - extended core workarounds for Xe2/3 - use DRM scheduler for delayed GT TLB invalidations - configs improvements and allow VF device enablement - prep work to expose mmio regions to userspace - VF migration support added - prepare GPU SVM for THP migration - start fixing XE_PAGE_SIZE vs PAGE_SIZE - add PSMI support for hw validation - resize VF bars to max possible size according to number of VFs - Ensure GT is in C0 during resume - pre-populate exported buffers - replace xe_hmm with gpusvm - add more SVM GT stats to debugfs - improve fake pci and WA kunnit handle for new platform testing - Test GuC to GuC comms to add debugging - use attribute groups to simplify sysfs registration - add Late Binding firmware code to interact with MEI i915: - apply multiple JSL/EHL/Gen7/Gen6 workarounds properly - protect against overflow in active_engine() - Use try_cmpxchg64() in __active_lookup() - include GuC registers in error state - get rid of dev->struct_mutex - iopoll: generalize read_poll_timout - lots more display refactoring - Reject HBR3 in any eDP Panel - Prune modes for YUV420 - Display Wa fix, additions, and updates - DP: Fix 2.7 Gbps link training on g4x - DP: Adjust the idle pattern handling - DP: Shuffle the link training code a bit - Don't set/read the DSI C clock divider on GLK - Enable_psr kernel parameter changes - Type-C enabled/disconnected dp-alt sink - Wildcat Lake enabling - DP HDR updates - DRAM detection - wait PSR idle on dsb commit - Remove FBC modulo 4 restriction for ADL-P+ - panic: refactor framebuffer allocation habanalabs: - debug/visibility improvements - vmalloc-backed coherent mmap support - HLDIO infrastructure nova-core: - various register!() macro improvements - minor vbios/firmware fixes/refactoring - advance firmware boot stages; process Booter and patch signatures - process GSP and GSP bootloader - Add r570.144 firmware bindings and update to it - Move GSP boot code to own module - Use new pin-init features to store driver's private data in a single allocation - Update ARef import from sync::aref nova-drm: - Update ARef import from sync::aref tyr: - initial driver skeleton for a rust driver for ARM Mali GPUs - capable of powering up, query metadata and provide it to userspace. msm: - GPU and Core: - in DT bindings describe clocks per GPU type - GMU bandwidth voting for x1-85 - a623/a663 speedbins - cleanup some remaining no-iommu leftovers after VM_BIND conversion - fix GEM obj 32b size truncation - add missing VM_BIND param validation - IFPC for x1-85 and a750 - register xml and gen_header.py sync from mesa - Display: - add missing bindings for display on SC8180X - added DisplayPort MST bindings - conversion from round_rate() to determine_rate() amdxdna: - add IOCTL_AMDXDNA_GET_ARRAY - support user space allocated buffers - streamline PM interfaces - Refactoring wrt. hardware contexts - improve error reporting nouveau: - use GSP firmware by default - improve error reporting - Pre-populate exported buffers ast: - Clean up detection of DRAM config exynos: - add DSIM bridge driver support for Exynos7870 - Document Exynos7870 DSIM compatible in dt-binding panthor: - Print task/pid on errors - Add support for Mali G710, G510, G310, Gx15, Gx20, Gx25 - Improve cache flushing - Fail VM bind if BO has offset renesas: - convert to RUNTIME_PM_OPS rcar-du: - Make number of lanes configurable - Use RUNTIME_PM_OPS - Add support for DSI commands rocket: - Add driver for Rockchip NPU plus DT bindings - Use kfree() and sizeof() correctly - Test DMA status rockchip: - dsi2: Add support for RK3576 plus DT bindings - Add support for RK3588 DPTX output tidss: - Use crtc_ fields for programming display mode - Remove other drivers from aperture pixpaper: - Add support for Mayqueen Pixpaper plus DT bindings v3d: - Support querying nubmer of GPU resets for KHR_robustness stm: - Clean up logging - ltdc: Add support support for STM32MP257F-EV1 plus DT bindings sitronix: - st7571-i2c: Add support for inverted displays and 2-bit grayscale tidss: - Convert to kernel's FIELD_ macros vesadrm: - Support 8-bit palette mode imagination: - Improve power management - Add support for TH1520 GPU - Support Risc-V architectures v3d: - Improve job management and locking vkms: - Support variants of ARGB8888, ARGB16161616, RGB565, RGB888 and P01x - Spport YUV with 16-bit components" * tag 'drm-next-2025-10-01' of https://gitlab.freedesktop.org/drm/kernel: (1455 commits) drm/amd: Add name to modes from amdgpu_connector_add_common_modes() drm/amd: Drop some common modes from amdgpu_connector_add_common_modes() drm/amdgpu: update MODULE_PARM_DESC for freesync_video drm/amd: Use dynamic array size declaration for amdgpu_connector_add_common_modes() drm/amd/display: Share dce100_validate_global with DCE6-8 drm/amd/display: Share dce100_validate_bandwidth with DCE6-8 drm/amdgpu: Fix fence signaling race condition in userqueue amd/amdkfd: enhance kfd process check in switch partition amd/amdkfd: resolve a race in amdgpu_amdkfd_device_fini_sw drm/amd/display: Reject modes with too high pixel clock on DCE6-10 drm/amd: Drop unnecessary check in amdgpu_connector_add_common_modes() drm/amd/display: Only enable common modes for eDP and LVDS drm/amdgpu: remove the redeclaration of variable i drm/amdgpu/userq: assign an error code for invalid userq va drm/amdgpu: revert "rework reserved VMID handling" v2 drm/amdgpu: remove leftover from enforcing isolation by VMID drm/amdgpu: Add fallback to pipe reset if KCQ ring reset fails accel/habanalabs: add Infineon version check accel/habanalabs/gaudi2: read preboot status after recovering from dirty state accel/habanalabs: add HL_GET_P_STATE passthrough type ...

Linus Torvalds committed 1 year ago

Commit 58809f62 parents 05a54fa b2ec5ca1254 files · +51985 −19096Browse files

Showing the changes to include/uapi (8 of 1254 files). Show all

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8 files

include/uapi/drm/amdgpu_drm.h +65 −7
include/uapi/drm/amdxdna_accel.h +136 −0
include/uapi/drm/drm.h +51 −12
include/uapi/drm/drm_mode.h +8 −0
include/uapi/drm/panthor_drm.h +3 −0
include/uapi/drm/rocket_accel.h +142 −0
include/uapi/drm/v3d_drm.h +2 −0
include/uapi/drm/xe_drm.h +281 −1

include/uapi/drm/amdgpu_drm.h+65−7

@@ -57,6 +57,7 @@ extern "C" { · 56 unmodified lines
57	57	#define DRM_AMDGPU_USERQ 0x16
58	58	#define DRM_AMDGPU_USERQ_SIGNAL 0x17
59	59	#define DRM_AMDGPU_USERQ_WAIT 0x18
	60	+#define DRM_AMDGPU_GEM_LIST_HANDLES 0x19
60	61
61	62	#define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create)
62	63	#define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap)
@@ -77,6 +78,7 @@ extern "C" { · 14 unmodified lines
77	78	#define DRM_IOCTL_AMDGPU_USERQ DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ, union drm_amdgpu_userq)
78	79	#define DRM_IOCTL_AMDGPU_USERQ_SIGNAL DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ_SIGNAL, struct drm_amdgpu_userq_signal)
79	80	#define DRM_IOCTL_AMDGPU_USERQ_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ_WAIT, struct drm_amdgpu_userq_wait)
	81	+#define DRM_IOCTL_AMDGPU_GEM_LIST_HANDLES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_LIST_HANDLES, struct drm_amdgpu_gem_list_handles)
80	82
81	83	/**
82	84	* DOC: memory domains
@@ -103,6 +105,8 @@ extern "C" { · 20 unmodified lines
103	105	*
104	106	* %AMDGPU_GEM_DOMAIN_DOORBELL Doorbell. It is an MMIO region for
105	107	* signalling user mode queues.
	108	+ *
	109	+ * %AMDGPU_GEM_DOMAIN_MMIO_REMAP MMIO remap page (special mapping for HDP flushing).
106	110	*/
107	111	#define AMDGPU_GEM_DOMAIN_CPU 0x1
108	112	#define AMDGPU_GEM_DOMAIN_GTT 0x2
@@ -111,13 +115,15 @@ extern "C" { · 2 unmodified lines
111	115	#define AMDGPU_GEM_DOMAIN_GWS 0x10
112	116	#define AMDGPU_GEM_DOMAIN_OA 0x20
113	117	#define AMDGPU_GEM_DOMAIN_DOORBELL 0x40
	118	+#define AMDGPU_GEM_DOMAIN_MMIO_REMAP 0x80
114	119	#define AMDGPU_GEM_DOMAIN_MASK (AMDGPU_GEM_DOMAIN_CPU \| \
115	120	AMDGPU_GEM_DOMAIN_GTT \| \
116	121	AMDGPU_GEM_DOMAIN_VRAM \| \
117	122	AMDGPU_GEM_DOMAIN_GDS \| \
118	123	AMDGPU_GEM_DOMAIN_GWS \| \
119		− AMDGPU_GEM_DOMAIN_OA \| \
120		− AMDGPU_GEM_DOMAIN_DOORBELL)
	124	+ AMDGPU_GEM_DOMAIN_OA \| \
	125	+ AMDGPU_GEM_DOMAIN_DOORBELL \| \
	126	+ AMDGPU_GEM_DOMAIN_MMIO_REMAP)
121	127
122	128	/* Flag that CPU access will be required for the case of VRAM domain */
123	129	#define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0)
@@ -800,6 +806,21 @@ union drm_amdgpu_wait_fences { · 676 unmodified lines
800	806
801	807	#define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0
802	808	#define AMDGPU_GEM_OP_SET_PLACEMENT 1
	809	+#define AMDGPU_GEM_OP_GET_MAPPING_INFO 2
	810	+
	811	+struct drm_amdgpu_gem_vm_entry {
	812	+ /* Start of mapping (in bytes) */
	813	+ __u64 addr;
	814	+
	815	+ /* Size of mapping (in bytes) */
	816	+ __u64 size;
	817	+
	818	+ /* Mapping offset */
	819	+ __u64 offset;
	820	+
	821	+ /* flags needed to recreate mapping */
	822	+ __u64 flags;
	823	+};
803	824
804	825	/* Sets or returns a value associated with a buffer. */
805	826	struct drm_amdgpu_gem_op {
@@ -807,8 +828,44 @@ struct drm_amdgpu_gem_op { · 1 unmodified line
807	828	__u32 handle;
808	829	/** AMDGPU_GEM_OP_* */
809	830	__u32 op;
810		− /** Input or return value */
	831	+ /** Input or return value. For MAPPING_INFO op: pointer to array of struct drm_amdgpu_gem_vm_entry */
811	832	__u64 value;
	833	+ /** For MAPPING_INFO op: number of mappings (in/out) */
	834	+ __u32 num_entries;
	835	+
	836	+ __u32 padding;
	837	+};
	838	+
	839	+#define AMDGPU_GEM_LIST_HANDLES_FLAG_IS_IMPORT (1 << 0)
	840	+
	841	+struct drm_amdgpu_gem_list_handles {
	842	+ /* User pointer to array of drm_amdgpu_gem_bo_info_entry */
	843	+ __u64 entries;
	844	+
	845	+ /* Size of entries buffer / Number of handles in process (if larger than size of buffer, must retry) */
	846	+ __u32 num_entries;
	847	+
	848	+ __u32 padding;
	849	+};
	850	+
	851	+struct drm_amdgpu_gem_list_handles_entry {
	852	+ /* gem handle of buffer object */
	853	+ __u32 gem_handle;
	854	+
	855	+ /* Currently just one flag: IS_IMPORT */
	856	+ __u32 flags;
	857	+
	858	+ /* Size of bo */
	859	+ __u64 size;
	860	+
	861	+ /* Preferred domains for GEM_CREATE */
	862	+ __u64 preferred_domains;
	863	+
	864	+ /* GEM_CREATE flags for re-creation of buffer */
	865	+ __u64 alloc_flags;
	866	+
	867	+ /* physical start_addr alignment in bytes for some HW requirements */
	868	+ __u64 alignment;
812	869	};
813	870
814	871	#define AMDGPU_VA_OP_MAP 1
@@ -1031,10 +1088,11 @@ struct drm_amdgpu_cs_chunk_cp_gfx_shadow { · 216 unmodified lines
1031	1088	* Query h/w info: Flag that this is integrated (a.h.a. fusion) GPU
1032	1089	*
1033	1090	*/
1034		−#define AMDGPU_IDS_FLAGS_FUSION 0x1
1035		−#define AMDGPU_IDS_FLAGS_PREEMPTION 0x2
1036		−#define AMDGPU_IDS_FLAGS_TMZ 0x4
1037		−#define AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD 0x8
	1091	+#define AMDGPU_IDS_FLAGS_FUSION 0x01
	1092	+#define AMDGPU_IDS_FLAGS_PREEMPTION 0x02
	1093	+#define AMDGPU_IDS_FLAGS_TMZ 0x04
	1094	+#define AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD 0x08
	1095	+#define AMDGPU_IDS_FLAGS_GANG_SUBMIT 0x10
1038	1096
1039	1097	/*
1040	1098	* Query h/w info: Flag identifying VF/PF/PT mode

include/uapi/drm/amdxdna_accel.h+136−0

@@ -34,6 +34,7 @@ enum amdxdna_drm_ioctl_id { · 33 unmodified lines
34	34	DRM_AMDXDNA_EXEC_CMD,
35	35	DRM_AMDXDNA_GET_INFO,
36	36	DRM_AMDXDNA_SET_STATE,
	37	+ DRM_AMDXDNA_GET_ARRAY = 10,
37	38	};
38	39
39	40	/**
@@ -153,6 +154,31 @@ enum amdxdna_bo_type { · 113 unmodified lines
153	154	AMDXDNA_BO_CMD,
154	155	};
155	156
	157	+/**
	158	+ * struct amdxdna_drm_va_entry
	159	+ * @vaddr: Virtual address.
	160	+ * @len: Size of entry.
	161	+ */
	162	+struct amdxdna_drm_va_entry {
	163	+ __u64 vaddr;
	164	+ __u64 len;
	165	+};
	166	+
	167	+/**
	168	+ * struct amdxdna_drm_va_tbl
	169	+ * @dmabuf_fd: The fd of dmabuf.
	170	+ * @num_entries: Number of va entries.
	171	+ * @va_entries: Array of va entries.
	172	+ *
	173	+ * The input can be either a dmabuf fd or a virtual address entry table.
	174	+ * When dmabuf_fd is used, num_entries must be zero.
	175	+ */
	176	+struct amdxdna_drm_va_tbl {
	177	+ __s32 dmabuf_fd;
	178	+ __u32 num_entries;
	179	+ struct amdxdna_drm_va_entry va_entries[];
	180	+};
	181	+
156	182	/**
157	183	* struct amdxdna_drm_create_bo - Create a buffer object.
158	184	* @flags: Buffer flags. MBZ.
@@ -430,6 +456,112 @@ struct amdxdna_drm_get_info { · 271 unmodified lines
430	456	__u64 buffer; /* in/out */
431	457	};
432	458
	459	+#define AMDXDNA_HWCTX_STATE_IDLE 0
	460	+#define AMDXDNA_HWCTX_STATE_ACTIVE 1
	461	+
	462	+/**
	463	+ * struct amdxdna_drm_hwctx_entry - The hardware context array entry
	464	+ */
	465	+struct amdxdna_drm_hwctx_entry {
	466	+ /** @context_id: Context ID. */
	467	+ __u32 context_id;
	468	+ /** @start_col: Start AIE array column assigned to context. */
	469	+ __u32 start_col;
	470	+ /** @num_col: Number of AIE array columns assigned to context. */
	471	+ __u32 num_col;
	472	+ /** @hwctx_id: The real hardware context id. */
	473	+ __u32 hwctx_id;
	474	+ /** @pid: ID of process which created this context. */
	475	+ __s64 pid;
	476	+ /** @command_submissions: Number of commands submitted. */
	477	+ __u64 command_submissions;
	478	+ /** @command_completions: Number of commands completed. */
	479	+ __u64 command_completions;
	480	+ /** @migrations: Number of times been migrated. */
	481	+ __u64 migrations;
	482	+ /** @preemptions: Number of times been preempted. */
	483	+ __u64 preemptions;
	484	+ /** @errors: Number of errors happened. */
	485	+ __u64 errors;
	486	+ /** @priority: Context priority. */
	487	+ __u64 priority;
	488	+ /** @heap_usage: Usage of device heap buffer. */
	489	+ __u64 heap_usage;
	490	+ /** @suspensions: Number of times been suspended. */
	491	+ __u64 suspensions;
	492	+ /**
	493	+ * @state: Context state.
	494	+ * %AMDXDNA_HWCTX_STATE_IDLE
	495	+ * %AMDXDNA_HWCTX_STATE_ACTIVE
	496	+ */
	497	+ __u32 state;
	498	+ /** @pasid: PASID been bound. */
	499	+ __u32 pasid;
	500	+ /** @gops: Giga operations per second. */
	501	+ __u32 gops;
	502	+ /** @fps: Frames per second. */
	503	+ __u32 fps;
	504	+ /** @dma_bandwidth: DMA bandwidth. */
	505	+ __u32 dma_bandwidth;
	506	+ /** @latency: Frame response latency. */
	507	+ __u32 latency;
	508	+ /** @frame_exec_time: Frame execution time. */
	509	+ __u32 frame_exec_time;
	510	+ /** @txn_op_idx: Index of last control code executed. */
	511	+ __u32 txn_op_idx;
	512	+ /** @ctx_pc: Program counter. */
	513	+ __u32 ctx_pc;
	514	+ /** @fatal_error_type: Fatal error type if context crashes. */
	515	+ __u32 fatal_error_type;
	516	+ /** @fatal_error_exception_type: Firmware exception type. */
	517	+ __u32 fatal_error_exception_type;
	518	+ /** @fatal_error_exception_pc: Firmware exception program counter. */
	519	+ __u32 fatal_error_exception_pc;
	520	+ /** @fatal_error_app_module: Exception module name. */
	521	+ __u32 fatal_error_app_module;
	522	+ /** @pad: Structure pad. */
	523	+ __u32 pad;
	524	+};
	525	+
	526	+#define DRM_AMDXDNA_HW_CONTEXT_ALL 0
	527	+
	528	+/**
	529	+ * struct amdxdna_drm_get_array - Get information array.
	530	+ */
	531	+struct amdxdna_drm_get_array {
	532	+ /**
	533	+ * @param:
	534	+ *
	535	+ * Supported params:
	536	+ *
	537	+ * %DRM_AMDXDNA_HW_CONTEXT_ALL:
	538	+ * Returns all created hardware contexts.
	539	+ */
	540	+ __u32 param;
	541	+ /**
	542	+ * @element_size:
	543	+ *
	544	+ * Specifies maximum element size and returns the actual element size.
	545	+ */
	546	+ __u32 element_size;
	547	+ /**
	548	+ * @num_element:
	549	+ *
	550	+ * Specifies maximum number of elements and returns the actual number
	551	+ * of elements.
	552	+ */
	553	+ __u32 num_element; /* in/out */
	554	+ /** @pad: MBZ */
	555	+ __u32 pad;
	556	+ /**
	557	+ * @buffer:
	558	+ *
	559	+ * Specifies the match conditions and returns the matched information
	560	+ * array.
	561	+ */
	562	+ __u64 buffer;
	563	+};
	564	+
433	565	enum amdxdna_drm_set_param {
434	566	DRM_AMDXDNA_SET_POWER_MODE,
435	567	DRM_AMDXDNA_WRITE_AIE_MEM,
@@ -494,6 +626,10 @@ struct amdxdna_drm_set_power_mode { · 58 unmodified lines
494	626	DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_SET_STATE, \
495	627	struct amdxdna_drm_set_state)
496	628
	629	+#define DRM_IOCTL_AMDXDNA_GET_ARRAY \
	630	+ DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_GET_ARRAY, \
	631	+ struct amdxdna_drm_get_array)
	632	+
497	633	#if defined(__cplusplus)
498	634	} /* extern c end */
499	635	#endif

include/uapi/drm/drm.h+51−12

@@ -597,34 +597,65 @@ struct drm_set_version { · 596 unmodified lines
597	597	int drm_dd_minor;
598	598	};
599	599
600		−/* DRM_IOCTL_GEM_CLOSE ioctl argument type */
	600	+/**
	601	+ * struct drm_gem_close - Argument for &DRM_IOCTL_GEM_CLOSE ioctl.
	602	+ * @handle: Handle of the object to be closed.
	603	+ * @pad: Padding.
	604	+ *
	605	+ * Releases the handle to an mm object.
	606	+ */
601	607	struct drm_gem_close {
602		− /** Handle of the object to be closed. */
603	608	__u32 handle;
604	609	__u32 pad;
605	610	};
606	611
607		−/* DRM_IOCTL_GEM_FLINK ioctl argument type */
	612	+/**
	613	+ * struct drm_gem_flink - Argument for &DRM_IOCTL_GEM_FLINK ioctl.
	614	+ * @handle: Handle for the object being named.
	615	+ * @name: Returned global name.
	616	+ *
	617	+ * Create a global name for an object, returning the name.
	618	+ *
	619	+ * Note that the name does not hold a reference; when the object
	620	+ * is freed, the name goes away.
	621	+ */
608	622	struct drm_gem_flink {
609		− /** Handle for the object being named */
610	623	__u32 handle;
611		−
612		− /** Returned global name */
613	624	__u32 name;
614	625	};
615	626
616		−/* DRM_IOCTL_GEM_OPEN ioctl argument type */
	627	+/**
	628	+ * struct drm_gem_open - Argument for &DRM_IOCTL_GEM_OPEN ioctl.
	629	+ * @name: Name of object being opened.
	630	+ * @handle: Returned handle for the object.
	631	+ * @size: Returned size of the object
	632	+ *
	633	+ * Open an object using the global name, returning a handle and the size.
	634	+ *
	635	+ * This handle (of course) holds a reference to the object, so the object
	636	+ * will not go away until the handle is deleted.
	637	+ */
617	638	struct drm_gem_open {
618		− /** Name of object being opened */
619	639	__u32 name;
620		−
621		− /** Returned handle for the object */
622	640	__u32 handle;
623		−
624		− /** Returned size of the object */
625	641	__u64 size;
626	642	};
627	643
	644	+/**
	645	+ * struct drm_gem_change_handle - Argument for &DRM_IOCTL_GEM_CHANGE_HANDLE ioctl.
	646	+ * @handle: The handle of a gem object.
	647	+ * @new_handle: An available gem handle.
	648	+ *
	649	+ * This ioctl changes the handle of a GEM object to the specified one.
	650	+ * The new handle must be unused. On success the old handle is closed
	651	+ * and all further IOCTL should refer to the new handle only.
	652	+ * Calls to DRM_IOCTL_PRIME_FD_TO_HANDLE will return the new handle.
	653	+ */
	654	+struct drm_gem_change_handle {
	655	+ __u32 handle;
	656	+ __u32 new_handle;
	657	+};
	658	+
628	659	/**
629	660	* DRM_CAP_DUMB_BUFFER
630	661	*
@@ -1309,6 +1340,14 @@ extern "C" { · 678 unmodified lines
1309	1340	*/
1310	1341	#define DRM_IOCTL_SET_CLIENT_NAME DRM_IOWR(0xD1, struct drm_set_client_name)
1311	1342
	1343	+/**
	1344	+ * DRM_IOCTL_GEM_CHANGE_HANDLE - Move an object to a different handle
	1345	+ *
	1346	+ * Some applications (notably CRIU) need objects to have specific gem handles.
	1347	+ * This ioctl changes the object at one gem handle to use a new gem handle.
	1348	+ */
	1349	+#define DRM_IOCTL_GEM_CHANGE_HANDLE DRM_IOWR(0xD2, struct drm_gem_change_handle)
	1350	+
1312	1351	/*
1313	1352	* Device specific ioctls should only be in their respective headers
1314	1353	* The device specific ioctl range is from 0x40 to 0x9f.

include/uapi/drm/drm_mode.h+8−0

@@ -962,6 +962,14 @@ struct hdr_output_metadata { · 961 unmodified lines
962	962	* Request that the kernel sends back a vblank event (see
963	963	* struct drm_event_vblank) with the &DRM_EVENT_FLIP_COMPLETE type when the
964	964	* page-flip is done.
	965	+ *
	966	+ * When used with atomic uAPI, one event will be delivered per CRTC included in
	967	+ * the atomic commit. A CRTC is included in an atomic commit if one of its
	968	+ * properties is set, or if a property is set on a connector or plane linked
	969	+ * via the CRTC_ID property to the CRTC. At least one CRTC must be included,
	970	+ * and all pulled in CRTCs must be either previously or newly powered on (in
	971	+ * other words, a powered off CRTC which stays off cannot be included in the
	972	+ * atomic commit).
965	973	*/
966	974	#define DRM_MODE_PAGE_FLIP_EVENT 0x01
967	975	/**

include/uapi/drm/panthor_drm.h+3−0

@@ -327,6 +327,9 @@ struct drm_panthor_gpu_info { · 326 unmodified lines
327	327
328	328	/** @pad: MBZ. */
329	329	__u32 pad;
	330	+
	331	+ /** @gpu_features: Bitmask describing supported GPU-wide features */
	332	+ __u64 gpu_features;
330	333	};
331	334
332	335	/**

include/uapi/drm/rocket_accel.h+142−0

@@ -0,0 +1,142 @@
	1	+/* SPDX-License-Identifier: MIT */
	2	+/*
	3	+ * Copyright © 2024 Tomeu Vizoso
	4	+ */
	5	+#ifndef __DRM_UAPI_ROCKET_ACCEL_H__
	6	+#define __DRM_UAPI_ROCKET_ACCEL_H__
	7	+
	8	+#include "drm.h"
	9	+
	10	+#if defined(__cplusplus)
	11	+extern "C" {
	12	+#endif
	13	+
	14	+#define DRM_ROCKET_CREATE_BO 0x00
	15	+#define DRM_ROCKET_SUBMIT 0x01
	16	+#define DRM_ROCKET_PREP_BO 0x02
	17	+#define DRM_ROCKET_FINI_BO 0x03
	18	+
	19	+#define DRM_IOCTL_ROCKET_CREATE_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_ROCKET_CREATE_BO, struct drm_rocket_create_bo)
	20	+#define DRM_IOCTL_ROCKET_SUBMIT DRM_IOW(DRM_COMMAND_BASE + DRM_ROCKET_SUBMIT, struct drm_rocket_submit)
	21	+#define DRM_IOCTL_ROCKET_PREP_BO DRM_IOW(DRM_COMMAND_BASE + DRM_ROCKET_PREP_BO, struct drm_rocket_prep_bo)
	22	+#define DRM_IOCTL_ROCKET_FINI_BO DRM_IOW(DRM_COMMAND_BASE + DRM_ROCKET_FINI_BO, struct drm_rocket_fini_bo)
	23	+
	24	+/**
	25	+ * struct drm_rocket_create_bo - ioctl argument for creating Rocket BOs.
	26	+ *
	27	+ */
	28	+struct drm_rocket_create_bo {
	29	+ /** Input: Size of the requested BO. */
	30	+ __u32 size;
	31	+
	32	+ /** Output: GEM handle for the BO. */
	33	+ __u32 handle;
	34	+
	35	+ /**
	36	+ * Output: DMA address for the BO in the NPU address space. This address
	37	+ * is private to the DRM fd and is valid for the lifetime of the GEM
	38	+ * handle.
	39	+ */
	40	+ __u64 dma_address;
	41	+
	42	+ /** Output: Offset into the drm node to use for subsequent mmap call. */
	43	+ __u64 offset;
	44	+};
	45	+
	46	+/**
	47	+ * struct drm_rocket_prep_bo - ioctl argument for starting CPU ownership of the BO.
	48	+ *
	49	+ * Takes care of waiting for any NPU jobs that might still use the NPU and performs cache
	50	+ * synchronization.
	51	+ */
	52	+struct drm_rocket_prep_bo {
	53	+ /** Input: GEM handle of the buffer object. */
	54	+ __u32 handle;
	55	+
	56	+ /** Reserved, must be zero. */
	57	+ __u32 reserved;
	58	+
	59	+ /** Input: Amount of time to wait for NPU jobs. */
	60	+ __s64 timeout_ns;
	61	+};
	62	+
	63	+/**
	64	+ * struct drm_rocket_fini_bo - ioctl argument for finishing CPU ownership of the BO.
	65	+ *
	66	+ * Synchronize caches for NPU access.
	67	+ */
	68	+struct drm_rocket_fini_bo {
	69	+ /** Input: GEM handle of the buffer object. */
	70	+ __u32 handle;
	71	+
	72	+ /** Reserved, must be zero. */
	73	+ __u32 reserved;
	74	+};
	75	+
	76	+/**
	77	+ * struct drm_rocket_task - A task to be run on the NPU
	78	+ *
	79	+ * A task is the smallest unit of work that can be run on the NPU.
	80	+ */
	81	+struct drm_rocket_task {
	82	+ /** Input: DMA address to NPU mapping of register command buffer */
	83	+ __u32 regcmd;
	84	+
	85	+ /** Input: Number of commands in the register command buffer */
	86	+ __u32 regcmd_count;
	87	+};
	88	+
	89	+/**
	90	+ * struct drm_rocket_job - A job to be run on the NPU
	91	+ *
	92	+ * The kernel will schedule the execution of this job taking into account its
	93	+ * dependencies with other jobs. All tasks in the same job will be executed
	94	+ * sequentially on the same core, to benefit from memory residency in SRAM.
	95	+ */
	96	+struct drm_rocket_job {
	97	+ /** Input: Pointer to an array of struct drm_rocket_task. */
	98	+ __u64 tasks;
	99	+
	100	+ /** Input: Pointer to a u32 array of the BOs that are read by the job. */
	101	+ __u64 in_bo_handles;
	102	+
	103	+ /** Input: Pointer to a u32 array of the BOs that are written to by the job. */
	104	+ __u64 out_bo_handles;
	105	+
	106	+ /** Input: Number of tasks passed in. */
	107	+ __u32 task_count;
	108	+
	109	+ /** Input: Size in bytes of the structs in the @tasks field. */
	110	+ __u32 task_struct_size;
	111	+
	112	+ /** Input: Number of input BO handles passed in (size is that times 4). */
	113	+ __u32 in_bo_handle_count;
	114	+
	115	+ /** Input: Number of output BO handles passed in (size is that times 4). */
	116	+ __u32 out_bo_handle_count;
	117	+};
	118	+
	119	+/**
	120	+ * struct drm_rocket_submit - ioctl argument for submitting commands to the NPU.
	121	+ *
	122	+ * The kernel will schedule the execution of these jobs in dependency order.
	123	+ */
	124	+struct drm_rocket_submit {
	125	+ /** Input: Pointer to an array of struct drm_rocket_job. */
	126	+ __u64 jobs;
	127	+
	128	+ /** Input: Number of jobs passed in. */
	129	+ __u32 job_count;
	130	+
	131	+ /** Input: Size in bytes of the structs in the @jobs field. */
	132	+ __u32 job_struct_size;
	133	+
	134	+ /** Reserved, must be zero. */
	135	+ __u64 reserved;
	136	+};
	137	+
	138	+#if defined(__cplusplus)
	139	+}
	140	+#endif
	141	+
	142	+#endif /* __DRM_UAPI_ROCKET_ACCEL_H__ */

include/uapi/drm/v3d_drm.h+2−0

@@ -294,6 +294,8 @@ enum drm_v3d_param { · 293 unmodified lines
294	294	DRM_V3D_PARAM_SUPPORTS_CPU_QUEUE,
295	295	DRM_V3D_PARAM_MAX_PERF_COUNTERS,
296	296	DRM_V3D_PARAM_SUPPORTS_SUPER_PAGES,
	297	+ DRM_V3D_PARAM_GLOBAL_RESET_COUNTER,
	298	+ DRM_V3D_PARAM_CONTEXT_RESET_COUNTER,
297	299	};
298	300
299	301	struct drm_v3d_get_param {

include/uapi/drm/xe_drm.h+281−1

@@ -81,6 +81,8 @@ extern "C" { · 80 unmodified lines
81	81	* - &DRM_IOCTL_XE_EXEC
82	82	* - &DRM_IOCTL_XE_WAIT_USER_FENCE
83	83	* - &DRM_IOCTL_XE_OBSERVATION
	84	+ * - &DRM_IOCTL_XE_MADVISE
	85	+ * - &DRM_IOCTL_XE_VM_QUERY_MEM_RANGE_ATTRS
84	86	*/
85	87
86	88	/*
@@ -102,6 +104,8 @@ extern "C" { · 15 unmodified lines
102	104	#define DRM_XE_EXEC 0x09
103	105	#define DRM_XE_WAIT_USER_FENCE 0x0a
104	106	#define DRM_XE_OBSERVATION 0x0b
	107	+#define DRM_XE_MADVISE 0x0c
	108	+#define DRM_XE_VM_QUERY_MEM_RANGE_ATTRS 0x0d
105	109
106	110	/* Must be kept compact -- no holes */
107	111
@@ -117,6 +121,8 @@ extern "C" { · 9 unmodified lines
117	121	#define DRM_IOCTL_XE_EXEC DRM_IOW(DRM_COMMAND_BASE + DRM_XE_EXEC, struct drm_xe_exec)
118	122	#define DRM_IOCTL_XE_WAIT_USER_FENCE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_WAIT_USER_FENCE, struct drm_xe_wait_user_fence)
119	123	#define DRM_IOCTL_XE_OBSERVATION DRM_IOW(DRM_COMMAND_BASE + DRM_XE_OBSERVATION, struct drm_xe_observation_param)
	124	+#define DRM_IOCTL_XE_MADVISE DRM_IOW(DRM_COMMAND_BASE + DRM_XE_MADVISE, struct drm_xe_madvise)
	125	+#define DRM_IOCTL_XE_VM_QUERY_MEM_RANGE_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_VM_QUERY_MEM_RANGE_ATTRS, struct drm_xe_vm_query_mem_range_attr)
120	126
121	127	/**
122	128	* DOC: Xe IOCTL Extensions
@@ -760,7 +766,11 @@ struct drm_xe_device_query { · 637 unmodified lines
760	766	* gem creation
761	767	*
762	768	* The @flags can be:
763		− * - %DRM_XE_GEM_CREATE_FLAG_DEFER_BACKING
	769	+ * - %DRM_XE_GEM_CREATE_FLAG_DEFER_BACKING - Modify the GEM object
	770	+ * allocation strategy by deferring physical memory allocation
	771	+ * until the object is either bound to a virtual memory region via
	772	+ * VM_BIND or accessed by the CPU. As a result, no backing memory is
	773	+ * reserved at the time of GEM object creation.
764	774	* - %DRM_XE_GEM_CREATE_FLAG_SCANOUT
765	775	* - %DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM - When using VRAM as a
766	776	* possible placement, ensure that the corresponding VRAM allocation
@@ -1003,6 +1013,10 @@ struct drm_xe_vm_destroy { · 236 unmodified lines
1003	1013	* valid on VMs with DRM_XE_VM_CREATE_FLAG_FAULT_MODE set. The CPU address
1004	1014	* mirror flag are only valid for DRM_XE_VM_BIND_OP_MAP operations, the BO
1005	1015	* handle MBZ, and the BO offset MBZ.
	1016	+ *
	1017	+ * The @prefetch_mem_region_instance for %DRM_XE_VM_BIND_OP_PREFETCH can also be:
	1018	+ * - %DRM_XE_CONSULT_MEM_ADVISE_PREF_LOC, which ensures prefetching occurs in
	1019	+ * the memory region advised by madvise.
1006	1020	*/
1007	1021	struct drm_xe_vm_bind_op {
1008	1022	/** @extensions: Pointer to the first extension struct, if any */
@@ -1108,6 +1122,7 @@ struct drm_xe_vm_bind_op { · 99 unmodified lines
1108	1122	/** @flags: Bind flags */
1109	1123	__u32 flags;
1110	1124
	1125	+#define DRM_XE_CONSULT_MEM_ADVISE_PREF_LOC -1
1111	1126	/**
1112	1127	* @prefetch_mem_region_instance: Memory region to prefetch VMA to.
1113	1128	* It is a region instance, not a mask.
@@ -1974,6 +1989,271 @@ struct drm_xe_query_eu_stall { · 860 unmodified lines
1974	1989	__u64 sampling_rates[];
1975	1990	};
1976	1991
	1992	+/**
	1993	+ * struct drm_xe_madvise - Input of &DRM_IOCTL_XE_MADVISE
	1994	+ *
	1995	+ * This structure is used to set memory attributes for a virtual address range
	1996	+ * in a VM. The type of attribute is specified by @type, and the corresponding
	1997	+ * union member is used to provide additional parameters for @type.
	1998	+ *
	1999	+ * Supported attribute types:
	2000	+ * - DRM_XE_MEM_RANGE_ATTR_PREFERRED_LOC: Set preferred memory location.
	2001	+ * - DRM_XE_MEM_RANGE_ATTR_ATOMIC: Set atomic access policy.
	2002	+ * - DRM_XE_MEM_RANGE_ATTR_PAT: Set page attribute table index.
	2003	+ *
	2004	+ * Example:
	2005	+ *
	2006	+ * .. code-block:: C
	2007	+ *
	2008	+ * struct drm_xe_madvise madvise = {
	2009	+ * .vm_id = vm_id,
	2010	+ * .start = 0x100000,
	2011	+ * .range = 0x2000,
	2012	+ * .type = DRM_XE_MEM_RANGE_ATTR_ATOMIC,
	2013	+ * .atomic_val = DRM_XE_ATOMIC_DEVICE,
	2014	+ * };
	2015	+ *
	2016	+ * ioctl(fd, DRM_IOCTL_XE_MADVISE, &madvise);
	2017	+ *
	2018	+ */
	2019	+struct drm_xe_madvise {
	2020	+ /** @extensions: Pointer to the first extension struct, if any */
	2021	+ __u64 extensions;
	2022	+
	2023	+ /** @start: start of the virtual address range */
	2024	+ __u64 start;
	2025	+
	2026	+ /** @range: size of the virtual address range */
	2027	+ __u64 range;
	2028	+
	2029	+ /** @vm_id: vm_id of the virtual range */
	2030	+ __u32 vm_id;
	2031	+
	2032	+#define DRM_XE_MEM_RANGE_ATTR_PREFERRED_LOC 0
	2033	+#define DRM_XE_MEM_RANGE_ATTR_ATOMIC 1
	2034	+#define DRM_XE_MEM_RANGE_ATTR_PAT 2
	2035	+ /** @type: type of attribute */
	2036	+ __u32 type;
	2037	+
	2038	+ union {
	2039	+ /**
	2040	+ * @preferred_mem_loc: preferred memory location
	2041	+ *
	2042	+ * Used when @type == DRM_XE_MEM_RANGE_ATTR_PREFERRED_LOC
	2043	+ *
	2044	+ * Supported values for @preferred_mem_loc.devmem_fd:
	2045	+ * - DRM_XE_PREFERRED_LOC_DEFAULT_DEVICE: set vram of fault tile as preferred loc
	2046	+ * - DRM_XE_PREFERRED_LOC_DEFAULT_SYSTEM: set smem as preferred loc
	2047	+ *
	2048	+ * Supported values for @preferred_mem_loc.migration_policy:
	2049	+ * - DRM_XE_MIGRATE_ALL_PAGES
	2050	+ * - DRM_XE_MIGRATE_ONLY_SYSTEM_PAGES
	2051	+ */
	2052	+ struct {
	2053	+#define DRM_XE_PREFERRED_LOC_DEFAULT_DEVICE 0
	2054	+#define DRM_XE_PREFERRED_LOC_DEFAULT_SYSTEM -1
	2055	+ /** @preferred_mem_loc.devmem_fd: fd for preferred loc */
	2056	+ __u32 devmem_fd;
	2057	+
	2058	+#define DRM_XE_MIGRATE_ALL_PAGES 0
	2059	+#define DRM_XE_MIGRATE_ONLY_SYSTEM_PAGES 1
	2060	+ /** @preferred_mem_loc.migration_policy: Page migration policy */
	2061	+ __u16 migration_policy;
	2062	+
	2063	+ /** @preferred_mem_loc.pad : MBZ */
	2064	+ __u16 pad;
	2065	+
	2066	+ /** @preferred_mem_loc.reserved : Reserved */
	2067	+ __u64 reserved;
	2068	+ } preferred_mem_loc;
	2069	+
	2070	+ /**
	2071	+ * @atomic: Atomic access policy
	2072	+ *
	2073	+ * Used when @type == DRM_XE_MEM_RANGE_ATTR_ATOMIC.
	2074	+ *
	2075	+ * Supported values for @atomic.val:
	2076	+ * - DRM_XE_ATOMIC_UNDEFINED: Undefined or default behaviour.
	2077	+ * Support both GPU and CPU atomic operations for system allocator.
	2078	+ * Support GPU atomic operations for normal(bo) allocator.
	2079	+ * - DRM_XE_ATOMIC_DEVICE: Support GPU atomic operations.
	2080	+ * - DRM_XE_ATOMIC_GLOBAL: Support both GPU and CPU atomic operations.
	2081	+ * - DRM_XE_ATOMIC_CPU: Support CPU atomic only, no GPU atomics supported.
	2082	+ */
	2083	+ struct {
	2084	+#define DRM_XE_ATOMIC_UNDEFINED 0
	2085	+#define DRM_XE_ATOMIC_DEVICE 1
	2086	+#define DRM_XE_ATOMIC_GLOBAL 2
	2087	+#define DRM_XE_ATOMIC_CPU 3
	2088	+ /** @atomic.val: value of atomic operation */
	2089	+ __u32 val;
	2090	+
	2091	+ /** @atomic.pad: MBZ */
	2092	+ __u32 pad;
	2093	+
	2094	+ /** @atomic.reserved: Reserved */
	2095	+ __u64 reserved;
	2096	+ } atomic;
	2097	+
	2098	+ /**
	2099	+ * @pat_index: Page attribute table index
	2100	+ *
	2101	+ * Used when @type == DRM_XE_MEM_RANGE_ATTR_PAT.
	2102	+ */
	2103	+ struct {
	2104	+ /** @pat_index.val: PAT index value */
	2105	+ __u32 val;
	2106	+
	2107	+ /** @pat_index.pad: MBZ */
	2108	+ __u32 pad;
	2109	+
	2110	+ /** @pat_index.reserved: Reserved */
	2111	+ __u64 reserved;
	2112	+ } pat_index;
	2113	+ };
	2114	+
	2115	+ /** @reserved: Reserved */
	2116	+ __u64 reserved[2];
	2117	+};
	2118	+
	2119	+/**
	2120	+ * struct drm_xe_mem_range_attr - Output of &DRM_IOCTL_XE_VM_QUERY_MEM_RANGES_ATTRS
	2121	+ *
	2122	+ * This structure is provided by userspace and filled by KMD in response to the
	2123	+ * DRM_IOCTL_XE_VM_QUERY_MEM_RANGES_ATTRS ioctl. It describes memory attributes of
	2124	+ * a memory ranges within a user specified address range in a VM.
	2125	+ *
	2126	+ * The structure includes information such as atomic access policy,
	2127	+ * page attribute table (PAT) index, and preferred memory location.
	2128	+ * Userspace allocates an array of these structures and passes a pointer to the
	2129	+ * ioctl to retrieve attributes for each memory ranges
	2130	+ *
	2131	+ * @extensions: Pointer to the first extension struct, if any
	2132	+ * @start: Start address of the memory range
	2133	+ * @end: End address of the virtual memory range
	2134	+ *
	2135	+ */
	2136	+struct drm_xe_mem_range_attr {
	2137	+ /** @extensions: Pointer to the first extension struct, if any */
	2138	+ __u64 extensions;
	2139	+
	2140	+ /** @start: start of the memory range */
	2141	+ __u64 start;
	2142	+
	2143	+ /** @end: end of the memory range */
	2144	+ __u64 end;
	2145	+
	2146	+ /** @preferred_mem_loc: preferred memory location */
	2147	+ struct {
	2148	+ /** @preferred_mem_loc.devmem_fd: fd for preferred loc */
	2149	+ __u32 devmem_fd;
	2150	+
	2151	+ /** @preferred_mem_loc.migration_policy: Page migration policy */
	2152	+ __u32 migration_policy;
	2153	+ } preferred_mem_loc;
	2154	+
	2155	+ /** @atomic: Atomic access policy */
	2156	+ struct {
	2157	+ /** @atomic.val: atomic attribute */
	2158	+ __u32 val;
	2159	+
	2160	+ /** @atomic.reserved: Reserved */
	2161	+ __u32 reserved;
	2162	+ } atomic;
	2163	+
	2164	+ /** @pat_index: Page attribute table index */
	2165	+ struct {
	2166	+ /** @pat_index.val: PAT index */
	2167	+ __u32 val;
	2168	+
	2169	+ /** @pat_index.reserved: Reserved */
	2170	+ __u32 reserved;
	2171	+ } pat_index;
	2172	+
	2173	+ /** @reserved: Reserved */
	2174	+ __u64 reserved[2];
	2175	+};
	2176	+
	2177	+/**
	2178	+ * struct drm_xe_vm_query_mem_range_attr - Input of &DRM_IOCTL_XE_VM_QUERY_MEM_ATTRIBUTES
	2179	+ *
	2180	+ * This structure is used to query memory attributes of memory regions
	2181	+ * within a user specified address range in a VM. It provides detailed
	2182	+ * information about each memory range, including atomic access policy,
	2183	+ * page attribute table (PAT) index, and preferred memory location.
	2184	+ *
	2185	+ * Userspace first calls the ioctl with @num_mem_ranges = 0,
	2186	+ * @sizeof_mem_ranges_attr = 0 and @vector_of_vma_mem_attr = NULL to retrieve
	2187	+ * the number of memory regions and size of each memory range attribute.
	2188	+ * Then, it allocates a buffer of that size and calls the ioctl again to fill
	2189	+ * the buffer with memory range attributes.
	2190	+ *
	2191	+ * If second call fails with -ENOSPC, it means memory ranges changed between
	2192	+ * first call and now, retry IOCTL again with @num_mem_ranges = 0,
	2193	+ * @sizeof_mem_ranges_attr = 0 and @vector_of_vma_mem_attr = NULL followed by
	2194	+ * Second ioctl call.
	2195	+ *
	2196	+ * Example:
	2197	+ *
	2198	+ * .. code-block:: C
	2199	+ *
	2200	+ * struct drm_xe_vm_query_mem_range_attr query = {
	2201	+ * .vm_id = vm_id,
	2202	+ * .start = 0x100000,
	2203	+ * .range = 0x2000,
	2204	+ * };
	2205	+ *
	2206	+ * // First ioctl call to get num of mem regions and sizeof each attribute
	2207	+ * ioctl(fd, DRM_IOCTL_XE_VM_QUERY_MEM_RANGE_ATTRS, &query);
	2208	+ *
	2209	+ * // Allocate buffer for the memory region attributes
	2210	+ * void ptr = malloc(query.num_mem_ranges query.sizeof_mem_range_attr);
	2211	+ * void *ptr_start = ptr;
	2212	+ *
	2213	+ * query.vector_of_mem_attr = (uintptr_t)ptr;
	2214	+ *
	2215	+ * // Second ioctl call to actually fill the memory attributes
	2216	+ * ioctl(fd, DRM_IOCTL_XE_VM_QUERY_MEM_RANGE_ATTRS, &query);
	2217	+ *
	2218	+ * // Iterate over the returned memory region attributes
	2219	+ * for (unsigned int i = 0; i < query.num_mem_ranges; ++i) {
	2220	+ * struct drm_xe_mem_range_attr attr = (struct drm_xe_mem_range_attr )ptr;
	2221	+ *
	2222	+ * // Do something with attr
	2223	+ *
	2224	+ * // Move pointer by one entry
	2225	+ * ptr += query.sizeof_mem_range_attr;
	2226	+ * }
	2227	+ *
	2228	+ * free(ptr_start);
	2229	+ */
	2230	+struct drm_xe_vm_query_mem_range_attr {
	2231	+ /** @extensions: Pointer to the first extension struct, if any */
	2232	+ __u64 extensions;
	2233	+
	2234	+ /** @vm_id: vm_id of the virtual range */
	2235	+ __u32 vm_id;
	2236	+
	2237	+ /** @num_mem_ranges: number of mem_ranges in range */
	2238	+ __u32 num_mem_ranges;
	2239	+
	2240	+ /** @start: start of the virtual address range */
	2241	+ __u64 start;
	2242	+
	2243	+ /** @range: size of the virtual address range */
	2244	+ __u64 range;
	2245	+
	2246	+ /** @sizeof_mem_range_attr: size of struct drm_xe_mem_range_attr */
	2247	+ __u64 sizeof_mem_range_attr;
	2248	+
	2249	+ /** @vector_of_mem_attr: userptr to array of struct drm_xe_mem_range_attr */
	2250	+ __u64 vector_of_mem_attr;
	2251	+
	2252	+ /** @reserved: Reserved */
	2253	+ __u64 reserved[2];
	2254	+
	2255	+};
	2256	+
1977	2257	#if defined(__cplusplus)
1978	2258	}
1979	2259	#endif

Merge tag 'drm-next-2025-10-01' of https://gitlab.freedesktop.org/drm/kernel

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