- Use FIELD_GET()/FIELD_PREP() when possible throughout drivers/pci/ (Ilpo Järvinen, Bjorn Helgaas) - Rework DPC control programming for clarity (Ilpo Järvinen) * pci/field-get: PCI/portdrv: Use FIELD_GET() PCI/VC: Use FIELD_GET() PCI/PTM: Use FIELD_GET() PCI/PME: Use FIELD_GET() PCI/ATS: Use FIELD_GET() PCI/ATS: Show PASID Capability register width in bitmasks PCI: Use FIELD_GET() in Sapphire RX 5600 XT Pulse quirk PCI: Use FIELD_GET() PCI/MSI: Use FIELD_GET/PREP() PCI/DPC: Use defines with DPC reason fields PCI/DPC: Use defined fields with DPC_CTL register PCI/DPC: Use FIELD_GET() PCI: hotplug: Use FIELD_GET/PREP() PCI: dwc: Use FIELD_GET/PREP() PCI: cadence: Use FIELD_GET() PCI: Use FIELD_GET() to extract Link Width PCI: mvebu: Use FIELD_PREP() with Link Width PCI: tegra194: Use FIELD_GET()/FIELD_PREP() with Link Width fields # Conflicts: # drivers/pci/controller/dwc/pcie-tegra194.c
Showing the changes to include/uapi (1 of 19 files). Show all
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| @@ -638,6 +638,7 @@ · 637 unmodified lines | |||
| 638 | #define PCI_EXP_RTCAP 0x1e /* Root Capabilities */ | 638 | #define PCI_EXP_RTCAP 0x1e /* Root Capabilities */ |
| 639 | #define PCI_EXP_RTCAP_CRSVIS 0x0001 /* CRS Software Visibility capability */ | 639 | #define PCI_EXP_RTCAP_CRSVIS 0x0001 /* CRS Software Visibility capability */ |
| 640 | #define PCI_EXP_RTSTA 0x20 /* Root Status */ | 640 | #define PCI_EXP_RTSTA 0x20 /* Root Status */ |
| 641 | #define PCI_EXP_RTSTA_PME_RQ_ID 0x0000ffff /* PME Requester ID */ | ||
| 641 | #define PCI_EXP_RTSTA_PME 0x00010000 /* PME status */ | 642 | #define PCI_EXP_RTSTA_PME 0x00010000 /* PME status */ |
| 642 | #define PCI_EXP_RTSTA_PENDING 0x00020000 /* PME pending */ | 643 | #define PCI_EXP_RTSTA_PENDING 0x00020000 /* PME pending */ |
| 643 | /* | 644 | /* |
| @@ -931,12 +932,13 @@ · 287 unmodified lines | |||
| 931 | 932 | ||
| 932 | /* Process Address Space ID */ | 933 | /* Process Address Space ID */ |
| 933 | #define PCI_PASID_CAP 0x04 /* PASID feature register */ | 934 | #define PCI_PASID_CAP 0x04 /* PASID feature register */ |
| 934 | #define PCI_PASID_CAP_EXEC 0x02 /* Exec permissions Supported */ | 935 | #define PCI_PASID_CAP_EXEC 0x0002 /* Exec permissions Supported */ |
| 935 | #define PCI_PASID_CAP_PRIV 0x04 /* Privilege Mode Supported */ | 936 | #define PCI_PASID_CAP_PRIV 0x0004 /* Privilege Mode Supported */ |
| 937 | #define PCI_PASID_CAP_WIDTH 0x1f00 | ||
| 936 | #define PCI_PASID_CTRL 0x06 /* PASID control register */ | 938 | #define PCI_PASID_CTRL 0x06 /* PASID control register */ |
| 937 | #define PCI_PASID_CTRL_ENABLE 0x01 /* Enable bit */ | 939 | #define PCI_PASID_CTRL_ENABLE 0x0001 /* Enable bit */ |
| 938 | #define PCI_PASID_CTRL_EXEC 0x02 /* Exec permissions Enable */ | 940 | #define PCI_PASID_CTRL_EXEC 0x0002 /* Exec permissions Enable */ |
| 939 | #define PCI_PASID_CTRL_PRIV 0x04 /* Privilege Mode Enable */ | 941 | #define PCI_PASID_CTRL_PRIV 0x0004 /* Privilege Mode Enable */ |
| 940 | #define PCI_EXT_CAP_PASID_SIZEOF 8 | 942 | #define PCI_EXT_CAP_PASID_SIZEOF 8 |
| 941 | 943 | ||
| 942 | /* Single Root I/O Virtualization */ | 944 | /* Single Root I/O Virtualization */ |
| @@ -976,6 +978,8 @@ · 33 unmodified lines | |||
| 976 | #define PCI_LTR_VALUE_MASK 0x000003ff | 978 | #define PCI_LTR_VALUE_MASK 0x000003ff |
| 977 | #define PCI_LTR_SCALE_MASK 0x00001c00 | 979 | #define PCI_LTR_SCALE_MASK 0x00001c00 |
| 978 | #define PCI_LTR_SCALE_SHIFT 10 | 980 | #define PCI_LTR_SCALE_SHIFT 10 |
| 981 | #define PCI_LTR_NOSNOOP_VALUE 0x03ff0000 /* Max No-Snoop Latency Value */ | ||
| 982 | #define PCI_LTR_NOSNOOP_SCALE 0x1c000000 /* Scale for Max Value */ | ||
| 979 | #define PCI_EXT_CAP_LTR_SIZEOF 8 | 983 | #define PCI_EXT_CAP_LTR_SIZEOF 8 |
| 980 | 984 | ||
| 981 | /* Access Control Service */ | 985 | /* Access Control Service */ |
| @@ -1043,9 +1047,16 @@ · 61 unmodified lines | |||
| 1043 | #define PCI_EXP_DPC_STATUS 0x08 /* DPC Status */ | 1047 | #define PCI_EXP_DPC_STATUS 0x08 /* DPC Status */ |
| 1044 | #define PCI_EXP_DPC_STATUS_TRIGGER 0x0001 /* Trigger Status */ | 1048 | #define PCI_EXP_DPC_STATUS_TRIGGER 0x0001 /* Trigger Status */ |
| 1045 | #define PCI_EXP_DPC_STATUS_TRIGGER_RSN 0x0006 /* Trigger Reason */ | 1049 | #define PCI_EXP_DPC_STATUS_TRIGGER_RSN 0x0006 /* Trigger Reason */ |
| 1050 | #define PCI_EXP_DPC_STATUS_TRIGGER_RSN_UNCOR 0x0000 /* Uncorrectable error */ | ||
| 1051 | #define PCI_EXP_DPC_STATUS_TRIGGER_RSN_NFE 0x0002 /* Rcvd ERR_NONFATAL */ | ||
| 1052 | #define PCI_EXP_DPC_STATUS_TRIGGER_RSN_FE 0x0004 /* Rcvd ERR_FATAL */ | ||
| 1053 | #define PCI_EXP_DPC_STATUS_TRIGGER_RSN_IN_EXT 0x0006 /* Reason in Trig Reason Extension field */ | ||
| 1046 | #define PCI_EXP_DPC_STATUS_INTERRUPT 0x0008 /* Interrupt Status */ | 1054 | #define PCI_EXP_DPC_STATUS_INTERRUPT 0x0008 /* Interrupt Status */ |
| 1047 | #define PCI_EXP_DPC_RP_BUSY 0x0010 /* Root Port Busy */ | 1055 | #define PCI_EXP_DPC_RP_BUSY 0x0010 /* Root Port Busy */ |
| 1048 | #define PCI_EXP_DPC_STATUS_TRIGGER_RSN_EXT 0x0060 /* Trig Reason Extension */ | 1056 | #define PCI_EXP_DPC_STATUS_TRIGGER_RSN_EXT 0x0060 /* Trig Reason Extension */ |
| 1057 | #define PCI_EXP_DPC_STATUS_TRIGGER_RSN_RP_PIO 0x0000 /* RP PIO error */ | ||
| 1058 | #define PCI_EXP_DPC_STATUS_TRIGGER_RSN_SW_TRIGGER 0x0020 /* DPC SW Trigger bit */ | ||
| 1059 | #define PCI_EXP_DPC_RP_PIO_FEP 0x1f00 /* RP PIO First Err Ptr */ | ||
| 1049 | 1060 | ||
| 1050 | #define PCI_EXP_DPC_SOURCE_ID 0x0A /* DPC Source Identifier */ | 1061 | #define PCI_EXP_DPC_SOURCE_ID 0x0A /* DPC Source Identifier */ |
| 1051 | 1062 | ||