History

soc: qcom: geni: Support for ICC voting

Add necessary macros and structure variables to support ICC BW voting from individual SE drivers.

Akash Asthana committed 6 years ago

Commit 58ffbba1 parent be24c6a2 files · +120 −0Browse files

Showing the changes to include/linux (1 of 2 files). Show all

Unified · Split

include/linux/qcom-geni-se.h+38−0
@@ -6,6 +6,8 @@ · 5 unmodified lines
6#ifndef _LINUX_QCOM_GENI_SE6#ifndef _LINUX_QCOM_GENI_SE
7#define _LINUX_QCOM_GENI_SE7#define _LINUX_QCOM_GENI_SE
8 8
9#include <linux/interconnect.h>
10
9/* Transfer mode supported by GENI Serial Engines */11/* Transfer mode supported by GENI Serial Engines */
10enum geni_se_xfer_mode {12enum geni_se_xfer_mode {
11 GENI_SE_INVALID,13 GENI_SE_INVALID,
@@ -25,6 +27,17 @@ enum geni_se_protocol_type { · 13 unmodified lines
25struct geni_wrapper;27struct geni_wrapper;
26struct clk;28struct clk;
27 29
30enum geni_icc_path_index {
31 GENI_TO_CORE,
32 CPU_TO_GENI,
33 GENI_TO_DDR
34};
35
36struct geni_icc_path {
37 struct icc_path *path;
38 unsigned int avg_bw;
39};
40
28/**41/**
29 * struct geni_se - GENI Serial Engine42 * struct geni_se - GENI Serial Engine
30 * @base: Base Address of the Serial Engine's register block43 * @base: Base Address of the Serial Engine's register block
@@ -33,6 +46,7 @@ struct clk; · 2 unmodified lines
33 * @clk: Handle to the core serial engine clock46 * @clk: Handle to the core serial engine clock
34 * @num_clk_levels: Number of valid clock levels in clk_perf_tbl47 * @num_clk_levels: Number of valid clock levels in clk_perf_tbl
35 * @clk_perf_tbl: Table of clock frequency input to serial engine clock48 * @clk_perf_tbl: Table of clock frequency input to serial engine clock
49 * @icc_paths: Array of ICC paths for SE
36 */50 */
37struct geni_se {51struct geni_se {
38 void __iomem *base;52 void __iomem *base;
@@ -41,6 +55,7 @@ struct geni_se { · 2 unmodified lines
41 struct clk *clk;55 struct clk *clk;
42 unsigned int num_clk_levels;56 unsigned int num_clk_levels;
43 unsigned long *clk_perf_tbl;57 unsigned long *clk_perf_tbl;
58 struct geni_icc_path icc_paths[3];
44};59};
45 60
46/* Common SE registers */61/* Common SE registers */
@@ -229,6 +244,21 @@ struct geni_se { · 182 unmodified lines
229#define GENI_SE_VERSION_MINOR(ver) ((ver & HW_VER_MINOR_MASK) >> HW_VER_MINOR_SHFT)244#define GENI_SE_VERSION_MINOR(ver) ((ver & HW_VER_MINOR_MASK) >> HW_VER_MINOR_SHFT)
230#define GENI_SE_VERSION_STEP(ver) (ver & HW_VER_STEP_MASK)245#define GENI_SE_VERSION_STEP(ver) (ver & HW_VER_STEP_MASK)
231 246
247/*
248 * Define bandwidth thresholds that cause the underlying Core 2X interconnect
249 * clock to run at the named frequency. These baseline values are recommended
250 * by the hardware team, and are not dynamically scaled with GENI bandwidth
251 * beyond basic on/off.
252 */
253#define CORE_2X_19_2_MHZ 960
254#define CORE_2X_50_MHZ 2500
255#define CORE_2X_100_MHZ 5000
256#define CORE_2X_150_MHZ 7500
257#define CORE_2X_200_MHZ 10000
258#define CORE_2X_236_MHZ 16383
259
260#define GENI_DEFAULT_BW Bps_to_icc(1000)
261
232#if IS_ENABLED(CONFIG_QCOM_GENI_SE)262#if IS_ENABLED(CONFIG_QCOM_GENI_SE)
233 263
234u32 geni_se_get_qup_hw_version(struct geni_se *se);264u32 geni_se_get_qup_hw_version(struct geni_se *se);
@@ -416,5 +446,13 @@ int geni_se_rx_dma_prep(struct geni_se *se, void *buf, size_t len, · 181 unmodified lines
416void geni_se_tx_dma_unprep(struct geni_se *se, dma_addr_t iova, size_t len);446void geni_se_tx_dma_unprep(struct geni_se *se, dma_addr_t iova, size_t len);
417 447
418void geni_se_rx_dma_unprep(struct geni_se *se, dma_addr_t iova, size_t len);448void geni_se_rx_dma_unprep(struct geni_se *se, dma_addr_t iova, size_t len);
449
450int geni_icc_get(struct geni_se *se, const char *icc_ddr);
451
452int geni_icc_set_bw(struct geni_se *se);
453
454int geni_icc_enable(struct geni_se *se);
455
456int geni_icc_disable(struct geni_se *se);
419#endif457#endif
420#endif458#endif