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tc: Add support for configuring the taprio scheduler

This traffic scheduler allows traffic classes states (transmission allowed/not allowed, in the simplest case) to be scheduled, according to a pre-generated time sequence. This is the basis of the IEEE 802.1Qbv specification. Example configuration: tc qdisc replace dev enp3s0 parent root handle 100 taprio \ num_tc 3 \ map 2 2 1 0 2 2 2 2 2 2 2 2 2 2 2 2 \ queues 1@0 1@1 2@2 \ base-time 1528743495910289987 \ sched-entry S 01 300000 \ sched-entry S 02 300000 \ sched-entry S 04 300000 \ clockid CLOCK_TAI The configuration format is similar to mqprio. The main difference is the presence of a schedule, built by multiple "sched-entry" definitions, each entry has the following format: sched-entry <CMD> <GATE MASK> <INTERVAL> The only supported <CMD> is "S", which means "SetGateStates", following the IEEE 802.1Qbv-2015 definition (Table 8-6). <GATE MASK> is a bitmask where each bit is a associated with a traffic class, so bit 0 (the least significant bit) being "on" means that traffic class 0 is "active" for that schedule entry. <INTERVAL> is a time duration in nanoseconds that specifies for how long that state defined by <CMD> and <GATE MASK> should be held before moving to the next entry. This schedule is circular, that is, after the last entry is executed it starts from the first one, indefinitely. The other parameters can be defined as follows: - base-time: specifies the instant when the schedule starts, if 'base-time' is a time in the past, the schedule will start at base-time + (N * cycle-time) where N is the smallest integer so the resulting time is greater than "now", and "cycle-time" is the sum of all the intervals of the entries in the schedule; - clockid: specifies the reference clock to be used; The parameters should be similar to what the IEEE 802.1Q family of specification defines.

Vinicius Costa Gomes committed 8 years ago

Commit 5a781cc1 parent 34f8c584 files · +1020 −0Browse files

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include/uapi/linux/pkt_sched.h+46−0
@@ -1084,4 +1084,50 @@ enum { · 1083 unmodified lines
1084 CAKE_ATM_MAX1084 CAKE_ATM_MAX
1085};1085};
1086 1086
1087
1088/* TAPRIO */
1089enum {
1090 TC_TAPRIO_CMD_SET_GATES = 0x00,
1091 TC_TAPRIO_CMD_SET_AND_HOLD = 0x01,
1092 TC_TAPRIO_CMD_SET_AND_RELEASE = 0x02,
1093};
1094
1095enum {
1096 TCA_TAPRIO_SCHED_ENTRY_UNSPEC,
1097 TCA_TAPRIO_SCHED_ENTRY_INDEX, /* u32 */
1098 TCA_TAPRIO_SCHED_ENTRY_CMD, /* u8 */
1099 TCA_TAPRIO_SCHED_ENTRY_GATE_MASK, /* u32 */
1100 TCA_TAPRIO_SCHED_ENTRY_INTERVAL, /* u32 */
1101 __TCA_TAPRIO_SCHED_ENTRY_MAX,
1102};
1103#define TCA_TAPRIO_SCHED_ENTRY_MAX (__TCA_TAPRIO_SCHED_ENTRY_MAX - 1)
1104
1105/* The format for schedule entry list is:
1106 * [TCA_TAPRIO_SCHED_ENTRY_LIST]
1107 * [TCA_TAPRIO_SCHED_ENTRY]
1108 * [TCA_TAPRIO_SCHED_ENTRY_CMD]
1109 * [TCA_TAPRIO_SCHED_ENTRY_GATES]
1110 * [TCA_TAPRIO_SCHED_ENTRY_INTERVAL]
1111 */
1112enum {
1113 TCA_TAPRIO_SCHED_UNSPEC,
1114 TCA_TAPRIO_SCHED_ENTRY,
1115 __TCA_TAPRIO_SCHED_MAX,
1116};
1117
1118#define TCA_TAPRIO_SCHED_MAX (__TCA_TAPRIO_SCHED_MAX - 1)
1119
1120enum {
1121 TCA_TAPRIO_ATTR_UNSPEC,
1122 TCA_TAPRIO_ATTR_PRIOMAP, /* struct tc_mqprio_qopt */
1123 TCA_TAPRIO_ATTR_SCHED_ENTRY_LIST, /* nested of entry */
1124 TCA_TAPRIO_ATTR_SCHED_BASE_TIME, /* s64 */
1125 TCA_TAPRIO_ATTR_SCHED_SINGLE_ENTRY, /* single entry */
1126 TCA_TAPRIO_ATTR_SCHED_CLOCKID, /* s32 */
1127 TCA_TAPRIO_PAD,
1128 __TCA_TAPRIO_ATTR_MAX,
1129};
1130
1131#define TCA_TAPRIO_ATTR_MAX (__TCA_TAPRIO_ATTR_MAX - 1)
1132
1087#endif1133#endif