Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus

Pull MIPS updates from Ralf Baechle: "This has been sitting in -next for a while with no objections and all MIPS defconfigs except one are building fine; that one platform got broken by another patch in your tree and I'm going to submit a patch separately. - a handful of fixes that didn't make 3.11 - a few bits of Octeon 3 support with more to come for a later release - platform enhancements for Octeon, ath79, Lantiq, Netlogic and Ralink SOCs - a GPIO driver for the Octeon - some dusting off of the DECstation code - the usual dose of cleanups" * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (65 commits) MIPS: DMA: Fix BUG due to smp_processor_id() in preemptible code MIPS: kexec: Fix random crashes while loading crashkernel MIPS: kdump: Skip walking indirection page for crashkernels MIPS: DECstation HRT calibration bug fixes MIPS: Export copy_from_user_page() (needed by lustre) MIPS: Add driver for the built-in PCI controller of the RT3883 SoC MIPS: DMA: For BMIPS5000 cores flush region just like non-coherent R10000 MIPS: ralink: Add support for reset-controller API MIPS: ralink: mt7620: Add cpu-feature-override header MIPS: ralink: mt7620: Add spi clock definition MIPS: ralink: mt7620: Add wdt clock definition MIPS: ralink: mt7620: Improve clock frequency detection MIPS: ralink: mt7620: This SoC has EHCI and OHCI hosts MIPS: ralink: mt7620: Add verbose ram info MIPS: ralink: Probe clocksources from OF MIPS: ralink: Add support for systick timer found on newer ralink SoC MIPS: ralink: Add support for periodic timer irq MIPS: Netlogic: Built-in DTB for XLP2xx SoC boards MIPS: Netlogic: Add support for USB on XLP2xx MIPS: Netlogic: XLP2xx update for I2C controller ...

Linus Torvalds committed 13 years ago

Commit 5a7d8a22 parents e0ea404 eb37e6d103 files · +3109 −484Browse files

Unified · Split

103 files

Documentation/devicetree/bindings/pci/ralink,rt3883-pci.txt +190 −0
arch/mips/Kconfig +5 −14
arch/mips/Makefile +29 −5
arch/mips/ath79/clock.c +149 −109
arch/mips/ath79/common.h +2 −0
arch/mips/ath79/dev-common.c +4 −6
arch/mips/ath79/setup.c +17 −6
arch/mips/boot/.gitignore +1 −0
arch/mips/boot/Makefile +15 −0
arch/mips/boot/compressed/Makefile +1 −1
arch/mips/boot/dts/include/dt-bindings +1 −0
arch/mips/cavium-octeon/octeon-irq.c +1 −1
arch/mips/cavium-octeon/setup.c +28 −0
arch/mips/cavium-octeon/smp.c +1 −3
arch/mips/configs/xway_defconfig +159 −0
arch/mips/dec/time.c +3 −2
arch/mips/include/asm/Kbuild +13 −0
arch/mips/include/asm/bmips.h +22 −33
arch/mips/include/asm/cpu.h +5 −1
arch/mips/include/asm/cputime.h +0 −6
arch/mips/include/asm/current.h +0 −1
arch/mips/include/asm/emergency-restart.h +0 −6
arch/mips/include/asm/local64.h +0 −1
arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h +0 −2
arch/mips/include/asm/mach-cavium-octeon/gpio.h +21 −0
arch/mips/include/asm/mach-lantiq/falcon/cpu-feature-overrides.h +58 −0
arch/mips/include/asm/mach-ralink/mt7620.h +32 −8
arch/mips/include/asm/mach-ralink/mt7620/cpu-feature-overrides.h +57 −0
arch/mips/include/asm/mutex.h +0 −9
arch/mips/include/asm/netlogic/xlp-hal/bridge.h +4 −0
arch/mips/include/asm/netlogic/xlp-hal/iomap.h +10 −0
arch/mips/include/asm/netlogic/xlp-hal/pic.h +3 −2
arch/mips/include/asm/netlogic/xlp-hal/sys.h +31 −0
arch/mips/include/asm/netlogic/xlp-hal/xlp.h +17 −0
arch/mips/include/asm/netlogic/xlr/pic.h +2 −0
arch/mips/include/asm/octeon/octeon.h +2 −0
arch/mips/include/asm/parport.h +0 −1
arch/mips/include/asm/percpu.h +0 −6
arch/mips/include/asm/scatterlist.h +0 −6
arch/mips/include/asm/sections.h +0 −6
arch/mips/include/asm/segment.h +0 −6
arch/mips/include/asm/serial.h +0 −1
arch/mips/include/asm/ucontext.h +0 −1
arch/mips/include/asm/xor.h +0 −1
arch/mips/include/uapi/asm/Kbuild +3 −2
arch/mips/include/uapi/asm/auxvec.h +0 −4
arch/mips/include/uapi/asm/ipcbuf.h +0 −1
arch/mips/kernel/cpu-probe.c +12 −0
arch/mips/kernel/csrc-ioasic.c +3 −3
arch/mips/kernel/idle.c +1 −0
arch/mips/kernel/mcount.S +1 −1
arch/mips/kernel/relocate_kernel.S +6 −0
arch/mips/kernel/setup.c +48 −51
arch/mips/kernel/time.c +9 −1
arch/mips/kernel/vmlinux.lds.S +1 −0
arch/mips/lantiq/falcon/sysctrl.c +4 −1
arch/mips/lantiq/xway/Makefile +1 −1
arch/mips/lantiq/xway/dcdc.c +63 −0
arch/mips/lasat/image/Makefile +2 −4
arch/mips/loongson/common/Makefile +2 −1
arch/mips/math-emu/cp1emu.c +0 −27
arch/mips/mm/c-octeon.c +14 −0
arch/mips/mm/dma-default.c +11 −7
arch/mips/mm/gup.c +2 −1
arch/mips/mm/init.c +1 −0
arch/mips/mm/tlb-funcs.S +2 −0
arch/mips/mm/tlbex.c +2 −0
arch/mips/netlogic/Kconfig +9 −0
arch/mips/netlogic/common/smp.c +1 −3
arch/mips/netlogic/common/time.c +2 −1
arch/mips/netlogic/dts/Makefile +1 −0
arch/mips/netlogic/dts/xlp_evp.dts +1 −8
arch/mips/netlogic/dts/xlp_fvp.dts +118 −0
arch/mips/netlogic/dts/xlp_svp.dts +1 −8
arch/mips/netlogic/xlp/Makefile +1 −0
arch/mips/netlogic/xlp/dt.c +7 −1
arch/mips/netlogic/xlp/nlm_hal.c +202 −35
arch/mips/netlogic/xlp/setup.c +43 −7
arch/mips/netlogic/xlp/usb-init-xlp2.c +218 −0
arch/mips/netlogic/xlp/usb-init.c +4 −2
arch/mips/netlogic/xlp/wakeup.c +6 −4
arch/mips/pci/Makefile +1 −0
arch/mips/pci/pci-octeon.c +5 −4
arch/mips/pci/pci-rt3883.c +636 −0
arch/mips/powertv/Kconfig +1 −8
arch/mips/powertv/asic/asic_devices.c +1 −11
arch/mips/powertv/init.c +0 −4
arch/mips/powertv/reset.c +0 −12
arch/mips/ralink/Kconfig +10 −0
arch/mips/ralink/Makefile +3 −1
arch/mips/ralink/Platform +1 −0
arch/mips/ralink/cevt-rt3352.c +145 −0
arch/mips/ralink/clk.c +1 −0
arch/mips/ralink/common.h +2 −0
arch/mips/ralink/mt7620.c +180 −25
arch/mips/ralink/of.c +3 −0
arch/mips/ralink/reset.c +62 −0
arch/mips/ralink/timer.c +185 −0
arch/mips/txx9/generic/setup.c +1 −1
drivers/gpio/Kconfig +8 −0
drivers/gpio/Makefile +1 −0
drivers/gpio/gpio-octeon.c +157 −0
scripts/package/buildtar +21 −0

Documentation/devicetree/bindings/pci/ralink,rt3883-pci.txt+190−0

@@ -0,0 +1,190 @@
	1	+* Mediatek/Ralink RT3883 PCI controller
	2	+
	3	+1) Main node
	4	+
	5	+ Required properties:
	6	+
	7	+ - compatible: must be "ralink,rt3883-pci"
	8	+
	9	+ - reg: specifies the physical base address of the controller and
	10	+ the length of the memory mapped region.
	11	+
	12	+ - #address-cells: specifies the number of cells needed to encode an
	13	+ address. The value must be 1.
	14	+
	15	+ - #size-cells: specifies the number of cells used to represent the size
	16	+ of an address. The value must be 1.
	17	+
	18	+ - ranges: specifies the translation between child address space and parent
	19	+ address space
	20	+
	21	+ Optional properties:
	22	+
	23	+ - status: indicates the operational status of the device.
	24	+ Value must be either "disabled" or "okay".
	25	+
	26	+2) Child nodes
	27	+
	28	+ The main node must have two child nodes which describes the built-in
	29	+ interrupt controller and the PCI host bridge.
	30	+
	31	+ a) Interrupt controller:
	32	+
	33	+ Required properties:
	34	+
	35	+ - interrupt-controller: identifies the node as an interrupt controller
	36	+
	37	+ - #address-cells: specifies the number of cells needed to encode an
	38	+ address. The value must be 0. As such, 'interrupt-map' nodes do not
	39	+ have to specify a parent unit address.
	40	+
	41	+ - #interrupt-cells: specifies the number of cells needed to encode an
	42	+ interrupt source. The value must be 1.
	43	+
	44	+ - interrupt-parent: the phandle for the interrupt controller that
	45	+ services interrupts for this device.
	46	+
	47	+ - interrupts: specifies the interrupt source of the parent interrupt
	48	+ controller. The format of the interrupt specifier depends on the
	49	+ parent interrupt controller.
	50	+
	51	+ b) PCI host bridge:
	52	+
	53	+ Required properties:
	54	+
	55	+ - #address-cells: specifies the number of cells needed to encode an
	56	+ address. The value must be 0.
	57	+
	58	+ - #size-cells: specifies the number of cells used to represent the size
	59	+ of an address. The value must be 2.
	60	+
	61	+ - #interrupt-cells: specifies the number of cells needed to encode an
	62	+ interrupt source. The value must be 1.
	63	+
	64	+ - device_type: must be "pci"
	65	+
	66	+ - bus-range: PCI bus numbers covered
	67	+
	68	+ - ranges: specifies the ranges for the PCI memory and I/O regions
	69	+
	70	+ - interrupt-map-mask,
	71	+ - interrupt-map: standard PCI properties to define the mapping of the
	72	+ PCI interface to interrupt numbers.
	73	+
	74	+ The PCI host bridge node migh have additional sub-nodes representing
	75	+ the onboard PCI devices/PCI slots. Each such sub-node must have the
	76	+ following mandatory properties:
	77	+
	78	+ - reg: used only for interrupt mapping, so only the first four bytes
	79	+ are used to refer to the correct bus number and device number.
	80	+
	81	+ - device_type: must be "pci"
	82	+
	83	+ If a given sub-node represents a PCI bridge it must have following
	84	+ mandatory properties as well:
	85	+
	86	+ - #address-cells: must be set to <3>
	87	+
	88	+ - #size-cells: must set to <2>
	89	+
	90	+ - #interrupt-cells: must be set to <1>
	91	+
	92	+ - interrupt-map-mask,
	93	+ - interrupt-map: standard PCI properties to define the mapping of the
	94	+ PCI interface to interrupt numbers.
	95	+
	96	+ Besides the required properties the sub-nodes may have these optional
	97	+ properties:
	98	+
	99	+ - status: indicates the operational status of the sub-node.
	100	+ Value must be either "disabled" or "okay".
	101	+
	102	+3) Example:
	103	+
	104	+ a) SoC specific dtsi file:
	105	+
	106	+ pci@10140000 {
	107	+ compatible = "ralink,rt3883-pci";
	108	+ reg = <0x10140000 0x20000>;
	109	+ #address-cells = <1>;
	110	+ #size-cells = <1>;
	111	+ ranges; /* direct mapping */
	112	+
	113	+ status = "disabled";
	114	+
	115	+ pciintc: interrupt-controller {
	116	+ interrupt-controller;
	117	+ #address-cells = <0>;
	118	+ #interrupt-cells = <1>;
	119	+
	120	+ interrupt-parent = <&cpuintc>;
	121	+ interrupts = <4>;
	122	+ };
	123	+
	124	+ host-bridge {
	125	+ #address-cells = <3>;
	126	+ #size-cells = <2>;
	127	+ #interrupt-cells = <1>;
	128	+
	129	+ device_type = "pci";
	130	+
	131	+ bus-range = <0 255>;
	132	+ ranges = <
	133	+ 0x02000000 0 0x00000000 0x20000000 0 0x10000000 /* pci memory */
	134	+ 0x01000000 0 0x00000000 0x10160000 0 0x00010000 /* io space */
	135	+ >;
	136	+
	137	+ interrupt-map-mask = <0xf800 0 0 7>;
	138	+ interrupt-map = <
	139	+ /* IDSEL 17 */
	140	+ 0x8800 0 0 1 &pciintc 18
	141	+ 0x8800 0 0 2 &pciintc 18
	142	+ 0x8800 0 0 3 &pciintc 18
	143	+ 0x8800 0 0 4 &pciintc 18
	144	+ /* IDSEL 18 */
	145	+ 0x9000 0 0 1 &pciintc 19
	146	+ 0x9000 0 0 2 &pciintc 19
	147	+ 0x9000 0 0 3 &pciintc 19
	148	+ 0x9000 0 0 4 &pciintc 19
	149	+ >;
	150	+
	151	+ pci-bridge@1 {
	152	+ reg = <0x0800 0 0 0 0>;
	153	+ device_type = "pci";
	154	+ #interrupt-cells = <1>;
	155	+ #address-cells = <3>;
	156	+ #size-cells = <2>;
	157	+
	158	+ interrupt-map-mask = <0x0 0 0 0>;
	159	+ interrupt-map = <0x0 0 0 0 &pciintc 20>;
	160	+
	161	+ status = "disabled";
	162	+ };
	163	+
	164	+ pci-slot@17 {
	165	+ reg = <0x8800 0 0 0 0>;
	166	+ device_type = "pci";
	167	+
	168	+ status = "disabled";
	169	+ };
	170	+
	171	+ pci-slot@18 {
	172	+ reg = <0x9000 0 0 0 0>;
	173	+ device_type = "pci";
	174	+
	175	+ status = "disabled";
	176	+ };
	177	+ };
	178	+ };
	179	+
	180	+ b) Board specific dts file:
	181	+
	182	+ pci@10140000 {
	183	+ status = "okay";
	184	+
	185	+ host-bridge {
	186	+ pci-bridge@1 {
	187	+ status = "okay";
	188	+ };
	189	+ };
	190	+ };

arch/mips/Kconfig+5−14

@@ -95,6 +95,7 @@ config ATH79 · 94 unmodified lines
95	95	select CSRC_R4K
96	96	select DMA_NONCOHERENT
97	97	select HAVE_CLK
	98	+ select CLKDEV_LOOKUP
98	99	select IRQ_CPU
99	100	select MIPS_MACHINE
100	101	select SYS_HAS_CPU_MIPS32_R2
@@ -131,7 +132,6 @@ config BCM63XX · 30 unmodified lines
131	132	select IRQ_CPU
132	133	select SYS_HAS_CPU_MIPS32_R1
133	134	select SYS_HAS_CPU_BMIPS4350 if !BCM63XX_CPU_6338 && !BCM63XX_CPU_6345 && !BCM63XX_CPU_6348
134		− select NR_CPUS_DEFAULT_2
135	135	select SYS_SUPPORTS_32BIT_KERNEL
136	136	select SYS_SUPPORTS_BIG_ENDIAN
137	137	select SYS_HAS_EARLY_PRINTK
@@ -445,6 +445,8 @@ config RALINK · 307 unmodified lines
445	445	select SYS_HAS_EARLY_PRINTK
446	446	select HAVE_MACH_CLKDEV
447	447	select CLKDEV_LOOKUP
	448	+ select ARCH_HAS_RESET_CONTROLLER
	449	+ select RESET_CONTROLLER
448	450
449	451	config SGI_IP22
450	452	bool "SGI IP22 (Indy/Indigo2)"
@@ -609,7 +611,6 @@ config SIBYTE_SWARM · 158 unmodified lines
609	611	select BOOT_ELF32
610	612	select DMA_COHERENT
611	613	select HAVE_PATA_PLATFORM
612		− select NR_CPUS_DEFAULT_2
613	614	select SIBYTE_SB1250
614	615	select SWAP_IO_SPACE
615	616	select SYS_HAS_CPU_SB1
@@ -623,7 +624,6 @@ config SIBYTE_LITTLESUR · 7 unmodified lines
623	624	select BOOT_ELF32
624	625	select DMA_COHERENT
625	626	select HAVE_PATA_PLATFORM
626		− select NR_CPUS_DEFAULT_2
627	627	select SIBYTE_SB1250
628	628	select SWAP_IO_SPACE
629	629	select SYS_HAS_CPU_SB1
@@ -635,7 +635,6 @@ config SIBYTE_SENTOSA · 5 unmodified lines
635	635	bool "Sibyte BCM91250E-Sentosa"
636	636	select BOOT_ELF32
637	637	select DMA_COHERENT
638		− select NR_CPUS_DEFAULT_2
639	638	select SIBYTE_SB1250
640	639	select SWAP_IO_SPACE
641	640	select SYS_HAS_CPU_SB1
@@ -731,6 +730,7 @@ config CAVIUM_OCTEON_SOC · 89 unmodified lines
731	730	select USB_ARCH_HAS_OHCI
732	731	select USB_ARCH_HAS_EHCI
733	732	select HOLES_IN_ZONE
	733	+ select ARCH_REQUIRE_GPIOLIB
734	734	help
735	735	This option supports all of the Octeon reference boards from Cavium
736	736	Networks. It builds a kernel that dynamically determines the Octeon
@@ -1860,7 +1860,6 @@ config MIPS_MT_SMP · 1123 unmodified lines
1860	1860	select CPU_MIPSR2_IRQ_VI
1861	1861	select CPU_MIPSR2_IRQ_EI
1862	1862	select MIPS_MT
1863		− select NR_CPUS_DEFAULT_2
1864	1863	select SMP
1865	1864	select SYS_SUPPORTS_SCHED_SMT if SMP
1866	1865	select SYS_SUPPORTS_SMP
@@ -2171,12 +2170,6 @@ config SYS_SUPPORTS_MIPS_CMP · 304 unmodified lines
2171	2170	config SYS_SUPPORTS_SMP
2172	2171	bool
2173	2172
2174		−config NR_CPUS_DEFAULT_1
2175		− bool
2176		−
2177		−config NR_CPUS_DEFAULT_2
2178		− bool
2179		−
2180	2173	config NR_CPUS_DEFAULT_4
2181	2174	bool
2182	2175
@@ -2194,10 +2187,8 @@ config NR_CPUS_DEFAULT_64 · 11 unmodified lines
2194	2187
2195	2188	config NR_CPUS
2196	2189	int "Maximum number of CPUs (2-64)"
2197		− range 1 64 if NR_CPUS_DEFAULT_1
	2190	+ range 2 64
2198	2191	depends on SMP
2199		− default "1" if NR_CPUS_DEFAULT_1
2200		− default "2" if NR_CPUS_DEFAULT_2
2201	2192	default "4" if NR_CPUS_DEFAULT_4
2202	2193	default "8" if NR_CPUS_DEFAULT_8
2203	2194	default "16" if NR_CPUS_DEFAULT_16

arch/mips/Makefile+29−5

@@ -194,6 +194,8 @@ include $(srctree)/arch/mips/Kbuild.platforms · 193 unmodified lines
194	194	ifdef CONFIG_PHYSICAL_START
195	195	load-y = $(CONFIG_PHYSICAL_START)
196	196	endif
	197	+entry-y = 0x$(shell $(NM) vmlinux 2>/dev/null \
	198	+ \| grep "\bkernel_entry\b" \| cut -f1 -d \ )
197	199
198	200	cflags-y += -I$(srctree)/arch/mips/include/asm/mach-generic
199	201	drivers-$(CONFIG_PCI) += arch/mips/pci/
@@ -225,6 +227,9 @@ KBUILD_CFLAGS += $(cflags-y) · 25 unmodified lines
225	227	KBUILD_CPPFLAGS += -DVMLINUX_LOAD_ADDRESS=$(load-y)
226	228	KBUILD_CPPFLAGS += -DDATAOFFSET=$(if $(dataoffset-y),$(dataoffset-y),0)
227	229
	230	+bootvars-y = VMLINUX_LOAD_ADDRESS=$(load-y) \
	231	+ VMLINUX_ENTRY_ADDRESS=$(entry-y)
	232	+
228	233	LDFLAGS += -m $(ld-emul)
229	234
230	235	ifdef CONFIG_CC_STACKPROTECTOR
@@ -254,9 +259,25 @@ drivers-$(CONFIG_OPROFILE) += arch/mips/oprofile/ · 23 unmodified lines
254	259	# suspend and hibernation support
255	260	drivers-$(CONFIG_PM) += arch/mips/power/
256	261
	262	+# boot image targets (arch/mips/boot/)
	263	+boot-y := vmlinux.bin
	264	+boot-y += vmlinux.ecoff
	265	+boot-y += vmlinux.srec
	266	+ifeq ($(shell expr $(load-y) \< 0xffffffff80000000 2> /dev/null), 0)
	267	+boot-y += uImage
	268	+boot-y += uImage.gz
	269	+endif
	270	+
	271	+# compressed boot image targets (arch/mips/boot/compressed/)
	272	+bootz-y := vmlinuz
	273	+bootz-y += vmlinuz.bin
	274	+bootz-y += vmlinuz.ecoff
	275	+bootz-y += vmlinuz.srec
	276	+
257	277	ifdef CONFIG_LASAT
258	278	rom.bin rom.sw: vmlinux
259		− $(Q)$(MAKE) $(build)=arch/mips/lasat/image $@
	279	+ $(Q)$(MAKE) $(build)=arch/mips/lasat/image \
	280	+ $(bootvars-y) $@
260	281	endif
261	282
262	283	#
@@ -280,13 +301,14 @@ vmlinux.64: vmlinux · 17 unmodified lines
280	301	all: $(all-y)
281	302
282	303	# boot
283		−vmlinux.bin vmlinux.ecoff vmlinux.srec: $(vmlinux-32) FORCE
284		− $(Q)$(MAKE) $(build)=arch/mips/boot VMLINUX=$(vmlinux-32) arch/mips/boot/$@
	304	+$(boot-y): $(vmlinux-32) FORCE
	305	+ $(Q)$(MAKE) $(build)=arch/mips/boot VMLINUX=$(vmlinux-32) \
	306	+ $(bootvars-y) arch/mips/boot/$@
285	307
286	308	# boot/compressed
287		−vmlinuz vmlinuz.bin vmlinuz.ecoff vmlinuz.srec: $(vmlinux-32) FORCE
	309	+$(bootz-y): $(vmlinux-32) FORCE
288	310	$(Q)$(MAKE) $(build)=arch/mips/boot/compressed \
289		− VMLINUX_LOAD_ADDRESS=$(load-y) 32bit-bfd=$(32bit-bfd) $@
	311	+ $(bootvars-y) 32bit-bfd=$(32bit-bfd) $@
290	312
291	313
292	314	CLEAN_FILES += vmlinux.32 vmlinux.64
@@ -323,6 +345,8 @@ define archhelp · 30 unmodified lines
323	345	echo ' vmlinuz.ecoff - ECOFF zboot image'
324	346	echo ' vmlinuz.bin - Raw binary zboot image'
325	347	echo ' vmlinuz.srec - SREC zboot image'
	348	+ echo ' uImage - U-Boot image'
	349	+ echo ' uImage.gz - U-Boot image (gzip)'
326	350	echo
327	351	echo ' These will be default as appropriate for a configured platform.'
328	352	endef

arch/mips/ath79/clock.c+149−109

@@ -16,6 +16,7 @@ · 15 unmodified lines
16	16	#include <linux/init.h>
17	17	#include <linux/err.h>
18	18	#include <linux/clk.h>
	19	+#include <linux/clkdev.h>
19	20
20	21	#include <asm/div64.h>
21	22
@@ -31,92 +32,132 @@ struct clk { · 9 unmodified lines
31	32	unsigned long rate;
32	33	};
33	34
34		−static struct clk ath79_ref_clk;
35		−static struct clk ath79_cpu_clk;
36		−static struct clk ath79_ddr_clk;
37		−static struct clk ath79_ahb_clk;
38		−static struct clk ath79_wdt_clk;
39		−static struct clk ath79_uart_clk;
	35	+static void __init ath79_add_sys_clkdev(const char *id, unsigned long rate)
	36	+{
	37	+ struct clk *clk;
	38	+ int err;
	39	+
	40	+ clk = kzalloc(sizeof(*clk), GFP_KERNEL);
	41	+ if (!clk)
	42	+ panic("failed to allocate %s clock structure", id);
	43	+
	44	+ clk->rate = rate;
	45	+
	46	+ err = clk_register_clkdev(clk, id, NULL);
	47	+ if (err)
	48	+ panic("unable to register %s clock device", id);
	49	+}
40	50
41	51	static void __init ar71xx_clocks_init(void)
42	52	{
	53	+ unsigned long ref_rate;
	54	+ unsigned long cpu_rate;
	55	+ unsigned long ddr_rate;
	56	+ unsigned long ahb_rate;
43	57	u32 pll;
44	58	u32 freq;
45	59	u32 div;
46	60
47		− ath79_ref_clk.rate = AR71XX_BASE_FREQ;
	61	+ ref_rate = AR71XX_BASE_FREQ;
48	62
49	63	pll = ath79_pll_rr(AR71XX_PLL_REG_CPU_CONFIG);
50	64
51	65	div = ((pll >> AR71XX_PLL_DIV_SHIFT) & AR71XX_PLL_DIV_MASK) + 1;
52		− freq = div * ath79_ref_clk.rate;
	66	+ freq = div * ref_rate;
53	67
54	68	div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1;
55		− ath79_cpu_clk.rate = freq / div;
	69	+ cpu_rate = freq / div;
56	70
57	71	div = ((pll >> AR71XX_DDR_DIV_SHIFT) & AR71XX_DDR_DIV_MASK) + 1;
58		− ath79_ddr_clk.rate = freq / div;
	72	+ ddr_rate = freq / div;
59	73
60	74	div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2;
61		− ath79_ahb_clk.rate = ath79_cpu_clk.rate / div;
	75	+ ahb_rate = cpu_rate / div;
	76	+
	77	+ ath79_add_sys_clkdev("ref", ref_rate);
	78	+ ath79_add_sys_clkdev("cpu", cpu_rate);
	79	+ ath79_add_sys_clkdev("ddr", ddr_rate);
	80	+ ath79_add_sys_clkdev("ahb", ahb_rate);
62	81
63		− ath79_wdt_clk.rate = ath79_ahb_clk.rate;
64		− ath79_uart_clk.rate = ath79_ahb_clk.rate;
	82	+ clk_add_alias("wdt", NULL, "ahb", NULL);
	83	+ clk_add_alias("uart", NULL, "ahb", NULL);
65	84	}
66	85
67	86	static void __init ar724x_clocks_init(void)
68	87	{
	88	+ unsigned long ref_rate;
	89	+ unsigned long cpu_rate;
	90	+ unsigned long ddr_rate;
	91	+ unsigned long ahb_rate;
69	92	u32 pll;
70	93	u32 freq;
71	94	u32 div;
72	95
73		− ath79_ref_clk.rate = AR724X_BASE_FREQ;
	96	+ ref_rate = AR724X_BASE_FREQ;
74	97	pll = ath79_pll_rr(AR724X_PLL_REG_CPU_CONFIG);
75	98
76	99	div = ((pll >> AR724X_PLL_DIV_SHIFT) & AR724X_PLL_DIV_MASK);
77		− freq = div * ath79_ref_clk.rate;
	100	+ freq = div * ref_rate;
78	101
79	102	div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK);
80	103	freq *= div;
81	104
82		− ath79_cpu_clk.rate = freq;
	105	+ cpu_rate = freq;
83	106
84	107	div = ((pll >> AR724X_DDR_DIV_SHIFT) & AR724X_DDR_DIV_MASK) + 1;
85		− ath79_ddr_clk.rate = freq / div;
	108	+ ddr_rate = freq / div;
86	109
87	110	div = (((pll >> AR724X_AHB_DIV_SHIFT) & AR724X_AHB_DIV_MASK) + 1) * 2;
88		− ath79_ahb_clk.rate = ath79_cpu_clk.rate / div;
	111	+ ahb_rate = cpu_rate / div;
	112	+
	113	+ ath79_add_sys_clkdev("ref", ref_rate);
	114	+ ath79_add_sys_clkdev("cpu", cpu_rate);
	115	+ ath79_add_sys_clkdev("ddr", ddr_rate);
	116	+ ath79_add_sys_clkdev("ahb", ahb_rate);
89	117
90		− ath79_wdt_clk.rate = ath79_ahb_clk.rate;
91		− ath79_uart_clk.rate = ath79_ahb_clk.rate;
	118	+ clk_add_alias("wdt", NULL, "ahb", NULL);
	119	+ clk_add_alias("uart", NULL, "ahb", NULL);
92	120	}
93	121
94	122	static void __init ar913x_clocks_init(void)
95	123	{
	124	+ unsigned long ref_rate;
	125	+ unsigned long cpu_rate;
	126	+ unsigned long ddr_rate;
	127	+ unsigned long ahb_rate;
96	128	u32 pll;
97	129	u32 freq;
98	130	u32 div;
99	131
100		− ath79_ref_clk.rate = AR913X_BASE_FREQ;
	132	+ ref_rate = AR913X_BASE_FREQ;
101	133	pll = ath79_pll_rr(AR913X_PLL_REG_CPU_CONFIG);
102	134
103	135	div = ((pll >> AR913X_PLL_DIV_SHIFT) & AR913X_PLL_DIV_MASK);
104		− freq = div * ath79_ref_clk.rate;
	136	+ freq = div * ref_rate;
105	137
106		− ath79_cpu_clk.rate = freq;
	138	+ cpu_rate = freq;
107	139
108	140	div = ((pll >> AR913X_DDR_DIV_SHIFT) & AR913X_DDR_DIV_MASK) + 1;
109		− ath79_ddr_clk.rate = freq / div;
	141	+ ddr_rate = freq / div;
110	142
111	143	div = (((pll >> AR913X_AHB_DIV_SHIFT) & AR913X_AHB_DIV_MASK) + 1) * 2;
112		− ath79_ahb_clk.rate = ath79_cpu_clk.rate / div;
	144	+ ahb_rate = cpu_rate / div;
113	145
114		− ath79_wdt_clk.rate = ath79_ahb_clk.rate;
115		− ath79_uart_clk.rate = ath79_ahb_clk.rate;
	146	+ ath79_add_sys_clkdev("ref", ref_rate);
	147	+ ath79_add_sys_clkdev("cpu", cpu_rate);
	148	+ ath79_add_sys_clkdev("ddr", ddr_rate);
	149	+ ath79_add_sys_clkdev("ahb", ahb_rate);
	150	+
	151	+ clk_add_alias("wdt", NULL, "ahb", NULL);
	152	+ clk_add_alias("uart", NULL, "ahb", NULL);
116	153	}
117	154
118	155	static void __init ar933x_clocks_init(void)
119	156	{
	157	+ unsigned long ref_rate;
	158	+ unsigned long cpu_rate;
	159	+ unsigned long ddr_rate;
	160	+ unsigned long ahb_rate;
120	161	u32 clock_ctrl;
121	162	u32 cpu_config;
122	163	u32 freq;
@@ -124,21 +165,21 @@ static void __init ar933x_clocks_init(void) · 1 unmodified line
124	165
125	166	t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
126	167	if (t & AR933X_BOOTSTRAP_REF_CLK_40)
127		− ath79_ref_clk.rate = (40 * 1000 * 1000);
	168	+ ref_rate = (40 * 1000 * 1000);
128	169	else
129		− ath79_ref_clk.rate = (25 * 1000 * 1000);
	170	+ ref_rate = (25 * 1000 * 1000);
130	171
131	172	clock_ctrl = ath79_pll_rr(AR933X_PLL_CLOCK_CTRL_REG);
132	173	if (clock_ctrl & AR933X_PLL_CLOCK_CTRL_BYPASS) {
133		− ath79_cpu_clk.rate = ath79_ref_clk.rate;
134		− ath79_ahb_clk.rate = ath79_ref_clk.rate;
135		− ath79_ddr_clk.rate = ath79_ref_clk.rate;
	174	+ cpu_rate = ref_rate;
	175	+ ahb_rate = ref_rate;
	176	+ ddr_rate = ref_rate;
136	177	} else {
137	178	cpu_config = ath79_pll_rr(AR933X_PLL_CPU_CONFIG_REG);
138	179
139	180	t = (cpu_config >> AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
140	181	AR933X_PLL_CPU_CONFIG_REFDIV_MASK;
141		− freq = ath79_ref_clk.rate / t;
	182	+ freq = ref_rate / t;
142	183
143	184	t = (cpu_config >> AR933X_PLL_CPU_CONFIG_NINT_SHIFT) &
144	185	AR933X_PLL_CPU_CONFIG_NINT_MASK;
@@ -153,19 +194,24 @@ static void __init ar933x_clocks_init(void) · 8 unmodified lines
153	194
154	195	t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT) &
155	196	AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK) + 1;
156		− ath79_cpu_clk.rate = freq / t;
	197	+ cpu_rate = freq / t;
157	198
158	199	t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT) &
159	200	AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK) + 1;
160		− ath79_ddr_clk.rate = freq / t;
	201	+ ddr_rate = freq / t;
161	202
162	203	t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT) &
163	204	AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK) + 1;
164		− ath79_ahb_clk.rate = freq / t;
	205	+ ahb_rate = freq / t;
165	206	}
166	207
167		− ath79_wdt_clk.rate = ath79_ref_clk.rate;
168		− ath79_uart_clk.rate = ath79_ref_clk.rate;
	208	+ ath79_add_sys_clkdev("ref", ref_rate);
	209	+ ath79_add_sys_clkdev("cpu", cpu_rate);
	210	+ ath79_add_sys_clkdev("ddr", ddr_rate);
	211	+ ath79_add_sys_clkdev("ahb", ahb_rate);
	212	+
	213	+ clk_add_alias("wdt", NULL, "ahb", NULL);
	214	+ clk_add_alias("uart", NULL, "ref", NULL);
169	215	}
170	216
171	217	static u32 __init ar934x_get_pll_freq(u32 ref, u32 ref_div, u32 nint, u32 nfrac,
@@ -174,12 +220,12 @@ static u32 __init ar934x_get_pll_freq(u32 ref, u32 ref_div, u32 nint, u32 nfrac, · 2 unmodified lines
174	220	u64 t;
175	221	u32 ret;
176	222
177		− t = ath79_ref_clk.rate;
	223	+ t = ref;
178	224	t *= nint;
179	225	do_div(t, ref_div);
180	226	ret = t;
181	227
182		− t = ath79_ref_clk.rate;
	228	+ t = ref;
183	229	t *= nfrac;
184	230	do_div(t, ref_div * frac);
185	231	ret += t;
@@ -190,6 +236,10 @@ static u32 __init ar934x_get_pll_freq(u32 ref, u32 ref_div, u32 nint, u32 nfrac, · 4 unmodified lines
190	236
191	237	static void __init ar934x_clocks_init(void)
192	238	{
	239	+ unsigned long ref_rate;
	240	+ unsigned long cpu_rate;
	241	+ unsigned long ddr_rate;
	242	+ unsigned long ahb_rate;
193	243	u32 pll, out_div, ref_div, nint, nfrac, frac, clk_ctrl, postdiv;
194	244	u32 cpu_pll, ddr_pll;
195	245	u32 bootstrap;
@@ -199,9 +249,9 @@ static void __init ar934x_clocks_init(void) · 3 unmodified lines
199	249
200	250	bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP);
201	251	if (bootstrap & AR934X_BOOTSTRAP_REF_CLK_40)
202		− ath79_ref_clk.rate = 40 * 1000 * 1000;
	252	+ ref_rate = 40 * 1000 * 1000;
203	253	else
204		− ath79_ref_clk.rate = 25 * 1000 * 1000;
	254	+ ref_rate = 25 * 1000 * 1000;
205	255
206	256	pll = __raw_readl(dpll_base + AR934X_SRIF_CPU_DPLL2_REG);
207	257	if (pll & AR934X_SRIF_DPLL2_LOCAL_PLL) {
@@ -227,7 +277,7 @@ static void __init ar934x_clocks_init(void) · 19 unmodified lines
227	277	frac = 1 << 6;
228	278	}
229	279
230		− cpu_pll = ar934x_get_pll_freq(ath79_ref_clk.rate, ref_div, nint,
	280	+ cpu_pll = ar934x_get_pll_freq(ref_rate, ref_div, nint,
231	281	nfrac, frac, out_div);
232	282
233	283	pll = __raw_readl(dpll_base + AR934X_SRIF_DDR_DPLL2_REG);
@@ -254,7 +304,7 @@ static void __init ar934x_clocks_init(void) · 20 unmodified lines
254	304	frac = 1 << 10;
255	305	}
256	306
257		− ddr_pll = ar934x_get_pll_freq(ath79_ref_clk.rate, ref_div, nint,
	307	+ ddr_pll = ar934x_get_pll_freq(ref_rate, ref_div, nint,
258	308	nfrac, frac, out_div);
259	309
260	310	clk_ctrl = ath79_pll_rr(AR934X_PLL_CPU_DDR_CLK_CTRL_REG);
@@ -263,49 +313,58 @@ static void __init ar934x_clocks_init(void) · 2 unmodified lines
263	313	AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK;
264	314
265	315	if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS)
266		− ath79_cpu_clk.rate = ath79_ref_clk.rate;
	316	+ cpu_rate = ref_rate;
267	317	else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL)
268		− ath79_cpu_clk.rate = cpu_pll / (postdiv + 1);
	318	+ cpu_rate = cpu_pll / (postdiv + 1);
269	319	else
270		− ath79_cpu_clk.rate = ddr_pll / (postdiv + 1);
	320	+ cpu_rate = ddr_pll / (postdiv + 1);
271	321
272	322	postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT) &
273	323	AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK;
274	324
275	325	if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS)
276		− ath79_ddr_clk.rate = ath79_ref_clk.rate;
	326	+ ddr_rate = ref_rate;
277	327	else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL)
278		− ath79_ddr_clk.rate = ddr_pll / (postdiv + 1);
	328	+ ddr_rate = ddr_pll / (postdiv + 1);
279	329	else
280		− ath79_ddr_clk.rate = cpu_pll / (postdiv + 1);
	330	+ ddr_rate = cpu_pll / (postdiv + 1);
281	331
282	332	postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT) &
283	333	AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK;
284	334
285	335	if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS)
286		− ath79_ahb_clk.rate = ath79_ref_clk.rate;
	336	+ ahb_rate = ref_rate;
287	337	else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL)
288		− ath79_ahb_clk.rate = ddr_pll / (postdiv + 1);
	338	+ ahb_rate = ddr_pll / (postdiv + 1);
289	339	else
290		− ath79_ahb_clk.rate = cpu_pll / (postdiv + 1);
	340	+ ahb_rate = cpu_pll / (postdiv + 1);
	341	+
	342	+ ath79_add_sys_clkdev("ref", ref_rate);
	343	+ ath79_add_sys_clkdev("cpu", cpu_rate);
	344	+ ath79_add_sys_clkdev("ddr", ddr_rate);
	345	+ ath79_add_sys_clkdev("ahb", ahb_rate);
291	346
292		− ath79_wdt_clk.rate = ath79_ref_clk.rate;
293		− ath79_uart_clk.rate = ath79_ref_clk.rate;
	347	+ clk_add_alias("wdt", NULL, "ref", NULL);
	348	+ clk_add_alias("uart", NULL, "ref", NULL);
294	349
295	350	iounmap(dpll_base);
296	351	}
297	352
298	353	static void __init qca955x_clocks_init(void)
299	354	{
	355	+ unsigned long ref_rate;
	356	+ unsigned long cpu_rate;
	357	+ unsigned long ddr_rate;
	358	+ unsigned long ahb_rate;
300	359	u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv;
301	360	u32 cpu_pll, ddr_pll;
302	361	u32 bootstrap;
303	362
304	363	bootstrap = ath79_reset_rr(QCA955X_RESET_REG_BOOTSTRAP);
305	364	if (bootstrap & QCA955X_BOOTSTRAP_REF_CLK_40)
306		− ath79_ref_clk.rate = 40 * 1000 * 1000;
	365	+ ref_rate = 40 * 1000 * 1000;
307	366	else
308		− ath79_ref_clk.rate = 25 * 1000 * 1000;
	367	+ ref_rate = 25 * 1000 * 1000;
309	368
310	369	pll = ath79_pll_rr(QCA955X_PLL_CPU_CONFIG_REG);
311	370	out_div = (pll >> QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
@@ -317,8 +376,8 @@ static void __init qca955x_clocks_init(void) · 5 unmodified lines
317	376	frac = (pll >> QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
318	377	QCA955X_PLL_CPU_CONFIG_NFRAC_MASK;
319	378
320		− cpu_pll = nint * ath79_ref_clk.rate / ref_div;
321		− cpu_pll += frac * ath79_ref_clk.rate / (ref_div * (1 << 6));
	379	+ cpu_pll = nint * ref_rate / ref_div;
	380	+ cpu_pll += frac * ref_rate / (ref_div * (1 << 6));
322	381	cpu_pll /= (1 << out_div);
323	382
324	383	pll = ath79_pll_rr(QCA955X_PLL_DDR_CONFIG_REG);
@@ -331,8 +390,8 @@ static void __init qca955x_clocks_init(void) · 6 unmodified lines
331	390	frac = (pll >> QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
332	391	QCA955X_PLL_DDR_CONFIG_NFRAC_MASK;
333	392
334		− ddr_pll = nint * ath79_ref_clk.rate / ref_div;
335		− ddr_pll += frac * ath79_ref_clk.rate / (ref_div * (1 << 10));
	393	+ ddr_pll = nint * ref_rate / ref_div;
	394	+ ddr_pll += frac * ref_rate / (ref_div * (1 << 10));
336	395	ddr_pll /= (1 << out_div);
337	396
338	397	clk_ctrl = ath79_pll_rr(QCA955X_PLL_CLK_CTRL_REG);
@@ -341,34 +400,39 @@ static void __init qca955x_clocks_init(void) · 2 unmodified lines
341	400	QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
342	401
343	402	if (clk_ctrl & QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS)
344		− ath79_cpu_clk.rate = ath79_ref_clk.rate;
	403	+ cpu_rate = ref_rate;
345	404	else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL)
346		− ath79_cpu_clk.rate = ddr_pll / (postdiv + 1);
	405	+ cpu_rate = ddr_pll / (postdiv + 1);
347	406	else
348		− ath79_cpu_clk.rate = cpu_pll / (postdiv + 1);
	407	+ cpu_rate = cpu_pll / (postdiv + 1);
349	408
350	409	postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) &
351	410	QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_MASK;
352	411
353	412	if (clk_ctrl & QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS)
354		− ath79_ddr_clk.rate = ath79_ref_clk.rate;
	413	+ ddr_rate = ref_rate;
355	414	else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL)
356		− ath79_ddr_clk.rate = cpu_pll / (postdiv + 1);
	415	+ ddr_rate = cpu_pll / (postdiv + 1);
357	416	else
358		− ath79_ddr_clk.rate = ddr_pll / (postdiv + 1);
	417	+ ddr_rate = ddr_pll / (postdiv + 1);
359	418
360	419	postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) &
361	420	QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_MASK;
362	421
363	422	if (clk_ctrl & QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
364		− ath79_ahb_clk.rate = ath79_ref_clk.rate;
	423	+ ahb_rate = ref_rate;
365	424	else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL)
366		− ath79_ahb_clk.rate = ddr_pll / (postdiv + 1);
	425	+ ahb_rate = ddr_pll / (postdiv + 1);
367	426	else
368		− ath79_ahb_clk.rate = cpu_pll / (postdiv + 1);
	427	+ ahb_rate = cpu_pll / (postdiv + 1);
369	428
370		− ath79_wdt_clk.rate = ath79_ref_clk.rate;
371		− ath79_uart_clk.rate = ath79_ref_clk.rate;
	429	+ ath79_add_sys_clkdev("ref", ref_rate);
	430	+ ath79_add_sys_clkdev("cpu", cpu_rate);
	431	+ ath79_add_sys_clkdev("ddr", ddr_rate);
	432	+ ath79_add_sys_clkdev("ahb", ahb_rate);
	433	+
	434	+ clk_add_alias("wdt", NULL, "ref", NULL);
	435	+ clk_add_alias("uart", NULL, "ref", NULL);
372	436	}
373	437
374	438	void __init ath79_clocks_init(void)
@@ -387,46 +451,27 @@ void __init ath79_clocks_init(void) · 12 unmodified lines
387	451	qca955x_clocks_init();
388	452	else
389	453	BUG();
390		−
391		− pr_info("Clocks: CPU:%lu.%03luMHz, DDR:%lu.%03luMHz, AHB:%lu.%03luMHz, "
392		− "Ref:%lu.%03luMHz",
393		− ath79_cpu_clk.rate / 1000000,
394		− (ath79_cpu_clk.rate / 1000) % 1000,
395		− ath79_ddr_clk.rate / 1000000,
396		− (ath79_ddr_clk.rate / 1000) % 1000,
397		− ath79_ahb_clk.rate / 1000000,
398		− (ath79_ahb_clk.rate / 1000) % 1000,
399		− ath79_ref_clk.rate / 1000000,
400		− (ath79_ref_clk.rate / 1000) % 1000);
401	454	}
402	455
403		−/*
404		− * Linux clock API
405		− */
406		−struct clk clk_get(struct device dev, const char *id)
	456	+unsigned long __init
	457	+ath79_get_sys_clk_rate(const char *id)
407	458	{
408		− if (!strcmp(id, "ref"))
409		− return &ath79_ref_clk;
410		−
411		− if (!strcmp(id, "cpu"))
412		− return &ath79_cpu_clk;
413		−
414		− if (!strcmp(id, "ddr"))
415		− return &ath79_ddr_clk;
416		−
417		− if (!strcmp(id, "ahb"))
418		− return &ath79_ahb_clk;
	459	+ struct clk *clk;
	460	+ unsigned long rate;
419	461
420		− if (!strcmp(id, "wdt"))
421		− return &ath79_wdt_clk;
	462	+ clk = clk_get(NULL, id);
	463	+ if (IS_ERR(clk))
	464	+ panic("unable to get %s clock, err=%d", id, (int) PTR_ERR(clk));
422	465
423		− if (!strcmp(id, "uart"))
424		− return &ath79_uart_clk;
	466	+ rate = clk_get_rate(clk);
	467	+ clk_put(clk);
425	468
426		− return ERR_PTR(-ENOENT);
	469	+ return rate;
427	470	}
428		−EXPORT_SYMBOL(clk_get);
429	471
	472	+/*
	473	+ * Linux clock API
	474	+ */
430	475	int clk_enable(struct clk *clk)
431	476	{
432	477	return 0;
@@ -443,8 +488,3 @@ unsigned long clk_get_rate(struct clk *clk) · 10 unmodified lines
443	488	return clk->rate;
444	489	}
445	490	EXPORT_SYMBOL(clk_get_rate);
446		−
447		−void clk_put(struct clk *clk)
448		−{
449		−}
450		−EXPORT_SYMBOL(clk_put);

arch/mips/ath79/common.h+2−0

@@ -21,6 +21,8 @@ · 20 unmodified lines
21	21	#define ATH79_MEM_SIZE_MAX (128 * 1024 * 1024)
22	22
23	23	void ath79_clocks_init(void);
	24	+unsigned long ath79_get_sys_clk_rate(const char *id);
	25	+
24	26	void ath79_ddr_wb_flush(unsigned int reg);
25	27
26	28	void ath79_gpio_function_enable(u32 mask);

arch/mips/ath79/dev-common.c+4−6

@@ -81,21 +81,19 @@ static struct platform_device ar933x_uart_device = { · 80 unmodified lines
81	81
82	82	void __init ath79_register_uart(void)
83	83	{
84		− struct clk *clk;
	84	+ unsigned long uart_clk_rate;
85	85
86		− clk = clk_get(NULL, "uart");
87		− if (IS_ERR(clk))
88		− panic("unable to get UART clock, err=%ld", PTR_ERR(clk));
	86	+ uart_clk_rate = ath79_get_sys_clk_rate("uart");
89	87
90	88	if (soc_is_ar71xx() \|\|
91	89	soc_is_ar724x() \|\|
92	90	soc_is_ar913x() \|\|
93	91	soc_is_ar934x() \|\|
94	92	soc_is_qca955x()) {
95		− ath79_uart_data[0].uartclk = clk_get_rate(clk);
	93	+ ath79_uart_data[0].uartclk = uart_clk_rate;
96	94	platform_device_register(&ath79_uart_device);
97	95	} else if (soc_is_ar933x()) {
98		− ar933x_uart_data.uartclk = clk_get_rate(clk);
	96	+ ar933x_uart_data.uartclk = uart_clk_rate;
99	97	platform_device_register(&ar933x_uart_device);
100	98	} else {
101	99	BUG();

arch/mips/ath79/setup.c+17−6

@@ -200,7 +200,6 @@ void __init plat_mem_setup(void) · 199 unmodified lines
200	200
201	201	ath79_detect_sys_type();
202	202	detect_memory_region(0, ATH79_MEM_SIZE_MIN, ATH79_MEM_SIZE_MAX);
203		− ath79_clocks_init();
204	203
205	204	_machine_restart = ath79_restart;
206	205	_machine_halt = ath79_halt;
@@ -209,13 +208,25 @@ void __init plat_mem_setup(void) · 2 unmodified lines
209	208
210	209	void __init plat_time_init(void)
211	210	{
212		− struct clk *clk;
	211	+ unsigned long cpu_clk_rate;
	212	+ unsigned long ahb_clk_rate;
	213	+ unsigned long ddr_clk_rate;
	214	+ unsigned long ref_clk_rate;
	215	+
	216	+ ath79_clocks_init();
	217	+
	218	+ cpu_clk_rate = ath79_get_sys_clk_rate("cpu");
	219	+ ahb_clk_rate = ath79_get_sys_clk_rate("ahb");
	220	+ ddr_clk_rate = ath79_get_sys_clk_rate("ddr");
	221	+ ref_clk_rate = ath79_get_sys_clk_rate("ref");
213	222
214		− clk = clk_get(NULL, "cpu");
215		− if (IS_ERR(clk))
216		− panic("unable to get CPU clock, err=%ld", PTR_ERR(clk));
	223	+ pr_info("Clocks: CPU:%lu.%03luMHz, DDR:%lu.%03luMHz, AHB:%lu.%03luMHz, Ref:%lu.%03luMHz",
	224	+ cpu_clk_rate / 1000000, (cpu_clk_rate / 1000) % 1000,
	225	+ ddr_clk_rate / 1000000, (ddr_clk_rate / 1000) % 1000,
	226	+ ahb_clk_rate / 1000000, (ahb_clk_rate / 1000) % 1000,
	227	+ ref_clk_rate / 1000000, (ref_clk_rate / 1000) % 1000);
217	228
218		− mips_hpt_frequency = clk_get_rate(clk) / 2;
	229	+ mips_hpt_frequency = cpu_clk_rate / 2;
219	230	}
220	231
221	232	static int __init ath79_setup(void)

arch/mips/boot/.gitignore+1−0

@@ -4,3 +4,4 @@ vmlinux.* · 3 unmodified lines
4	4	zImage
5	5	zImage.tmp
6	6	calc_vmlinuz_load_addr
	7	+uImage

arch/mips/boot/Makefile+15−0

@@ -40,3 +40,18 @@ quiet_cmd_srec = OBJCOPY $@ · 39 unmodified lines
40	40	cmd_srec = $(OBJCOPY) -S -O srec $(strip-flags) $(VMLINUX) $@
41	41	$(obj)/vmlinux.srec: $(VMLINUX) FORCE
42	42	$(call if_changed,srec)
	43	+
	44	+UIMAGE_LOADADDR = $(VMLINUX_LOAD_ADDRESS)
	45	+UIMAGE_ENTRYADDR = $(VMLINUX_ENTRY_ADDRESS)
	46	+
	47	+$(obj)/vmlinux.bin.gz: $(obj)/vmlinux.bin FORCE
	48	+ $(call if_changed,gzip)
	49	+
	50	+targets += uImage.gz
	51	+$(obj)/uImage.gz: $(obj)/vmlinux.bin.gz FORCE
	52	+ $(call if_changed,uimage,gzip)
	53	+
	54	+targets += uImage
	55	+$(obj)/uImage: $(obj)/uImage.gz FORCE
	56	+ @ln -sf $(notdir $<) $@
	57	+ @echo ' Image $@ is ready'

arch/mips/boot/compressed/Makefile+1−1

@@ -25,7 +25,7 @@ KBUILD_CFLAGS := $(LINUXINCLUDE) $(KBUILD_CFLAGS) -D__KERNEL__ \ · 24 unmodified lines
25	25
26	26	KBUILD_AFLAGS := $(LINUXINCLUDE) $(KBUILD_AFLAGS) -D__ASSEMBLY__ \
27	27	-DBOOT_HEAP_SIZE=$(BOOT_HEAP_SIZE) \
28		− -DKERNEL_ENTRY=0x$(shell $(NM) $(objtree)/$(KBUILD_IMAGE) 2>/dev/null \| grep " kernel_entry" \| cut -f1 -d \ )
	28	+ -DKERNEL_ENTRY=$(VMLINUX_ENTRY_ADDRESS)
29	29
30	30	targets := head.o decompress.o dbg.o uart-16550.o uart-alchemy.o
31	31

arch/mips/boot/dts/include/dt-bindings+1−0

@@ -0,0 +1 @@
	1	+../../../../../include/dt-bindings

arch/mips/cavium-octeon/octeon-irq.c+1−1

@@ -1776,7 +1776,7 @@ asmlinkage void plat_irq_dispatch(void) · 1775 unmodified lines
1776	1776
1777	1777	#ifdef CONFIG_HOTPLUG_CPU
1778	1778
1779		−void fixup_irqs(void)
	1779	+void octeon_fixup_irqs(void)
1780	1780	{
1781	1781	irq_cpu_offline();
1782	1782	}

arch/mips/cavium-octeon/setup.c+28−0

@@ -8,6 +8,7 @@ · 7 unmodified lines
8	8	* written by Ralf Baechle <ralf@linux-mips.org>
9	9	*/
10	10	#include <linux/compiler.h>
	11	+#include <linux/vmalloc.h>
11	12	#include <linux/init.h>
12	13	#include <linux/kernel.h>
13	14	#include <linux/console.h>
@@ -1139,3 +1140,30 @@ static int __init edac_devinit(void) · 1125 unmodified lines
1139	1140	return err;
1140	1141	}
1141	1142	device_initcall(edac_devinit);
	1143	+
	1144	+static void __initdata *octeon_dummy_iospace;
	1145	+
	1146	+static int __init octeon_no_pci_init(void)
	1147	+{
	1148	+ /*
	1149	+ * Initially assume there is no PCI. The PCI/PCIe platform code will
	1150	+ * later re-initialize these to correct values if they are present.
	1151	+ */
	1152	+ octeon_dummy_iospace = vzalloc(IO_SPACE_LIMIT);
	1153	+ set_io_port_base((unsigned long)octeon_dummy_iospace);
	1154	+ ioport_resource.start = MAX_RESOURCE;
	1155	+ ioport_resource.end = 0;
	1156	+ return 0;
	1157	+}
	1158	+core_initcall(octeon_no_pci_init);
	1159	+
	1160	+static int __init octeon_no_pci_release(void)
	1161	+{
	1162	+ /*
	1163	+ * Release the allocated memory if a real IO space is there.
	1164	+ */
	1165	+ if ((unsigned long)octeon_dummy_iospace != mips_io_port_base)
	1166	+ vfree(octeon_dummy_iospace);
	1167	+ return 0;
	1168	+}
	1169	+late_initcall(octeon_no_pci_release);

arch/mips/cavium-octeon/smp.c+1−3

@@ -255,8 +255,6 @@ static void octeon_cpus_done(void) · 254 unmodified lines
255	255	/* State of each CPU. */
256	256	DEFINE_PER_CPU(int, cpu_state);
257	257
258		−extern void fixup_irqs(void);
259		−
260	258	static int octeon_cpu_disable(void)
261	259	{
262	260	unsigned int cpu = smp_processor_id();
@@ -267,7 +265,7 @@ static int octeon_cpu_disable(void) · 4 unmodified lines
267	265	set_cpu_online(cpu, false);
268	266	cpu_clear(cpu, cpu_callin_map);
269	267	local_irq_disable();
270		− fixup_irqs();
	268	+ octeon_fixup_irqs();
271	269	local_irq_enable();
272	270
273	271	flush_cache_all();

arch/mips/configs/xway_defconfig+159−0

@@ -0,0 +1,159 @@
	1	+CONFIG_LANTIQ=y
	2	+CONFIG_XRX200_PHY_FW=y
	3	+CONFIG_CPU_MIPS32_R2=y
	4	+# CONFIG_COMPACTION is not set
	5	+# CONFIG_CROSS_MEMORY_ATTACH is not set
	6	+CONFIG_HZ_100=y
	7	+# CONFIG_SECCOMP is not set
	8	+# CONFIG_LOCALVERSION_AUTO is not set
	9	+CONFIG_SYSVIPC=y
	10	+CONFIG_HIGH_RES_TIMERS=y
	11	+CONFIG_BLK_DEV_INITRD=y
	12	+# CONFIG_RD_GZIP is not set
	13	+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
	14	+CONFIG_KALLSYMS_ALL=y
	15	+# CONFIG_AIO is not set
	16	+CONFIG_EMBEDDED=y
	17	+# CONFIG_VM_EVENT_COUNTERS is not set
	18	+# CONFIG_SLUB_DEBUG is not set
	19	+# CONFIG_COMPAT_BRK is not set
	20	+CONFIG_MODULES=y
	21	+CONFIG_MODULE_UNLOAD=y
	22	+# CONFIG_BLK_DEV_BSG is not set
	23	+CONFIG_PARTITION_ADVANCED=y
	24	+# CONFIG_IOSCHED_CFQ is not set
	25	+# CONFIG_COREDUMP is not set
	26	+# CONFIG_SUSPEND is not set
	27	+CONFIG_NET=y
	28	+CONFIG_PACKET=y
	29	+CONFIG_UNIX=y
	30	+CONFIG_INET=y
	31	+CONFIG_IP_MULTICAST=y
	32	+CONFIG_IP_ADVANCED_ROUTER=y
	33	+CONFIG_IP_MULTIPLE_TABLES=y
	34	+CONFIG_IP_ROUTE_MULTIPATH=y
	35	+CONFIG_IP_ROUTE_VERBOSE=y
	36	+CONFIG_IP_MROUTE=y
	37	+CONFIG_IP_MROUTE_MULTIPLE_TABLES=y
	38	+CONFIG_ARPD=y
	39	+CONFIG_SYN_COOKIES=y
	40	+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
	41	+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
	42	+# CONFIG_INET_XFRM_MODE_BEET is not set
	43	+# CONFIG_INET_LRO is not set
	44	+# CONFIG_INET_DIAG is not set
	45	+CONFIG_TCP_CONG_ADVANCED=y
	46	+# CONFIG_TCP_CONG_BIC is not set
	47	+# CONFIG_TCP_CONG_WESTWOOD is not set
	48	+# CONFIG_TCP_CONG_HTCP is not set
	49	+# CONFIG_IPV6 is not set
	50	+CONFIG_NETFILTER=y
	51	+# CONFIG_BRIDGE_NETFILTER is not set
	52	+CONFIG_NF_CONNTRACK=m
	53	+CONFIG_NF_CONNTRACK_FTP=m
	54	+CONFIG_NF_CONNTRACK_IRC=m
	55	+CONFIG_NETFILTER_XT_TARGET_CT=m
	56	+CONFIG_NETFILTER_XT_TARGET_LOG=m
	57	+CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
	58	+CONFIG_NETFILTER_XT_MATCH_COMMENT=m
	59	+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
	60	+CONFIG_NETFILTER_XT_MATCH_LIMIT=m
	61	+CONFIG_NETFILTER_XT_MATCH_MAC=m
	62	+CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
	63	+CONFIG_NETFILTER_XT_MATCH_STATE=m
	64	+CONFIG_NF_CONNTRACK_IPV4=m
	65	+# CONFIG_NF_CONNTRACK_PROC_COMPAT is not set
	66	+CONFIG_IP_NF_IPTABLES=m
	67	+CONFIG_IP_NF_FILTER=m
	68	+CONFIG_IP_NF_TARGET_REJECT=m
	69	+CONFIG_IP_NF_MANGLE=m
	70	+CONFIG_IP_NF_RAW=m
	71	+CONFIG_BRIDGE=y
	72	+# CONFIG_BRIDGE_IGMP_SNOOPING is not set
	73	+CONFIG_VLAN_8021Q=y
	74	+CONFIG_NET_SCHED=y
	75	+CONFIG_HAMRADIO=y
	76	+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
	77	+# CONFIG_FIRMWARE_IN_KERNEL is not set
	78	+CONFIG_MTD=y
	79	+CONFIG_MTD_CMDLINE_PARTS=y
	80	+CONFIG_MTD_BLOCK=y
	81	+CONFIG_MTD_CFI=y
	82	+CONFIG_MTD_CFI_AMDSTD=y
	83	+CONFIG_MTD_COMPLEX_MAPPINGS=y
	84	+CONFIG_MTD_PHYSMAP=y
	85	+CONFIG_MTD_PHYSMAP_OF=y
	86	+CONFIG_MTD_LANTIQ=y
	87	+CONFIG_EEPROM_93CX6=m
	88	+CONFIG_SCSI=y
	89	+CONFIG_BLK_DEV_SD=y
	90	+CONFIG_NETDEVICES=y
	91	+CONFIG_LANTIQ_ETOP=y
	92	+# CONFIG_NET_VENDOR_WIZNET is not set
	93	+CONFIG_PHYLIB=y
	94	+CONFIG_PPP=m
	95	+CONFIG_PPP_FILTER=y
	96	+CONFIG_PPP_MULTILINK=y
	97	+CONFIG_PPPOE=m
	98	+CONFIG_PPP_ASYNC=m
	99	+CONFIG_ISDN=y
	100	+CONFIG_INPUT=m
	101	+CONFIG_INPUT_POLLDEV=m
	102	+# CONFIG_INPUT_MOUSEDEV is not set
	103	+# CONFIG_KEYBOARD_ATKBD is not set
	104	+# CONFIG_INPUT_MOUSE is not set
	105	+CONFIG_INPUT_MISC=y
	106	+# CONFIG_SERIO is not set
	107	+# CONFIG_VT is not set
	108	+# CONFIG_LEGACY_PTYS is not set
	109	+# CONFIG_DEVKMEM is not set
	110	+CONFIG_SERIAL_8250=y
	111	+CONFIG_SERIAL_8250_CONSOLE=y
	112	+CONFIG_SERIAL_8250_RUNTIME_UARTS=2
	113	+CONFIG_SERIAL_OF_PLATFORM=y
	114	+CONFIG_SPI=y
	115	+CONFIG_GPIO_MM_LANTIQ=y
	116	+CONFIG_GPIO_STP_XWAY=y
	117	+# CONFIG_HWMON is not set
	118	+CONFIG_WATCHDOG=y
	119	+# CONFIG_HID is not set
	120	+# CONFIG_USB_HID is not set
	121	+CONFIG_USB=y
	122	+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
	123	+CONFIG_USB_STORAGE=y
	124	+CONFIG_USB_STORAGE_DEBUG=y
	125	+CONFIG_NEW_LEDS=y
	126	+CONFIG_LEDS_CLASS=y
	127	+CONFIG_LEDS_TRIGGERS=y
	128	+CONFIG_LEDS_TRIGGER_TIMER=y
	129	+CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
	130	+CONFIG_STAGING=y
	131	+# CONFIG_IOMMU_SUPPORT is not set
	132	+# CONFIG_DNOTIFY is not set
	133	+# CONFIG_PROC_PAGE_MONITOR is not set
	134	+CONFIG_TMPFS=y
	135	+CONFIG_TMPFS_XATTR=y
	136	+CONFIG_JFFS2_FS=y
	137	+CONFIG_JFFS2_SUMMARY=y
	138	+CONFIG_JFFS2_FS_XATTR=y
	139	+# CONFIG_JFFS2_FS_POSIX_ACL is not set
	140	+# CONFIG_JFFS2_FS_SECURITY is not set
	141	+CONFIG_JFFS2_COMPRESSION_OPTIONS=y
	142	+# CONFIG_JFFS2_ZLIB is not set
	143	+CONFIG_SQUASHFS=y
	144	+# CONFIG_SQUASHFS_ZLIB is not set
	145	+CONFIG_SQUASHFS_XZ=y
	146	+CONFIG_PRINTK_TIME=y
	147	+# CONFIG_ENABLE_MUST_CHECK is not set
	148	+CONFIG_STRIP_ASM_SYMS=y
	149	+CONFIG_DEBUG_FS=y
	150	+CONFIG_MAGIC_SYSRQ=y
	151	+# CONFIG_SCHED_DEBUG is not set
	152	+# CONFIG_FTRACE is not set
	153	+CONFIG_CMDLINE_BOOL=y
	154	+CONFIG_CRYPTO_MANAGER=m
	155	+CONFIG_CRYPTO_ARC4=m
	156	+# CONFIG_CRYPTO_ANSI_CPRNG is not set
	157	+CONFIG_CRC_ITU_T=m
	158	+CONFIG_CRC32_SARWATE=y
	159	+CONFIG_AVERAGE=y

arch/mips/dec/time.c+3−2

@@ -126,12 +126,13 @@ int rtc_mips_set_mmss(unsigned long nowtime) · 125 unmodified lines
126	126	void __init plat_time_init(void)
127	127	{
128	128	u32 start, end;
129		− int i = HZ / 10;
	129	+ int i = HZ / 8;
130	130
131	131	/* Set up the rate of periodic DS1287 interrupts. */
132	132	ds1287_set_base_clock(HZ);
133	133
134	134	if (cpu_has_counter) {
	135	+ ds1287_timer_state();
135	136	while (!ds1287_timer_state())
136	137	;
137	138
@@ -143,7 +144,7 @@ void __init plat_time_init(void) · 5 unmodified lines
143	144
144	145	end = read_c0_count();
145	146
146		− mips_hpt_frequency = (end - start) * 10;
	147	+ mips_hpt_frequency = (end - start) * 8;
147	148	printk(KERN_INFO "MIPS counter frequency %dHz\n",
148	149	mips_hpt_frequency);
149	150	} else if (IOASIC)

arch/mips/include/asm/Kbuild+13−0

@@ -1,2 +1,15 @@
1	1	# MIPS headers
	2	+generic-y += cputime.h
	3	+generic-y += current.h
	4	+generic-y += emergency-restart.h
	5	+generic-y += local64.h
	6	+generic-y += mutex.h
	7	+generic-y += parport.h
	8	+generic-y += percpu.h
	9	+generic-y += scatterlist.h
	10	+generic-y += sections.h
	11	+generic-y += segment.h
	12	+generic-y += serial.h
2	13	generic-y += trace_clock.h
	14	+generic-y += ucontext.h
	15	+generic-y += xor.h

arch/mips/include/asm/bmips.h+22−33

@@ -65,44 +65,33 @@ static inline unsigned long bmips_read_zscm_reg(unsigned int offset) · 64 unmodified lines
65	65	{
66	66	unsigned long ret;
67	67
68		− __asm__ __volatile__(
69		− ".set push\n"
70		− ".set noreorder\n"
71		− "cache %1, 0(%2)\n"
72		− "sync\n"
73		− "_ssnop\n"
74		− "_ssnop\n"
75		− "_ssnop\n"
76		− "_ssnop\n"
77		− "_ssnop\n"
78		− "_ssnop\n"
79		− "_ssnop\n"
80		− "mfc0 %0, $28, 3\n"
81		− "_ssnop\n"
82		− ".set pop\n"
83		− : "=&r" (ret)
84		− : "i" (Index_Load_Tag_S), "r" (ZSCM_REG_BASE + offset)
85		− : "memory");
	68	+ barrier();
	69	+ cache_op(Index_Load_Tag_S, ZSCM_REG_BASE + offset);
	70	+ __sync();
	71	+ _ssnop();
	72	+ _ssnop();
	73	+ _ssnop();
	74	+ _ssnop();
	75	+ _ssnop();
	76	+ _ssnop();
	77	+ _ssnop();
	78	+ ret = read_c0_ddatalo();
	79	+ _ssnop();
	80	+
86	81	return ret;
87	82	}
88	83
89	84	static inline void bmips_write_zscm_reg(unsigned int offset, unsigned long data)
90	85	{
91		− __asm__ __volatile__(
92		− ".set push\n"
93		− ".set noreorder\n"
94		− "mtc0 %0, $28, 3\n"
95		− "_ssnop\n"
96		− "_ssnop\n"
97		− "_ssnop\n"
98		− "cache %1, 0(%2)\n"
99		− "_ssnop\n"
100		− "_ssnop\n"
101		− "_ssnop\n"
102		− : /* no outputs */
103		− : "r" (data),
104		− "i" (Index_Store_Tag_S), "r" (ZSCM_REG_BASE + offset)
105		− : "memory");
	86	+ write_c0_ddatalo(data);
	87	+ _ssnop();
	88	+ _ssnop();
	89	+ _ssnop();
	90	+ cache_op(Index_Store_Tag_S, ZSCM_REG_BASE + offset);
	91	+ _ssnop();
	92	+ _ssnop();
	93	+ _ssnop();
	94	+ barrier();
106	95	}
107	96
108	97	#endif /* !defined(__ASSEMBLY__) */

arch/mips/include/asm/cpu.h+5−1

@@ -141,6 +141,9 @@ · 140 unmodified lines
141	141	#define PRID_IMP_CAVIUM_CN68XX 0x9100
142	142	#define PRID_IMP_CAVIUM_CN66XX 0x9200
143	143	#define PRID_IMP_CAVIUM_CN61XX 0x9300
	144	+#define PRID_IMP_CAVIUM_CNF71XX 0x9400
	145	+#define PRID_IMP_CAVIUM_CN78XX 0x9500
	146	+#define PRID_IMP_CAVIUM_CN70XX 0x9600
144	147
145	148	/*
146	149	* These are the PRID's for when 23:16 == PRID_COMP_INGENIC
@@ -176,6 +179,7 @@ · 29 unmodified lines
176	179
177	180	#define PRID_IMP_NETLOGIC_XLP8XX 0x1000
178	181	#define PRID_IMP_NETLOGIC_XLP3XX 0x1100
	182	+#define PRID_IMP_NETLOGIC_XLP2XX 0x1200
179	183
180	184	/*
181	185	* Definitions for 7:0 on legacy processors
@@ -272,7 +276,7 @@ enum cpu_type_enum { · 90 unmodified lines
272	276	*/
273	277	CPU_5KC, CPU_5KE, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2,
274	278	CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS, CPU_CAVIUM_OCTEON2,
275		− CPU_XLR, CPU_XLP,
	279	+ CPU_CAVIUM_OCTEON3, CPU_XLR, CPU_XLP,
276	280
277	281	CPU_LAST
278	282	};

arch/mips/include/asm/cputime.h+0−6

@@ -1,6 +0,0 @@
1		−#ifndef __MIPS_CPUTIME_H
2		−#define __MIPS_CPUTIME_H
3		−
4		−#include <asm-generic/cputime.h>
5		−
6		−#endif /* __MIPS_CPUTIME_H */

arch/mips/include/asm/current.h+0−1

@@ -1 +0,0 @@
1		−#include <asm-generic/current.h>

arch/mips/include/asm/emergency-restart.h+0−6

@@ -1,6 +0,0 @@
1		−#ifndef _ASM_EMERGENCY_RESTART_H
2		−#define _ASM_EMERGENCY_RESTART_H
3		−
4		−#include <asm-generic/emergency-restart.h>
5		−
6		−#endif /* _ASM_EMERGENCY_RESTART_H */

arch/mips/include/asm/local64.h+0−1

@@ -1 +0,0 @@
1		−#include <asm-generic/local64.h>

arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h+0−2

@@ -42,8 +42,6 @@ · 41 unmodified lines
42	42	#define cpu_has_mips64r1 0
43	43	#define cpu_has_mips64r2 0
44	44
45		−#define cpu_has_dsp 0
46		−#define cpu_has_dsp2 0
47	45	#define cpu_has_mipsmt 0
48	46
49	47	#define cpu_has_64bits 0

arch/mips/include/asm/mach-cavium-octeon/gpio.h+21−0

@@ -0,0 +1,21 @@
	1	+#ifndef __ASM_MACH_CAVIUM_OCTEON_GPIO_H
	2	+#define __ASM_MACH_CAVIUM_OCTEON_GPIO_H
	3	+
	4	+#ifdef CONFIG_GPIOLIB
	5	+#define gpio_get_value __gpio_get_value
	6	+#define gpio_set_value __gpio_set_value
	7	+#define gpio_cansleep __gpio_cansleep
	8	+#else
	9	+int gpio_request(unsigned gpio, const char *label);
	10	+void gpio_free(unsigned gpio);
	11	+int gpio_direction_input(unsigned gpio);
	12	+int gpio_direction_output(unsigned gpio, int value);
	13	+int gpio_get_value(unsigned gpio);
	14	+void gpio_set_value(unsigned gpio, int value);
	15	+#endif
	16	+
	17	+#include <asm-generic/gpio.h>
	18	+
	19	+#define gpio_to_irq __gpio_to_irq
	20	+
	21	+#endif /* __ASM_MACH_GENERIC_GPIO_H */

arch/mips/include/asm/mach-lantiq/falcon/cpu-feature-overrides.h+58−0

@@ -0,0 +1,58 @@
	1	+/*
	2	+ * Lantiq FALCON specific CPU feature overrides
	3	+ *
	4	+ * Copyright (C) 2013 Thomas Langer, Lantiq Deutschland
	5	+ *
	6	+ * This file was derived from: include/asm-mips/cpu-features.h
	7	+ * Copyright (C) 2003, 2004 Ralf Baechle
	8	+ * Copyright (C) 2004 Maciej W. Rozycki
	9	+ *
	10	+ * This program is free software; you can redistribute it and/or modify it
	11	+ * under the terms of the GNU General Public License version 2 as published
	12	+ * by the Free Software Foundation.
	13	+ *
	14	+ */
	15	+#ifndef __ASM_MACH_FALCON_CPU_FEATURE_OVERRIDES_H
	16	+#define __ASM_MACH_FALCON_CPU_FEATURE_OVERRIDES_H
	17	+
	18	+#define cpu_has_tlb 1
	19	+#define cpu_has_4kex 1
	20	+#define cpu_has_3k_cache 0
	21	+#define cpu_has_4k_cache 1
	22	+#define cpu_has_tx39_cache 0
	23	+#define cpu_has_sb1_cache 0
	24	+#define cpu_has_fpu 0
	25	+#define cpu_has_32fpr 0
	26	+#define cpu_has_counter 1
	27	+#define cpu_has_watch 1
	28	+#define cpu_has_divec 1
	29	+
	30	+#define cpu_has_prefetch 1
	31	+#define cpu_has_ejtag 1
	32	+#define cpu_has_llsc 1
	33	+
	34	+#define cpu_has_mips16 1
	35	+#define cpu_has_mdmx 0
	36	+#define cpu_has_mips3d 0
	37	+#define cpu_has_smartmips 0
	38	+
	39	+#define cpu_has_mips32r1 1
	40	+#define cpu_has_mips32r2 1
	41	+#define cpu_has_mips64r1 0
	42	+#define cpu_has_mips64r2 0
	43	+
	44	+#define cpu_has_dsp 1
	45	+#define cpu_has_mipsmt 1
	46	+
	47	+#define cpu_has_vint 1
	48	+#define cpu_has_veic 1
	49	+
	50	+#define cpu_has_64bits 0
	51	+#define cpu_has_64bit_zero_reg 0
	52	+#define cpu_has_64bit_gp_regs 0
	53	+#define cpu_has_64bit_addresses 0
	54	+
	55	+#define cpu_dcache_line_size() 32
	56	+#define cpu_icache_line_size() 32
	57	+
	58	+#endif /* __ASM_MACH_FALCON_CPU_FEATURE_OVERRIDES_H */

arch/mips/include/asm/mach-ralink/mt7620.h+32−8

@@ -20,6 +20,8 @@ · 19 unmodified lines
20	20	#define SYSC_REG_CHIP_REV 0x0c
21	21	#define SYSC_REG_SYSTEM_CONFIG0 0x10
22	22	#define SYSC_REG_SYSTEM_CONFIG1 0x14
	23	+#define SYSC_REG_CLKCFG0 0x2c
	24	+#define SYSC_REG_CPU_SYS_CLKCFG 0x3c
23	25	#define SYSC_REG_CPLL_CONFIG0 0x54
24	26	#define SYSC_REG_CPLL_CONFIG1 0x58
25	27
@@ -29,20 +31,42 @@ · 3 unmodified lines
29	31	#define MT7620A_CHIP_NAME0 0x3637544d
30	32	#define MT7620A_CHIP_NAME1 0x20203032
31	33
	34	+#define SYSCFG0_XTAL_FREQ_SEL BIT(6)
	35	+
32	36	#define CHIP_REV_PKG_MASK 0x1
33	37	#define CHIP_REV_PKG_SHIFT 16
34	38	#define CHIP_REV_VER_MASK 0xf
35	39	#define CHIP_REV_VER_SHIFT 8
36	40	#define CHIP_REV_ECO_MASK 0xf
37	41
38		−#define CPLL_SW_CONFIG_SHIFT 31
39		−#define CPLL_SW_CONFIG_MASK 0x1
40		−#define CPLL_CPU_CLK_SHIFT 24
41		−#define CPLL_CPU_CLK_MASK 0x1
42		−#define CPLL_MULT_RATIO_SHIFT 16
43		−#define CPLL_MULT_RATIO 0x7
44		−#define CPLL_DIV_RATIO_SHIFT 10
45		−#define CPLL_DIV_RATIO 0x3
	42	+#define CLKCFG0_PERI_CLK_SEL BIT(4)
	43	+
	44	+#define CPU_SYS_CLKCFG_OCP_RATIO_SHIFT 16
	45	+#define CPU_SYS_CLKCFG_OCP_RATIO_MASK 0xf
	46	+#define CPU_SYS_CLKCFG_OCP_RATIO_1 0 /* 1:1 (Reserved) */
	47	+#define CPU_SYS_CLKCFG_OCP_RATIO_1_5 1 /* 1:1.5 (Reserved) */
	48	+#define CPU_SYS_CLKCFG_OCP_RATIO_2 2 /* 1:2 */
	49	+#define CPU_SYS_CLKCFG_OCP_RATIO_2_5 3 /* 1:2.5 (Reserved) */
	50	+#define CPU_SYS_CLKCFG_OCP_RATIO_3 4 /* 1:3 */
	51	+#define CPU_SYS_CLKCFG_OCP_RATIO_3_5 5 /* 1:3.5 (Reserved) */
	52	+#define CPU_SYS_CLKCFG_OCP_RATIO_4 6 /* 1:4 */
	53	+#define CPU_SYS_CLKCFG_OCP_RATIO_5 7 /* 1:5 */
	54	+#define CPU_SYS_CLKCFG_OCP_RATIO_10 8 /* 1:10 */
	55	+#define CPU_SYS_CLKCFG_CPU_FDIV_SHIFT 8
	56	+#define CPU_SYS_CLKCFG_CPU_FDIV_MASK 0x1f
	57	+#define CPU_SYS_CLKCFG_CPU_FFRAC_SHIFT 0
	58	+#define CPU_SYS_CLKCFG_CPU_FFRAC_MASK 0x1f
	59	+
	60	+#define CPLL_CFG0_SW_CFG BIT(31)
	61	+#define CPLL_CFG0_PLL_MULT_RATIO_SHIFT 16
	62	+#define CPLL_CFG0_PLL_MULT_RATIO_MASK 0x7
	63	+#define CPLL_CFG0_LC_CURFCK BIT(15)
	64	+#define CPLL_CFG0_BYPASS_REF_CLK BIT(14)
	65	+#define CPLL_CFG0_PLL_DIV_RATIO_SHIFT 10
	66	+#define CPLL_CFG0_PLL_DIV_RATIO_MASK 0x3
	67	+
	68	+#define CPLL_CFG1_CPU_AUX1 BIT(25)
	69	+#define CPLL_CFG1_CPU_AUX0 BIT(24)
46	70
47	71	#define SYSCFG0_DRAM_TYPE_MASK 0x3
48	72	#define SYSCFG0_DRAM_TYPE_SHIFT 4

arch/mips/include/asm/mach-ralink/mt7620/cpu-feature-overrides.h+57−0

@@ -0,0 +1,57 @@
	1	+/*
	2	+ * Ralink MT7620 specific CPU feature overrides
	3	+ *
	4	+ * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
	5	+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
	6	+ *
	7	+ * This file was derived from: include/asm-mips/cpu-features.h
	8	+ * Copyright (C) 2003, 2004 Ralf Baechle
	9	+ * Copyright (C) 2004 Maciej W. Rozycki
	10	+ *
	11	+ * This program is free software; you can redistribute it and/or modify it
	12	+ * under the terms of the GNU General Public License version 2 as published
	13	+ * by the Free Software Foundation.
	14	+ *
	15	+ */
	16	+#ifndef _MT7620_CPU_FEATURE_OVERRIDES_H
	17	+#define _MT7620_CPU_FEATURE_OVERRIDES_H
	18	+
	19	+#define cpu_has_tlb 1
	20	+#define cpu_has_4kex 1
	21	+#define cpu_has_3k_cache 0
	22	+#define cpu_has_4k_cache 1
	23	+#define cpu_has_tx39_cache 0
	24	+#define cpu_has_sb1_cache 0
	25	+#define cpu_has_fpu 0
	26	+#define cpu_has_32fpr 0
	27	+#define cpu_has_counter 1
	28	+#define cpu_has_watch 1
	29	+#define cpu_has_divec 1
	30	+
	31	+#define cpu_has_prefetch 1
	32	+#define cpu_has_ejtag 1
	33	+#define cpu_has_llsc 1
	34	+
	35	+#define cpu_has_mips16 1
	36	+#define cpu_has_mdmx 0
	37	+#define cpu_has_mips3d 0
	38	+#define cpu_has_smartmips 0
	39	+
	40	+#define cpu_has_mips32r1 1
	41	+#define cpu_has_mips32r2 1
	42	+#define cpu_has_mips64r1 0
	43	+#define cpu_has_mips64r2 0
	44	+
	45	+#define cpu_has_dsp 1
	46	+#define cpu_has_dsp2 0
	47	+#define cpu_has_mipsmt 0
	48	+
	49	+#define cpu_has_64bits 0
	50	+#define cpu_has_64bit_zero_reg 0
	51	+#define cpu_has_64bit_gp_regs 0
	52	+#define cpu_has_64bit_addresses 0
	53	+
	54	+#define cpu_dcache_line_size() 32
	55	+#define cpu_icache_line_size() 32
	56	+
	57	+#endif /* _MT7620_CPU_FEATURE_OVERRIDES_H */

arch/mips/include/asm/mutex.h+0−9

@@ -1,9 +0,0 @@
1		−/*
2		− * Pull in the generic implementation for the mutex fastpath.
3		− *
4		− * TODO: implement optimized primitives instead, or leave the generic
5		− * implementation in place, or pick the atomic_xchg() based generic
6		− * implementation. (see asm-generic/mutex-xchg.h for details)
7		− */
8		−
9		−#include <asm-generic/mutex-dec.h>

arch/mips/include/asm/netlogic/xlp-hal/bridge.h+4−0

@@ -88,6 +88,7 @@ · 87 unmodified lines
88	88	#define BRIDGE_DRAM_LIMIT6 0x22
89	89	#define BRIDGE_DRAM_LIMIT7 0x23
90	90
	91	+#define BRIDGE_DRAM_NODE_TRANSLN(i) (0x24 + (i))
91	92	#define BRIDGE_DRAM_NODE_TRANSLN0 0x24
92	93	#define BRIDGE_DRAM_NODE_TRANSLN1 0x25
93	94	#define BRIDGE_DRAM_NODE_TRANSLN2 0x26
@@ -96,6 +97,8 @@ · 2 unmodified lines
96	97	#define BRIDGE_DRAM_NODE_TRANSLN5 0x29
97	98	#define BRIDGE_DRAM_NODE_TRANSLN6 0x2a
98	99	#define BRIDGE_DRAM_NODE_TRANSLN7 0x2b
	100	+
	101	+#define BRIDGE_DRAM_CHNL_TRANSLN(i) (0x2c + (i))
99	102	#define BRIDGE_DRAM_CHNL_TRANSLN0 0x2c
100	103	#define BRIDGE_DRAM_CHNL_TRANSLN1 0x2d
101	104	#define BRIDGE_DRAM_CHNL_TRANSLN2 0x2e
@@ -104,6 +107,7 @@ · 2 unmodified lines
104	107	#define BRIDGE_DRAM_CHNL_TRANSLN5 0x31
105	108	#define BRIDGE_DRAM_CHNL_TRANSLN6 0x32
106	109	#define BRIDGE_DRAM_CHNL_TRANSLN7 0x33
	110	+
107	111	#define BRIDGE_PCIEMEM_BASE0 0x34
108	112	#define BRIDGE_PCIEMEM_BASE1 0x35
109	113	#define BRIDGE_PCIEMEM_BASE2 0x36

arch/mips/include/asm/netlogic/xlp-hal/iomap.h+10−0

@@ -72,6 +72,12 @@ · 71 unmodified lines
72	72	#define XLP_IO_USB_OHCI2_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 4)
73	73	#define XLP_IO_USB_OHCI3_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 5)
74	74
	75	+/* XLP2xx has an updated USB block */
	76	+#define XLP2XX_IO_USB_OFFSET(node, i) XLP_HDR_OFFSET(node, 0, 4, i)
	77	+#define XLP2XX_IO_USB_XHCI0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 4, 1)
	78	+#define XLP2XX_IO_USB_XHCI1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 4, 2)
	79	+#define XLP2XX_IO_USB_XHCI2_OFFSET(node) XLP_HDR_OFFSET(node, 0, 4, 3)
	80	+
75	81	#define XLP_IO_NAE_OFFSET(node) XLP_HDR_OFFSET(node, 0, 3, 0)
76	82	#define XLP_IO_POE_OFFSET(node) XLP_HDR_OFFSET(node, 0, 3, 1)
77	83
@@ -88,6 +94,9 @@ · 10 unmodified lines
88	94	#define XLP_IO_I2C0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 2)
89	95	#define XLP_IO_I2C1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 3)
90	96	#define XLP_IO_GPIO_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 4)
	97	+/* on 2XX, all I2C busses are on the same block */
	98	+#define XLP2XX_IO_I2C_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 7)
	99	+
91	100	/* system management */
92	101	#define XLP_IO_SYS_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 5)
93	102	#define XLP_IO_JTAG_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 6)
@@ -145,6 +154,7 @@ · 51 unmodified lines
145	154	#define PCI_DEVICE_ID_NLM_NOR 0x1015
146	155	#define PCI_DEVICE_ID_NLM_NAND 0x1016
147	156	#define PCI_DEVICE_ID_NLM_MMC 0x1018
	157	+#define PCI_DEVICE_ID_NLM_XHCI 0x101d
148	158
149	159	#ifndef __ASSEMBLY__
150	160

arch/mips/include/asm/netlogic/xlp-hal/pic.h+3−2

@@ -208,13 +208,14 @@ · 207 unmodified lines
208	208	#define PIC_LOCAL_SCHEDULING 1
209	209	#define PIC_GLOBAL_SCHEDULING 0
210	210
211		−#define PIC_CLK_HZ 133333333
212		−
213	211	#define nlm_read_pic_reg(b, r) nlm_read_reg64(b, r)
214	212	#define nlm_write_pic_reg(b, r, v) nlm_write_reg64(b, r, v)
215	213	#define nlm_get_pic_pcibase(node) nlm_pcicfg_base(XLP_IO_PIC_OFFSET(node))
216	214	#define nlm_get_pic_regbase(node) (nlm_get_pic_pcibase(node) + XLP_IO_PCI_HDRSZ)
217	215
	216	+/* We use PIC on node 0 as a timer */
	217	+#define pic_timer_freq() nlm_get_pic_frequency(0)
	218	+
218	219	/* IRT and h/w interrupt routines */
219	220	static inline int
220	221	nlm_pic_read_irt(uint64_t base, int irt_index)

arch/mips/include/asm/netlogic/xlp-hal/sys.h+31−0

@@ -117,6 +117,36 @@ · 116 unmodified lines
117	117	#define SYS_SCRTCH2 0x4b
118	118	#define SYS_SCRTCH3 0x4c
119	119
	120	+/* PLL registers XLP2XX */
	121	+#define SYS_PLL_CTRL0 0x240
	122	+#define SYS_PLL_CTRL1 0x241
	123	+#define SYS_PLL_CTRL2 0x242
	124	+#define SYS_PLL_CTRL3 0x243
	125	+#define SYS_DMC_PLL_CTRL0 0x244
	126	+#define SYS_DMC_PLL_CTRL1 0x245
	127	+#define SYS_DMC_PLL_CTRL2 0x246
	128	+#define SYS_DMC_PLL_CTRL3 0x247
	129	+
	130	+#define SYS_PLL_CTRL0_DEVX(x) (0x248 + (x) * 4)
	131	+#define SYS_PLL_CTRL1_DEVX(x) (0x249 + (x) * 4)
	132	+#define SYS_PLL_CTRL2_DEVX(x) (0x24a + (x) * 4)
	133	+#define SYS_PLL_CTRL3_DEVX(x) (0x24b + (x) * 4)
	134	+
	135	+#define SYS_CPU_PLL_CHG_CTRL 0x288
	136	+#define SYS_PLL_CHG_CTRL 0x289
	137	+#define SYS_CLK_DEV_DIS 0x28a
	138	+#define SYS_CLK_DEV_SEL 0x28b
	139	+#define SYS_CLK_DEV_DIV 0x28c
	140	+#define SYS_CLK_DEV_CHG 0x28d
	141	+#define SYS_CLK_DEV_SEL_REG 0x28e
	142	+#define SYS_CLK_DEV_DIV_REG 0x28f
	143	+#define SYS_CPU_PLL_LOCK 0x29f
	144	+#define SYS_SYS_PLL_LOCK 0x2a0
	145	+#define SYS_PLL_MEM_CMD 0x2a1
	146	+#define SYS_CPU_PLL_MEM_REQ 0x2a2
	147	+#define SYS_SYS_PLL_MEM_REQ 0x2a3
	148	+#define SYS_PLL_MEM_STAT 0x2a4
	149	+
120	150	#ifndef __ASSEMBLY__
121	151
122	152	#define nlm_read_sys_reg(b, r) nlm_read_reg(b, r)
@@ -124,5 +154,6 @@ · 1 unmodified line
124	154	#define nlm_get_sys_pcibase(node) nlm_pcicfg_base(XLP_IO_SYS_OFFSET(node))
125	155	#define nlm_get_sys_regbase(node) (nlm_get_sys_pcibase(node) + XLP_IO_PCI_HDRSZ)
126	156
	157	+unsigned int nlm_get_pic_frequency(int node);
127	158	#endif
128	159	#endif

arch/mips/include/asm/netlogic/xlp-hal/xlp.h+17−0

@@ -41,15 +41,22 @@ · 40 unmodified lines
41	41	#define PIC_PCIE_LINK_1_IRQ 20
42	42	#define PIC_PCIE_LINK_2_IRQ 21
43	43	#define PIC_PCIE_LINK_3_IRQ 22
	44	+
44	45	#define PIC_EHCI_0_IRQ 23
45	46	#define PIC_EHCI_1_IRQ 24
46	47	#define PIC_OHCI_0_IRQ 25
47	48	#define PIC_OHCI_1_IRQ 26
48	49	#define PIC_OHCI_2_IRQ 27
49	50	#define PIC_OHCI_3_IRQ 28
	51	+#define PIC_2XX_XHCI_0_IRQ 23
	52	+#define PIC_2XX_XHCI_1_IRQ 24
	53	+#define PIC_2XX_XHCI_2_IRQ 25
	54	+
50	55	#define PIC_MMC_IRQ 29
51	56	#define PIC_I2C_0_IRQ 30
52	57	#define PIC_I2C_1_IRQ 31
	58	+#define PIC_I2C_2_IRQ 32
	59	+#define PIC_I2C_3_IRQ 33
53	60
54	61	#ifndef __ASSEMBLY__
55	62
@@ -59,7 +66,17 @@ void xlp_wakeup_secondary_cpus(void); · 3 unmodified lines
59	66
60	67	void xlp_mmu_init(void);
61	68	void nlm_hal_init(void);
	69	+int xlp_get_dram_map(int n, uint64_t *dram_map);
	70	+
	71	+/* Device tree related */
62	72	void xlp_dt_init(void fdtp);
63	73
	74	+static inline int cpu_is_xlpii(void)
	75	+{
	76	+ int chip = read_c0_prid() & 0xff00;
	77	+
	78	+ return chip == PRID_IMP_NETLOGIC_XLP2XX;
	79	+}
	80	+
64	81	#endif /* !__ASSEMBLY__ */
65	82	#endif /* _ASM_NLM_XLP_H */

arch/mips/include/asm/netlogic/xlr/pic.h+2−0

@@ -36,6 +36,8 @@ · 35 unmodified lines
36	36	#define _ASM_NLM_XLR_PIC_H
37	37
38	38	#define PIC_CLK_HZ 66666666
	39	+#define pic_timer_freq() PIC_CLK_HZ
	40	+
39	41	/* PIC hardware interrupt numbers */
40	42	#define PIC_IRT_WD_INDEX 0
41	43	#define PIC_IRT_TIMER_0_INDEX 1

arch/mips/include/asm/octeon/octeon.h+2−0

@@ -251,4 +251,6 @@ extern void (*octeon_irq_setup_secondary)(void); · 250 unmodified lines
251	251	typedef void (*octeon_irq_ip4_handler_t)(void);
252	252	void octeon_irq_set_ip4_handler(octeon_irq_ip4_handler_t);
253	253
	254	+extern void octeon_fixup_irqs(void);
	255	+
254	256	#endif /* __ASM_OCTEON_OCTEON_H */

arch/mips/include/asm/parport.h+0−1

@@ -1 +0,0 @@
1		−#include <asm-generic/parport.h>

arch/mips/include/asm/percpu.h+0−6

@@ -1,6 +0,0 @@
1		−#ifndef __ASM_PERCPU_H
2		−#define __ASM_PERCPU_H
3		−
4		−#include <asm-generic/percpu.h>
5		−
6		−#endif /* __ASM_PERCPU_H */

arch/mips/include/asm/scatterlist.h+0−6

@@ -1,6 +0,0 @@
1		−#ifndef __ASM_SCATTERLIST_H
2		−#define __ASM_SCATTERLIST_H
3		−
4		−#include <asm-generic/scatterlist.h>
5		−
6		−#endif /* __ASM_SCATTERLIST_H */

arch/mips/include/asm/sections.h+0−6

@@ -1,6 +0,0 @@
1		−#ifndef _ASM_SECTIONS_H
2		−#define _ASM_SECTIONS_H
3		−
4		−#include <asm-generic/sections.h>
5		−
6		−#endif /* _ASM_SECTIONS_H */

arch/mips/include/asm/segment.h+0−6

@@ -1,6 +0,0 @@
1		−#ifndef _ASM_SEGMENT_H
2		−#define _ASM_SEGMENT_H
3		−
4		−/* Only here because we have some old header files that expect it.. */
5		−
6		−#endif /* _ASM_SEGMENT_H */

arch/mips/include/asm/serial.h+0−1

@@ -1 +0,0 @@
1		−#include <asm-generic/serial.h>

arch/mips/include/asm/ucontext.h+0−1

@@ -1 +0,0 @@
1		−#include <asm-generic/ucontext.h>

arch/mips/include/asm/xor.h+0−1

@@ -1 +0,0 @@
1		−#include <asm-generic/xor.h>

arch/mips/include/uapi/asm/Kbuild+3−2

@@ -1,7 +1,9 @@
1	1	# UAPI Header export list
2	2	include include/uapi/asm-generic/Kbuild.asm
3	3
4		−header-y += auxvec.h
	4	+generic-y += auxvec.h
	5	+generic-y += ipcbuf.h
	6	+
5	7	header-y += bitsperlong.h
6	8	header-y += break.h
7	9	header-y += byteorder.h
@@ -11,7 +13,6 @@ header-y += fcntl.h · 3 unmodified lines
11	13	header-y += inst.h
12	14	header-y += ioctl.h
13	15	header-y += ioctls.h
14		−header-y += ipcbuf.h
15	16	header-y += kvm_para.h
16	17	header-y += mman.h
17	18	header-y += msgbuf.h

arch/mips/include/uapi/asm/auxvec.h+0−4

@@ -1,4 +0,0 @@
1		−#ifndef _ASM_AUXVEC_H
2		−#define _ASM_AUXVEC_H
3		−
4		−#endif /* _ASM_AUXVEC_H */

arch/mips/include/uapi/asm/ipcbuf.h+0−1

@@ -1 +0,0 @@
1		−#include <asm-generic/ipcbuf.h>

arch/mips/kernel/cpu-probe.c+12−0

@@ -852,10 +852,17 @@ platform: · 851 unmodified lines
852	852	case PRID_IMP_CAVIUM_CN63XX:
853	853	case PRID_IMP_CAVIUM_CN66XX:
854	854	case PRID_IMP_CAVIUM_CN68XX:
	855	+ case PRID_IMP_CAVIUM_CNF71XX:
855	856	c->cputype = CPU_CAVIUM_OCTEON2;
856	857	__cpu_name[cpu] = "Cavium Octeon II";
857	858	set_elf_platform(cpu, "octeon2");
858	859	break;
	860	+ case PRID_IMP_CAVIUM_CN70XX:
	861	+ case PRID_IMP_CAVIUM_CN78XX:
	862	+ c->cputype = CPU_CAVIUM_OCTEON3;
	863	+ __cpu_name[cpu] = "Cavium Octeon III";
	864	+ set_elf_platform(cpu, "octeon3");
	865	+ break;
859	866	default:
860	867	printk(KERN_INFO "Unknown Octeon chip!\n");
861	868	c->cputype = CPU_UNKNOWN;
@@ -899,6 +906,11 @@ static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu) · 37 unmodified lines
899	906	MIPS_CPU_LLSC);
900	907
901	908	switch (c->processor_id & 0xff00) {
	909	+ case PRID_IMP_NETLOGIC_XLP2XX:
	910	+ c->cputype = CPU_XLP;
	911	+ __cpu_name[cpu] = "Broadcom XLPII";
	912	+ break;
	913	+
902	914	case PRID_IMP_NETLOGIC_XLP8XX:
903	915	case PRID_IMP_NETLOGIC_XLP3XX:
904	916	c->cputype = CPU_XLP;

arch/mips/kernel/csrc-ioasic.c+3−3

@@ -41,9 +41,9 @@ void __init dec_ioasic_clocksource_init(void) · 40 unmodified lines
41	41	{
42	42	unsigned int freq;
43	43	u32 start, end;
44		− int i = HZ / 10;
45		−
	44	+ int i = HZ / 8;
46	45
	46	+ ds1287_timer_state();
47	47	while (!ds1287_timer_state())
48	48	;
49	49
@@ -55,7 +55,7 @@ void __init dec_ioasic_clocksource_init(void) · 5 unmodified lines
55	55
56	56	end = dec_ioasic_hpt_read(&clocksource_dec);
57	57
58		− freq = (end - start) * 10;
	58	+ freq = (end - start) * 8;
59	59	printk(KERN_INFO "I/O ASIC clock frequency %dHz\n", freq);
60	60
61	61	clocksource_dec.rating = 200 + freq / 10000000;

arch/mips/kernel/idle.c+1−0

@@ -166,6 +166,7 @@ void __init check_wait(void) · 165 unmodified lines
166	166	case CPU_CAVIUM_OCTEON:
167	167	case CPU_CAVIUM_OCTEON_PLUS:
168	168	case CPU_CAVIUM_OCTEON2:
	169	+ case CPU_CAVIUM_OCTEON3:
169	170	case CPU_JZRISC:
170	171	case CPU_LOONGSON1:
171	172	case CPU_XLR:

arch/mips/kernel/mcount.S+1−1

@@ -83,7 +83,7 @@ _mcount: · 82 unmodified lines
83	83	PTR_S MCOUNT_RA_ADDRESS_REG, PT_R12(sp)
84	84	#endif
85	85
86		− move a0, ra /* arg1: self return address */
	86	+ PTR_SUBU a0, ra, 8 /* arg1: self address */
87	87	.globl ftrace_call
88	88	ftrace_call:
89	89	nop /* a placeholder for the call to a real tracing function */

arch/mips/kernel/relocate_kernel.S+6−0

@@ -26,6 +26,12 @@ process_entry: · 25 unmodified lines
26	26	PTR_L s2, (s0)
27	27	PTR_ADD s0, s0, SZREG
28	28
	29	+ /*
	30	+ * In case of a kdump/crash kernel, the indirection page is not
	31	+ * populated as the kernel is directly copied to a reserved location
	32	+ */
	33	+ beqz s2, done
	34	+
29	35	/* destination page */
30	36	and s3, s2, 0x1
31	37	beq s3, zero, 1f

arch/mips/kernel/setup.c+48−51

@@ -552,6 +552,52 @@ static void __init arch_mem_addpart(phys_t mem, phys_t end, int type) · 551 unmodified lines
552	552	add_memory_region(mem, size, type);
553	553	}
554	554
	555	+#ifdef CONFIG_KEXEC
	556	+static inline unsigned long long get_total_mem(void)
	557	+{
	558	+ unsigned long long total;
	559	+
	560	+ total = max_pfn - min_low_pfn;
	561	+ return total << PAGE_SHIFT;
	562	+}
	563	+
	564	+static void __init mips_parse_crashkernel(void)
	565	+{
	566	+ unsigned long long total_mem;
	567	+ unsigned long long crash_size, crash_base;
	568	+ int ret;
	569	+
	570	+ total_mem = get_total_mem();
	571	+ ret = parse_crashkernel(boot_command_line, total_mem,
	572	+ &crash_size, &crash_base);
	573	+ if (ret != 0 \|\| crash_size <= 0)
	574	+ return;
	575	+
	576	+ crashk_res.start = crash_base;
	577	+ crashk_res.end = crash_base + crash_size - 1;
	578	+}
	579	+
	580	+static void __init request_crashkernel(struct resource *res)
	581	+{
	582	+ int ret;
	583	+
	584	+ ret = request_resource(res, &crashk_res);
	585	+ if (!ret)
	586	+ pr_info("Reserving %ldMB of memory at %ldMB for crashkernel\n",
	587	+ (unsigned long)((crashk_res.end -
	588	+ crashk_res.start + 1) >> 20),
	589	+ (unsigned long)(crashk_res.start >> 20));
	590	+}
	591	+#else /* !defined(CONFIG_KEXEC) */
	592	+static void __init mips_parse_crashkernel(void)
	593	+{
	594	+}
	595	+
	596	+static void __init request_crashkernel(struct resource *res)
	597	+{
	598	+}
	599	+#endif /* !defined(CONFIG_KEXEC) */
	600	+
555	601	static void __init arch_mem_init(char **cmdline_p)
556	602	{
557	603	extern void plat_mem_setup(void);
@@ -608,6 +654,8 @@ static void __init arch_mem_init(char **cmdline_p) · 50 unmodified lines
608	654	BOOTMEM_DEFAULT);
609	655	}
610	656	#endif
	657	+
	658	+ mips_parse_crashkernel();
611	659	#ifdef CONFIG_KEXEC
612	660	if (crashk_res.start != crashk_res.end)
613	661	reserve_bootmem(crashk_res.start,
@@ -620,52 +668,6 @@ static void __init arch_mem_init(char **cmdline_p) · 6 unmodified lines
620	668	paging_init();
621	669	}
622	670
623		−#ifdef CONFIG_KEXEC
624		−static inline unsigned long long get_total_mem(void)
625		−{
626		− unsigned long long total;
627		−
628		− total = max_pfn - min_low_pfn;
629		− return total << PAGE_SHIFT;
630		−}
631		−
632		−static void __init mips_parse_crashkernel(void)
633		−{
634		− unsigned long long total_mem;
635		− unsigned long long crash_size, crash_base;
636		− int ret;
637		−
638		− total_mem = get_total_mem();
639		− ret = parse_crashkernel(boot_command_line, total_mem,
640		− &crash_size, &crash_base);
641		− if (ret != 0 \|\| crash_size <= 0)
642		− return;
643		−
644		− crashk_res.start = crash_base;
645		− crashk_res.end = crash_base + crash_size - 1;
646		−}
647		−
648		−static void __init request_crashkernel(struct resource *res)
649		−{
650		− int ret;
651		−
652		− ret = request_resource(res, &crashk_res);
653		− if (!ret)
654		− pr_info("Reserving %ldMB of memory at %ldMB for crashkernel\n",
655		− (unsigned long)((crashk_res.end -
656		− crashk_res.start + 1) >> 20),
657		− (unsigned long)(crashk_res.start >> 20));
658		−}
659		−#else /* !defined(CONFIG_KEXEC) */
660		−static void __init mips_parse_crashkernel(void)
661		−{
662		−}
663		−
664		−static void __init request_crashkernel(struct resource *res)
665		−{
666		−}
667		−#endif /* !defined(CONFIG_KEXEC) */
668		−
669	671	static void __init resource_init(void)
670	672	{
671	673	int i;
@@ -678,11 +680,6 @@ static void __init resource_init(void) · 6 unmodified lines
678	680	data_resource.start = __pa_symbol(&_etext);
679	681	data_resource.end = __pa_symbol(&_edata) - 1;
680	682
681		− /*
682		− * Request address space for all standard RAM.
683		− */
684		− mips_parse_crashkernel();
685		−
686	683	for (i = 0; i < boot_mem_map.nr_map; i++) {
687	684	struct resource *res;
688	685	unsigned long start, end;

arch/mips/kernel/time.c+9−1

@@ -121,6 +121,14 @@ void __init time_init(void) · 120 unmodified lines
121	121	{
122	122	plat_time_init();
123	123
124		− if (!mips_clockevent_init() \|\| !cpu_has_mfc0_count_bug())
	124	+ /*
	125	+ * The use of the R4k timer as a clock event takes precedence;
	126	+ * if reading the Count register might interfere with the timer
	127	+ * interrupt, then we don't use the timer as a clock source.
	128	+ * We may still use the timer as a clock source though if the
	129	+ * timer interrupt isn't reliable; the interference doesn't
	130	+ * matter then, because we don't use the interrupt.
	131	+ */
	132	+ if (mips_clockevent_init() != 0 \|\| !cpu_has_mfc0_count_bug())
125	133	init_mips_clocksource();
126	134	}

arch/mips/kernel/vmlinux.lds.S+1−0

@@ -179,5 +179,6 @@ SECTIONS · 178 unmodified lines
179	179	*(.options)
180	180	*(.pdr)
181	181	*(.reginfo)
	182	+ *(.eh_frame)
182	183	}
183	184	}

arch/mips/lantiq/falcon/sysctrl.c+4−1

@@ -48,6 +48,7 @@ · 47 unmodified lines
48	48	#define CPU0CC_CPUDIV 0x0001
49	49
50	50	/* Activation Status Register */
	51	+#define ACTS_ASC0_ACT 0x00001000
51	52	#define ACTS_ASC1_ACT 0x00000800
52	53	#define ACTS_I2C_ACT 0x00004000
53	54	#define ACTS_P0 0x00010000
@@ -108,6 +109,7 @@ static void sysctl_deactivate(struct clk *clk) · 54 unmodified lines
108	109	static int sysctl_clken(struct clk *clk)
109	110	{
110	111	sysctl_w32(clk->module, clk->bits, SYSCTL_CLKEN);
	112	+ sysctl_w32(clk->module, clk->bits, SYSCTL_ACT);
111	113	sysctl_wait(clk, clk->bits, SYSCTL_CLKS);
112	114	return 0;
113	115	}
@@ -256,6 +258,7 @@ void __init ltq_soc_init(void) · 142 unmodified lines
256	258	clkdev_add_sys("1e800400.pad", SYSCTL_SYS1, ACTS_PADCTRL1);
257	259	clkdev_add_sys("1e800500.pad", SYSCTL_SYS1, ACTS_PADCTRL3);
258	260	clkdev_add_sys("1e800600.pad", SYSCTL_SYS1, ACTS_PADCTRL4);
259		− clkdev_add_sys("1e100C00.serial", SYSCTL_SYS1, ACTS_ASC1_ACT);
	261	+ clkdev_add_sys("1e100b00.serial", SYSCTL_SYS1, ACTS_ASC1_ACT);
	262	+ clkdev_add_sys("1e100c00.serial", SYSCTL_SYS1, ACTS_ASC0_ACT);
260	263	clkdev_add_sys("1e200000.i2c", SYSCTL_SYS1, ACTS_I2C_ACT);
261	264	}

arch/mips/lantiq/xway/Makefile+1−1

@@ -1,3 +1,3 @@
1		−obj-y := prom.o sysctrl.o clk.o reset.o dma.o gptu.o
	1	+obj-y := prom.o sysctrl.o clk.o reset.o dma.o gptu.o dcdc.o
2	2
3	3	obj-$(CONFIG_XRX200_PHY_FW) += xrx200_phy_fw.o

arch/mips/lantiq/xway/dcdc.c+63−0

@@ -0,0 +1,63 @@
	1	+/*
	2	+ * This program is free software; you can redistribute it and/or modify it
	3	+ * under the terms of the GNU General Public License version 2 as published
	4	+ * by the Free Software Foundation.
	5	+ *
	6	+ * Copyright (C) 2012 John Crispin <blogic@openwrt.org>
	7	+ * Copyright (C) 2010 Sameer Ahmad, Lantiq GmbH
	8	+ */
	9	+
	10	+#include <linux/ioport.h>
	11	+#include <linux/of_platform.h>
	12	+
	13	+#include <lantiq_soc.h>
	14	+
	15	+/* Bias and regulator Setup Register */
	16	+#define DCDC_BIAS_VREG0 0xa
	17	+/* Bias and regulator Setup Register */
	18	+#define DCDC_BIAS_VREG1 0xb
	19	+
	20	+#define dcdc_w8(x, y) ltq_w8((x), dcdc_membase + (y))
	21	+#define dcdc_r8(x) ltq_r8(dcdc_membase + (x))
	22	+
	23	+static void __iomem *dcdc_membase;
	24	+
	25	+static int dcdc_probe(struct platform_device *pdev)
	26	+{
	27	+ struct resource *res;
	28	+
	29	+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	30	+ dcdc_membase = devm_ioremap_resource(&pdev->dev, res);
	31	+ if (IS_ERR(dcdc_membase))
	32	+ return PTR_ERR(dcdc_membase);
	33	+
	34	+ dev_info(&pdev->dev, "Core Voltage : %d mV\n",
	35	+ dcdc_r8(DCDC_BIAS_VREG1) * 8);
	36	+
	37	+ return 0;
	38	+}
	39	+
	40	+static const struct of_device_id dcdc_match[] = {
	41	+ { .compatible = "lantiq,dcdc-xrx200" },
	42	+ {},
	43	+};
	44	+
	45	+static struct platform_driver dcdc_driver = {
	46	+ .probe = dcdc_probe,
	47	+ .driver = {
	48	+ .name = "dcdc-xrx200",
	49	+ .owner = THIS_MODULE,
	50	+ .of_match_table = dcdc_match,
	51	+ },
	52	+};
	53	+
	54	+int __init dcdc_init(void)
	55	+{
	56	+ int ret = platform_driver_register(&dcdc_driver);
	57	+
	58	+ if (ret)
	59	+ pr_info("dcdc: Error registering platform driver\n");
	60	+ return ret;
	61	+}
	62	+
	63	+arch_initcall(dcdc_init);

arch/mips/lasat/image/Makefile+2−4

@@ -13,13 +13,11 @@ endif · 12 unmodified lines
13	13	MKLASATIMG = mklasatimg
14	14	MKLASATIMG_ARCH = mq2,mqpro,sp100,sp200
15	15	KERNEL_IMAGE = vmlinux
16		−KERNEL_START = $(shell $(NM) $(KERNEL_IMAGE) \| grep " _text" \| cut -f1 -d\ )
17		−KERNEL_ENTRY = $(shell $(NM) $(KERNEL_IMAGE) \| grep kernel_entry \| cut -f1 -d\ )
18	16
19	17	LDSCRIPT= -L$(srctree)/$(src) -Tromscript.normal
20	18
21		−HEAD_DEFINES := -D_kernel_start=0x$(KERNEL_START) \
22		− -D_kernel_entry=0x$(KERNEL_ENTRY) \
	19	+HEAD_DEFINES := -D_kernel_start=$(VMLINUX_LOAD_ADDRESS) \
	20	+ -D_kernel_entry=$(VMLINUX_ENTRY_ADDRESS) \
23	21	-D VERSION="\"$(Version)\"" \
24	22	-D TIMESTAMP=$(shell date +%s)
25	23

arch/mips/loongson/common/Makefile+2−1

@@ -3,8 +3,9 @@ · 2 unmodified lines
3	3	#
4	4
5	5	obj-y += setup.o init.o cmdline.o env.o time.o reset.o irq.o \
6		− pci.o bonito-irq.o mem.o machtype.o platform.o
	6	+ bonito-irq.o mem.o machtype.o platform.o
7	7	obj-$(CONFIG_GPIOLIB) += gpio.o
	8	+obj-$(CONFIG_PCI) += pci.o
8	9
9	10	#
10	11	# Serial port support

arch/mips/math-emu/cp1emu.c+0−27

@@ -436,7 +436,6 @@ static int microMIPS32_to_MIPS32(union mips_instruction *insn_ptr) · 435 unmodified lines
436	436	break;
437	437	default:
438	438	return SIGILL;
439		− break;
440	439	}
441	440	break;
442	441	case mm_32f_74_op: /* c.cond.fmt */
@@ -451,12 +450,10 @@ static int microMIPS32_to_MIPS32(union mips_instruction *insn_ptr) · 8 unmodified lines
451	450	break;
452	451	default:
453	452	return SIGILL;
454		− break;
455	453	}
456	454	break;
457	455	default:
458	456	return SIGILL;
459		− break;
460	457	}
461	458
462	459	*insn_ptr = mips32_insn;
@@ -491,7 +488,6 @@ int mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn, · 28 unmodified lines
491	488	dec_insn.next_pc_inc;
492	489	*contpc = regs->regs[insn.mm_i_format.rs];
493	490	return 1;
494		− break;
495	491	}
496	492	}
497	493	break;
@@ -513,7 +509,6 @@ int mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn, · 15 unmodified lines
513	509	dec_insn.pc_inc +
514	510	dec_insn.next_pc_inc;
515	511	return 1;
516		− break;
517	512	case mm_bgezals_op:
518	513	case mm_bgezal_op:
519	514	regs->regs[31] = regs->cp0_epc +
@@ -530,7 +525,6 @@ int mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn, · 10 unmodified lines
530	525	dec_insn.pc_inc +
531	526	dec_insn.next_pc_inc;
532	527	return 1;
533		− break;
534	528	case mm_blez_op:
535	529	if ((long)regs->regs[insn.mm_i_format.rs] <= 0)
536	530	*contpc = regs->cp0_epc +
@@ -541,7 +535,6 @@ int mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn, · 4 unmodified lines
541	535	dec_insn.pc_inc +
542	536	dec_insn.next_pc_inc;
543	537	return 1;
544		− break;
545	538	case mm_bgtz_op:
546	539	if ((long)regs->regs[insn.mm_i_format.rs] <= 0)
547	540	*contpc = regs->cp0_epc +
@@ -552,7 +545,6 @@ int mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn, · 4 unmodified lines
552	545	dec_insn.pc_inc +
553	546	dec_insn.next_pc_inc;
554	547	return 1;
555		− break;
556	548	case mm_bc2f_op:
557	549	case mm_bc1f_op:
558	550	bc_false = 1;
@@ -580,7 +572,6 @@ int mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn, · 21 unmodified lines
580	572	*contpc = regs->cp0_epc +
581	573	dec_insn.pc_inc + dec_insn.next_pc_inc;
582	574	return 1;
583		− break;
584	575	}
585	576	break;
586	577	case mm_pool16c_op:
@@ -593,7 +584,6 @@ int mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn, · 6 unmodified lines
593	584	case mm_jr16_op:
594	585	*contpc = regs->regs[insn.mm_i_format.rs];
595	586	return 1;
596		− break;
597	587	}
598	588	break;
599	589	case mm_beqz16_op:
@@ -605,7 +595,6 @@ int mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn, · 5 unmodified lines
605	595	*contpc = regs->cp0_epc +
606	596	dec_insn.pc_inc + dec_insn.next_pc_inc;
607	597	return 1;
608		− break;
609	598	case mm_bnez16_op:
610	599	if ((long)regs->regs[reg16to32map[insn.mm_b1_format.rs]] != 0)
611	600	*contpc = regs->cp0_epc +
@@ -615,12 +604,10 @@ int mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn, · 3 unmodified lines
615	604	*contpc = regs->cp0_epc +
616	605	dec_insn.pc_inc + dec_insn.next_pc_inc;
617	606	return 1;
618		− break;
619	607	case mm_b16_op:
620	608	*contpc = regs->cp0_epc + dec_insn.pc_inc +
621	609	(insn.mm_b0_format.simmediate << 1);
622	610	return 1;
623		− break;
624	611	case mm_beq32_op:
625	612	if (regs->regs[insn.mm_i_format.rs] ==
626	613	regs->regs[insn.mm_i_format.rt])
@@ -632,7 +619,6 @@ int mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn, · 5 unmodified lines
632	619	dec_insn.pc_inc +
633	620	dec_insn.next_pc_inc;
634	621	return 1;
635		− break;
636	622	case mm_bne32_op:
637	623	if (regs->regs[insn.mm_i_format.rs] !=
638	624	regs->regs[insn.mm_i_format.rt])
@@ -643,7 +629,6 @@ int mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn, · 4 unmodified lines
643	629	*contpc = regs->cp0_epc +
644	630	dec_insn.pc_inc + dec_insn.next_pc_inc;
645	631	return 1;
646		− break;
647	632	case mm_jalx32_op:
648	633	regs->regs[31] = regs->cp0_epc +
649	634	dec_insn.pc_inc + dec_insn.next_pc_inc;
@@ -652,7 +637,6 @@ int mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn, · 2 unmodified lines
652	637	*contpc <<= 28;
653	638	*contpc \|= (insn.j_format.target << 2);
654	639	return 1;
655		− break;
656	640	case mm_jals32_op:
657	641	case mm_jal32_op:
658	642	regs->regs[31] = regs->cp0_epc +
@@ -665,7 +649,6 @@ int mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn, · 6 unmodified lines
665	649	*contpc \|= (insn.j_format.target << 1);
666	650	set_isa16_mode(*contpc);
667	651	return 1;
668		− break;
669	652	}
670	653	return 0;
671	654	}
@@ -694,7 +677,6 @@ static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn, · 22 unmodified lines
694	677	case jr_op:
695	678	*contpc = regs->regs[insn.r_format.rs];
696	679	return 1;
697		− break;
698	680	}
699	681	break;
700	682	case bcond_op:
@@ -716,7 +698,6 @@ static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn, · 15 unmodified lines
716	698	dec_insn.pc_inc +
717	699	dec_insn.next_pc_inc;
718	700	return 1;
719		− break;
720	701	case bgezal_op:
721	702	case bgezall_op:
722	703	regs->regs[31] = regs->cp0_epc +
@@ -734,7 +715,6 @@ static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn, · 11 unmodified lines
734	715	dec_insn.pc_inc +
735	716	dec_insn.next_pc_inc;
736	717	return 1;
737		− break;
738	718	}
739	719	break;
740	720	case jalx_op:
@@ -752,7 +732,6 @@ static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn, · 11 unmodified lines
752	732	/* Set microMIPS mode bit: XOR for jalx. */
753	733	*contpc ^= bit;
754	734	return 1;
755		− break;
756	735	case beq_op:
757	736	case beql_op:
758	737	if (regs->regs[insn.i_format.rs] ==
@@ -765,7 +744,6 @@ static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn, · 6 unmodified lines
765	744	dec_insn.pc_inc +
766	745	dec_insn.next_pc_inc;
767	746	return 1;
768		− break;
769	747	case bne_op:
770	748	case bnel_op:
771	749	if (regs->regs[insn.i_format.rs] !=
@@ -778,7 +756,6 @@ static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn, · 6 unmodified lines
778	756	dec_insn.pc_inc +
779	757	dec_insn.next_pc_inc;
780	758	return 1;
781		− break;
782	759	case blez_op:
783	760	case blezl_op:
784	761	if ((long)regs->regs[insn.i_format.rs] <= 0)
@@ -790,7 +767,6 @@ static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn, · 5 unmodified lines
790	767	dec_insn.pc_inc +
791	768	dec_insn.next_pc_inc;
792	769	return 1;
793		− break;
794	770	case bgtz_op:
795	771	case bgtzl_op:
796	772	if ((long)regs->regs[insn.i_format.rs] > 0)
@@ -802,7 +778,6 @@ static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn, · 5 unmodified lines
802	778	dec_insn.pc_inc +
803	779	dec_insn.next_pc_inc;
804	780	return 1;
805		− break;
806	781	#ifdef CONFIG_CPU_CAVIUM_OCTEON
807	782	case lwc2_op: /* This is bbit0 on Octeon */
808	783	if ((regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt)) == 0)
@@ -856,7 +831,6 @@ static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn, · 47 unmodified lines
856	831	dec_insn.pc_inc +
857	832	dec_insn.next_pc_inc;
858	833	return 1;
859		− break;
860	834	case 1: /* bc1t */
861	835	case 3: /* bc1tl */
862	836	if (fcr31 & (1 << bit))
@@ -868,7 +842,6 @@ static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn, · 5 unmodified lines
868	842	dec_insn.pc_inc +
869	843	dec_insn.next_pc_inc;
870	844	return 1;
871		− break;
872	845	}
873	846	}
874	847	break;

arch/mips/mm/c-octeon.c+14−0

@@ -224,6 +224,20 @@ static void probe_octeon(void) · 223 unmodified lines
224	224	c->options \|= MIPS_CPU_PREFETCH;
225	225	break;
226	226
	227	+ case CPU_CAVIUM_OCTEON3:
	228	+ c->icache.linesz = 128;
	229	+ c->icache.sets = 16;
	230	+ c->icache.ways = 39;
	231	+ c->icache.flags \|= MIPS_CACHE_VTAG;
	232	+ icache_size = c->icache.sets * c->icache.ways * c->icache.linesz;
	233	+
	234	+ c->dcache.linesz = 128;
	235	+ c->dcache.ways = 32;
	236	+ c->dcache.sets = 8;
	237	+ dcache_size = c->dcache.sets * c->dcache.ways * c->dcache.linesz;
	238	+ c->options \|= MIPS_CPU_PREFETCH;
	239	+ break;
	240	+
227	241	default:
228	242	panic("Unsupported Cavium Networks CPU type");
229	243	break;

arch/mips/mm/dma-default.c+11−7

@@ -50,16 +50,20 @@ static inline struct page dma_addr_to_page(struct device dev, · 49 unmodified lines
50	50	}
51	51
52	52	/*
	53	+ * The affected CPUs below in 'cpu_needs_post_dma_flush()' can
	54	+ * speculatively fill random cachelines with stale data at any time,
	55	+ * requiring an extra flush post-DMA.
	56	+ *
53	57	* Warning on the terminology - Linux calls an uncached area coherent;
54	58	* MIPS terminology calls memory areas with hardware maintained coherency
55	59	* coherent.
56	60	*/
57		−
58		−static inline int cpu_is_noncoherent_r10000(struct device *dev)
	61	+static inline int cpu_needs_post_dma_flush(struct device *dev)
59	62	{
60	63	return !plat_device_is_coherent(dev) &&
61		− (current_cpu_type() == CPU_R10000 \|\|
62		− current_cpu_type() == CPU_R12000);
	64	+ (boot_cpu_type() == CPU_R10000 \|\|
	65	+ boot_cpu_type() == CPU_R12000 \|\|
	66	+ boot_cpu_type() == CPU_BMIPS5000);
63	67	}
64	68
65	69	static gfp_t massage_gfp_flags(const struct device *dev, gfp_t gfp)
@@ -230,7 +234,7 @@ static inline void __dma_sync(struct page *page, · 164 unmodified lines
230	234	static void mips_dma_unmap_page(struct device *dev, dma_addr_t dma_addr,
231	235	size_t size, enum dma_data_direction direction, struct dma_attrs *attrs)
232	236	{
233		− if (cpu_is_noncoherent_r10000(dev))
	237	+ if (cpu_needs_post_dma_flush(dev))
234	238	__dma_sync(dma_addr_to_page(dev, dma_addr),
235	239	dma_addr & ~PAGE_MASK, size, direction);
236	240
@@ -284,7 +288,7 @@ static void mips_dma_unmap_sg(struct device dev, struct scatterlist sg, · 47 unmodified lines
284	288	static void mips_dma_sync_single_for_cpu(struct device *dev,
285	289	dma_addr_t dma_handle, size_t size, enum dma_data_direction direction)
286	290	{
287		− if (cpu_is_noncoherent_r10000(dev))
	291	+ if (cpu_needs_post_dma_flush(dev))
288	292	__dma_sync(dma_addr_to_page(dev, dma_handle),
289	293	dma_handle & ~PAGE_MASK, size, direction);
290	294	}
@@ -305,7 +309,7 @@ static void mips_dma_sync_sg_for_cpu(struct device *dev, · 14 unmodified lines
305	309
306	310	/* Make sure that gcc doesn't leave the empty loop body. */
307	311	for (i = 0; i < nelems; i++, sg++) {
308		− if (cpu_is_noncoherent_r10000(dev))
	312	+ if (cpu_needs_post_dma_flush(dev))
309	313	__dma_sync(sg_page(sg), sg->offset, sg->length,
310	314	direction);
311	315	}

arch/mips/mm/gup.c+2−1

@@ -12,6 +12,7 @@ · 11 unmodified lines
12	12	#include <linux/swap.h>
13	13	#include <linux/hugetlb.h>
14	14
	15	+#include <asm/cpu-features.h>
15	16	#include <asm/pgtable.h>
16	17
17	18	static inline pte_t gup_get_pte(pte_t *ptep)
@@ -273,7 +274,7 @@ int get_user_pages_fast(unsigned long start, int nr_pages, int write, · 255 unmodified lines
273	274	len = (unsigned long) nr_pages << PAGE_SHIFT;
274	275
275	276	end = start + len;
276		− if (end < start)
	277	+ if (end < start \|\| cpu_has_dc_aliases)
277	278	goto slow_irqon;
278	279
279	280	/* XXX: batch / limit 'nr' */

arch/mips/mm/init.c+1−0

@@ -254,6 +254,7 @@ void copy_from_user_page(struct vm_area_struct *vma, · 253 unmodified lines
254	254	SetPageDcacheDirty(page);
255	255	}
256	256	}
	257	+EXPORT_SYMBOL_GPL(copy_from_user_page);
257	258
258	259	void __init fixrange_init(unsigned long start, unsigned long end,
259	260	pgd_t *pgd_base)

arch/mips/mm/tlb-funcs.S+2−0

@@ -16,10 +16,12 @@ · 15 unmodified lines
16	16
17	17	#define FASTPATH_SIZE 128
18	18
	19	+#ifdef CONFIG_MIPS_PGD_C0_CONTEXT
19	20	LEAF(tlbmiss_handler_setup_pgd)
20	21	.space 16 * 4
21	22	END(tlbmiss_handler_setup_pgd)
22	23	EXPORT(tlbmiss_handler_setup_pgd_end)
	24	+#endif
23	25
24	26	LEAF(handle_tlbm)
25	27	.space FASTPATH_SIZE * 4

arch/mips/mm/tlbex.c+2−0

@@ -85,6 +85,7 @@ static int use_bbit_insns(void) · 84 unmodified lines
85	85	case CPU_CAVIUM_OCTEON:
86	86	case CPU_CAVIUM_OCTEON_PLUS:
87	87	case CPU_CAVIUM_OCTEON2:
	88	+ case CPU_CAVIUM_OCTEON3:
88	89	return 1;
89	90	default:
90	91	return 0;
@@ -95,6 +96,7 @@ static int use_lwx_insns(void) · 4 unmodified lines
95	96	{
96	97	switch (current_cpu_type()) {
97	98	case CPU_CAVIUM_OCTEON2:
	99	+ case CPU_CAVIUM_OCTEON3:
98	100	return 1;
99	101	default:
100	102	return 0;

arch/mips/netlogic/Kconfig+9−0

@@ -19,6 +19,15 @@ config DT_XLP_SVP · 18 unmodified lines
19	19	pointer to the kernel. The corresponding DTS file is at
20	20	arch/mips/netlogic/dts/xlp_svp.dts
21	21
	22	+config DT_XLP_FVP
	23	+ bool "Built-in device tree for XLP FVP boards"
	24	+ default y
	25	+ help
	26	+ Add an FDT blob for XLP FVP board into the kernel.
	27	+ This DTB will be used if the firmware does not pass in a DTB
	28	+ pointer to the kernel. The corresponding DTS file is at
	29	+ arch/mips/netlogic/dts/xlp_fvp.dts
	30	+
22	31	config NLM_MULTINODE
23	32	bool "Support for multi-chip boards"
24	33	depends on NLM_XLP_BOARD

arch/mips/netlogic/common/smp.c+1−3

@@ -106,9 +106,7 @@ void nlm_early_init_secondary(int cpu) · 105 unmodified lines
106	106	{
107	107	change_c0_config(CONF_CM_CMASK, 0x3);
108	108	#ifdef CONFIG_CPU_XLP
109		− /* mmu init, once per core */
110		− if (cpu % NLM_THREADS_PER_CORE == 0)
111		− xlp_mmu_init();
	109	+ xlp_mmu_init();
112	110	#endif
113	111	write_c0_ebase(nlm_current_node()->ebase);
114	112	}

arch/mips/netlogic/common/time.c+2−1

@@ -45,6 +45,7 @@ · 44 unmodified lines
45	45	#if defined(CONFIG_CPU_XLP)
46	46	#include <asm/netlogic/xlp-hal/iomap.h>
47	47	#include <asm/netlogic/xlp-hal/xlp.h>
	48	+#include <asm/netlogic/xlp-hal/sys.h>
48	49	#include <asm/netlogic/xlp-hal/pic.h>
49	50	#elif defined(CONFIG_CPU_XLR)
50	51	#include <asm/netlogic/xlr/iomap.h>
@@ -91,7 +92,7 @@ static void nlm_init_pic_timer(void) · 40 unmodified lines
91	92	csrc_pic.read = nlm_get_pic_timer;
92	93	}
93	94	csrc_pic.rating = 1000;
94		− clocksource_register_hz(&csrc_pic, PIC_CLK_HZ);
	95	+ clocksource_register_hz(&csrc_pic, pic_timer_freq());
95	96	}
96	97
97	98	void __init plat_time_init(void)

arch/mips/netlogic/dts/Makefile+1−0

@@ -1,2 +1,3 @@
1	1	obj-$(CONFIG_DT_XLP_EVP) := xlp_evp.dtb.o
2	2	obj-$(CONFIG_DT_XLP_SVP) += xlp_svp.dtb.o
	3	+obj-$(CONFIG_DT_XLP_FVP) += xlp_fvp.dtb.o

arch/mips/netlogic/dts/xlp_evp.dts+1−8

@@ -9,19 +9,12 @@ · 8 unmodified lines
9	9	#address-cells = <2>;
10	10	#size-cells = <2>;
11	11
12		− memory {
13		− device_type = "memory";
14		− reg = <0 0x00100000 0 0x0FF00000 // 255M at 1M
15		− 0 0x20000000 0 0xa0000000 // 2560M at 512M
16		− 0 0xe0000000 1 0x00000000>;
17		− };
18		−
19	12	soc {
20	13	#address-cells = <2>;
21	14	#size-cells = <1>;
22	15	compatible = "simple-bus";
23	16	ranges = <0 0 0 0x18000000 0x04000000 // PCIe CFG
24		− 1 0 0 0x16000000 0x01000000>; // GBU chipselects
	17	+ 1 0 0 0x16000000 0x02000000>; // GBU chipselects
25	18
26	19	serial0: serial@30000 {
27	20	device_type = "serial";

arch/mips/netlogic/dts/xlp_fvp.dts+118−0

@@ -0,0 +1,118 @@
	1	+/*
	2	+ * XLP2XX Device Tree Source for FVP boards
	3	+ */
	4	+
	5	+/dts-v1/;
	6	+/ {
	7	+ model = "netlogic,XLP-FVP";
	8	+ compatible = "netlogic,xlp";
	9	+ #address-cells = <2>;
	10	+ #size-cells = <2>;
	11	+
	12	+ soc {
	13	+ #address-cells = <2>;
	14	+ #size-cells = <1>;
	15	+ compatible = "simple-bus";
	16	+ ranges = <0 0 0 0x18000000 0x04000000 // PCIe CFG
	17	+ 1 0 0 0x16000000 0x02000000>; // GBU chipselects
	18	+
	19	+ serial0: serial@30000 {
	20	+ device_type = "serial";
	21	+ compatible = "ns16550";
	22	+ reg = <0 0x30100 0xa00>;
	23	+ reg-shift = <2>;
	24	+ reg-io-width = <4>;
	25	+ clock-frequency = <133333333>;
	26	+ interrupt-parent = <&pic>;
	27	+ interrupts = <17>;
	28	+ };
	29	+ serial1: serial@31000 {
	30	+ device_type = "serial";
	31	+ compatible = "ns16550";
	32	+ reg = <0 0x31100 0xa00>;
	33	+ reg-shift = <2>;
	34	+ reg-io-width = <4>;
	35	+ clock-frequency = <133333333>;
	36	+ interrupt-parent = <&pic>;
	37	+ interrupts = <18>;
	38	+ };
	39	+ i2c0: ocores@37100 {
	40	+ compatible = "opencores,i2c-ocores";
	41	+ #address-cells = <1>;
	42	+ #size-cells = <0>;
	43	+ reg = <0 0x37100 0x20>;
	44	+ reg-shift = <2>;
	45	+ reg-io-width = <4>;
	46	+ clock-frequency = <32000000>;
	47	+ interrupt-parent = <&pic>;
	48	+ interrupts = <30>;
	49	+ };
	50	+ i2c1: ocores@37120 {
	51	+ compatible = "opencores,i2c-ocores";
	52	+ #address-cells = <1>;
	53	+ #size-cells = <0>;
	54	+ reg = <0 0x37120 0x20>;
	55	+ reg-shift = <2>;
	56	+ reg-io-width = <4>;
	57	+ clock-frequency = <32000000>;
	58	+ interrupt-parent = <&pic>;
	59	+ interrupts = <31>;
	60	+
	61	+ rtc@68 {
	62	+ compatible = "dallas,ds1374";
	63	+ reg = <0x68>;
	64	+ };
	65	+
	66	+ dtt@4c {
	67	+ compatible = "national,lm90";
	68	+ reg = <0x4c>;
	69	+ };
	70	+ };
	71	+ pic: pic@4000 {
	72	+ compatible = "netlogic,xlp-pic";
	73	+ #address-cells = <0>;
	74	+ #interrupt-cells = <1>;
	75	+ reg = <0 0x4000 0x200>;
	76	+ interrupt-controller;
	77	+ };
	78	+
	79	+ nor_flash@1,0 {
	80	+ compatible = "cfi-flash";
	81	+ #address-cells = <1>;
	82	+ #size-cells = <1>;
	83	+ bank-width = <2>;
	84	+ reg = <1 0 0x1000000>;
	85	+
	86	+ partition@0 {
	87	+ label = "x-loader";
	88	+ reg = <0x0 0x100000>; /* 1M */
	89	+ read-only;
	90	+ };
	91	+
	92	+ partition@100000 {
	93	+ label = "u-boot";
	94	+ reg = <0x100000 0x100000>; /* 1M */
	95	+ };
	96	+
	97	+ partition@200000 {
	98	+ label = "kernel";
	99	+ reg = <0x200000 0x500000>; /* 5M */
	100	+ };
	101	+
	102	+ partition@700000 {
	103	+ label = "rootfs";
	104	+ reg = <0x700000 0x800000>; /* 8M */
	105	+ };
	106	+
	107	+ partition@f00000 {
	108	+ label = "env";
	109	+ reg = <0xf00000 0x100000>; /* 1M */
	110	+ read-only;
	111	+ };
	112	+ };
	113	+ };
	114	+
	115	+ chosen {
	116	+ bootargs = "console=ttyS0,115200 rdinit=/sbin/init";
	117	+ };
	118	+};

arch/mips/netlogic/dts/xlp_svp.dts+1−8

@@ -9,19 +9,12 @@ · 8 unmodified lines
9	9	#address-cells = <2>;
10	10	#size-cells = <2>;
11	11
12		− memory {
13		− device_type = "memory";
14		− reg = <0 0x00100000 0 0x0FF00000 // 255M at 1M
15		− 0 0x20000000 0 0xa0000000 // 2560M at 512M
16		− 0 0xe0000000 0 0x40000000>;
17		− };
18		−
19	12	soc {
20	13	#address-cells = <2>;
21	14	#size-cells = <1>;
22	15	compatible = "simple-bus";
23	16	ranges = <0 0 0 0x18000000 0x04000000 // PCIe CFG
24		− 1 0 0 0x16000000 0x01000000>; // GBU chipselects
	17	+ 1 0 0 0x16000000 0x02000000>; // GBU chipselects
25	18
26	19	serial0: serial@30000 {
27	20	device_type = "serial";

arch/mips/netlogic/xlp/Makefile+1−0

@@ -1,3 +1,4 @@
1	1	obj-y += setup.o nlm_hal.o cop2-ex.o dt.o
2	2	obj-$(CONFIG_SMP) += wakeup.o
3	3	obj-$(CONFIG_USB) += usb-init.o
	4	+obj-$(CONFIG_USB) += usb-init-xlp2.o

arch/mips/netlogic/xlp/dt.c+7−1

@@ -39,12 +39,18 @@ · 38 unmodified lines
39	39	#include <linux/of_platform.h>
40	40	#include <linux/of_device.h>
41	41
42		−extern u32 __dtb_xlp_evp_begin[], __dtb_xlp_svp_begin[], __dtb_start[];
	42	+extern u32 __dtb_xlp_evp_begin[], __dtb_xlp_svp_begin[],
	43	+ __dtb_xlp_fvp_begin[], __dtb_start[];
43	44
44	45	void __init xlp_dt_init(void fdtp)
45	46	{
46	47	if (!fdtp) {
47	48	switch (current_cpu_data.processor_id & 0xff00) {
	49	+#ifdef CONFIG_DT_XLP_FVP
	50	+ case PRID_IMP_NETLOGIC_XLP2XX:
	51	+ fdtp = __dtb_xlp_fvp_begin;
	52	+ break;
	53	+#endif
48	54	#ifdef CONFIG_DT_XLP_SVP
49	55	case PRID_IMP_NETLOGIC_XLP3XX:
50	56	fdtp = __dtb_xlp_svp_begin;

arch/mips/netlogic/xlp/nlm_hal.c+202−35

@@ -44,6 +44,7 @@ · 43 unmodified lines
44	44	#include <asm/netlogic/haldefs.h>
45	45	#include <asm/netlogic/xlp-hal/iomap.h>
46	46	#include <asm/netlogic/xlp-hal/xlp.h>
	47	+#include <asm/netlogic/xlp-hal/bridge.h>
47	48	#include <asm/netlogic/xlp-hal/pic.h>
48	49	#include <asm/netlogic/xlp-hal/sys.h>
49	50
@@ -64,6 +65,7 @@ int nlm_irq_to_irt(int irq) · 14 unmodified lines
64	65	uint64_t pcibase;
65	66	int devoff, irt;
66	67
	68	+ devoff = 0;
67	69	switch (irq) {
68	70	case PIC_UART_0_IRQ:
69	71	devoff = XLP_IO_UART0_OFFSET(0);
@@ -71,44 +73,68 @@ int nlm_irq_to_irt(int irq) · 1 unmodified line
71	73	case PIC_UART_1_IRQ:
72	74	devoff = XLP_IO_UART1_OFFSET(0);
73	75	break;
74		− case PIC_EHCI_0_IRQ:
75		− devoff = XLP_IO_USB_EHCI0_OFFSET(0);
76		− break;
77		− case PIC_EHCI_1_IRQ:
78		− devoff = XLP_IO_USB_EHCI1_OFFSET(0);
79		− break;
80		− case PIC_OHCI_0_IRQ:
81		− devoff = XLP_IO_USB_OHCI0_OFFSET(0);
82		− break;
83		− case PIC_OHCI_1_IRQ:
84		− devoff = XLP_IO_USB_OHCI1_OFFSET(0);
85		− break;
86		− case PIC_OHCI_2_IRQ:
87		− devoff = XLP_IO_USB_OHCI2_OFFSET(0);
88		− break;
89		− case PIC_OHCI_3_IRQ:
90		− devoff = XLP_IO_USB_OHCI3_OFFSET(0);
91		− break;
92	76	case PIC_MMC_IRQ:
93	77	devoff = XLP_IO_SD_OFFSET(0);
94	78	break;
95		− case PIC_I2C_0_IRQ:
96		− devoff = XLP_IO_I2C0_OFFSET(0);
97		− break;
	79	+ case PIC_I2C_0_IRQ: /* I2C will be fixed up */
98	80	case PIC_I2C_1_IRQ:
99		− devoff = XLP_IO_I2C1_OFFSET(0);
	81	+ case PIC_I2C_2_IRQ:
	82	+ case PIC_I2C_3_IRQ:
	83	+ if (cpu_is_xlpii())
	84	+ devoff = XLP2XX_IO_I2C_OFFSET(0);
	85	+ else
	86	+ devoff = XLP_IO_I2C0_OFFSET(0);
100	87	break;
101	88	default:
102		− devoff = 0;
103		− break;
	89	+ if (cpu_is_xlpii()) {
	90	+ switch (irq) {
	91	+ /* XLP2XX has three XHCI USB controller */
	92	+ case PIC_2XX_XHCI_0_IRQ:
	93	+ devoff = XLP2XX_IO_USB_XHCI0_OFFSET(0);
	94	+ break;
	95	+ case PIC_2XX_XHCI_1_IRQ:
	96	+ devoff = XLP2XX_IO_USB_XHCI1_OFFSET(0);
	97	+ break;
	98	+ case PIC_2XX_XHCI_2_IRQ:
	99	+ devoff = XLP2XX_IO_USB_XHCI2_OFFSET(0);
	100	+ break;
	101	+ }
	102	+ } else {
	103	+ switch (irq) {
	104	+ case PIC_EHCI_0_IRQ:
	105	+ devoff = XLP_IO_USB_EHCI0_OFFSET(0);
	106	+ break;
	107	+ case PIC_EHCI_1_IRQ:
	108	+ devoff = XLP_IO_USB_EHCI1_OFFSET(0);
	109	+ break;
	110	+ case PIC_OHCI_0_IRQ:
	111	+ devoff = XLP_IO_USB_OHCI0_OFFSET(0);
	112	+ break;
	113	+ case PIC_OHCI_1_IRQ:
	114	+ devoff = XLP_IO_USB_OHCI1_OFFSET(0);
	115	+ break;
	116	+ case PIC_OHCI_2_IRQ:
	117	+ devoff = XLP_IO_USB_OHCI2_OFFSET(0);
	118	+ break;
	119	+ case PIC_OHCI_3_IRQ:
	120	+ devoff = XLP_IO_USB_OHCI3_OFFSET(0);
	121	+ break;
	122	+ }
	123	+ }
104	124	}
105	125
106	126	if (devoff != 0) {
107	127	pcibase = nlm_pcicfg_base(devoff);
108	128	irt = nlm_read_reg(pcibase, XLP_PCI_IRTINFO_REG) & 0xffff;
109		− /* HW bug, I2C 1 irt entry is off by one */
110		− if (irq == PIC_I2C_1_IRQ)
111		− irt = irt + 1;
	129	+ /* HW weirdness, I2C IRT entry has to be fixed up */
	130	+ switch (irq) {
	131	+ case PIC_I2C_1_IRQ:
	132	+ irt = irt + 1; break;
	133	+ case PIC_I2C_2_IRQ:
	134	+ irt = irt + 2; break;
	135	+ case PIC_I2C_3_IRQ:
	136	+ irt = irt + 3; break;
	137	+ }
112	138	} else if (irq >= PIC_PCIE_LINK_0_IRQ && irq <= PIC_PCIE_LINK_3_IRQ) {
113	139	/* HW bug, PCI IRT entries are bad on early silicon, fix */
114	140	irt = PIC_IRT_PCIE_LINK_INDEX(irq - PIC_PCIE_LINK_0_IRQ);
@@ -126,19 +152,160 @@ unsigned int nlm_get_core_frequency(int node, int core) · 11 unmodified lines
126	152
127	153	sysbase = nlm_get_node(node)->sysbase;
128	154	rstval = nlm_read_sys_reg(sysbase, SYS_POWER_ON_RESET_CFG);
129		− dfsval = nlm_read_sys_reg(sysbase, SYS_CORE_DFS_DIV_VALUE);
130		− pll_divf = ((rstval >> 10) & 0x7f) + 1;
131		− pll_divr = ((rstval >> 8) & 0x3) + 1;
132		− ext_div = ((rstval >> 30) & 0x3) + 1;
133		− dfs_div = ((dfsval >> (core * 4)) & 0xf) + 1;
134		−
135		− num = 800000000ULL * pll_divf;
136		− denom = 3 * pll_divr * ext_div * dfs_div;
	155	+ if (cpu_is_xlpii()) {
	156	+ num = 1000000ULL * (400 * 3 + 100 * (rstval >> 26));
	157	+ denom = 3;
	158	+ } else {
	159	+ dfsval = nlm_read_sys_reg(sysbase, SYS_CORE_DFS_DIV_VALUE);
	160	+ pll_divf = ((rstval >> 10) & 0x7f) + 1;
	161	+ pll_divr = ((rstval >> 8) & 0x3) + 1;
	162	+ ext_div = ((rstval >> 30) & 0x3) + 1;
	163	+ dfs_div = ((dfsval >> (core * 4)) & 0xf) + 1;
	164	+
	165	+ num = 800000000ULL * pll_divf;
	166	+ denom = 3 * pll_divr * ext_div * dfs_div;
	167	+ }
137	168	do_div(num, denom);
138	169	return (unsigned int)num;
139	170	}
140	171
	172	+/* Calculate Frequency to the PIC from PLL.
	173	+ * freq_out = ( ref_freq/2 * (6 + ctrl2[7:0]) + ctrl2[20:8]/2^13 ) /
	174	+ * ((2^ctrl0[7:5]) * Table(ctrl0[26:24]))
	175	+ */
	176	+static unsigned int nlm_2xx_get_pic_frequency(int node)
	177	+{
	178	+ u32 ctrl_val0, ctrl_val2, vco_post_div, pll_post_div;
	179	+ u32 mdiv, fdiv, pll_out_freq_den, reg_select, ref_div, pic_div;
	180	+ u64 ref_clk, sysbase, pll_out_freq_num, ref_clk_select;
	181	+
	182	+ sysbase = nlm_get_node(node)->sysbase;
	183	+
	184	+ /* Find ref_clk_base */
	185	+ ref_clk_select =
	186	+ (nlm_read_sys_reg(sysbase, SYS_POWER_ON_RESET_CFG) >> 18) & 0x3;
	187	+ switch (ref_clk_select) {
	188	+ case 0:
	189	+ ref_clk = 200000000ULL;
	190	+ ref_div = 3;
	191	+ break;
	192	+ case 1:
	193	+ ref_clk = 100000000ULL;
	194	+ ref_div = 1;
	195	+ break;
	196	+ case 2:
	197	+ ref_clk = 125000000ULL;
	198	+ ref_div = 1;
	199	+ break;
	200	+ case 3:
	201	+ ref_clk = 400000000ULL;
	202	+ ref_div = 3;
	203	+ break;
	204	+ }
	205	+
	206	+ /* Find the clock source PLL device for PIC */
	207	+ reg_select = (nlm_read_sys_reg(sysbase, SYS_CLK_DEV_SEL) >> 22) & 0x3;
	208	+ switch (reg_select) {
	209	+ case 0:
	210	+ ctrl_val0 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL0);
	211	+ ctrl_val2 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL2);
	212	+ break;
	213	+ case 1:
	214	+ ctrl_val0 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL0_DEVX(0));
	215	+ ctrl_val2 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL2_DEVX(0));
	216	+ break;
	217	+ case 2:
	218	+ ctrl_val0 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL0_DEVX(1));
	219	+ ctrl_val2 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL2_DEVX(1));
	220	+ break;
	221	+ case 3:
	222	+ ctrl_val0 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL0_DEVX(2));
	223	+ ctrl_val2 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL2_DEVX(2));
	224	+ break;
	225	+ }
	226	+
	227	+ vco_post_div = (ctrl_val0 >> 5) & 0x7;
	228	+ pll_post_div = (ctrl_val0 >> 24) & 0x7;
	229	+ mdiv = ctrl_val2 & 0xff;
	230	+ fdiv = (ctrl_val2 >> 8) & 0xfff;
	231	+
	232	+ /* Find PLL post divider value */
	233	+ switch (pll_post_div) {
	234	+ case 1:
	235	+ pll_post_div = 2;
	236	+ break;
	237	+ case 3:
	238	+ pll_post_div = 4;
	239	+ break;
	240	+ case 7:
	241	+ pll_post_div = 8;
	242	+ break;
	243	+ case 6:
	244	+ pll_post_div = 16;
	245	+ break;
	246	+ case 0:
	247	+ default:
	248	+ pll_post_div = 1;
	249	+ break;
	250	+ }
	251	+
	252	+ fdiv = fdiv/(1 << 13);
	253	+ pll_out_freq_num = ((ref_clk >> 1) * (6 + mdiv)) + fdiv;
	254	+ pll_out_freq_den = (1 << vco_post_div) * pll_post_div * 3;
	255	+
	256	+ if (pll_out_freq_den > 0)
	257	+ do_div(pll_out_freq_num, pll_out_freq_den);
	258	+
	259	+ /* PIC post divider, which happens after PLL */
	260	+ pic_div = (nlm_read_sys_reg(sysbase, SYS_CLK_DEV_DIV) >> 22) & 0x3;
	261	+ do_div(pll_out_freq_num, 1 << pic_div);
	262	+
	263	+ return pll_out_freq_num;
	264	+}
	265	+
	266	+unsigned int nlm_get_pic_frequency(int node)
	267	+{
	268	+ if (cpu_is_xlpii())
	269	+ return nlm_2xx_get_pic_frequency(node);
	270	+ else
	271	+ return 133333333;
	272	+}
	273	+
141	274	unsigned int nlm_get_cpu_frequency(void)
142	275	{
143	276	return nlm_get_core_frequency(0, 0);
144	277	}
	278	+
	279	+/*
	280	+ * Fills upto 8 pairs of entries containing the DRAM map of a node
	281	+ * if n < 0, get dram map for all nodes
	282	+ */
	283	+int xlp_get_dram_map(int n, uint64_t *dram_map)
	284	+{
	285	+ uint64_t bridgebase, base, lim;
	286	+ uint32_t val;
	287	+ int i, node, rv;
	288	+
	289	+ /* Look only at mapping on Node 0, we don't handle crazy configs */
	290	+ bridgebase = nlm_get_bridge_regbase(0);
	291	+ rv = 0;
	292	+ for (i = 0; i < 8; i++) {
	293	+ val = nlm_read_bridge_reg(bridgebase,
	294	+ BRIDGE_DRAM_NODE_TRANSLN(i));
	295	+ node = (val >> 1) & 0x3;
	296	+ if (n >= 0 && n != node)
	297	+ continue;
	298	+ val = nlm_read_bridge_reg(bridgebase, BRIDGE_DRAM_BAR(i));
	299	+ val = (val >> 12) & 0xfffff;
	300	+ base = (uint64_t) val << 20;
	301	+ val = nlm_read_bridge_reg(bridgebase, BRIDGE_DRAM_LIMIT(i));
	302	+ val = (val >> 12) & 0xfffff;
	303	+ if (val == 0) /* BAR not used */
	304	+ continue;
	305	+ lim = ((uint64_t)val + 1) << 20;
	306	+ dram_map[rv] = base;
	307	+ dram_map[rv + 1] = lim;
	308	+ rv += 2;
	309	+ }
	310	+ return rv;
	311	+}

arch/mips/netlogic/xlp/setup.c+43−7

@@ -73,6 +73,23 @@ static void nlm_fixup_mem(void) · 72 unmodified lines
73	73	}
74	74	}
75	75
	76	+static void __init xlp_init_mem_from_bars(void)
	77	+{
	78	+ uint64_t map[16];
	79	+ int i, n;
	80	+
	81	+ n = xlp_get_dram_map(-1, map); /* -1: info for all nodes */
	82	+ for (i = 0; i < n; i += 2) {
	83	+ /* exclude 0x1000_0000-0x2000_0000, u-boot device */
	84	+ if (map[i] <= 0x10000000 && map[i+1] > 0x10000000)
	85	+ map[i+1] = 0x10000000;
	86	+ if (map[i] > 0x10000000 && map[i] < 0x20000000)
	87	+ map[i] = 0x20000000;
	88	+
	89	+ add_memory_region(map[i], map[i+1] - map[i], BOOT_MEM_RAM);
	90	+ }
	91	+}
	92	+
76	93	void __init plat_mem_setup(void)
77	94	{
78	95	panic_timeout = 5;
@@ -82,12 +99,23 @@ void __init plat_mem_setup(void) · 3 unmodified lines
82	99
83	100	/* memory and bootargs from DT */
84	101	early_init_devtree(initial_boot_params);
	102	+
	103	+ if (boot_mem_map.nr_map == 0) {
	104	+ pr_info("Using DRAM BARs for memory map.\n");
	105	+ xlp_init_mem_from_bars();
	106	+ }
	107	+ /* Calculate and setup wired entries for mapped kernel */
85	108	nlm_fixup_mem();
86	109	}
87	110
88	111	const char *get_system_type(void)
89	112	{
90		− return "Netlogic XLP Series";
	113	+ switch (read_c0_prid() & 0xff00) {
	114	+ case PRID_IMP_NETLOGIC_XLP2XX:
	115	+ return "Broadcom XLPII Series";
	116	+ default:
	117	+ return "Netlogic XLP Series";
	118	+ }
91	119	}
92	120
93	121	void __init prom_free_prom_memory(void)
@@ -97,12 +125,20 @@ void __init prom_free_prom_memory(void) · 3 unmodified lines
97	125
98	126	void xlp_mmu_init(void)
99	127	{
100		− /* enable extended TLB and Large Fixed TLB */
101		− write_c0_config6(read_c0_config6() \| 0x24);
102		−
103		− /* set page mask of Fixed TLB in config7 */
104		− write_c0_config7(PM_DEFAULT_MASK >>
105		− (13 + (ffz(PM_DEFAULT_MASK >> 13) / 2)));
	128	+ u32 conf4;
	129	+
	130	+ if (cpu_is_xlpii()) {
	131	+ /* XLPII series has extended pagesize in config 4 */
	132	+ conf4 = read_c0_config4() & ~0x1f00u;
	133	+ write_c0_config4(conf4 \| ((PAGE_SHIFT - 10) / 2 << 8));
	134	+ } else {
	135	+ /* enable extended TLB and Large Fixed TLB */
	136	+ write_c0_config6(read_c0_config6() \| 0x24);
	137	+
	138	+ /* set page mask of extended Fixed TLB in config7 */
	139	+ write_c0_config7(PM_DEFAULT_MASK >>
	140	+ (13 + (ffz(PM_DEFAULT_MASK >> 13) / 2)));
	141	+ }
106	142	}
107	143
108	144	void nlm_percpu_init(int hwcpuid)

arch/mips/netlogic/xlp/usb-init-xlp2.c+218−0

@@ -0,0 +1,218 @@
	1	+/*
	2	+ * Copyright (c) 2003-2013 Broadcom Corporation
	3	+ * All Rights Reserved
	4	+ *
	5	+ * This software is available to you under a choice of one of two
	6	+ * licenses. You may choose to be licensed under the terms of the GNU
	7	+ * General Public License (GPL) Version 2, available from the file
	8	+ * COPYING in the main directory of this source tree, or the Broadcom
	9	+ * license below:
	10	+ *
	11	+ * Redistribution and use in source and binary forms, with or without
	12	+ * modification, are permitted provided that the following conditions
	13	+ * are met:
	14	+ *
	15	+ * 1. Redistributions of source code must retain the above copyright
	16	+ * notice, this list of conditions and the following disclaimer.
	17	+ * 2. Redistributions in binary form must reproduce the above copyright
	18	+ * notice, this list of conditions and the following disclaimer in
	19	+ * the documentation and/or other materials provided with the
	20	+ * distribution.
	21	+ *
	22	+ * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
	23	+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
	24	+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
	25	+ * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
	26	+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
	27	+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
	28	+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
	29	+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
	30	+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
	31	+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
	32	+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	33	+ */
	34	+
	35	+#include <linux/dma-mapping.h>
	36	+#include <linux/kernel.h>
	37	+#include <linux/delay.h>
	38	+#include <linux/init.h>
	39	+#include <linux/pci.h>
	40	+#include <linux/platform_device.h>
	41	+#include <linux/irq.h>
	42	+
	43	+#include <asm/netlogic/common.h>
	44	+#include <asm/netlogic/haldefs.h>
	45	+#include <asm/netlogic/xlp-hal/iomap.h>
	46	+#include <asm/netlogic/xlp-hal/xlp.h>
	47	+
	48	+#define XLPII_USB3_CTL_0 0xc0
	49	+#define XLPII_VAUXRST BIT(0)
	50	+#define XLPII_VCCRST BIT(1)
	51	+#define XLPII_NUM2PORT 9
	52	+#define XLPII_NUM3PORT 13
	53	+#define XLPII_RTUNEREQ BIT(20)
	54	+#define XLPII_MS_CSYSREQ BIT(21)
	55	+#define XLPII_XS_CSYSREQ BIT(22)
	56	+#define XLPII_RETENABLEN BIT(23)
	57	+#define XLPII_TX2RX BIT(24)
	58	+#define XLPII_XHCIREV BIT(25)
	59	+#define XLPII_ECCDIS BIT(26)
	60	+
	61	+#define XLPII_USB3_INT_REG 0xc2
	62	+#define XLPII_USB3_INT_MASK 0xc3
	63	+
	64	+#define XLPII_USB_PHY_TEST 0xc6
	65	+#define XLPII_PRESET BIT(0)
	66	+#define XLPII_ATERESET BIT(1)
	67	+#define XLPII_LOOPEN BIT(2)
	68	+#define XLPII_TESTPDHSP BIT(3)
	69	+#define XLPII_TESTPDSSP BIT(4)
	70	+#define XLPII_TESTBURNIN BIT(5)
	71	+
	72	+#define XLPII_USB_PHY_LOS_LV 0xc9
	73	+#define XLPII_LOSLEV 0
	74	+#define XLPII_LOSBIAS 5
	75	+#define XLPII_SQRXTX 8
	76	+#define XLPII_TXBOOST 11
	77	+#define XLPII_RSLKSEL 16
	78	+#define XLPII_FSEL 20
	79	+
	80	+#define XLPII_USB_RFCLK_REG 0xcc
	81	+#define XLPII_VVLD 30
	82	+
	83	+#define nlm_read_usb_reg(b, r) nlm_read_reg(b, r)
	84	+#define nlm_write_usb_reg(b, r, v) nlm_write_reg(b, r, v)
	85	+
	86	+#define nlm_xlpii_get_usb_pcibase(node, inst) \
	87	+ nlm_pcicfg_base(XLP2XX_IO_USB_OFFSET(node, inst))
	88	+#define nlm_xlpii_get_usb_regbase(node, inst) \
	89	+ (nlm_xlpii_get_usb_pcibase(node, inst) + XLP_IO_PCI_HDRSZ)
	90	+
	91	+static void xlpii_usb_ack(struct irq_data *data)
	92	+{
	93	+ u64 port_addr;
	94	+
	95	+ switch (data->irq) {
	96	+ case PIC_2XX_XHCI_0_IRQ:
	97	+ port_addr = nlm_xlpii_get_usb_regbase(0, 1);
	98	+ break;
	99	+ case PIC_2XX_XHCI_1_IRQ:
	100	+ port_addr = nlm_xlpii_get_usb_regbase(0, 2);
	101	+ break;
	102	+ case PIC_2XX_XHCI_2_IRQ:
	103	+ port_addr = nlm_xlpii_get_usb_regbase(0, 3);
	104	+ break;
	105	+ default:
	106	+ pr_err("No matching USB irq!\n");
	107	+ return;
	108	+ }
	109	+ nlm_write_usb_reg(port_addr, XLPII_USB3_INT_REG, 0xffffffff);
	110	+}
	111	+
	112	+static void nlm_xlpii_usb_hw_reset(int node, int port)
	113	+{
	114	+ u64 port_addr, xhci_base, pci_base;
	115	+ void __iomem *corebase;
	116	+ u32 val;
	117	+
	118	+ port_addr = nlm_xlpii_get_usb_regbase(node, port);
	119	+
	120	+ /* Set frequency */
	121	+ val = nlm_read_usb_reg(port_addr, XLPII_USB_PHY_LOS_LV);
	122	+ val &= ~(0x3f << XLPII_FSEL);
	123	+ val \|= (0x27 << XLPII_FSEL);
	124	+ nlm_write_usb_reg(port_addr, XLPII_USB_PHY_LOS_LV, val);
	125	+
	126	+ val = nlm_read_usb_reg(port_addr, XLPII_USB_RFCLK_REG);
	127	+ val \|= (1 << XLPII_VVLD);
	128	+ nlm_write_usb_reg(port_addr, XLPII_USB_RFCLK_REG, val);
	129	+
	130	+ /* PHY reset */
	131	+ val = nlm_read_usb_reg(port_addr, XLPII_USB_PHY_TEST);
	132	+ val &= (XLPII_ATERESET \| XLPII_LOOPEN \| XLPII_TESTPDHSP
	133	+ \| XLPII_TESTPDSSP \| XLPII_TESTBURNIN);
	134	+ nlm_write_usb_reg(port_addr, XLPII_USB_PHY_TEST, val);
	135	+
	136	+ /* Setup control register */
	137	+ val = XLPII_VAUXRST \| XLPII_VCCRST \| (1 << XLPII_NUM2PORT)
	138	+ \| (1 << XLPII_NUM3PORT) \| XLPII_MS_CSYSREQ \| XLPII_XS_CSYSREQ
	139	+ \| XLPII_RETENABLEN \| XLPII_XHCIREV;
	140	+ nlm_write_usb_reg(port_addr, XLPII_USB3_CTL_0, val);
	141	+
	142	+ /* Enable interrupts */
	143	+ nlm_write_usb_reg(port_addr, XLPII_USB3_INT_MASK, 0x00000001);
	144	+
	145	+ /* Clear all interrupts */
	146	+ nlm_write_usb_reg(port_addr, XLPII_USB3_INT_REG, 0xffffffff);
	147	+
	148	+ udelay(2000);
	149	+
	150	+ /* XHCI configuration at PCI mem */
	151	+ pci_base = nlm_xlpii_get_usb_pcibase(node, port);
	152	+ xhci_base = nlm_read_usb_reg(pci_base, 0x4) & ~0xf;
	153	+ corebase = ioremap(xhci_base, 0x10000);
	154	+ if (!corebase)
	155	+ return;
	156	+
	157	+ writel(0x240002, corebase + 0xc2c0);
	158	+ /* GCTL 0xc110 */
	159	+ val = readl(corebase + 0xc110);
	160	+ val &= ~(0x3 << 12);
	161	+ val \|= (1 << 12);
	162	+ writel(val, corebase + 0xc110);
	163	+ udelay(100);
	164	+
	165	+ /* PHYCFG 0xc200 */
	166	+ val = readl(corebase + 0xc200);
	167	+ val &= ~(1 << 6);
	168	+ writel(val, corebase + 0xc200);
	169	+ udelay(100);
	170	+
	171	+ /* PIPECTL 0xc2c0 */
	172	+ val = readl(corebase + 0xc2c0);
	173	+ val &= ~(1 << 17);
	174	+ writel(val, corebase + 0xc2c0);
	175	+
	176	+ iounmap(corebase);
	177	+}
	178	+
	179	+static int __init nlm_platform_xlpii_usb_init(void)
	180	+{
	181	+ if (!cpu_is_xlpii())
	182	+ return 0;
	183	+
	184	+ pr_info("Initializing 2XX USB Interface\n");
	185	+ nlm_xlpii_usb_hw_reset(0, 1);
	186	+ nlm_xlpii_usb_hw_reset(0, 2);
	187	+ nlm_xlpii_usb_hw_reset(0, 3);
	188	+ nlm_set_pic_extra_ack(0, PIC_2XX_XHCI_0_IRQ, xlpii_usb_ack);
	189	+ nlm_set_pic_extra_ack(0, PIC_2XX_XHCI_1_IRQ, xlpii_usb_ack);
	190	+ nlm_set_pic_extra_ack(0, PIC_2XX_XHCI_2_IRQ, xlpii_usb_ack);
	191	+
	192	+ return 0;
	193	+}
	194	+
	195	+arch_initcall(nlm_platform_xlpii_usb_init);
	196	+
	197	+static u64 xlp_usb_dmamask = ~(u32)0;
	198	+
	199	+/* Fixup IRQ for USB devices on XLP the SoC PCIe bus */
	200	+static void nlm_usb_fixup_final(struct pci_dev *dev)
	201	+{
	202	+ dev->dev.dma_mask = &xlp_usb_dmamask;
	203	+ dev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
	204	+ switch (dev->devfn) {
	205	+ case 0x21:
	206	+ dev->irq = PIC_2XX_XHCI_0_IRQ;
	207	+ break;
	208	+ case 0x22:
	209	+ dev->irq = PIC_2XX_XHCI_1_IRQ;
	210	+ break;
	211	+ case 0x23:
	212	+ dev->irq = PIC_2XX_XHCI_2_IRQ;
	213	+ break;
	214	+ }
	215	+}
	216	+
	217	+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_NETLOGIC, PCI_DEVICE_ID_NLM_XHCI,
	218	+ nlm_usb_fixup_final);

arch/mips/netlogic/xlp/usb-init.c+4−2

@@ -75,8 +75,7 @@ static void nlm_usb_intr_en(int node, int port) · 74 unmodified lines
75	75	port_addr = nlm_get_usb_regbase(node, port);
76	76	val = nlm_read_usb_reg(port_addr, USB_INT_EN);
77	77	val = USB_CTRL_INTERRUPT_EN \| USB_OHCI_INTERRUPT_EN \|
78		− USB_OHCI_INTERRUPT1_EN \| USB_CTRL_INTERRUPT_EN \|
79		− USB_OHCI_INTERRUPT_EN \| USB_OHCI_INTERRUPT2_EN;
	78	+ USB_OHCI_INTERRUPT1_EN \| USB_OHCI_INTERRUPT2_EN;
80	79	nlm_write_usb_reg(port_addr, USB_INT_EN, val);
81	80	}
82	81
@@ -100,6 +99,9 @@ static void nlm_usb_hw_reset(int node, int port) · 17 unmodified lines
100	99
101	100	static int __init nlm_platform_usb_init(void)
102	101	{
	102	+ if (cpu_is_xlpii())
	103	+ return 0;
	104	+
103	105	pr_info("Initializing USB Interface\n");
104	106	nlm_usb_hw_reset(0, 0);
105	107	nlm_usb_hw_reset(0, 3);

arch/mips/netlogic/xlp/wakeup.c+6−4

@@ -58,10 +58,12 @@ static int xlp_wakeup_core(uint64_t sysbase, int node, int core) · 57 unmodified lines
58	58
59	59	coremask = (1 << core);
60	60
61		− /* Enable CPU clock */
62		− value = nlm_read_sys_reg(sysbase, SYS_CORE_DFS_DIS_CTRL);
63		− value &= ~coremask;
64		− nlm_write_sys_reg(sysbase, SYS_CORE_DFS_DIS_CTRL, value);
	61	+ /* Enable CPU clock in case of 8xx/3xx */
	62	+ if (!cpu_is_xlpii()) {
	63	+ value = nlm_read_sys_reg(sysbase, SYS_CORE_DFS_DIS_CTRL);
	64	+ value &= ~coremask;
	65	+ nlm_write_sys_reg(sysbase, SYS_CORE_DFS_DIS_CTRL, value);
	66	+ }
65	67
66	68	/* Remove CPU Reset */
67	69	value = nlm_read_sys_reg(sysbase, SYS_CPU_RESET);

arch/mips/pci/Makefile+1−0

@@ -41,6 +41,7 @@ obj-$(CONFIG_SIBYTE_BCM1x80) += pci-bcm1480.o pci-bcm1480ht.o · 40 unmodified lines
41	41	obj-$(CONFIG_SNI_RM) += fixup-sni.o ops-sni.o
42	42	obj-$(CONFIG_LANTIQ) += fixup-lantiq.o
43	43	obj-$(CONFIG_PCI_LANTIQ) += pci-lantiq.o ops-lantiq.o
	44	+obj-$(CONFIG_SOC_RT3883) += pci-rt3883.o
44	45	obj-$(CONFIG_TANBAC_TB0219) += fixup-tb0219.o
45	46	obj-$(CONFIG_TANBAC_TB0226) += fixup-tb0226.o
46	47	obj-$(CONFIG_TANBAC_TB0287) += fixup-tb0287.o

arch/mips/pci/pci-octeon.c+5−4

@@ -586,15 +586,16 @@ static int __init octeon_pci_setup(void) · 585 unmodified lines
586	586	else
587	587	octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_BIG;
588	588
589		− /* PCI I/O and PCI MEM values */
590		− set_io_port_base(OCTEON_PCI_IOSPACE_BASE);
591		− ioport_resource.start = 0;
592		− ioport_resource.end = OCTEON_PCI_IOSPACE_SIZE - 1;
593	589	if (!octeon_is_pci_host()) {
594	590	pr_notice("Not in host mode, PCI Controller not initialized\n");
595	591	return 0;
596	592	}
597	593
	594	+ /* PCI I/O and PCI MEM values */
	595	+ set_io_port_base(OCTEON_PCI_IOSPACE_BASE);
	596	+ ioport_resource.start = 0;
	597	+ ioport_resource.end = OCTEON_PCI_IOSPACE_SIZE - 1;
	598	+
598	599	pr_notice("%s Octeon big bar support\n",
599	600	(octeon_dma_bar_type ==
600	601	OCTEON_DMA_BAR_TYPE_BIG) ? "Enabling" : "Disabling");

arch/mips/pci/pci-rt3883.c+636−0

@@ -0,0 +1,636 @@
	1	+/*
	2	+ * Ralink RT3662/RT3883 SoC PCI support
	3	+ *
	4	+ * Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
	5	+ *
	6	+ * Parts of this file are based on Ralink's 2.6.21 BSP
	7	+ *
	8	+ * This program is free software; you can redistribute it and/or modify it
	9	+ * under the terms of the GNU General Public License version 2 as published
	10	+ * by the Free Software Foundation.
	11	+ */
	12	+
	13	+#include <linux/types.h>
	14	+#include <linux/pci.h>
	15	+#include <linux/io.h>
	16	+#include <linux/init.h>
	17	+#include <linux/delay.h>
	18	+#include <linux/interrupt.h>
	19	+#include <linux/module.h>
	20	+#include <linux/of.h>
	21	+#include <linux/of_irq.h>
	22	+#include <linux/of_pci.h>
	23	+#include <linux/platform_device.h>
	24	+
	25	+#include <asm/mach-ralink/rt3883.h>
	26	+#include <asm/mach-ralink/ralink_regs.h>
	27	+
	28	+#define RT3883_MEMORY_BASE 0x00000000
	29	+#define RT3883_MEMORY_SIZE 0x02000000
	30	+
	31	+#define RT3883_PCI_REG_PCICFG 0x00
	32	+#define RT3883_PCICFG_P2P_BR_DEVNUM_M 0xf
	33	+#define RT3883_PCICFG_P2P_BR_DEVNUM_S 16
	34	+#define RT3883_PCICFG_PCIRST BIT(1)
	35	+#define RT3883_PCI_REG_PCIRAW 0x04
	36	+#define RT3883_PCI_REG_PCIINT 0x08
	37	+#define RT3883_PCI_REG_PCIENA 0x0c
	38	+
	39	+#define RT3883_PCI_REG_CFGADDR 0x20
	40	+#define RT3883_PCI_REG_CFGDATA 0x24
	41	+#define RT3883_PCI_REG_MEMBASE 0x28
	42	+#define RT3883_PCI_REG_IOBASE 0x2c
	43	+#define RT3883_PCI_REG_ARBCTL 0x80
	44	+
	45	+#define RT3883_PCI_REG_BASE(_x) (0x1000 + (_x) * 0x1000)
	46	+#define RT3883_PCI_REG_BAR0SETUP(_x) (RT3883_PCI_REG_BASE((_x)) + 0x10)
	47	+#define RT3883_PCI_REG_IMBASEBAR0(_x) (RT3883_PCI_REG_BASE((_x)) + 0x18)
	48	+#define RT3883_PCI_REG_ID(_x) (RT3883_PCI_REG_BASE((_x)) + 0x30)
	49	+#define RT3883_PCI_REG_CLASS(_x) (RT3883_PCI_REG_BASE((_x)) + 0x34)
	50	+#define RT3883_PCI_REG_SUBID(_x) (RT3883_PCI_REG_BASE((_x)) + 0x38)
	51	+#define RT3883_PCI_REG_STATUS(_x) (RT3883_PCI_REG_BASE((_x)) + 0x50)
	52	+
	53	+#define RT3883_PCI_MODE_NONE 0
	54	+#define RT3883_PCI_MODE_PCI BIT(0)
	55	+#define RT3883_PCI_MODE_PCIE BIT(1)
	56	+#define RT3883_PCI_MODE_BOTH (RT3883_PCI_MODE_PCI \| RT3883_PCI_MODE_PCIE)
	57	+
	58	+#define RT3883_PCI_IRQ_COUNT 32
	59	+
	60	+#define RT3883_P2P_BR_DEVNUM 1
	61	+
	62	+struct rt3883_pci_controller {
	63	+ void __iomem *base;
	64	+ spinlock_t lock;
	65	+
	66	+ struct device_node *intc_of_node;
	67	+ struct irq_domain *irq_domain;
	68	+
	69	+ struct pci_controller pci_controller;
	70	+ struct resource io_res;
	71	+ struct resource mem_res;
	72	+
	73	+ bool pcie_ready;
	74	+};
	75	+
	76	+static inline struct rt3883_pci_controller *
	77	+pci_bus_to_rt3883_controller(struct pci_bus *bus)
	78	+{
	79	+ struct pci_controller *hose;
	80	+
	81	+ hose = (struct pci_controller *) bus->sysdata;
	82	+ return container_of(hose, struct rt3883_pci_controller, pci_controller);
	83	+}
	84	+
	85	+static inline u32 rt3883_pci_r32(struct rt3883_pci_controller *rpc,
	86	+ unsigned reg)
	87	+{
	88	+ return ioread32(rpc->base + reg);
	89	+}
	90	+
	91	+static inline void rt3883_pci_w32(struct rt3883_pci_controller *rpc,
	92	+ u32 val, unsigned reg)
	93	+{
	94	+ iowrite32(val, rpc->base + reg);
	95	+}
	96	+
	97	+static inline u32 rt3883_pci_get_cfgaddr(unsigned int bus, unsigned int slot,
	98	+ unsigned int func, unsigned int where)
	99	+{
	100	+ return (bus << 16) \| (slot << 11) \| (func << 8) \| (where & 0xfc) \|
	101	+ 0x80000000;
	102	+}
	103	+
	104	+static u32 rt3883_pci_read_cfg32(struct rt3883_pci_controller *rpc,
	105	+ unsigned bus, unsigned slot,
	106	+ unsigned func, unsigned reg)
	107	+{
	108	+ unsigned long flags;
	109	+ u32 address;
	110	+ u32 ret;
	111	+
	112	+ address = rt3883_pci_get_cfgaddr(bus, slot, func, reg);
	113	+
	114	+ spin_lock_irqsave(&rpc->lock, flags);
	115	+ rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR);
	116	+ ret = rt3883_pci_r32(rpc, RT3883_PCI_REG_CFGDATA);
	117	+ spin_unlock_irqrestore(&rpc->lock, flags);
	118	+
	119	+ return ret;
	120	+}
	121	+
	122	+static void rt3883_pci_write_cfg32(struct rt3883_pci_controller *rpc,
	123	+ unsigned bus, unsigned slot,
	124	+ unsigned func, unsigned reg, u32 val)
	125	+{
	126	+ unsigned long flags;
	127	+ u32 address;
	128	+
	129	+ address = rt3883_pci_get_cfgaddr(bus, slot, func, reg);
	130	+
	131	+ spin_lock_irqsave(&rpc->lock, flags);
	132	+ rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR);
	133	+ rt3883_pci_w32(rpc, val, RT3883_PCI_REG_CFGDATA);
	134	+ spin_unlock_irqrestore(&rpc->lock, flags);
	135	+}
	136	+
	137	+static void rt3883_pci_irq_handler(unsigned int irq, struct irq_desc *desc)
	138	+{
	139	+ struct rt3883_pci_controller *rpc;
	140	+ u32 pending;
	141	+
	142	+ rpc = irq_get_handler_data(irq);
	143	+
	144	+ pending = rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIINT) &
	145	+ rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA);
	146	+
	147	+ if (!pending) {
	148	+ spurious_interrupt();
	149	+ return;
	150	+ }
	151	+
	152	+ while (pending) {
	153	+ unsigned bit = __ffs(pending);
	154	+
	155	+ irq = irq_find_mapping(rpc->irq_domain, bit);
	156	+ generic_handle_irq(irq);
	157	+
	158	+ pending &= ~BIT(bit);
	159	+ }
	160	+}
	161	+
	162	+static void rt3883_pci_irq_unmask(struct irq_data *d)
	163	+{
	164	+ struct rt3883_pci_controller *rpc;
	165	+ u32 t;
	166	+
	167	+ rpc = irq_data_get_irq_chip_data(d);
	168	+
	169	+ t = rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA);
	170	+ rt3883_pci_w32(rpc, t \| BIT(d->hwirq), RT3883_PCI_REG_PCIENA);
	171	+ /* flush write */
	172	+ rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA);
	173	+}
	174	+
	175	+static void rt3883_pci_irq_mask(struct irq_data *d)
	176	+{
	177	+ struct rt3883_pci_controller *rpc;
	178	+ u32 t;
	179	+
	180	+ rpc = irq_data_get_irq_chip_data(d);
	181	+
	182	+ t = rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA);
	183	+ rt3883_pci_w32(rpc, t & ~BIT(d->hwirq), RT3883_PCI_REG_PCIENA);
	184	+ /* flush write */
	185	+ rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA);
	186	+}
	187	+
	188	+static struct irq_chip rt3883_pci_irq_chip = {
	189	+ .name = "RT3883 PCI",
	190	+ .irq_mask = rt3883_pci_irq_mask,
	191	+ .irq_unmask = rt3883_pci_irq_unmask,
	192	+ .irq_mask_ack = rt3883_pci_irq_mask,
	193	+};
	194	+
	195	+static int rt3883_pci_irq_map(struct irq_domain *d, unsigned int irq,
	196	+ irq_hw_number_t hw)
	197	+{
	198	+ irq_set_chip_and_handler(irq, &rt3883_pci_irq_chip, handle_level_irq);
	199	+ irq_set_chip_data(irq, d->host_data);
	200	+
	201	+ return 0;
	202	+}
	203	+
	204	+static const struct irq_domain_ops rt3883_pci_irq_domain_ops = {
	205	+ .map = rt3883_pci_irq_map,
	206	+ .xlate = irq_domain_xlate_onecell,
	207	+};
	208	+
	209	+static int rt3883_pci_irq_init(struct device *dev,
	210	+ struct rt3883_pci_controller *rpc)
	211	+{
	212	+ int irq;
	213	+
	214	+ irq = irq_of_parse_and_map(rpc->intc_of_node, 0);
	215	+ if (irq == 0) {
	216	+ dev_err(dev, "%s has no IRQ",
	217	+ of_node_full_name(rpc->intc_of_node));
	218	+ return -EINVAL;
	219	+ }
	220	+
	221	+ /* disable all interrupts */
	222	+ rt3883_pci_w32(rpc, 0, RT3883_PCI_REG_PCIENA);
	223	+
	224	+ rpc->irq_domain =
	225	+ irq_domain_add_linear(rpc->intc_of_node, RT3883_PCI_IRQ_COUNT,
	226	+ &rt3883_pci_irq_domain_ops,
	227	+ rpc);
	228	+ if (!rpc->irq_domain) {
	229	+ dev_err(dev, "unable to add IRQ domain\n");
	230	+ return -ENODEV;
	231	+ }
	232	+
	233	+ irq_set_handler_data(irq, rpc);
	234	+ irq_set_chained_handler(irq, rt3883_pci_irq_handler);
	235	+
	236	+ return 0;
	237	+}
	238	+
	239	+static int rt3883_pci_config_read(struct pci_bus *bus, unsigned int devfn,
	240	+ int where, int size, u32 *val)
	241	+{
	242	+ struct rt3883_pci_controller *rpc;
	243	+ unsigned long flags;
	244	+ u32 address;
	245	+ u32 data;
	246	+
	247	+ rpc = pci_bus_to_rt3883_controller(bus);
	248	+
	249	+ if (!rpc->pcie_ready && bus->number == 1)
	250	+ return PCIBIOS_DEVICE_NOT_FOUND;
	251	+
	252	+ address = rt3883_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
	253	+ PCI_FUNC(devfn), where);
	254	+
	255	+ spin_lock_irqsave(&rpc->lock, flags);
	256	+ rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR);
	257	+ data = rt3883_pci_r32(rpc, RT3883_PCI_REG_CFGDATA);
	258	+ spin_unlock_irqrestore(&rpc->lock, flags);
	259	+
	260	+ switch (size) {
	261	+ case 1:
	262	+ *val = (data >> ((where & 3) << 3)) & 0xff;
	263	+ break;
	264	+ case 2:
	265	+ *val = (data >> ((where & 3) << 3)) & 0xffff;
	266	+ break;
	267	+ case 4:
	268	+ *val = data;
	269	+ break;
	270	+ }
	271	+
	272	+ return PCIBIOS_SUCCESSFUL;
	273	+}
	274	+
	275	+static int rt3883_pci_config_write(struct pci_bus *bus, unsigned int devfn,
	276	+ int where, int size, u32 val)
	277	+{
	278	+ struct rt3883_pci_controller *rpc;
	279	+ unsigned long flags;
	280	+ u32 address;
	281	+ u32 data;
	282	+
	283	+ rpc = pci_bus_to_rt3883_controller(bus);
	284	+
	285	+ if (!rpc->pcie_ready && bus->number == 1)
	286	+ return PCIBIOS_DEVICE_NOT_FOUND;
	287	+
	288	+ address = rt3883_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
	289	+ PCI_FUNC(devfn), where);
	290	+
	291	+ spin_lock_irqsave(&rpc->lock, flags);
	292	+ rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR);
	293	+ data = rt3883_pci_r32(rpc, RT3883_PCI_REG_CFGDATA);
	294	+
	295	+ switch (size) {
	296	+ case 1:
	297	+ data = (data & ~(0xff << ((where & 3) << 3))) \|
	298	+ (val << ((where & 3) << 3));
	299	+ break;
	300	+ case 2:
	301	+ data = (data & ~(0xffff << ((where & 3) << 3))) \|
	302	+ (val << ((where & 3) << 3));
	303	+ break;
	304	+ case 4:
	305	+ data = val;
	306	+ break;
	307	+ }
	308	+
	309	+ rt3883_pci_w32(rpc, data, RT3883_PCI_REG_CFGDATA);
	310	+ spin_unlock_irqrestore(&rpc->lock, flags);
	311	+
	312	+ return PCIBIOS_SUCCESSFUL;
	313	+}
	314	+
	315	+static struct pci_ops rt3883_pci_ops = {
	316	+ .read = rt3883_pci_config_read,
	317	+ .write = rt3883_pci_config_write,
	318	+};
	319	+
	320	+static void rt3883_pci_preinit(struct rt3883_pci_controller *rpc, unsigned mode)
	321	+{
	322	+ u32 syscfg1;
	323	+ u32 rstctrl;
	324	+ u32 clkcfg1;
	325	+ u32 t;
	326	+
	327	+ rstctrl = rt_sysc_r32(RT3883_SYSC_REG_RSTCTRL);
	328	+ syscfg1 = rt_sysc_r32(RT3883_SYSC_REG_SYSCFG1);
	329	+ clkcfg1 = rt_sysc_r32(RT3883_SYSC_REG_CLKCFG1);
	330	+
	331	+ if (mode & RT3883_PCI_MODE_PCIE) {
	332	+ rstctrl \|= RT3883_RSTCTRL_PCIE;
	333	+ rt_sysc_w32(rstctrl, RT3883_SYSC_REG_RSTCTRL);
	334	+
	335	+ /* setup PCI PAD drive mode */
	336	+ syscfg1 &= ~(0x30);
	337	+ syscfg1 \|= (2 << 4);
	338	+ rt_sysc_w32(syscfg1, RT3883_SYSC_REG_SYSCFG1);
	339	+
	340	+ t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN0);
	341	+ t &= ~BIT(31);
	342	+ rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN0);
	343	+
	344	+ t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN1);
	345	+ t &= 0x80ffffff;
	346	+ rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN1);
	347	+
	348	+ t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN1);
	349	+ t \|= 0xa << 24;
	350	+ rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN1);
	351	+
	352	+ t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN0);
	353	+ t \|= BIT(31);
	354	+ rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN0);
	355	+
	356	+ msleep(50);
	357	+
	358	+ rstctrl &= ~RT3883_RSTCTRL_PCIE;
	359	+ rt_sysc_w32(rstctrl, RT3883_SYSC_REG_RSTCTRL);
	360	+ }
	361	+
	362	+ syscfg1 \|= (RT3883_SYSCFG1_PCIE_RC_MODE \| RT3883_SYSCFG1_PCI_HOST_MODE);
	363	+
	364	+ clkcfg1 &= ~(RT3883_CLKCFG1_PCI_CLK_EN \| RT3883_CLKCFG1_PCIE_CLK_EN);
	365	+
	366	+ if (mode & RT3883_PCI_MODE_PCI) {
	367	+ clkcfg1 \|= RT3883_CLKCFG1_PCI_CLK_EN;
	368	+ rstctrl &= ~RT3883_RSTCTRL_PCI;
	369	+ }
	370	+
	371	+ if (mode & RT3883_PCI_MODE_PCIE) {
	372	+ clkcfg1 \|= RT3883_CLKCFG1_PCIE_CLK_EN;
	373	+ rstctrl &= ~RT3883_RSTCTRL_PCIE;
	374	+ }
	375	+
	376	+ rt_sysc_w32(syscfg1, RT3883_SYSC_REG_SYSCFG1);
	377	+ rt_sysc_w32(rstctrl, RT3883_SYSC_REG_RSTCTRL);
	378	+ rt_sysc_w32(clkcfg1, RT3883_SYSC_REG_CLKCFG1);
	379	+
	380	+ msleep(500);
	381	+
	382	+ /*
	383	+ * setup the device number of the P2P bridge
	384	+ * and de-assert the reset line
	385	+ */
	386	+ t = (RT3883_P2P_BR_DEVNUM << RT3883_PCICFG_P2P_BR_DEVNUM_S);
	387	+ rt3883_pci_w32(rpc, t, RT3883_PCI_REG_PCICFG);
	388	+
	389	+ /* flush write */
	390	+ rt3883_pci_r32(rpc, RT3883_PCI_REG_PCICFG);
	391	+ msleep(500);
	392	+
	393	+ if (mode & RT3883_PCI_MODE_PCIE) {
	394	+ msleep(500);
	395	+
	396	+ t = rt3883_pci_r32(rpc, RT3883_PCI_REG_STATUS(1));
	397	+
	398	+ rpc->pcie_ready = t & BIT(0);
	399	+
	400	+ if (!rpc->pcie_ready) {
	401	+ /* reset the PCIe block */
	402	+ t = rt_sysc_r32(RT3883_SYSC_REG_RSTCTRL);
	403	+ t \|= RT3883_RSTCTRL_PCIE;
	404	+ rt_sysc_w32(t, RT3883_SYSC_REG_RSTCTRL);
	405	+ t &= ~RT3883_RSTCTRL_PCIE;
	406	+ rt_sysc_w32(t, RT3883_SYSC_REG_RSTCTRL);
	407	+
	408	+ /* turn off PCIe clock */
	409	+ t = rt_sysc_r32(RT3883_SYSC_REG_CLKCFG1);
	410	+ t &= ~RT3883_CLKCFG1_PCIE_CLK_EN;
	411	+ rt_sysc_w32(t, RT3883_SYSC_REG_CLKCFG1);
	412	+
	413	+ t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN0);
	414	+ t &= ~0xf000c080;
	415	+ rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN0);
	416	+ }
	417	+ }
	418	+
	419	+ /* enable PCI arbiter */
	420	+ rt3883_pci_w32(rpc, 0x79, RT3883_PCI_REG_ARBCTL);
	421	+}
	422	+
	423	+static int rt3883_pci_probe(struct platform_device *pdev)
	424	+{
	425	+ struct rt3883_pci_controller *rpc;
	426	+ struct device *dev = &pdev->dev;
	427	+ struct device_node *np = dev->of_node;
	428	+ struct resource *res;
	429	+ struct device_node *child;
	430	+ u32 val;
	431	+ int err;
	432	+ int mode;
	433	+
	434	+ rpc = devm_kzalloc(dev, sizeof(*rpc), GFP_KERNEL);
	435	+ if (!rpc)
	436	+ return -ENOMEM;
	437	+
	438	+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	439	+ if (!res)
	440	+ return -EINVAL;
	441	+
	442	+ rpc->base = devm_ioremap_resource(dev, res);
	443	+ if (IS_ERR(rpc->base))
	444	+ return PTR_ERR(rpc->base);
	445	+
	446	+ /* find the interrupt controller child node */
	447	+ for_each_child_of_node(np, child) {
	448	+ if (of_get_property(child, "interrupt-controller", NULL) &&
	449	+ of_node_get(child)) {
	450	+ rpc->intc_of_node = child;
	451	+ break;
	452	+ }
	453	+ }
	454	+
	455	+ if (!rpc->intc_of_node) {
	456	+ dev_err(dev, "%s has no %s child node",
	457	+ of_node_full_name(rpc->intc_of_node),
	458	+ "interrupt controller");
	459	+ return -EINVAL;
	460	+ }
	461	+
	462	+ /* find the PCI host bridge child node */
	463	+ for_each_child_of_node(np, child) {
	464	+ if (child->type &&
	465	+ of_node_cmp(child->type, "pci") == 0 &&
	466	+ of_node_get(child)) {
	467	+ rpc->pci_controller.of_node = child;
	468	+ break;
	469	+ }
	470	+ }
	471	+
	472	+ if (!rpc->pci_controller.of_node) {
	473	+ dev_err(dev, "%s has no %s child node",
	474	+ of_node_full_name(rpc->intc_of_node),
	475	+ "PCI host bridge");
	476	+ err = -EINVAL;
	477	+ goto err_put_intc_node;
	478	+ }
	479	+
	480	+ mode = RT3883_PCI_MODE_NONE;
	481	+ for_each_available_child_of_node(rpc->pci_controller.of_node, child) {
	482	+ int devfn;
	483	+
	484	+ if (!child->type \|\|
	485	+ of_node_cmp(child->type, "pci") != 0)
	486	+ continue;
	487	+
	488	+ devfn = of_pci_get_devfn(child);
	489	+ if (devfn < 0)
	490	+ continue;
	491	+
	492	+ switch (PCI_SLOT(devfn)) {
	493	+ case 1:
	494	+ mode \|= RT3883_PCI_MODE_PCIE;
	495	+ break;
	496	+
	497	+ case 17:
	498	+ case 18:
	499	+ mode \|= RT3883_PCI_MODE_PCI;
	500	+ break;
	501	+ }
	502	+ }
	503	+
	504	+ if (mode == RT3883_PCI_MODE_NONE) {
	505	+ dev_err(dev, "unable to determine PCI mode\n");
	506	+ err = -EINVAL;
	507	+ goto err_put_hb_node;
	508	+ }
	509	+
	510	+ dev_info(dev, "mode:%s%s\n",
	511	+ (mode & RT3883_PCI_MODE_PCI) ? " PCI" : "",
	512	+ (mode & RT3883_PCI_MODE_PCIE) ? " PCIe" : "");
	513	+
	514	+ rt3883_pci_preinit(rpc, mode);
	515	+
	516	+ rpc->pci_controller.pci_ops = &rt3883_pci_ops;
	517	+ rpc->pci_controller.io_resource = &rpc->io_res;
	518	+ rpc->pci_controller.mem_resource = &rpc->mem_res;
	519	+
	520	+ /* Load PCI I/O and memory resources from DT */
	521	+ pci_load_of_ranges(&rpc->pci_controller,
	522	+ rpc->pci_controller.of_node);
	523	+
	524	+ rt3883_pci_w32(rpc, rpc->mem_res.start, RT3883_PCI_REG_MEMBASE);
	525	+ rt3883_pci_w32(rpc, rpc->io_res.start, RT3883_PCI_REG_IOBASE);
	526	+
	527	+ ioport_resource.start = rpc->io_res.start;
	528	+ ioport_resource.end = rpc->io_res.end;
	529	+
	530	+ /* PCI */
	531	+ rt3883_pci_w32(rpc, 0x03ff0000, RT3883_PCI_REG_BAR0SETUP(0));
	532	+ rt3883_pci_w32(rpc, RT3883_MEMORY_BASE, RT3883_PCI_REG_IMBASEBAR0(0));
	533	+ rt3883_pci_w32(rpc, 0x08021814, RT3883_PCI_REG_ID(0));
	534	+ rt3883_pci_w32(rpc, 0x00800001, RT3883_PCI_REG_CLASS(0));
	535	+ rt3883_pci_w32(rpc, 0x28801814, RT3883_PCI_REG_SUBID(0));
	536	+
	537	+ /* PCIe */
	538	+ rt3883_pci_w32(rpc, 0x03ff0000, RT3883_PCI_REG_BAR0SETUP(1));
	539	+ rt3883_pci_w32(rpc, RT3883_MEMORY_BASE, RT3883_PCI_REG_IMBASEBAR0(1));
	540	+ rt3883_pci_w32(rpc, 0x08021814, RT3883_PCI_REG_ID(1));
	541	+ rt3883_pci_w32(rpc, 0x06040001, RT3883_PCI_REG_CLASS(1));
	542	+ rt3883_pci_w32(rpc, 0x28801814, RT3883_PCI_REG_SUBID(1));
	543	+
	544	+ err = rt3883_pci_irq_init(dev, rpc);
	545	+ if (err)
	546	+ goto err_put_hb_node;
	547	+
	548	+ /* PCIe */
	549	+ val = rt3883_pci_read_cfg32(rpc, 0, 0x01, 0, PCI_COMMAND);
	550	+ val \|= PCI_COMMAND_IO \| PCI_COMMAND_MEMORY \| PCI_COMMAND_MASTER;
	551	+ rt3883_pci_write_cfg32(rpc, 0, 0x01, 0, PCI_COMMAND, val);
	552	+
	553	+ /* PCI */
	554	+ val = rt3883_pci_read_cfg32(rpc, 0, 0x00, 0, PCI_COMMAND);
	555	+ val \|= PCI_COMMAND_IO \| PCI_COMMAND_MEMORY \| PCI_COMMAND_MASTER;
	556	+ rt3883_pci_write_cfg32(rpc, 0, 0x00, 0, PCI_COMMAND, val);
	557	+
	558	+ if (mode == RT3883_PCI_MODE_PCIE) {
	559	+ rt3883_pci_w32(rpc, 0x03ff0001, RT3883_PCI_REG_BAR0SETUP(0));
	560	+ rt3883_pci_w32(rpc, 0x03ff0001, RT3883_PCI_REG_BAR0SETUP(1));
	561	+
	562	+ rt3883_pci_write_cfg32(rpc, 0, RT3883_P2P_BR_DEVNUM, 0,
	563	+ PCI_BASE_ADDRESS_0,
	564	+ RT3883_MEMORY_BASE);
	565	+ /* flush write */
	566	+ rt3883_pci_read_cfg32(rpc, 0, RT3883_P2P_BR_DEVNUM, 0,
	567	+ PCI_BASE_ADDRESS_0);
	568	+ } else {
	569	+ rt3883_pci_write_cfg32(rpc, 0, RT3883_P2P_BR_DEVNUM, 0,
	570	+ PCI_IO_BASE, 0x00000101);
	571	+ }
	572	+
	573	+ register_pci_controller(&rpc->pci_controller);
	574	+
	575	+ return 0;
	576	+
	577	+err_put_hb_node:
	578	+ of_node_put(rpc->pci_controller.of_node);
	579	+err_put_intc_node:
	580	+ of_node_put(rpc->intc_of_node);
	581	+ return err;
	582	+}
	583	+
	584	+int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
	585	+{
	586	+ struct of_irq dev_irq;
	587	+ int err;
	588	+ int irq;
	589	+
	590	+ err = of_irq_map_pci(dev, &dev_irq);
	591	+ if (err) {
	592	+ pr_err("pci %s: unable to get irq map, err=%d\n",
	593	+ pci_name((struct pci_dev *) dev), err);
	594	+ return 0;
	595	+ }
	596	+
	597	+ irq = irq_create_of_mapping(dev_irq.controller,
	598	+ dev_irq.specifier,
	599	+ dev_irq.size);
	600	+
	601	+ if (irq == 0)
	602	+ pr_crit("pci %s: no irq found for pin %u\n",
	603	+ pci_name((struct pci_dev *) dev), pin);
	604	+ else
	605	+ pr_info("pci %s: using irq %d for pin %u\n",
	606	+ pci_name((struct pci_dev *) dev), irq, pin);
	607	+
	608	+ return irq;
	609	+}
	610	+
	611	+int pcibios_plat_dev_init(struct pci_dev *dev)
	612	+{
	613	+ return 0;
	614	+}
	615	+
	616	+static const struct of_device_id rt3883_pci_ids[] = {
	617	+ { .compatible = "ralink,rt3883-pci" },
	618	+ {},
	619	+};
	620	+MODULE_DEVICE_TABLE(of, rt3883_pci_ids);
	621	+
	622	+static struct platform_driver rt3883_pci_driver = {
	623	+ .probe = rt3883_pci_probe,
	624	+ .driver = {
	625	+ .name = "rt3883-pci",
	626	+ .owner = THIS_MODULE,
	627	+ .of_match_table = of_match_ptr(rt3883_pci_ids),
	628	+ },
	629	+};
	630	+
	631	+static int __init rt3883_pci_init(void)
	632	+{
	633	+ return platform_driver_register(&rt3883_pci_driver);
	634	+}
	635	+
	636	+postcore_initcall(rt3883_pci_init);

arch/mips/powertv/Kconfig+1−8

@@ -1,14 +1,7 @@
1		−config BOOTLOADER_DRIVER
2		− bool "PowerTV Bootloader Driver Support"
3		− default n
4		− depends on POWERTV
5		− help
6		− Use this option if you want to load bootloader driver.
7		−
8	1	config BOOTLOADER_FAMILY
9	2	string "POWERTV Bootloader Family string"
10	3	default "85"
11		− depends on POWERTV && !BOOTLOADER_DRIVER
	4	+ depends on POWERTV
12	5	help
13	6	This value should be specified when the bootloader driver is disabled
14	7	and must be exactly two characters long. Families supported are:

arch/mips/powertv/asic/asic_devices.c+1−11

@@ -147,20 +147,10 @@ static __init noinline void platform_set_family(void) · 146 unmodified lines
147	147	if (check_forcefamily(forced_family) == 0)
148	148	bootldr_family = BOOTLDRFAMILY(forced_family[0],
149	149	forced_family[1]);
150		− else {
151		−
152		−#ifdef CONFIG_BOOTLOADER_DRIVER
153		− bootldr_family = (unsigned short) kbldr_GetSWFamily();
154		−#else
155		−#if defined(CONFIG_BOOTLOADER_FAMILY)
	150	+ else
156	151	bootldr_family = (unsigned short) BOOTLDRFAMILY(
157	152	CONFIG_BOOTLOADER_FAMILY[0],
158	153	CONFIG_BOOTLOADER_FAMILY[1]);
159		−#else
160		−#error "Unknown Bootloader Family"
161		−#endif
162		−#endif
163		− }
164	154
165	155	pr_info("Bootloader Family = 0x%04X\n", bootldr_family);
166	156

arch/mips/powertv/init.c+0−4

@@ -87,8 +87,4 @@ void __init prom_init(void) · 86 unmodified lines
87	87
88	88	configure_platform();
89	89	prom_meminit();
90		−
91		−#ifndef CONFIG_BOOTLOADER_DRIVER
92		− pr_info("\nBootloader driver isn't loaded...\n");
93		−#endif
94	90	}

arch/mips/powertv/reset.c+0−12

@@ -21,24 +21,12 @@ · 20 unmodified lines
21	21	#include <linux/io.h>
22	22	#include <asm/reboot.h> /* Not included by linux/reboot.h */
23	23
24		−#ifdef CONFIG_BOOTLOADER_DRIVER
25		−#include <asm/mach-powertv/kbldr.h>
26		−#endif
27		−
28	24	#include <asm/mach-powertv/asic_regs.h>
29	25	#include "reset.h"
30	26
31	27	static void mips_machine_restart(char *command)
32	28	{
33		−#ifdef CONFIG_BOOTLOADER_DRIVER
34		− /*
35		− * Call the bootloader's reset function to ensure
36		− * that persistent data is flushed before hard reset
37		− */
38		− kbldr_SetCauseAndReset();
39		−#else
40	29	writel(0x1, asic_reg_addr(watchdog));
41		−#endif
42	30	}
43	31
44	32	void mips_reboot_setup(void)

arch/mips/ralink/Kconfig+10−0

@@ -1,5 +1,12 @@
1	1	if RALINK
2	2
	3	+config CLKEVT_RT3352
	4	+ bool
	5	+ depends on SOC_RT305X \|\| SOC_MT7620
	6	+ default y
	7	+ select CLKSRC_OF
	8	+ select CLKSRC_MMIO
	9	+
3	10	choice
4	11	prompt "Ralink SoC selection"
5	12	default SOC_RT305X
@@ -19,9 +26,12 @@ choice · 13 unmodified lines
19	26	bool "RT3883"
20	27	select USB_ARCH_HAS_OHCI
21	28	select USB_ARCH_HAS_EHCI
	29	+ select HW_HAS_PCI
22	30
23	31	config SOC_MT7620
24	32	bool "MT7620"
	33	+ select USB_ARCH_HAS_OHCI
	34	+ select USB_ARCH_HAS_EHCI
25	35
26	36	endchoice
27	37

arch/mips/ralink/Makefile+3−1

@@ -6,7 +6,9 @@ · 5 unmodified lines
6	6	# Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
7	7	# Copyright (C) 2013 John Crispin <blogic@openwrt.org>
8	8
9		−obj-y := prom.o of.o reset.o clk.o irq.o
	9	+obj-y := prom.o of.o reset.o clk.o irq.o timer.o
	10	+
	11	+obj-$(CONFIG_CLKEVT_RT3352) += cevt-rt3352.o
10	12
11	13	obj-$(CONFIG_SOC_RT288X) += rt288x.o
12	14	obj-$(CONFIG_SOC_RT305X) += rt305x.o

arch/mips/ralink/Platform+1−0

@@ -26,3 +26,4 @@ cflags-$(CONFIG_SOC_RT3883) += -I$(srctree)/arch/mips/include/asm/mach-ralink/rt · 25 unmodified lines
26	26	# Ralink MT7620
27	27	#
28	28	load-$(CONFIG_SOC_MT7620) += 0xffffffff80000000
	29	+cflags-$(CONFIG_SOC_MT7620) += -I$(srctree)/arch/mips/include/asm/mach-ralink/mt7620

arch/mips/ralink/cevt-rt3352.c+145−0

@@ -0,0 +1,145 @@
	1	+/*
	2	+ * This file is subject to the terms and conditions of the GNU General Public
	3	+ * License. See the file "COPYING" in the main directory of this archive
	4	+ * for more details.
	5	+ *
	6	+ * Copyright (C) 2013 by John Crispin <blogic@openwrt.org>
	7	+ */
	8	+
	9	+#include <linux/clockchips.h>
	10	+#include <linux/clocksource.h>
	11	+#include <linux/interrupt.h>
	12	+#include <linux/reset.h>
	13	+#include <linux/init.h>
	14	+#include <linux/time.h>
	15	+#include <linux/of.h>
	16	+#include <linux/of_irq.h>
	17	+#include <linux/of_address.h>
	18	+
	19	+#include <asm/mach-ralink/ralink_regs.h>
	20	+
	21	+#define SYSTICK_FREQ (50 * 1000)
	22	+
	23	+#define SYSTICK_CONFIG 0x00
	24	+#define SYSTICK_COMPARE 0x04
	25	+#define SYSTICK_COUNT 0x08
	26	+
	27	+/* route systick irq to mips irq 7 instead of the r4k-timer */
	28	+#define CFG_EXT_STK_EN 0x2
	29	+/* enable the counter */
	30	+#define CFG_CNT_EN 0x1
	31	+
	32	+struct systick_device {
	33	+ void __iomem *membase;
	34	+ struct clock_event_device dev;
	35	+ int irq_requested;
	36	+ int freq_scale;
	37	+};
	38	+
	39	+static void systick_set_clock_mode(enum clock_event_mode mode,
	40	+ struct clock_event_device *evt);
	41	+
	42	+static int systick_next_event(unsigned long delta,
	43	+ struct clock_event_device *evt)
	44	+{
	45	+ struct systick_device *sdev;
	46	+ u32 count;
	47	+
	48	+ sdev = container_of(evt, struct systick_device, dev);
	49	+ count = ioread32(sdev->membase + SYSTICK_COUNT);
	50	+ count = (count + delta) % SYSTICK_FREQ;
	51	+ iowrite32(count + delta, sdev->membase + SYSTICK_COMPARE);
	52	+
	53	+ return 0;
	54	+}
	55	+
	56	+static void systick_event_handler(struct clock_event_device *dev)
	57	+{
	58	+ /* noting to do here */
	59	+}
	60	+
	61	+static irqreturn_t systick_interrupt(int irq, void *dev_id)
	62	+{
	63	+ struct clock_event_device dev = (struct clock_event_device ) dev_id;
	64	+
	65	+ dev->event_handler(dev);
	66	+
	67	+ return IRQ_HANDLED;
	68	+}
	69	+
	70	+static struct systick_device systick = {
	71	+ .dev = {
	72	+ /*
	73	+ * cevt-r4k uses 300, make sure systick
	74	+ * gets used if available
	75	+ */
	76	+ .rating = 310,
	77	+ .features = CLOCK_EVT_FEAT_ONESHOT,
	78	+ .set_next_event = systick_next_event,
	79	+ .set_mode = systick_set_clock_mode,
	80	+ .event_handler = systick_event_handler,
	81	+ },
	82	+};
	83	+
	84	+static struct irqaction systick_irqaction = {
	85	+ .handler = systick_interrupt,
	86	+ .flags = IRQF_PERCPU \| IRQF_TIMER,
	87	+ .dev_id = &systick.dev,
	88	+};
	89	+
	90	+static void systick_set_clock_mode(enum clock_event_mode mode,
	91	+ struct clock_event_device *evt)
	92	+{
	93	+ struct systick_device *sdev;
	94	+
	95	+ sdev = container_of(evt, struct systick_device, dev);
	96	+
	97	+ switch (mode) {
	98	+ case CLOCK_EVT_MODE_ONESHOT:
	99	+ if (!sdev->irq_requested)
	100	+ setup_irq(systick.dev.irq, &systick_irqaction);
	101	+ sdev->irq_requested = 1;
	102	+ iowrite32(CFG_EXT_STK_EN \| CFG_CNT_EN,
	103	+ systick.membase + SYSTICK_CONFIG);
	104	+ break;
	105	+
	106	+ case CLOCK_EVT_MODE_SHUTDOWN:
	107	+ if (sdev->irq_requested)
	108	+ free_irq(systick.dev.irq, &systick_irqaction);
	109	+ sdev->irq_requested = 0;
	110	+ iowrite32(0, systick.membase + SYSTICK_CONFIG);
	111	+ break;
	112	+
	113	+ default:
	114	+ pr_err("%s: Unhandeled mips clock_mode\n", systick.dev.name);
	115	+ break;
	116	+ }
	117	+}
	118	+
	119	+static void __init ralink_systick_init(struct device_node *np)
	120	+{
	121	+ systick.membase = of_iomap(np, 0);
	122	+ if (!systick.membase)
	123	+ return;
	124	+
	125	+ systick_irqaction.name = np->name;
	126	+ systick.dev.name = np->name;
	127	+ clockevents_calc_mult_shift(&systick.dev, SYSTICK_FREQ, 60);
	128	+ systick.dev.max_delta_ns = clockevent_delta2ns(0x7fff, &systick.dev);
	129	+ systick.dev.min_delta_ns = clockevent_delta2ns(0x3, &systick.dev);
	130	+ systick.dev.irq = irq_of_parse_and_map(np, 0);
	131	+ if (!systick.dev.irq) {
	132	+ pr_err("%s: request_irq failed", np->name);
	133	+ return;
	134	+ }
	135	+
	136	+ clocksource_mmio_init(systick.membase + SYSTICK_COUNT, np->name,
	137	+ SYSTICK_FREQ, 301, 16, clocksource_mmio_readl_up);
	138	+
	139	+ clockevents_register_device(&systick.dev);
	140	+
	141	+ pr_info("%s: runing - mult: %d, shift: %d\n",
	142	+ np->name, systick.dev.mult, systick.dev.shift);
	143	+}
	144	+
	145	+CLOCKSOURCE_OF_DECLARE(systick, "ralink,cevt-systick", ralink_systick_init);

arch/mips/ralink/clk.c+1−0

@@ -69,4 +69,5 @@ void __init plat_time_init(void) · 68 unmodified lines
69	69	pr_info("CPU Clock: %ldMHz\n", clk_get_rate(clk) / 1000000);
70	70	mips_hpt_frequency = clk_get_rate(clk) / 2;
71	71	clk_put(clk);
	72	+ clocksource_of_init();
72	73	}

arch/mips/ralink/common.h+2−0

@@ -46,6 +46,8 @@ extern void ralink_of_remap(void); · 45 unmodified lines
46	46	extern void ralink_clk_init(void);
47	47	extern void ralink_clk_add(const char *dev, unsigned long rate);
48	48
	49	+extern void ralink_rst_init(void);
	50	+
49	51	extern void prom_soc_init(struct ralink_soc_info *soc_info);
50	52
51	53	__iomem void plat_of_remap_node(const char node);

arch/mips/ralink/mt7620.c+180−25

@@ -23,9 +23,6 @@ · 22 unmodified lines
23	23	/* does the board have sdram or ddram */
24	24	static int dram_type;
25	25
26		−/* the pll dividers */
27		−static u32 mt7620_clk_divider[] = { 2, 3, 4, 8 };
28		−
29	26	static struct ralink_pinmux_grp mode_mux[] = {
30	27	{
31	28	.name = "i2c",
@@ -140,34 +137,189 @@ struct ralink_pinmux rt_gpio_pinmux = { · 108 unmodified lines
140	137	.uart_mask = MT7620_GPIO_MODE_UART0_MASK,
141	138	};
142	139
143		−void __init ralink_clk_init(void)
	140	+static __init u32
	141	+mt7620_calc_rate(u32 ref_rate, u32 mul, u32 div)
144	142	{
145		− unsigned long cpu_rate, sys_rate;
146		− u32 c0 = rt_sysc_r32(SYSC_REG_CPLL_CONFIG0);
147		− u32 c1 = rt_sysc_r32(SYSC_REG_CPLL_CONFIG1);
148		− u32 swconfig = (c0 >> CPLL_SW_CONFIG_SHIFT) & CPLL_SW_CONFIG_MASK;
149		− u32 cpu_clk = (c1 >> CPLL_CPU_CLK_SHIFT) & CPLL_CPU_CLK_MASK;
150		−
151		− if (cpu_clk) {
152		− cpu_rate = 480000000;
153		− } else if (!swconfig) {
154		− cpu_rate = 600000000;
155		− } else {
156		− u32 m = (c0 >> CPLL_MULT_RATIO_SHIFT) & CPLL_MULT_RATIO;
157		− u32 d = (c0 >> CPLL_DIV_RATIO_SHIFT) & CPLL_DIV_RATIO;
	143	+ u64 t;
158	144
159		− cpu_rate = ((40 * (m + 24)) / mt7620_clk_divider[d]) * 1000000;
160		− }
	145	+ t = ref_rate;
	146	+ t *= mul;
	147	+ do_div(t, div);
	148	+
	149	+ return t;
	150	+}
	151	+
	152	+#define MHZ(x) ((x) * 1000 * 1000)
	153	+
	154	+static __init unsigned long
	155	+mt7620_get_xtal_rate(void)
	156	+{
	157	+ u32 reg;
	158	+
	159	+ reg = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG0);
	160	+ if (reg & SYSCFG0_XTAL_FREQ_SEL)
	161	+ return MHZ(40);
	162	+
	163	+ return MHZ(20);
	164	+}
	165	+
	166	+static __init unsigned long
	167	+mt7620_get_periph_rate(unsigned long xtal_rate)
	168	+{
	169	+ u32 reg;
	170	+
	171	+ reg = rt_sysc_r32(SYSC_REG_CLKCFG0);
	172	+ if (reg & CLKCFG0_PERI_CLK_SEL)
	173	+ return xtal_rate;
	174	+
	175	+ return MHZ(40);
	176	+}
	177	+
	178	+static const u32 mt7620_clk_divider[] __initconst = { 2, 3, 4, 8 };
	179	+
	180	+static __init unsigned long
	181	+mt7620_get_cpu_pll_rate(unsigned long xtal_rate)
	182	+{
	183	+ u32 reg;
	184	+ u32 mul;
	185	+ u32 div;
	186	+
	187	+ reg = rt_sysc_r32(SYSC_REG_CPLL_CONFIG0);
	188	+ if (reg & CPLL_CFG0_BYPASS_REF_CLK)
	189	+ return xtal_rate;
	190	+
	191	+ if ((reg & CPLL_CFG0_SW_CFG) == 0)
	192	+ return MHZ(600);
	193	+
	194	+ mul = (reg >> CPLL_CFG0_PLL_MULT_RATIO_SHIFT) &
	195	+ CPLL_CFG0_PLL_MULT_RATIO_MASK;
	196	+ mul += 24;
	197	+ if (reg & CPLL_CFG0_LC_CURFCK)
	198	+ mul *= 2;
	199	+
	200	+ div = (reg >> CPLL_CFG0_PLL_DIV_RATIO_SHIFT) &
	201	+ CPLL_CFG0_PLL_DIV_RATIO_MASK;
	202	+
	203	+ WARN_ON(div >= ARRAY_SIZE(mt7620_clk_divider));
	204	+
	205	+ return mt7620_calc_rate(xtal_rate, mul, mt7620_clk_divider[div]);
	206	+}
	207	+
	208	+static __init unsigned long
	209	+mt7620_get_pll_rate(unsigned long xtal_rate, unsigned long cpu_pll_rate)
	210	+{
	211	+ u32 reg;
	212	+
	213	+ reg = rt_sysc_r32(SYSC_REG_CPLL_CONFIG1);
	214	+ if (reg & CPLL_CFG1_CPU_AUX1)
	215	+ return xtal_rate;
	216	+
	217	+ if (reg & CPLL_CFG1_CPU_AUX0)
	218	+ return MHZ(480);
161	219
	220	+ return cpu_pll_rate;
	221	+}
	222	+
	223	+static __init unsigned long
	224	+mt7620_get_cpu_rate(unsigned long pll_rate)
	225	+{
	226	+ u32 reg;
	227	+ u32 mul;
	228	+ u32 div;
	229	+
	230	+ reg = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG);
	231	+
	232	+ mul = reg & CPU_SYS_CLKCFG_CPU_FFRAC_MASK;
	233	+ div = (reg >> CPU_SYS_CLKCFG_CPU_FDIV_SHIFT) &
	234	+ CPU_SYS_CLKCFG_CPU_FDIV_MASK;
	235	+
	236	+ return mt7620_calc_rate(pll_rate, mul, div);
	237	+}
	238	+
	239	+static const u32 mt7620_ocp_dividers[16] __initconst = {
	240	+ [CPU_SYS_CLKCFG_OCP_RATIO_2] = 2,
	241	+ [CPU_SYS_CLKCFG_OCP_RATIO_3] = 3,
	242	+ [CPU_SYS_CLKCFG_OCP_RATIO_4] = 4,
	243	+ [CPU_SYS_CLKCFG_OCP_RATIO_5] = 5,
	244	+ [CPU_SYS_CLKCFG_OCP_RATIO_10] = 10,
	245	+};
	246	+
	247	+static __init unsigned long
	248	+mt7620_get_dram_rate(unsigned long pll_rate)
	249	+{
162	250	if (dram_type == SYSCFG0_DRAM_TYPE_SDRAM)
163		− sys_rate = cpu_rate / 4;
164		− else
165		− sys_rate = cpu_rate / 3;
	251	+ return pll_rate / 4;
	252	+
	253	+ return pll_rate / 3;
	254	+}
	255	+
	256	+static __init unsigned long
	257	+mt7620_get_sys_rate(unsigned long cpu_rate)
	258	+{
	259	+ u32 reg;
	260	+ u32 ocp_ratio;
	261	+ u32 div;
	262	+
	263	+ reg = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG);
	264	+
	265	+ ocp_ratio = (reg >> CPU_SYS_CLKCFG_OCP_RATIO_SHIFT) &
	266	+ CPU_SYS_CLKCFG_OCP_RATIO_MASK;
	267	+
	268	+ if (WARN_ON(ocp_ratio >= ARRAY_SIZE(mt7620_ocp_dividers)))
	269	+ return cpu_rate;
	270	+
	271	+ div = mt7620_ocp_dividers[ocp_ratio];
	272	+ if (WARN(!div, "invalid divider for OCP ratio %u", ocp_ratio))
	273	+ return cpu_rate;
	274	+
	275	+ return cpu_rate / div;
	276	+}
	277	+
	278	+void __init ralink_clk_init(void)
	279	+{
	280	+ unsigned long xtal_rate;
	281	+ unsigned long cpu_pll_rate;
	282	+ unsigned long pll_rate;
	283	+ unsigned long cpu_rate;
	284	+ unsigned long sys_rate;
	285	+ unsigned long dram_rate;
	286	+ unsigned long periph_rate;
	287	+
	288	+ xtal_rate = mt7620_get_xtal_rate();
	289	+
	290	+ cpu_pll_rate = mt7620_get_cpu_pll_rate(xtal_rate);
	291	+ pll_rate = mt7620_get_pll_rate(xtal_rate, cpu_pll_rate);
	292	+
	293	+ cpu_rate = mt7620_get_cpu_rate(pll_rate);
	294	+ dram_rate = mt7620_get_dram_rate(pll_rate);
	295	+ sys_rate = mt7620_get_sys_rate(cpu_rate);
	296	+ periph_rate = mt7620_get_periph_rate(xtal_rate);
	297	+
	298	+#define RFMT(label) label ":%lu.%03luMHz "
	299	+#define RINT(x) ((x) / 1000000)
	300	+#define RFRAC(x) (((x) / 1000) % 1000)
	301	+
	302	+ pr_debug(RFMT("XTAL") RFMT("CPU_PLL") RFMT("PLL"),
	303	+ RINT(xtal_rate), RFRAC(xtal_rate),
	304	+ RINT(cpu_pll_rate), RFRAC(cpu_pll_rate),
	305	+ RINT(pll_rate), RFRAC(pll_rate));
	306	+
	307	+ pr_debug(RFMT("CPU") RFMT("DRAM") RFMT("SYS") RFMT("PERIPH"),
	308	+ RINT(cpu_rate), RFRAC(cpu_rate),
	309	+ RINT(dram_rate), RFRAC(dram_rate),
	310	+ RINT(sys_rate), RFRAC(sys_rate),
	311	+ RINT(periph_rate), RFRAC(periph_rate));
	312	+
	313	+#undef RFRAC
	314	+#undef RINT
	315	+#undef RFMT
166	316
167	317	ralink_clk_add("cpu", cpu_rate);
168		− ralink_clk_add("10000100.timer", 40000000);
169		− ralink_clk_add("10000500.uart", 40000000);
170		− ralink_clk_add("10000c00.uartlite", 40000000);
	318	+ ralink_clk_add("10000100.timer", periph_rate);
	319	+ ralink_clk_add("10000120.watchdog", periph_rate);
	320	+ ralink_clk_add("10000500.uart", periph_rate);
	321	+ ralink_clk_add("10000b00.spi", sys_rate);
	322	+ ralink_clk_add("10000c00.uartlite", periph_rate);
171	323	}
172	324
173	325	void __init ralink_of_remap(void)
@@ -214,16 +366,19 @@ void prom_soc_init(struct ralink_soc_info *soc_info) · 40 unmodified lines
214	366
215	367	switch (dram_type) {
216	368	case SYSCFG0_DRAM_TYPE_SDRAM:
	369	+ pr_info("Board has SDRAM\n");
217	370	soc_info->mem_size_min = MT7620_SDRAM_SIZE_MIN;
218	371	soc_info->mem_size_max = MT7620_SDRAM_SIZE_MAX;
219	372	break;
220	373
221	374	case SYSCFG0_DRAM_TYPE_DDR1:
	375	+ pr_info("Board has DDR1\n");
222	376	soc_info->mem_size_min = MT7620_DDR1_SIZE_MIN;
223	377	soc_info->mem_size_max = MT7620_DDR1_SIZE_MAX;
224	378	break;
225	379
226	380	case SYSCFG0_DRAM_TYPE_DDR2:
	381	+ pr_info("Board has DDR2\n");
227	382	soc_info->mem_size_min = MT7620_DDR2_SIZE_MIN;
228	383	soc_info->mem_size_max = MT7620_DDR2_SIZE_MAX;
229	384	break;

arch/mips/ralink/of.c+3−0

@@ -110,6 +110,9 @@ static int __init plat_of_setup(void) · 109 unmodified lines
110	110	if (of_platform_populate(NULL, of_ids, NULL, NULL))
111	111	panic("failed to populate DT\n");
112	112
	113	+ /* make sure ithat the reset controller is setup early */
	114	+ ralink_rst_init();
	115	+
113	116	return 0;
114	117	}
115	118

arch/mips/ralink/reset.c+62−0

@@ -10,6 +10,8 @@ · 9 unmodified lines
10	10
11	11	#include <linux/pm.h>
12	12	#include <linux/io.h>
	13	+#include <linux/of.h>
	14	+#include <linux/reset-controller.h>
13	15
14	16	#include <asm/reboot.h>
15	17
@@ -19,6 +21,66 @@ · 3 unmodified lines
19	21	#define SYSC_REG_RESET_CTRL 0x034
20	22	#define RSTCTL_RESET_SYSTEM BIT(0)
21	23
	24	+static int ralink_assert_device(struct reset_controller_dev *rcdev,
	25	+ unsigned long id)
	26	+{
	27	+ u32 val;
	28	+
	29	+ if (id < 8)
	30	+ return -1;
	31	+
	32	+ val = rt_sysc_r32(SYSC_REG_RESET_CTRL);
	33	+ val \|= BIT(id);
	34	+ rt_sysc_w32(val, SYSC_REG_RESET_CTRL);
	35	+
	36	+ return 0;
	37	+}
	38	+
	39	+static int ralink_deassert_device(struct reset_controller_dev *rcdev,
	40	+ unsigned long id)
	41	+{
	42	+ u32 val;
	43	+
	44	+ if (id < 8)
	45	+ return -1;
	46	+
	47	+ val = rt_sysc_r32(SYSC_REG_RESET_CTRL);
	48	+ val &= ~BIT(id);
	49	+ rt_sysc_w32(val, SYSC_REG_RESET_CTRL);
	50	+
	51	+ return 0;
	52	+}
	53	+
	54	+static int ralink_reset_device(struct reset_controller_dev *rcdev,
	55	+ unsigned long id)
	56	+{
	57	+ ralink_assert_device(rcdev, id);
	58	+ return ralink_deassert_device(rcdev, id);
	59	+}
	60	+
	61	+static struct reset_control_ops reset_ops = {
	62	+ .reset = ralink_reset_device,
	63	+ .assert = ralink_assert_device,
	64	+ .deassert = ralink_deassert_device,
	65	+};
	66	+
	67	+static struct reset_controller_dev reset_dev = {
	68	+ .ops = &reset_ops,
	69	+ .owner = THIS_MODULE,
	70	+ .nr_resets = 32,
	71	+ .of_reset_n_cells = 1,
	72	+};
	73	+
	74	+void ralink_rst_init(void)
	75	+{
	76	+ reset_dev.of_node = of_find_compatible_node(NULL, NULL,
	77	+ "ralink,rt2880-reset");
	78	+ if (!reset_dev.of_node)
	79	+ pr_err("Failed to find reset controller node");
	80	+ else
	81	+ reset_controller_register(&reset_dev);
	82	+}
	83	+
22	84	static void ralink_restart(char *command)
23	85	{
24	86	local_irq_disable();

arch/mips/ralink/timer.c+185−0

@@ -0,0 +1,185 @@
	1	+/*
	2	+ * This program is free software; you can redistribute it and/or modify it
	3	+ * under the terms of the GNU General Public License version 2 as published
	4	+ * by the Free Software Foundation.
	5	+ *
	6	+ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
	7	+*/
	8	+
	9	+#include <linux/module.h>
	10	+#include <linux/platform_device.h>
	11	+#include <linux/interrupt.h>
	12	+#include <linux/timer.h>
	13	+#include <linux/of_gpio.h>
	14	+#include <linux/clk.h>
	15	+
	16	+#include <asm/mach-ralink/ralink_regs.h>
	17	+
	18	+#define TIMER_REG_TMRSTAT 0x00
	19	+#define TIMER_REG_TMR0LOAD 0x10
	20	+#define TIMER_REG_TMR0CTL 0x18
	21	+
	22	+#define TMRSTAT_TMR0INT BIT(0)
	23	+
	24	+#define TMR0CTL_ENABLE BIT(7)
	25	+#define TMR0CTL_MODE_PERIODIC BIT(4)
	26	+#define TMR0CTL_PRESCALER 1
	27	+#define TMR0CTL_PRESCALE_VAL (0xf - TMR0CTL_PRESCALER)
	28	+#define TMR0CTL_PRESCALE_DIV (65536 / BIT(TMR0CTL_PRESCALER))
	29	+
	30	+struct rt_timer {
	31	+ struct device *dev;
	32	+ void __iomem *membase;
	33	+ int irq;
	34	+ unsigned long timer_freq;
	35	+ unsigned long timer_div;
	36	+};
	37	+
	38	+static inline void rt_timer_w32(struct rt_timer *rt, u8 reg, u32 val)
	39	+{
	40	+ __raw_writel(val, rt->membase + reg);
	41	+}
	42	+
	43	+static inline u32 rt_timer_r32(struct rt_timer *rt, u8 reg)
	44	+{
	45	+ return __raw_readl(rt->membase + reg);
	46	+}
	47	+
	48	+static irqreturn_t rt_timer_irq(int irq, void *_rt)
	49	+{
	50	+ struct rt_timer rt = (struct rt_timer ) _rt;
	51	+
	52	+ rt_timer_w32(rt, TIMER_REG_TMR0LOAD, rt->timer_freq / rt->timer_div);
	53	+ rt_timer_w32(rt, TIMER_REG_TMRSTAT, TMRSTAT_TMR0INT);
	54	+
	55	+ return IRQ_HANDLED;
	56	+}
	57	+
	58	+
	59	+static int rt_timer_request(struct rt_timer *rt)
	60	+{
	61	+ int err = request_irq(rt->irq, rt_timer_irq, IRQF_DISABLED,
	62	+ dev_name(rt->dev), rt);
	63	+ if (err) {
	64	+ dev_err(rt->dev, "failed to request irq\n");
	65	+ } else {
	66	+ u32 t = TMR0CTL_MODE_PERIODIC \| TMR0CTL_PRESCALE_VAL;
	67	+ rt_timer_w32(rt, TIMER_REG_TMR0CTL, t);
	68	+ }
	69	+ return err;
	70	+}
	71	+
	72	+static void rt_timer_free(struct rt_timer *rt)
	73	+{
	74	+ free_irq(rt->irq, rt);
	75	+}
	76	+
	77	+static int rt_timer_config(struct rt_timer *rt, unsigned long divisor)
	78	+{
	79	+ if (rt->timer_freq < divisor)
	80	+ rt->timer_div = rt->timer_freq;
	81	+ else
	82	+ rt->timer_div = divisor;
	83	+
	84	+ rt_timer_w32(rt, TIMER_REG_TMR0LOAD, rt->timer_freq / rt->timer_div);
	85	+
	86	+ return 0;
	87	+}
	88	+
	89	+static int rt_timer_enable(struct rt_timer *rt)
	90	+{
	91	+ u32 t;
	92	+
	93	+ rt_timer_w32(rt, TIMER_REG_TMR0LOAD, rt->timer_freq / rt->timer_div);
	94	+
	95	+ t = rt_timer_r32(rt, TIMER_REG_TMR0CTL);
	96	+ t \|= TMR0CTL_ENABLE;
	97	+ rt_timer_w32(rt, TIMER_REG_TMR0CTL, t);
	98	+
	99	+ return 0;
	100	+}
	101	+
	102	+static void rt_timer_disable(struct rt_timer *rt)
	103	+{
	104	+ u32 t;
	105	+
	106	+ t = rt_timer_r32(rt, TIMER_REG_TMR0CTL);
	107	+ t &= ~TMR0CTL_ENABLE;
	108	+ rt_timer_w32(rt, TIMER_REG_TMR0CTL, t);
	109	+}
	110	+
	111	+static int rt_timer_probe(struct platform_device *pdev)
	112	+{
	113	+ struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	114	+ struct rt_timer *rt;
	115	+ struct clk *clk;
	116	+
	117	+ rt = devm_kzalloc(&pdev->dev, sizeof(*rt), GFP_KERNEL);
	118	+ if (!rt) {
	119	+ dev_err(&pdev->dev, "failed to allocate memory\n");
	120	+ return -ENOMEM;
	121	+ }
	122	+
	123	+ rt->irq = platform_get_irq(pdev, 0);
	124	+ if (!rt->irq) {
	125	+ dev_err(&pdev->dev, "failed to load irq\n");
	126	+ return -ENOENT;
	127	+ }
	128	+
	129	+ rt->membase = devm_request_and_ioremap(&pdev->dev, res);
	130	+ if (IS_ERR(rt->membase))
	131	+ return PTR_ERR(rt->membase);
	132	+
	133	+ clk = devm_clk_get(&pdev->dev, NULL);
	134	+ if (IS_ERR(clk)) {
	135	+ dev_err(&pdev->dev, "failed get clock rate\n");
	136	+ return PTR_ERR(clk);
	137	+ }
	138	+
	139	+ rt->timer_freq = clk_get_rate(clk) / TMR0CTL_PRESCALE_DIV;
	140	+ if (!rt->timer_freq)
	141	+ return -EINVAL;
	142	+
	143	+ rt->dev = &pdev->dev;
	144	+ platform_set_drvdata(pdev, rt);
	145	+
	146	+ rt_timer_request(rt);
	147	+ rt_timer_config(rt, 2);
	148	+ rt_timer_enable(rt);
	149	+
	150	+ dev_info(&pdev->dev, "maximum frequncy is %luHz\n", rt->timer_freq);
	151	+
	152	+ return 0;
	153	+}
	154	+
	155	+static int rt_timer_remove(struct platform_device *pdev)
	156	+{
	157	+ struct rt_timer *rt = platform_get_drvdata(pdev);
	158	+
	159	+ rt_timer_disable(rt);
	160	+ rt_timer_free(rt);
	161	+
	162	+ return 0;
	163	+}
	164	+
	165	+static const struct of_device_id rt_timer_match[] = {
	166	+ { .compatible = "ralink,rt2880-timer" },
	167	+ {},
	168	+};
	169	+MODULE_DEVICE_TABLE(of, rt_timer_match);
	170	+
	171	+static struct platform_driver rt_timer_driver = {
	172	+ .probe = rt_timer_probe,
	173	+ .remove = rt_timer_remove,
	174	+ .driver = {
	175	+ .name = "rt-timer",
	176	+ .owner = THIS_MODULE,
	177	+ .of_match_table = rt_timer_match
	178	+ },
	179	+};
	180	+
	181	+module_platform_driver(rt_timer_driver);
	182	+
	183	+MODULE_DESCRIPTION("Ralink RT2880 timer");
	184	+MODULE_AUTHOR("John Crispin <blogic@openwrt.org");
	185	+MODULE_LICENSE("GPL");

arch/mips/txx9/generic/setup.c+1−1

@@ -350,7 +350,7 @@ static void __init select_board(void) · 349 unmodified lines
350	350	}
351	351
352	352	/* select "default" board */
353		−#ifdef CONFIG_CPU_TX39XX
	353	+#ifdef CONFIG_TOSHIBA_JMR3927
354	354	txx9_board_vec = &jmr3927_vec;
355	355	#endif
356	356	#ifdef CONFIG_CPU_TX49XX

drivers/gpio/Kconfig+8−0

@@ -203,6 +203,14 @@ config GPIO_MXS · 202 unmodified lines
203	203	select GPIO_GENERIC
204	204	select GENERIC_IRQ_CHIP
205	205
	206	+config GPIO_OCTEON
	207	+ tristate "Cavium OCTEON GPIO"
	208	+ depends on GPIOLIB && CAVIUM_OCTEON_SOC
	209	+ default y
	210	+ help
	211	+ Say yes here to support the on-chip GPIO lines on the OCTEON
	212	+ family of SOCs.
	213	+
206	214	config GPIO_PL061
207	215	bool "PrimeCell PL061 GPIO support"
208	216	depends on ARM && ARM_AMBA

drivers/gpio/Makefile+1−0

@@ -52,6 +52,7 @@ obj-$(CONFIG_GPIO_MSM_V2) += gpio-msm-v2.o · 51 unmodified lines
52	52	obj-$(CONFIG_GPIO_MVEBU) += gpio-mvebu.o
53	53	obj-$(CONFIG_GPIO_MXC) += gpio-mxc.o
54	54	obj-$(CONFIG_GPIO_MXS) += gpio-mxs.o
	55	+obj-$(CONFIG_GPIO_OCTEON) += gpio-octeon.o
55	56	obj-$(CONFIG_ARCH_OMAP) += gpio-omap.o
56	57	obj-$(CONFIG_GPIO_PCA953X) += gpio-pca953x.o
57	58	obj-$(CONFIG_GPIO_PCF857X) += gpio-pcf857x.o

drivers/gpio/gpio-octeon.c+157−0

@@ -0,0 +1,157 @@
	1	+/*
	2	+ * This file is subject to the terms and conditions of the GNU General Public
	3	+ * License. See the file "COPYING" in the main directory of this archive
	4	+ * for more details.
	5	+ *
	6	+ * Copyright (C) 2011, 2012 Cavium Inc.
	7	+ */
	8	+
	9	+#include <linux/platform_device.h>
	10	+#include <linux/kernel.h>
	11	+#include <linux/module.h>
	12	+#include <linux/gpio.h>
	13	+#include <linux/io.h>
	14	+
	15	+#include <asm/octeon/octeon.h>
	16	+#include <asm/octeon/cvmx-gpio-defs.h>
	17	+
	18	+#define RX_DAT 0x80
	19	+#define TX_SET 0x88
	20	+#define TX_CLEAR 0x90
	21	+/*
	22	+ * The address offset of the GPIO configuration register for a given
	23	+ * line.
	24	+ */
	25	+static unsigned int bit_cfg_reg(unsigned int offset)
	26	+{
	27	+ /*
	28	+ * The register stride is 8, with a discontinuity after the
	29	+ * first 16.
	30	+ */
	31	+ if (offset < 16)
	32	+ return 8 * offset;
	33	+ else
	34	+ return 8 * (offset - 16) + 0x100;
	35	+}
	36	+
	37	+struct octeon_gpio {
	38	+ struct gpio_chip chip;
	39	+ u64 register_base;
	40	+};
	41	+
	42	+static int octeon_gpio_dir_in(struct gpio_chip *chip, unsigned offset)
	43	+{
	44	+ struct octeon_gpio *gpio = container_of(chip, struct octeon_gpio, chip);
	45	+
	46	+ cvmx_write_csr(gpio->register_base + bit_cfg_reg(offset), 0);
	47	+ return 0;
	48	+}
	49	+
	50	+static void octeon_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
	51	+{
	52	+ struct octeon_gpio *gpio = container_of(chip, struct octeon_gpio, chip);
	53	+ u64 mask = 1ull << offset;
	54	+ u64 reg = gpio->register_base + (value ? TX_SET : TX_CLEAR);
	55	+ cvmx_write_csr(reg, mask);
	56	+}
	57	+
	58	+static int octeon_gpio_dir_out(struct gpio_chip *chip, unsigned offset,
	59	+ int value)
	60	+{
	61	+ struct octeon_gpio *gpio = container_of(chip, struct octeon_gpio, chip);
	62	+ union cvmx_gpio_bit_cfgx cfgx;
	63	+
	64	+ octeon_gpio_set(chip, offset, value);
	65	+
	66	+ cfgx.u64 = 0;
	67	+ cfgx.s.tx_oe = 1;
	68	+
	69	+ cvmx_write_csr(gpio->register_base + bit_cfg_reg(offset), cfgx.u64);
	70	+ return 0;
	71	+}
	72	+
	73	+static int octeon_gpio_get(struct gpio_chip *chip, unsigned offset)
	74	+{
	75	+ struct octeon_gpio *gpio = container_of(chip, struct octeon_gpio, chip);
	76	+ u64 read_bits = cvmx_read_csr(gpio->register_base + RX_DAT);
	77	+
	78	+ return ((1ull << offset) & read_bits) != 0;
	79	+}
	80	+
	81	+static int octeon_gpio_probe(struct platform_device *pdev)
	82	+{
	83	+ struct octeon_gpio *gpio;
	84	+ struct gpio_chip *chip;
	85	+ struct resource *res_mem;
	86	+ int err = 0;
	87	+
	88	+ gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
	89	+ if (!gpio)
	90	+ return -ENOMEM;
	91	+ chip = &gpio->chip;
	92	+
	93	+ res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	94	+ if (res_mem == NULL) {
	95	+ dev_err(&pdev->dev, "found no memory resource\n");
	96	+ err = -ENXIO;
	97	+ goto out;
	98	+ }
	99	+ if (!devm_request_mem_region(&pdev->dev, res_mem->start,
	100	+ resource_size(res_mem),
	101	+ res_mem->name)) {
	102	+ dev_err(&pdev->dev, "request_mem_region failed\n");
	103	+ err = -ENXIO;
	104	+ goto out;
	105	+ }
	106	+ gpio->register_base = (u64)devm_ioremap(&pdev->dev, res_mem->start,
	107	+ resource_size(res_mem));
	108	+
	109	+ pdev->dev.platform_data = chip;
	110	+ chip->label = "octeon-gpio";
	111	+ chip->dev = &pdev->dev;
	112	+ chip->owner = THIS_MODULE;
	113	+ chip->base = 0;
	114	+ chip->can_sleep = 0;
	115	+ chip->ngpio = 20;
	116	+ chip->direction_input = octeon_gpio_dir_in;
	117	+ chip->get = octeon_gpio_get;
	118	+ chip->direction_output = octeon_gpio_dir_out;
	119	+ chip->set = octeon_gpio_set;
	120	+ err = gpiochip_add(chip);
	121	+ if (err)
	122	+ goto out;
	123	+
	124	+ dev_info(&pdev->dev, "OCTEON GPIO driver probed.\n");
	125	+out:
	126	+ return err;
	127	+}
	128	+
	129	+static int octeon_gpio_remove(struct platform_device *pdev)
	130	+{
	131	+ struct gpio_chip *chip = pdev->dev.platform_data;
	132	+ return gpiochip_remove(chip);
	133	+}
	134	+
	135	+static struct of_device_id octeon_gpio_match[] = {
	136	+ {
	137	+ .compatible = "cavium,octeon-3860-gpio",
	138	+ },
	139	+ {},
	140	+};
	141	+MODULE_DEVICE_TABLE(of, octeon_gpio_match);
	142	+
	143	+static struct platform_driver octeon_gpio_driver = {
	144	+ .driver = {
	145	+ .name = "octeon_gpio",
	146	+ .owner = THIS_MODULE,
	147	+ .of_match_table = octeon_gpio_match,
	148	+ },
	149	+ .probe = octeon_gpio_probe,
	150	+ .remove = octeon_gpio_remove,
	151	+};
	152	+
	153	+module_platform_driver(octeon_gpio_driver);
	154	+
	155	+MODULE_DESCRIPTION("Cavium Inc. OCTEON GPIO Driver");
	156	+MODULE_AUTHOR("David Daney");
	157	+MODULE_LICENSE("GPL");

scripts/package/buildtar+21−0

@@ -87,6 +87,27 @@ case "${ARCH}" in · 86 unmodified lines
87	87	[ -f "${objtree}/vmlinux.SYS" ] && cp -v -- "${objtree}/vmlinux.SYS" "${tmpdir}/boot/vmlinux-${KERNELRELEASE}.SYS"
88	88	[ -f "${objtree}/vmlinux.dsk" ] && cp -v -- "${objtree}/vmlinux.dsk" "${tmpdir}/boot/vmlinux-${KERNELRELEASE}.dsk"
89	89	;;
	90	+ mips)
	91	+ if [ -f "${objtree}/arch/mips/boot/compressed/vmlinux.bin" ]; then
	92	+ cp -v -- "${objtree}/arch/mips/boot/compressed/vmlinux.bin" "${tmpdir}/boot/vmlinuz-${KERNELRELEASE}"
	93	+ elif [ -f "${objtree}/arch/mips/boot/compressed/vmlinux.ecoff" ]; then
	94	+ cp -v -- "${objtree}/arch/mips/boot/compressed/vmlinux.ecoff" "${tmpdir}/boot/vmlinuz-${KERNELRELEASE}"
	95	+ elif [ -f "${objtree}/arch/mips/boot/compressed/vmlinux.srec" ]; then
	96	+ cp -v -- "${objtree}/arch/mips/boot/compressed/vmlinux.srec" "${tmpdir}/boot/vmlinuz-${KERNELRELEASE}"
	97	+ elif [ -f "${objtree}/vmlinux.32" ]; then
	98	+ cp -v -- "${objtree}/vmlinux.32" "${tmpdir}/boot/vmlinux-${KERNELRELEASE}"
	99	+ elif [ -f "${objtree}/vmlinux.64" ]; then
	100	+ cp -v -- "${objtree}/vmlinux.64" "${tmpdir}/boot/vmlinux-${KERNELRELEASE}"
	101	+ elif [ -f "${objtree}/arch/mips/boot/vmlinux.bin" ]; then
	102	+ cp -v -- "${objtree}/arch/mips/boot/vmlinux.bin" "${tmpdir}/boot/vmlinux-${KERNELRELEASE}"
	103	+ elif [ -f "${objtree}/arch/mips/boot/vmlinux.ecoff" ]; then
	104	+ cp -v -- "${objtree}/arch/mips/boot/vmlinux.ecoff" "${tmpdir}/boot/vmlinux-${KERNELRELEASE}"
	105	+ elif [ -f "${objtree}/arch/mips/boot/vmlinux.srec" ]; then
	106	+ cp -v -- "${objtree}/arch/mips/boot/vmlinux.srec" "${tmpdir}/boot/vmlinux-${KERNELRELEASE}"
	107	+ elif [ -f "${objtree}/vmlinux" ]; then
	108	+ cp -v -- "${objtree}/vmlinux" "${tmpdir}/boot/vmlinux-${KERNELRELEASE}"
	109	+ fi
	110	+ ;;
90	111	*)
91	112	[ -f "${KBUILD_IMAGE}" ] && cp -v -- "${KBUILD_IMAGE}" "${tmpdir}/boot/vmlinux-kbuild-${KERNELRELEASE}"
92	113	echo "" >&2