History

Merge branch 'qca8k-QCA8334-switch-support'

Michal Vokáč says: ==================== Add support for QCA8334 switch This series basically adds support for a QCA8334 ethernet switch to the qca8k driver. It is a four-port variant of the already supported seven port QCA8337. Register map is the same for the whole familly and all chips have the same device ID. Major part of this series enhances the CPU port setting. Currently the CPU port is not set to any sensible defaults compatible with the xGMII interface. This series forces the CPU port to its maximum bandwidth and also allows to adjust the new defaults using fixed-link device tree sub-node. Alongside these changes I fixed two checkpatch warnings regarding SPDX and redundant parentheses. Changes in v3: - Rebased on latest net-next/master. - Corrected fixed-link documentation. ====================

David S. Miller committed 8 years ago

Commit 5a867ab2 parents 038ed45 38222b13 files · +79 −15Browse files

Unified · Split

3 files
  1. Documentation/devicetree/bindings/net/dsa/qca8k.txt +22 −1
  2. drivers/net/dsa/qca8k.c +52 −12
  3. drivers/net/dsa/qca8k.h +5 −2
Documentation/devicetree/bindings/net/dsa/qca8k.txt+22−1
@@ -2,7 +2,10 @@ · 1 unmodified line
2 2
3Required properties:3Required properties:
4 4
5- compatible: should be "qca,qca8337"5- compatible: should be one of:
6 "qca,qca8334"
7 "qca,qca8337"
8
6- #size-cells: must be 09- #size-cells: must be 0
7- #address-cells: must be 110- #address-cells: must be 1
8 11
@@ -14,6 +17,20 @@ port and PHY id, each subnode describing a port needs to have a valid phandle · 5 unmodified lines
14referencing the internal PHY connected to it. The CPU port of this switch is17referencing the internal PHY connected to it. The CPU port of this switch is
15always port 0.18always port 0.
16 19
20A CPU port node has the following optional node:
21
22- fixed-link : Fixed-link subnode describing a link to a non-MDIO
23 managed entity. See
24 Documentation/devicetree/bindings/net/fixed-link.txt
25 for details.
26
27For QCA8K the 'fixed-link' sub-node supports only the following properties:
28
29- 'speed' (integer, mandatory), to indicate the link speed. Accepted
30 values are 10, 100 and 1000
31- 'full-duplex' (boolean, optional), to indicate that full duplex is
32 used. When absent, half duplex is assumed.
33
17Example:34Example:
18 35
19 36
@@ -53,6 +70,10 @@ Example: · 33 unmodified lines
53 label = "cpu";70 label = "cpu";
54 ethernet = <&gmac1>;71 ethernet = <&gmac1>;
55 phy-mode = "rgmii";72 phy-mode = "rgmii";
73 fixed-link {
74 speed = 1000;
75 full-duplex;
76 };
56 };77 };
57 78
58 port@1 {79 port@1 {
drivers/net/dsa/qca8k.c+52−12
@@ -1,17 +1,9 @@
1// SPDX-License-Identifier: GPL-2.0
1/*2/*
2 * Copyright (C) 2009 Felix Fietkau <nbd@nbd.name>3 * Copyright (C) 2009 Felix Fietkau <nbd@nbd.name>
3 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>4 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
4 * Copyright (c) 2015, The Linux Foundation. All rights reserved.5 * Copyright (c) 2015, The Linux Foundation. All rights reserved.
5 * Copyright (c) 2016 John Crispin <john@phrozen.org>6 * Copyright (c) 2016 John Crispin <john@phrozen.org>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 and
9 * only version 2 as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */7 */
16 8
17#include <linux/module.h>9#include <linux/module.h>
@@ -473,10 +465,10 @@ qca8k_set_pad_ctrl(struct qca8k_priv *priv, int port, int mode) · 455 unmodified lines
473static void465static void
474qca8k_port_set_status(struct qca8k_priv *priv, int port, int enable)466qca8k_port_set_status(struct qca8k_priv *priv, int port, int enable)
475{467{
476 u32 mask = QCA8K_PORT_STATUS_TXMAC;468 u32 mask = QCA8K_PORT_STATUS_TXMAC | QCA8K_PORT_STATUS_RXMAC;
477 469
478 /* Port 0 and 6 have no internal PHY */470 /* Port 0 and 6 have no internal PHY */
479 if ((port > 0) && (port < 6))471 if (port > 0 && port < 6)
480 mask |= QCA8K_PORT_STATUS_LINK_AUTO;472 mask |= QCA8K_PORT_STATUS_LINK_AUTO;
481 473
482 if (enable)474 if (enable)
@@ -490,6 +482,7 @@ qca8k_setup(struct dsa_switch *ds) · 7 unmodified lines
490{482{
491 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;483 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
492 int ret, i, phy_mode = -1;484 int ret, i, phy_mode = -1;
485 u32 mask;
493 486
494 /* Make sure that port 0 is the cpu port */487 /* Make sure that port 0 is the cpu port */
495 if (!dsa_is_cpu_port(ds, 0)) {488 if (!dsa_is_cpu_port(ds, 0)) {
@@ -515,7 +508,10 @@ qca8k_setup(struct dsa_switch *ds) · 19 unmodified lines
515 if (ret < 0)508 if (ret < 0)
516 return ret;509 return ret;
517 510
518 /* Enable CPU Port */511 /* Enable CPU Port, force it to maximum bandwidth and full-duplex */
512 mask = QCA8K_PORT_STATUS_SPEED_1000 | QCA8K_PORT_STATUS_TXFLOW |
513 QCA8K_PORT_STATUS_RXFLOW | QCA8K_PORT_STATUS_DUPLEX;
514 qca8k_write(priv, QCA8K_REG_PORT_STATUS(QCA8K_CPU_PORT), mask);
519 qca8k_reg_set(priv, QCA8K_REG_GLOBAL_FW_CTRL0,515 qca8k_reg_set(priv, QCA8K_REG_GLOBAL_FW_CTRL0,
520 QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN);516 QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN);
521 qca8k_port_set_status(priv, QCA8K_CPU_PORT, 1);517 qca8k_port_set_status(priv, QCA8K_CPU_PORT, 1);
@@ -583,6 +579,47 @@ qca8k_setup(struct dsa_switch *ds) · 61 unmodified lines
583 return 0;579 return 0;
584}580}
585 581
582static void
583qca8k_adjust_link(struct dsa_switch *ds, int port, struct phy_device *phy)
584{
585 struct qca8k_priv *priv = ds->priv;
586 u32 reg;
587
588 /* Force fixed-link setting for CPU port, skip others. */
589 if (!phy_is_pseudo_fixed_link(phy))
590 return;
591
592 /* Set port speed */
593 switch (phy->speed) {
594 case 10:
595 reg = QCA8K_PORT_STATUS_SPEED_10;
596 break;
597 case 100:
598 reg = QCA8K_PORT_STATUS_SPEED_100;
599 break;
600 case 1000:
601 reg = QCA8K_PORT_STATUS_SPEED_1000;
602 break;
603 default:
604 dev_dbg(priv->dev, "port%d link speed %dMbps not supported.\n",
605 port, phy->speed);
606 return;
607 }
608
609 /* Set duplex mode */
610 if (phy->duplex == DUPLEX_FULL)
611 reg |= QCA8K_PORT_STATUS_DUPLEX;
612
613 /* Force flow control */
614 if (dsa_is_cpu_port(ds, port))
615 reg |= QCA8K_PORT_STATUS_RXFLOW | QCA8K_PORT_STATUS_TXFLOW;
616
617 /* Force link down before changing MAC options */
618 qca8k_port_set_status(priv, port, 0);
619 qca8k_write(priv, QCA8K_REG_PORT_STATUS(port), reg);
620 qca8k_port_set_status(priv, port, 1);
621}
622
586static int623static int
587qca8k_phy_read(struct dsa_switch *ds, int phy, int regnum)624qca8k_phy_read(struct dsa_switch *ds, int phy, int regnum)
588{625{
@@ -837,6 +874,7 @@ qca8k_get_tag_protocol(struct dsa_switch *ds, int port) · 248 unmodified lines
837static const struct dsa_switch_ops qca8k_switch_ops = {874static const struct dsa_switch_ops qca8k_switch_ops = {
838 .get_tag_protocol = qca8k_get_tag_protocol,875 .get_tag_protocol = qca8k_get_tag_protocol,
839 .setup = qca8k_setup,876 .setup = qca8k_setup,
877 .adjust_link = qca8k_adjust_link,
840 .get_strings = qca8k_get_strings,878 .get_strings = qca8k_get_strings,
841 .phy_read = qca8k_phy_read,879 .phy_read = qca8k_phy_read,
842 .phy_write = qca8k_phy_write,880 .phy_write = qca8k_phy_write,
@@ -868,6 +906,7 @@ qca8k_sw_probe(struct mdio_device *mdiodev) · 25 unmodified lines
868 return -ENOMEM;906 return -ENOMEM;
869 907
870 priv->bus = mdiodev->bus;908 priv->bus = mdiodev->bus;
909 priv->dev = &mdiodev->dev;
871 910
872 /* read the switches ID register */911 /* read the switches ID register */
873 id = qca8k_read(priv, QCA8K_REG_MASK_CTRL);912 id = qca8k_read(priv, QCA8K_REG_MASK_CTRL);
@@ -939,6 +978,7 @@ static SIMPLE_DEV_PM_OPS(qca8k_pm_ops, · 65 unmodified lines
939 qca8k_suspend, qca8k_resume);978 qca8k_suspend, qca8k_resume);
940 979
941static const struct of_device_id qca8k_of_match[] = {980static const struct of_device_id qca8k_of_match[] = {
981 { .compatible = "qca,qca8334" },
942 { .compatible = "qca,qca8337" },982 { .compatible = "qca,qca8337" },
943 { /* sentinel */ },983 { /* sentinel */ },
944};984};
drivers/net/dsa/qca8k.h+5−2
@@ -51,8 +51,10 @@ · 50 unmodified lines
51#define QCA8K_GOL_MAC_ADDR0 0x6051#define QCA8K_GOL_MAC_ADDR0 0x60
52#define QCA8K_GOL_MAC_ADDR1 0x6452#define QCA8K_GOL_MAC_ADDR1 0x64
53#define QCA8K_REG_PORT_STATUS(_i) (0x07c + (_i) * 4)53#define QCA8K_REG_PORT_STATUS(_i) (0x07c + (_i) * 4)
54#define QCA8K_PORT_STATUS_SPEED GENMASK(2, 0)54#define QCA8K_PORT_STATUS_SPEED GENMASK(1, 0)
55#define QCA8K_PORT_STATUS_SPEED_S 055#define QCA8K_PORT_STATUS_SPEED_10 0
56#define QCA8K_PORT_STATUS_SPEED_100 0x1
57#define QCA8K_PORT_STATUS_SPEED_1000 0x2
56#define QCA8K_PORT_STATUS_TXMAC BIT(2)58#define QCA8K_PORT_STATUS_TXMAC BIT(2)
57#define QCA8K_PORT_STATUS_RXMAC BIT(3)59#define QCA8K_PORT_STATUS_RXMAC BIT(3)
58#define QCA8K_PORT_STATUS_TXFLOW BIT(4)60#define QCA8K_PORT_STATUS_TXFLOW BIT(4)
@@ -165,6 +167,7 @@ struct qca8k_priv { · 106 unmodified lines
165 struct ar8xxx_port_status port_sts[QCA8K_NUM_PORTS];167 struct ar8xxx_port_status port_sts[QCA8K_NUM_PORTS];
166 struct dsa_switch *ds;168 struct dsa_switch *ds;
167 struct mutex reg_mutex;169 struct mutex reg_mutex;
170 struct device *dev;
168};171};
169 172
170struct qca8k_mib_desc {173struct qca8k_mib_desc {