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PCI/IOV: Restore VF resizable BAR state after reset

Similar to regular resizable BARs, VF BARs can also be resized, e.g. by the system firmware or the PCI subsystem itself. The capability layout is the same as PCI_EXT_CAP_ID_REBAR. Add the capability ID and restore it as a part of IOV state. See PCIe r6.2, sec 7.8.7.

Michał Winiarski committed 1 year ago

Commit 5a8f77e1 parent 19272b33 files · +50 −1Browse files

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include/uapi/linux/pci_regs.h+9−0
@@ -745,6 +745,7 @@ · 744 unmodified lines
745#define PCI_EXT_CAP_ID_L1SS 0x1E /* L1 PM Substates */745#define PCI_EXT_CAP_ID_L1SS 0x1E /* L1 PM Substates */
746#define PCI_EXT_CAP_ID_PTM 0x1F /* Precision Time Measurement */746#define PCI_EXT_CAP_ID_PTM 0x1F /* Precision Time Measurement */
747#define PCI_EXT_CAP_ID_DVSEC 0x23 /* Designated Vendor-Specific */747#define PCI_EXT_CAP_ID_DVSEC 0x23 /* Designated Vendor-Specific */
748#define PCI_EXT_CAP_ID_VF_REBAR 0x24 /* VF Resizable BAR */
748#define PCI_EXT_CAP_ID_DLF 0x25 /* Data Link Feature */749#define PCI_EXT_CAP_ID_DLF 0x25 /* Data Link Feature */
749#define PCI_EXT_CAP_ID_PL_16GT 0x26 /* Physical Layer 16.0 GT/s */750#define PCI_EXT_CAP_ID_PL_16GT 0x26 /* Physical Layer 16.0 GT/s */
750#define PCI_EXT_CAP_ID_NPEM 0x29 /* Native PCIe Enclosure Management */751#define PCI_EXT_CAP_ID_NPEM 0x29 /* Native PCIe Enclosure Management */
@@ -1141,6 +1142,14 @@ · 390 unmodified lines
1141#define PCI_DVSEC_HEADER2 0x8 /* Designated Vendor-Specific Header2 */1142#define PCI_DVSEC_HEADER2 0x8 /* Designated Vendor-Specific Header2 */
1142#define PCI_DVSEC_HEADER2_ID(x) ((x) & 0xffff)1143#define PCI_DVSEC_HEADER2_ID(x) ((x) & 0xffff)
1143 1144
1145/* VF Resizable BARs, same layout as PCI_REBAR */
1146#define PCI_VF_REBAR_CAP PCI_REBAR_CAP
1147#define PCI_VF_REBAR_CAP_SIZES PCI_REBAR_CAP_SIZES
1148#define PCI_VF_REBAR_CTRL PCI_REBAR_CTRL
1149#define PCI_VF_REBAR_CTRL_BAR_IDX PCI_REBAR_CTRL_BAR_IDX
1150#define PCI_VF_REBAR_CTRL_NBAR_MASK PCI_REBAR_CTRL_NBAR_MASK
1151#define PCI_VF_REBAR_CTRL_BAR_SIZE PCI_REBAR_CTRL_BAR_SIZE
1152
1144/* Data Link Feature */1153/* Data Link Feature */
1145#define PCI_DLF_CAP 0x04 /* Capabilities Register */1154#define PCI_DLF_CAP 0x04 /* Capabilities Register */
1146#define PCI_DLF_EXCHANGE_ENABLE 0x80000000 /* Data Link Feature Exchange Enable */1155#define PCI_DLF_EXCHANGE_ENABLE 0x80000000 /* Data Link Feature Exchange Enable */