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[media] videodev2.h/v4l2-dv-timings.h: add V4L2_DV_FL_IS_CE_VIDEO flag

In the past the V4L2_DV_BT_STD_CEA861 standard bit was used to determine whether the format is a CE (Consumer Electronics) format or not. However, the 640x480p59.94 format is part of the CEA-861 standard, but it is *not* a CE video format. Add a new flag to make this explicit. This information is needed in order to determine the default R'G'B' encoding for the format: for CE video this is limited range (16-235) instead of full range (0-255). The header with all the timings has been updated with this new flag.

Hans Verkuil committed 11 years ago

Commit 5ce65d11 parent acd2b672 files · +45 −25Browse files

Showing the changes to include/uapi (2 of 2 files). Show all

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2 files
  1. include/uapi/linux/v4l2-dv-timings.h +39 −25
  2. include/uapi/linux/videodev2.h +6 −0
include/uapi/linux/v4l2-dv-timings.h+39−25
@@ -48,14 +48,15 @@ · 47 unmodified lines
48 .type = V4L2_DV_BT_656_1120, \48 .type = V4L2_DV_BT_656_1120, \
49 V4L2_INIT_BT_TIMINGS(720, 480, 1, 0, \49 V4L2_INIT_BT_TIMINGS(720, 480, 1, 0, \
50 13500000, 19, 62, 57, 4, 3, 15, 4, 3, 16, \50 13500000, 19, 62, 57, 4, 3, 15, 4, 3, 16, \
51 V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_HALF_LINE) \51 V4L2_DV_BT_STD_CEA861, \
52 V4L2_DV_FL_HALF_LINE | V4L2_DV_FL_IS_CE_VIDEO) \
52}53}
53 54
54#define V4L2_DV_BT_CEA_720X480P59_94 { \55#define V4L2_DV_BT_CEA_720X480P59_94 { \
55 .type = V4L2_DV_BT_656_1120, \56 .type = V4L2_DV_BT_656_1120, \
56 V4L2_INIT_BT_TIMINGS(720, 480, 0, 0, \57 V4L2_INIT_BT_TIMINGS(720, 480, 0, 0, \
57 27000000, 16, 62, 60, 9, 6, 30, 0, 0, 0, \58 27000000, 16, 62, 60, 9, 6, 30, 0, 0, 0, \
58 V4L2_DV_BT_STD_CEA861, 0) \59 V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_IS_CE_VIDEO) \
59}60}
60 61
61/* Note: these are the nominal timings, for HDMI links this format is typically62/* Note: these are the nominal timings, for HDMI links this format is typically
@@ -64,14 +65,15 @@ · 2 unmodified lines
64 .type = V4L2_DV_BT_656_1120, \65 .type = V4L2_DV_BT_656_1120, \
65 V4L2_INIT_BT_TIMINGS(720, 576, 1, 0, \66 V4L2_INIT_BT_TIMINGS(720, 576, 1, 0, \
66 13500000, 12, 63, 69, 2, 3, 19, 2, 3, 20, \67 13500000, 12, 63, 69, 2, 3, 19, 2, 3, 20, \
67 V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_HALF_LINE) \68 V4L2_DV_BT_STD_CEA861, \
69 V4L2_DV_FL_HALF_LINE | V4L2_DV_FL_IS_CE_VIDEO) \
68}70}
69 71
70#define V4L2_DV_BT_CEA_720X576P50 { \72#define V4L2_DV_BT_CEA_720X576P50 { \
71 .type = V4L2_DV_BT_656_1120, \73 .type = V4L2_DV_BT_656_1120, \
72 V4L2_INIT_BT_TIMINGS(720, 576, 0, 0, \74 V4L2_INIT_BT_TIMINGS(720, 576, 0, 0, \
73 27000000, 12, 64, 68, 5, 5, 39, 0, 0, 0, \75 27000000, 12, 64, 68, 5, 5, 39, 0, 0, 0, \
74 V4L2_DV_BT_STD_CEA861, 0) \76 V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_IS_CE_VIDEO) \
75}77}
76 78
77#define V4L2_DV_BT_CEA_1280X720P24 { \79#define V4L2_DV_BT_CEA_1280X720P24 { \
@@ -88,7 +90,7 @@ · 10 unmodified lines
88 V4L2_INIT_BT_TIMINGS(1280, 720, 0, \90 V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
89 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \91 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
90 74250000, 2420, 40, 220, 5, 5, 20, 0, 0, 0, \92 74250000, 2420, 40, 220, 5, 5, 20, 0, 0, 0, \
91 V4L2_DV_BT_STD_CEA861, 0) \93 V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_IS_CE_VIDEO) \
92}94}
93 95
94#define V4L2_DV_BT_CEA_1280X720P30 { \96#define V4L2_DV_BT_CEA_1280X720P30 { \
@@ -96,7 +98,8 @@ · 1 unmodified line
96 V4L2_INIT_BT_TIMINGS(1280, 720, 0, \98 V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
97 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \99 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
98 74250000, 1760, 40, 220, 5, 5, 20, 0, 0, 0, \100 74250000, 1760, 40, 220, 5, 5, 20, 0, 0, 0, \
99 V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_CAN_REDUCE_FPS) \101 V4L2_DV_BT_STD_CEA861, \
102 V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO) \
100}103}
101 104
102#define V4L2_DV_BT_CEA_1280X720P50 { \105#define V4L2_DV_BT_CEA_1280X720P50 { \
@@ -104,7 +107,7 @@ · 1 unmodified line
104 V4L2_INIT_BT_TIMINGS(1280, 720, 0, \107 V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
105 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \108 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
106 74250000, 440, 40, 220, 5, 5, 20, 0, 0, 0, \109 74250000, 440, 40, 220, 5, 5, 20, 0, 0, 0, \
107 V4L2_DV_BT_STD_CEA861, 0) \110 V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_IS_CE_VIDEO) \
108}111}
109 112
110#define V4L2_DV_BT_CEA_1280X720P60 { \113#define V4L2_DV_BT_CEA_1280X720P60 { \
@@ -112,7 +115,8 @@ · 1 unmodified line
112 V4L2_INIT_BT_TIMINGS(1280, 720, 0, \115 V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
113 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \116 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
114 74250000, 110, 40, 220, 5, 5, 20, 0, 0, 0, \117 74250000, 110, 40, 220, 5, 5, 20, 0, 0, 0, \
115 V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_CAN_REDUCE_FPS) \118 V4L2_DV_BT_STD_CEA861, \
119 V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO) \
116}120}
117 121
118#define V4L2_DV_BT_CEA_1920X1080P24 { \122#define V4L2_DV_BT_CEA_1920X1080P24 { \
@@ -120,7 +124,8 @@ · 1 unmodified line
120 V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \124 V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \
121 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \125 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
122 74250000, 638, 44, 148, 4, 5, 36, 0, 0, 0, \126 74250000, 638, 44, 148, 4, 5, 36, 0, 0, 0, \
123 V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_CAN_REDUCE_FPS) \127 V4L2_DV_BT_STD_CEA861, \
128 V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO) \
124}129}
125 130
126#define V4L2_DV_BT_CEA_1920X1080P25 { \131#define V4L2_DV_BT_CEA_1920X1080P25 { \
@@ -128,7 +133,7 @@ · 1 unmodified line
128 V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \133 V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \
129 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \134 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
130 74250000, 528, 44, 148, 4, 5, 36, 0, 0, 0, \135 74250000, 528, 44, 148, 4, 5, 36, 0, 0, 0, \
131 V4L2_DV_BT_STD_CEA861, 0) \136 V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_IS_CE_VIDEO) \
132}137}
133 138
134#define V4L2_DV_BT_CEA_1920X1080P30 { \139#define V4L2_DV_BT_CEA_1920X1080P30 { \
@@ -136,7 +141,8 @@ · 1 unmodified line
136 V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \141 V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \
137 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \142 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
138 74250000, 88, 44, 148, 4, 5, 36, 0, 0, 0, \143 74250000, 88, 44, 148, 4, 5, 36, 0, 0, 0, \
139 V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_CAN_REDUCE_FPS) \144 V4L2_DV_BT_STD_CEA861, \
145 V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO) \
140}146}
141 147
142#define V4L2_DV_BT_CEA_1920X1080I50 { \148#define V4L2_DV_BT_CEA_1920X1080I50 { \
@@ -144,7 +150,8 @@ · 1 unmodified line
144 V4L2_INIT_BT_TIMINGS(1920, 1080, 1, \150 V4L2_INIT_BT_TIMINGS(1920, 1080, 1, \
145 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \151 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
146 74250000, 528, 44, 148, 2, 5, 15, 2, 5, 16, \152 74250000, 528, 44, 148, 2, 5, 15, 2, 5, 16, \
147 V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_HALF_LINE) \153 V4L2_DV_BT_STD_CEA861, \
154 V4L2_DV_FL_HALF_LINE | V4L2_DV_FL_IS_CE_VIDEO) \
148}155}
149 156
150#define V4L2_DV_BT_CEA_1920X1080P50 { \157#define V4L2_DV_BT_CEA_1920X1080P50 { \
@@ -152,7 +159,7 @@ · 1 unmodified line
152 V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \159 V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \
153 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \160 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
154 148500000, 528, 44, 148, 4, 5, 36, 0, 0, 0, \161 148500000, 528, 44, 148, 4, 5, 36, 0, 0, 0, \
155 V4L2_DV_BT_STD_CEA861, 0) \162 V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_IS_CE_VIDEO) \
156}163}
157 164
158#define V4L2_DV_BT_CEA_1920X1080I60 { \165#define V4L2_DV_BT_CEA_1920X1080I60 { \
@@ -161,7 +168,8 @@ · 2 unmodified lines
161 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \168 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
162 74250000, 88, 44, 148, 2, 5, 15, 2, 5, 16, \169 74250000, 88, 44, 148, 2, 5, 15, 2, 5, 16, \
163 V4L2_DV_BT_STD_CEA861, \170 V4L2_DV_BT_STD_CEA861, \
164 V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_HALF_LINE) \171 V4L2_DV_FL_CAN_REDUCE_FPS | \
172 V4L2_DV_FL_HALF_LINE | V4L2_DV_FL_IS_CE_VIDEO) \
165}173}
166 174
167#define V4L2_DV_BT_CEA_1920X1080P60 { \175#define V4L2_DV_BT_CEA_1920X1080P60 { \
@@ -170,77 +178,83 @@ · 2 unmodified lines
170 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \178 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
171 148500000, 88, 44, 148, 4, 5, 36, 0, 0, 0, \179 148500000, 88, 44, 148, 4, 5, 36, 0, 0, 0, \
172 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CEA861, \180 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CEA861, \
173 V4L2_DV_FL_CAN_REDUCE_FPS) \181 V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO) \
174}182}
175 183
176#define V4L2_DV_BT_CEA_3840X2160P24 { \184#define V4L2_DV_BT_CEA_3840X2160P24 { \
177 .type = V4L2_DV_BT_656_1120, \185 .type = V4L2_DV_BT_656_1120, \
178 V4L2_INIT_BT_TIMINGS(3840, 2160, 0, V4L2_DV_HSYNC_POS_POL, \186 V4L2_INIT_BT_TIMINGS(3840, 2160, 0, V4L2_DV_HSYNC_POS_POL, \
179 297000000, 1276, 88, 296, 8, 10, 72, 0, 0, 0, \187 297000000, 1276, 88, 296, 8, 10, 72, 0, 0, 0, \
180 V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_CAN_REDUCE_FPS) \188 V4L2_DV_BT_STD_CEA861, \
189 V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO) \
181}190}
182 191
183#define V4L2_DV_BT_CEA_3840X2160P25 { \192#define V4L2_DV_BT_CEA_3840X2160P25 { \
184 .type = V4L2_DV_BT_656_1120, \193 .type = V4L2_DV_BT_656_1120, \
185 V4L2_INIT_BT_TIMINGS(3840, 2160, 0, V4L2_DV_HSYNC_POS_POL, \194 V4L2_INIT_BT_TIMINGS(3840, 2160, 0, V4L2_DV_HSYNC_POS_POL, \
186 297000000, 1056, 88, 296, 8, 10, 72, 0, 0, 0, \195 297000000, 1056, 88, 296, 8, 10, 72, 0, 0, 0, \
187 V4L2_DV_BT_STD_CEA861, 0) \196 V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_IS_CE_VIDEO) \
188}197}
189 198
190#define V4L2_DV_BT_CEA_3840X2160P30 { \199#define V4L2_DV_BT_CEA_3840X2160P30 { \
191 .type = V4L2_DV_BT_656_1120, \200 .type = V4L2_DV_BT_656_1120, \
192 V4L2_INIT_BT_TIMINGS(3840, 2160, 0, V4L2_DV_HSYNC_POS_POL, \201 V4L2_INIT_BT_TIMINGS(3840, 2160, 0, V4L2_DV_HSYNC_POS_POL, \
193 297000000, 176, 88, 296, 8, 10, 72, 0, 0, 0, \202 297000000, 176, 88, 296, 8, 10, 72, 0, 0, 0, \
194 V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_CAN_REDUCE_FPS) \203 V4L2_DV_BT_STD_CEA861, \
204 V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO) \
195}205}
196 206
197#define V4L2_DV_BT_CEA_3840X2160P50 { \207#define V4L2_DV_BT_CEA_3840X2160P50 { \
198 .type = V4L2_DV_BT_656_1120, \208 .type = V4L2_DV_BT_656_1120, \
199 V4L2_INIT_BT_TIMINGS(3840, 2160, 0, V4L2_DV_HSYNC_POS_POL, \209 V4L2_INIT_BT_TIMINGS(3840, 2160, 0, V4L2_DV_HSYNC_POS_POL, \
200 594000000, 1056, 88, 296, 8, 10, 72, 0, 0, 0, \210 594000000, 1056, 88, 296, 8, 10, 72, 0, 0, 0, \
201 V4L2_DV_BT_STD_CEA861, 0) \211 V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_IS_CE_VIDEO) \
202}212}
203 213
204#define V4L2_DV_BT_CEA_3840X2160P60 { \214#define V4L2_DV_BT_CEA_3840X2160P60 { \
205 .type = V4L2_DV_BT_656_1120, \215 .type = V4L2_DV_BT_656_1120, \
206 V4L2_INIT_BT_TIMINGS(3840, 2160, 0, V4L2_DV_HSYNC_POS_POL, \216 V4L2_INIT_BT_TIMINGS(3840, 2160, 0, V4L2_DV_HSYNC_POS_POL, \
207 594000000, 176, 88, 296, 8, 10, 72, 0, 0, 0, \217 594000000, 176, 88, 296, 8, 10, 72, 0, 0, 0, \
208 V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_CAN_REDUCE_FPS) \218 V4L2_DV_BT_STD_CEA861, \
219 V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO) \
209}220}
210 221
211#define V4L2_DV_BT_CEA_4096X2160P24 { \222#define V4L2_DV_BT_CEA_4096X2160P24 { \
212 .type = V4L2_DV_BT_656_1120, \223 .type = V4L2_DV_BT_656_1120, \
213 V4L2_INIT_BT_TIMINGS(4096, 2160, 0, V4L2_DV_HSYNC_POS_POL, \224 V4L2_INIT_BT_TIMINGS(4096, 2160, 0, V4L2_DV_HSYNC_POS_POL, \
214 297000000, 1020, 88, 296, 8, 10, 72, 0, 0, 0, \225 297000000, 1020, 88, 296, 8, 10, 72, 0, 0, 0, \
215 V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_CAN_REDUCE_FPS) \226 V4L2_DV_BT_STD_CEA861, \
227 V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO) \
216}228}
217 229
218#define V4L2_DV_BT_CEA_4096X2160P25 { \230#define V4L2_DV_BT_CEA_4096X2160P25 { \
219 .type = V4L2_DV_BT_656_1120, \231 .type = V4L2_DV_BT_656_1120, \
220 V4L2_INIT_BT_TIMINGS(4096, 2160, 0, V4L2_DV_HSYNC_POS_POL, \232 V4L2_INIT_BT_TIMINGS(4096, 2160, 0, V4L2_DV_HSYNC_POS_POL, \
221 297000000, 968, 88, 128, 8, 10, 72, 0, 0, 0, \233 297000000, 968, 88, 128, 8, 10, 72, 0, 0, 0, \
222 V4L2_DV_BT_STD_CEA861, 0) \234 V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_IS_CE_VIDEO) \
223}235}
224 236
225#define V4L2_DV_BT_CEA_4096X2160P30 { \237#define V4L2_DV_BT_CEA_4096X2160P30 { \
226 .type = V4L2_DV_BT_656_1120, \238 .type = V4L2_DV_BT_656_1120, \
227 V4L2_INIT_BT_TIMINGS(4096, 2160, 0, V4L2_DV_HSYNC_POS_POL, \239 V4L2_INIT_BT_TIMINGS(4096, 2160, 0, V4L2_DV_HSYNC_POS_POL, \
228 297000000, 88, 88, 128, 8, 10, 72, 0, 0, 0, \240 297000000, 88, 88, 128, 8, 10, 72, 0, 0, 0, \
229 V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_CAN_REDUCE_FPS) \241 V4L2_DV_BT_STD_CEA861, \
242 V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO) \
230}243}
231 244
232#define V4L2_DV_BT_CEA_4096X2160P50 { \245#define V4L2_DV_BT_CEA_4096X2160P50 { \
233 .type = V4L2_DV_BT_656_1120, \246 .type = V4L2_DV_BT_656_1120, \
234 V4L2_INIT_BT_TIMINGS(4096, 2160, 0, V4L2_DV_HSYNC_POS_POL, \247 V4L2_INIT_BT_TIMINGS(4096, 2160, 0, V4L2_DV_HSYNC_POS_POL, \
235 594000000, 968, 88, 128, 8, 10, 72, 0, 0, 0, \248 594000000, 968, 88, 128, 8, 10, 72, 0, 0, 0, \
236 V4L2_DV_BT_STD_CEA861, 0) \249 V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_IS_CE_VIDEO) \
237}250}
238 251
239#define V4L2_DV_BT_CEA_4096X2160P60 { \252#define V4L2_DV_BT_CEA_4096X2160P60 { \
240 .type = V4L2_DV_BT_656_1120, \253 .type = V4L2_DV_BT_656_1120, \
241 V4L2_INIT_BT_TIMINGS(4096, 2160, 0, V4L2_DV_HSYNC_POS_POL, \254 V4L2_INIT_BT_TIMINGS(4096, 2160, 0, V4L2_DV_HSYNC_POS_POL, \
242 594000000, 88, 88, 128, 8, 10, 72, 0, 0, 0, \255 594000000, 88, 88, 128, 8, 10, 72, 0, 0, 0, \
243 V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_CAN_REDUCE_FPS) \256 V4L2_DV_BT_STD_CEA861, \
257 V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO) \
244}258}
245 259
246 260
include/uapi/linux/videodev2.h+6−0
@@ -1188,6 +1188,12 @@ struct v4l2_bt_timings { · 1187 unmodified lines
1188 exactly the same number of half-lines. Whether half-lines can be detected1188 exactly the same number of half-lines. Whether half-lines can be detected
1189 or used depends on the hardware. */1189 or used depends on the hardware. */
1190#define V4L2_DV_FL_HALF_LINE (1 << 3)1190#define V4L2_DV_FL_HALF_LINE (1 << 3)
1191/* If set, then this is a Consumer Electronics (CE) video format. Such formats
1192 * differ from other formats (commonly called IT formats) in that if RGB
1193 * encoding is used then by default the RGB values use limited range (i.e.
1194 * use the range 16-235) as opposed to 0-255. All formats defined in CEA-861
1195 * except for the 640x480 format are CE formats. */
1196#define V4L2_DV_FL_IS_CE_VIDEO (1 << 4)
1191 1197
1192/* A few useful defines to calculate the total blanking and frame sizes */1198/* A few useful defines to calculate the total blanking and frame sizes */
1193#define V4L2_DV_BT_BLANKING_WIDTH(bt) \1199#define V4L2_DV_BT_BLANKING_WIDTH(bt) \

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