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qed: reformat several structures a bit

Reformat a few nvm_cfg* structures (and partly qed_dev) prior to adding new fields and definitions.

Alexander Lobakin committed 6 years ago

Commit 5d4193c1 parent 9bdca143 files · +237 −229Browse files

Unified · Split

3 files
  1. drivers/net/ethernet/qlogic/qed/qed.h +55 −54
  2. drivers/net/ethernet/qlogic/qed/qed_hsi.h +176 −169
  3. drivers/net/ethernet/qlogic/qed/qed_mcp.h +6 −6
drivers/net/ethernet/qlogic/qed/qed.h+55−54
@@ -280,48 +280,49 @@ enum qed_db_rec_exec { · 279 unmodified lines
280 280
281struct qed_hw_info {281struct qed_hw_info {
282 /* PCI personality */282 /* PCI personality */
283 enum qed_pci_personality personality;283 enum qed_pci_personality personality;
284#define QED_IS_RDMA_PERSONALITY(dev) \284#define QED_IS_RDMA_PERSONALITY(dev) \
285 ((dev)->hw_info.personality == QED_PCI_ETH_ROCE || \285 ((dev)->hw_info.personality == QED_PCI_ETH_ROCE || \
286 (dev)->hw_info.personality == QED_PCI_ETH_IWARP || \286 (dev)->hw_info.personality == QED_PCI_ETH_IWARP || \
287 (dev)->hw_info.personality == QED_PCI_ETH_RDMA)287 (dev)->hw_info.personality == QED_PCI_ETH_RDMA)
288#define QED_IS_ROCE_PERSONALITY(dev) \288#define QED_IS_ROCE_PERSONALITY(dev) \
289 ((dev)->hw_info.personality == QED_PCI_ETH_ROCE || \289 ((dev)->hw_info.personality == QED_PCI_ETH_ROCE || \
290 (dev)->hw_info.personality == QED_PCI_ETH_RDMA)290 (dev)->hw_info.personality == QED_PCI_ETH_RDMA)
291#define QED_IS_IWARP_PERSONALITY(dev) \291#define QED_IS_IWARP_PERSONALITY(dev) \
292 ((dev)->hw_info.personality == QED_PCI_ETH_IWARP || \292 ((dev)->hw_info.personality == QED_PCI_ETH_IWARP || \
293 (dev)->hw_info.personality == QED_PCI_ETH_RDMA)293 (dev)->hw_info.personality == QED_PCI_ETH_RDMA)
294#define QED_IS_L2_PERSONALITY(dev) \294#define QED_IS_L2_PERSONALITY(dev) \
295 ((dev)->hw_info.personality == QED_PCI_ETH || \295 ((dev)->hw_info.personality == QED_PCI_ETH || \
296 QED_IS_RDMA_PERSONALITY(dev))296 QED_IS_RDMA_PERSONALITY(dev))
297#define QED_IS_FCOE_PERSONALITY(dev) \297#define QED_IS_FCOE_PERSONALITY(dev) \
298 ((dev)->hw_info.personality == QED_PCI_FCOE)298 ((dev)->hw_info.personality == QED_PCI_FCOE)
299#define QED_IS_ISCSI_PERSONALITY(dev) \299#define QED_IS_ISCSI_PERSONALITY(dev) \
300 ((dev)->hw_info.personality == QED_PCI_ISCSI)300 ((dev)->hw_info.personality == QED_PCI_ISCSI)
301 301
302 /* Resource Allocation scheme results */302 /* Resource Allocation scheme results */
303 u32 resc_start[QED_MAX_RESC];303 u32 resc_start[QED_MAX_RESC];
304 u32 resc_num[QED_MAX_RESC];304 u32 resc_num[QED_MAX_RESC];
305 u32 feat_num[QED_MAX_FEATURES];305#define RESC_START(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_start[resc])
306#define RESC_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_num[resc])
307#define RESC_END(_p_hwfn, resc) (RESC_START(_p_hwfn, resc) + \
308 RESC_NUM(_p_hwfn, resc))
306 309
307#define RESC_START(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_start[resc])310 u32 feat_num[QED_MAX_FEATURES];
308#define RESC_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_num[resc])311#define FEAT_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.feat_num[resc])
309#define RESC_END(_p_hwfn, resc) (RESC_START(_p_hwfn, resc) + \
310 RESC_NUM(_p_hwfn, resc))
311#define FEAT_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.feat_num[resc])
312 312
313 /* Amount of traffic classes HW supports */313 /* Amount of traffic classes HW supports */
314 u8 num_hw_tc;314 u8 num_hw_tc;
315 315
316 /* Amount of TCs which should be active according to DCBx or upper316 /* Amount of TCs which should be active according to DCBx or upper
317 * layer driver configuration.317 * layer driver configuration.
318 */318 */
319 u8 num_active_tc;319 u8 num_active_tc;
320
320 u8 offload_tc;321 u8 offload_tc;
321 bool offload_tc_set;322 bool offload_tc_set;
322 323
323 bool multi_tc_roce_en;324 bool multi_tc_roce_en;
324#define IS_QED_MULTI_TC_ROCE(p_hwfn) (((p_hwfn)->hw_info.multi_tc_roce_en))325#define IS_QED_MULTI_TC_ROCE(p_hwfn) ((p_hwfn)->hw_info.multi_tc_roce_en)
325 326
326 u32 concrete_fid;327 u32 concrete_fid;
327 u16 opaque_fid;328 u16 opaque_fid;
@@ -338,10 +339,10 @@ struct qed_hw_info { · 10 unmodified lines
338 339
339 u32 port_mode;340 u32 port_mode;
340 u32 hw_mode;341 u32 hw_mode;
341 unsigned long device_capabilities;342 unsigned long device_capabilities;
342 u16 mtu;343 u16 mtu;
343 344
344 enum qed_wol_support b_wol_support;345 enum qed_wol_support b_wol_support;
345};346};
346 347
347/* maximun size of read/write commands (HW limit) */348/* maximun size of read/write commands (HW limit) */
@@ -715,41 +716,41 @@ struct qed_dbg_feature { · 367 unmodified lines
715};716};
716 717
717struct qed_dev {718struct qed_dev {
718 u32 dp_module;719 u32 dp_module;
719 u8 dp_level;720 u8 dp_level;
720 char name[NAME_SIZE];721 char name[NAME_SIZE];
721 722
722 enum qed_dev_type type;723 enum qed_dev_type type;
723/* Translate type/revision combo into the proper conditions */724 /* Translate type/revision combo into the proper conditions */
724#define QED_IS_BB(dev) ((dev)->type == QED_DEV_TYPE_BB)725#define QED_IS_BB(dev) ((dev)->type == QED_DEV_TYPE_BB)
725#define QED_IS_BB_B0(dev) (QED_IS_BB(dev) && \726#define QED_IS_BB_B0(dev) (QED_IS_BB(dev) && CHIP_REV_IS_B0(dev))
726 CHIP_REV_IS_B0(dev))727#define QED_IS_AH(dev) ((dev)->type == QED_DEV_TYPE_AH)
727#define QED_IS_AH(dev) ((dev)->type == QED_DEV_TYPE_AH)728#define QED_IS_K2(dev) QED_IS_AH(dev)
728#define QED_IS_K2(dev) QED_IS_AH(dev)729#define QED_IS_E4(dev) (QED_IS_BB(dev) || QED_IS_AH(dev))
729 730
730 u16 vendor_id;731 u16 vendor_id;
731 u16 device_id;732
732#define QED_DEV_ID_MASK 0xff00733 u16 device_id;
733#define QED_DEV_ID_MASK_BB 0x1600734#define QED_DEV_ID_MASK 0xff00
734#define QED_DEV_ID_MASK_AH 0x8000735#define QED_DEV_ID_MASK_BB 0x1600
735#define QED_IS_E4(dev) (QED_IS_BB(dev) || QED_IS_AH(dev))736#define QED_DEV_ID_MASK_AH 0x8000
736 737
737 u16 chip_num;738 u16 chip_num;
738#define CHIP_NUM_MASK 0xffff739#define CHIP_NUM_MASK 0xffff
739#define CHIP_NUM_SHIFT 16740#define CHIP_NUM_SHIFT 16
740 741
741 u16 chip_rev;742 u16 chip_rev;
742#define CHIP_REV_MASK 0xf743#define CHIP_REV_MASK 0xf
743#define CHIP_REV_SHIFT 12744#define CHIP_REV_SHIFT 12
744#define CHIP_REV_IS_B0(_cdev) ((_cdev)->chip_rev == 1)745#define CHIP_REV_IS_B0(_cdev) ((_cdev)->chip_rev == 1)
745 746
746 u16 chip_metal;747 u16 chip_metal;
747#define CHIP_METAL_MASK 0xff748#define CHIP_METAL_MASK 0xff
748#define CHIP_METAL_SHIFT 4749#define CHIP_METAL_SHIFT 4
749 750
750 u16 chip_bond_id;751 u16 chip_bond_id;
751#define CHIP_BOND_ID_MASK 0xf752#define CHIP_BOND_ID_MASK 0xf
752#define CHIP_BOND_ID_SHIFT 0753#define CHIP_BOND_ID_SHIFT 0
753 754
754 u8 num_engines;755 u8 num_engines;
755 u8 num_ports;756 u8 num_ports;
drivers/net/ethernet/qlogic/qed/qed_hsi.h+176−169
@@ -12532,67 +12532,67 @@ struct public_drv_mb { · 12531 unmodified lines
12532#define DRV_MB_PARAM_SET_LED_MODE_ON 0x112532#define DRV_MB_PARAM_SET_LED_MODE_ON 0x1
12533#define DRV_MB_PARAM_SET_LED_MODE_OFF 0x212533#define DRV_MB_PARAM_SET_LED_MODE_OFF 0x2
12534 12534
12535#define DRV_MB_PARAM_TRANSCEIVER_PORT_OFFSET 012535#define DRV_MB_PARAM_TRANSCEIVER_PORT_OFFSET 0
12536#define DRV_MB_PARAM_TRANSCEIVER_PORT_MASK 0x0000000312536#define DRV_MB_PARAM_TRANSCEIVER_PORT_MASK 0x00000003
12537#define DRV_MB_PARAM_TRANSCEIVER_SIZE_OFFSET 212537#define DRV_MB_PARAM_TRANSCEIVER_SIZE_OFFSET 2
12538#define DRV_MB_PARAM_TRANSCEIVER_SIZE_MASK 0x000000FC12538#define DRV_MB_PARAM_TRANSCEIVER_SIZE_MASK 0x000000fc
12539#define DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_OFFSET 812539#define DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_OFFSET 8
12540#define DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK 0x0000FF0012540#define DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK 0x0000ff00
12541#define DRV_MB_PARAM_TRANSCEIVER_OFFSET_OFFSET 1612541#define DRV_MB_PARAM_TRANSCEIVER_OFFSET_OFFSET 16
12542#define DRV_MB_PARAM_TRANSCEIVER_OFFSET_MASK 0xFFFF000012542#define DRV_MB_PARAM_TRANSCEIVER_OFFSET_MASK 0xffff0000
12543 12543
12544 /* Resource Allocation params - Driver version support */12544 /* Resource Allocation params - Driver version support */
12545#define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_MASK 0xFFFF000012545#define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_MASK 0xffff0000
12546#define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_SHIFT 1612546#define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_SHIFT 16
12547#define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_MASK 0x0000FFFF12547#define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_MASK 0x0000ffff
12548#define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_SHIFT 012548#define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_SHIFT 0
12549 12549
12550#define DRV_MB_PARAM_BIST_REGISTER_TEST 112550#define DRV_MB_PARAM_BIST_REGISTER_TEST 1
12551#define DRV_MB_PARAM_BIST_CLOCK_TEST 212551#define DRV_MB_PARAM_BIST_CLOCK_TEST 2
12552#define DRV_MB_PARAM_BIST_NVM_TEST_NUM_IMAGES 312552#define DRV_MB_PARAM_BIST_NVM_TEST_NUM_IMAGES 3
12553#define DRV_MB_PARAM_BIST_NVM_TEST_IMAGE_BY_INDEX 412553#define DRV_MB_PARAM_BIST_NVM_TEST_IMAGE_BY_INDEX 4
12554 12554
12555#define DRV_MB_PARAM_BIST_RC_UNKNOWN 012555#define DRV_MB_PARAM_BIST_RC_UNKNOWN 0
12556#define DRV_MB_PARAM_BIST_RC_PASSED 112556#define DRV_MB_PARAM_BIST_RC_PASSED 1
12557#define DRV_MB_PARAM_BIST_RC_FAILED 212557#define DRV_MB_PARAM_BIST_RC_FAILED 2
12558#define DRV_MB_PARAM_BIST_RC_INVALID_PARAMETER 312558#define DRV_MB_PARAM_BIST_RC_INVALID_PARAMETER 3
12559 12559
12560#define DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT 012560#define DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT 0
12561#define DRV_MB_PARAM_BIST_TEST_INDEX_MASK 0x000000FF12561#define DRV_MB_PARAM_BIST_TEST_INDEX_MASK 0x000000ff
12562#define DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_SHIFT 812562#define DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_SHIFT 8
12563#define DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_MASK 0x0000FF0012563#define DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_MASK 0x0000ff00
12564 12564
12565#define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_MASK 0x0000FFFF12565#define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_MASK 0x0000ffff
12566#define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_OFFSET 012566#define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_OFFSET 0
12567#define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_EEE 0x0000000212567#define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_EEE 0x00000002
12568#define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_FEC_CONTROL 0x0000000412568#define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_FEC_CONTROL 0x00000004
12569#define DRV_MB_PARAM_FEATURE_SUPPORT_FUNC_VLINK 0x0001000012569#define DRV_MB_PARAM_FEATURE_SUPPORT_FUNC_VLINK 0x00010000
12570 12570
12571/* DRV_MSG_CODE_DEBUG_DATA_SEND parameters */12571/* DRV_MSG_CODE_DEBUG_DATA_SEND parameters */
12572#define DRV_MSG_CODE_DEBUG_DATA_SEND_SIZE_OFFSET 012572#define DRV_MSG_CODE_DEBUG_DATA_SEND_SIZE_OFFSET 0
12573#define DRV_MSG_CODE_DEBUG_DATA_SEND_SIZE_MASK 0xFF12573#define DRV_MSG_CODE_DEBUG_DATA_SEND_SIZE_MASK 0xff
12574 12574
12575/* Driver attributes params */12575/* Driver attributes params */
12576#define DRV_MB_PARAM_ATTRIBUTE_KEY_OFFSET 012576#define DRV_MB_PARAM_ATTRIBUTE_KEY_OFFSET 0
12577#define DRV_MB_PARAM_ATTRIBUTE_KEY_MASK 0x00FFFFFF12577#define DRV_MB_PARAM_ATTRIBUTE_KEY_MASK 0x00ffffff
12578#define DRV_MB_PARAM_ATTRIBUTE_CMD_OFFSET 2412578#define DRV_MB_PARAM_ATTRIBUTE_CMD_OFFSET 24
12579#define DRV_MB_PARAM_ATTRIBUTE_CMD_MASK 0xFF00000012579#define DRV_MB_PARAM_ATTRIBUTE_CMD_MASK 0xff000000
12580 12580
12581#define DRV_MB_PARAM_NVM_CFG_OPTION_ID_OFFSET 012581#define DRV_MB_PARAM_NVM_CFG_OPTION_ID_OFFSET 0
12582#define DRV_MB_PARAM_NVM_CFG_OPTION_ID_SHIFT 012582#define DRV_MB_PARAM_NVM_CFG_OPTION_ID_SHIFT 0
12583#define DRV_MB_PARAM_NVM_CFG_OPTION_ID_MASK 0x0000FFFF12583#define DRV_MB_PARAM_NVM_CFG_OPTION_ID_MASK 0x0000ffff
12584#define DRV_MB_PARAM_NVM_CFG_OPTION_ALL_SHIFT 1612584#define DRV_MB_PARAM_NVM_CFG_OPTION_ALL_SHIFT 16
12585#define DRV_MB_PARAM_NVM_CFG_OPTION_ALL_MASK 0x0001000012585#define DRV_MB_PARAM_NVM_CFG_OPTION_ALL_MASK 0x00010000
12586#define DRV_MB_PARAM_NVM_CFG_OPTION_INIT_SHIFT 1712586#define DRV_MB_PARAM_NVM_CFG_OPTION_INIT_SHIFT 17
12587#define DRV_MB_PARAM_NVM_CFG_OPTION_INIT_MASK 0x0002000012587#define DRV_MB_PARAM_NVM_CFG_OPTION_INIT_MASK 0x00020000
12588#define DRV_MB_PARAM_NVM_CFG_OPTION_COMMIT_SHIFT 1812588#define DRV_MB_PARAM_NVM_CFG_OPTION_COMMIT_SHIFT 18
12589#define DRV_MB_PARAM_NVM_CFG_OPTION_COMMIT_MASK 0x0004000012589#define DRV_MB_PARAM_NVM_CFG_OPTION_COMMIT_MASK 0x00040000
12590#define DRV_MB_PARAM_NVM_CFG_OPTION_FREE_SHIFT 1912590#define DRV_MB_PARAM_NVM_CFG_OPTION_FREE_SHIFT 19
12591#define DRV_MB_PARAM_NVM_CFG_OPTION_FREE_MASK 0x0008000012591#define DRV_MB_PARAM_NVM_CFG_OPTION_FREE_MASK 0x00080000
12592#define DRV_MB_PARAM_NVM_CFG_OPTION_ENTITY_SEL_SHIFT 2012592#define DRV_MB_PARAM_NVM_CFG_OPTION_ENTITY_SEL_SHIFT 20
12593#define DRV_MB_PARAM_NVM_CFG_OPTION_ENTITY_SEL_MASK 0x0010000012593#define DRV_MB_PARAM_NVM_CFG_OPTION_ENTITY_SEL_MASK 0x00100000
12594#define DRV_MB_PARAM_NVM_CFG_OPTION_ENTITY_ID_SHIFT 2412594#define DRV_MB_PARAM_NVM_CFG_OPTION_ENTITY_ID_SHIFT 24
12595#define DRV_MB_PARAM_NVM_CFG_OPTION_ENTITY_ID_MASK 0x0f00000012595#define DRV_MB_PARAM_NVM_CFG_OPTION_ENTITY_ID_MASK 0x0f000000
12596 12596
12597 u32 fw_mb_header;12597 u32 fw_mb_header;
12598#define FW_MSG_CODE_MASK 0xffff000012598#define FW_MSG_CODE_MASK 0xffff0000
@@ -12639,56 +12639,56 @@ struct public_drv_mb { · 40 unmodified lines
12639 12639
12640#define FW_MSG_CODE_MDUMP_INVALID_CMD 0x0003000012640#define FW_MSG_CODE_MDUMP_INVALID_CMD 0x00030000
12641 12641
12642 u32 fw_mb_param;12642 u32 fw_mb_param;
12643#define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_MASK 0xffff000012643#define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_MASK 0xffff0000
12644#define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_SHIFT 1612644#define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_SHIFT 16
12645#define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_MASK 0x0000ffff12645#define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_MASK 0x0000ffff
12646#define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_SHIFT 012646#define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_SHIFT 0
12647 12647
12648 /* Get PF RDMA protocol command response */12648 /* Get PF RDMA protocol command response */
12649#define FW_MB_PARAM_GET_PF_RDMA_NONE 0x012649#define FW_MB_PARAM_GET_PF_RDMA_NONE 0x0
12650#define FW_MB_PARAM_GET_PF_RDMA_ROCE 0x112650#define FW_MB_PARAM_GET_PF_RDMA_ROCE 0x1
12651#define FW_MB_PARAM_GET_PF_RDMA_IWARP 0x212651#define FW_MB_PARAM_GET_PF_RDMA_IWARP 0x2
12652#define FW_MB_PARAM_GET_PF_RDMA_BOTH 0x312652#define FW_MB_PARAM_GET_PF_RDMA_BOTH 0x3
12653 12653
12654 /* Get MFW feature support response */12654 /* Get MFW feature support response */
12655#define FW_MB_PARAM_FEATURE_SUPPORT_SMARTLINQ 0x0000000112655#define FW_MB_PARAM_FEATURE_SUPPORT_SMARTLINQ BIT(0)
12656#define FW_MB_PARAM_FEATURE_SUPPORT_EEE 0x0000000212656#define FW_MB_PARAM_FEATURE_SUPPORT_EEE BIT(1)
12657#define FW_MB_PARAM_FEATURE_SUPPORT_FEC_CONTROL 0x0000002012657#define FW_MB_PARAM_FEATURE_SUPPORT_FEC_CONTROL BIT(5)
12658#define FW_MB_PARAM_FEATURE_SUPPORT_VLINK 0x0001000012658#define FW_MB_PARAM_FEATURE_SUPPORT_VLINK BIT(16)
12659 12659
12660#define FW_MB_PARAM_LOAD_DONE_DID_EFUSE_ERROR BIT(0)12660#define FW_MB_PARAM_LOAD_DONE_DID_EFUSE_ERROR BIT(0)
12661 12661
12662#define FW_MB_PARAM_ENG_CFG_FIR_AFFIN_VALID_MASK 0x0000000112662#define FW_MB_PARAM_ENG_CFG_FIR_AFFIN_VALID_MASK 0x00000001
12663#define FW_MB_PARAM_ENG_CFG_FIR_AFFIN_VALID_SHIFT 012663#define FW_MB_PARAM_ENG_CFG_FIR_AFFIN_VALID_SHIFT 0
12664#define FW_MB_PARAM_ENG_CFG_FIR_AFFIN_VALUE_MASK 0x0000000212664#define FW_MB_PARAM_ENG_CFG_FIR_AFFIN_VALUE_MASK 0x00000002
12665#define FW_MB_PARAM_ENG_CFG_FIR_AFFIN_VALUE_SHIFT 112665#define FW_MB_PARAM_ENG_CFG_FIR_AFFIN_VALUE_SHIFT 1
12666#define FW_MB_PARAM_ENG_CFG_L2_AFFIN_VALID_MASK 0x0000000412666#define FW_MB_PARAM_ENG_CFG_L2_AFFIN_VALID_MASK 0x00000004
12667#define FW_MB_PARAM_ENG_CFG_L2_AFFIN_VALID_SHIFT 212667#define FW_MB_PARAM_ENG_CFG_L2_AFFIN_VALID_SHIFT 2
12668#define FW_MB_PARAM_ENG_CFG_L2_AFFIN_VALUE_MASK 0x0000000812668#define FW_MB_PARAM_ENG_CFG_L2_AFFIN_VALUE_MASK 0x00000008
12669#define FW_MB_PARAM_ENG_CFG_L2_AFFIN_VALUE_SHIFT 312669#define FW_MB_PARAM_ENG_CFG_L2_AFFIN_VALUE_SHIFT 3
12670 12670
12671#define FW_MB_PARAM_PPFID_BITMAP_MASK 0xff12671#define FW_MB_PARAM_PPFID_BITMAP_MASK 0xff
12672#define FW_MB_PARAM_PPFID_BITMAP_SHIFT 012672#define FW_MB_PARAM_PPFID_BITMAP_SHIFT 0
12673 12673
12674 u32 drv_pulse_mb;12674 u32 drv_pulse_mb;
12675#define DRV_PULSE_SEQ_MASK 0x00007fff12675#define DRV_PULSE_SEQ_MASK 0x00007fff
12676#define DRV_PULSE_SYSTEM_TIME_MASK 0xffff000012676#define DRV_PULSE_SYSTEM_TIME_MASK 0xffff0000
12677#define DRV_PULSE_ALWAYS_ALIVE 0x0000800012677#define DRV_PULSE_ALWAYS_ALIVE 0x00008000
12678 12678
12679 u32 mcp_pulse_mb;12679 u32 mcp_pulse_mb;
12680#define MCP_PULSE_SEQ_MASK 0x00007fff12680#define MCP_PULSE_SEQ_MASK 0x00007fff
12681#define MCP_PULSE_ALWAYS_ALIVE 0x0000800012681#define MCP_PULSE_ALWAYS_ALIVE 0x00008000
12682#define MCP_EVENT_MASK 0xffff000012682#define MCP_EVENT_MASK 0xffff0000
12683#define MCP_EVENT_OTHER_DRIVER_RESET_REQ 0x0001000012683#define MCP_EVENT_OTHER_DRIVER_RESET_REQ 0x00010000
12684 12684
12685 union drv_union_data union_data;12685 union drv_union_data union_data;
12686};12686};
12687 12687
12688#define FW_MB_PARAM_NVM_PUT_FILE_REQ_OFFSET_MASK 0x00ffffff12688#define FW_MB_PARAM_NVM_PUT_FILE_REQ_OFFSET_MASK 0x00ffffff
12689#define FW_MB_PARAM_NVM_PUT_FILE_REQ_OFFSET_SHIFT 012689#define FW_MB_PARAM_NVM_PUT_FILE_REQ_OFFSET_SHIFT 0
12690#define FW_MB_PARAM_NVM_PUT_FILE_REQ_SIZE_MASK 0xff00000012690#define FW_MB_PARAM_NVM_PUT_FILE_REQ_SIZE_MASK 0xff000000
12691#define FW_MB_PARAM_NVM_PUT_FILE_REQ_SIZE_SHIFT 2412691#define FW_MB_PARAM_NVM_PUT_FILE_REQ_SIZE_SHIFT 24
12692 12692
12693enum MFW_DRV_MSG_TYPE {12693enum MFW_DRV_MSG_TYPE {
12694 MFW_DRV_MSG_LINK_CHANGE,12694 MFW_DRV_MSG_LINK_CHANGE,
@@ -12975,86 +12975,93 @@ enum tlvs { · 280 unmodified lines
12975};12975};
12976 12976
12977struct nvm_cfg_mac_address {12977struct nvm_cfg_mac_address {
12978 u32 mac_addr_hi;12978 u32 mac_addr_hi;
12979#define NVM_CFG_MAC_ADDRESS_HI_MASK 0x0000FFFF12979#define NVM_CFG_MAC_ADDRESS_HI_MASK 0x0000ffff
12980#define NVM_CFG_MAC_ADDRESS_HI_OFFSET 012980#define NVM_CFG_MAC_ADDRESS_HI_OFFSET 0
12981 u32 mac_addr_lo;12981
12982 u32 mac_addr_lo;
12982};12983};
12983 12984
12984struct nvm_cfg1_glob {12985struct nvm_cfg1_glob {
12985 u32 generic_cont0;12986 u32 generic_cont0;
12986#define NVM_CFG1_GLOB_MF_MODE_MASK 0x00000FF012987#define NVM_CFG1_GLOB_MF_MODE_MASK 0x00000ff0
12987#define NVM_CFG1_GLOB_MF_MODE_OFFSET 412988#define NVM_CFG1_GLOB_MF_MODE_OFFSET 4
12988#define NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED 0x012989#define NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED 0x0
12989#define NVM_CFG1_GLOB_MF_MODE_DEFAULT 0x112990#define NVM_CFG1_GLOB_MF_MODE_DEFAULT 0x1
12990#define NVM_CFG1_GLOB_MF_MODE_SPIO4 0x212991#define NVM_CFG1_GLOB_MF_MODE_SPIO4 0x2
12991#define NVM_CFG1_GLOB_MF_MODE_NPAR1_0 0x312992#define NVM_CFG1_GLOB_MF_MODE_NPAR1_0 0x3
12992#define NVM_CFG1_GLOB_MF_MODE_NPAR1_5 0x412993#define NVM_CFG1_GLOB_MF_MODE_NPAR1_5 0x4
12993#define NVM_CFG1_GLOB_MF_MODE_NPAR2_0 0x512994#define NVM_CFG1_GLOB_MF_MODE_NPAR2_0 0x5
12994#define NVM_CFG1_GLOB_MF_MODE_BD 0x612995#define NVM_CFG1_GLOB_MF_MODE_BD 0x6
12995#define NVM_CFG1_GLOB_MF_MODE_UFP 0x712996#define NVM_CFG1_GLOB_MF_MODE_UFP 0x7
12996 u32 engineering_change[3];12997
12997 u32 manufacturing_id;12998 u32 engineering_change[3];
12998 u32 serial_number[4];12999 u32 manufacturing_id;
12999 u32 pcie_cfg;13000 u32 serial_number[4];
13000 u32 mgmt_traffic;13001 u32 pcie_cfg;
13001 u32 core_cfg;13002 u32 mgmt_traffic;
13002#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK 0x000000FF13003
13003#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET 013004 u32 core_cfg;
13004#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G 0x013005#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK 0x000000ff
13005#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G 0x113006#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET 0
13006#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G 0x213007#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G 0x0
13007#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F 0x313008#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G 0x1
13008#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E 0x413009#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G 0x2
13009#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G 0x513010#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F 0x3
13010#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G 0xB13011#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E 0x4
13011#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G 0xC13012#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G 0x5
13012#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G 0xD13013#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G 0xb
13013#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G 0xE13014#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G 0xc
13014#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G 0xF13015#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G 0xd
13015 13016#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G 0xe
13016 u32 e_lane_cfg1;13017#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G 0xf
13017 u32 e_lane_cfg2;13018
13018 u32 f_lane_cfg1;13019 u32 e_lane_cfg1;
13019 u32 f_lane_cfg2;13020 u32 e_lane_cfg2;
13020 u32 mps10_preemphasis;13021 u32 f_lane_cfg1;
13021 u32 mps10_driver_current;13022 u32 f_lane_cfg2;
13022 u32 mps25_preemphasis;13023 u32 mps10_preemphasis;
13023 u32 mps25_driver_current;13024 u32 mps10_driver_current;
13024 u32 pci_id;13025 u32 mps25_preemphasis;
13025 u32 pci_subsys_id;13026 u32 mps25_driver_current;
13026 u32 bar;13027 u32 pci_id;
13027 u32 mps10_txfir_main;13028 u32 pci_subsys_id;
13028 u32 mps10_txfir_post;13029 u32 bar;
13029 u32 mps25_txfir_main;13030 u32 mps10_txfir_main;
13030 u32 mps25_txfir_post;13031 u32 mps10_txfir_post;
13031 u32 manufacture_ver;13032 u32 mps25_txfir_main;
13032 u32 manufacture_time;13033 u32 mps25_txfir_post;
13033 u32 led_global_settings;13034 u32 manufacture_ver;
13034 u32 generic_cont1;13035 u32 manufacture_time;
13035 u32 mbi_version;13036 u32 led_global_settings;
13036#define NVM_CFG1_GLOB_MBI_VERSION_0_MASK 0x000000FF13037 u32 generic_cont1;
13037#define NVM_CFG1_GLOB_MBI_VERSION_0_OFFSET 013038
13038#define NVM_CFG1_GLOB_MBI_VERSION_1_MASK 0x0000FF0013039 u32 mbi_version;
13039#define NVM_CFG1_GLOB_MBI_VERSION_1_OFFSET 813040#define NVM_CFG1_GLOB_MBI_VERSION_0_MASK 0x000000ff
13040#define NVM_CFG1_GLOB_MBI_VERSION_2_MASK 0x00FF000013041#define NVM_CFG1_GLOB_MBI_VERSION_0_OFFSET 0
13041#define NVM_CFG1_GLOB_MBI_VERSION_2_OFFSET 1613042#define NVM_CFG1_GLOB_MBI_VERSION_1_MASK 0x0000ff00
13042 u32 mbi_date;13043#define NVM_CFG1_GLOB_MBI_VERSION_1_OFFSET 8
13043 u32 misc_sig;13044#define NVM_CFG1_GLOB_MBI_VERSION_2_MASK 0x00ff0000
13044 u32 device_capabilities;13045#define NVM_CFG1_GLOB_MBI_VERSION_2_OFFSET 16
13045#define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET 0x113046
13046#define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE 0x213047 u32 mbi_date;
13047#define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI 0x413048 u32 misc_sig;
13048#define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE 0x813049
13049 u32 power_dissipated;13050 u32 device_capabilities;
13050 u32 power_consumed;13051#define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET 0x1
13051 u32 efi_version;13052#define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE 0x2
13052 u32 multi_network_modes_capability;13053#define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI 0x4
13053 u32 reserved[41];13054#define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE 0x8
13055
13056 u32 power_dissipated;
13057 u32 power_consumed;
13058 u32 efi_version;
13059 u32 multi_net_modes_cap;
13060 u32 reserved[41];
13054};13061};
13055 13062
13056struct nvm_cfg1_path {13063struct nvm_cfg1_path {
13057 u32 reserved[30];13064 u32 reserved[30];
13058};13065};
13059 13066
13060struct nvm_cfg1_port {13067struct nvm_cfg1_port {
@@ -13082,7 +13089,7 @@ struct nvm_cfg1_port { · 21 unmodified lines
13082#define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_OFFSET 013089#define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_OFFSET 0
13083#define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G 0x113090#define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G 0x1
13084#define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G 0x213091#define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G 0x2
13085#define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_20G 0x413092#define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_20G 0x4
13086#define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G 0x813093#define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G 0x8
13087#define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G 0x1013094#define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G 0x10
13088#define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G 0x2013095#define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G 0x20
@@ -13094,7 +13101,7 @@ struct nvm_cfg1_port { · 5 unmodified lines
13094#define NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG 0x013101#define NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG 0x0
13095#define NVM_CFG1_PORT_DRV_LINK_SPEED_1G 0x113102#define NVM_CFG1_PORT_DRV_LINK_SPEED_1G 0x1
13096#define NVM_CFG1_PORT_DRV_LINK_SPEED_10G 0x213103#define NVM_CFG1_PORT_DRV_LINK_SPEED_10G 0x2
13097#define NVM_CFG1_PORT_DRV_LINK_SPEED_20G 0x313104#define NVM_CFG1_PORT_DRV_LINK_SPEED_20G 0x3
13098#define NVM_CFG1_PORT_DRV_LINK_SPEED_25G 0x413105#define NVM_CFG1_PORT_DRV_LINK_SPEED_25G 0x4
13099#define NVM_CFG1_PORT_DRV_LINK_SPEED_40G 0x513106#define NVM_CFG1_PORT_DRV_LINK_SPEED_40G 0x5
13100#define NVM_CFG1_PORT_DRV_LINK_SPEED_50G 0x613107#define NVM_CFG1_PORT_DRV_LINK_SPEED_50G 0x6
drivers/net/ethernet/qlogic/qed/qed_mcp.h+6−6
@@ -16,15 +16,15 @@ · 15 unmodified lines
16#include "qed_dev_api.h"16#include "qed_dev_api.h"
17 17
18struct qed_mcp_link_speed_params {18struct qed_mcp_link_speed_params {
19 bool autoneg;19 bool autoneg;
20 u32 advertised_speeds; /* bitmask of DRV_SPEED_CAPABILITY */20 u32 advertised_speeds;
21 u32 forced_speed; /* In Mb/s */21 u32 forced_speed; /* In Mb/s */
22};22};
23 23
24struct qed_mcp_link_pause_params {24struct qed_mcp_link_pause_params {
25 bool autoneg;25 bool autoneg;
26 bool forced_rx;26 bool forced_rx;
27 bool forced_tx;27 bool forced_tx;
28};28};
29 29
30enum qed_mcp_eee_mode {30enum qed_mcp_eee_mode {

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