History

Merge branch 'net-stmmac-Stop-using-hard-coded-callbacks'

Jose Abreu says: ==================== net: stmmac: Stop using hard-coded callbacks This a starting point for a cleanup and re-organization of stmmac. In this series we stop using hard-coded callbacks along the code and use instead helpers which are defined in a single place ("hwif.h"). This brings several advantages: 1) Less typing :) 2) Guaranteed function pointer check 3) More flexibility By 2) we stop using the repeated pattern of: if (priv->hw->mac->some_func) priv->hw->mac->some_func(...) I didn't check but I expect the final .ko will be bigger with this series because *all* of function pointers are checked. Anyway, I hope this can make the code more readable and more flexible now. ====================

David S. Miller committed 8 years ago

Commit 5da8baa2 parents 309c446 2c520b113 files · +726 −577Browse files

Unified · Split

13 files
  1. drivers/net/ethernet/stmicro/stmmac/chain_mode.c +16 −18
  2. drivers/net/ethernet/stmicro/stmmac/common.h +1 −198
  3. drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.c +2 −2
  4. drivers/net/ethernet/stmicro/stmmac/dwmac5.c +11 −8
  5. drivers/net/ethernet/stmicro/stmmac/dwmac5.h +3 −3
  6. drivers/net/ethernet/stmicro/stmmac/enh_desc.c +2 −2
  7. drivers/net/ethernet/stmicro/stmmac/hwif.h +421 −0
  8. drivers/net/ethernet/stmicro/stmmac/norm_desc.c +2 −2
  9. drivers/net/ethernet/stmicro/stmmac/ring_mode.c +18 −21
  10. drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c +31 −51
  11. drivers/net/ethernet/stmicro/stmmac/stmmac_hwtstamp.c +18 −16
  12. drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +196 −243
  13. drivers/net/ethernet/stmicro/stmmac/stmmac_ptp.c +5 −13
drivers/net/ethernet/stmicro/stmmac/chain_mode.c+16−18
@@ -24,7 +24,7 @@ · 23 unmodified lines
24 24
25#include "stmmac.h"25#include "stmmac.h"
26 26
27static int stmmac_jumbo_frm(void *p, struct sk_buff *skb, int csum)27static int jumbo_frm(void *p, struct sk_buff *skb, int csum)
28{28{
29 struct stmmac_tx_queue *tx_q = (struct stmmac_tx_queue *)p;29 struct stmmac_tx_queue *tx_q = (struct stmmac_tx_queue *)p;
30 unsigned int nopaged_len = skb_headlen(skb);30 unsigned int nopaged_len = skb_headlen(skb);
@@ -51,8 +51,8 @@ static int stmmac_jumbo_frm(void *p, struct sk_buff *skb, int csum) · 20 unmodified lines
51 tx_q->tx_skbuff_dma[entry].buf = des2;51 tx_q->tx_skbuff_dma[entry].buf = des2;
52 tx_q->tx_skbuff_dma[entry].len = bmax;52 tx_q->tx_skbuff_dma[entry].len = bmax;
53 /* do not close the descriptor and do not set own bit */53 /* do not close the descriptor and do not set own bit */
54 priv->hw->desc->prepare_tx_desc(desc, 1, bmax, csum, STMMAC_CHAIN_MODE,54 stmmac_prepare_tx_desc(priv, desc, 1, bmax, csum, STMMAC_CHAIN_MODE,
55 0, false, skb->len);55 0, false, skb->len);
56 56
57 while (len != 0) {57 while (len != 0) {
58 tx_q->tx_skbuff[entry] = NULL;58 tx_q->tx_skbuff[entry] = NULL;
@@ -68,9 +68,8 @@ static int stmmac_jumbo_frm(void *p, struct sk_buff *skb, int csum) · 9 unmodified lines
68 return -1;68 return -1;
69 tx_q->tx_skbuff_dma[entry].buf = des2;69 tx_q->tx_skbuff_dma[entry].buf = des2;
70 tx_q->tx_skbuff_dma[entry].len = bmax;70 tx_q->tx_skbuff_dma[entry].len = bmax;
71 priv->hw->desc->prepare_tx_desc(desc, 0, bmax, csum,71 stmmac_prepare_tx_desc(priv, desc, 0, bmax, csum,
72 STMMAC_CHAIN_MODE, 1,72 STMMAC_CHAIN_MODE, 1, false, skb->len);
73 false, skb->len);
74 len -= bmax;73 len -= bmax;
75 i++;74 i++;
76 } else {75 } else {
@@ -83,9 +82,8 @@ static int stmmac_jumbo_frm(void *p, struct sk_buff *skb, int csum) · 6 unmodified lines
83 tx_q->tx_skbuff_dma[entry].buf = des2;82 tx_q->tx_skbuff_dma[entry].buf = des2;
84 tx_q->tx_skbuff_dma[entry].len = len;83 tx_q->tx_skbuff_dma[entry].len = len;
85 /* last descriptor can be set now */84 /* last descriptor can be set now */
86 priv->hw->desc->prepare_tx_desc(desc, 0, len, csum,85 stmmac_prepare_tx_desc(priv, desc, 0, len, csum,
87 STMMAC_CHAIN_MODE, 1,86 STMMAC_CHAIN_MODE, 1, true, skb->len);
88 true, skb->len);
89 len = 0;87 len = 0;
90 }88 }
91 }89 }
@@ -95,7 +93,7 @@ static int stmmac_jumbo_frm(void *p, struct sk_buff *skb, int csum) · 3 unmodified lines
95 return entry;93 return entry;
96}94}
97 95
98static unsigned int stmmac_is_jumbo_frm(int len, int enh_desc)96static unsigned int is_jumbo_frm(int len, int enh_desc)
99{97{
100 unsigned int ret = 0;98 unsigned int ret = 0;
101 99
@@ -107,7 +105,7 @@ static unsigned int stmmac_is_jumbo_frm(int len, int enh_desc) · 5 unmodified lines
107 return ret;105 return ret;
108}106}
109 107
110static void stmmac_init_dma_chain(void *des, dma_addr_t phy_addr,108static void init_dma_chain(void *des, dma_addr_t phy_addr,
111 unsigned int size, unsigned int extend_desc)109 unsigned int size, unsigned int extend_desc)
112{110{
113 /*111 /*
@@ -137,7 +135,7 @@ static void stmmac_init_dma_chain(void *des, dma_addr_t phy_addr, · 23 unmodified lines
137 }135 }
138}136}
139 137
140static void stmmac_refill_desc3(void *priv_ptr, struct dma_desc *p)138static void refill_desc3(void *priv_ptr, struct dma_desc *p)
141{139{
142 struct stmmac_rx_queue *rx_q = (struct stmmac_rx_queue *)priv_ptr;140 struct stmmac_rx_queue *rx_q = (struct stmmac_rx_queue *)priv_ptr;
143 struct stmmac_priv *priv = rx_q->priv_data;141 struct stmmac_priv *priv = rx_q->priv_data;
@@ -153,7 +151,7 @@ static void stmmac_refill_desc3(void *priv_ptr, struct dma_desc *p) · 9 unmodified lines
153 sizeof(struct dma_desc)));151 sizeof(struct dma_desc)));
154}152}
155 153
156static void stmmac_clean_desc3(void *priv_ptr, struct dma_desc *p)154static void clean_desc3(void *priv_ptr, struct dma_desc *p)
157{155{
158 struct stmmac_tx_queue *tx_q = (struct stmmac_tx_queue *)priv_ptr;156 struct stmmac_tx_queue *tx_q = (struct stmmac_tx_queue *)priv_ptr;
159 struct stmmac_priv *priv = tx_q->priv_data;157 struct stmmac_priv *priv = tx_q->priv_data;
@@ -171,9 +169,9 @@ static void stmmac_clean_desc3(void *priv_ptr, struct dma_desc *p) · 11 unmodified lines
171}169}
172 170
173const struct stmmac_mode_ops chain_mode_ops = {171const struct stmmac_mode_ops chain_mode_ops = {
174 .init = stmmac_init_dma_chain,172 .init = init_dma_chain,
175 .is_jumbo_frm = stmmac_is_jumbo_frm,173 .is_jumbo_frm = is_jumbo_frm,
176 .jumbo_frm = stmmac_jumbo_frm,174 .jumbo_frm = jumbo_frm,
177 .refill_desc3 = stmmac_refill_desc3,175 .refill_desc3 = refill_desc3,
178 .clean_desc3 = stmmac_clean_desc3,176 .clean_desc3 = clean_desc3,
179};177};
drivers/net/ethernet/stmicro/stmmac/common.h+1−198
@@ -32,6 +32,7 @@ · 31 unmodified lines
32#endif32#endif
33 33
34#include "descs.h"34#include "descs.h"
35#include "hwif.h"
35#include "mmc.h"36#include "mmc.h"
36 37
37/* Synopsys Core versions */38/* Synopsys Core versions */
@@ -377,197 +378,11 @@ struct dma_features { · 339 unmodified lines
377 378
378#define JUMBO_LEN 9000379#define JUMBO_LEN 9000
379 380
380/* Descriptors helpers */
381struct stmmac_desc_ops {
382 /* DMA RX descriptor ring initialization */
383 void (*init_rx_desc) (struct dma_desc *p, int disable_rx_ic, int mode,
384 int end);
385 /* DMA TX descriptor ring initialization */
386 void (*init_tx_desc) (struct dma_desc *p, int mode, int end);
387
388 /* Invoked by the xmit function to prepare the tx descriptor */
389 void (*prepare_tx_desc) (struct dma_desc *p, int is_fs, int len,
390 bool csum_flag, int mode, bool tx_own,
391 bool ls, unsigned int tot_pkt_len);
392 void (*prepare_tso_tx_desc)(struct dma_desc *p, int is_fs, int len1,
393 int len2, bool tx_own, bool ls,
394 unsigned int tcphdrlen,
395 unsigned int tcppayloadlen);
396 /* Set/get the owner of the descriptor */
397 void (*set_tx_owner) (struct dma_desc *p);
398 int (*get_tx_owner) (struct dma_desc *p);
399 /* Clean the tx descriptor as soon as the tx irq is received */
400 void (*release_tx_desc) (struct dma_desc *p, int mode);
401 /* Clear interrupt on tx frame completion. When this bit is
402 * set an interrupt happens as soon as the frame is transmitted */
403 void (*set_tx_ic)(struct dma_desc *p);
404 /* Last tx segment reports the transmit status */
405 int (*get_tx_ls) (struct dma_desc *p);
406 /* Return the transmit status looking at the TDES1 */
407 int (*tx_status) (void *data, struct stmmac_extra_stats *x,
408 struct dma_desc *p, void __iomem *ioaddr);
409 /* Get the buffer size from the descriptor */
410 int (*get_tx_len) (struct dma_desc *p);
411 /* Handle extra events on specific interrupts hw dependent */
412 void (*set_rx_owner) (struct dma_desc *p);
413 /* Get the receive frame size */
414 int (*get_rx_frame_len) (struct dma_desc *p, int rx_coe_type);
415 /* Return the reception status looking at the RDES1 */
416 int (*rx_status) (void *data, struct stmmac_extra_stats *x,
417 struct dma_desc *p);
418 void (*rx_extended_status) (void *data, struct stmmac_extra_stats *x,
419 struct dma_extended_desc *p);
420 /* Set tx timestamp enable bit */
421 void (*enable_tx_timestamp) (struct dma_desc *p);
422 /* get tx timestamp status */
423 int (*get_tx_timestamp_status) (struct dma_desc *p);
424 /* get timestamp value */
425 u64(*get_timestamp) (void *desc, u32 ats);
426 /* get rx timestamp status */
427 int (*get_rx_timestamp_status)(void *desc, void *next_desc, u32 ats);
428 /* Display ring */
429 void (*display_ring)(void *head, unsigned int size, bool rx);
430 /* set MSS via context descriptor */
431 void (*set_mss)(struct dma_desc *p, unsigned int mss);
432};
433
434extern const struct stmmac_desc_ops enh_desc_ops;381extern const struct stmmac_desc_ops enh_desc_ops;
435extern const struct stmmac_desc_ops ndesc_ops;382extern const struct stmmac_desc_ops ndesc_ops;
436 383
437/* Specific DMA helpers */
438struct stmmac_dma_ops {
439 /* DMA core initialization */
440 int (*reset)(void __iomem *ioaddr);
441 void (*init)(void __iomem *ioaddr, struct stmmac_dma_cfg *dma_cfg,
442 u32 dma_tx, u32 dma_rx, int atds);
443 void (*init_chan)(void __iomem *ioaddr,
444 struct stmmac_dma_cfg *dma_cfg, u32 chan);
445 void (*init_rx_chan)(void __iomem *ioaddr,
446 struct stmmac_dma_cfg *dma_cfg,
447 u32 dma_rx_phy, u32 chan);
448 void (*init_tx_chan)(void __iomem *ioaddr,
449 struct stmmac_dma_cfg *dma_cfg,
450 u32 dma_tx_phy, u32 chan);
451 /* Configure the AXI Bus Mode Register */
452 void (*axi)(void __iomem *ioaddr, struct stmmac_axi *axi);
453 /* Dump DMA registers */
454 void (*dump_regs)(void __iomem *ioaddr, u32 *reg_space);
455 /* Set tx/rx threshold in the csr6 register
456 * An invalid value enables the store-and-forward mode */
457 void (*dma_mode)(void __iomem *ioaddr, int txmode, int rxmode,
458 int rxfifosz);
459 void (*dma_rx_mode)(void __iomem *ioaddr, int mode, u32 channel,
460 int fifosz, u8 qmode);
461 void (*dma_tx_mode)(void __iomem *ioaddr, int mode, u32 channel,
462 int fifosz, u8 qmode);
463 /* To track extra statistic (if supported) */
464 void (*dma_diagnostic_fr) (void *data, struct stmmac_extra_stats *x,
465 void __iomem *ioaddr);
466 void (*enable_dma_transmission) (void __iomem *ioaddr);
467 void (*enable_dma_irq)(void __iomem *ioaddr, u32 chan);
468 void (*disable_dma_irq)(void __iomem *ioaddr, u32 chan);
469 void (*start_tx)(void __iomem *ioaddr, u32 chan);
470 void (*stop_tx)(void __iomem *ioaddr, u32 chan);
471 void (*start_rx)(void __iomem *ioaddr, u32 chan);
472 void (*stop_rx)(void __iomem *ioaddr, u32 chan);
473 int (*dma_interrupt) (void __iomem *ioaddr,
474 struct stmmac_extra_stats *x, u32 chan);
475 /* If supported then get the optional core features */
476 void (*get_hw_feature)(void __iomem *ioaddr,
477 struct dma_features *dma_cap);
478 /* Program the HW RX Watchdog */
479 void (*rx_watchdog)(void __iomem *ioaddr, u32 riwt, u32 number_chan);
480 void (*set_tx_ring_len)(void __iomem *ioaddr, u32 len, u32 chan);
481 void (*set_rx_ring_len)(void __iomem *ioaddr, u32 len, u32 chan);
482 void (*set_rx_tail_ptr)(void __iomem *ioaddr, u32 tail_ptr, u32 chan);
483 void (*set_tx_tail_ptr)(void __iomem *ioaddr, u32 tail_ptr, u32 chan);
484 void (*enable_tso)(void __iomem *ioaddr, bool en, u32 chan);
485};
486
487struct mac_device_info;384struct mac_device_info;
488 385
489/* Helpers to program the MAC core */
490struct stmmac_ops {
491 /* MAC core initialization */
492 void (*core_init)(struct mac_device_info *hw, struct net_device *dev);
493 /* Enable the MAC RX/TX */
494 void (*set_mac)(void __iomem *ioaddr, bool enable);
495 /* Enable and verify that the IPC module is supported */
496 int (*rx_ipc)(struct mac_device_info *hw);
497 /* Enable RX Queues */
498 void (*rx_queue_enable)(struct mac_device_info *hw, u8 mode, u32 queue);
499 /* RX Queues Priority */
500 void (*rx_queue_prio)(struct mac_device_info *hw, u32 prio, u32 queue);
501 /* TX Queues Priority */
502 void (*tx_queue_prio)(struct mac_device_info *hw, u32 prio, u32 queue);
503 /* RX Queues Routing */
504 void (*rx_queue_routing)(struct mac_device_info *hw, u8 packet,
505 u32 queue);
506 /* Program RX Algorithms */
507 void (*prog_mtl_rx_algorithms)(struct mac_device_info *hw, u32 rx_alg);
508 /* Program TX Algorithms */
509 void (*prog_mtl_tx_algorithms)(struct mac_device_info *hw, u32 tx_alg);
510 /* Set MTL TX queues weight */
511 void (*set_mtl_tx_queue_weight)(struct mac_device_info *hw,
512 u32 weight, u32 queue);
513 /* RX MTL queue to RX dma mapping */
514 void (*map_mtl_to_dma)(struct mac_device_info *hw, u32 queue, u32 chan);
515 /* Configure AV Algorithm */
516 void (*config_cbs)(struct mac_device_info *hw, u32 send_slope,
517 u32 idle_slope, u32 high_credit, u32 low_credit,
518 u32 queue);
519 /* Dump MAC registers */
520 void (*dump_regs)(struct mac_device_info *hw, u32 *reg_space);
521 /* Handle extra events on specific interrupts hw dependent */
522 int (*host_irq_status)(struct mac_device_info *hw,
523 struct stmmac_extra_stats *x);
524 /* Handle MTL interrupts */
525 int (*host_mtl_irq_status)(struct mac_device_info *hw, u32 chan);
526 /* Multicast filter setting */
527 void (*set_filter)(struct mac_device_info *hw, struct net_device *dev);
528 /* Flow control setting */
529 void (*flow_ctrl)(struct mac_device_info *hw, unsigned int duplex,
530 unsigned int fc, unsigned int pause_time, u32 tx_cnt);
531 /* Set power management mode (e.g. magic frame) */
532 void (*pmt)(struct mac_device_info *hw, unsigned long mode);
533 /* Set/Get Unicast MAC addresses */
534 void (*set_umac_addr)(struct mac_device_info *hw, unsigned char *addr,
535 unsigned int reg_n);
536 void (*get_umac_addr)(struct mac_device_info *hw, unsigned char *addr,
537 unsigned int reg_n);
538 void (*set_eee_mode)(struct mac_device_info *hw,
539 bool en_tx_lpi_clockgating);
540 void (*reset_eee_mode)(struct mac_device_info *hw);
541 void (*set_eee_timer)(struct mac_device_info *hw, int ls, int tw);
542 void (*set_eee_pls)(struct mac_device_info *hw, int link);
543 void (*debug)(void __iomem *ioaddr, struct stmmac_extra_stats *x,
544 u32 rx_queues, u32 tx_queues);
545 /* PCS calls */
546 void (*pcs_ctrl_ane)(void __iomem *ioaddr, bool ane, bool srgmi_ral,
547 bool loopback);
548 void (*pcs_rane)(void __iomem *ioaddr, bool restart);
549 void (*pcs_get_adv_lp)(void __iomem *ioaddr, struct rgmii_adv *adv);
550 /* Safety Features */
551 int (*safety_feat_config)(void __iomem *ioaddr, unsigned int asp);
552 bool (*safety_feat_irq_status)(struct net_device *ndev,
553 void __iomem *ioaddr, unsigned int asp,
554 struct stmmac_safety_stats *stats);
555 const char *(*safety_feat_dump)(struct stmmac_safety_stats *stats,
556 int index, unsigned long *count);
557};
558
559/* PTP and HW Timer helpers */
560struct stmmac_hwtimestamp {
561 void (*config_hw_tstamping) (void __iomem *ioaddr, u32 data);
562 u32 (*config_sub_second_increment)(void __iomem *ioaddr, u32 ptp_clock,
563 int gmac4);
564 int (*init_systime) (void __iomem *ioaddr, u32 sec, u32 nsec);
565 int (*config_addend) (void __iomem *ioaddr, u32 addend);
566 int (*adjust_systime) (void __iomem *ioaddr, u32 sec, u32 nsec,
567 int add_sub, int gmac4);
568 u64(*get_systime) (void __iomem *ioaddr);
569};
570
571extern const struct stmmac_hwtimestamp stmmac_ptp;386extern const struct stmmac_hwtimestamp stmmac_ptp;
572extern const struct stmmac_mode_ops dwmac4_ring_mode_ops;387extern const struct stmmac_mode_ops dwmac4_ring_mode_ops;
573 388
@@ -590,18 +405,6 @@ struct mii_regs { · 16 unmodified lines
590 unsigned int clk_csr_mask;405 unsigned int clk_csr_mask;
591};406};
592 407
593/* Helpers to manage the descriptors for chain and ring modes */
594struct stmmac_mode_ops {
595 void (*init) (void *des, dma_addr_t phy_addr, unsigned int size,
596 unsigned int extend_desc);
597 unsigned int (*is_jumbo_frm) (int len, int ehn_desc);
598 int (*jumbo_frm)(void *priv, struct sk_buff *skb, int csum);
599 int (*set_16kib_bfsize)(int mtu);
600 void (*init_desc3)(struct dma_desc *p);
601 void (*refill_desc3) (void *priv, struct dma_desc *p);
602 void (*clean_desc3) (void *priv, struct dma_desc *p);
603};
604
605struct mac_device_info {408struct mac_device_info {
606 const struct stmmac_ops *mac;409 const struct stmmac_ops *mac;
607 const struct stmmac_desc_ops *desc;410 const struct stmmac_desc_ops *desc;
drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.c+2−2
@@ -223,7 +223,7 @@ static int dwmac4_wrback_get_tx_timestamp_status(struct dma_desc *p) · 222 unmodified lines
223 return 0;223 return 0;
224}224}
225 225
226static inline u64 dwmac4_get_timestamp(void *desc, u32 ats)226static inline void dwmac4_get_timestamp(void *desc, u32 ats, u64 *ts)
227{227{
228 struct dma_desc *p = (struct dma_desc *)desc;228 struct dma_desc *p = (struct dma_desc *)desc;
229 u64 ns;229 u64 ns;
@@ -232,7 +232,7 @@ static inline u64 dwmac4_get_timestamp(void *desc, u32 ats) · 2 unmodified lines
232 /* convert high/sec time stamp value to nanosecond */232 /* convert high/sec time stamp value to nanosecond */
233 ns += le32_to_cpu(p->des1) * 1000000000ULL;233 ns += le32_to_cpu(p->des1) * 1000000000ULL;
234 234
235 return ns;235 *ts = ns;
236}236}
237 237
238static int dwmac4_rx_check_timestamp(void *desc)238static int dwmac4_rx_check_timestamp(void *desc)
drivers/net/ethernet/stmicro/stmmac/dwmac5.c+11−8
@@ -237,15 +237,16 @@ int dwmac5_safety_feat_config(void __iomem *ioaddr, unsigned int asp) · 236 unmodified lines
237 return 0;237 return 0;
238}238}
239 239
240bool dwmac5_safety_feat_irq_status(struct net_device *ndev,240int dwmac5_safety_feat_irq_status(struct net_device *ndev,
241 void __iomem *ioaddr, unsigned int asp,241 void __iomem *ioaddr, unsigned int asp,
242 struct stmmac_safety_stats *stats)242 struct stmmac_safety_stats *stats)
243{243{
244 bool ret = false, err, corr;244 bool err, corr;
245 u32 mtl, dma;245 u32 mtl, dma;
246 int ret = 0;
246 247
247 if (!asp)248 if (!asp)
248 return false;249 return -EINVAL;
249 250
250 mtl = readl(ioaddr + MTL_SAFETY_INT_STATUS);251 mtl = readl(ioaddr + MTL_SAFETY_INT_STATUS);
251 dma = readl(ioaddr + DMA_SAFETY_INT_STATUS);252 dma = readl(ioaddr + DMA_SAFETY_INT_STATUS);
@@ -282,17 +283,19 @@ static const struct dwmac5_error { · 30 unmodified lines
282 { dwmac5_dma_errors },283 { dwmac5_dma_errors },
283};284};
284 285
285const char *dwmac5_safety_feat_dump(struct stmmac_safety_stats *stats,286int dwmac5_safety_feat_dump(struct stmmac_safety_stats *stats,
286 int index, unsigned long *count)287 int index, unsigned long *count, const char **desc)
287{288{
288 int module = index / 32, offset = index % 32;289 int module = index / 32, offset = index % 32;
289 unsigned long *ptr = (unsigned long *)stats;290 unsigned long *ptr = (unsigned long *)stats;
290 291
291 if (module >= ARRAY_SIZE(dwmac5_all_errors))292 if (module >= ARRAY_SIZE(dwmac5_all_errors))
292 return NULL;293 return -EINVAL;
293 if (!dwmac5_all_errors[module].desc[offset].valid)294 if (!dwmac5_all_errors[module].desc[offset].valid)
294 return NULL;295 return -EINVAL;
295 if (count)296 if (count)
296 *count = *(ptr + index);297 *count = *(ptr + index);
297 return dwmac5_all_errors[module].desc[offset].desc;298 if (desc)
299 *desc = dwmac5_all_errors[module].desc[offset].desc;
300 return 0;
298}301}
drivers/net/ethernet/stmicro/stmmac/dwmac5.h+3−3
@@ -43,10 +43,10 @@ · 42 unmodified lines
43#define DMA_ECC_INT_STATUS 0x0000108843#define DMA_ECC_INT_STATUS 0x00001088
44 44
45int dwmac5_safety_feat_config(void __iomem *ioaddr, unsigned int asp);45int dwmac5_safety_feat_config(void __iomem *ioaddr, unsigned int asp);
46bool dwmac5_safety_feat_irq_status(struct net_device *ndev,46int dwmac5_safety_feat_irq_status(struct net_device *ndev,
47 void __iomem *ioaddr, unsigned int asp,47 void __iomem *ioaddr, unsigned int asp,
48 struct stmmac_safety_stats *stats);48 struct stmmac_safety_stats *stats);
49const char *dwmac5_safety_feat_dump(struct stmmac_safety_stats *stats,49int dwmac5_safety_feat_dump(struct stmmac_safety_stats *stats,
50 int index, unsigned long *count);50 int index, unsigned long *count, const char **desc);
51 51
52#endif /* __DWMAC5_H__ */52#endif /* __DWMAC5_H__ */
drivers/net/ethernet/stmicro/stmmac/enh_desc.c+2−2
@@ -382,7 +382,7 @@ static int enh_desc_get_tx_timestamp_status(struct dma_desc *p) · 381 unmodified lines
382 return (le32_to_cpu(p->des0) & ETDES0_TIME_STAMP_STATUS) >> 17;382 return (le32_to_cpu(p->des0) & ETDES0_TIME_STAMP_STATUS) >> 17;
383}383}
384 384
385static u64 enh_desc_get_timestamp(void *desc, u32 ats)385static void enh_desc_get_timestamp(void *desc, u32 ats, u64 *ts)
386{386{
387 u64 ns;387 u64 ns;
388 388
@@ -397,7 +397,7 @@ static u64 enh_desc_get_timestamp(void *desc, u32 ats) · 8 unmodified lines
397 ns += le32_to_cpu(p->des3) * 1000000000ULL;397 ns += le32_to_cpu(p->des3) * 1000000000ULL;
398 }398 }
399 399
400 return ns;400 *ts = ns;
401}401}
402 402
403static int enh_desc_get_rx_timestamp_status(void *desc, void *next_desc,403static int enh_desc_get_rx_timestamp_status(void *desc, void *next_desc,
drivers/net/ethernet/stmicro/stmmac/hwif.h+421−0
@@ -0,0 +1,421 @@
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2// Copyright (c) 2018 Synopsys, Inc. and/or its affiliates.
3// stmmac HW Interface Callbacks
4
5#ifndef __STMMAC_HWIF_H__
6#define __STMMAC_HWIF_H__
7
8#define stmmac_do_void_callback(__priv, __module, __cname, __arg0, __args...) \
9({ \
10 int __result = -EINVAL; \
11 if ((__priv)->hw->__module->__cname) { \
12 (__priv)->hw->__module->__cname((__arg0), ##__args); \
13 __result = 0; \
14 } \
15 __result; \
16})
17#define stmmac_do_callback(__priv, __module, __cname, __arg0, __args...) \
18({ \
19 int __result = -EINVAL; \
20 if ((__priv)->hw->__module->__cname) \
21 __result = (__priv)->hw->__module->__cname((__arg0), ##__args); \
22 __result; \
23})
24
25struct stmmac_extra_stats;
26struct stmmac_safety_stats;
27struct dma_desc;
28struct dma_extended_desc;
29
30/* Descriptors helpers */
31struct stmmac_desc_ops {
32 /* DMA RX descriptor ring initialization */
33 void (*init_rx_desc)(struct dma_desc *p, int disable_rx_ic, int mode,
34 int end);
35 /* DMA TX descriptor ring initialization */
36 void (*init_tx_desc)(struct dma_desc *p, int mode, int end);
37 /* Invoked by the xmit function to prepare the tx descriptor */
38 void (*prepare_tx_desc)(struct dma_desc *p, int is_fs, int len,
39 bool csum_flag, int mode, bool tx_own, bool ls,
40 unsigned int tot_pkt_len);
41 void (*prepare_tso_tx_desc)(struct dma_desc *p, int is_fs, int len1,
42 int len2, bool tx_own, bool ls, unsigned int tcphdrlen,
43 unsigned int tcppayloadlen);
44 /* Set/get the owner of the descriptor */
45 void (*set_tx_owner)(struct dma_desc *p);
46 int (*get_tx_owner)(struct dma_desc *p);
47 /* Clean the tx descriptor as soon as the tx irq is received */
48 void (*release_tx_desc)(struct dma_desc *p, int mode);
49 /* Clear interrupt on tx frame completion. When this bit is
50 * set an interrupt happens as soon as the frame is transmitted */
51 void (*set_tx_ic)(struct dma_desc *p);
52 /* Last tx segment reports the transmit status */
53 int (*get_tx_ls)(struct dma_desc *p);
54 /* Return the transmit status looking at the TDES1 */
55 int (*tx_status)(void *data, struct stmmac_extra_stats *x,
56 struct dma_desc *p, void __iomem *ioaddr);
57 /* Get the buffer size from the descriptor */
58 int (*get_tx_len)(struct dma_desc *p);
59 /* Handle extra events on specific interrupts hw dependent */
60 void (*set_rx_owner)(struct dma_desc *p);
61 /* Get the receive frame size */
62 int (*get_rx_frame_len)(struct dma_desc *p, int rx_coe_type);
63 /* Return the reception status looking at the RDES1 */
64 int (*rx_status)(void *data, struct stmmac_extra_stats *x,
65 struct dma_desc *p);
66 void (*rx_extended_status)(void *data, struct stmmac_extra_stats *x,
67 struct dma_extended_desc *p);
68 /* Set tx timestamp enable bit */
69 void (*enable_tx_timestamp) (struct dma_desc *p);
70 /* get tx timestamp status */
71 int (*get_tx_timestamp_status) (struct dma_desc *p);
72 /* get timestamp value */
73 void (*get_timestamp)(void *desc, u32 ats, u64 *ts);
74 /* get rx timestamp status */
75 int (*get_rx_timestamp_status)(void *desc, void *next_desc, u32 ats);
76 /* Display ring */
77 void (*display_ring)(void *head, unsigned int size, bool rx);
78 /* set MSS via context descriptor */
79 void (*set_mss)(struct dma_desc *p, unsigned int mss);
80};
81
82#define stmmac_init_rx_desc(__priv, __args...) \
83 stmmac_do_void_callback(__priv, desc, init_rx_desc, __args)
84#define stmmac_init_tx_desc(__priv, __args...) \
85 stmmac_do_void_callback(__priv, desc, init_tx_desc, __args)
86#define stmmac_prepare_tx_desc(__priv, __args...) \
87 stmmac_do_void_callback(__priv, desc, prepare_tx_desc, __args)
88#define stmmac_prepare_tso_tx_desc(__priv, __args...) \
89 stmmac_do_void_callback(__priv, desc, prepare_tso_tx_desc, __args)
90#define stmmac_set_tx_owner(__priv, __args...) \
91 stmmac_do_void_callback(__priv, desc, set_tx_owner, __args)
92#define stmmac_get_tx_owner(__priv, __args...) \
93 stmmac_do_callback(__priv, desc, get_tx_owner, __args)
94#define stmmac_release_tx_desc(__priv, __args...) \
95 stmmac_do_void_callback(__priv, desc, release_tx_desc, __args)
96#define stmmac_set_tx_ic(__priv, __args...) \
97 stmmac_do_void_callback(__priv, desc, set_tx_ic, __args)
98#define stmmac_get_tx_ls(__priv, __args...) \
99 stmmac_do_callback(__priv, desc, get_tx_ls, __args)
100#define stmmac_tx_status(__priv, __args...) \
101 stmmac_do_callback(__priv, desc, tx_status, __args)
102#define stmmac_get_tx_len(__priv, __args...) \
103 stmmac_do_callback(__priv, desc, get_tx_len, __args)
104#define stmmac_set_rx_owner(__priv, __args...) \
105 stmmac_do_void_callback(__priv, desc, set_rx_owner, __args)
106#define stmmac_get_rx_frame_len(__priv, __args...) \
107 stmmac_do_callback(__priv, desc, get_rx_frame_len, __args)
108#define stmmac_rx_status(__priv, __args...) \
109 stmmac_do_callback(__priv, desc, rx_status, __args)
110#define stmmac_rx_extended_status(__priv, __args...) \
111 stmmac_do_void_callback(__priv, desc, rx_extended_status, __args)
112#define stmmac_enable_tx_timestamp(__priv, __args...) \
113 stmmac_do_void_callback(__priv, desc, enable_tx_timestamp, __args)
114#define stmmac_get_tx_timestamp_status(__priv, __args...) \
115 stmmac_do_callback(__priv, desc, get_tx_timestamp_status, __args)
116#define stmmac_get_timestamp(__priv, __args...) \
117 stmmac_do_void_callback(__priv, desc, get_timestamp, __args)
118#define stmmac_get_rx_timestamp_status(__priv, __args...) \
119 stmmac_do_callback(__priv, desc, get_rx_timestamp_status, __args)
120#define stmmac_display_ring(__priv, __args...) \
121 stmmac_do_void_callback(__priv, desc, display_ring, __args)
122#define stmmac_set_mss(__priv, __args...) \
123 stmmac_do_void_callback(__priv, desc, set_mss, __args)
124
125struct stmmac_dma_cfg;
126struct dma_features;
127
128/* Specific DMA helpers */
129struct stmmac_dma_ops {
130 /* DMA core initialization */
131 int (*reset)(void __iomem *ioaddr);
132 void (*init)(void __iomem *ioaddr, struct stmmac_dma_cfg *dma_cfg,
133 u32 dma_tx, u32 dma_rx, int atds);
134 void (*init_chan)(void __iomem *ioaddr,
135 struct stmmac_dma_cfg *dma_cfg, u32 chan);
136 void (*init_rx_chan)(void __iomem *ioaddr,
137 struct stmmac_dma_cfg *dma_cfg,
138 u32 dma_rx_phy, u32 chan);
139 void (*init_tx_chan)(void __iomem *ioaddr,
140 struct stmmac_dma_cfg *dma_cfg,
141 u32 dma_tx_phy, u32 chan);
142 /* Configure the AXI Bus Mode Register */
143 void (*axi)(void __iomem *ioaddr, struct stmmac_axi *axi);
144 /* Dump DMA registers */
145 void (*dump_regs)(void __iomem *ioaddr, u32 *reg_space);
146 /* Set tx/rx threshold in the csr6 register
147 * An invalid value enables the store-and-forward mode */
148 void (*dma_mode)(void __iomem *ioaddr, int txmode, int rxmode,
149 int rxfifosz);
150 void (*dma_rx_mode)(void __iomem *ioaddr, int mode, u32 channel,
151 int fifosz, u8 qmode);
152 void (*dma_tx_mode)(void __iomem *ioaddr, int mode, u32 channel,
153 int fifosz, u8 qmode);
154 /* To track extra statistic (if supported) */
155 void (*dma_diagnostic_fr) (void *data, struct stmmac_extra_stats *x,
156 void __iomem *ioaddr);
157 void (*enable_dma_transmission) (void __iomem *ioaddr);
158 void (*enable_dma_irq)(void __iomem *ioaddr, u32 chan);
159 void (*disable_dma_irq)(void __iomem *ioaddr, u32 chan);
160 void (*start_tx)(void __iomem *ioaddr, u32 chan);
161 void (*stop_tx)(void __iomem *ioaddr, u32 chan);
162 void (*start_rx)(void __iomem *ioaddr, u32 chan);
163 void (*stop_rx)(void __iomem *ioaddr, u32 chan);
164 int (*dma_interrupt) (void __iomem *ioaddr,
165 struct stmmac_extra_stats *x, u32 chan);
166 /* If supported then get the optional core features */
167 void (*get_hw_feature)(void __iomem *ioaddr,
168 struct dma_features *dma_cap);
169 /* Program the HW RX Watchdog */
170 void (*rx_watchdog)(void __iomem *ioaddr, u32 riwt, u32 number_chan);
171 void (*set_tx_ring_len)(void __iomem *ioaddr, u32 len, u32 chan);
172 void (*set_rx_ring_len)(void __iomem *ioaddr, u32 len, u32 chan);
173 void (*set_rx_tail_ptr)(void __iomem *ioaddr, u32 tail_ptr, u32 chan);
174 void (*set_tx_tail_ptr)(void __iomem *ioaddr, u32 tail_ptr, u32 chan);
175 void (*enable_tso)(void __iomem *ioaddr, bool en, u32 chan);
176};
177
178#define stmmac_reset(__priv, __args...) \
179 stmmac_do_callback(__priv, dma, reset, __args)
180#define stmmac_dma_init(__priv, __args...) \
181 stmmac_do_void_callback(__priv, dma, init, __args)
182#define stmmac_init_chan(__priv, __args...) \
183 stmmac_do_void_callback(__priv, dma, init_chan, __args)
184#define stmmac_init_rx_chan(__priv, __args...) \
185 stmmac_do_void_callback(__priv, dma, init_rx_chan, __args)
186#define stmmac_init_tx_chan(__priv, __args...) \
187 stmmac_do_void_callback(__priv, dma, init_tx_chan, __args)
188#define stmmac_axi(__priv, __args...) \
189 stmmac_do_void_callback(__priv, dma, axi, __args)
190#define stmmac_dump_dma_regs(__priv, __args...) \
191 stmmac_do_void_callback(__priv, dma, dump_regs, __args)
192#define stmmac_dma_mode(__priv, __args...) \
193 stmmac_do_void_callback(__priv, dma, dma_mode, __args)
194#define stmmac_dma_rx_mode(__priv, __args...) \
195 stmmac_do_void_callback(__priv, dma, dma_rx_mode, __args)
196#define stmmac_dma_tx_mode(__priv, __args...) \
197 stmmac_do_void_callback(__priv, dma, dma_tx_mode, __args)
198#define stmmac_dma_diagnostic_fr(__priv, __args...) \
199 stmmac_do_void_callback(__priv, dma, dma_diagnostic_fr, __args)
200#define stmmac_enable_dma_transmission(__priv, __args...) \
201 stmmac_do_void_callback(__priv, dma, enable_dma_transmission, __args)
202#define stmmac_enable_dma_irq(__priv, __args...) \
203 stmmac_do_void_callback(__priv, dma, enable_dma_irq, __args)
204#define stmmac_disable_dma_irq(__priv, __args...) \
205 stmmac_do_void_callback(__priv, dma, disable_dma_irq, __args)
206#define stmmac_start_tx(__priv, __args...) \
207 stmmac_do_void_callback(__priv, dma, start_tx, __args)
208#define stmmac_stop_tx(__priv, __args...) \
209 stmmac_do_void_callback(__priv, dma, stop_tx, __args)
210#define stmmac_start_rx(__priv, __args...) \
211 stmmac_do_void_callback(__priv, dma, start_rx, __args)
212#define stmmac_stop_rx(__priv, __args...) \
213 stmmac_do_void_callback(__priv, dma, stop_rx, __args)
214#define stmmac_dma_interrupt_status(__priv, __args...) \
215 stmmac_do_callback(__priv, dma, dma_interrupt, __args)
216#define stmmac_get_hw_feature(__priv, __args...) \
217 stmmac_do_void_callback(__priv, dma, get_hw_feature, __args)
218#define stmmac_rx_watchdog(__priv, __args...) \
219 stmmac_do_void_callback(__priv, dma, rx_watchdog, __args)
220#define stmmac_set_tx_ring_len(__priv, __args...) \
221 stmmac_do_void_callback(__priv, dma, set_tx_ring_len, __args)
222#define stmmac_set_rx_ring_len(__priv, __args...) \
223 stmmac_do_void_callback(__priv, dma, set_rx_ring_len, __args)
224#define stmmac_set_rx_tail_ptr(__priv, __args...) \
225 stmmac_do_void_callback(__priv, dma, set_rx_tail_ptr, __args)
226#define stmmac_set_tx_tail_ptr(__priv, __args...) \
227 stmmac_do_void_callback(__priv, dma, set_tx_tail_ptr, __args)
228#define stmmac_enable_tso(__priv, __args...) \
229 stmmac_do_void_callback(__priv, dma, enable_tso, __args)
230
231struct mac_device_info;
232struct net_device;
233struct rgmii_adv;
234struct stmmac_safety_stats;
235
236/* Helpers to program the MAC core */
237struct stmmac_ops {
238 /* MAC core initialization */
239 void (*core_init)(struct mac_device_info *hw, struct net_device *dev);
240 /* Enable the MAC RX/TX */
241 void (*set_mac)(void __iomem *ioaddr, bool enable);
242 /* Enable and verify that the IPC module is supported */
243 int (*rx_ipc)(struct mac_device_info *hw);
244 /* Enable RX Queues */
245 void (*rx_queue_enable)(struct mac_device_info *hw, u8 mode, u32 queue);
246 /* RX Queues Priority */
247 void (*rx_queue_prio)(struct mac_device_info *hw, u32 prio, u32 queue);
248 /* TX Queues Priority */
249 void (*tx_queue_prio)(struct mac_device_info *hw, u32 prio, u32 queue);
250 /* RX Queues Routing */
251 void (*rx_queue_routing)(struct mac_device_info *hw, u8 packet,
252 u32 queue);
253 /* Program RX Algorithms */
254 void (*prog_mtl_rx_algorithms)(struct mac_device_info *hw, u32 rx_alg);
255 /* Program TX Algorithms */
256 void (*prog_mtl_tx_algorithms)(struct mac_device_info *hw, u32 tx_alg);
257 /* Set MTL TX queues weight */
258 void (*set_mtl_tx_queue_weight)(struct mac_device_info *hw,
259 u32 weight, u32 queue);
260 /* RX MTL queue to RX dma mapping */
261 void (*map_mtl_to_dma)(struct mac_device_info *hw, u32 queue, u32 chan);
262 /* Configure AV Algorithm */
263 void (*config_cbs)(struct mac_device_info *hw, u32 send_slope,
264 u32 idle_slope, u32 high_credit, u32 low_credit,
265 u32 queue);
266 /* Dump MAC registers */
267 void (*dump_regs)(struct mac_device_info *hw, u32 *reg_space);
268 /* Handle extra events on specific interrupts hw dependent */
269 int (*host_irq_status)(struct mac_device_info *hw,
270 struct stmmac_extra_stats *x);
271 /* Handle MTL interrupts */
272 int (*host_mtl_irq_status)(struct mac_device_info *hw, u32 chan);
273 /* Multicast filter setting */
274 void (*set_filter)(struct mac_device_info *hw, struct net_device *dev);
275 /* Flow control setting */
276 void (*flow_ctrl)(struct mac_device_info *hw, unsigned int duplex,
277 unsigned int fc, unsigned int pause_time, u32 tx_cnt);
278 /* Set power management mode (e.g. magic frame) */
279 void (*pmt)(struct mac_device_info *hw, unsigned long mode);
280 /* Set/Get Unicast MAC addresses */
281 void (*set_umac_addr)(struct mac_device_info *hw, unsigned char *addr,
282 unsigned int reg_n);
283 void (*get_umac_addr)(struct mac_device_info *hw, unsigned char *addr,
284 unsigned int reg_n);
285 void (*set_eee_mode)(struct mac_device_info *hw,
286 bool en_tx_lpi_clockgating);
287 void (*reset_eee_mode)(struct mac_device_info *hw);
288 void (*set_eee_timer)(struct mac_device_info *hw, int ls, int tw);
289 void (*set_eee_pls)(struct mac_device_info *hw, int link);
290 void (*debug)(void __iomem *ioaddr, struct stmmac_extra_stats *x,
291 u32 rx_queues, u32 tx_queues);
292 /* PCS calls */
293 void (*pcs_ctrl_ane)(void __iomem *ioaddr, bool ane, bool srgmi_ral,
294 bool loopback);
295 void (*pcs_rane)(void __iomem *ioaddr, bool restart);
296 void (*pcs_get_adv_lp)(void __iomem *ioaddr, struct rgmii_adv *adv);
297 /* Safety Features */
298 int (*safety_feat_config)(void __iomem *ioaddr, unsigned int asp);
299 int (*safety_feat_irq_status)(struct net_device *ndev,
300 void __iomem *ioaddr, unsigned int asp,
301 struct stmmac_safety_stats *stats);
302 int (*safety_feat_dump)(struct stmmac_safety_stats *stats,
303 int index, unsigned long *count, const char **desc);
304};
305
306#define stmmac_core_init(__priv, __args...) \
307 stmmac_do_void_callback(__priv, mac, core_init, __args)
308#define stmmac_mac_set(__priv, __args...) \
309 stmmac_do_void_callback(__priv, mac, set_mac, __args)
310#define stmmac_rx_ipc(__priv, __args...) \
311 stmmac_do_callback(__priv, mac, rx_ipc, __args)
312#define stmmac_rx_queue_enable(__priv, __args...) \
313 stmmac_do_void_callback(__priv, mac, rx_queue_enable, __args)
314#define stmmac_rx_queue_prio(__priv, __args...) \
315 stmmac_do_void_callback(__priv, mac, rx_queue_prio, __args)
316#define stmmac_tx_queue_prio(__priv, __args...) \
317 stmmac_do_void_callback(__priv, mac, tx_queue_prio, __args)
318#define stmmac_rx_queue_routing(__priv, __args...) \
319 stmmac_do_void_callback(__priv, mac, rx_queue_routing, __args)
320#define stmmac_prog_mtl_rx_algorithms(__priv, __args...) \
321 stmmac_do_void_callback(__priv, mac, prog_mtl_rx_algorithms, __args)
322#define stmmac_prog_mtl_tx_algorithms(__priv, __args...) \
323 stmmac_do_void_callback(__priv, mac, prog_mtl_tx_algorithms, __args)
324#define stmmac_set_mtl_tx_queue_weight(__priv, __args...) \
325 stmmac_do_void_callback(__priv, mac, set_mtl_tx_queue_weight, __args)
326#define stmmac_map_mtl_to_dma(__priv, __args...) \
327 stmmac_do_void_callback(__priv, mac, map_mtl_to_dma, __args)
328#define stmmac_config_cbs(__priv, __args...) \
329 stmmac_do_void_callback(__priv, mac, config_cbs, __args)
330#define stmmac_dump_mac_regs(__priv, __args...) \
331 stmmac_do_void_callback(__priv, mac, dump_regs, __args)
332#define stmmac_host_irq_status(__priv, __args...) \
333 stmmac_do_callback(__priv, mac, host_irq_status, __args)
334#define stmmac_host_mtl_irq_status(__priv, __args...) \
335 stmmac_do_callback(__priv, mac, host_mtl_irq_status, __args)
336#define stmmac_set_filter(__priv, __args...) \
337 stmmac_do_void_callback(__priv, mac, set_filter, __args)
338#define stmmac_flow_ctrl(__priv, __args...) \
339 stmmac_do_void_callback(__priv, mac, flow_ctrl, __args)
340#define stmmac_pmt(__priv, __args...) \
341 stmmac_do_void_callback(__priv, mac, pmt, __args)
342#define stmmac_set_umac_addr(__priv, __args...) \
343 stmmac_do_void_callback(__priv, mac, set_umac_addr, __args)
344#define stmmac_get_umac_addr(__priv, __args...) \
345 stmmac_do_void_callback(__priv, mac, get_umac_addr, __args)
346#define stmmac_set_eee_mode(__priv, __args...) \
347 stmmac_do_void_callback(__priv, mac, set_eee_mode, __args)
348#define stmmac_reset_eee_mode(__priv, __args...) \
349 stmmac_do_void_callback(__priv, mac, reset_eee_mode, __args)
350#define stmmac_set_eee_timer(__priv, __args...) \
351 stmmac_do_void_callback(__priv, mac, set_eee_timer, __args)
352#define stmmac_set_eee_pls(__priv, __args...) \
353 stmmac_do_void_callback(__priv, mac, set_eee_pls, __args)
354#define stmmac_mac_debug(__priv, __args...) \
355 stmmac_do_void_callback(__priv, mac, debug, __args)
356#define stmmac_pcs_ctrl_ane(__priv, __args...) \
357 stmmac_do_void_callback(__priv, mac, pcs_ctrl_ane, __args)
358#define stmmac_pcs_rane(__priv, __args...) \
359 stmmac_do_void_callback(__priv, mac, pcs_rane, __args)
360#define stmmac_pcs_get_adv_lp(__priv, __args...) \
361 stmmac_do_void_callback(__priv, mac, pcs_get_adv_lp, __args)
362#define stmmac_safety_feat_config(__priv, __args...) \
363 stmmac_do_callback(__priv, mac, safety_feat_config, __args)
364#define stmmac_safety_feat_irq_status(__priv, __args...) \
365 stmmac_do_callback(__priv, mac, safety_feat_irq_status, __args)
366#define stmmac_safety_feat_dump(__priv, __args...) \
367 stmmac_do_callback(__priv, mac, safety_feat_dump, __args)
368
369/* PTP and HW Timer helpers */
370struct stmmac_hwtimestamp {
371 void (*config_hw_tstamping) (void __iomem *ioaddr, u32 data);
372 void (*config_sub_second_increment)(void __iomem *ioaddr, u32 ptp_clock,
373 int gmac4, u32 *ssinc);
374 int (*init_systime) (void __iomem *ioaddr, u32 sec, u32 nsec);
375 int (*config_addend) (void __iomem *ioaddr, u32 addend);
376 int (*adjust_systime) (void __iomem *ioaddr, u32 sec, u32 nsec,
377 int add_sub, int gmac4);
378 void (*get_systime) (void __iomem *ioaddr, u64 *systime);
379};
380
381#define stmmac_config_hw_tstamping(__priv, __args...) \
382 stmmac_do_void_callback(__priv, ptp, config_hw_tstamping, __args)
383#define stmmac_config_sub_second_increment(__priv, __args...) \
384 stmmac_do_void_callback(__priv, ptp, config_sub_second_increment, __args)
385#define stmmac_init_systime(__priv, __args...) \
386 stmmac_do_callback(__priv, ptp, init_systime, __args)
387#define stmmac_config_addend(__priv, __args...) \
388 stmmac_do_callback(__priv, ptp, config_addend, __args)
389#define stmmac_adjust_systime(__priv, __args...) \
390 stmmac_do_callback(__priv, ptp, adjust_systime, __args)
391#define stmmac_get_systime(__priv, __args...) \
392 stmmac_do_void_callback(__priv, ptp, get_systime, __args)
393
394/* Helpers to manage the descriptors for chain and ring modes */
395struct stmmac_mode_ops {
396 void (*init) (void *des, dma_addr_t phy_addr, unsigned int size,
397 unsigned int extend_desc);
398 unsigned int (*is_jumbo_frm) (int len, int ehn_desc);
399 int (*jumbo_frm)(void *priv, struct sk_buff *skb, int csum);
400 int (*set_16kib_bfsize)(int mtu);
401 void (*init_desc3)(struct dma_desc *p);
402 void (*refill_desc3) (void *priv, struct dma_desc *p);
403 void (*clean_desc3) (void *priv, struct dma_desc *p);
404};
405
406#define stmmac_mode_init(__priv, __args...) \
407 stmmac_do_void_callback(__priv, mode, init, __args)
408#define stmmac_is_jumbo_frm(__priv, __args...) \
409 stmmac_do_callback(__priv, mode, is_jumbo_frm, __args)
410#define stmmac_jumbo_frm(__priv, __args...) \
411 stmmac_do_callback(__priv, mode, jumbo_frm, __args)
412#define stmmac_set_16kib_bfsize(__priv, __args...) \
413 stmmac_do_callback(__priv, mode, set_16kib_bfsize, __args)
414#define stmmac_init_desc3(__priv, __args...) \
415 stmmac_do_void_callback(__priv, mode, init_desc3, __args)
416#define stmmac_refill_desc3(__priv, __args...) \
417 stmmac_do_void_callback(__priv, mode, refill_desc3, __args)
418#define stmmac_clean_desc3(__priv, __args...) \
419 stmmac_do_void_callback(__priv, mode, clean_desc3, __args)
420
421#endif /* __STMMAC_HWIF_H__ */
drivers/net/ethernet/stmicro/stmmac/norm_desc.c+2−2
@@ -253,7 +253,7 @@ static int ndesc_get_tx_timestamp_status(struct dma_desc *p) · 252 unmodified lines
253 return (le32_to_cpu(p->des0) & TDES0_TIME_STAMP_STATUS) >> 17;253 return (le32_to_cpu(p->des0) & TDES0_TIME_STAMP_STATUS) >> 17;
254}254}
255 255
256static u64 ndesc_get_timestamp(void *desc, u32 ats)256static void ndesc_get_timestamp(void *desc, u32 ats, u64 *ts)
257{257{
258 struct dma_desc *p = (struct dma_desc *)desc;258 struct dma_desc *p = (struct dma_desc *)desc;
259 u64 ns;259 u64 ns;
@@ -262,7 +262,7 @@ static u64 ndesc_get_timestamp(void *desc, u32 ats) · 2 unmodified lines
262 /* convert high/sec time stamp value to nanosecond */262 /* convert high/sec time stamp value to nanosecond */
263 ns += le32_to_cpu(p->des3) * 1000000000ULL;263 ns += le32_to_cpu(p->des3) * 1000000000ULL;
264 264
265 return ns;265 *ts = ns;
266}266}
267 267
268static int ndesc_get_rx_timestamp_status(void *desc, void *next_desc, u32 ats)268static int ndesc_get_rx_timestamp_status(void *desc, void *next_desc, u32 ats)
drivers/net/ethernet/stmicro/stmmac/ring_mode.c+18−21
@@ -24,7 +24,7 @@ · 23 unmodified lines
24 24
25#include "stmmac.h"25#include "stmmac.h"
26 26
27static int stmmac_jumbo_frm(void *p, struct sk_buff *skb, int csum)27static int jumbo_frm(void *p, struct sk_buff *skb, int csum)
28{28{
29 struct stmmac_tx_queue *tx_q = (struct stmmac_tx_queue *)p;29 struct stmmac_tx_queue *tx_q = (struct stmmac_tx_queue *)p;
30 unsigned int nopaged_len = skb_headlen(skb);30 unsigned int nopaged_len = skb_headlen(skb);
@@ -58,9 +58,8 @@ static int stmmac_jumbo_frm(void *p, struct sk_buff *skb, int csum) · 27 unmodified lines
58 tx_q->tx_skbuff_dma[entry].is_jumbo = true;58 tx_q->tx_skbuff_dma[entry].is_jumbo = true;
59 59
60 desc->des3 = cpu_to_le32(des2 + BUF_SIZE_4KiB);60 desc->des3 = cpu_to_le32(des2 + BUF_SIZE_4KiB);
61 priv->hw->desc->prepare_tx_desc(desc, 1, bmax, csum,61 stmmac_prepare_tx_desc(priv, desc, 1, bmax, csum,
62 STMMAC_RING_MODE, 0,62 STMMAC_RING_MODE, 0, false, skb->len);
63 false, skb->len);
64 tx_q->tx_skbuff[entry] = NULL;63 tx_q->tx_skbuff[entry] = NULL;
65 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE);64 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE);
66 65
@@ -79,9 +78,8 @@ static int stmmac_jumbo_frm(void *p, struct sk_buff *skb, int csum) · 12 unmodified lines
79 tx_q->tx_skbuff_dma[entry].is_jumbo = true;78 tx_q->tx_skbuff_dma[entry].is_jumbo = true;
80 79
81 desc->des3 = cpu_to_le32(des2 + BUF_SIZE_4KiB);80 desc->des3 = cpu_to_le32(des2 + BUF_SIZE_4KiB);
82 priv->hw->desc->prepare_tx_desc(desc, 0, len, csum,81 stmmac_prepare_tx_desc(priv, desc, 0, len, csum,
83 STMMAC_RING_MODE, 1,82 STMMAC_RING_MODE, 1, true, skb->len);
84 true, skb->len);
85 } else {83 } else {
86 des2 = dma_map_single(priv->device, skb->data,84 des2 = dma_map_single(priv->device, skb->data,
87 nopaged_len, DMA_TO_DEVICE);85 nopaged_len, DMA_TO_DEVICE);
@@ -92,9 +90,8 @@ static int stmmac_jumbo_frm(void *p, struct sk_buff *skb, int csum) · 4 unmodified lines
92 tx_q->tx_skbuff_dma[entry].len = nopaged_len;90 tx_q->tx_skbuff_dma[entry].len = nopaged_len;
93 tx_q->tx_skbuff_dma[entry].is_jumbo = true;91 tx_q->tx_skbuff_dma[entry].is_jumbo = true;
94 desc->des3 = cpu_to_le32(des2 + BUF_SIZE_4KiB);92 desc->des3 = cpu_to_le32(des2 + BUF_SIZE_4KiB);
95 priv->hw->desc->prepare_tx_desc(desc, 1, nopaged_len, csum,93 stmmac_prepare_tx_desc(priv, desc, 1, nopaged_len, csum,
96 STMMAC_RING_MODE, 0,94 STMMAC_RING_MODE, 0, true, skb->len);
97 true, skb->len);
98 }95 }
99 96
100 tx_q->cur_tx = entry;97 tx_q->cur_tx = entry;
@@ -102,7 +99,7 @@ static int stmmac_jumbo_frm(void *p, struct sk_buff *skb, int csum) · 1 unmodified line
102 return entry;99 return entry;
103}100}
104 101
105static unsigned int stmmac_is_jumbo_frm(int len, int enh_desc)102static unsigned int is_jumbo_frm(int len, int enh_desc)
106{103{
107 unsigned int ret = 0;104 unsigned int ret = 0;
108 105
@@ -112,7 +109,7 @@ static unsigned int stmmac_is_jumbo_frm(int len, int enh_desc) · 3 unmodified lines
112 return ret;109 return ret;
113}110}
114 111
115static void stmmac_refill_desc3(void *priv_ptr, struct dma_desc *p)112static void refill_desc3(void *priv_ptr, struct dma_desc *p)
116{113{
117 struct stmmac_priv *priv = (struct stmmac_priv *)priv_ptr;114 struct stmmac_priv *priv = (struct stmmac_priv *)priv_ptr;
118 115
@@ -122,12 +119,12 @@ static void stmmac_refill_desc3(void *priv_ptr, struct dma_desc *p) · 3 unmodified lines
122}119}
123 120
124/* In ring mode we need to fill the desc3 because it is used as buffer */121/* In ring mode we need to fill the desc3 because it is used as buffer */
125static void stmmac_init_desc3(struct dma_desc *p)122static void init_desc3(struct dma_desc *p)
126{123{
127 p->des3 = cpu_to_le32(le32_to_cpu(p->des2) + BUF_SIZE_8KiB);124 p->des3 = cpu_to_le32(le32_to_cpu(p->des2) + BUF_SIZE_8KiB);
128}125}
129 126
130static void stmmac_clean_desc3(void *priv_ptr, struct dma_desc *p)127static void clean_desc3(void *priv_ptr, struct dma_desc *p)
131{128{
132 struct stmmac_tx_queue *tx_q = (struct stmmac_tx_queue *)priv_ptr;129 struct stmmac_tx_queue *tx_q = (struct stmmac_tx_queue *)priv_ptr;
133 struct stmmac_priv *priv = tx_q->priv_data;130 struct stmmac_priv *priv = tx_q->priv_data;
@@ -140,7 +137,7 @@ static void stmmac_clean_desc3(void *priv_ptr, struct dma_desc *p) · 6 unmodified lines
140 p->des3 = 0;137 p->des3 = 0;
141}138}
142 139
143static int stmmac_set_16kib_bfsize(int mtu)140static int set_16kib_bfsize(int mtu)
144{141{
145 int ret = 0;142 int ret = 0;
146 if (unlikely(mtu >= BUF_SIZE_8KiB))143 if (unlikely(mtu >= BUF_SIZE_8KiB))
@@ -149,10 +146,10 @@ static int stmmac_set_16kib_bfsize(int mtu) · 2 unmodified lines
149}146}
150 147
151const struct stmmac_mode_ops ring_mode_ops = {148const struct stmmac_mode_ops ring_mode_ops = {
152 .is_jumbo_frm = stmmac_is_jumbo_frm,149 .is_jumbo_frm = is_jumbo_frm,
153 .jumbo_frm = stmmac_jumbo_frm,150 .jumbo_frm = jumbo_frm,
154 .refill_desc3 = stmmac_refill_desc3,151 .refill_desc3 = refill_desc3,
155 .init_desc3 = stmmac_init_desc3,152 .init_desc3 = init_desc3,
156 .clean_desc3 = stmmac_clean_desc3,153 .clean_desc3 = clean_desc3,
157 .set_16kib_bfsize = stmmac_set_16kib_bfsize,154 .set_16kib_bfsize = set_16kib_bfsize,
158};155};
drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c+31−51
@@ -291,11 +291,9 @@ static int stmmac_ethtool_get_link_ksettings(struct net_device *dev, · 290 unmodified lines
291 cmd->base.speed = priv->xstats.pcs_speed;291 cmd->base.speed = priv->xstats.pcs_speed;
292 292
293 /* Get and convert ADV/LP_ADV from the HW AN registers */293 /* Get and convert ADV/LP_ADV from the HW AN registers */
294 if (!priv->hw->mac->pcs_get_adv_lp)294 if (stmmac_pcs_get_adv_lp(priv, priv->ioaddr, &adv))
295 return -EOPNOTSUPP; /* should never happen indeed */295 return -EOPNOTSUPP; /* should never happen indeed */
296 296
297 priv->hw->mac->pcs_get_adv_lp(priv->ioaddr, &adv);
298
299 /* Encoding of PSE bits is defined in 802.3z, 37.2.1.4 */297 /* Encoding of PSE bits is defined in 802.3z, 37.2.1.4 */
300 298
301 ethtool_convert_link_mode_to_legacy_u32(299 ethtool_convert_link_mode_to_legacy_u32(
@@ -393,11 +391,7 @@ stmmac_ethtool_set_link_ksettings(struct net_device *dev, · 91 unmodified lines
393 ADVERTISED_10baseT_Full);391 ADVERTISED_10baseT_Full);
394 392
395 spin_lock(&priv->lock);393 spin_lock(&priv->lock);
396 394 stmmac_pcs_ctrl_ane(priv, priv->ioaddr, 1, priv->hw->ps, 0);
397 if (priv->hw->mac->pcs_ctrl_ane)
398 priv->hw->mac->pcs_ctrl_ane(priv->ioaddr, 1,
399 priv->hw->ps, 0);
400
401 spin_unlock(&priv->lock);395 spin_unlock(&priv->lock);
402 396
403 return 0;397 return 0;
@@ -442,8 +436,8 @@ static void stmmac_ethtool_gregs(struct net_device *dev, · 38 unmodified lines
442 436
443 memset(reg_space, 0x0, REG_SPACE_SIZE);437 memset(reg_space, 0x0, REG_SPACE_SIZE);
444 438
445 priv->hw->mac->dump_regs(priv->hw, reg_space);439 stmmac_dump_mac_regs(priv, priv->hw, reg_space);
446 priv->hw->dma->dump_regs(priv->ioaddr, reg_space);440 stmmac_dump_dma_regs(priv, priv->ioaddr, reg_space);
447 /* Copy DMA registers to where ethtool expects them */441 /* Copy DMA registers to where ethtool expects them */
448 memcpy(&reg_space[ETHTOOL_DMA_OFFSET], &reg_space[DMA_BUS_MODE / 4],442 memcpy(&reg_space[ETHTOOL_DMA_OFFSET], &reg_space[DMA_BUS_MODE / 4],
449 NUM_DWMAC1000_DMA_REGS * 4);443 NUM_DWMAC1000_DMA_REGS * 4);
@@ -454,15 +448,13 @@ stmmac_get_pauseparam(struct net_device *netdev, · 4 unmodified lines
454 struct ethtool_pauseparam *pause)448 struct ethtool_pauseparam *pause)
455{449{
456 struct stmmac_priv *priv = netdev_priv(netdev);450 struct stmmac_priv *priv = netdev_priv(netdev);
451 struct rgmii_adv adv_lp;
457 452
458 pause->rx_pause = 0;453 pause->rx_pause = 0;
459 pause->tx_pause = 0;454 pause->tx_pause = 0;
460 455
461 if (priv->hw->pcs && priv->hw->mac->pcs_get_adv_lp) {456 if (priv->hw->pcs && !stmmac_pcs_get_adv_lp(priv, priv->ioaddr, &adv_lp)) {
462 struct rgmii_adv adv_lp;
463
464 pause->autoneg = 1;457 pause->autoneg = 1;
465 priv->hw->mac->pcs_get_adv_lp(priv->ioaddr, &adv_lp);
466 if (!adv_lp.pause)458 if (!adv_lp.pause)
467 return;459 return;
468 } else {460 } else {
@@ -488,12 +480,10 @@ stmmac_set_pauseparam(struct net_device *netdev, · 19 unmodified lines
488 u32 tx_cnt = priv->plat->tx_queues_to_use;480 u32 tx_cnt = priv->plat->tx_queues_to_use;
489 struct phy_device *phy = netdev->phydev;481 struct phy_device *phy = netdev->phydev;
490 int new_pause = FLOW_OFF;482 int new_pause = FLOW_OFF;
483 struct rgmii_adv adv_lp;
491 484
492 if (priv->hw->pcs && priv->hw->mac->pcs_get_adv_lp) {485 if (priv->hw->pcs && !stmmac_pcs_get_adv_lp(priv, priv->ioaddr, &adv_lp)) {
493 struct rgmii_adv adv_lp;
494
495 pause->autoneg = 1;486 pause->autoneg = 1;
496 priv->hw->mac->pcs_get_adv_lp(priv->ioaddr, &adv_lp);
497 if (!adv_lp.pause)487 if (!adv_lp.pause)
498 return -EOPNOTSUPP;488 return -EOPNOTSUPP;
499 } else {489 } else {
@@ -515,37 +505,32 @@ stmmac_set_pauseparam(struct net_device *netdev, · 15 unmodified lines
515 return phy_start_aneg(phy);505 return phy_start_aneg(phy);
516 }506 }
517 507
518 priv->hw->mac->flow_ctrl(priv->hw, phy->duplex, priv->flow_ctrl,508 stmmac_flow_ctrl(priv, priv->hw, phy->duplex, priv->flow_ctrl,
519 priv->pause, tx_cnt);509 priv->pause, tx_cnt);
520 return 0;510 return 0;
521}511}
522 512
523static void stmmac_get_ethtool_stats(struct net_device *dev,513static void stmmac_get_ethtool_stats(struct net_device *dev,
524 struct ethtool_stats *dummy, u64 *data)514 struct ethtool_stats *dummy, u64 *data)
525{515{
526 const char *(*dump)(struct stmmac_safety_stats *stats, int index,
527 unsigned long *count);
528 struct stmmac_priv *priv = netdev_priv(dev);516 struct stmmac_priv *priv = netdev_priv(dev);
529 u32 rx_queues_count = priv->plat->rx_queues_to_use;517 u32 rx_queues_count = priv->plat->rx_queues_to_use;
530 u32 tx_queues_count = priv->plat->tx_queues_to_use;518 u32 tx_queues_count = priv->plat->tx_queues_to_use;
531 unsigned long count;519 unsigned long count;
532 int i, j = 0;520 int i, j = 0, ret;
533
534 if (priv->dma_cap.asp && priv->hw->mac->safety_feat_dump) {
535 dump = priv->hw->mac->safety_feat_dump;
536 521
522 if (priv->dma_cap.asp) {
537 for (i = 0; i < STMMAC_SAFETY_FEAT_SIZE; i++) {523 for (i = 0; i < STMMAC_SAFETY_FEAT_SIZE; i++) {
538 if (dump(&priv->sstats, i, &count))524 if (!stmmac_safety_feat_dump(priv, &priv->sstats, i,
525 &count, NULL))
539 data[j++] = count;526 data[j++] = count;
540 }527 }
541 }528 }
542 529
543 /* Update the DMA HW counters for dwmac10/100 */530 /* Update the DMA HW counters for dwmac10/100 */
544 if (priv->hw->dma->dma_diagnostic_fr)531 ret = stmmac_dma_diagnostic_fr(priv, &dev->stats, (void *) &priv->xstats,
545 priv->hw->dma->dma_diagnostic_fr(&dev->stats,532 priv->ioaddr);
546 (void *) &priv->xstats,533 if (ret) {
547 priv->ioaddr);
548 else {
549 /* If supported, for new GMAC chips expose the MMC counters */534 /* If supported, for new GMAC chips expose the MMC counters */
550 if (priv->dma_cap.rmon) {535 if (priv->dma_cap.rmon) {
551 dwmac_mmc_read(priv->mmcaddr, &priv->mmc);536 dwmac_mmc_read(priv->mmcaddr, &priv->mmc);
@@ -565,11 +550,10 @@ static void stmmac_get_ethtool_stats(struct net_device *dev, · 13 unmodified lines
565 priv->xstats.phy_eee_wakeup_error_n = val;550 priv->xstats.phy_eee_wakeup_error_n = val;
566 }551 }
567 552
568 if ((priv->hw->mac->debug) &&553 if (priv->synopsys_id >= DWMAC_CORE_3_50)
569 (priv->synopsys_id >= DWMAC_CORE_3_50))554 stmmac_mac_debug(priv, priv->ioaddr,
570 priv->hw->mac->debug(priv->ioaddr,555 (void *)&priv->xstats,
571 (void *)&priv->xstats,556 rx_queues_count, tx_queues_count);
572 rx_queues_count, tx_queues_count);
573 }557 }
574 for (i = 0; i < STMMAC_STATS_LEN; i++) {558 for (i = 0; i < STMMAC_STATS_LEN; i++) {
575 char *p = (char *)priv + stmmac_gstrings_stats[i].stat_offset;559 char *p = (char *)priv + stmmac_gstrings_stats[i].stat_offset;
@@ -581,8 +565,6 @@ static void stmmac_get_ethtool_stats(struct net_device *dev, · 5 unmodified lines
581static int stmmac_get_sset_count(struct net_device *netdev, int sset)565static int stmmac_get_sset_count(struct net_device *netdev, int sset)
582{566{
583 struct stmmac_priv *priv = netdev_priv(netdev);567 struct stmmac_priv *priv = netdev_priv(netdev);
584 const char *(*dump)(struct stmmac_safety_stats *stats, int index,
585 unsigned long *count);
586 int i, len, safety_len = 0;568 int i, len, safety_len = 0;
587 569
588 switch (sset) {570 switch (sset) {
@@ -591,11 +573,11 @@ static int stmmac_get_sset_count(struct net_device *netdev, int sset) · 2 unmodified lines
591 573
592 if (priv->dma_cap.rmon)574 if (priv->dma_cap.rmon)
593 len += STMMAC_MMC_STATS_LEN;575 len += STMMAC_MMC_STATS_LEN;
594 if (priv->dma_cap.asp && priv->hw->mac->safety_feat_dump) {576 if (priv->dma_cap.asp) {
595 dump = priv->hw->mac->safety_feat_dump;
596
597 for (i = 0; i < STMMAC_SAFETY_FEAT_SIZE; i++) {577 for (i = 0; i < STMMAC_SAFETY_FEAT_SIZE; i++) {
598 if (dump(&priv->sstats, i, NULL))578 if (!stmmac_safety_feat_dump(priv,
579 &priv->sstats, i,
580 NULL, NULL))
599 safety_len++;581 safety_len++;
600 }582 }
601 583
@@ -613,17 +595,15 @@ static void stmmac_get_strings(struct net_device *dev, u32 stringset, u8 *data) · 11 unmodified lines
613 int i;595 int i;
614 u8 *p = data;596 u8 *p = data;
615 struct stmmac_priv *priv = netdev_priv(dev);597 struct stmmac_priv *priv = netdev_priv(dev);
616 const char *(*dump)(struct stmmac_safety_stats *stats, int index,
617 unsigned long *count);
618 598
619 switch (stringset) {599 switch (stringset) {
620 case ETH_SS_STATS:600 case ETH_SS_STATS:
621 if (priv->dma_cap.asp && priv->hw->mac->safety_feat_dump) {601 if (priv->dma_cap.asp) {
622 dump = priv->hw->mac->safety_feat_dump;
623 for (i = 0; i < STMMAC_SAFETY_FEAT_SIZE; i++) {602 for (i = 0; i < STMMAC_SAFETY_FEAT_SIZE; i++) {
624 const char *desc = dump(&priv->sstats, i, NULL);603 const char *desc;
625 604 if (!stmmac_safety_feat_dump(priv,
626 if (desc) {605 &priv->sstats, i,
606 NULL, &desc)) {
627 memcpy(p, desc, ETH_GSTRING_LEN);607 memcpy(p, desc, ETH_GSTRING_LEN);
628 p += ETH_GSTRING_LEN;608 p += ETH_GSTRING_LEN;
629 }609 }
@@ -810,7 +790,7 @@ static int stmmac_set_coalesce(struct net_device *dev, · 180 unmodified lines
810 priv->tx_coal_frames = ec->tx_max_coalesced_frames;790 priv->tx_coal_frames = ec->tx_max_coalesced_frames;
811 priv->tx_coal_timer = ec->tx_coalesce_usecs;791 priv->tx_coal_timer = ec->tx_coalesce_usecs;
812 priv->rx_riwt = rx_riwt;792 priv->rx_riwt = rx_riwt;
813 priv->hw->dma->rx_watchdog(priv->ioaddr, priv->rx_riwt, rx_cnt);793 stmmac_rx_watchdog(priv, priv->ioaddr, priv->rx_riwt, rx_cnt);
814 794
815 return 0;795 return 0;
816}796}
drivers/net/ethernet/stmicro/stmmac/stmmac_hwtstamp.c+18−16
@@ -24,13 +24,13 @@ · 23 unmodified lines
24#include "common.h"24#include "common.h"
25#include "stmmac_ptp.h"25#include "stmmac_ptp.h"
26 26
27static void stmmac_config_hw_tstamping(void __iomem *ioaddr, u32 data)27static void config_hw_tstamping(void __iomem *ioaddr, u32 data)
28{28{
29 writel(data, ioaddr + PTP_TCR);29 writel(data, ioaddr + PTP_TCR);
30}30}
31 31
32static u32 stmmac_config_sub_second_increment(void __iomem *ioaddr,32static void config_sub_second_increment(void __iomem *ioaddr,
33 u32 ptp_clock, int gmac4)33 u32 ptp_clock, int gmac4, u32 *ssinc)
34{34{
35 u32 value = readl(ioaddr + PTP_TCR);35 u32 value = readl(ioaddr + PTP_TCR);
36 unsigned long data;36 unsigned long data;
@@ -57,10 +57,11 @@ static u32 stmmac_config_sub_second_increment(void __iomem *ioaddr, · 20 unmodified lines
57 57
58 writel(reg_value, ioaddr + PTP_SSIR);58 writel(reg_value, ioaddr + PTP_SSIR);
59 59
60 return data;60 if (ssinc)
61 *ssinc = data;
61}62}
62 63
63static int stmmac_init_systime(void __iomem *ioaddr, u32 sec, u32 nsec)64static int init_systime(void __iomem *ioaddr, u32 sec, u32 nsec)
64{65{
65 int limit;66 int limit;
66 u32 value;67 u32 value;
@@ -85,7 +86,7 @@ static int stmmac_init_systime(void __iomem *ioaddr, u32 sec, u32 nsec) · 18 unmodified lines
85 return 0;86 return 0;
86}87}
87 88
88static int stmmac_config_addend(void __iomem *ioaddr, u32 addend)89static int config_addend(void __iomem *ioaddr, u32 addend)
89{90{
90 u32 value;91 u32 value;
91 int limit;92 int limit;
@@ -109,8 +110,8 @@ static int stmmac_config_addend(void __iomem *ioaddr, u32 addend) · 17 unmodified lines
109 return 0;110 return 0;
110}111}
111 112
112static int stmmac_adjust_systime(void __iomem *ioaddr, u32 sec, u32 nsec,113static int adjust_systime(void __iomem *ioaddr, u32 sec, u32 nsec,
113 int add_sub, int gmac4)114 int add_sub, int gmac4)
114{115{
115 u32 value;116 u32 value;
116 int limit;117 int limit;
@@ -152,7 +153,7 @@ static int stmmac_adjust_systime(void __iomem *ioaddr, u32 sec, u32 nsec, · 35 unmodified lines
152 return 0;153 return 0;
153}154}
154 155
155static u64 stmmac_get_systime(void __iomem *ioaddr)156static void get_systime(void __iomem *ioaddr, u64 *systime)
156{157{
157 u64 ns;158 u64 ns;
158 159
@@ -161,14 +162,15 @@ static u64 stmmac_get_systime(void __iomem *ioaddr) · 2 unmodified lines
161 /* Get the TSS and convert sec time value to nanosecond */162 /* Get the TSS and convert sec time value to nanosecond */
162 ns += readl(ioaddr + PTP_STSR) * 1000000000ULL;163 ns += readl(ioaddr + PTP_STSR) * 1000000000ULL;
163 164
164 return ns;165 if (systime)
166 *systime = ns;
165}167}
166 168
167const struct stmmac_hwtimestamp stmmac_ptp = {169const struct stmmac_hwtimestamp stmmac_ptp = {
168 .config_hw_tstamping = stmmac_config_hw_tstamping,170 .config_hw_tstamping = config_hw_tstamping,
169 .init_systime = stmmac_init_systime,171 .init_systime = init_systime,
170 .config_sub_second_increment = stmmac_config_sub_second_increment,172 .config_sub_second_increment = config_sub_second_increment,
171 .config_addend = stmmac_config_addend,173 .config_addend = config_addend,
172 .adjust_systime = stmmac_adjust_systime,174 .adjust_systime = adjust_systime,
173 .get_systime = stmmac_get_systime,175 .get_systime = get_systime,
174};176};
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c+196−243
@@ -50,6 +50,7 @@ · 49 unmodified lines
50#include <linux/reset.h>50#include <linux/reset.h>
51#include <linux/of_mdio.h>51#include <linux/of_mdio.h>
52#include "dwmac1000.h"52#include "dwmac1000.h"
53#include "hwif.h"
53 54
54#define STMMAC_ALIGN(x) L1_CACHE_ALIGN(x)55#define STMMAC_ALIGN(x) L1_CACHE_ALIGN(x)
55#define TSO_MAX_BUFF_SIZE (SZ_16K - 1)56#define TSO_MAX_BUFF_SIZE (SZ_16K - 1)
@@ -335,8 +336,8 @@ static void stmmac_enable_eee_mode(struct stmmac_priv *priv) · 279 unmodified lines
335 336
336 /* Check and enter in LPI mode */337 /* Check and enter in LPI mode */
337 if (!priv->tx_path_in_lpi_mode)338 if (!priv->tx_path_in_lpi_mode)
338 priv->hw->mac->set_eee_mode(priv->hw,339 stmmac_set_eee_mode(priv, priv->hw,
339 priv->plat->en_tx_lpi_clockgating);340 priv->plat->en_tx_lpi_clockgating);
340}341}
341 342
342/**343/**
@@ -347,7 +348,7 @@ static void stmmac_enable_eee_mode(struct stmmac_priv *priv) · 4 unmodified lines
347 */348 */
348void stmmac_disable_eee_mode(struct stmmac_priv *priv)349void stmmac_disable_eee_mode(struct stmmac_priv *priv)
349{350{
350 priv->hw->mac->reset_eee_mode(priv->hw);351 stmmac_reset_eee_mode(priv, priv->hw);
351 del_timer_sync(&priv->eee_ctrl_timer);352 del_timer_sync(&priv->eee_ctrl_timer);
352 priv->tx_path_in_lpi_mode = false;353 priv->tx_path_in_lpi_mode = false;
353}354}
@@ -410,8 +411,8 @@ bool stmmac_eee_init(struct stmmac_priv *priv) · 56 unmodified lines
410 if (priv->eee_active) {411 if (priv->eee_active) {
411 netdev_dbg(priv->dev, "disable EEE\n");412 netdev_dbg(priv->dev, "disable EEE\n");
412 del_timer_sync(&priv->eee_ctrl_timer);413 del_timer_sync(&priv->eee_ctrl_timer);
413 priv->hw->mac->set_eee_timer(priv->hw, 0,414 stmmac_set_eee_timer(priv, priv->hw, 0,
414 tx_lpi_timer);415 tx_lpi_timer);
415 }416 }
416 priv->eee_active = 0;417 priv->eee_active = 0;
417 spin_unlock_irqrestore(&priv->lock, flags);418 spin_unlock_irqrestore(&priv->lock, flags);
@@ -426,12 +427,11 @@ bool stmmac_eee_init(struct stmmac_priv *priv) · 8 unmodified lines
426 mod_timer(&priv->eee_ctrl_timer,427 mod_timer(&priv->eee_ctrl_timer,
427 STMMAC_LPI_T(eee_timer));428 STMMAC_LPI_T(eee_timer));
428 429
429 priv->hw->mac->set_eee_timer(priv->hw,430 stmmac_set_eee_timer(priv, priv->hw,
430 STMMAC_DEFAULT_LIT_LS,431 STMMAC_DEFAULT_LIT_LS, tx_lpi_timer);
431 tx_lpi_timer);
432 }432 }
433 /* Set HW EEE according to the speed */433 /* Set HW EEE according to the speed */
434 priv->hw->mac->set_eee_pls(priv->hw, ndev->phydev->link);434 stmmac_set_eee_pls(priv, priv->hw, ndev->phydev->link);
435 435
436 ret = true;436 ret = true;
437 spin_unlock_irqrestore(&priv->lock, flags);437 spin_unlock_irqrestore(&priv->lock, flags);
@@ -464,9 +464,9 @@ static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv, · 26 unmodified lines
464 return;464 return;
465 465
466 /* check tx tstamp status */466 /* check tx tstamp status */
467 if (priv->hw->desc->get_tx_timestamp_status(p)) {467 if (stmmac_get_tx_timestamp_status(priv, p)) {
468 /* get the valid tstamp */468 /* get the valid tstamp */
469 ns = priv->hw->desc->get_timestamp(p, priv->adv_ts);469 stmmac_get_timestamp(priv, p, priv->adv_ts, &ns);
470 470
471 memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));471 memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
472 shhwtstamp.hwtstamp = ns_to_ktime(ns);472 shhwtstamp.hwtstamp = ns_to_ktime(ns);
@@ -502,8 +502,8 @@ static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv, struct dma_desc *p, · 29 unmodified lines
502 desc = np;502 desc = np;
503 503
504 /* Check if timestamp is available */504 /* Check if timestamp is available */
505 if (priv->hw->desc->get_rx_timestamp_status(p, np, priv->adv_ts)) {505 if (stmmac_get_rx_timestamp_status(priv, p, np, priv->adv_ts)) {
506 ns = priv->hw->desc->get_timestamp(desc, priv->adv_ts);506 stmmac_get_timestamp(priv, desc, priv->adv_ts, &ns);
507 netdev_dbg(priv->dev, "get valid RX hw timestamp %llu\n", ns);507 netdev_dbg(priv->dev, "get valid RX hw timestamp %llu\n", ns);
508 shhwtstamp = skb_hwtstamps(skb);508 shhwtstamp = skb_hwtstamps(skb);
509 memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));509 memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
@@ -707,18 +707,18 @@ static int stmmac_hwtstamp_ioctl(struct net_device *dev, struct ifreq *ifr) · 197 unmodified lines
707 priv->hwts_tx_en = config.tx_type == HWTSTAMP_TX_ON;707 priv->hwts_tx_en = config.tx_type == HWTSTAMP_TX_ON;
708 708
709 if (!priv->hwts_tx_en && !priv->hwts_rx_en)709 if (!priv->hwts_tx_en && !priv->hwts_rx_en)
710 priv->hw->ptp->config_hw_tstamping(priv->ptpaddr, 0);710 stmmac_config_hw_tstamping(priv, priv->ptpaddr, 0);
711 else {711 else {
712 value = (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | PTP_TCR_TSCTRLSSR |712 value = (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | PTP_TCR_TSCTRLSSR |
713 tstamp_all | ptp_v2 | ptp_over_ethernet |713 tstamp_all | ptp_v2 | ptp_over_ethernet |
714 ptp_over_ipv6_udp | ptp_over_ipv4_udp | ts_event_en |714 ptp_over_ipv6_udp | ptp_over_ipv4_udp | ts_event_en |
715 ts_master_en | snap_type_sel);715 ts_master_en | snap_type_sel);
716 priv->hw->ptp->config_hw_tstamping(priv->ptpaddr, value);716 stmmac_config_hw_tstamping(priv, priv->ptpaddr, value);
717 717
718 /* program Sub Second Increment reg */718 /* program Sub Second Increment reg */
719 sec_inc = priv->hw->ptp->config_sub_second_increment(719 stmmac_config_sub_second_increment(priv,
720 priv->ptpaddr, priv->plat->clk_ptp_rate,720 priv->ptpaddr, priv->plat->clk_ptp_rate,
721 priv->plat->has_gmac4);721 priv->plat->has_gmac4, &sec_inc);
722 temp = div_u64(1000000000ULL, sec_inc);722 temp = div_u64(1000000000ULL, sec_inc);
723 723
724 /* calculate default added value:724 /* calculate default added value:
@@ -728,15 +728,14 @@ static int stmmac_hwtstamp_ioctl(struct net_device *dev, struct ifreq *ifr) · 3 unmodified lines
728 */728 */
729 temp = (u64)(temp << 32);729 temp = (u64)(temp << 32);
730 priv->default_addend = div_u64(temp, priv->plat->clk_ptp_rate);730 priv->default_addend = div_u64(temp, priv->plat->clk_ptp_rate);
731 priv->hw->ptp->config_addend(priv->ptpaddr,731 stmmac_config_addend(priv, priv->ptpaddr, priv->default_addend);
732 priv->default_addend);
733 732
734 /* initialize system time */733 /* initialize system time */
735 ktime_get_real_ts64(&now);734 ktime_get_real_ts64(&now);
736 735
737 /* lower 32 bits of tv_sec are safe until y2106 */736 /* lower 32 bits of tv_sec are safe until y2106 */
738 priv->hw->ptp->init_systime(priv->ptpaddr, (u32)now.tv_sec,737 stmmac_init_systime(priv, priv->ptpaddr,
739 now.tv_nsec);738 (u32)now.tv_sec, now.tv_nsec);
740 }739 }
741 740
742 return copy_to_user(ifr->ifr_data, &config,741 return copy_to_user(ifr->ifr_data, &config,
@@ -795,8 +794,8 @@ static void stmmac_mac_flow_ctrl(struct stmmac_priv *priv, u32 duplex) · 52 unmodified lines
795{794{
796 u32 tx_cnt = priv->plat->tx_queues_to_use;795 u32 tx_cnt = priv->plat->tx_queues_to_use;
797 796
798 priv->hw->mac->flow_ctrl(priv->hw, duplex, priv->flow_ctrl,797 stmmac_flow_ctrl(priv, priv->hw, duplex, priv->flow_ctrl,
799 priv->pause, tx_cnt);798 priv->pause, tx_cnt);
800}799}
801 800
802/**801/**
@@ -1008,7 +1007,7 @@ static void stmmac_display_rx_rings(struct stmmac_priv *priv) · 205 unmodified lines
1008 head_rx = (void *)rx_q->dma_rx;1007 head_rx = (void *)rx_q->dma_rx;
1009 1008
1010 /* Display RX ring */1009 /* Display RX ring */
1011 priv->hw->desc->display_ring(head_rx, DMA_RX_SIZE, true);1010 stmmac_display_ring(priv, head_rx, DMA_RX_SIZE, true);
1012 }1011 }
1013}1012}
1014 1013
@@ -1029,7 +1028,7 @@ static void stmmac_display_tx_rings(struct stmmac_priv *priv) · 14 unmodified lines
1029 else1028 else
1030 head_tx = (void *)tx_q->dma_tx;1029 head_tx = (void *)tx_q->dma_tx;
1031 1030
1032 priv->hw->desc->display_ring(head_tx, DMA_TX_SIZE, false);1031 stmmac_display_ring(priv, head_tx, DMA_TX_SIZE, false);
1033 }1032 }
1034}1033}
1035 1034
@@ -1073,13 +1072,13 @@ static void stmmac_clear_rx_descriptors(struct stmmac_priv *priv, u32 queue) · 37 unmodified lines
1073 /* Clear the RX descriptors */1072 /* Clear the RX descriptors */
1074 for (i = 0; i < DMA_RX_SIZE; i++)1073 for (i = 0; i < DMA_RX_SIZE; i++)
1075 if (priv->extend_desc)1074 if (priv->extend_desc)
1076 priv->hw->desc->init_rx_desc(&rx_q->dma_erx[i].basic,1075 stmmac_init_rx_desc(priv, &rx_q->dma_erx[i].basic,
1077 priv->use_riwt, priv->mode,1076 priv->use_riwt, priv->mode,
1078 (i == DMA_RX_SIZE - 1));1077 (i == DMA_RX_SIZE - 1));
1079 else1078 else
1080 priv->hw->desc->init_rx_desc(&rx_q->dma_rx[i],1079 stmmac_init_rx_desc(priv, &rx_q->dma_rx[i],
1081 priv->use_riwt, priv->mode,1080 priv->use_riwt, priv->mode,
1082 (i == DMA_RX_SIZE - 1));1081 (i == DMA_RX_SIZE - 1));
1083}1082}
1084 1083
1085/**1084/**
@@ -1097,13 +1096,11 @@ static void stmmac_clear_tx_descriptors(struct stmmac_priv *priv, u32 queue) · 11 unmodified lines
1097 /* Clear the TX descriptors */1096 /* Clear the TX descriptors */
1098 for (i = 0; i < DMA_TX_SIZE; i++)1097 for (i = 0; i < DMA_TX_SIZE; i++)
1099 if (priv->extend_desc)1098 if (priv->extend_desc)
1100 priv->hw->desc->init_tx_desc(&tx_q->dma_etx[i].basic,1099 stmmac_init_tx_desc(priv, &tx_q->dma_etx[i].basic,
1101 priv->mode,1100 priv->mode, (i == DMA_TX_SIZE - 1));
1102 (i == DMA_TX_SIZE - 1));
1103 else1101 else
1104 priv->hw->desc->init_tx_desc(&tx_q->dma_tx[i],1102 stmmac_init_tx_desc(priv, &tx_q->dma_tx[i],
1105 priv->mode,1103 priv->mode, (i == DMA_TX_SIZE - 1));
1106 (i == DMA_TX_SIZE - 1));
1107}1104}
1108 1105
1109/**1106/**
@@ -1164,9 +1161,8 @@ static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p, · 54 unmodified lines
1164 else1161 else
1165 p->des2 = cpu_to_le32(rx_q->rx_skbuff_dma[i]);1162 p->des2 = cpu_to_le32(rx_q->rx_skbuff_dma[i]);
1166 1163
1167 if ((priv->hw->mode->init_desc3) &&1164 if (priv->dma_buf_sz == BUF_SIZE_16KiB)
1168 (priv->dma_buf_sz == BUF_SIZE_16KiB))1165 stmmac_init_desc3(priv, p);
1169 priv->hw->mode->init_desc3(p);
1170 1166
1171 return 0;1167 return 0;
1172}1168}
@@ -1232,13 +1228,14 @@ static int init_dma_rx_desc_rings(struct net_device *dev, gfp_t flags) · 59 unmodified lines
1232{1228{
1233 struct stmmac_priv *priv = netdev_priv(dev);1229 struct stmmac_priv *priv = netdev_priv(dev);
1234 u32 rx_count = priv->plat->rx_queues_to_use;1230 u32 rx_count = priv->plat->rx_queues_to_use;
1235 unsigned int bfsize = 0;
1236 int ret = -ENOMEM;1231 int ret = -ENOMEM;
1232 int bfsize = 0;
1237 int queue;1233 int queue;
1238 int i;1234 int i;
1239 1235
1240 if (priv->hw->mode->set_16kib_bfsize)1236 bfsize = stmmac_set_16kib_bfsize(priv, dev->mtu);
1241 bfsize = priv->hw->mode->set_16kib_bfsize(dev->mtu);1237 if (bfsize < 0)
1238 bfsize = 0;
1242 1239
1243 if (bfsize < BUF_SIZE_16KiB)1240 if (bfsize < BUF_SIZE_16KiB)
1244 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz);1241 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz);
@@ -1282,13 +1279,11 @@ static int init_dma_rx_desc_rings(struct net_device *dev, gfp_t flags) · 37 unmodified lines
1282 /* Setup the chained descriptor addresses */1279 /* Setup the chained descriptor addresses */
1283 if (priv->mode == STMMAC_CHAIN_MODE) {1280 if (priv->mode == STMMAC_CHAIN_MODE) {
1284 if (priv->extend_desc)1281 if (priv->extend_desc)
1285 priv->hw->mode->init(rx_q->dma_erx,1282 stmmac_mode_init(priv, rx_q->dma_erx,
1286 rx_q->dma_rx_phy,1283 rx_q->dma_rx_phy, DMA_RX_SIZE, 1);
1287 DMA_RX_SIZE, 1);
1288 else1284 else
1289 priv->hw->mode->init(rx_q->dma_rx,1285 stmmac_mode_init(priv, rx_q->dma_rx,
1290 rx_q->dma_rx_phy,1286 rx_q->dma_rx_phy, DMA_RX_SIZE, 0);
1291 DMA_RX_SIZE, 0);
1292 }1287 }
1293 }1288 }
1294 1289
@@ -1335,13 +1330,11 @@ static int init_dma_tx_desc_rings(struct net_device *dev) · 40 unmodified lines
1335 /* Setup the chained descriptor addresses */1330 /* Setup the chained descriptor addresses */
1336 if (priv->mode == STMMAC_CHAIN_MODE) {1331 if (priv->mode == STMMAC_CHAIN_MODE) {
1337 if (priv->extend_desc)1332 if (priv->extend_desc)
1338 priv->hw->mode->init(tx_q->dma_etx,1333 stmmac_mode_init(priv, tx_q->dma_etx,
1339 tx_q->dma_tx_phy,1334 tx_q->dma_tx_phy, DMA_TX_SIZE, 1);
1340 DMA_TX_SIZE, 1);
1341 else1335 else
1342 priv->hw->mode->init(tx_q->dma_tx,1336 stmmac_mode_init(priv, tx_q->dma_tx,
1343 tx_q->dma_tx_phy,1337 tx_q->dma_tx_phy, DMA_TX_SIZE, 0);
1344 DMA_TX_SIZE, 0);
1345 }1338 }
1346 1339
1347 for (i = 0; i < DMA_TX_SIZE; i++) {1340 for (i = 0; i < DMA_TX_SIZE; i++) {
@@ -1664,7 +1657,7 @@ static void stmmac_mac_enable_rx_queues(struct stmmac_priv *priv) · 316 unmodified lines
1664 1657
1665 for (queue = 0; queue < rx_queues_count; queue++) {1658 for (queue = 0; queue < rx_queues_count; queue++) {
1666 mode = priv->plat->rx_queues_cfg[queue].mode_to_use;1659 mode = priv->plat->rx_queues_cfg[queue].mode_to_use;
1667 priv->hw->mac->rx_queue_enable(priv->hw, mode, queue);1660 stmmac_rx_queue_enable(priv, priv->hw, mode, queue);
1668 }1661 }
1669}1662}
1670 1663
@@ -1678,7 +1671,7 @@ static void stmmac_mac_enable_rx_queues(struct stmmac_priv *priv) · 7 unmodified lines
1678static void stmmac_start_rx_dma(struct stmmac_priv *priv, u32 chan)1671static void stmmac_start_rx_dma(struct stmmac_priv *priv, u32 chan)
1679{1672{
1680 netdev_dbg(priv->dev, "DMA RX processes started in channel %d\n", chan);1673 netdev_dbg(priv->dev, "DMA RX processes started in channel %d\n", chan);
1681 priv->hw->dma->start_rx(priv->ioaddr, chan);1674 stmmac_start_rx(priv, priv->ioaddr, chan);
1682}1675}
1683 1676
1684/**1677/**
@@ -1691,7 +1684,7 @@ static void stmmac_start_rx_dma(struct stmmac_priv *priv, u32 chan) · 6 unmodified lines
1691static void stmmac_start_tx_dma(struct stmmac_priv *priv, u32 chan)1684static void stmmac_start_tx_dma(struct stmmac_priv *priv, u32 chan)
1692{1685{
1693 netdev_dbg(priv->dev, "DMA TX processes started in channel %d\n", chan);1686 netdev_dbg(priv->dev, "DMA TX processes started in channel %d\n", chan);
1694 priv->hw->dma->start_tx(priv->ioaddr, chan);1687 stmmac_start_tx(priv, priv->ioaddr, chan);
1695}1688}
1696 1689
1697/**1690/**
@@ -1704,7 +1697,7 @@ static void stmmac_start_tx_dma(struct stmmac_priv *priv, u32 chan) · 6 unmodified lines
1704static void stmmac_stop_rx_dma(struct stmmac_priv *priv, u32 chan)1697static void stmmac_stop_rx_dma(struct stmmac_priv *priv, u32 chan)
1705{1698{
1706 netdev_dbg(priv->dev, "DMA RX processes stopped in channel %d\n", chan);1699 netdev_dbg(priv->dev, "DMA RX processes stopped in channel %d\n", chan);
1707 priv->hw->dma->stop_rx(priv->ioaddr, chan);1700 stmmac_stop_rx(priv, priv->ioaddr, chan);
1708}1701}
1709 1702
1710/**1703/**
@@ -1717,7 +1710,7 @@ static void stmmac_stop_rx_dma(struct stmmac_priv *priv, u32 chan) · 6 unmodified lines
1717static void stmmac_stop_tx_dma(struct stmmac_priv *priv, u32 chan)1710static void stmmac_stop_tx_dma(struct stmmac_priv *priv, u32 chan)
1718{1711{
1719 netdev_dbg(priv->dev, "DMA TX processes stopped in channel %d\n", chan);1712 netdev_dbg(priv->dev, "DMA TX processes stopped in channel %d\n", chan);
1720 priv->hw->dma->stop_tx(priv->ioaddr, chan);1713 stmmac_stop_tx(priv, priv->ioaddr, chan);
1721}1714}
1722 1715
1723/**1716/**
@@ -1808,19 +1801,18 @@ static void stmmac_dma_operation_mode(struct stmmac_priv *priv) · 84 unmodified lines
1808 for (chan = 0; chan < rx_channels_count; chan++) {1801 for (chan = 0; chan < rx_channels_count; chan++) {
1809 qmode = priv->plat->rx_queues_cfg[chan].mode_to_use;1802 qmode = priv->plat->rx_queues_cfg[chan].mode_to_use;
1810 1803
1811 priv->hw->dma->dma_rx_mode(priv->ioaddr, rxmode, chan,1804 stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan,
1812 rxfifosz, qmode);1805 rxfifosz, qmode);
1813 }1806 }
1814 1807
1815 for (chan = 0; chan < tx_channels_count; chan++) {1808 for (chan = 0; chan < tx_channels_count; chan++) {
1816 qmode = priv->plat->tx_queues_cfg[chan].mode_to_use;1809 qmode = priv->plat->tx_queues_cfg[chan].mode_to_use;
1817 1810
1818 priv->hw->dma->dma_tx_mode(priv->ioaddr, txmode, chan,1811 stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan,
1819 txfifosz, qmode);1812 txfifosz, qmode);
1820 }1813 }
1821 } else {1814 } else {
1822 priv->hw->dma->dma_mode(priv->ioaddr, txmode, rxmode,1815 stmmac_dma_mode(priv, priv->ioaddr, txmode, rxmode, rxfifosz);
1823 rxfifosz);
1824 }1816 }
1825}1817}
1826 1818
@@ -1851,9 +1843,8 @@ static void stmmac_tx_clean(struct stmmac_priv *priv, u32 queue) · 24 unmodified lines
1851 else1843 else
1852 p = tx_q->dma_tx + entry;1844 p = tx_q->dma_tx + entry;
1853 1845
1854 status = priv->hw->desc->tx_status(&priv->dev->stats,1846 status = stmmac_tx_status(priv, &priv->dev->stats,
1855 &priv->xstats, p,1847 &priv->xstats, p, priv->ioaddr);
1856 priv->ioaddr);
1857 /* Check if the descriptor is owned by the DMA */1848 /* Check if the descriptor is owned by the DMA */
1858 if (unlikely(status & tx_dma_own))1849 if (unlikely(status & tx_dma_own))
1859 break;1850 break;
@@ -1891,8 +1882,7 @@ static void stmmac_tx_clean(struct stmmac_priv *priv, u32 queue) · 31 unmodified lines
1891 tx_q->tx_skbuff_dma[entry].map_as_page = false;1882 tx_q->tx_skbuff_dma[entry].map_as_page = false;
1892 }1883 }
1893 1884
1894 if (priv->hw->mode->clean_desc3)1885 stmmac_clean_desc3(priv, tx_q, p);
1895 priv->hw->mode->clean_desc3(tx_q, p);
1896 1886
1897 tx_q->tx_skbuff_dma[entry].last_segment = false;1887 tx_q->tx_skbuff_dma[entry].last_segment = false;
1898 tx_q->tx_skbuff_dma[entry].is_jumbo = false;1888 tx_q->tx_skbuff_dma[entry].is_jumbo = false;
@@ -1904,7 +1894,7 @@ static void stmmac_tx_clean(struct stmmac_priv *priv, u32 queue) · 5 unmodified lines
1904 tx_q->tx_skbuff[entry] = NULL;1894 tx_q->tx_skbuff[entry] = NULL;
1905 }1895 }
1906 1896
1907 priv->hw->desc->release_tx_desc(p, priv->mode);1897 stmmac_release_tx_desc(priv, p, priv->mode);
1908 1898
1909 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE);1899 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE);
1910 }1900 }
@@ -1929,16 +1919,6 @@ static void stmmac_tx_clean(struct stmmac_priv *priv, u32 queue) · 18 unmodified lines
1929 netif_tx_unlock(priv->dev);1919 netif_tx_unlock(priv->dev);
1930}1920}
1931 1921
1932static inline void stmmac_enable_dma_irq(struct stmmac_priv *priv, u32 chan)
1933{
1934 priv->hw->dma->enable_dma_irq(priv->ioaddr, chan);
1935}
1936
1937static inline void stmmac_disable_dma_irq(struct stmmac_priv *priv, u32 chan)
1938{
1939 priv->hw->dma->disable_dma_irq(priv->ioaddr, chan);
1940}
1941
1942/**1922/**
1943 * stmmac_tx_err - to manage the tx error1923 * stmmac_tx_err - to manage the tx error
1944 * @priv: driver private structure1924 * @priv: driver private structure
@@ -1957,13 +1937,11 @@ static void stmmac_tx_err(struct stmmac_priv *priv, u32 chan) · 12 unmodified lines
1957 dma_free_tx_skbufs(priv, chan);1937 dma_free_tx_skbufs(priv, chan);
1958 for (i = 0; i < DMA_TX_SIZE; i++)1938 for (i = 0; i < DMA_TX_SIZE; i++)
1959 if (priv->extend_desc)1939 if (priv->extend_desc)
1960 priv->hw->desc->init_tx_desc(&tx_q->dma_etx[i].basic,1940 stmmac_init_tx_desc(priv, &tx_q->dma_etx[i].basic,
1961 priv->mode,1941 priv->mode, (i == DMA_TX_SIZE - 1));
1962 (i == DMA_TX_SIZE - 1));
1963 else1942 else
1964 priv->hw->desc->init_tx_desc(&tx_q->dma_tx[i],1943 stmmac_init_tx_desc(priv, &tx_q->dma_tx[i],
1965 priv->mode,1944 priv->mode, (i == DMA_TX_SIZE - 1));
1966 (i == DMA_TX_SIZE - 1));
1967 tx_q->dirty_tx = 0;1945 tx_q->dirty_tx = 0;
1968 tx_q->cur_tx = 0;1946 tx_q->cur_tx = 0;
1969 tx_q->mss = 0;1947 tx_q->mss = 0;
@@ -2004,30 +1982,30 @@ static void stmmac_set_dma_operation_mode(struct stmmac_priv *priv, u32 txmode, · 34 unmodified lines
2004 txfifosz /= tx_channels_count;1982 txfifosz /= tx_channels_count;
2005 1983
2006 if (priv->synopsys_id >= DWMAC_CORE_4_00) {1984 if (priv->synopsys_id >= DWMAC_CORE_4_00) {
2007 priv->hw->dma->dma_rx_mode(priv->ioaddr, rxmode, chan,1985 stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan, rxfifosz,
2008 rxfifosz, rxqmode);1986 rxqmode);
2009 priv->hw->dma->dma_tx_mode(priv->ioaddr, txmode, chan,1987 stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan, txfifosz,
2010 txfifosz, txqmode);1988 txqmode);
2011 } else {1989 } else {
2012 priv->hw->dma->dma_mode(priv->ioaddr, txmode, rxmode,1990 stmmac_dma_mode(priv, priv->ioaddr, txmode, rxmode, rxfifosz);
2013 rxfifosz);
2014 }1991 }
2015}1992}
2016 1993
2017static bool stmmac_safety_feat_interrupt(struct stmmac_priv *priv)1994static bool stmmac_safety_feat_interrupt(struct stmmac_priv *priv)
2018{1995{
2019 bool ret = false;1996 int ret = false;
2020 1997
2021 /* Safety features are only available in cores >= 5.10 */1998 /* Safety features are only available in cores >= 5.10 */
2022 if (priv->synopsys_id < DWMAC_CORE_5_10)1999 if (priv->synopsys_id < DWMAC_CORE_5_10)
2023 return ret;2000 return ret;
2024 if (priv->hw->mac->safety_feat_irq_status)2001 ret = stmmac_safety_feat_irq_status(priv, priv->dev,
2025 ret = priv->hw->mac->safety_feat_irq_status(priv->dev,2002 priv->ioaddr, priv->dma_cap.asp, &priv->sstats);
2026 priv->ioaddr, priv->dma_cap.asp, &priv->sstats);2003 if (ret && (ret != -EINVAL)) {
2027
2028 if (ret)
2029 stmmac_global_err(priv);2004 stmmac_global_err(priv);
2030 return ret;2005 return true;
2006 }
2007
2008 return false;
2031}2009}
2032 2010
2033/**2011/**
@@ -2054,16 +2032,15 @@ static void stmmac_dma_interrupt(struct stmmac_priv *priv) · 20 unmodified lines
2054 * all tx queues rather than just a single tx queue.2032 * all tx queues rather than just a single tx queue.
2055 */2033 */
2056 for (chan = 0; chan < channels_to_check; chan++)2034 for (chan = 0; chan < channels_to_check; chan++)
2057 status[chan] = priv->hw->dma->dma_interrupt(priv->ioaddr,2035 status[chan] = stmmac_dma_interrupt_status(priv, priv->ioaddr,
2058 &priv->xstats,2036 &priv->xstats, chan);
2059 chan);
2060 2037
2061 for (chan = 0; chan < rx_channel_count; chan++) {2038 for (chan = 0; chan < rx_channel_count; chan++) {
2062 if (likely(status[chan] & handle_rx)) {2039 if (likely(status[chan] & handle_rx)) {
2063 struct stmmac_rx_queue *rx_q = &priv->rx_queue[chan];2040 struct stmmac_rx_queue *rx_q = &priv->rx_queue[chan];
2064 2041
2065 if (likely(napi_schedule_prep(&rx_q->napi))) {2042 if (likely(napi_schedule_prep(&rx_q->napi))) {
2066 stmmac_disable_dma_irq(priv, chan);2043 stmmac_disable_dma_irq(priv, priv->ioaddr, chan);
2067 __napi_schedule(&rx_q->napi);2044 __napi_schedule(&rx_q->napi);
2068 poll_scheduled = true;2045 poll_scheduled = true;
2069 }2046 }
@@ -2084,7 +2061,8 @@ static void stmmac_dma_interrupt(struct stmmac_priv *priv) · 14 unmodified lines
2084 &priv->rx_queue[0];2061 &priv->rx_queue[0];
2085 2062
2086 if (likely(napi_schedule_prep(&rx_q->napi))) {2063 if (likely(napi_schedule_prep(&rx_q->napi))) {
2087 stmmac_disable_dma_irq(priv, chan);2064 stmmac_disable_dma_irq(priv,
2065 priv->ioaddr, chan);
2088 __napi_schedule(&rx_q->napi);2066 __napi_schedule(&rx_q->napi);
2089 }2067 }
2090 break;2068 break;
@@ -2180,15 +2158,7 @@ static void stmmac_selec_desc_mode(struct stmmac_priv *priv) · 89 unmodified lines
2180 */2158 */
2181static int stmmac_get_hw_features(struct stmmac_priv *priv)2159static int stmmac_get_hw_features(struct stmmac_priv *priv)
2182{2160{
2183 u32 ret = 0;2161 return stmmac_get_hw_feature(priv, priv->ioaddr, &priv->dma_cap) == 0;
2184
2185 if (priv->hw->dma->get_hw_feature) {
2186 priv->hw->dma->get_hw_feature(priv->ioaddr,
2187 &priv->dma_cap);
2188 ret = 1;
2189 }
2190
2191 return ret;
2192}2162}
2193 2163
2194/**2164/**
@@ -2201,8 +2171,7 @@ static int stmmac_get_hw_features(struct stmmac_priv *priv) · 6 unmodified lines
2201static void stmmac_check_ether_addr(struct stmmac_priv *priv)2171static void stmmac_check_ether_addr(struct stmmac_priv *priv)
2202{2172{
2203 if (!is_valid_ether_addr(priv->dev->dev_addr)) {2173 if (!is_valid_ether_addr(priv->dev->dev_addr)) {
2204 priv->hw->mac->get_umac_addr(priv->hw,2174 stmmac_get_umac_addr(priv, priv->hw, priv->dev->dev_addr, 0);
2205 priv->dev->dev_addr, 0);
2206 if (!is_valid_ether_addr(priv->dev->dev_addr))2175 if (!is_valid_ether_addr(priv->dev->dev_addr))
2207 eth_hw_addr_random(priv->dev);2176 eth_hw_addr_random(priv->dev);
2208 netdev_info(priv->dev, "device MAC address %pM\n",2177 netdev_info(priv->dev, "device MAC address %pM\n",
@@ -2238,7 +2207,7 @@ static int stmmac_init_dma_engine(struct stmmac_priv *priv) · 29 unmodified lines
2238 if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE))2207 if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE))
2239 atds = 1;2208 atds = 1;
2240 2209
2241 ret = priv->hw->dma->reset(priv->ioaddr);2210 ret = stmmac_reset(priv, priv->ioaddr);
2242 if (ret) {2211 if (ret) {
2243 dev_err(priv->device, "Failed to reset the dma\n");2212 dev_err(priv->device, "Failed to reset the dma\n");
2244 return ret;2213 return ret;
@@ -2246,51 +2215,48 @@ static int stmmac_init_dma_engine(struct stmmac_priv *priv) · 1 unmodified line
2246 2215
2247 if (priv->synopsys_id >= DWMAC_CORE_4_00) {2216 if (priv->synopsys_id >= DWMAC_CORE_4_00) {
2248 /* DMA Configuration */2217 /* DMA Configuration */
2249 priv->hw->dma->init(priv->ioaddr, priv->plat->dma_cfg,2218 stmmac_dma_init(priv, priv->ioaddr, priv->plat->dma_cfg,
2250 dummy_dma_tx_phy, dummy_dma_rx_phy, atds);2219 dummy_dma_tx_phy, dummy_dma_rx_phy, atds);
2251 2220
2252 /* DMA RX Channel Configuration */2221 /* DMA RX Channel Configuration */
2253 for (chan = 0; chan < rx_channels_count; chan++) {2222 for (chan = 0; chan < rx_channels_count; chan++) {
2254 rx_q = &priv->rx_queue[chan];2223 rx_q = &priv->rx_queue[chan];
2255 2224
2256 priv->hw->dma->init_rx_chan(priv->ioaddr,2225 stmmac_init_rx_chan(priv, priv->ioaddr,
2257 priv->plat->dma_cfg,2226 priv->plat->dma_cfg, rx_q->dma_rx_phy,
2258 rx_q->dma_rx_phy, chan);2227 chan);
2259 2228
2260 rx_q->rx_tail_addr = rx_q->dma_rx_phy +2229 rx_q->rx_tail_addr = rx_q->dma_rx_phy +
2261 (DMA_RX_SIZE * sizeof(struct dma_desc));2230 (DMA_RX_SIZE * sizeof(struct dma_desc));
2262 priv->hw->dma->set_rx_tail_ptr(priv->ioaddr,2231 stmmac_set_rx_tail_ptr(priv, priv->ioaddr,
2263 rx_q->rx_tail_addr,2232 rx_q->rx_tail_addr, chan);
2264 chan);
2265 }2233 }
2266 2234
2267 /* DMA TX Channel Configuration */2235 /* DMA TX Channel Configuration */
2268 for (chan = 0; chan < tx_channels_count; chan++) {2236 for (chan = 0; chan < tx_channels_count; chan++) {
2269 tx_q = &priv->tx_queue[chan];2237 tx_q = &priv->tx_queue[chan];
2270 2238
2271 priv->hw->dma->init_chan(priv->ioaddr,2239 stmmac_init_chan(priv, priv->ioaddr,
2272 priv->plat->dma_cfg,2240 priv->plat->dma_cfg, chan);
2273 chan);
2274 2241
2275 priv->hw->dma->init_tx_chan(priv->ioaddr,2242 stmmac_init_tx_chan(priv, priv->ioaddr,
2276 priv->plat->dma_cfg,2243 priv->plat->dma_cfg, tx_q->dma_tx_phy,
2277 tx_q->dma_tx_phy, chan);2244 chan);
2278 2245
2279 tx_q->tx_tail_addr = tx_q->dma_tx_phy +2246 tx_q->tx_tail_addr = tx_q->dma_tx_phy +
2280 (DMA_TX_SIZE * sizeof(struct dma_desc));2247 (DMA_TX_SIZE * sizeof(struct dma_desc));
2281 priv->hw->dma->set_tx_tail_ptr(priv->ioaddr,2248 stmmac_set_tx_tail_ptr(priv, priv->ioaddr,
2282 tx_q->tx_tail_addr,2249 tx_q->tx_tail_addr, chan);
2283 chan);
2284 }2250 }
2285 } else {2251 } else {
2286 rx_q = &priv->rx_queue[chan];2252 rx_q = &priv->rx_queue[chan];
2287 tx_q = &priv->tx_queue[chan];2253 tx_q = &priv->tx_queue[chan];
2288 priv->hw->dma->init(priv->ioaddr, priv->plat->dma_cfg,2254 stmmac_dma_init(priv, priv->ioaddr, priv->plat->dma_cfg,
2289 tx_q->dma_tx_phy, rx_q->dma_rx_phy, atds);2255 tx_q->dma_tx_phy, rx_q->dma_rx_phy, atds);
2290 }2256 }
2291 2257
2292 if (priv->plat->axi && priv->hw->dma->axi)2258 if (priv->plat->axi)
2293 priv->hw->dma->axi(priv->ioaddr, priv->plat->axi);2259 stmmac_axi(priv, priv->ioaddr, priv->plat->axi);
2294 2260
2295 return ret;2261 return ret;
2296}2262}
@@ -2336,18 +2302,14 @@ static void stmmac_set_rings_length(struct stmmac_priv *priv) · 39 unmodified lines
2336 u32 chan;2302 u32 chan;
2337 2303
2338 /* set TX ring length */2304 /* set TX ring length */
2339 if (priv->hw->dma->set_tx_ring_len) {2305 for (chan = 0; chan < tx_channels_count; chan++)
2340 for (chan = 0; chan < tx_channels_count; chan++)2306 stmmac_set_tx_ring_len(priv, priv->ioaddr,
2341 priv->hw->dma->set_tx_ring_len(priv->ioaddr,2307 (DMA_TX_SIZE - 1), chan);
2342 (DMA_TX_SIZE - 1), chan);
2343 }
2344 2308
2345 /* set RX ring length */2309 /* set RX ring length */
2346 if (priv->hw->dma->set_rx_ring_len) {2310 for (chan = 0; chan < rx_channels_count; chan++)
2347 for (chan = 0; chan < rx_channels_count; chan++)2311 stmmac_set_rx_ring_len(priv, priv->ioaddr,
2348 priv->hw->dma->set_rx_ring_len(priv->ioaddr,2312 (DMA_RX_SIZE - 1), chan);
2349 (DMA_RX_SIZE - 1), chan);
2350 }
2351}2313}
2352 2314
2353/**2315/**
@@ -2363,7 +2325,7 @@ static void stmmac_set_tx_queue_weight(struct stmmac_priv *priv) · 9 unmodified lines
2363 2325
2364 for (queue = 0; queue < tx_queues_count; queue++) {2326 for (queue = 0; queue < tx_queues_count; queue++) {
2365 weight = priv->plat->tx_queues_cfg[queue].weight;2327 weight = priv->plat->tx_queues_cfg[queue].weight;
2366 priv->hw->mac->set_mtl_tx_queue_weight(priv->hw, weight, queue);2328 stmmac_set_mtl_tx_queue_weight(priv, priv->hw, weight, queue);
2367 }2329 }
2368}2330}
2369 2331
@@ -2384,7 +2346,7 @@ static void stmmac_configure_cbs(struct stmmac_priv *priv) · 14 unmodified lines
2384 if (mode_to_use == MTL_QUEUE_DCB)2346 if (mode_to_use == MTL_QUEUE_DCB)
2385 continue;2347 continue;
2386 2348
2387 priv->hw->mac->config_cbs(priv->hw,2349 stmmac_config_cbs(priv, priv->hw,
2388 priv->plat->tx_queues_cfg[queue].send_slope,2350 priv->plat->tx_queues_cfg[queue].send_slope,
2389 priv->plat->tx_queues_cfg[queue].idle_slope,2351 priv->plat->tx_queues_cfg[queue].idle_slope,
2390 priv->plat->tx_queues_cfg[queue].high_credit,2352 priv->plat->tx_queues_cfg[queue].high_credit,
@@ -2406,7 +2368,7 @@ static void stmmac_rx_queue_dma_chan_map(struct stmmac_priv *priv) · 15 unmodified lines
2406 2368
2407 for (queue = 0; queue < rx_queues_count; queue++) {2369 for (queue = 0; queue < rx_queues_count; queue++) {
2408 chan = priv->plat->rx_queues_cfg[queue].chan;2370 chan = priv->plat->rx_queues_cfg[queue].chan;
2409 priv->hw->mac->map_mtl_to_dma(priv->hw, queue, chan);2371 stmmac_map_mtl_to_dma(priv, priv->hw, queue, chan);
2410 }2372 }
2411}2373}
2412 2374
@@ -2426,7 +2388,7 @@ static void stmmac_mac_config_rx_queues_prio(struct stmmac_priv *priv) · 13 unmodified lines
2426 continue;2388 continue;
2427 2389
2428 prio = priv->plat->rx_queues_cfg[queue].prio;2390 prio = priv->plat->rx_queues_cfg[queue].prio;
2429 priv->hw->mac->rx_queue_prio(priv->hw, prio, queue);2391 stmmac_rx_queue_prio(priv, priv->hw, prio, queue);
2430 }2392 }
2431}2393}
2432 2394
@@ -2446,7 +2408,7 @@ static void stmmac_mac_config_tx_queues_prio(struct stmmac_priv *priv) · 13 unmodified lines
2446 continue;2408 continue;
2447 2409
2448 prio = priv->plat->tx_queues_cfg[queue].prio;2410 prio = priv->plat->tx_queues_cfg[queue].prio;
2449 priv->hw->mac->tx_queue_prio(priv->hw, prio, queue);2411 stmmac_tx_queue_prio(priv, priv->hw, prio, queue);
2450 }2412 }
2451}2413}
2452 2414
@@ -2467,7 +2429,7 @@ static void stmmac_mac_config_rx_queues_routing(struct stmmac_priv *priv) · 14 unmodified lines
2467 continue;2429 continue;
2468 2430
2469 packet = priv->plat->rx_queues_cfg[queue].pkt_route;2431 packet = priv->plat->rx_queues_cfg[queue].pkt_route;
2470 priv->hw->mac->rx_queue_routing(priv->hw, packet, queue);2432 stmmac_rx_queue_routing(priv, priv->hw, packet, queue);
2471 }2433 }
2472}2434}
2473 2435
@@ -2481,50 +2443,47 @@ static void stmmac_mtl_configuration(struct stmmac_priv *priv) · 7 unmodified lines
2481 u32 rx_queues_count = priv->plat->rx_queues_to_use;2443 u32 rx_queues_count = priv->plat->rx_queues_to_use;
2482 u32 tx_queues_count = priv->plat->tx_queues_to_use;2444 u32 tx_queues_count = priv->plat->tx_queues_to_use;
2483 2445
2484 if (tx_queues_count > 1 && priv->hw->mac->set_mtl_tx_queue_weight)2446 if (tx_queues_count > 1)
2485 stmmac_set_tx_queue_weight(priv);2447 stmmac_set_tx_queue_weight(priv);
2486 2448
2487 /* Configure MTL RX algorithms */2449 /* Configure MTL RX algorithms */
2488 if (rx_queues_count > 1 && priv->hw->mac->prog_mtl_rx_algorithms)2450 if (rx_queues_count > 1)
2489 priv->hw->mac->prog_mtl_rx_algorithms(priv->hw,2451 stmmac_prog_mtl_rx_algorithms(priv, priv->hw,
2490 priv->plat->rx_sched_algorithm);2452 priv->plat->rx_sched_algorithm);
2491 2453
2492 /* Configure MTL TX algorithms */2454 /* Configure MTL TX algorithms */
2493 if (tx_queues_count > 1 && priv->hw->mac->prog_mtl_tx_algorithms)2455 if (tx_queues_count > 1)
2494 priv->hw->mac->prog_mtl_tx_algorithms(priv->hw,2456 stmmac_prog_mtl_tx_algorithms(priv, priv->hw,
2495 priv->plat->tx_sched_algorithm);2457 priv->plat->tx_sched_algorithm);
2496 2458
2497 /* Configure CBS in AVB TX queues */2459 /* Configure CBS in AVB TX queues */
2498 if (tx_queues_count > 1 && priv->hw->mac->config_cbs)2460 if (tx_queues_count > 1)
2499 stmmac_configure_cbs(priv);2461 stmmac_configure_cbs(priv);
2500 2462
2501 /* Map RX MTL to DMA channels */2463 /* Map RX MTL to DMA channels */
2502 if (priv->hw->mac->map_mtl_to_dma)2464 stmmac_rx_queue_dma_chan_map(priv);
2503 stmmac_rx_queue_dma_chan_map(priv);
2504 2465
2505 /* Enable MAC RX Queues */2466 /* Enable MAC RX Queues */
2506 if (priv->hw->mac->rx_queue_enable)2467 stmmac_mac_enable_rx_queues(priv);
2507 stmmac_mac_enable_rx_queues(priv);
2508 2468
2509 /* Set RX priorities */2469 /* Set RX priorities */
2510 if (rx_queues_count > 1 && priv->hw->mac->rx_queue_prio)2470 if (rx_queues_count > 1)
2511 stmmac_mac_config_rx_queues_prio(priv);2471 stmmac_mac_config_rx_queues_prio(priv);
2512 2472
2513 /* Set TX priorities */2473 /* Set TX priorities */
2514 if (tx_queues_count > 1 && priv->hw->mac->tx_queue_prio)2474 if (tx_queues_count > 1)
2515 stmmac_mac_config_tx_queues_prio(priv);2475 stmmac_mac_config_tx_queues_prio(priv);
2516 2476
2517 /* Set RX routing */2477 /* Set RX routing */
2518 if (rx_queues_count > 1 && priv->hw->mac->rx_queue_routing)2478 if (rx_queues_count > 1)
2519 stmmac_mac_config_rx_queues_routing(priv);2479 stmmac_mac_config_rx_queues_routing(priv);
2520}2480}
2521 2481
2522static void stmmac_safety_feat_configuration(struct stmmac_priv *priv)2482static void stmmac_safety_feat_configuration(struct stmmac_priv *priv)
2523{2483{
2524 if (priv->hw->mac->safety_feat_config && priv->dma_cap.asp) {2484 if (priv->dma_cap.asp) {
2525 netdev_info(priv->dev, "Enabling Safety Features\n");2485 netdev_info(priv->dev, "Enabling Safety Features\n");
2526 priv->hw->mac->safety_feat_config(priv->ioaddr,2486 stmmac_safety_feat_config(priv, priv->ioaddr, priv->dma_cap.asp);
2527 priv->dma_cap.asp);
2528 } else {2487 } else {
2529 netdev_info(priv->dev, "No Safety Features support found\n");2488 netdev_info(priv->dev, "No Safety Features support found\n");
2530 }2489 }
@@ -2559,7 +2518,7 @@ static int stmmac_hw_setup(struct net_device *dev, bool init_ptp) · 28 unmodified lines
2559 }2518 }
2560 2519
2561 /* Copy the MAC addr into the HW */2520 /* Copy the MAC addr into the HW */
2562 priv->hw->mac->set_umac_addr(priv->hw, dev->dev_addr, 0);2521 stmmac_set_umac_addr(priv, priv->hw, dev->dev_addr, 0);
2563 2522
2564 /* PS and related bits will be programmed according to the speed */2523 /* PS and related bits will be programmed according to the speed */
2565 if (priv->hw->pcs) {2524 if (priv->hw->pcs) {
@@ -2575,7 +2534,7 @@ static int stmmac_hw_setup(struct net_device *dev, bool init_ptp) · 9 unmodified lines
2575 }2534 }
2576 2535
2577 /* Initialize the MAC Core */2536 /* Initialize the MAC Core */
2578 priv->hw->mac->core_init(priv->hw, dev);2537 stmmac_core_init(priv, priv->hw, dev);
2579 2538
2580 /* Initialize MTL*/2539 /* Initialize MTL*/
2581 if (priv->synopsys_id >= DWMAC_CORE_4_00)2540 if (priv->synopsys_id >= DWMAC_CORE_4_00)
@@ -2585,7 +2544,7 @@ static int stmmac_hw_setup(struct net_device *dev, bool init_ptp) · 3 unmodified lines
2585 if (priv->synopsys_id >= DWMAC_CORE_5_10)2544 if (priv->synopsys_id >= DWMAC_CORE_5_10)
2586 stmmac_safety_feat_configuration(priv);2545 stmmac_safety_feat_configuration(priv);
2587 2546
2588 ret = priv->hw->mac->rx_ipc(priv->hw);2547 ret = stmmac_rx_ipc(priv, priv->hw);
2589 if (!ret) {2548 if (!ret) {
2590 netdev_warn(priv->dev, "RX IPC Checksum Offload disabled\n");2549 netdev_warn(priv->dev, "RX IPC Checksum Offload disabled\n");
2591 priv->plat->rx_coe = STMMAC_RX_COE_NONE;2550 priv->plat->rx_coe = STMMAC_RX_COE_NONE;
@@ -2593,7 +2552,7 @@ static int stmmac_hw_setup(struct net_device *dev, bool init_ptp) · 1 unmodified line
2593 }2552 }
2594 2553
2595 /* Enable the MAC Rx/Tx */2554 /* Enable the MAC Rx/Tx */
2596 priv->hw->mac->set_mac(priv->ioaddr, true);2555 stmmac_mac_set(priv, priv->ioaddr, true);
2597 2556
2598 /* Set the HW DMA mode and the COE */2557 /* Set the HW DMA mode and the COE */
2599 stmmac_dma_operation_mode(priv);2558 stmmac_dma_operation_mode(priv);
@@ -2623,13 +2582,14 @@ static int stmmac_hw_setup(struct net_device *dev, bool init_ptp) · 23 unmodified lines
2623 2582
2624 priv->tx_lpi_timer = STMMAC_DEFAULT_TWT_LS;2583 priv->tx_lpi_timer = STMMAC_DEFAULT_TWT_LS;
2625 2584
2626 if ((priv->use_riwt) && (priv->hw->dma->rx_watchdog)) {2585 if (priv->use_riwt) {
2627 priv->rx_riwt = MAX_DMA_RIWT;2586 ret = stmmac_rx_watchdog(priv, priv->ioaddr, MAX_DMA_RIWT, rx_cnt);
2628 priv->hw->dma->rx_watchdog(priv->ioaddr, MAX_DMA_RIWT, rx_cnt);2587 if (!ret)
2588 priv->rx_riwt = MAX_DMA_RIWT;
2629 }2589 }
2630 2590
2631 if (priv->hw->pcs && priv->hw->mac->pcs_ctrl_ane)2591 if (priv->hw->pcs)
2632 priv->hw->mac->pcs_ctrl_ane(priv->hw, 1, priv->hw->ps, 0);2592 stmmac_pcs_ctrl_ane(priv, priv->hw, 1, priv->hw->ps, 0);
2633 2593
2634 /* set TX and RX rings length */2594 /* set TX and RX rings length */
2635 stmmac_set_rings_length(priv);2595 stmmac_set_rings_length(priv);
@@ -2637,7 +2597,7 @@ static int stmmac_hw_setup(struct net_device *dev, bool init_ptp) · 1 unmodified line
2637 /* Enable TSO */2597 /* Enable TSO */
2638 if (priv->tso) {2598 if (priv->tso) {
2639 for (chan = 0; chan < tx_cnt; chan++)2599 for (chan = 0; chan < tx_cnt; chan++)
2640 priv->hw->dma->enable_tso(priv->ioaddr, 1, chan);2600 stmmac_enable_tso(priv, priv->ioaddr, 1, chan);
2641 }2601 }
2642 2602
2643 return 0;2603 return 0;
@@ -2808,7 +2768,7 @@ static int stmmac_release(struct net_device *dev) · 164 unmodified lines
2808 free_dma_desc_resources(priv);2768 free_dma_desc_resources(priv);
2809 2769
2810 /* Disable the MAC Rx/Tx */2770 /* Disable the MAC Rx/Tx */
2811 priv->hw->mac->set_mac(priv->ioaddr, false);2771 stmmac_mac_set(priv, priv->ioaddr, false);
2812 2772
2813 netif_carrier_off(dev);2773 netif_carrier_off(dev);
2814 2774
@@ -2851,10 +2811,10 @@ static void stmmac_tso_allocator(struct stmmac_priv *priv, unsigned int des, · 36 unmodified lines
2851 buff_size = tmp_len >= TSO_MAX_BUFF_SIZE ?2811 buff_size = tmp_len >= TSO_MAX_BUFF_SIZE ?
2852 TSO_MAX_BUFF_SIZE : tmp_len;2812 TSO_MAX_BUFF_SIZE : tmp_len;
2853 2813
2854 priv->hw->desc->prepare_tso_tx_desc(desc, 0, buff_size,2814 stmmac_prepare_tso_tx_desc(priv, desc, 0, buff_size,
2855 0, 1,2815 0, 1,
2856 (last_segment) && (tmp_len <= TSO_MAX_BUFF_SIZE),2816 (last_segment) && (tmp_len <= TSO_MAX_BUFF_SIZE),
2857 0, 0);2817 0, 0);
2858 2818
2859 tmp_len -= TSO_MAX_BUFF_SIZE;2819 tmp_len -= TSO_MAX_BUFF_SIZE;
2860 }2820 }
@@ -2926,7 +2886,7 @@ static netdev_tx_t stmmac_tso_xmit(struct sk_buff *skb, struct net_device *dev) · 65 unmodified lines
2926 /* set new MSS value if needed */2886 /* set new MSS value if needed */
2927 if (mss != tx_q->mss) {2887 if (mss != tx_q->mss) {
2928 mss_desc = tx_q->dma_tx + tx_q->cur_tx;2888 mss_desc = tx_q->dma_tx + tx_q->cur_tx;
2929 priv->hw->desc->set_mss(mss_desc, mss);2889 stmmac_set_mss(priv, mss_desc, mss);
2930 tx_q->mss = mss;2890 tx_q->mss = mss;
2931 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, DMA_TX_SIZE);2891 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, DMA_TX_SIZE);
2932 WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]);2892 WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]);
@@ -3012,7 +2972,7 @@ static netdev_tx_t stmmac_tso_xmit(struct sk_buff *skb, struct net_device *dev) · 79 unmodified lines
3012 STMMAC_COAL_TIMER(priv->tx_coal_timer));2972 STMMAC_COAL_TIMER(priv->tx_coal_timer));
3013 } else {2973 } else {
3014 priv->tx_count_frames = 0;2974 priv->tx_count_frames = 0;
3015 priv->hw->desc->set_tx_ic(desc);2975 stmmac_set_tx_ic(priv, desc);
3016 priv->xstats.tx_set_ic_bit++;2976 priv->xstats.tx_set_ic_bit++;
3017 }2977 }
3018 2978
@@ -3022,11 +2982,11 @@ static netdev_tx_t stmmac_tso_xmit(struct sk_buff *skb, struct net_device *dev) · 3 unmodified lines
3022 priv->hwts_tx_en)) {2982 priv->hwts_tx_en)) {
3023 /* declare that device is doing timestamping */2983 /* declare that device is doing timestamping */
3024 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;2984 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
3025 priv->hw->desc->enable_tx_timestamp(first);2985 stmmac_enable_tx_timestamp(priv, first);
3026 }2986 }
3027 2987
3028 /* Complete the first descriptor before granting the DMA */2988 /* Complete the first descriptor before granting the DMA */
3029 priv->hw->desc->prepare_tso_tx_desc(first, 1,2989 stmmac_prepare_tso_tx_desc(priv, first, 1,
3030 proto_hdr_len,2990 proto_hdr_len,
3031 pay_len,2991 pay_len,
3032 1, tx_q->tx_skbuff_dma[first_entry].last_segment,2992 1, tx_q->tx_skbuff_dma[first_entry].last_segment,
@@ -3040,7 +3000,7 @@ static netdev_tx_t stmmac_tso_xmit(struct sk_buff *skb, struct net_device *dev) · 7 unmodified lines
3040 * sure that MSS's own bit is the last thing written.3000 * sure that MSS's own bit is the last thing written.
3041 */3001 */
3042 dma_wmb();3002 dma_wmb();
3043 priv->hw->desc->set_tx_owner(mss_desc);3003 stmmac_set_tx_owner(priv, mss_desc);
3044 }3004 }
3045 3005
3046 /* The own bit must be the latest setting done when prepare the3006 /* The own bit must be the latest setting done when prepare the
@@ -3054,8 +3014,7 @@ static netdev_tx_t stmmac_tso_xmit(struct sk_buff *skb, struct net_device *dev) · 7 unmodified lines
3054 __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry,3014 __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry,
3055 tx_q->cur_tx, first, nfrags);3015 tx_q->cur_tx, first, nfrags);
3056 3016
3057 priv->hw->desc->display_ring((void *)tx_q->dma_tx, DMA_TX_SIZE,3017 stmmac_display_ring(priv, (void *)tx_q->dma_tx, DMA_TX_SIZE, 0);
3058 0);
3059 3018
3060 pr_info(">>> frame to be transmitted: ");3019 pr_info(">>> frame to be transmitted: ");
3061 print_pkt(skb->data, skb_headlen(skb));3020 print_pkt(skb->data, skb_headlen(skb));
@@ -3063,8 +3022,7 @@ static netdev_tx_t stmmac_tso_xmit(struct sk_buff *skb, struct net_device *dev) · 1 unmodified line
3063 3022
3064 netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len);3023 netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len);
3065 3024
3066 priv->hw->dma->set_tx_tail_ptr(priv->ioaddr, tx_q->tx_tail_addr,3025 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, tx_q->tx_tail_addr, queue);
3067 queue);
3068 3026
3069 return NETDEV_TX_OK;3027 return NETDEV_TX_OK;
3070 3028
@@ -3136,11 +3094,11 @@ static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev) · 65 unmodified lines
3136 enh_desc = priv->plat->enh_desc;3094 enh_desc = priv->plat->enh_desc;
3137 /* To program the descriptors according to the size of the frame */3095 /* To program the descriptors according to the size of the frame */
3138 if (enh_desc)3096 if (enh_desc)
3139 is_jumbo = priv->hw->mode->is_jumbo_frm(skb->len, enh_desc);3097 is_jumbo = stmmac_is_jumbo_frm(priv, skb->len, enh_desc);
3140 3098
3141 if (unlikely(is_jumbo) && likely(priv->synopsys_id <3099 if (unlikely(is_jumbo) && likely(priv->synopsys_id <
3142 DWMAC_CORE_4_00)) {3100 DWMAC_CORE_4_00)) {
3143 entry = priv->hw->mode->jumbo_frm(tx_q, skb, csum_insertion);3101 entry = stmmac_jumbo_frm(priv, tx_q, skb, csum_insertion);
3144 if (unlikely(entry < 0))3102 if (unlikely(entry < 0))
3145 goto dma_map_err;3103 goto dma_map_err;
3146 }3104 }
@@ -3174,9 +3132,8 @@ static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev) · 27 unmodified lines
3174 tx_q->tx_skbuff_dma[entry].last_segment = last_segment;3132 tx_q->tx_skbuff_dma[entry].last_segment = last_segment;
3175 3133
3176 /* Prepare the descriptor and set the own bit too */3134 /* Prepare the descriptor and set the own bit too */
3177 priv->hw->desc->prepare_tx_desc(desc, 0, len, csum_insertion,3135 stmmac_prepare_tx_desc(priv, desc, 0, len, csum_insertion,
3178 priv->mode, 1, last_segment,3136 priv->mode, 1, last_segment, skb->len);
3179 skb->len);
3180 }3137 }
3181 3138
3182 /* Only the last descriptor gets to point to the skb. */3139 /* Only the last descriptor gets to point to the skb. */
@@ -3203,7 +3160,7 @@ static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev) · 20 unmodified lines
3203 else3160 else
3204 tx_head = (void *)tx_q->dma_tx;3161 tx_head = (void *)tx_q->dma_tx;
3205 3162
3206 priv->hw->desc->display_ring(tx_head, DMA_TX_SIZE, false);3163 stmmac_display_ring(priv, tx_head, DMA_TX_SIZE, false);
3207 3164
3208 netdev_dbg(priv->dev, ">>> frame to be transmitted: ");3165 netdev_dbg(priv->dev, ">>> frame to be transmitted: ");
3209 print_pkt(skb->data, skb->len);3166 print_pkt(skb->data, skb->len);
@@ -3228,7 +3185,7 @@ static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev) · 18 unmodified lines
3228 STMMAC_COAL_TIMER(priv->tx_coal_timer));3185 STMMAC_COAL_TIMER(priv->tx_coal_timer));
3229 } else {3186 } else {
3230 priv->tx_count_frames = 0;3187 priv->tx_count_frames = 0;
3231 priv->hw->desc->set_tx_ic(desc);3188 stmmac_set_tx_ic(priv, desc);
3232 priv->xstats.tx_set_ic_bit++;3189 priv->xstats.tx_set_ic_bit++;
3233 }3190 }
3234 3191
@@ -3259,13 +3216,13 @@ static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev) · 24 unmodified lines
3259 priv->hwts_tx_en)) {3216 priv->hwts_tx_en)) {
3260 /* declare that device is doing timestamping */3217 /* declare that device is doing timestamping */
3261 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;3218 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
3262 priv->hw->desc->enable_tx_timestamp(first);3219 stmmac_enable_tx_timestamp(priv, first);
3263 }3220 }
3264 3221
3265 /* Prepare the first descriptor setting the OWN bit too */3222 /* Prepare the first descriptor setting the OWN bit too */
3266 priv->hw->desc->prepare_tx_desc(first, 1, nopaged_len,3223 stmmac_prepare_tx_desc(priv, first, 1, nopaged_len,
3267 csum_insertion, priv->mode, 1,3224 csum_insertion, priv->mode, 1, last_segment,
3268 last_segment, skb->len);3225 skb->len);
3269 3226
3270 /* The own bit must be the latest setting done when prepare the3227 /* The own bit must be the latest setting done when prepare the
3271 * descriptor and then barrier is needed to make sure that3228 * descriptor and then barrier is needed to make sure that
@@ -3277,10 +3234,10 @@ static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev) · 5 unmodified lines
3277 netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len);3234 netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len);
3278 3235
3279 if (priv->synopsys_id < DWMAC_CORE_4_00)3236 if (priv->synopsys_id < DWMAC_CORE_4_00)
3280 priv->hw->dma->enable_dma_transmission(priv->ioaddr);3237 stmmac_enable_dma_transmission(priv, priv->ioaddr);
3281 else3238 else
3282 priv->hw->dma->set_tx_tail_ptr(priv->ioaddr, tx_q->tx_tail_addr,3239 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, tx_q->tx_tail_addr,
3283 queue);3240 queue);
3284 3241
3285 return NETDEV_TX_OK;3242 return NETDEV_TX_OK;
3286 3243
@@ -3370,8 +3327,8 @@ static inline void stmmac_rx_refill(struct stmmac_priv *priv, u32 queue) · 83 unmodified lines
3370 } else {3327 } else {
3371 p->des2 = cpu_to_le32(rx_q->rx_skbuff_dma[entry]);3328 p->des2 = cpu_to_le32(rx_q->rx_skbuff_dma[entry]);
3372 }3329 }
3373 if (priv->hw->mode->refill_desc3)3330
3374 priv->hw->mode->refill_desc3(rx_q, p);3331 stmmac_refill_desc3(priv, rx_q, p);
3375 3332
3376 if (rx_q->rx_zeroc_thresh > 0)3333 if (rx_q->rx_zeroc_thresh > 0)
3377 rx_q->rx_zeroc_thresh--;3334 rx_q->rx_zeroc_thresh--;
@@ -3382,9 +3339,9 @@ static inline void stmmac_rx_refill(struct stmmac_priv *priv, u32 queue) · 4 unmodified lines
3382 dma_wmb();3339 dma_wmb();
3383 3340
3384 if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00))3341 if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00))
3385 priv->hw->desc->init_rx_desc(p, priv->use_riwt, 0, 0);3342 stmmac_init_rx_desc(priv, p, priv->use_riwt, 0, 0);
3386 else3343 else
3387 priv->hw->desc->set_rx_owner(p);3344 stmmac_set_rx_owner(priv, p);
3388 3345
3389 dma_wmb();3346 dma_wmb();
3390 3347
@@ -3418,7 +3375,7 @@ static int stmmac_rx(struct stmmac_priv *priv, int limit, u32 queue) · 27 unmodified lines
3418 else3375 else
3419 rx_head = (void *)rx_q->dma_rx;3376 rx_head = (void *)rx_q->dma_rx;
3420 3377
3421 priv->hw->desc->display_ring(rx_head, DMA_RX_SIZE, true);3378 stmmac_display_ring(priv, rx_head, DMA_RX_SIZE, true);
3422 }3379 }
3423 while (count < limit) {3380 while (count < limit) {
3424 int status;3381 int status;
@@ -3431,8 +3388,8 @@ static int stmmac_rx(struct stmmac_priv *priv, int limit, u32 queue) · 6 unmodified lines
3431 p = rx_q->dma_rx + entry;3388 p = rx_q->dma_rx + entry;
3432 3389
3433 /* read the status of the incoming frame */3390 /* read the status of the incoming frame */
3434 status = priv->hw->desc->rx_status(&priv->dev->stats,3391 status = stmmac_rx_status(priv, &priv->dev->stats,
3435 &priv->xstats, p);3392 &priv->xstats, p);
3436 /* check if managed by the DMA otherwise go ahead */3393 /* check if managed by the DMA otherwise go ahead */
3437 if (unlikely(status & dma_own))3394 if (unlikely(status & dma_own))
3438 break;3395 break;
@@ -3449,11 +3406,9 @@ static int stmmac_rx(struct stmmac_priv *priv, int limit, u32 queue) · 10 unmodified lines
3449 3406
3450 prefetch(np);3407 prefetch(np);
3451 3408
3452 if ((priv->extend_desc) && (priv->hw->desc->rx_extended_status))3409 if (priv->extend_desc)
3453 priv->hw->desc->rx_extended_status(&priv->dev->stats,3410 stmmac_rx_extended_status(priv, &priv->dev->stats,
3454 &priv->xstats,3411 &priv->xstats, rx_q->dma_erx + entry);
3455 rx_q->dma_erx +
3456 entry);
3457 if (unlikely(status == discard_frame)) {3412 if (unlikely(status == discard_frame)) {
3458 priv->dev->stats.rx_errors++;3413 priv->dev->stats.rx_errors++;
3459 if (priv->hwts_rx_en && !priv->extend_desc) {3414 if (priv->hwts_rx_en && !priv->extend_desc) {
@@ -3479,7 +3434,7 @@ static int stmmac_rx(struct stmmac_priv *priv, int limit, u32 queue) · 19 unmodified lines
3479 else3434 else
3480 des = le32_to_cpu(p->des2);3435 des = le32_to_cpu(p->des2);
3481 3436
3482 frame_len = priv->hw->desc->get_rx_frame_len(p, coe);3437 frame_len = stmmac_get_rx_frame_len(priv, p, coe);
3483 3438
3484 /* If frame length is greater than skb buffer size3439 /* If frame length is greater than skb buffer size
3485 * (preallocated during init) then the packet is3440 * (preallocated during init) then the packet is
@@ -3616,7 +3571,7 @@ static int stmmac_poll(struct napi_struct *napi, int budget) · 130 unmodified lines
3616 work_done = stmmac_rx(priv, budget, rx_q->queue_index);3571 work_done = stmmac_rx(priv, budget, rx_q->queue_index);
3617 if (work_done < budget) {3572 if (work_done < budget) {
3618 napi_complete_done(napi, work_done);3573 napi_complete_done(napi, work_done);
3619 stmmac_enable_dma_irq(priv, chan);3574 stmmac_enable_dma_irq(priv, priv->ioaddr, chan);
3620 }3575 }
3621 return work_done;3576 return work_done;
3622}3577}
@@ -3649,7 +3604,7 @@ static void stmmac_set_rx_mode(struct net_device *dev) · 26 unmodified lines
3649{3604{
3650 struct stmmac_priv *priv = netdev_priv(dev);3605 struct stmmac_priv *priv = netdev_priv(dev);
3651 3606
3652 priv->hw->mac->set_filter(priv->hw, dev);3607 stmmac_set_filter(priv, priv->hw, dev);
3653}3608}
3654 3609
3655/**3610/**
@@ -3722,7 +3677,7 @@ static int stmmac_set_features(struct net_device *netdev, · 66 unmodified lines
3722 /* No check needed because rx_coe has been set before and it will be3677 /* No check needed because rx_coe has been set before and it will be
3723 * fixed in case of issue.3678 * fixed in case of issue.
3724 */3679 */
3725 priv->hw->mac->rx_ipc(priv->hw);3680 stmmac_rx_ipc(priv, priv->hw);
3726 3681
3727 return 0;3682 return 0;
3728}3683}
@@ -3766,8 +3721,7 @@ static irqreturn_t stmmac_interrupt(int irq, void *dev_id) · 37 unmodified lines
3766 3721
3767 /* To handle GMAC own interrupts */3722 /* To handle GMAC own interrupts */
3768 if ((priv->plat->has_gmac) || (priv->plat->has_gmac4)) {3723 if ((priv->plat->has_gmac) || (priv->plat->has_gmac4)) {
3769 int status = priv->hw->mac->host_irq_status(priv->hw,3724 int status = stmmac_host_irq_status(priv, priv->hw, &priv->xstats);
3770 &priv->xstats);
3771 3725
3772 if (unlikely(status)) {3726 if (unlikely(status)) {
3773 /* For LPI we need to save the tx status */3727 /* For LPI we need to save the tx status */
@@ -3782,15 +3736,14 @@ static irqreturn_t stmmac_interrupt(int irq, void *dev_id) · 8 unmodified lines
3782 struct stmmac_rx_queue *rx_q =3736 struct stmmac_rx_queue *rx_q =
3783 &priv->rx_queue[queue];3737 &priv->rx_queue[queue];
3784 3738
3785 status |=3739 status |= stmmac_host_mtl_irq_status(priv,
3786 priv->hw->mac->host_mtl_irq_status(priv->hw,3740 priv->hw, queue);
3787 queue);
3788 3741
3789 if (status & CORE_IRQ_MTL_RX_OVERFLOW &&3742 if (status & CORE_IRQ_MTL_RX_OVERFLOW)
3790 priv->hw->dma->set_rx_tail_ptr)3743 stmmac_set_rx_tail_ptr(priv,
3791 priv->hw->dma->set_rx_tail_ptr(priv->ioaddr,3744 priv->ioaddr,
3792 rx_q->rx_tail_addr,3745 rx_q->rx_tail_addr,
3793 queue);3746 queue);
3794 }3747 }
3795 }3748 }
3796 3749
@@ -3864,7 +3817,7 @@ static int stmmac_set_mac_address(struct net_device *ndev, void *addr) · 67 unmodified lines
3864 if (ret)3817 if (ret)
3865 return ret;3818 return ret;
3866 3819
3867 priv->hw->mac->set_umac_addr(priv->hw, ndev->dev_addr, 0);3820 stmmac_set_umac_addr(priv, priv->hw, ndev->dev_addr, 0);
3868 3821
3869 return ret;3822 return ret;
3870}3823}
@@ -4453,7 +4406,7 @@ int stmmac_dvr_remove(struct device *dev) · 582 unmodified lines
4453 4406
4454 stmmac_stop_all_dma(priv);4407 stmmac_stop_all_dma(priv);
4455 4408
4456 priv->hw->mac->set_mac(priv->ioaddr, false);4409 stmmac_mac_set(priv, priv->ioaddr, false);
4457 netif_carrier_off(ndev);4410 netif_carrier_off(ndev);
4458 unregister_netdev(ndev);4411 unregister_netdev(ndev);
4459 if (priv->plat->stmmac_rst)4412 if (priv->plat->stmmac_rst)
@@ -4502,10 +4455,10 @@ int stmmac_suspend(struct device *dev) · 42 unmodified lines
4502 4455
4503 /* Enable Power down mode by programming the PMT regs */4456 /* Enable Power down mode by programming the PMT regs */
4504 if (device_may_wakeup(priv->device)) {4457 if (device_may_wakeup(priv->device)) {
4505 priv->hw->mac->pmt(priv->hw, priv->wolopts);4458 stmmac_pmt(priv, priv->hw, priv->wolopts);
4506 priv->irq_wake = 1;4459 priv->irq_wake = 1;
4507 } else {4460 } else {
4508 priv->hw->mac->set_mac(priv->ioaddr, false);4461 stmmac_mac_set(priv, priv->ioaddr, false);
4509 pinctrl_pm_select_sleep_state(priv->device);4462 pinctrl_pm_select_sleep_state(priv->device);
4510 /* Disable clock in case of PWM is off */4463 /* Disable clock in case of PWM is off */
4511 clk_disable(priv->plat->pclk);4464 clk_disable(priv->plat->pclk);
@@ -4569,7 +4522,7 @@ int stmmac_resume(struct device *dev) · 57 unmodified lines
4569 */4522 */
4570 if (device_may_wakeup(priv->device)) {4523 if (device_may_wakeup(priv->device)) {
4571 spin_lock_irqsave(&priv->lock, flags);4524 spin_lock_irqsave(&priv->lock, flags);
4572 priv->hw->mac->pmt(priv->hw, 0);4525 stmmac_pmt(priv, priv->hw, 0);
4573 spin_unlock_irqrestore(&priv->lock, flags);4526 spin_unlock_irqrestore(&priv->lock, flags);
4574 priv->irq_wake = 0;4527 priv->irq_wake = 0;
4575 } else {4528 } else {
drivers/net/ethernet/stmicro/stmmac/stmmac_ptp.c+5−13
@@ -49,9 +49,7 @@ static int stmmac_adjust_freq(struct ptp_clock_info *ptp, s32 ppb) · 48 unmodified lines
49 addend = neg_adj ? (addend - diff) : (addend + diff);49 addend = neg_adj ? (addend - diff) : (addend + diff);
50 50
51 spin_lock_irqsave(&priv->ptp_lock, flags);51 spin_lock_irqsave(&priv->ptp_lock, flags);
52 52 stmmac_config_addend(priv, priv->ptpaddr, addend);
53 priv->hw->ptp->config_addend(priv->ptpaddr, addend);
54
55 spin_unlock_irqrestore(&priv->ptp_lock, flags);53 spin_unlock_irqrestore(&priv->ptp_lock, flags);
56 54
57 return 0;55 return 0;
@@ -84,10 +82,8 @@ static int stmmac_adjust_time(struct ptp_clock_info *ptp, s64 delta) · 26 unmodified lines
84 nsec = reminder;82 nsec = reminder;
85 83
86 spin_lock_irqsave(&priv->ptp_lock, flags);84 spin_lock_irqsave(&priv->ptp_lock, flags);
87 85 stmmac_adjust_systime(priv, priv->ptpaddr, sec, nsec, neg_adj,
88 priv->hw->ptp->adjust_systime(priv->ptpaddr, sec, nsec, neg_adj,86 priv->plat->has_gmac4);
89 priv->plat->has_gmac4);
90
91 spin_unlock_irqrestore(&priv->ptp_lock, flags);87 spin_unlock_irqrestore(&priv->ptp_lock, flags);
92 88
93 return 0;89 return 0;
@@ -110,9 +106,7 @@ static int stmmac_get_time(struct ptp_clock_info *ptp, struct timespec64 *ts) · 16 unmodified lines
110 u64 ns;106 u64 ns;
111 107
112 spin_lock_irqsave(&priv->ptp_lock, flags);108 spin_lock_irqsave(&priv->ptp_lock, flags);
113 109 stmmac_get_systime(priv, priv->ptpaddr, &ns);
114 ns = priv->hw->ptp->get_systime(priv->ptpaddr);
115
116 spin_unlock_irqrestore(&priv->ptp_lock, flags);110 spin_unlock_irqrestore(&priv->ptp_lock, flags);
117 111
118 *ts = ns_to_timespec64(ns);112 *ts = ns_to_timespec64(ns);
@@ -137,9 +131,7 @@ static int stmmac_set_time(struct ptp_clock_info *ptp, · 18 unmodified lines
137 unsigned long flags;131 unsigned long flags;
138 132
139 spin_lock_irqsave(&priv->ptp_lock, flags);133 spin_lock_irqsave(&priv->ptp_lock, flags);
140 134 stmmac_init_systime(priv, priv->ptpaddr, ts->tv_sec, ts->tv_nsec);
141 priv->hw->ptp->init_systime(priv->ptpaddr, ts->tv_sec, ts->tv_nsec);
142
143 spin_unlock_irqrestore(&priv->ptp_lock, flags);135 spin_unlock_irqrestore(&priv->ptp_lock, flags);
144 136
145 return 0;137 return 0;