Merge tag 'soc-fixes-6.9-2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull ARM SoC fixes from Arnd Bergmann: "There are a lot of minor DT fixes for Mediatek, Rockchip, Qualcomm and Microchip and NXP, addressing both build-time warnings and bugs found during runtime testing. Most of these changes are machine specific fixups, but there are a few notable regressions that affect an entire SoC: - The Qualcomm MSI support that was improved for 6.9 ended up being wrong on some chips and now gets fixed. - The i.MX8MP camera interface broke due to a typo and gets updated again. The main driver fix is also for Qualcomm platforms, rewriting an interface in the QSEECOM firmware support that could lead to crashing the kernel from a trusted application. The only other code changes are minor fixes for Mediatek SoC drivers" * tag 'soc-fixes-6.9-2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (50 commits) ARM: dts: imx6ull-tarragon: fix USB over-current polarity soc: mediatek: mtk-socinfo: depends on CONFIG_SOC_BUS soc: mediatek: mtk-svs: Append "-thermal" to thermal zone names arm64: dts: imx8mp: Fix assigned-clocks for second CSI2 ARM: dts: microchip: at91-sama7g54_curiosity: Replace regulator-suspend-voltage with the valid property ARM: dts: microchip: at91-sama7g5ek: Replace regulator-suspend-voltage with the valid property arm64: dts: rockchip: Fix USB interface compatible string on kobol-helios64 arm64: dts: qcom: sc8180x: Fix ss_phy_irq for secondary USB controller arm64: dts: qcom: sm8650: Fix the msi-map entries arm64: dts: qcom: sm8550: Fix the msi-map entries arm64: dts: qcom: sm8450: Fix the msi-map entries arm64: dts: qcom: sc8280xp: add missing PCIe minimum OPP arm64: dts: qcom: x1e80100: Fix the compatible for cluster idle states arm64: dts: qcom: Fix type of "wdog" IRQs for remoteprocs arm64: dts: rockchip: regulator for sd needs to be always on for BPI-R2Pro dt-bindings: rockchip: grf: Add missing type to 'pcie-phy' node arm64: dts: rockchip: drop redundant disable-gpios in Lubancat 2 arm64: dts: rockchip: drop redundant disable-gpios in Lubancat 1 arm64: dts: rockchip: drop redundant pcie-reset-suspend in Scarlet Dumo arm64: dts: rockchip: mark system power controller and fix typo on orangepi-5-plus ...

Linus Torvalds committed 2 years ago

Commit 5eb45732 parents e6ebf01 9f26bc744 files · +331 −193Browse files

Unified · Split

44 files

Documentation/devicetree/bindings/soc/rockchip/grf.yaml +1 −0
arch/arm/boot/dts/microchip/at91-sama7g54_curiosity.dts +4 −4
arch/arm/boot/dts/microchip/at91-sama7g5ek.dts +4 −4
arch/arm/boot/dts/nxp/imx/imx6ull-tarragon-common.dtsi +1 −0
arch/arm64/boot/dts/freescale/imx8mp.dtsi +1 −1
arch/arm64/boot/dts/mediatek/mt2712-evb.dts +4 −4
arch/arm64/boot/dts/mediatek/mt2712e.dtsi +2 −1
arch/arm64/boot/dts/mediatek/mt7622.dtsi +14 −20
arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts +3 −3
arch/arm64/boot/dts/mediatek/mt7986a.dtsi +2 −6
arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi +0 −1
arch/arm64/boot/dts/mediatek/mt8183.dtsi +1 −0
arch/arm64/boot/dts/mediatek/mt8186-corsola.dtsi +1 −1
arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi +3 −3
arch/arm64/boot/dts/mediatek/mt8192.dtsi +1 −0
arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi +34 −2
arch/arm64/boot/dts/mediatek/mt8195.dtsi +5 −0
arch/arm64/boot/dts/qcom/sc7280.dtsi +2 −2
arch/arm64/boot/dts/qcom/sc8180x.dtsi +1 −1
arch/arm64/boot/dts/qcom/sc8280xp.dtsi +8 −3
arch/arm64/boot/dts/qcom/sm6350.dtsi +2 −2
arch/arm64/boot/dts/qcom/sm6375.dtsi +1 −1
arch/arm64/boot/dts/qcom/sm8250.dtsi +3 −3
arch/arm64/boot/dts/qcom/sm8450.dtsi +4 −12
arch/arm64/boot/dts/qcom/sm8550.dtsi +4 −6
arch/arm64/boot/dts/qcom/sm8650.dtsi +4 −6
arch/arm64/boot/dts/qcom/x1e80100.dtsi +2 −2
arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi +1 −2
arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts +1 −1
arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts +0 −1
arch/arm64/boot/dts/rockchip/rk3399-puma-haikou.dts +2 −0
arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi +47 −6
arch/arm64/boot/dts/rockchip/rk3566-lubancat-1.dts +0 −1
arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts +4 −2
arch/arm64/boot/dts/rockchip/rk3568-lubancat-2.dts +0 −1
arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5.dtsi +2 −2
arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts +2 −1
arch/arm64/boot/dts/rockchip/rk3588-quartzpro64.dts +1 −0
drivers/firmware/qcom/qcom_qseecom_uefisecapp.c +91 −46
drivers/firmware/qcom/qcom_scm.c +6 −31
drivers/soc/mediatek/Kconfig +1 −0
drivers/soc/mediatek/mtk-svs.c +5 −2
include/linux/firmware/qcom/qcom_qseecom.h +51 −4
include/linux/firmware/qcom/qcom_scm.h +5 −5

Documentation/devicetree/bindings/soc/rockchip/grf.yaml+1−0

@@ -171,6 +171,7 @@ allOf: · 170 unmodified lines
171	171	unevaluatedProperties: false
172	172
173	173	pcie-phy:
	174	+ type: object
174	175	description:
175	176	Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt
176	177

arch/arm/boot/dts/microchip/at91-sama7g54_curiosity.dts+4−4

@@ -242,7 +242,7 @@ · 241 unmodified lines
242	242
243	243	regulator-state-standby {
244	244	regulator-on-in-suspend;
245		− regulator-suspend-voltage = <1150000>;
	245	+ regulator-suspend-microvolt = <1150000>;
246	246	regulator-mode = <4>;
247	247	};
248	248
@@ -263,7 +263,7 @@ · 14 unmodified lines
263	263
264	264	regulator-state-standby {
265	265	regulator-on-in-suspend;
266		− regulator-suspend-voltage = <1050000>;
	266	+ regulator-suspend-microvolt = <1050000>;
267	267	regulator-mode = <4>;
268	268	};
269	269
@@ -280,7 +280,7 @@ · 10 unmodified lines
280	280	regulator-always-on;
281	281
282	282	regulator-state-standby {
283		− regulator-suspend-voltage = <1800000>;
	283	+ regulator-suspend-microvolt = <1800000>;
284	284	regulator-on-in-suspend;
285	285	};
286	286
@@ -296,7 +296,7 @@ · 9 unmodified lines
296	296	regulator-always-on;
297	297
298	298	regulator-state-standby {
299		− regulator-suspend-voltage = <3300000>;
	299	+ regulator-suspend-microvolt = <3300000>;
300	300	regulator-on-in-suspend;
301	301	};
302	302

arch/arm/boot/dts/microchip/at91-sama7g5ek.dts+4−4

@@ -293,7 +293,7 @@ · 292 unmodified lines
293	293
294	294	regulator-state-standby {
295	295	regulator-on-in-suspend;
296		− regulator-suspend-voltage = <1150000>;
	296	+ regulator-suspend-microvolt = <1150000>;
297	297	regulator-mode = <4>;
298	298	};
299	299
@@ -314,7 +314,7 @@ · 14 unmodified lines
314	314
315	315	regulator-state-standby {
316	316	regulator-on-in-suspend;
317		− regulator-suspend-voltage = <1050000>;
	317	+ regulator-suspend-microvolt = <1050000>;
318	318	regulator-mode = <4>;
319	319	};
320	320
@@ -331,7 +331,7 @@ · 10 unmodified lines
331	331	regulator-always-on;
332	332
333	333	regulator-state-standby {
334		− regulator-suspend-voltage = <1800000>;
	334	+ regulator-suspend-microvolt = <1800000>;
335	335	regulator-on-in-suspend;
336	336	};
337	337
@@ -346,7 +346,7 @@ · 8 unmodified lines
346	346	regulator-max-microvolt = <3700000>;
347	347
348	348	regulator-state-standby {
349		− regulator-suspend-voltage = <1800000>;
	349	+ regulator-suspend-microvolt = <1800000>;
350	350	regulator-on-in-suspend;
351	351	};
352	352

arch/arm/boot/dts/nxp/imx/imx6ull-tarragon-common.dtsi+1−0

@@ -805,6 +805,7 @@ · 804 unmodified lines
805	805	&pinctrl_usb_pwr>;
806	806	dr_mode = "host";
807	807	power-active-high;
	808	+ over-current-active-low;
808	809	disable-over-current;
809	810	status = "okay";
810	811	};

arch/arm64/boot/dts/freescale/imx8mp.dtsi+1−1

@@ -1672,7 +1672,7 @@ · 1671 unmodified lines
1672	1672	<&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>,
1673	1673	<&clk IMX8MP_CLK_MEDIA_AXI_ROOT>;
1674	1674	clock-names = "pclk", "wrap", "phy", "axi";
1675		− assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM1_PIX>,
	1675	+ assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM2_PIX>,
1676	1676	<&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>;
1677	1677	assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>,
1678	1678	<&clk IMX8MP_CLK_24M>;

arch/arm64/boot/dts/mediatek/mt2712-evb.dts+4−4

@@ -129,7 +129,7 @@ · 128 unmodified lines
129	129	};
130	130
131	131	&pio {
132		− eth_default: eth_default {
	132	+ eth_default: eth-default-pins {
133	133	tx_pins {
134	134	pinmux = <MT2712_PIN_71_GBE_TXD3__FUNC_GBE_TXD3>,
135	135	<MT2712_PIN_72_GBE_TXD2__FUNC_GBE_TXD2>,
@@ -156,7 +156,7 @@ · 20 unmodified lines
156	156	};
157	157	};
158	158
159		− eth_sleep: eth_sleep {
	159	+ eth_sleep: eth-sleep-pins {
160	160	tx_pins {
161	161	pinmux = <MT2712_PIN_71_GBE_TXD3__FUNC_GPIO71>,
162	162	<MT2712_PIN_72_GBE_TXD2__FUNC_GPIO72>,
@@ -182,14 +182,14 @@ · 19 unmodified lines
182	182	};
183	183	};
184	184
185		− usb0_id_pins_float: usb0_iddig {
	185	+ usb0_id_pins_float: usb0-iddig-pins {
186	186	pins_iddig {
187	187	pinmux = <MT2712_PIN_12_IDDIG_P0__FUNC_IDDIG_A>;
188	188	bias-pull-up;
189	189	};
190	190	};
191	191
192		− usb1_id_pins_float: usb1_iddig {
	192	+ usb1_id_pins_float: usb1-iddig-pins {
193	193	pins_iddig {
194	194	pinmux = <MT2712_PIN_14_IDDIG_P1__FUNC_IDDIG_B>;
195	195	bias-pull-up;

arch/arm64/boot/dts/mediatek/mt2712e.dtsi+2−1

@@ -249,10 +249,11 @@ · 248 unmodified lines
249	249	#clock-cells = <1>;
250	250	};
251	251
252		− infracfg: syscon@10001000 {
	252	+ infracfg: clock-controller@10001000 {
253	253	compatible = "mediatek,mt2712-infracfg", "syscon";
254	254	reg = <0 0x10001000 0 0x1000>;
255	255	#clock-cells = <1>;
	256	+ #reset-cells = <1>;
256	257	};
257	258
258	259	pericfg: syscon@10003000 {

arch/arm64/boot/dts/mediatek/mt7622.dtsi+14−20

@@ -252,7 +252,7 @@ · 251 unmodified lines
252	252	clock-names = "hif_sel";
253	253	};
254	254
255		− cir: cir@10009000 {
	255	+ cir: ir-receiver@10009000 {
256	256	compatible = "mediatek,mt7622-cir";
257	257	reg = <0 0x10009000 0 0x1000>;
258	258	interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_LOW>;
@@ -283,16 +283,14 @@ · 24 unmodified lines
283	283	};
284	284	};
285	285
286		− apmixedsys: apmixedsys@10209000 {
287		− compatible = "mediatek,mt7622-apmixedsys",
288		− "syscon";
	286	+ apmixedsys: clock-controller@10209000 {
	287	+ compatible = "mediatek,mt7622-apmixedsys";
289	288	reg = <0 0x10209000 0 0x1000>;
290	289	#clock-cells = <1>;
291	290	};
292	291
293		− topckgen: topckgen@10210000 {
294		− compatible = "mediatek,mt7622-topckgen",
295		− "syscon";
	292	+ topckgen: clock-controller@10210000 {
	293	+ compatible = "mediatek,mt7622-topckgen";
296	294	reg = <0 0x10210000 0 0x1000>;
297	295	#clock-cells = <1>;
298	296	};
@@ -515,7 +513,6 @@ · 216 unmodified lines
515	513	<&pericfg CLK_PERI_AUXADC_PD>;
516	514	clock-names = "therm", "auxadc";
517	515	resets = <&pericfg MT7622_PERI_THERM_SW_RST>;
518		− reset-names = "therm";
519	516	mediatek,auxadc = <&auxadc>;
520	517	mediatek,apmixedsys = <&apmixedsys>;
521	518	nvmem-cells = <&thermal_calibration>;
@@ -734,9 +731,8 @@ · 212 unmodified lines
734	731	power-domains = <&scpsys MT7622_POWER_DOMAIN_WB>;
735	732	};
736	733
737		− ssusbsys: ssusbsys@1a000000 {
738		− compatible = "mediatek,mt7622-ssusbsys",
739		− "syscon";
	734	+ ssusbsys: clock-controller@1a000000 {
	735	+ compatible = "mediatek,mt7622-ssusbsys";
740	736	reg = <0 0x1a000000 0 0x1000>;
741	737	#clock-cells = <1>;
742	738	#reset-cells = <1>;
@@ -793,9 +789,8 @@ · 50 unmodified lines
793	789	};
794	790	};
795	791
796		− pciesys: pciesys@1a100800 {
797		− compatible = "mediatek,mt7622-pciesys",
798		− "syscon";
	792	+ pciesys: clock-controller@1a100800 {
	793	+ compatible = "mediatek,mt7622-pciesys";
799	794	reg = <0 0x1a100800 0 0x1000>;
800	795	#clock-cells = <1>;
801	796	#reset-cells = <1>;
@@ -921,12 +916,13 @@ · 119 unmodified lines
921	916	};
922	917	};
923	918
924		− hifsys: syscon@1af00000 {
925		− compatible = "mediatek,mt7622-hifsys", "syscon";
	919	+ hifsys: clock-controller@1af00000 {
	920	+ compatible = "mediatek,mt7622-hifsys";
926	921	reg = <0 0x1af00000 0 0x70>;
	922	+ #clock-cells = <1>;
927	923	};
928	924
929		− ethsys: syscon@1b000000 {
	925	+ ethsys: clock-controller@1b000000 {
930	926	compatible = "mediatek,mt7622-ethsys",
931	927	"syscon";
932	928	reg = <0 0x1b000000 0 0x1000>;
@@ -966,9 +962,7 @@ · 33 unmodified lines
966	962	};
967	963
968	964	eth: ethernet@1b100000 {
969		− compatible = "mediatek,mt7622-eth",
970		− "mediatek,mt2701-eth",
971		− "syscon";
	965	+ compatible = "mediatek,mt7622-eth";
972	966	reg = <0 0x1b100000 0 0x20000>;
973	967	interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_LOW>,
974	968	<GIC_SPI 224 IRQ_TYPE_LEVEL_LOW>,

arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts+3−3

@@ -146,19 +146,19 @@ · 145 unmodified lines
146	146
147	147	&cpu_thermal {
148	148	cooling-maps {
149		− cpu-active-high {
	149	+ map-cpu-active-high {
150	150	/* active: set fan to cooling level 2 */
151	151	cooling-device = <&fan 2 2>;
152	152	trip = <&cpu_trip_active_high>;
153	153	};
154	154
155		− cpu-active-med {
	155	+ map-cpu-active-med {
156	156	/* active: set fan to cooling level 1 */
157	157	cooling-device = <&fan 1 1>;
158	158	trip = <&cpu_trip_active_med>;
159	159	};
160	160
161		− cpu-active-low {
	161	+ map-cpu-active-low {
162	162	/* active: set fan to cooling level 0 */
163	163	cooling-device = <&fan 0 0>;
164	164	trip = <&cpu_trip_active_low>;

arch/arm64/boot/dts/mediatek/mt7986a.dtsi+2−6

@@ -332,9 +332,8 @@ · 331 unmodified lines
332	332	reg = <0 0x1100c800 0 0x800>;
333	333	interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
334	334	clocks = <&infracfg CLK_INFRA_THERM_CK>,
335		− <&infracfg CLK_INFRA_ADC_26M_CK>,
336		− <&infracfg CLK_INFRA_ADC_FRC_CK>;
337		− clock-names = "therm", "auxadc", "adc_32k";
	335	+ <&infracfg CLK_INFRA_ADC_26M_CK>;
	336	+ clock-names = "therm", "auxadc";
338	337	nvmem-cells = <&thermal_calibration>;
339	338	nvmem-cell-names = "calibration-data";
340	339	#thermal-sensor-cells = <1>;
@@ -492,8 +491,6 @@ · 151 unmodified lines
492	491	compatible = "mediatek,mt7986-ethsys",
493	492	"syscon";
494	493	reg = <0 0x15000000 0 0x1000>;
495		− #address-cells = <1>;
496		− #size-cells = <1>;
497	494	#clock-cells = <1>;
498	495	#reset-cells = <1>;
499	496	};
@@ -556,7 +553,6 @@ · 56 unmodified lines
556	553	<&topckgen CLK_TOP_SGM_325M_SEL>;
557	554	assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>,
558	555	<&apmixedsys CLK_APMIXED_SGMPLL>;
559		− #reset-cells = <1>;
560	556	#address-cells = <1>;
561	557	#size-cells = <0>;
562	558	mediatek,ethsys = <&ethsys>;

arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi+0−1

@@ -433,7 +433,6 @@ · 432 unmodified lines
433	433	};
434	434
435	435	&mt6358_vgpu_reg {
436		− regulator-min-microvolt = <625000>;
437	436	regulator-max-microvolt = <900000>;
438	437
439	438	regulator-coupled-with = <&mt6358_vsram_gpu_reg>;

arch/arm64/boot/dts/mediatek/mt8183.dtsi+1−0

@@ -1637,6 +1637,7 @@ · 1636 unmodified lines
1637	1637	compatible = "mediatek,mt8183-mfgcfg", "syscon";
1638	1638	reg = <0 0x13000000 0 0x1000>;
1639	1639	#clock-cells = <1>;
	1640	+ power-domains = <&spm MT8183_POWER_DOMAIN_MFG_ASYNC>;
1640	1641	};
1641	1642
1642	1643	gpu: gpu@13040000 {

arch/arm64/boot/dts/mediatek/mt8186-corsola.dtsi+1−1

@@ -1296,7 +1296,7 @@ · 1295 unmodified lines
1296	1296	* regulator coupling requirements.
1297	1297	*/
1298	1298	regulator-name = "ppvar_dvdd_vgpu";
1299		− regulator-min-microvolt = <600000>;
	1299	+ regulator-min-microvolt = <500000>;
1300	1300	regulator-max-microvolt = <950000>;
1301	1301	regulator-ramp-delay = <6250>;
1302	1302	regulator-enable-ramp-delay = <200>;

arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi+3−3

@@ -1421,7 +1421,7 @@ · 1420 unmodified lines
1421	1421	mt6315_6_vbuck1: vbuck1 {
1422	1422	regulator-compatible = "vbuck1";
1423	1423	regulator-name = "Vbcpu";
1424		− regulator-min-microvolt = <300000>;
	1424	+ regulator-min-microvolt = <400000>;
1425	1425	regulator-max-microvolt = <1193750>;
1426	1426	regulator-enable-ramp-delay = <256>;
1427	1427	regulator-allowed-modes = <0 1 2>;
@@ -1431,7 +1431,7 @@ · 3 unmodified lines
1431	1431	mt6315_6_vbuck3: vbuck3 {
1432	1432	regulator-compatible = "vbuck3";
1433	1433	regulator-name = "Vlcpu";
1434		− regulator-min-microvolt = <300000>;
	1434	+ regulator-min-microvolt = <400000>;
1435	1435	regulator-max-microvolt = <1193750>;
1436	1436	regulator-enable-ramp-delay = <256>;
1437	1437	regulator-allowed-modes = <0 1 2>;
@@ -1448,7 +1448,7 @@ · 10 unmodified lines
1448	1448	mt6315_7_vbuck1: vbuck1 {
1449	1449	regulator-compatible = "vbuck1";
1450	1450	regulator-name = "Vgpu";
1451		− regulator-min-microvolt = <606250>;
	1451	+ regulator-min-microvolt = <400000>;
1452	1452	regulator-max-microvolt = <800000>;
1453	1453	regulator-enable-ramp-delay = <256>;
1454	1454	regulator-allowed-modes = <0 1 2>;

arch/arm64/boot/dts/mediatek/mt8192.dtsi+1−0

@@ -1464,6 +1464,7 @@ · 1463 unmodified lines
1464	1464	reg = <0 0x14001000 0 0x1000>;
1465	1465	interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>;
1466	1466	clocks = <&mmsys CLK_MM_DISP_MUTEX0>;
	1467	+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>;
1467	1468	mediatek,gce-events = <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0>,
1468	1469	<CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_1>;
1469	1470	power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;

arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi+34−2

@@ -264,6 +264,38 @@ · 263 unmodified lines
264	264	status = "okay";
265	265	};
266	266
	267	+&cpu0 {
	268	+ cpu-supply = <&mt6359_vcore_buck_reg>;
	269	+};
	270	+
	271	+&cpu1 {
	272	+ cpu-supply = <&mt6359_vcore_buck_reg>;
	273	+};
	274	+
	275	+&cpu2 {
	276	+ cpu-supply = <&mt6359_vcore_buck_reg>;
	277	+};
	278	+
	279	+&cpu3 {
	280	+ cpu-supply = <&mt6359_vcore_buck_reg>;
	281	+};
	282	+
	283	+&cpu4 {
	284	+ cpu-supply = <&mt6315_6_vbuck1>;
	285	+};
	286	+
	287	+&cpu5 {
	288	+ cpu-supply = <&mt6315_6_vbuck1>;
	289	+};
	290	+
	291	+&cpu6 {
	292	+ cpu-supply = <&mt6315_6_vbuck1>;
	293	+};
	294	+
	295	+&cpu7 {
	296	+ cpu-supply = <&mt6315_6_vbuck1>;
	297	+};
	298	+
267	299	&dp_intf0 {
268	300	status = "okay";
269	301
@@ -1214,7 +1246,7 @@ · 944 unmodified lines
1214	1246	mt6315_6_vbuck1: vbuck1 {
1215	1247	regulator-compatible = "vbuck1";
1216	1248	regulator-name = "Vbcpu";
1217		− regulator-min-microvolt = <300000>;
	1249	+ regulator-min-microvolt = <400000>;
1218	1250	regulator-max-microvolt = <1193750>;
1219	1251	regulator-enable-ramp-delay = <256>;
1220	1252	regulator-ramp-delay = <6250>;
@@ -1232,7 +1264,7 @@ · 11 unmodified lines
1232	1264	mt6315_7_vbuck1: vbuck1 {
1233	1265	regulator-compatible = "vbuck1";
1234	1266	regulator-name = "Vgpu";
1235		− regulator-min-microvolt = <625000>;
	1267	+ regulator-min-microvolt = <400000>;
1236	1268	regulator-max-microvolt = <1193750>;
1237	1269	regulator-enable-ramp-delay = <256>;
1238	1270	regulator-ramp-delay = <6250>;

arch/arm64/boot/dts/mediatek/mt8195.dtsi+5−0

@@ -2028,6 +2028,7 @@ · 2027 unmodified lines
2028	2028	compatible = "mediatek,mt8195-vppsys0", "syscon";
2029	2029	reg = <0 0x14000000 0 0x1000>;
2030	2030	#clock-cells = <1>;
	2031	+ mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0 0x1000>;
2031	2032	};
2032	2033
2033	2034	dma-controller@14001000 {
@@ -2251,6 +2252,7 @@ · 217 unmodified lines
2251	2252	compatible = "mediatek,mt8195-vppsys1", "syscon";
2252	2253	reg = <0 0x14f00000 0 0x1000>;
2253	2254	#clock-cells = <1>;
	2255	+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0 0x1000>;
2254	2256	};
2255	2257
2256	2258	mutex@14f01000 {
@@ -3080,6 +3082,7 @@ · 823 unmodified lines
3080	3082	reg = <0 0x1c01a000 0 0x1000>;
3081	3083	mboxes = <&gce0 0 CMDQ_THR_PRIO_4>;
3082	3084	#clock-cells = <1>;
	3085	+ mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0xa000 0x1000>;
3083	3086	};
3084	3087
3085	3088
@@ -3261,6 +3264,7 @@ · 175 unmodified lines
3261	3264	interrupts = <GIC_SPI 658 IRQ_TYPE_LEVEL_HIGH 0>;
3262	3265	power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3263	3266	clocks = <&vdosys0 CLK_VDO0_DISP_MUTEX0>;
	3267	+ mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0x6000 0x1000>;
3264	3268	mediatek,gce-events = <CMDQ_EVENT_VDO0_DISP_STREAM_DONE_0>;
3265	3269	};
3266	3270
@@ -3331,6 +3335,7 @@ · 64 unmodified lines
3331	3335	power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3332	3336	clocks = <&vdosys1 CLK_VDO1_DISP_MUTEX>;
3333	3337	clock-names = "vdo1_mutex";
	3338	+ mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x1000 0x1000>;
3334	3339	mediatek,gce-events = <CMDQ_EVENT_VDO1_STREAM_DONE_ENG_0>;
3335	3340	};
3336	3341

arch/arm64/boot/dts/qcom/sc7280.dtsi+2−2

@@ -3707,7 +3707,7 @@ · 3706 unmodified lines
3707	3707	compatible = "qcom,sc7280-adsp-pas";
3708	3708	reg = <0 0x03700000 0 0x100>;
3709	3709
3710		− interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
	3710	+ interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
3711	3711	<&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3712	3712	<&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
3713	3713	<&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
@@ -3944,7 +3944,7 @@ · 230 unmodified lines
3944	3944	compatible = "qcom,sc7280-cdsp-pas";
3945	3945	reg = <0 0x0a300000 0 0x10000>;
3946	3946
3947		− interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
	3947	+ interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
3948	3948	<&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3949	3949	<&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
3950	3950	<&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,

arch/arm64/boot/dts/qcom/sc8180x.dtsi+1−1

@@ -2701,7 +2701,7 @@ · 2700 unmodified lines
2701	2701	resets = <&gcc GCC_USB30_SEC_BCR>;
2702	2702	power-domains = <&gcc USB30_SEC_GDSC>;
2703	2703	interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
2704		− <&pdc 7 IRQ_TYPE_LEVEL_HIGH>,
	2704	+ <&pdc 40 IRQ_TYPE_LEVEL_HIGH>,
2705	2705	<&pdc 10 IRQ_TYPE_EDGE_BOTH>,
2706	2706	<&pdc 11 IRQ_TYPE_EDGE_BOTH>;
2707	2707	interrupt-names = "hs_phy_irq", "ss_phy_irq",

arch/arm64/boot/dts/qcom/sc8280xp.dtsi+8−3

@@ -1774,6 +1774,7 @@ · 1773 unmodified lines
1774	1774	reset-names = "pci";
1775	1775
1776	1776	power-domains = <&gcc PCIE_4_GDSC>;
	1777	+ required-opps = <&rpmhpd_opp_nom>;
1777	1778
1778	1779	phys = <&pcie4_phy>;
1779	1780	phy-names = "pciephy";
@@ -1872,6 +1873,7 @@ · 92 unmodified lines
1872	1873	reset-names = "pci";
1873	1874
1874	1875	power-domains = <&gcc PCIE_3B_GDSC>;
	1876	+ required-opps = <&rpmhpd_opp_nom>;
1875	1877
1876	1878	phys = <&pcie3b_phy>;
1877	1879	phy-names = "pciephy";
@@ -1970,6 +1972,7 @@ · 92 unmodified lines
1970	1972	reset-names = "pci";
1971	1973
1972	1974	power-domains = <&gcc PCIE_3A_GDSC>;
	1975	+ required-opps = <&rpmhpd_opp_nom>;
1973	1976
1974	1977	phys = <&pcie3a_phy>;
1975	1978	phy-names = "pciephy";
@@ -2071,6 +2074,7 @@ · 95 unmodified lines
2071	2074	reset-names = "pci";
2072	2075
2073	2076	power-domains = <&gcc PCIE_2B_GDSC>;
	2077	+ required-opps = <&rpmhpd_opp_nom>;
2074	2078
2075	2079	phys = <&pcie2b_phy>;
2076	2080	phy-names = "pciephy";
@@ -2169,6 +2173,7 @@ · 92 unmodified lines
2169	2173	reset-names = "pci";
2170	2174
2171	2175	power-domains = <&gcc PCIE_2A_GDSC>;
	2176	+ required-opps = <&rpmhpd_opp_nom>;
2172	2177
2173	2178	phys = <&pcie2a_phy>;
2174	2179	phy-names = "pciephy";
@@ -2641,7 +2646,7 @@ · 466 unmodified lines
2641	2646	compatible = "qcom,sc8280xp-adsp-pas";
2642	2647	reg = <0 0x03000000 0 0x100>;
2643	2648
2644		− interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
	2649	+ interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
2645	2650	<&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
2646	2651	<&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
2647	2652	<&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
@@ -4977,7 +4982,7 @@ · 2329 unmodified lines
4977	4982	compatible = "qcom,sc8280xp-nsp0-pas";
4978	4983	reg = <0 0x1b300000 0 0x100>;
4979	4984
4980		− interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
	4985	+ interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
4981	4986	<&smp2p_nsp0_in 0 IRQ_TYPE_EDGE_RISING>,
4982	4987	<&smp2p_nsp0_in 1 IRQ_TYPE_EDGE_RISING>,
4983	4988	<&smp2p_nsp0_in 2 IRQ_TYPE_EDGE_RISING>,
@@ -5108,7 +5113,7 @@ · 124 unmodified lines
5108	5113	compatible = "qcom,sc8280xp-nsp1-pas";
5109	5114	reg = <0 0x21300000 0 0x100>;
5110	5115
5111		− interrupts-extended = <&intc GIC_SPI 887 IRQ_TYPE_LEVEL_HIGH>,
	5116	+ interrupts-extended = <&intc GIC_SPI 887 IRQ_TYPE_EDGE_RISING>,
5112	5117	<&smp2p_nsp1_in 0 IRQ_TYPE_EDGE_RISING>,
5113	5118	<&smp2p_nsp1_in 1 IRQ_TYPE_EDGE_RISING>,
5114	5119	<&smp2p_nsp1_in 2 IRQ_TYPE_EDGE_RISING>,

arch/arm64/boot/dts/qcom/sm6350.dtsi+2−2

@@ -1252,7 +1252,7 @@ · 1251 unmodified lines
1252	1252	compatible = "qcom,sm6350-adsp-pas";
1253	1253	reg = <0 0x03000000 0 0x100>;
1254	1254
1255		− interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
	1255	+ interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
1256	1256	<&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
1257	1257	<&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
1258	1258	<&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
@@ -1511,7 +1511,7 @@ · 252 unmodified lines
1511	1511	compatible = "qcom,sm6350-cdsp-pas";
1512	1512	reg = <0 0x08300000 0 0x10000>;
1513	1513
1514		− interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
	1514	+ interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
1515	1515	<&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
1516	1516	<&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
1517	1517	<&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,

arch/arm64/boot/dts/qcom/sm6375.dtsi+1−1

@@ -1561,7 +1561,7 @@ · 1560 unmodified lines
1561	1561	compatible = "qcom,sm6375-adsp-pas";
1562	1562	reg = <0 0x0a400000 0 0x100>;
1563	1563
1564		− interrupts-extended = <&intc GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
	1564	+ interrupts-extended = <&intc GIC_SPI 282 IRQ_TYPE_EDGE_RISING>,
1565	1565	<&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
1566	1566	<&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
1567	1567	<&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,

arch/arm64/boot/dts/qcom/sm8250.dtsi+3−3

@@ -3062,7 +3062,7 @@ · 3061 unmodified lines
3062	3062	compatible = "qcom,sm8250-slpi-pas";
3063	3063	reg = <0 0x05c00000 0 0x4000>;
3064	3064
3065		− interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>,
	3065	+ interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>,
3066	3066	<&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
3067	3067	<&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>,
3068	3068	<&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>,
@@ -3766,7 +3766,7 @@ · 697 unmodified lines
3766	3766	compatible = "qcom,sm8250-cdsp-pas";
3767	3767	reg = <0 0x08300000 0 0x10000>;
3768	3768
3769		− interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
	3769	+ interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
3770	3770	<&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
3771	3771	<&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
3772	3772	<&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
@@ -5928,7 +5928,7 @@ · 2155 unmodified lines
5928	5928	compatible = "qcom,sm8250-adsp-pas";
5929	5929	reg = <0 0x17300000 0 0x100>;
5930	5930
5931		− interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
	5931	+ interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
5932	5932	<&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
5933	5933	<&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
5934	5934	<&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,

arch/arm64/boot/dts/qcom/sm8450.dtsi+4−12

@@ -1777,12 +1777,8 @@ · 1776 unmodified lines
1777	1777	ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
1778	1778	<0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
1779	1779
1780		− /*
1781		− * MSIs for BDF (1:0.0) only works with Device ID 0x5980.
1782		− * Hence, the IDs are swapped.
1783		− */
1784		− msi-map = <0x0 &gic_its 0x5981 0x1>,
1785		− <0x100 &gic_its 0x5980 0x1>;
	1780	+ msi-map = <0x0 &gic_its 0x5980 0x1>,
	1781	+ <0x100 &gic_its 0x5981 0x1>;
1786	1782	msi-map-mask = <0xff00>;
1787	1783	interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
1788	1784	<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
@@ -1900,12 +1896,8 @@ · 111 unmodified lines
1900	1896	ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
1901	1897	<0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
1902	1898
1903		− /*
1904		− * MSIs for BDF (1:0.0) only works with Device ID 0x5a00.
1905		− * Hence, the IDs are swapped.
1906		− */
1907		− msi-map = <0x0 &gic_its 0x5a01 0x1>,
1908		− <0x100 &gic_its 0x5a00 0x1>;
	1899	+ msi-map = <0x0 &gic_its 0x5a00 0x1>,
	1900	+ <0x100 &gic_its 0x5a01 0x1>;
1909	1901	msi-map-mask = <0xff00>;
1910	1902	interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
1911	1903	<GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,

arch/arm64/boot/dts/qcom/sm8550.dtsi+4−6

@@ -1755,9 +1755,8 @@ · 1754 unmodified lines
1755	1755	<&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_0 0>;
1756	1756	interconnect-names = "pcie-mem", "cpu-pcie";
1757	1757
1758		− /* Entries are reversed due to the unusual ITS DeviceID encoding */
1759		− msi-map = <0x0 &gic_its 0x1401 0x1>,
1760		− <0x100 &gic_its 0x1400 0x1>;
	1758	+ msi-map = <0x0 &gic_its 0x1400 0x1>,
	1759	+ <0x100 &gic_its 0x1401 0x1>;
1761	1760	iommu-map = <0x0 &apps_smmu 0x1400 0x1>,
1762	1761	<0x100 &apps_smmu 0x1401 0x1>;
1763	1762
@@ -1867,9 +1866,8 @@ · 103 unmodified lines
1867	1866	<&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_1 0>;
1868	1867	interconnect-names = "pcie-mem", "cpu-pcie";
1869	1868
1870		− /* Entries are reversed due to the unusual ITS DeviceID encoding */
1871		− msi-map = <0x0 &gic_its 0x1481 0x1>,
1872		− <0x100 &gic_its 0x1480 0x1>;
	1869	+ msi-map = <0x0 &gic_its 0x1480 0x1>,
	1870	+ <0x100 &gic_its 0x1481 0x1>;
1873	1871	iommu-map = <0x0 &apps_smmu 0x1480 0x1>,
1874	1872	<0x100 &apps_smmu 0x1481 0x1>;
1875	1873

arch/arm64/boot/dts/qcom/sm8650.dtsi+4−6

@@ -2274,9 +2274,8 @@ · 2273 unmodified lines
2274	2274	interrupt-map-mask = <0 0 0 0x7>;
2275	2275	#interrupt-cells = <1>;
2276	2276
2277		− /* Entries are reversed due to the unusual ITS DeviceID encoding */
2278		− msi-map = <0x0 &gic_its 0x1401 0x1>,
2279		− <0x100 &gic_its 0x1400 0x1>;
	2277	+ msi-map = <0x0 &gic_its 0x1400 0x1>,
	2278	+ <0x100 &gic_its 0x1401 0x1>;
2280	2279	msi-map-mask = <0xff00>;
2281	2280
2282	2281	linux,pci-domain = <0>;
@@ -2402,9 +2401,8 @@ · 119 unmodified lines
2402	2401	interrupt-map-mask = <0 0 0 0x7>;
2403	2402	#interrupt-cells = <1>;
2404	2403
2405		− /* Entries are reversed due to the unusual ITS DeviceID encoding */
2406		− msi-map = <0x0 &gic_its 0x1481 0x1>,
2407		− <0x100 &gic_its 0x1480 0x1>;
	2404	+ msi-map = <0x0 &gic_its 0x1480 0x1>,
	2405	+ <0x100 &gic_its 0x1481 0x1>;
2408	2406	msi-map-mask = <0xff00>;
2409	2407
2410	2408	linux,pci-domain = <1>;

arch/arm64/boot/dts/qcom/x1e80100.dtsi+2−2

@@ -284,7 +284,7 @@ · 283 unmodified lines
284	284
285	285	domain-idle-states {
286	286	CLUSTER_CL4: cluster-sleep-0 {
287		− compatible = "arm,idle-state";
	287	+ compatible = "domain-idle-state";
288	288	idle-state-name = "l2-ret";
289	289	arm,psci-suspend-param = <0x01000044>;
290	290	entry-latency-us = <350>;
@@ -293,7 +293,7 @@ · 2 unmodified lines
293	293	};
294	294
295	295	CLUSTER_CL5: cluster-sleep-1 {
296		− compatible = "arm,idle-state";
	296	+ compatible = "domain-idle-state";
297	297	idle-state-name = "ret-pll-off";
298	298	arm,psci-suspend-param = <0x01000054>;
299	299	entry-latency-us = <2200>;

arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi+1−2

@@ -663,7 +663,7 @@ camera: &i2c7 { · 662 unmodified lines
663	663	port@1 {
664	664	reg = <1>;
665	665
666		− mipi1_in_panel: endpoint@1 {
	666	+ mipi1_in_panel: endpoint {
667	667	remote-endpoint = <&mipi1_out_panel>;
668	668	};
669	669	};
@@ -689,7 +689,6 @@ camera: &i2c7 { · 19 unmodified lines
689	689	ep-gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>;
690	690
691	691	/* PERST# asserted in S3 */
692		− pcie-reset-suspend = <1>;
693	692
694	693	vpcie3v3-supply = <&wlan_3v3>;
695	694	vpcie1v8-supply = <&pp1800_pcie>;

arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts+1−1

@@ -611,7 +611,7 @@ · 610 unmodified lines
611	611	#size-cells = <0>;
612	612
613	613	interface@0 { /* interface 0 of configuration 1 */
614		− compatible = "usbbda,8156.config1.0";
	614	+ compatible = "usbifbda,8156.config1.0";
615	615	reg = <0 1>;
616	616	};
617	617	};

arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts+0−1

@@ -779,7 +779,6 @@ · 778 unmodified lines
779	779	};
780	780
781	781	&pcie0 {
782		− bus-scan-delay-ms = <1000>;
783	782	ep-gpios = <&gpio2 RK_PD4 GPIO_ACTIVE_HIGH>;
784	783	num-lanes = <4>;
785	784	pinctrl-names = "default";

arch/arm64/boot/dts/rockchip/rk3399-puma-haikou.dts+2−0

@@ -194,6 +194,8 @@ · 193 unmodified lines
194	194	num-lanes = <4>;
195	195	pinctrl-names = "default";
196	196	pinctrl-0 = <&pcie_clkreqn_cpm>;
	197	+ vpcie3v3-supply = <&vcc3v3_baseboard>;
	198	+ vpcie12v-supply = <&dc_12v>;
197	199	status = "okay";
198	200	};
199	201

arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi+47−6

@@ -79,6 +79,26 @@ · 78 unmodified lines
79	79	regulator-max-microvolt = <5000000>;
80	80	};
81	81
	82	+ vcca_0v9: vcca-0v9-regulator {
	83	+ compatible = "regulator-fixed";
	84	+ regulator-name = "vcca_0v9";
	85	+ regulator-always-on;
	86	+ regulator-boot-on;
	87	+ regulator-min-microvolt = <900000>;
	88	+ regulator-max-microvolt = <900000>;
	89	+ vin-supply = <&vcc_1v8>;
	90	+ };
	91	+
	92	+ vcca_1v8: vcca-1v8-regulator {
	93	+ compatible = "regulator-fixed";
	94	+ regulator-name = "vcca_1v8";
	95	+ regulator-always-on;
	96	+ regulator-boot-on;
	97	+ regulator-min-microvolt = <1800000>;
	98	+ regulator-max-microvolt = <1800000>;
	99	+ vin-supply = <&vcc3v3_sys>;
	100	+ };
	101	+
82	102	vdd_log: vdd-log {
83	103	compatible = "pwm-regulator";
84	104	pwms = <&pwm2 0 25000 1>;
@@ -416,16 +436,28 @@ · 331 unmodified lines
416	436	gpio1830-supply = <&vcc_1v8>;
417	437	};
418	438
419		−&pmu_io_domains {
420		− status = "okay";
421		− pmu1830-supply = <&vcc_1v8>;
	439	+&pcie0 {
	440	+ /* PCIe PHY supplies */
	441	+ vpcie0v9-supply = <&vcca_0v9>;
	442	+ vpcie1v8-supply = <&vcca_1v8>;
422	443	};
423	444
424		−&pwm2 {
425		− status = "okay";
	445	+&pcie_clkreqn_cpm {
	446	+ rockchip,pins =
	447	+ <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>;
426	448	};
427	449
428	450	&pinctrl {
	451	+ pinctrl-names = "default";
	452	+ pinctrl-0 = <&q7_thermal_pin>;
	453	+
	454	+ gpios {
	455	+ q7_thermal_pin: q7-thermal-pin {
	456	+ rockchip,pins =
	457	+ <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
	458	+ };
	459	+ };
	460	+
429	461	i2c8 {
430	462	i2c8_xfer_a: i2c8-xfer {
431	463	rockchip,pins =
@@ -458,11 +490,20 @@ · 26 unmodified lines
458	490	usb3 {
459	491	usb3_id: usb3-id {
460	492	rockchip,pins =
461		− <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
	493	+ <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>;
462	494	};
463	495	};
464	496	};
465	497
	498	+&pmu_io_domains {
	499	+ status = "okay";
	500	+ pmu1830-supply = <&vcc_1v8>;
	501	+};
	502	+
	503	+&pwm2 {
	504	+ status = "okay";
	505	+};
	506	+
466	507	&sdhci {
467	508	/*
468	509	* Signal integrity isn't great at 200MHz but 100MHz has proven stable

arch/arm64/boot/dts/rockchip/rk3566-lubancat-1.dts+0−1

@@ -447,7 +447,6 @@ · 446 unmodified lines
447	447
448	448	&pcie2x1 {
449	449	reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
450		− disable-gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
451	450	vpcie3v3-supply = <&vcc3v3_pcie>;
452	451	status = "okay";
453	452	};

arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts+4−2

@@ -416,6 +416,8 @@ · 415 unmodified lines
416	416
417	417	vccio_sd: LDO_REG5 {
418	418	regulator-name = "vccio_sd";
	419	+ regulator-always-on;
	420	+ regulator-boot-on;
419	421	regulator-min-microvolt = <1800000>;
420	422	regulator-max-microvolt = <3300000>;
421	423
@@ -525,9 +527,9 @@ · 103 unmodified lines
525	527	#address-cells = <1>;
526	528	#size-cells = <0>;
527	529
528		− switch@0 {
	530	+ switch@1f {
529	531	compatible = "mediatek,mt7531";
530		− reg = <0>;
	532	+ reg = <0x1f>;
531	533
532	534	ports {
533	535	#address-cells = <1>;

arch/arm64/boot/dts/rockchip/rk3568-lubancat-2.dts+0−1

@@ -523,7 +523,6 @@ · 522 unmodified lines
523	523
524	524	&pcie2x1 {
525	525	reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>;
526		− disable-gpios = <&gpio3 RK_PC2 GPIO_ACTIVE_HIGH>;
527	526	vpcie3v3-supply = <&vcc3v3_mini_pcie>;
528	527	status = "okay";
529	528	};

arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5.dtsi+2−2

@@ -216,9 +216,9 @@ · 215 unmodified lines
216	216	pinctrl-0 = <&i2c7m0_xfer>;
217	217	status = "okay";
218	218
219		− es8316: audio-codec@11 {
	219	+ es8316: audio-codec@10 {
220	220	compatible = "everest,es8316";
221		− reg = <0x11>;
	221	+ reg = <0x10>;
222	222	assigned-clocks = <&cru I2S0_8CH_MCLKOUT>;
223	223	assigned-clock-rates = <12288000>;
224	224	clocks = <&cru I2S0_8CH_MCLKOUT>;

arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts+2−1

@@ -485,6 +485,7 @@ · 484 unmodified lines
485	485	pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
486	486	<&rk806_dvs2_null>, <&rk806_dvs3_null>;
487	487	spi-max-frequency = <1000000>;
	488	+ system-power-controller;
488	489
489	490	vcc1-supply = <&vcc5v0_sys>;
490	491	vcc2-supply = <&vcc5v0_sys>;
@@ -506,7 +507,7 @@ · 15 unmodified lines
506	507	#gpio-cells = <2>;
507	508
508	509	rk806_dvs1_null: dvs1-null-pins {
509		− pins = "gpio_pwrctrl2";
	510	+ pins = "gpio_pwrctrl1";
510	511	function = "pin_fun0";
511	512	};
512	513

arch/arm64/boot/dts/rockchip/rk3588-quartzpro64.dts+1−0

@@ -456,6 +456,7 @@ · 455 unmodified lines
456	456	<&rk806_dvs2_null>, <&rk806_dvs3_null>;
457	457	pinctrl-names = "default";
458	458	spi-max-frequency = <1000000>;
	459	+ system-power-controller;
459	460
460	461	vcc1-supply = <&vcc4v0_sys>;
461	462	vcc2-supply = <&vcc4v0_sys>;

drivers/firmware/qcom/qcom_qseecom_uefisecapp.c+91−46

@@ -221,6 +221,19 @@ struct qsee_rsp_uefi_query_variable_info { · 220 unmodified lines
221	221	* alignment of 8 bytes (64 bits) for GUIDs. Our definition of efi_guid_t,
222	222	* however, has an alignment of 4 byte (32 bits). So far, this seems to work
223	223	* fine here. See also the comment on the typedef of efi_guid_t.
	224	+ *
	225	+ * Note: It looks like uefisecapp is quite picky about how the memory passed to
	226	+ * it is structured and aligned. In particular the request/response setup used
	227	+ * for QSEE_CMD_UEFI_GET_VARIABLE. While qcom_qseecom_app_send(), in theory,
	228	+ * accepts separate buffers/addresses for the request and response parts, in
	229	+ * practice, however, it seems to expect them to be both part of a larger
	230	+ * contiguous block. We initially allocated separate buffers for the request
	231	+ * and response but this caused the QSEE_CMD_UEFI_GET_VARIABLE command to
	232	+ * either not write any response to the response buffer or outright crash the
	233	+ * device. Therefore, we now allocate a single contiguous block of DMA memory
	234	+ * for both and properly align the data using the macros below. In particular,
	235	+ * request and response structs are aligned at 8 byte (via __reqdata_offs()),
	236	+ * following the driver that this has been reverse-engineered from.
224	237	*/
225	238	#define qcuefi_buf_align_fields(fields...) \
226	239	({ \
@@ -244,6 +257,12 @@ struct qsee_rsp_uefi_query_variable_info { · 17 unmodified lines
244	257	#define __array_offs(type, count, offset) \
245	258	__field_impl(sizeof(type) * (count), __alignof__(type), offset)
246	259
	260	+#define __array_offs_aligned(type, count, align, offset) \
	261	+ __field_impl(sizeof(type) * (count), align, offset)
	262	+
	263	+#define __reqdata_offs(size, offset) \
	264	+ __array_offs_aligned(u8, size, 8, offset)
	265	+
247	266	#define __array(type, count) __array_offs(type, count, NULL)
248	267	#define __field_offs(type, offset) __array_offs(type, 1, offset)
249	268	#define __field(type) __array_offs(type, 1, NULL)
@@ -277,10 +296,15 @@ static efi_status_t qsee_uefi_get_variable(struct qcuefi_client *qcuefi, const e · 27 unmodified lines
277	296	unsigned long buffer_size = *data_size;
278	297	efi_status_t efi_status = EFI_SUCCESS;
279	298	unsigned long name_length;
	299	+ dma_addr_t cmd_buf_dma;
	300	+ size_t cmd_buf_size;
	301	+ void *cmd_buf;
280	302	size_t guid_offs;
281	303	size_t name_offs;
282	304	size_t req_size;
283	305	size_t rsp_size;
	306	+ size_t req_offs;
	307	+ size_t rsp_offs;
284	308	ssize_t status;
285	309
286	310	if (!name \|\| !guid)
@@ -304,17 +328,19 @@ static efi_status_t qsee_uefi_get_variable(struct qcuefi_client *qcuefi, const e · 17 unmodified lines
304	328	__array(u8, buffer_size)
305	329	);
306	330
307		− req_data = kzalloc(req_size, GFP_KERNEL);
308		− if (!req_data) {
	331	+ cmd_buf_size = qcuefi_buf_align_fields(
	332	+ __reqdata_offs(req_size, &req_offs)
	333	+ __reqdata_offs(rsp_size, &rsp_offs)
	334	+ );
	335	+
	336	+ cmd_buf = qseecom_dma_alloc(qcuefi->client, cmd_buf_size, &cmd_buf_dma, GFP_KERNEL);
	337	+ if (!cmd_buf) {
309	338	efi_status = EFI_OUT_OF_RESOURCES;
310	339	goto out;
311	340	}
312	341
313		− rsp_data = kzalloc(rsp_size, GFP_KERNEL);
314		− if (!rsp_data) {
315		− efi_status = EFI_OUT_OF_RESOURCES;
316		− goto out_free_req;
317		− }
	342	+ req_data = cmd_buf + req_offs;
	343	+ rsp_data = cmd_buf + rsp_offs;
318	344
319	345	req_data->command_id = QSEE_CMD_UEFI_GET_VARIABLE;
320	346	req_data->data_size = buffer_size;
@@ -332,7 +358,9 @@ static efi_status_t qsee_uefi_get_variable(struct qcuefi_client *qcuefi, const e · 11 unmodified lines
332	358
333	359	memcpy(((void *)req_data) + req_data->guid_offset, guid, req_data->guid_size);
334	360
335		− status = qcom_qseecom_app_send(qcuefi->client, req_data, req_size, rsp_data, rsp_size);
	361	+ status = qcom_qseecom_app_send(qcuefi->client,
	362	+ cmd_buf_dma + req_offs, req_size,
	363	+ cmd_buf_dma + rsp_offs, rsp_size);
336	364	if (status) {
337	365	efi_status = EFI_DEVICE_ERROR;
338	366	goto out_free;
@@ -407,9 +435,7 @@ static efi_status_t qsee_uefi_get_variable(struct qcuefi_client *qcuefi, const e · 68 unmodified lines
407	435	memcpy(data, ((void *)rsp_data) + rsp_data->data_offset, rsp_data->data_size);
408	436
409	437	out_free:
410		− kfree(rsp_data);
411		−out_free_req:
412		− kfree(req_data);
	438	+ qseecom_dma_free(qcuefi->client, cmd_buf_size, cmd_buf, cmd_buf_dma);
413	439	out:
414	440	return efi_status;
415	441	}
@@ -422,10 +448,15 @@ static efi_status_t qsee_uefi_set_variable(struct qcuefi_client *qcuefi, const e · 6 unmodified lines
422	448	struct qsee_rsp_uefi_set_variable *rsp_data;
423	449	efi_status_t efi_status = EFI_SUCCESS;
424	450	unsigned long name_length;
	451	+ dma_addr_t cmd_buf_dma;
	452	+ size_t cmd_buf_size;
	453	+ void *cmd_buf;
425	454	size_t name_offs;
426	455	size_t guid_offs;
427	456	size_t data_offs;
428	457	size_t req_size;
	458	+ size_t req_offs;
	459	+ size_t rsp_offs;
429	460	ssize_t status;
430	461
431	462	if (!name \|\| !guid)
@@ -450,17 +481,19 @@ static efi_status_t qsee_uefi_set_variable(struct qcuefi_client *qcuefi, const e · 18 unmodified lines
450	481	__array_offs(u8, data_size, &data_offs)
451	482	);
452	483
453		− req_data = kzalloc(req_size, GFP_KERNEL);
454		− if (!req_data) {
	484	+ cmd_buf_size = qcuefi_buf_align_fields(
	485	+ __reqdata_offs(req_size, &req_offs)
	486	+ __reqdata_offs(sizeof(*rsp_data), &rsp_offs)
	487	+ );
	488	+
	489	+ cmd_buf = qseecom_dma_alloc(qcuefi->client, cmd_buf_size, &cmd_buf_dma, GFP_KERNEL);
	490	+ if (!cmd_buf) {
455	491	efi_status = EFI_OUT_OF_RESOURCES;
456	492	goto out;
457	493	}
458	494
459		− rsp_data = kzalloc(sizeof(*rsp_data), GFP_KERNEL);
460		− if (!rsp_data) {
461		− efi_status = EFI_OUT_OF_RESOURCES;
462		− goto out_free_req;
463		− }
	495	+ req_data = cmd_buf + req_offs;
	496	+ rsp_data = cmd_buf + rsp_offs;
464	497
465	498	req_data->command_id = QSEE_CMD_UEFI_SET_VARIABLE;
466	499	req_data->attributes = attributes;
@@ -483,8 +516,9 @@ static efi_status_t qsee_uefi_set_variable(struct qcuefi_client *qcuefi, const e · 16 unmodified lines
483	516	if (data_size)
484	517	memcpy(((void *)req_data) + req_data->data_offset, data, req_data->data_size);
485	518
486		− status = qcom_qseecom_app_send(qcuefi->client, req_data, req_size, rsp_data,
487		− sizeof(*rsp_data));
	519	+ status = qcom_qseecom_app_send(qcuefi->client,
	520	+ cmd_buf_dma + req_offs, req_size,
	521	+ cmd_buf_dma + rsp_offs, sizeof(*rsp_data));
488	522	if (status) {
489	523	efi_status = EFI_DEVICE_ERROR;
490	524	goto out_free;
@@ -507,9 +541,7 @@ static efi_status_t qsee_uefi_set_variable(struct qcuefi_client *qcuefi, const e · 16 unmodified lines
507	541	}
508	542
509	543	out_free:
510		− kfree(rsp_data);
511		−out_free_req:
512		− kfree(req_data);
	544	+ qseecom_dma_free(qcuefi->client, cmd_buf_size, cmd_buf, cmd_buf_dma);
513	545	out:
514	546	return efi_status;
515	547	}
@@ -521,10 +553,15 @@ static efi_status_t qsee_uefi_get_next_variable(struct qcuefi_client *qcuefi, · 5 unmodified lines
521	553	struct qsee_req_uefi_get_next_variable *req_data;
522	554	struct qsee_rsp_uefi_get_next_variable *rsp_data;
523	555	efi_status_t efi_status = EFI_SUCCESS;
	556	+ dma_addr_t cmd_buf_dma;
	557	+ size_t cmd_buf_size;
	558	+ void *cmd_buf;
524	559	size_t guid_offs;
525	560	size_t name_offs;
526	561	size_t req_size;
527	562	size_t rsp_size;
	563	+ size_t req_offs;
	564	+ size_t rsp_offs;
528	565	ssize_t status;
529	566
530	567	if (!name_size \|\| !name \|\| !guid)
@@ -545,17 +582,19 @@ static efi_status_t qsee_uefi_get_next_variable(struct qcuefi_client *qcuefi, · 14 unmodified lines
545	582	__array(name, name_size / sizeof(*name))
546	583	);
547	584
548		− req_data = kzalloc(req_size, GFP_KERNEL);
549		− if (!req_data) {
	585	+ cmd_buf_size = qcuefi_buf_align_fields(
	586	+ __reqdata_offs(req_size, &req_offs)
	587	+ __reqdata_offs(rsp_size, &rsp_offs)
	588	+ );
	589	+
	590	+ cmd_buf = qseecom_dma_alloc(qcuefi->client, cmd_buf_size, &cmd_buf_dma, GFP_KERNEL);
	591	+ if (!cmd_buf) {
550	592	efi_status = EFI_OUT_OF_RESOURCES;
551	593	goto out;
552	594	}
553	595
554		− rsp_data = kzalloc(rsp_size, GFP_KERNEL);
555		− if (!rsp_data) {
556		− efi_status = EFI_OUT_OF_RESOURCES;
557		− goto out_free_req;
558		− }
	596	+ req_data = cmd_buf + req_offs;
	597	+ rsp_data = cmd_buf + rsp_offs;
559	598
560	599	req_data->command_id = QSEE_CMD_UEFI_GET_NEXT_VARIABLE;
561	600	req_data->guid_offset = guid_offs;
@@ -572,7 +611,9 @@ static efi_status_t qsee_uefi_get_next_variable(struct qcuefi_client *qcuefi, · 10 unmodified lines
572	611	goto out_free;
573	612	}
574	613
575		− status = qcom_qseecom_app_send(qcuefi->client, req_data, req_size, rsp_data, rsp_size);
	614	+ status = qcom_qseecom_app_send(qcuefi->client,
	615	+ cmd_buf_dma + req_offs, req_size,
	616	+ cmd_buf_dma + rsp_offs, rsp_size);
576	617	if (status) {
577	618	efi_status = EFI_DEVICE_ERROR;
578	619	goto out_free;
@@ -645,9 +686,7 @@ static efi_status_t qsee_uefi_get_next_variable(struct qcuefi_client *qcuefi, · 66 unmodified lines
645	686	}
646	687
647	688	out_free:
648		− kfree(rsp_data);
649		−out_free_req:
650		− kfree(req_data);
	689	+ qseecom_dma_free(qcuefi->client, cmd_buf_size, cmd_buf, cmd_buf_dma);
651	690	out:
652	691	return efi_status;
653	692	}
@@ -659,26 +698,34 @@ static efi_status_t qsee_uefi_query_variable_info(struct qcuefi_client *qcuefi, · 5 unmodified lines
659	698	struct qsee_req_uefi_query_variable_info *req_data;
660	699	struct qsee_rsp_uefi_query_variable_info *rsp_data;
661	700	efi_status_t efi_status = EFI_SUCCESS;
	701	+ dma_addr_t cmd_buf_dma;
	702	+ size_t cmd_buf_size;
	703	+ void *cmd_buf;
	704	+ size_t req_offs;
	705	+ size_t rsp_offs;
662	706	int status;
663	707
664		− req_data = kzalloc(sizeof(*req_data), GFP_KERNEL);
665		− if (!req_data) {
	708	+ cmd_buf_size = qcuefi_buf_align_fields(
	709	+ __reqdata_offs(sizeof(*req_data), &req_offs)
	710	+ __reqdata_offs(sizeof(*rsp_data), &rsp_offs)
	711	+ );
	712	+
	713	+ cmd_buf = qseecom_dma_alloc(qcuefi->client, cmd_buf_size, &cmd_buf_dma, GFP_KERNEL);
	714	+ if (!cmd_buf) {
666	715	efi_status = EFI_OUT_OF_RESOURCES;
667	716	goto out;
668	717	}
669	718
670		− rsp_data = kzalloc(sizeof(*rsp_data), GFP_KERNEL);
671		− if (!rsp_data) {
672		− efi_status = EFI_OUT_OF_RESOURCES;
673		− goto out_free_req;
674		− }
	719	+ req_data = cmd_buf + req_offs;
	720	+ rsp_data = cmd_buf + rsp_offs;
675	721
676	722	req_data->command_id = QSEE_CMD_UEFI_QUERY_VARIABLE_INFO;
677	723	req_data->attributes = attr;
678	724	req_data->length = sizeof(*req_data);
679	725
680		− status = qcom_qseecom_app_send(qcuefi->client, req_data, sizeof(*req_data), rsp_data,
681		− sizeof(*rsp_data));
	726	+ status = qcom_qseecom_app_send(qcuefi->client,
	727	+ cmd_buf_dma + req_offs, sizeof(*req_data),
	728	+ cmd_buf_dma + rsp_offs, sizeof(*rsp_data));
682	729	if (status) {
683	730	efi_status = EFI_DEVICE_ERROR;
684	731	goto out_free;
@@ -711,9 +758,7 @@ static efi_status_t qsee_uefi_query_variable_info(struct qcuefi_client *qcuefi, · 26 unmodified lines
711	758	*max_variable_size = rsp_data->max_variable_size;
712	759
713	760	out_free:
714		− kfree(rsp_data);
715		−out_free_req:
716		− kfree(req_data);
	761	+ qseecom_dma_free(qcuefi->client, cmd_buf_size, cmd_buf, cmd_buf_dma);
717	762	out:
718	763	return efi_status;
719	764	}

drivers/firmware/qcom/qcom_scm.c+6−31

@@ -1576,9 +1576,9 @@ EXPORT_SYMBOL_GPL(qcom_scm_qseecom_app_get_id); · 1575 unmodified lines
1576	1576	/**
1577	1577	* qcom_scm_qseecom_app_send() - Send to and receive data from a given QSEE app.
1578	1578	* @app_id: The ID of the target app.
1579		− * @req: Request buffer sent to the app (must be DMA-mappable).
	1579	+ * @req: DMA address of the request buffer sent to the app.
1580	1580	* @req_size: Size of the request buffer.
1581		− * @rsp: Response buffer, written to by the app (must be DMA-mappable).
	1581	+ * @rsp: DMA address of the response buffer, written to by the app.
1582	1582	* @rsp_size: Size of the response buffer.
1583	1583	*
1584	1584	* Sends a request to the QSEE app associated with the given ID and read back
@@ -1589,33 +1589,13 @@ EXPORT_SYMBOL_GPL(qcom_scm_qseecom_app_get_id); · 4 unmodified lines
1589	1589	*
1590	1590	* Return: Zero on success, nonzero on failure.
1591	1591	*/
1592		−int qcom_scm_qseecom_app_send(u32 app_id, void req, size_t req_size, void rsp,
1593		− size_t rsp_size)
	1592	+int qcom_scm_qseecom_app_send(u32 app_id, dma_addr_t req, size_t req_size,
	1593	+ dma_addr_t rsp, size_t rsp_size)
1594	1594	{
1595	1595	struct qcom_scm_qseecom_resp res = {};
1596	1596	struct qcom_scm_desc desc = {};
1597		− dma_addr_t req_phys;
1598		− dma_addr_t rsp_phys;
1599	1597	int status;
1600	1598
1601		− /* Map request buffer */
1602		− req_phys = dma_map_single(__scm->dev, req, req_size, DMA_TO_DEVICE);
1603		− status = dma_mapping_error(__scm->dev, req_phys);
1604		− if (status) {
1605		− dev_err(__scm->dev, "qseecom: failed to map request buffer\n");
1606		− return status;
1607		− }
1608		−
1609		− /* Map response buffer */
1610		− rsp_phys = dma_map_single(__scm->dev, rsp, rsp_size, DMA_FROM_DEVICE);
1611		− status = dma_mapping_error(__scm->dev, rsp_phys);
1612		− if (status) {
1613		− dma_unmap_single(__scm->dev, req_phys, req_size, DMA_TO_DEVICE);
1614		− dev_err(__scm->dev, "qseecom: failed to map response buffer\n");
1615		− return status;
1616		− }
1617		−
1618		− /* Set up SCM call data */
1619	1599	desc.owner = QSEECOM_TZ_OWNER_TZ_APPS;
1620	1600	desc.svc = QSEECOM_TZ_SVC_APP_ID_PLACEHOLDER;
1621	1601	desc.cmd = QSEECOM_TZ_CMD_APP_SEND;
@@ -1623,18 +1603,13 @@ int qcom_scm_qseecom_app_send(u32 app_id, void req, size_t req_size, void rsp, · 1 unmodified line
1623	1603	QCOM_SCM_RW, QCOM_SCM_VAL,
1624	1604	QCOM_SCM_RW, QCOM_SCM_VAL);
1625	1605	desc.args[0] = app_id;
1626		− desc.args[1] = req_phys;
	1606	+ desc.args[1] = req;
1627	1607	desc.args[2] = req_size;
1628		− desc.args[3] = rsp_phys;
	1608	+ desc.args[3] = rsp;
1629	1609	desc.args[4] = rsp_size;
1630	1610
1631		− /* Perform call */
1632	1611	status = qcom_scm_qseecom_call(&desc, &res);
1633	1612
1634		− /* Unmap buffers */
1635		− dma_unmap_single(__scm->dev, rsp_phys, rsp_size, DMA_FROM_DEVICE);
1636		− dma_unmap_single(__scm->dev, req_phys, req_size, DMA_TO_DEVICE);
1637		−
1638	1613	if (status)
1639	1614	return status;
1640	1615

drivers/soc/mediatek/Kconfig+1−0

@@ -72,6 +72,7 @@ config MTK_SOCINFO · 71 unmodified lines
72	72	tristate "MediaTek SoC Information"
73	73	default y
74	74	depends on NVMEM_MTK_EFUSE
	75	+ select SOC_BUS
75	76	help
76	77	The MediaTek SoC Information (mtk-socinfo) driver provides
77	78	information about the SoC to the userspace including the

drivers/soc/mediatek/mtk-svs.c+5−2

@@ -1768,6 +1768,7 @@ static int svs_bank_resource_setup(struct svs_platform *svsp) · 1767 unmodified lines
1768	1768	const struct svs_bank_pdata *bdata;
1769	1769	struct svs_bank *svsb;
1770	1770	struct dev_pm_opp *opp;
	1771	+ char tz_name_buf[20];
1771	1772	unsigned long freq;
1772	1773	int count, ret;
1773	1774	u32 idx, i;
@@ -1819,10 +1820,12 @@ static int svs_bank_resource_setup(struct svs_platform *svsp) · 45 unmodified lines
1819	1820	}
1820	1821
1821	1822	if (!IS_ERR_OR_NULL(bdata->tzone_name)) {
1822		− svsb->tzd = thermal_zone_get_zone_by_name(bdata->tzone_name);
	1823	+ snprintf(tz_name_buf, ARRAY_SIZE(tz_name_buf),
	1824	+ "%s-thermal", bdata->tzone_name);
	1825	+ svsb->tzd = thermal_zone_get_zone_by_name(tz_name_buf);
1823	1826	if (IS_ERR(svsb->tzd)) {
1824	1827	dev_err(svsb->dev, "cannot get \"%s\" thermal zone\n",
1825		− bdata->tzone_name);
	1828	+ tz_name_buf);
1826	1829	return PTR_ERR(svsb->tzd);
1827	1830	}
1828	1831	}

include/linux/firmware/qcom/qcom_qseecom.h+51−4

@@ -10,6 +10,7 @@ · 9 unmodified lines
10	10	#define __QCOM_QSEECOM_H
11	11
12	12	#include <linux/auxiliary_bus.h>
	13	+#include <linux/dma-mapping.h>
13	14	#include <linux/types.h>
14	15
15	16	#include <linux/firmware/qcom/qcom_scm.h>
@@ -24,12 +25,57 @@ struct qseecom_client { · 8 unmodified lines
24	25	u32 app_id;
25	26	};
26	27
	28	+/**
	29	+ * qseecom_scm_dev() - Get the SCM device associated with the QSEECOM client.
	30	+ * @client: The QSEECOM client device.
	31	+ *
	32	+ * Returns the SCM device under which the provided QSEECOM client device
	33	+ * operates. This function is intended to be used for DMA allocations.
	34	+ */
	35	+static inline struct device qseecom_scm_dev(struct qseecom_client client)
	36	+{
	37	+ return client->aux_dev.dev.parent->parent;
	38	+}
	39	+
	40	+/**
	41	+ * qseecom_dma_alloc() - Allocate DMA memory for a QSEECOM client.
	42	+ * @client: The QSEECOM client to allocate the memory for.
	43	+ * @size: The number of bytes to allocate.
	44	+ * @dma_handle: Pointer to where the DMA address should be stored.
	45	+ * @gfp: Allocation flags.
	46	+ *
	47	+ * Wrapper function for dma_alloc_coherent(), allocating DMA memory usable for
	48	+ * TZ/QSEECOM communication. Refer to dma_alloc_coherent() for details.
	49	+ */
	50	+static inline void qseecom_dma_alloc(struct qseecom_client client, size_t size,
	51	+ dma_addr_t *dma_handle, gfp_t gfp)
	52	+{
	53	+ return dma_alloc_coherent(qseecom_scm_dev(client), size, dma_handle, gfp);
	54	+}
	55	+
	56	+/**
	57	+ * dma_free_coherent() - Free QSEECOM DMA memory.
	58	+ * @client: The QSEECOM client for which the memory has been allocated.
	59	+ * @size: The number of bytes allocated.
	60	+ * @cpu_addr: Virtual memory address to free.
	61	+ * @dma_handle: DMA memory address to free.
	62	+ *
	63	+ * Wrapper function for dma_free_coherent(), freeing memory previously
	64	+ * allocated with qseecom_dma_alloc(). Refer to dma_free_coherent() for
	65	+ * details.
	66	+ */
	67	+static inline void qseecom_dma_free(struct qseecom_client *client, size_t size,
	68	+ void *cpu_addr, dma_addr_t dma_handle)
	69	+{
	70	+ return dma_free_coherent(qseecom_scm_dev(client), size, cpu_addr, dma_handle);
	71	+}
	72	+
27	73	/**
28	74	* qcom_qseecom_app_send() - Send to and receive data from a given QSEE app.
29	75	* @client: The QSEECOM client associated with the target app.
30		− * @req: Request buffer sent to the app (must be DMA-mappable).
	76	+ * @req: DMA address of the request buffer sent to the app.
31	77	* @req_size: Size of the request buffer.
32		− * @rsp: Response buffer, written to by the app (must be DMA-mappable).
	78	+ * @rsp: DMA address of the response buffer, written to by the app.
33	79	* @rsp_size: Size of the response buffer.
34	80	*
35	81	* Sends a request to the QSEE app associated with the given client and read
@@ -43,8 +89,9 @@ struct qseecom_client { · 7 unmodified lines
43	89	*
44	90	* Return: Zero on success, nonzero on failure.
45	91	*/
46		−static inline int qcom_qseecom_app_send(struct qseecom_client client, void req, size_t req_size,
47		− void *rsp, size_t rsp_size)
	92	+static inline int qcom_qseecom_app_send(struct qseecom_client *client,
	93	+ dma_addr_t req, size_t req_size,
	94	+ dma_addr_t rsp, size_t rsp_size)
48	95	{
49	96	return qcom_scm_qseecom_app_send(client->app_id, req, req_size, rsp, rsp_size);
50	97	}

include/linux/firmware/qcom/qcom_scm.h+5−5

@@ -118,8 +118,8 @@ bool qcom_scm_lmh_dcvsh_available(void); · 117 unmodified lines
118	118	#ifdef CONFIG_QCOM_QSEECOM
119	119
120	120	int qcom_scm_qseecom_app_get_id(const char app_name, u32 app_id);
121		−int qcom_scm_qseecom_app_send(u32 app_id, void req, size_t req_size, void rsp,
122		− size_t rsp_size);
	121	+int qcom_scm_qseecom_app_send(u32 app_id, dma_addr_t req, size_t req_size,
	122	+ dma_addr_t rsp, size_t rsp_size);
123	123
124	124	#else /* CONFIG_QCOM_QSEECOM */
125	125
@@ -128,9 +128,9 @@ static inline int qcom_scm_qseecom_app_get_id(const char app_name, u32 app_id) · 2 unmodified lines
128	128	return -EINVAL;
129	129	}
130	130
131		−static inline int qcom_scm_qseecom_app_send(u32 app_id, void *req,
132		− size_t req_size, void *rsp,
133		− size_t rsp_size)
	131	+static inline int qcom_scm_qseecom_app_send(u32 app_id,
	132	+ dma_addr_t req, size_t req_size,
	133	+ dma_addr_t rsp, size_t rsp_size)
134	134	{
135	135	return -EINVAL;
136	136	}