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drm/etnaviv: add further minor features and varyings count

Export further minor feature bitmasks and the varyings count from the GPU specifications registers to userspace.

Russell King committed 10 years ago

Commit 602eb481 parent 472f79d3 files · +73 −1Browse files

Unified · Split

3 files
  1. drivers/gpu/drm/etnaviv/etnaviv_gpu.c +61 −1
  2. drivers/gpu/drm/etnaviv/etnaviv_gpu.h +9 −0
  3. include/uapi/drm/etnaviv_drm.h +3 −0
drivers/gpu/drm/etnaviv/etnaviv_gpu.c+61−1
@@ -72,6 +72,14 @@ int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value) · 71 unmodified lines
72 *value = gpu->identity.minor_features3;72 *value = gpu->identity.minor_features3;
73 break;73 break;
74 74
75 case ETNAVIV_PARAM_GPU_FEATURES_5:
76 *value = gpu->identity.minor_features4;
77 break;
78
79 case ETNAVIV_PARAM_GPU_FEATURES_6:
80 *value = gpu->identity.minor_features5;
81 break;
82
75 case ETNAVIV_PARAM_GPU_STREAM_COUNT:83 case ETNAVIV_PARAM_GPU_STREAM_COUNT:
76 *value = gpu->identity.stream_count;84 *value = gpu->identity.stream_count;
77 break;85 break;
@@ -112,6 +120,10 @@ int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value) · 34 unmodified lines
112 *value = gpu->identity.num_constants;120 *value = gpu->identity.num_constants;
113 break;121 break;
114 122
123 case ETNAVIV_PARAM_GPU_NUM_VARYINGS:
124 *value = gpu->identity.varyings_count;
125 break;
126
115 default:127 default:
116 DBG("%s: invalid param: %u", dev_name(gpu->dev), param);128 DBG("%s: invalid param: %u", dev_name(gpu->dev), param);
117 return -EINVAL;129 return -EINVAL;
@@ -131,10 +143,13 @@ static void etnaviv_hw_specs(struct etnaviv_gpu *gpu) · 13 unmodified lines
131{143{
132 if (gpu->identity.minor_features0 &144 if (gpu->identity.minor_features0 &
133 chipMinorFeatures0_MORE_MINOR_FEATURES) {145 chipMinorFeatures0_MORE_MINOR_FEATURES) {
134 u32 specs[2];146 u32 specs[4];
147 unsigned int streams;
135 148
136 specs[0] = gpu_read(gpu, VIVS_HI_CHIP_SPECS);149 specs[0] = gpu_read(gpu, VIVS_HI_CHIP_SPECS);
137 specs[1] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_2);150 specs[1] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_2);
151 specs[2] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_3);
152 specs[3] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_4);
138 153
139 gpu->identity.stream_count = etnaviv_field(specs[0],154 gpu->identity.stream_count = etnaviv_field(specs[0],
140 VIVS_HI_CHIP_SPECS_STREAM_COUNT);155 VIVS_HI_CHIP_SPECS_STREAM_COUNT);
@@ -158,6 +173,15 @@ static void etnaviv_hw_specs(struct etnaviv_gpu *gpu) · 17 unmodified lines
158 VIVS_HI_CHIP_SPECS_2_INSTRUCTION_COUNT);173 VIVS_HI_CHIP_SPECS_2_INSTRUCTION_COUNT);
159 gpu->identity.num_constants = etnaviv_field(specs[1],174 gpu->identity.num_constants = etnaviv_field(specs[1],
160 VIVS_HI_CHIP_SPECS_2_NUM_CONSTANTS);175 VIVS_HI_CHIP_SPECS_2_NUM_CONSTANTS);
176
177 gpu->identity.varyings_count = etnaviv_field(specs[2],
178 VIVS_HI_CHIP_SPECS_3_VARYINGS_COUNT);
179
180 /* This overrides the value from older register if non-zero */
181 streams = etnaviv_field(specs[3],
182 VIVS_HI_CHIP_SPECS_4_STREAM_COUNT);
183 if (streams)
184 gpu->identity.stream_count = streams;
161 }185 }
162 186
163 /* Fill in the stream count if not specified */187 /* Fill in the stream count if not specified */
@@ -239,6 +263,30 @@ static void etnaviv_hw_specs(struct etnaviv_gpu *gpu) · 75 unmodified lines
239 263
240 if (gpu->identity.num_constants == 0)264 if (gpu->identity.num_constants == 0)
241 gpu->identity.num_constants = 168;265 gpu->identity.num_constants = 168;
266
267 if (gpu->identity.varyings_count == 0) {
268 if (gpu->identity.minor_features1 & chipMinorFeatures1_HALTI0)
269 gpu->identity.varyings_count = 12;
270 else
271 gpu->identity.varyings_count = 8;
272 }
273
274 /*
275 * For some cores, two varyings are consumed for position, so the
276 * maximum varying count needs to be reduced by one.
277 */
278 if (etnaviv_is_model_rev(gpu, GC5000, 0x5434) ||
279 etnaviv_is_model_rev(gpu, GC4000, 0x5222) ||
280 etnaviv_is_model_rev(gpu, GC4000, 0x5245) ||
281 etnaviv_is_model_rev(gpu, GC4000, 0x5208) ||
282 etnaviv_is_model_rev(gpu, GC3000, 0x5435) ||
283 etnaviv_is_model_rev(gpu, GC2200, 0x5244) ||
284 etnaviv_is_model_rev(gpu, GC2100, 0x5108) ||
285 etnaviv_is_model_rev(gpu, GC2000, 0x5108) ||
286 etnaviv_is_model_rev(gpu, GC1500, 0x5246) ||
287 etnaviv_is_model_rev(gpu, GC880, 0x5107) ||
288 etnaviv_is_model_rev(gpu, GC880, 0x5106))
289 gpu->identity.varyings_count -= 1;
242}290}
243 291
244static void etnaviv_hw_identify(struct etnaviv_gpu *gpu)292static void etnaviv_hw_identify(struct etnaviv_gpu *gpu)
@@ -305,6 +353,8 @@ static void etnaviv_hw_identify(struct etnaviv_gpu *gpu) · 60 unmodified lines
305 gpu->identity.minor_features1 = 0;353 gpu->identity.minor_features1 = 0;
306 gpu->identity.minor_features2 = 0;354 gpu->identity.minor_features2 = 0;
307 gpu->identity.minor_features3 = 0;355 gpu->identity.minor_features3 = 0;
356 gpu->identity.minor_features4 = 0;
357 gpu->identity.minor_features5 = 0;
308 } else358 } else
309 gpu->identity.minor_features0 =359 gpu->identity.minor_features0 =
310 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_0);360 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_0);
@@ -317,6 +367,10 @@ static void etnaviv_hw_identify(struct etnaviv_gpu *gpu) · 6 unmodified lines
317 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_2);367 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_2);
318 gpu->identity.minor_features3 =368 gpu->identity.minor_features3 =
319 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_3);369 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_3);
370 gpu->identity.minor_features4 =
371 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_4);
372 gpu->identity.minor_features5 =
373 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_5);
320 }374 }
321 375
322 /* GC600 idle register reports zero bits where modules aren't present */376 /* GC600 idle register reports zero bits where modules aren't present */
@@ -645,6 +699,10 @@ int etnaviv_gpu_debugfs(struct etnaviv_gpu *gpu, struct seq_file *m) · 322 unmodified lines
645 gpu->identity.minor_features2);699 gpu->identity.minor_features2);
646 seq_printf(m, "\t minor_features3: 0x%08x\n",700 seq_printf(m, "\t minor_features3: 0x%08x\n",
647 gpu->identity.minor_features3);701 gpu->identity.minor_features3);
702 seq_printf(m, "\t minor_features4: 0x%08x\n",
703 gpu->identity.minor_features4);
704 seq_printf(m, "\t minor_features5: 0x%08x\n",
705 gpu->identity.minor_features5);
648 706
649 seq_puts(m, "\tspecs\n");707 seq_puts(m, "\tspecs\n");
650 seq_printf(m, "\t stream_count: %d\n",708 seq_printf(m, "\t stream_count: %d\n",
@@ -667,6 +725,8 @@ int etnaviv_gpu_debugfs(struct etnaviv_gpu *gpu, struct seq_file *m) · 16 unmodified lines
667 gpu->identity.instruction_count);725 gpu->identity.instruction_count);
668 seq_printf(m, "\t num_constants: %d\n",726 seq_printf(m, "\t num_constants: %d\n",
669 gpu->identity.num_constants);727 gpu->identity.num_constants);
728 seq_printf(m, "\t varyings_count: %d\n",
729 gpu->identity.varyings_count);
670 730
671 seq_printf(m, "\taxi: 0x%08x\n", axi);731 seq_printf(m, "\taxi: 0x%08x\n", axi);
672 seq_printf(m, "\tidle: 0x%08x\n", idle);732 seq_printf(m, "\tidle: 0x%08x\n", idle);
drivers/gpu/drm/etnaviv/etnaviv_gpu.h+9−0
@@ -46,6 +46,12 @@ struct etnaviv_chip_identity { · 45 unmodified lines
46 /* Supported minor feature 3 fields. */46 /* Supported minor feature 3 fields. */
47 u32 minor_features3;47 u32 minor_features3;
48 48
49 /* Supported minor feature 4 fields. */
50 u32 minor_features4;
51
52 /* Supported minor feature 5 fields. */
53 u32 minor_features5;
54
49 /* Number of streams supported. */55 /* Number of streams supported. */
50 u32 stream_count;56 u32 stream_count;
51 57
@@ -75,6 +81,9 @@ struct etnaviv_chip_identity { · 23 unmodified lines
75 81
76 /* Buffer size */82 /* Buffer size */
77 u32 buffer_size;83 u32 buffer_size;
84
85 /* Number of varyings */
86 u8 varyings_count;
78};87};
79 88
80struct etnaviv_event {89struct etnaviv_event {
include/uapi/drm/etnaviv_drm.h+3−0
@@ -48,6 +48,8 @@ struct drm_etnaviv_timespec { · 47 unmodified lines
48#define ETNAVIV_PARAM_GPU_FEATURES_2 0x0548#define ETNAVIV_PARAM_GPU_FEATURES_2 0x05
49#define ETNAVIV_PARAM_GPU_FEATURES_3 0x0649#define ETNAVIV_PARAM_GPU_FEATURES_3 0x06
50#define ETNAVIV_PARAM_GPU_FEATURES_4 0x0750#define ETNAVIV_PARAM_GPU_FEATURES_4 0x07
51#define ETNAVIV_PARAM_GPU_FEATURES_5 0x08
52#define ETNAVIV_PARAM_GPU_FEATURES_6 0x09
51 53
52#define ETNAVIV_PARAM_GPU_STREAM_COUNT 0x1054#define ETNAVIV_PARAM_GPU_STREAM_COUNT 0x10
53#define ETNAVIV_PARAM_GPU_REGISTER_MAX 0x1155#define ETNAVIV_PARAM_GPU_REGISTER_MAX 0x11
@@ -59,6 +61,7 @@ struct drm_etnaviv_timespec { · 5 unmodified lines
59#define ETNAVIV_PARAM_GPU_BUFFER_SIZE 0x1761#define ETNAVIV_PARAM_GPU_BUFFER_SIZE 0x17
60#define ETNAVIV_PARAM_GPU_INSTRUCTION_COUNT 0x1862#define ETNAVIV_PARAM_GPU_INSTRUCTION_COUNT 0x18
61#define ETNAVIV_PARAM_GPU_NUM_CONSTANTS 0x1963#define ETNAVIV_PARAM_GPU_NUM_CONSTANTS 0x19
64#define ETNAVIV_PARAM_GPU_NUM_VARYINGS 0x1a
62 65
63#define ETNA_MAX_PIPES 466#define ETNA_MAX_PIPES 4
64 67