From Nicolas Ferre: Here are fixes for AT91 that are mainly related to device tree. One RM9200 setup option is the only C code change. Some documentation changes can clarify the pinctrl use. Then, some defconfig modifications are allowing the affected platforms to boot. * tag 'at91-fixes' of git://github.com/at91linux/linux-at91: ARM: at91/dts: correct comment in at91sam9x5.dtsi for mii ARM: at91/at91_dt_defconfig: add at91sam9n12 SoC to DT defconfig ARM: at91/at91_dt_defconfig: remove memory specification to cmdline ARM: at91/dts: add macb mii pinctrl config for kizbox ARM: at91: rm9200: remake the BGA as default version ARM: at91: fix gpios on i2c-gpio for RM9200 DT ARM: at91/at91sam9x5 DTS: add SCK USART pins ARM: at91/at91sam9x5 DTS: correct wrong PIO BANK values on u(s)arts ARM: at91/at91-pinctrl documentation: fix typo and add some details
Unified · Split
| @@ -81,7 +81,8 @@ PA31 TXD4 · 80 unmodified lines | ||
| 81 | 81 | Required properties for pin configuration node: |
| 82 | 82 | - atmel,pins: 4 integers array, represents a group of pins mux and config |
| 83 | 83 | setting. The format is atmel,pins = <PIN_BANK PIN_BANK_NUM PERIPH CONFIG>. |
| 84 | − The PERIPH 0 means gpio. | |
| 84 | + The PERIPH 0 means gpio, PERIPH 1 is periph A, PERIPH 2 is periph B... | |
| 85 | + PIN_BANK 0 is pioA, PIN_BANK 1 is pioB... | |
| 85 | 86 | |
| 86 | 87 | Bits used for CONFIG: |
| 87 | 88 | PULL_UP (1 << 0): indicate this pin need a pull up. |
| @@ -126,7 +127,7 @@ pinctrl@fffff400 { · 38 unmodified lines | ||
| 126 | 127 | pinctrl_dbgu: dbgu-0 { |
| 127 | 128 | atmel,pins = |
| 128 | 129 | <1 14 0x1 0x0 /* PB14 periph A */ |
| 129 | − 1 15 0x1 0x1>; /* PB15 periph with pullup */ | |
| 130 | + 1 15 0x1 0x1>; /* PB15 periph A with pullup */ | |
| 130 | 131 | }; |
| 131 | 132 | }; |
| 132 | 133 | }; |
| @@ -336,8 +336,8 @@ · 335 unmodified lines | ||
| 336 | 336 | |
| 337 | 337 | i2c@0 { |
| 338 | 338 | compatible = "i2c-gpio"; |
| 339 | − gpios = <&pioA 23 0 /* sda */ | |
| 340 | − &pioA 24 0 /* scl */ | |
| 339 | + gpios = <&pioA 25 0 /* sda */ | |
| 340 | + &pioA 26 0 /* scl */ | |
| 341 | 341 | >; |
| 342 | 342 | i2c-gpio,sda-open-drain; |
| 343 | 343 | i2c-gpio,scl-open-drain; |
| @@ -143,6 +143,11 @@ · 142 unmodified lines | ||
| 143 | 143 | atmel,pins = |
| 144 | 144 | <0 3 0x1 0x0>; /* PA3 periph A */ |
| 145 | 145 | }; |
| 146 | + | |
| 147 | + pinctrl_usart0_sck: usart0_sck-0 { | |
| 148 | + atmel,pins = | |
| 149 | + <0 4 0x1 0x0>; /* PA4 periph A */ | |
| 150 | + }; | |
| 146 | 151 | }; |
| 147 | 152 | |
| 148 | 153 | usart1 { |
| @@ -154,12 +159,17 @@ · 5 unmodified lines | ||
| 154 | 159 | |
| 155 | 160 | pinctrl_usart1_rts: usart1_rts-0 { |
| 156 | 161 | atmel,pins = |
| 157 | − <3 27 0x3 0x0>; /* PC27 periph C */ | |
| 162 | + <2 27 0x3 0x0>; /* PC27 periph C */ | |
| 158 | 163 | }; |
| 159 | 164 | |
| 160 | 165 | pinctrl_usart1_cts: usart1_cts-0 { |
| 161 | 166 | atmel,pins = |
| 162 | − <3 28 0x3 0x0>; /* PC28 periph C */ | |
| 167 | + <2 28 0x3 0x0>; /* PC28 periph C */ | |
| 168 | + }; | |
| 169 | + | |
| 170 | + pinctrl_usart1_sck: usart1_sck-0 { | |
| 171 | + atmel,pins = | |
| 172 | + <2 28 0x3 0x0>; /* PC29 periph C */ | |
| 163 | 173 | }; |
| 164 | 174 | }; |
| 165 | 175 | |
| @@ -172,46 +182,56 @@ · 6 unmodified lines | ||
| 172 | 182 | |
| 173 | 183 | pinctrl_uart2_rts: uart2_rts-0 { |
| 174 | 184 | atmel,pins = |
| 175 | − <0 0 0x2 0x0>; /* PB0 periph B */ | |
| 185 | + <1 0 0x2 0x0>; /* PB0 periph B */ | |
| 176 | 186 | }; |
| 177 | 187 | |
| 178 | 188 | pinctrl_uart2_cts: uart2_cts-0 { |
| 179 | 189 | atmel,pins = |
| 180 | − <0 1 0x2 0x0>; /* PB1 periph B */ | |
| 190 | + <1 1 0x2 0x0>; /* PB1 periph B */ | |
| 191 | + }; | |
| 192 | + | |
| 193 | + pinctrl_usart2_sck: usart2_sck-0 { | |
| 194 | + atmel,pins = | |
| 195 | + <1 2 0x2 0x0>; /* PB2 periph B */ | |
| 181 | 196 | }; |
| 182 | 197 | }; |
| 183 | 198 | |
| 184 | 199 | usart3 { |
| 185 | 200 | pinctrl_uart3: usart3-0 { |
| 186 | 201 | atmel,pins = |
| 187 | − <3 23 0x2 0x1 /* PC22 periph B with pullup */ | |
| 188 | − 3 23 0x2 0x0>; /* PC23 periph B */ | |
| 202 | + <2 23 0x2 0x1 /* PC22 periph B with pullup */ | |
| 203 | + 2 23 0x2 0x0>; /* PC23 periph B */ | |
| 189 | 204 | }; |
| 190 | 205 | |
| 191 | 206 | pinctrl_usart3_rts: usart3_rts-0 { |
| 192 | 207 | atmel,pins = |
| 193 | − <3 24 0x2 0x0>; /* PC24 periph B */ | |
| 208 | + <2 24 0x2 0x0>; /* PC24 periph B */ | |
| 194 | 209 | }; |
| 195 | 210 | |
| 196 | 211 | pinctrl_usart3_cts: usart3_cts-0 { |
| 197 | 212 | atmel,pins = |
| 198 | − <3 25 0x2 0x0>; /* PC25 periph B */ | |
| 213 | + <2 25 0x2 0x0>; /* PC25 periph B */ | |
| 214 | + }; | |
| 215 | + | |
| 216 | + pinctrl_usart3_sck: usart3_sck-0 { | |
| 217 | + atmel,pins = | |
| 218 | + <2 26 0x2 0x0>; /* PC26 periph B */ | |
| 199 | 219 | }; |
| 200 | 220 | }; |
| 201 | 221 | |
| 202 | 222 | uart0 { |
| 203 | 223 | pinctrl_uart0: uart0-0 { |
| 204 | 224 | atmel,pins = |
| 205 | − <3 8 0x3 0x0 /* PC8 periph C */ | |
| 206 | − 3 9 0x3 0x1>; /* PC9 periph C with pullup */ | |
| 225 | + <2 8 0x3 0x0 /* PC8 periph C */ | |
| 226 | + 2 9 0x3 0x1>; /* PC9 periph C with pullup */ | |
| 207 | 227 | }; |
| 208 | 228 | }; |
| 209 | 229 | |
| 210 | 230 | uart1 { |
| 211 | 231 | pinctrl_uart1: uart1-0 { |
| 212 | 232 | atmel,pins = |
| 213 | − <3 16 0x3 0x0 /* PC16 periph C */ | |
| 214 | − 3 17 0x3 0x1>; /* PC17 periph C with pullup */ | |
| 233 | + <2 16 0x3 0x0 /* PC16 periph C */ | |
| 234 | + 2 17 0x3 0x1>; /* PC17 periph C with pullup */ | |
| 215 | 235 | }; |
| 216 | 236 | }; |
| 217 | 237 | |
| @@ -240,14 +260,14 @@ · 22 unmodified lines | ||
| 240 | 260 | |
| 241 | 261 | pinctrl_macb0_rmii_mii: macb0_rmii_mii-0 { |
| 242 | 262 | atmel,pins = |
| 243 | − <1 8 0x1 0x0 /* PA8 periph A */ | |
| 244 | − 1 11 0x1 0x0 /* PA11 periph A */ | |
| 245 | − 1 12 0x1 0x0 /* PA12 periph A */ | |
| 246 | − 1 13 0x1 0x0 /* PA13 periph A */ | |
| 247 | − 1 14 0x1 0x0 /* PA14 periph A */ | |
| 248 | − 1 15 0x1 0x0 /* PA15 periph A */ | |
| 249 | − 1 16 0x1 0x0 /* PA16 periph A */ | |
| 250 | − 1 17 0x1 0x0>; /* PA17 periph A */ | |
| 263 | + <1 8 0x1 0x0 /* PB8 periph A */ | |
| 264 | + 1 11 0x1 0x0 /* PB11 periph A */ | |
| 265 | + 1 12 0x1 0x0 /* PB12 periph A */ | |
| 266 | + 1 13 0x1 0x0 /* PB13 periph A */ | |
| 267 | + 1 14 0x1 0x0 /* PB14 periph A */ | |
| 268 | + 1 15 0x1 0x0 /* PB15 periph A */ | |
| 269 | + 1 16 0x1 0x0 /* PB16 periph A */ | |
| 270 | + 1 17 0x1 0x0>; /* PB17 periph A */ | |
| 251 | 271 | }; |
| 252 | 272 | }; |
| 253 | 273 | |
| @@ -48,6 +48,8 @@ · 47 unmodified lines | ||
| 48 | 48 | |
| 49 | 49 | macb0: ethernet@fffc4000 { |
| 50 | 50 | phy-mode = "mii"; |
| 51 | + pinctrl-0 = <&pinctrl_macb_rmii | |
| 52 | + &pinctrl_macb_rmii_mii_alt>; | |
| 51 | 53 | status = "okay"; |
| 52 | 54 | }; |
| 53 | 55 | |
| @@ -19,6 +19,7 @@ CONFIG_SOC_AT91SAM9260=y · 18 unmodified lines | ||
| 19 | 19 | CONFIG_SOC_AT91SAM9263=y |
| 20 | 20 | CONFIG_SOC_AT91SAM9G45=y |
| 21 | 21 | CONFIG_SOC_AT91SAM9X5=y |
| 22 | +CONFIG_SOC_AT91SAM9N12=y | |
| 22 | 23 | CONFIG_MACH_AT91SAM_DT=y |
| 23 | 24 | CONFIG_AT91_PROGRAMMABLE_CLOCKS=y |
| 24 | 25 | CONFIG_AT91_TIMER_HZ=128 |
| @@ -31,7 +32,7 @@ CONFIG_ZBOOT_ROM_TEXT=0x0 · 6 unmodified lines | ||
| 31 | 32 | CONFIG_ZBOOT_ROM_BSS=0x0 |
| 32 | 33 | CONFIG_ARM_APPENDED_DTB=y |
| 33 | 34 | CONFIG_ARM_ATAG_DTB_COMPAT=y |
| 34 | −CONFIG_CMDLINE="mem=128M console=ttyS0,115200 initrd=0x21100000,25165824 root=/dev/ram0 rw" | |
| 35 | +CONFIG_CMDLINE="console=ttyS0,115200 initrd=0x21100000,25165824 root=/dev/ram0 rw" | |
| 35 | 36 | CONFIG_KEXEC=y |
| 36 | 37 | CONFIG_AUTO_ZRELADDR=y |
| 37 | 38 | # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set |
| @@ -105,6 +105,8 @@ static void __init soc_detect(u32 dbgu_base) · 104 unmodified lines | ||
| 105 | 105 | switch (socid) { |
| 106 | 106 | case ARCH_ID_AT91RM9200: |
| 107 | 107 | at91_soc_initdata.type = AT91_SOC_RM9200; |
| 108 | + if (at91_soc_initdata.subtype == AT91_SOC_SUBTYPE_NONE) | |
| 109 | + at91_soc_initdata.subtype = AT91_SOC_RM9200_BGA; | |
| 108 | 110 | at91_boot_soc = at91rm9200_soc; |
| 109 | 111 | break; |
| 110 | 112 | |