Merge tag 'mfd-next-5.20' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd

Pull MFD updates from Lee Jones: "Core Framework: - Change maintainer email address - Use acpi_dev_for_each_child() helper to walk the ACPI list New Device Support: - BCM2711 RPiVid ASB in Broadcom BCM2835 - MT8195 dual-core RISC-V MCU in Chrome OS Embedded Controller - Regulator, RTC and Keys in MediaTek MT6357 PMIC - GPIO in X-Powers AXP20x PMIC - MT6331 and MT6332 in MediaTek MT6357 PMIC - Intel Meteor Lake-P PCI in Intel LPSS PCI New Functionality: - Add support for non-ACPI platforms; lpc_ich Fix-ups: - Use platform data instead of hard-coded values; bcm2835-pm - Make use of BIT/GENMASK macros; intel_soc_pmic_bxtwc - Use dev_err_probe() helper; intel_soc_pmic_chtwc, intel_soc_pmic_bxtwc - Use provided generic APIs / helpers; lpc_ich - Clean-up .remove() return values; asic3, t7l66xb, tc6387xb, tc6393xb - Use correct formatting specifiers; syscon - Replace sprintf() with sysfs_emit(); intel_soc_pmic_bxtwc - Automatically detect and fill USB endpoint pointers; dln2 - Use more appropriate dev/platform/spi resources APIs; intel_soc_pmic_bxtwc - Make use of pm_sleep_ptr(); intel_soc_pmic_chtwc, intel_soc_pmic_bxtwc - Improve error handling; intel_soc_pmic_bxtwc - Use core driver API to create groups; intel_soc_pmic_bxtwc - Kconfig fix-ups; MFD_SUN6I_PRCM - Admin: whitespace/email addresses/etc; max77714, db8500-prcmu, ipaq-micro, intel_soc_pmic_bxtwc - Remove duplicate/unused code/functionality; lpc_ich, twl-core, qcom-pm8008, intel_soc_pmic_bxtwc - DT fix-ups / conversions; da9063, ti,j721e-system-controller, st,stm32-timers, mt6397, qcom,tcsr, mps,mp2629, qcom-pm8xxx, fsl,imx8qxp-csr Bug Fixes: - Fix of_node reference leak; max77620" * tag 'mfd-next-5.20' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd: (49 commits) dt-bindings: mfd: stm32-timers: Move fixed string node names under 'properties' dt-bindings: mfd: st,stm32-timers: Correct 'resets' property name dt-bindings: mfd: syscon: Update Lee Jones' email address MAINTAINERS: Use Lee Jones' kernel.org address for Syscon submissions MAINTAINERS: Use Lee Jones' kernel.org address for MFD submissions mfd: sun6i-prcm: Update Kconfig description mfd: intel_soc_pmic_bxtwc: Fix spelling in the comment mfd: intel_soc_pmic_bxtwc: Drop unneeded casting mfd: intel_soc_pmic_bxtwc: Use sysfs_emit() instead of sprintf() mfd: intel_soc_pmic_bxtwc: Use bits.h macros for all masks mfd: intel_soc_pmic_bxtwc: Drop redundant ACPI_PTR() mfd: intel_soc_pmic_bxtwc: Switch from CONFIG_PM_SLEEP guards to pm_sleep_ptr() etc mfd: intel_soc_pmic_bxtwc: Extend use of temporary variable for struct device mfd: intel_soc_pmic_bxtwc: Use dev_err_probe() mfd: intel_soc_pmic_bxtwc: Convert to use platform_get/set_drvdata() mfd: intel_soc_pmic_bxtwc: Create sysfs attributes using core driver's facility mfd: intel_soc_pmic_bxtwc: Don't shadow error codes in show()/store() mfd: intel-lpss: Add Intel Meteor Lake-P PCI IDs mfd: mt6397: Add basic support for MT6331+MT6332 PMIC mfd: axp20x: Add AXP221/AXP223/AXP809 GPIO cells ...

Linus Torvalds committed 4 years ago

Commit 613b2a82 parents 668c3c2 ae4ccae49 files · +3565 −762Browse files

Unified · Split

49 files

Documentation/devicetree/bindings/mfd/da9063.txt +0 −114
Documentation/devicetree/bindings/mfd/dlg,da9063.yaml +132 −0
Documentation/devicetree/bindings/mfd/mps,mp2629.yaml +3 −1
Documentation/devicetree/bindings/mfd/mt6397.txt +6 −2
Documentation/devicetree/bindings/mfd/qcom,tcsr.txt +0 −24
Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml +50 −0
Documentation/devicetree/bindings/mfd/qcom-pm8xxx.yaml +1 −1
Documentation/devicetree/bindings/mfd/st,stm32-lptimer.yaml +14 −14
Documentation/devicetree/bindings/mfd/st,stm32-timers.yaml +26 −11
Documentation/devicetree/bindings/mfd/syscon.yaml +1 −1
Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml +12 −0
Documentation/devicetree/bindings/trivial-devices.yaml +0 −2
MAINTAINERS +4 −4
arch/arm/mach-pxa/eseries.c +1 −3
arch/arm/mach-pxa/tosa.c +1 −3
drivers/mfd/Kconfig +3 −2
drivers/mfd/asic3.c +3 −6
drivers/mfd/axp20x.c +9 −0
drivers/mfd/cros_ec_dev.c +5 −0
drivers/mfd/db8500-prcmu.c +1 −1
drivers/mfd/dln2.c +4 −13
drivers/mfd/intel-lpss-pci.c +13 −0
drivers/mfd/intel_soc_pmic_bxtwc.c +75 −119
drivers/mfd/intel_soc_pmic_chtwc.c +11 −16
drivers/mfd/max77620.c +2 −0
drivers/mfd/max77714.c +2 −2
drivers/mfd/mt6358-irq.c +24 −0
drivers/mfd/mt6397-core.c +91 −0
drivers/mfd/mt6397-irq.c +8 −1
drivers/mfd/qcom-pm8008.c +20 −33
drivers/mfd/syscon.c +1 −2
drivers/mfd/t7l66xb.c +1 −5
drivers/mfd/tc6393xb.c +2 −3
drivers/mfd/twl-core.c +5 −318
include/linux/mfd/ipaq-micro.h +2 −2
include/linux/mfd/max77714.h +1 −1
include/linux/mfd/mt6331/core.h +40 −0
include/linux/mfd/mt6331/registers.h +584 −0
include/linux/mfd/mt6332/core.h +65 −0
include/linux/mfd/mt6332/registers.h +642 −0
include/linux/mfd/mt6357/core.h +119 −0
include/linux/mfd/mt6357/registers.h +1574 −0
include/linux/mfd/mt6397/core.h +3 −0
include/linux/mfd/t7l66xb.h +0 −1
include/linux/mfd/tc6387xb.h +0 −1
include/linux/mfd/tc6393xb.h +1 −1
include/linux/mfd/twl.h +0 −55
include/linux/platform_data/cros_ec_commands.h +2 −0
include/linux/platform_data/cros_ec_proto.h +1 −0

Documentation/devicetree/bindings/mfd/da9063.txt+0−114

@@ -1,114 +0,0 @@
1		−* Dialog DA9063/DA9063L Power Management Integrated Circuit (PMIC)
2		−
3		−DA9063 consists of a large and varied group of sub-devices (I2C Only):
4		−
5		−Device Supply Names Description
6		−------ ------------ -----------
7		−da9063-regulator : : LDOs & BUCKs
8		−da9063-onkey : : On Key
9		−da9063-rtc : : Real-Time Clock (DA9063 only)
10		−da9063-watchdog : : Watchdog
11		−
12		−======
13		−
14		−Required properties:
15		−
16		−- compatible : Should be "dlg,da9063" or "dlg,da9063l"
17		−- reg : Specifies the I2C slave address (this defaults to 0x58 but it can be
18		− modified to match the chip's OTP settings).
19		−- interrupts : IRQ line information.
20		−- interrupt-controller
21		−
22		−Sub-nodes:
23		−
24		−- regulators : This node defines the settings for the LDOs and BUCKs.
25		− The DA9063(L) regulators are bound using their names listed below:
26		−
27		− bcore1 : BUCK CORE1
28		− bcore2 : BUCK CORE2
29		− bpro : BUCK PRO
30		− bmem : BUCK MEM
31		− bio : BUCK IO
32		− bperi : BUCK PERI
33		− ldo1 : LDO_1 (DA9063 only)
34		− ldo2 : LDO_2 (DA9063 only)
35		− ldo3 : LDO_3
36		− ldo4 : LDO_4 (DA9063 only)
37		− ldo5 : LDO_5 (DA9063 only)
38		− ldo6 : LDO_6 (DA9063 only)
39		− ldo7 : LDO_7
40		− ldo8 : LDO_8
41		− ldo9 : LDO_9
42		− ldo10 : LDO_10 (DA9063 only)
43		− ldo11 : LDO_11
44		−
45		− The component follows the standard regulator framework and the bindings
46		− details of individual regulator device can be found in:
47		− Documentation/devicetree/bindings/regulator/regulator.txt
48		−
49		−- rtc : This node defines settings for the Real-Time Clock associated with
50		− the DA9063 only. The RTC is not present in DA9063L. There are currently
51		− no entries in this binding, however compatible = "dlg,da9063-rtc" should
52		− be added if a node is created.
53		−
54		−- onkey : This node defines the OnKey settings for controlling the key
55		− functionality of the device. The node should contain the compatible property
56		− with the value "dlg,da9063-onkey".
57		−
58		− Optional onkey properties:
59		−
60		− - dlg,disable-key-power : Disable power-down using a long key-press. If this
61		− entry exists the OnKey driver will remove support for the KEY_POWER key
62		− press. If this entry does not exist then by default the key-press
63		− triggered power down is enabled and the OnKey will support both KEY_POWER
64		− and KEY_SLEEP.
65		−
66		−- watchdog : This node defines settings for the Watchdog timer associated
67		− with the DA9063 and DA9063L. The node should contain the compatible property
68		− with the value "dlg,da9063-watchdog".
69		−
70		− Optional watchdog properties:
71		− - dlg,use-sw-pm: Add this property to disable the watchdog during suspend.
72		− Only use this option if you can't use the watchdog automatic suspend
73		− function during a suspend (see register CONTROL_B).
74		−
75		−Example:
76		−
77		− pmic0: da9063@58 {
78		− compatible = "dlg,da9063"
79		− reg = <0x58>;
80		− interrupt-parent = <&gpio6>;
81		− interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
82		− interrupt-controller;
83		−
84		− rtc {
85		− compatible = "dlg,da9063-rtc";
86		− };
87		−
88		− wdt {
89		− compatible = "dlg,da9063-watchdog";
90		− };
91		−
92		− onkey {
93		− compatible = "dlg,da9063-onkey";
94		− dlg,disable-key-power;
95		− };
96		−
97		− regulators {
98		− DA9063_BCORE1: bcore1 {
99		− regulator-name = "BCORE1";
100		− regulator-min-microvolt = <300000>;
101		− regulator-max-microvolt = <1570000>;
102		− regulator-min-microamp = <500000>;
103		− regulator-max-microamp = <2000000>;
104		− regulator-boot-on;
105		− };
106		− DA9063_LDO11: ldo11 {
107		− regulator-name = "LDO_11";
108		− regulator-min-microvolt = <900000>;
109		− regulator-max-microvolt = <3600000>;
110		− regulator-boot-on;
111		− };
112		− };
113		− };
114		−

Documentation/devicetree/bindings/mfd/dlg,da9063.yaml+132−0

@@ -0,0 +1,132 @@
	1	+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
	2	+%YAML 1.2
	3	+---
	4	+$id: http://devicetree.org/schemas/mfd/dlg,da9063.yaml#
	5	+$schema: http://devicetree.org/meta-schemas/core.yaml#
	6	+
	7	+title: Dialog DA9063/DA9063L Power Management Integrated Circuit (PMIC)
	8	+
	9	+maintainers:
	10	+ - Steve Twiss <stwiss.opensource@diasemi.com>
	11	+
	12	+description: \|
	13	+ For device-tree bindings of other sub-modules refer to the binding documents
	14	+ under the respective sub-system directories.
	15	+
	16	+properties:
	17	+ compatible:
	18	+ enum:
	19	+ - dlg,da9063
	20	+ - dlg,da9063l
	21	+
	22	+ reg:
	23	+ maxItems: 1
	24	+
	25	+ interrupts:
	26	+ maxItems: 1
	27	+
	28	+ interrupt-controller: true
	29	+
	30	+ "#interrupt-cells":
	31	+ const: 2
	32	+
	33	+ dlg,use-sw-pm:
	34	+ type: boolean
	35	+ description:
	36	+ Disable the watchdog during suspend.
	37	+ Only use this option if you can't use the watchdog automatic suspend
	38	+ function during a suspend (see register CONTROL_B).
	39	+
	40	+ watchdog:
	41	+ type: object
	42	+ $ref: /schemas/watchdog/watchdog.yaml#
	43	+ unevaluatedProperties: false
	44	+ properties:
	45	+ compatible:
	46	+ const: dlg,da9063-watchdog
	47	+
	48	+ rtc:
	49	+ type: object
	50	+ $ref: /schemas/rtc/rtc.yaml#
	51	+ unevaluatedProperties: false
	52	+ properties:
	53	+ compatible:
	54	+ const: dlg,da9063-rtc
	55	+
	56	+ onkey:
	57	+ type: object
	58	+ $ref: /schemas/input/input.yaml#
	59	+ unevaluatedProperties: false
	60	+ properties:
	61	+ compatible:
	62	+ const: dlg,da9063-onkey
	63	+
	64	+ dlg,disable-key-power:
	65	+ type: boolean
	66	+ description: \|
	67	+ Disable power-down using a long key-press.
	68	+ If this entry does not exist then by default the key-press triggered
	69	+ power down is enabled and the OnKey will support both KEY_POWER and
	70	+ KEY_SLEEP.
	71	+
	72	+ regulators:
	73	+ type: object
	74	+ patternProperties:
	75	+ "^(ldo[1-11]\|bcore[1-2]\|bpro\|bmem\|bio\|bperi)$":
	76	+ $ref: /schemas/regulator/regulator.yaml
	77	+ unevaluatedProperties: false
	78	+
	79	+required:
	80	+ - compatible
	81	+ - reg
	82	+ - interrupts
	83	+ - interrupt-controller
	84	+
	85	+additionalProperties: false
	86	+
	87	+examples:
	88	+ - \|
	89	+ #include <dt-bindings/interrupt-controller/irq.h>
	90	+ i2c {
	91	+ #address-cells = <1>;
	92	+ #size-cells = <0>;
	93	+ pmic@58 {
	94	+ compatible = "dlg,da9063";
	95	+ reg = <0x58>;
	96	+ #interrupt-cells = <2>;
	97	+ interrupt-parent = <&gpio6>;
	98	+ interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
	99	+ interrupt-controller;
	100	+
	101	+ rtc {
	102	+ compatible = "dlg,da9063-rtc";
	103	+ };
	104	+
	105	+ watchdog {
	106	+ compatible = "dlg,da9063-watchdog";
	107	+ };
	108	+
	109	+ onkey {
	110	+ compatible = "dlg,da9063-onkey";
	111	+ dlg,disable-key-power;
	112	+ };
	113	+
	114	+ regulators {
	115	+ regulator-bcore1 {
	116	+ regulator-name = "BCORE1";
	117	+ regulator-min-microvolt = <300000>;
	118	+ regulator-max-microvolt = <1570000>;
	119	+ regulator-min-microamp = <500000>;
	120	+ regulator-max-microamp = <2000000>;
	121	+ regulator-boot-on;
	122	+ };
	123	+ regulator-ldo11 {
	124	+ regulator-name = "LDO_11";
	125	+ regulator-min-microvolt = <900000>;
	126	+ regulator-max-microvolt = <3600000>;
	127	+ regulator-boot-on;
	128	+ };
	129	+ };
	130	+ };
	131	+ };
	132	+...

Documentation/devicetree/bindings/mfd/mps,mp2629.yaml+3−1

@@ -18,7 +18,9 @@ description: \| · 17 unmodified lines
18	18
19	19	properties:
20	20	compatible:
21		− const: mps,mp2629
	21	+ enum:
	22	+ - mps,mp2629
	23	+ - mps,mp2733
22	24
23	25	reg:
24	26	maxItems: 1

Documentation/devicetree/bindings/mfd/mt6397.txt+6−2

@@ -20,6 +20,7 @@ This document describes the binding for MFD device and its sub module. · 19 unmodified lines
20	20	Required properties:
21	21	compatible:
22	22	"mediatek,mt6323" for PMIC MT6323
	23	+ "mediatek,mt6331" for PMIC MT6331 and MT6332
23	24	"mediatek,mt6358" for PMIC MT6358 and MT6366
24	25	"mediatek,mt6359" for PMIC MT6359
25	26	"mediatek,mt6397" for PMIC MT6397
@@ -29,6 +30,7 @@ Optional subnodes: · 3 unmodified lines
29	30	- rtc
30	31	Required properties: Should be one of follows
31	32	- compatible: "mediatek,mt6323-rtc"
	33	+ - compatible: "mediatek,mt6331-rtc"
32	34	- compatible: "mediatek,mt6358-rtc"
33	35	- compatible: "mediatek,mt6397-rtc"
34	36	For details, see ../rtc/rtc-mt6397.txt
@@ -52,8 +54,10 @@ Optional subnodes: · 17 unmodified lines
52	54	see ../leds/leds-mt6323.txt
53	55
54	56	- keys
55		− Required properties:
56		− - compatible: "mediatek,mt6397-keys" or "mediatek,mt6323-keys"
	57	+ Required properties: Should be one of the following
	58	+ - compatible: "mediatek,mt6323-keys"
	59	+ - compatible: "mediatek,mt6331-keys"
	60	+ - compatible: "mediatek,mt6397-keys"
57	61	see ../input/mtk-pmic-keys.txt
58	62
59	63	- power-controller

Documentation/devicetree/bindings/mfd/qcom,tcsr.txt+0−24

@@ -1,24 +0,0 @@
1		−QCOM Top Control and Status Register
2		−
3		−Qualcomm devices have a set of registers that provide various control and status
4		−functions for their peripherals. This node is intended to allow access to these
5		−registers via syscon.
6		−
7		−Required properties:
8		−- compatible: Should contain:
9		− "qcom,tcsr-ipq6018", "syscon", "simple-mfd" for IPQ6018
10		− "qcom,tcsr-ipq8064", "syscon" for IPQ8064
11		− "qcom,tcsr-apq8064", "syscon" for APQ8064
12		− "qcom,tcsr-msm8660", "syscon" for MSM8660
13		− "qcom,tcsr-msm8953", "syscon" for MSM8953
14		− "qcom,tcsr-msm8960", "syscon" for MSM8960
15		− "qcom,tcsr-msm8974", "syscon" for MSM8974
16		− "qcom,tcsr-apq8084", "syscon" for APQ8084
17		− "qcom,tcsr-msm8916", "syscon" for MSM8916
18		−- reg: Address range for TCSR registers
19		−
20		−Example:
21		− tcsr: syscon@1a400000 {
22		− compatible = "qcom,tcsr-msm8960", "syscon";
23		− reg = <0x1a400000 0x100>;
24		− };

Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml+50−0

@@ -0,0 +1,50 @@
	1	+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
	2	+%YAML 1.2
	3	+---
	4	+$id: http://devicetree.org/schemas/mfd/qcom,tcsr.yaml#
	5	+$schema: http://devicetree.org/meta-schemas/core.yaml#
	6	+
	7	+title: Qualcomm Top Control and Status Register
	8	+
	9	+maintainers:
	10	+ - Bjorn Andersson <bjorn.andersson@linaro.org>
	11	+
	12	+description:
	13	+ Qualcomm devices have a set of registers that provide various control and
	14	+ status functions for their peripherals.
	15	+
	16	+properties:
	17	+ compatible:
	18	+ oneOf:
	19	+ - items:
	20	+ - enum:
	21	+ - qcom,tcsr-apq8064
	22	+ - qcom,tcsr-apq8084
	23	+ - qcom,tcsr-ipq8064
	24	+ - qcom,tcsr-mdm9615
	25	+ - qcom,tcsr-msm8660
	26	+ - qcom,tcsr-msm8916
	27	+ - qcom,tcsr-msm8953
	28	+ - qcom,tcsr-msm8960
	29	+ - qcom,tcsr-msm8974
	30	+ - const: syscon
	31	+ - items:
	32	+ - const: qcom,tcsr-ipq6018
	33	+ - const: syscon
	34	+ - const: simple-mfd
	35	+
	36	+ reg:
	37	+ maxItems: 1
	38	+
	39	+required:
	40	+ - compatible
	41	+ - reg
	42	+
	43	+additionalProperties: false
	44	+
	45	+examples:
	46	+ - \|
	47	+ syscon@1a400000 {
	48	+ compatible = "qcom,tcsr-msm8960", "syscon";
	49	+ reg = <0x1a400000 0x100>;
	50	+ };

Documentation/devicetree/bindings/mfd/qcom-pm8xxx.yaml+1−1

@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# · 6 unmodified lines
7	7	title: Qualcomm PM8xxx PMIC multi-function devices
8	8
9	9	maintainers:
10		− - Satya Priya <skakit@codeaurora.org>
	10	+ - Satya Priya <quic_c_skakit@quicinc.com>
11	11
12	12	description: \|
13	13	The PM8xxx family of Power Management ICs are used to provide regulated

Documentation/devicetree/bindings/mfd/st,stm32-lptimer.yaml+14−14

@@ -58,43 +58,43 @@ properties: · 57 unmodified lines
58	58	- "#pwm-cells"
59	59	- compatible
60	60
61		−patternProperties:
62		− "^trigger@[0-9]+$":
	61	+ counter:
63	62	type: object
64	63
65	64	properties:
66	65	compatible:
67		− const: st,stm32-lptimer-trigger
68		−
69		− reg:
70		− description: Identify trigger hardware block.
71		− items:
72		− minimum: 0
73		− maximum: 2
	66	+ const: st,stm32-lptimer-counter
74	67
75	68	required:
76	69	- compatible
77		− - reg
78	70
79		− counter:
	71	+ timer:
80	72	type: object
81	73
82	74	properties:
83	75	compatible:
84		− const: st,stm32-lptimer-counter
	76	+ const: st,stm32-lptimer-timer
85	77
86	78	required:
87	79	- compatible
88	80
89		− timer:
	81	+patternProperties:
	82	+ "^trigger@[0-9]+$":
90	83	type: object
91	84
92	85	properties:
93	86	compatible:
94		− const: st,stm32-lptimer-timer
	87	+ const: st,stm32-lptimer-trigger
	88	+
	89	+ reg:
	90	+ description: Identify trigger hardware block.
	91	+ items:
	92	+ minimum: 0
	93	+ maximum: 2
95	94
96	95	required:
97	96	- compatible
	97	+ - reg
98	98
99	99	required:
100	100	- "#address-cells"

Documentation/devicetree/bindings/mfd/st,stm32-timers.yaml+26−11

@@ -33,7 +33,7 @@ properties: · 32 unmodified lines
33	33	items:
34	34	- const: int
35	35
36		− reset:
	36	+ resets:
37	37	maxItems: 1
38	38
39	39	dmas:
@@ -46,6 +46,21 @@ properties: · 6 unmodified lines
46	46	minItems: 1
47	47	maxItems: 7
48	48
	49	+ interrupts:
	50	+ oneOf:
	51	+ - maxItems: 1
	52	+ - maxItems: 4
	53	+
	54	+ interrupt-names:
	55	+ oneOf:
	56	+ - items:
	57	+ - const: global
	58	+ - items:
	59	+ - const: brk
	60	+ - const: up
	61	+ - const: trg-com
	62	+ - const: cc
	63	+
49	64	"#address-cells":
50	65	const: 1
51	66
@@ -87,6 +102,16 @@ properties: · 35 unmodified lines
87	102	- "#pwm-cells"
88	103	- compatible
89	104
	105	+ counter:
	106	+ type: object
	107	+
	108	+ properties:
	109	+ compatible:
	110	+ const: st,stm32-timer-counter
	111	+
	112	+ required:
	113	+ - compatible
	114	+
90	115	patternProperties:
91	116	"^timer@[0-9]+$":
92	117	type: object
@@ -107,16 +132,6 @@ patternProperties: · 14 unmodified lines
107	132	- compatible
108	133	- reg
109	134
110		− counter:
111		− type: object
112		−
113		− properties:
114		− compatible:
115		− const: st,stm32-timer-counter
116		−
117		− required:
118		− - compatible
119		−
120	135	required:
121	136	- compatible
122	137	- reg

Documentation/devicetree/bindings/mfd/syscon.yaml+1−1

@@ -17,7 +17,7 @@ description: \| · 16 unmodified lines
17	17	and access the registers directly.
18	18
19	19	maintainers:
20		− - Lee Jones <lee.jones@linaro.org>
	20	+ - Lee Jones <lee@kernel.org>
21	21
22	22	select:
23	23	properties:

Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml+12−0

@@ -48,6 +48,12 @@ patternProperties: · 47 unmodified lines
48	48	description:
49	49	This is the SERDES lane control mux.
50	50
	51	+ "^clock-controller@[0-9a-f]+$":
	52	+ type: object
	53	+ $ref: /schemas/clock/ti,am654-ehrpwm-tbclk.yaml#
	54	+ description:
	55	+ Clock provider for TI EHRPWM nodes.
	56	+
51	57	required:
52	58	- compatible
53	59	- reg
@@ -79,5 +85,11 @@ examples: · 25 unmodified lines
79	85	<0x40c0 0x3>, <0x40c4 0x3>, <0x40c8 0x3>, <0x40cc 0x3>;
80	86	/* SERDES4 lane0/1/2/3 select */
81	87	};
	88	+
	89	+ clock-controller@4140 {
	90	+ compatible = "ti,am654-ehrpwm-tbclk", "syscon";
	91	+ reg = <0x4140 0x18>;
	92	+ #clock-cells = <1>;
	93	+ };
82	94	};
83	95	...

Documentation/devicetree/bindings/trivial-devices.yaml+0−2

@@ -95,8 +95,6 @@ properties: · 94 unmodified lines
95	95	- dh,dhcom-board
96	96	# DA9053: flexible system level PMIC with multicore support
97	97	- dlg,da9053
98		− # DA9063: system PMIC for quad-core application processors
99		− - dlg,da9063
100	98	# DMARD05: 3-axis I2C Accelerometer
101	99	- domintech,dmard05
102	100	# DMARD06: 3-axis I2C Accelerometer

MAINTAINERS+4−4

@@ -5999,6 +5999,7 @@ W: http://www.dialog-semiconductor.com/products · 5998 unmodified lines
5999	5999	F: Documentation/devicetree/bindings/input/da90??-onkey.txt
6000	6000	F: Documentation/devicetree/bindings/input/dlg,da72??.txt
6001	6001	F: Documentation/devicetree/bindings/mfd/da90*.txt
	6002	+F: Documentation/devicetree/bindings/mfd/da90*.yaml
6002	6003	F: Documentation/devicetree/bindings/regulator/dlg,da9*.yaml
6003	6004	F: Documentation/devicetree/bindings/regulator/da92*.txt
6004	6005	F: Documentation/devicetree/bindings/regulator/slg51000.txt
@@ -10388,7 +10389,7 @@ F: drivers/gpio/gpio-*cove.c · 4383 unmodified lines
10388	10389
10389	10390	INTEL PMIC MULTIFUNCTION DEVICE DRIVERS
10390	10391	M: Andy Shevchenko <andy@kernel.org>
10391		−S: Maintained
	10392	+S: Supported
10392	10393	F: drivers/mfd/intel_soc_pmic*
10393	10394	F: include/linux/mfd/intel_soc_pmic*
10394	10395
@@ -12401,7 +12402,6 @@ F: Documentation/devicetree/bindings/*/maxim,max77686.yaml · 2006 unmodified lines
12401	12402	F: Documentation/devicetree/bindings/*/maxim,max77693.yaml
12402	12403	F: Documentation/devicetree/bindings/*/maxim,max77843.yaml
12403	12404	F: Documentation/devicetree/bindings/clock/maxim,max77686.txt
12404		−F: Documentation/devicetree/bindings/mfd/max77693.txt
12405	12405	F: drivers//max77843.c
12406	12406	F: drivers//max14577.c
12407	12407	F: drivers//max77686.c
@@ -13872,7 +13872,7 @@ F: Documentation/devicetree/bindings/media/i2c/aptina,mt9v111.yaml · 1464 unmodified lines
13872	13872	F: drivers/media/i2c/mt9v111.c
13873	13873
13874	13874	MULTIFUNCTION DEVICES (MFD)
13875		−M: Lee Jones <lee.jones@linaro.org>
	13875	+M: Lee Jones <lee@kernel.org>
13876	13876	S: Supported
13877	13877	T: git git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd.git
13878	13878	F: Documentation/devicetree/bindings/mfd/
@@ -19689,7 +19689,7 @@ S: Maintained · 5810 unmodified lines
19689	19689	F: drivers/mmc/host/sdhci-pci-dwc-mshc.c
19690	19690
19691	19691	SYSTEM CONFIGURATION (SYSCON)
19692		−M: Lee Jones <lee.jones@linaro.org>
	19692	+M: Lee Jones <lee@kernel.org>
19693	19693	M: Arnd Bergmann <arnd@arndb.de>
19694	19694	S: Supported
19695	19695	T: git git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd.git

arch/arm/mach-pxa/eseries.c+1−3

@@ -81,11 +81,10 @@ int eseries_tmio_enable(struct platform_device *dev) · 80 unmodified lines
81	81	return 0;
82	82	}
83	83
84		−int eseries_tmio_disable(struct platform_device *dev)
	84	+void eseries_tmio_disable(struct platform_device *dev)
85	85	{
86	86	gpio_set_value(GPIO_ESERIES_TMIO_SUSPEND, 0);
87	87	gpio_set_value(GPIO_ESERIES_TMIO_PCLR, 0);
88		− return 0;
89	88	}
90	89
91	90	int eseries_tmio_suspend(struct platform_device *dev)
@@ -134,7 +133,6 @@ static void __init __maybe_unused eseries_register_clks(void) · 42 unmodified lines
134	133
135	134	static struct tc6387xb_platform_data e330_tc6387xb_info = {
136	135	.enable = &eseries_tmio_enable,
137		− .disable = &eseries_tmio_disable,
138	136	.suspend = &eseries_tmio_suspend,
139	137	.resume = &eseries_tmio_resume,
140	138	};

arch/arm/mach-pxa/tosa.c+1−3

@@ -678,13 +678,11 @@ err_req_pclr: · 677 unmodified lines
678	678	return rc;
679	679	}
680	680
681		−static int tosa_tc6393xb_disable(struct platform_device *dev)
	681	+static void tosa_tc6393xb_disable(struct platform_device *dev)
682	682	{
683	683	gpio_free(TOSA_GPIO_TC6393XB_L3V_ON);
684	684	gpio_free(TOSA_GPIO_TC6393XB_SUSPEND);
685	685	gpio_free(TOSA_GPIO_TC6393XB_REST_IN);
686		−
687		− return 0;
688	686	}
689	687
690	688	static int tosa_tc6393xb_resume(struct platform_device *dev)

drivers/mfd/Kconfig+3−2

@@ -1358,12 +1358,13 @@ config MFD_STA2X11 · 1357 unmodified lines
1358	1358	select REGMAP_MMIO
1359	1359
1360	1360	config MFD_SUN6I_PRCM
1361		− bool "Allwinner A31 PRCM controller"
	1361	+ bool "Allwinner A31/A23/A33 PRCM controller"
1362	1362	depends on ARCH_SUNXI \|\| COMPILE_TEST
1363	1363	select MFD_CORE
1364	1364	help
1365	1365	Support for the PRCM (Power/Reset/Clock Management) unit available
1366		− in A31 SoC.
	1366	+ in the A31, A23, and A33 SoCs. Other Allwinner SoCs contain similar
	1367	+ hardware, but they do not use this driver.
1367	1368
1368	1369	config MFD_SYSCON
1369	1370	bool "System Controller Register R/W Based on Regmap"

drivers/mfd/asic3.c+3−6

@@ -596,12 +596,11 @@ static __init int asic3_gpio_probe(struct platform_device *pdev, · 595 unmodified lines
596	596	return gpiochip_add_data(&asic->gpio, asic);
597	597	}
598	598
599		−static int asic3_gpio_remove(struct platform_device *pdev)
	599	+static void asic3_gpio_remove(struct platform_device *pdev)
600	600	{
601	601	struct asic3 *asic = platform_get_drvdata(pdev);
602	602
603	603	gpiochip_remove(&asic->gpio);
604		− return 0;
605	604	}
606	605
607	606	static void asic3_clk_enable(struct asic3 asic, struct asic3_clk clk)
@@ -1030,7 +1029,6 @@ static int __init asic3_probe(struct platform_device *pdev) · 422 unmodified lines
1030	1029
1031	1030	static int asic3_remove(struct platform_device *pdev)
1032	1031	{
1033		− int ret;
1034	1032	struct asic3 *asic = platform_get_drvdata(pdev);
1035	1033
1036	1034	asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),
@@ -1038,9 +1036,8 @@ static int asic3_remove(struct platform_device *pdev) · 1 unmodified line
1038	1036
1039	1037	asic3_mfd_remove(pdev);
1040	1038
1041		− ret = asic3_gpio_remove(pdev);
1042		− if (ret < 0)
1043		− return ret;
	1039	+ asic3_gpio_remove(pdev);
	1040	+
1044	1041	asic3_irq_remove(pdev);
1045	1042
1046	1043	asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), 0);

drivers/mfd/axp20x.c+9−0

@@ -619,6 +619,9 @@ static const struct mfd_cell axp20x_cells[] = { · 618 unmodified lines
619	619
620	620	static const struct mfd_cell axp221_cells[] = {
621	621	{
	622	+ .name = "axp20x-gpio",
	623	+ .of_compatible = "x-powers,axp221-gpio",
	624	+ }, {
622	625	.name = "axp221-pek",
623	626	.num_resources = ARRAY_SIZE(axp22x_pek_resources),
624	627	.resources = axp22x_pek_resources,
@@ -645,6 +648,9 @@ static const struct mfd_cell axp221_cells[] = { · 20 unmodified lines
645	648
646	649	static const struct mfd_cell axp223_cells[] = {
647	650	{
	651	+ .name = "axp20x-gpio",
	652	+ .of_compatible = "x-powers,axp221-gpio",
	653	+ }, {
648	654	.name = "axp221-pek",
649	655	.num_resources = ARRAY_SIZE(axp22x_pek_resources),
650	656	.resources = axp22x_pek_resources,
@@ -785,6 +791,9 @@ static const struct mfd_cell axp806_cells[] = { · 134 unmodified lines
785	791
786	792	static const struct mfd_cell axp809_cells[] = {
787	793	{
	794	+ .name = "axp20x-gpio",
	795	+ .of_compatible = "x-powers,axp221-gpio",
	796	+ }, {
788	797	.name = "axp221-pek",
789	798	.num_resources = ARRAY_SIZE(axp809_pek_resources),
790	799	.resources = axp809_pek_resources,

drivers/mfd/cros_ec_dev.c+5−0

@@ -64,6 +64,11 @@ static const struct cros_feature_to_name cros_mcu_devices[] = { · 63 unmodified lines
64	64	.name = CROS_EC_DEV_SCP_NAME,
65	65	.desc = "System Control Processor",
66	66	},
	67	+ {
	68	+ .id = EC_FEATURE_SCP_C1,
	69	+ .name = CROS_EC_DEV_SCP_C1_NAME,
	70	+ .desc = "System Control Processor 2nd Core",
	71	+ },
67	72	{
68	73	.id = EC_FEATURE_TOUCHPAD,
69	74	.name = CROS_EC_DEV_TP_NAME,

drivers/mfd/db8500-prcmu.c+1−1

@@ -798,7 +798,7 @@ void db8500_prcmu_get_abb_event_buffer(void __iomem **buf) · 797 unmodified lines
798	798	* @opp: The new ARM operating point to which transition is to be made
799	799	* Returns: 0 on success, non-zero on failure
800	800	*
801		− * This function sets the the operating point of the ARM.
	801	+ * This function sets the operating point of the ARM.
802	802	*/
803	803	int db8500_prcmu_set_arm_opp(u8 opp)
804	804	{

drivers/mfd/dln2.c+4−13

@@ -91,11 +91,6 @@ struct dln2_mod_rx_slots { · 90 unmodified lines
91	91	spinlock_t lock;
92	92	};
93	93
94		−enum dln2_endpoint {
95		− DLN2_EP_OUT = 0,
96		− DLN2_EP_IN = 1,
97		−};
98		−
99	94	struct dln2_dev {
100	95	struct usb_device *usb_dev;
101	96	struct usb_interface *interface;
@@ -777,16 +772,12 @@ static int dln2_probe(struct usb_interface *interface, · 675 unmodified lines
777	772	int ret;
778	773	int i, j;
779	774
780		− if (hostif->desc.bInterfaceNumber != 0 \|\|
781		− hostif->desc.bNumEndpoints < 2)
	775	+ if (hostif->desc.bInterfaceNumber != 0)
782	776	return -ENODEV;
783	777
784		− epout = &hostif->endpoint[DLN2_EP_OUT].desc;
785		− if (!usb_endpoint_is_bulk_out(epout))
786		− return -ENODEV;
787		− epin = &hostif->endpoint[DLN2_EP_IN].desc;
788		− if (!usb_endpoint_is_bulk_in(epin))
789		− return -ENODEV;
	778	+ ret = usb_find_common_endpoints(hostif, &epin, &epout, NULL, NULL);
	779	+ if (ret)
	780	+ return ret;
790	781
791	782	dln2 = kzalloc(sizeof(*dln2), GFP_KERNEL);
792	783	if (!dln2)

drivers/mfd/intel-lpss-pci.c+13−0

@@ -385,6 +385,19 @@ static const struct pci_device_id intel_lpss_pci_ids[] = { · 384 unmodified lines
385	385	{ PCI_VDEVICE(INTEL, 0x7afc), (kernel_ulong_t)&bxt_i2c_info },
386	386	{ PCI_VDEVICE(INTEL, 0x7afd), (kernel_ulong_t)&bxt_i2c_info },
387	387	{ PCI_VDEVICE(INTEL, 0x7afe), (kernel_ulong_t)&bxt_uart_info },
	388	+ /* MTL-P */
	389	+ { PCI_VDEVICE(INTEL, 0x7e25), (kernel_ulong_t)&bxt_uart_info },
	390	+ { PCI_VDEVICE(INTEL, 0x7e26), (kernel_ulong_t)&bxt_uart_info },
	391	+ { PCI_VDEVICE(INTEL, 0x7e27), (kernel_ulong_t)&bxt_info },
	392	+ { PCI_VDEVICE(INTEL, 0x7e30), (kernel_ulong_t)&bxt_info },
	393	+ { PCI_VDEVICE(INTEL, 0x7e46), (kernel_ulong_t)&bxt_info },
	394	+ { PCI_VDEVICE(INTEL, 0x7e50), (kernel_ulong_t)&bxt_i2c_info },
	395	+ { PCI_VDEVICE(INTEL, 0x7e51), (kernel_ulong_t)&bxt_i2c_info },
	396	+ { PCI_VDEVICE(INTEL, 0x7e52), (kernel_ulong_t)&bxt_uart_info },
	397	+ { PCI_VDEVICE(INTEL, 0x7e78), (kernel_ulong_t)&bxt_i2c_info },
	398	+ { PCI_VDEVICE(INTEL, 0x7e79), (kernel_ulong_t)&bxt_i2c_info },
	399	+ { PCI_VDEVICE(INTEL, 0x7e7a), (kernel_ulong_t)&bxt_i2c_info },
	400	+ { PCI_VDEVICE(INTEL, 0x7e7b), (kernel_ulong_t)&bxt_i2c_info },
388	401	/* LKF */
389	402	{ PCI_VDEVICE(INTEL, 0x98a8), (kernel_ulong_t)&bxt_uart_info },
390	403	{ PCI_VDEVICE(INTEL, 0x98a9), (kernel_ulong_t)&bxt_uart_info },

drivers/mfd/intel_soc_pmic_bxtwc.c+75−119

@@ -2,10 +2,11 @@ · 1 unmodified line
2	2	/*
3	3	* MFD core driver for Intel Broxton Whiskey Cove PMIC
4	4	*
5		− * Copyright (C) 2015 Intel Corporation. All rights reserved.
	5	+ * Copyright (C) 2015-2017, 2022 Intel Corporation. All rights reserved.
6	6	*/
7	7
8	8	#include <linux/acpi.h>
	9	+#include <linux/bits.h>
9	10	#include <linux/delay.h>
10	11	#include <linux/err.h>
11	12	#include <linux/interrupt.h>
@@ -18,9 +19,9 @@ · 6 unmodified lines
18	19	#include <asm/intel_scu_ipc.h>
19	20
20	21	/* PMIC device registers */
21		−#define REG_ADDR_MASK 0xFF00
	22	+#define REG_ADDR_MASK GENMASK(15, 8)
22	23	#define REG_ADDR_SHIFT 8
23		−#define REG_OFFSET_MASK 0xFF
	24	+#define REG_OFFSET_MASK GENMASK(7, 0)
24	25
25	26	/* Interrupt Status Registers */
26	27	#define BXTWC_IRQLVL1 0x4E02
@@ -112,29 +113,29 @@ static const struct regmap_irq bxtwc_regmap_irqs[] = { · 85 unmodified lines
112	113	};
113	114
114	115	static const struct regmap_irq bxtwc_regmap_irqs_pwrbtn[] = {
115		− REGMAP_IRQ_REG(BXTWC_PWRBTN_IRQ, 0, 0x01),
	116	+ REGMAP_IRQ_REG(BXTWC_PWRBTN_IRQ, 0, BIT(0)),
116	117	};
117	118
118	119	static const struct regmap_irq bxtwc_regmap_irqs_bcu[] = {
119		− REGMAP_IRQ_REG(BXTWC_BCU_IRQ, 0, 0x1f),
	120	+ REGMAP_IRQ_REG(BXTWC_BCU_IRQ, 0, GENMASK(4, 0)),
120	121	};
121	122
122	123	static const struct regmap_irq bxtwc_regmap_irqs_adc[] = {
123		− REGMAP_IRQ_REG(BXTWC_ADC_IRQ, 0, 0xff),
	124	+ REGMAP_IRQ_REG(BXTWC_ADC_IRQ, 0, GENMASK(7, 0)),
124	125	};
125	126
126	127	static const struct regmap_irq bxtwc_regmap_irqs_chgr[] = {
127		− REGMAP_IRQ_REG(BXTWC_USBC_IRQ, 0, 0x20),
128		− REGMAP_IRQ_REG(BXTWC_CHGR0_IRQ, 0, 0x1f),
129		− REGMAP_IRQ_REG(BXTWC_CHGR1_IRQ, 1, 0x1f),
	128	+ REGMAP_IRQ_REG(BXTWC_USBC_IRQ, 0, BIT(5)),
	129	+ REGMAP_IRQ_REG(BXTWC_CHGR0_IRQ, 0, GENMASK(4, 0)),
	130	+ REGMAP_IRQ_REG(BXTWC_CHGR1_IRQ, 1, GENMASK(4, 0)),
130	131	};
131	132
132	133	static const struct regmap_irq bxtwc_regmap_irqs_tmu[] = {
133		− REGMAP_IRQ_REG(BXTWC_TMU_IRQ, 0, 0x06),
	134	+ REGMAP_IRQ_REG(BXTWC_TMU_IRQ, 0, GENMASK(2, 1)),
134	135	};
135	136
136	137	static const struct regmap_irq bxtwc_regmap_irqs_crit[] = {
137		− REGMAP_IRQ_REG(BXTWC_CRIT_IRQ, 0, 0x03),
	138	+ REGMAP_IRQ_REG(BXTWC_CRIT_IRQ, 0, GENMASK(1, 0)),
138	139	};
139	140
140	141	static struct regmap_irq_chip bxtwc_regmap_irq_chip = {
@@ -333,17 +334,19 @@ static unsigned long bxtwc_reg_addr; · 192 unmodified lines
333	334	static ssize_t addr_show(struct device *dev,
334	335	struct device_attribute attr, char buf)
335	336	{
336		− return sprintf(buf, "0x%lx\n", bxtwc_reg_addr);
	337	+ return sysfs_emit(buf, "0x%lx\n", bxtwc_reg_addr);
337	338	}
338	339
339	340	static ssize_t addr_store(struct device *dev,
340	341	struct device_attribute attr, const char buf, size_t count)
341	342	{
342		− if (kstrtoul(buf, 0, &bxtwc_reg_addr)) {
343		− dev_err(dev, "Invalid register address\n");
344		− return -EINVAL;
345		− }
346		− return (ssize_t)count;
	343	+ int ret;
	344	+
	345	+ ret = kstrtoul(buf, 0, &bxtwc_reg_addr);
	346	+ if (ret)
	347	+ return ret;
	348	+
	349	+ return count;
347	350	}
348	351
349	352	static ssize_t val_show(struct device *dev,
@@ -354,12 +357,12 @@ static ssize_t val_show(struct device *dev, · 4 unmodified lines
354	357	struct intel_soc_pmic *pmic = dev_get_drvdata(dev);
355	358
356	359	ret = regmap_read(pmic->regmap, bxtwc_reg_addr, &val);
357		− if (ret < 0) {
	360	+ if (ret) {
358	361	dev_err(dev, "Failed to read 0x%lx\n", bxtwc_reg_addr);
359		− return -EIO;
	362	+ return ret;
360	363	}
361	364
362		− return sprintf(buf, "0x%02x\n", val);
	365	+ return sysfs_emit(buf, "0x%02x\n", val);
363	366	}
364	367
365	368	static ssize_t val_store(struct device *dev,
@@ -377,7 +380,7 @@ static ssize_t val_store(struct device *dev, · 11 unmodified lines
377	380	if (ret) {
378	381	dev_err(dev, "Failed to write value 0x%02x to address 0x%lx",
379	382	val, bxtwc_reg_addr);
380		− return -EIO;
	383	+ return ret;
381	384	}
382	385	return count;
383	386	}
@@ -394,6 +397,11 @@ static const struct attribute_group bxtwc_group = { · 10 unmodified lines
394	397	.attrs = bxtwc_attrs,
395	398	};
396	399
	400	+static const struct attribute_group *bxtwc_groups[] = {
	401	+ &bxtwc_group,
	402	+ NULL
	403	+};
	404	+
397	405	static const struct regmap_config bxtwc_regmap_config = {
398	406	.reg_bits = 16,
399	407	.val_bits = 8,
@@ -410,12 +418,9 @@ static int bxtwc_add_chained_irq_chip(struct intel_soc_pmic *pmic, · 10 unmodified lines
410	418	int irq;
411	419
412	420	irq = regmap_irq_get_virq(pdata, pirq);
413		− if (irq < 0) {
414		− dev_err(pmic->dev,
415		− "Failed to get parent vIRQ(%d) for chip %s, ret:%d\n",
416		− pirq, chip->name, irq);
417		− return irq;
418		− }
	421	+ if (irq < 0)
	422	+ return dev_err_probe(pmic->dev, irq, "Failed to get parent vIRQ(%d) for chip %s\n",
	423	+ pirq, chip->name);
419	424
420	425	return devm_regmap_add_irq_chip(pmic->dev, pmic->regmap, irq, irq_flags,
421	426	0, chip, data);
@@ -423,25 +428,19 @@ static int bxtwc_add_chained_irq_chip(struct intel_soc_pmic *pmic, · 1 unmodified line
423	428
424	429	static int bxtwc_probe(struct platform_device *pdev)
425	430	{
	431	+ struct device *dev = &pdev->dev;
426	432	int ret;
427		− acpi_handle handle;
428	433	acpi_status status;
429	434	unsigned long long hrv;
430	435	struct intel_soc_pmic *pmic;
431	436
432		− handle = ACPI_HANDLE(&pdev->dev);
433		− status = acpi_evaluate_integer(handle, "_HRV", NULL, &hrv);
434		− if (ACPI_FAILURE(status)) {
435		− dev_err(&pdev->dev, "Failed to get PMIC hardware revision\n");
436		− return -ENODEV;
437		− }
438		− if (hrv != BROXTON_PMIC_WC_HRV) {
439		− dev_err(&pdev->dev, "Invalid PMIC hardware revision: %llu\n",
440		− hrv);
441		− return -ENODEV;
442		− }
	437	+ status = acpi_evaluate_integer(ACPI_HANDLE(dev), "_HRV", NULL, &hrv);
	438	+ if (ACPI_FAILURE(status))
	439	+ return dev_err_probe(dev, -ENODEV, "Failed to get PMIC hardware revision\n");
	440	+ if (hrv != BROXTON_PMIC_WC_HRV)
	441	+ return dev_err_probe(dev, -ENODEV, "Invalid PMIC hardware revision: %llu\n", hrv);
443	442
444		− pmic = devm_kzalloc(&pdev->dev, sizeof(*pmic), GFP_KERNEL);
	443	+ pmic = devm_kzalloc(dev, sizeof(*pmic), GFP_KERNEL);
445	444	if (!pmic)
446	445	return -ENOMEM;
447	446
@@ -450,49 +449,39 @@ static int bxtwc_probe(struct platform_device *pdev) · 2 unmodified lines
450	449	return ret;
451	450	pmic->irq = ret;
452	451
453		− dev_set_drvdata(&pdev->dev, pmic);
454		− pmic->dev = &pdev->dev;
	452	+ platform_set_drvdata(pdev, pmic);
	453	+ pmic->dev = dev;
455	454
456		− pmic->scu = devm_intel_scu_ipc_dev_get(&pdev->dev);
	455	+ pmic->scu = devm_intel_scu_ipc_dev_get(dev);
457	456	if (!pmic->scu)
458	457	return -EPROBE_DEFER;
459	458
460		− pmic->regmap = devm_regmap_init(&pdev->dev, NULL, pmic,
461		− &bxtwc_regmap_config);
462		− if (IS_ERR(pmic->regmap)) {
463		− ret = PTR_ERR(pmic->regmap);
464		− dev_err(&pdev->dev, "Failed to initialise regmap: %d\n", ret);
465		− return ret;
466		− }
	459	+ pmic->regmap = devm_regmap_init(dev, NULL, pmic, &bxtwc_regmap_config);
	460	+ if (IS_ERR(pmic->regmap))
	461	+ return dev_err_probe(dev, PTR_ERR(pmic->regmap), "Failed to initialise regmap\n");
467	462
468		− ret = devm_regmap_add_irq_chip(&pdev->dev, pmic->regmap, pmic->irq,
	463	+ ret = devm_regmap_add_irq_chip(dev, pmic->regmap, pmic->irq,
469	464	IRQF_ONESHOT \| IRQF_SHARED,
470	465	0, &bxtwc_regmap_irq_chip,
471	466	&pmic->irq_chip_data);
472		− if (ret) {
473		− dev_err(&pdev->dev, "Failed to add IRQ chip\n");
474		− return ret;
475		− }
	467	+ if (ret)
	468	+ return dev_err_probe(dev, ret, "Failed to add IRQ chip\n");
476	469
477	470	ret = bxtwc_add_chained_irq_chip(pmic, pmic->irq_chip_data,
478	471	BXTWC_PWRBTN_LVL1_IRQ,
479	472	IRQF_ONESHOT,
480	473	&bxtwc_regmap_irq_chip_pwrbtn,
481	474	&pmic->irq_chip_data_pwrbtn);
482		− if (ret) {
483		− dev_err(&pdev->dev, "Failed to add PWRBTN IRQ chip\n");
484		− return ret;
485		− }
	475	+ if (ret)
	476	+ return dev_err_probe(dev, ret, "Failed to add PWRBTN IRQ chip\n");
486	477
487	478	ret = bxtwc_add_chained_irq_chip(pmic, pmic->irq_chip_data,
488	479	BXTWC_TMU_LVL1_IRQ,
489	480	IRQF_ONESHOT,
490	481	&bxtwc_regmap_irq_chip_tmu,
491	482	&pmic->irq_chip_data_tmu);
492		− if (ret) {
493		− dev_err(&pdev->dev, "Failed to add TMU IRQ chip\n");
494		− return ret;
495		− }
	483	+ if (ret)
	484	+ return dev_err_probe(dev, ret, "Failed to add TMU IRQ chip\n");
496	485
497	486	/* Add chained IRQ handler for BCU IRQs */
498	487	ret = bxtwc_add_chained_irq_chip(pmic, pmic->irq_chip_data,
@@ -500,12 +489,8 @@ static int bxtwc_probe(struct platform_device *pdev) · 1 unmodified line
500	489	IRQF_ONESHOT,
501	490	&bxtwc_regmap_irq_chip_bcu,
502	491	&pmic->irq_chip_data_bcu);
503		−
504		−
505		− if (ret) {
506		− dev_err(&pdev->dev, "Failed to add BUC IRQ chip\n");
507		− return ret;
508		− }
	492	+ if (ret)
	493	+ return dev_err_probe(dev, ret, "Failed to add BUC IRQ chip\n");
509	494
510	495	/* Add chained IRQ handler for ADC IRQs */
511	496	ret = bxtwc_add_chained_irq_chip(pmic, pmic->irq_chip_data,
@@ -513,12 +498,8 @@ static int bxtwc_probe(struct platform_device *pdev) · 1 unmodified line
513	498	IRQF_ONESHOT,
514	499	&bxtwc_regmap_irq_chip_adc,
515	500	&pmic->irq_chip_data_adc);
516		−
517		−
518		− if (ret) {
519		− dev_err(&pdev->dev, "Failed to add ADC IRQ chip\n");
520		− return ret;
521		− }
	501	+ if (ret)
	502	+ return dev_err_probe(dev, ret, "Failed to add ADC IRQ chip\n");
522	503
523	504	/* Add chained IRQ handler for CHGR IRQs */
524	505	ret = bxtwc_add_chained_irq_chip(pmic, pmic->irq_chip_data,
@@ -526,12 +507,8 @@ static int bxtwc_probe(struct platform_device *pdev) · 1 unmodified line
526	507	IRQF_ONESHOT,
527	508	&bxtwc_regmap_irq_chip_chgr,
528	509	&pmic->irq_chip_data_chgr);
529		−
530		−
531		− if (ret) {
532		− dev_err(&pdev->dev, "Failed to add CHGR IRQ chip\n");
533		− return ret;
534		− }
	510	+ if (ret)
	511	+ return dev_err_probe(dev, ret, "Failed to add CHGR IRQ chip\n");
535	512
536	513	/* Add chained IRQ handler for CRIT IRQs */
537	514	ret = bxtwc_add_chained_irq_chip(pmic, pmic->irq_chip_data,
@@ -539,54 +516,33 @@ static int bxtwc_probe(struct platform_device *pdev) · 1 unmodified line
539	516	IRQF_ONESHOT,
540	517	&bxtwc_regmap_irq_chip_crit,
541	518	&pmic->irq_chip_data_crit);
	519	+ if (ret)
	520	+ return dev_err_probe(dev, ret, "Failed to add CRIT IRQ chip\n");
542	521
543		−
544		− if (ret) {
545		− dev_err(&pdev->dev, "Failed to add CRIT IRQ chip\n");
546		− return ret;
547		− }
548		−
549		− ret = devm_mfd_add_devices(&pdev->dev, PLATFORM_DEVID_NONE, bxt_wc_dev,
550		− ARRAY_SIZE(bxt_wc_dev), NULL, 0, NULL);
551		− if (ret) {
552		− dev_err(&pdev->dev, "Failed to add devices\n");
553		− return ret;
554		− }
555		−
556		− ret = sysfs_create_group(&pdev->dev.kobj, &bxtwc_group);
557		− if (ret) {
558		− dev_err(&pdev->dev, "Failed to create sysfs group %d\n", ret);
559		− return ret;
560		− }
	522	+ ret = devm_mfd_add_devices(dev, PLATFORM_DEVID_NONE, bxt_wc_dev, ARRAY_SIZE(bxt_wc_dev),
	523	+ NULL, 0, NULL);
	524	+ if (ret)
	525	+ return dev_err_probe(dev, ret, "Failed to add devices\n");
561	526
562	527	/*
563		− * There is known hw bug. Upon reset BIT 5 of register
	528	+ * There is a known H/W bug. Upon reset, BIT 5 of register
564	529	* BXTWC_CHGR_LVL1_IRQ is 0 which is the expected value. However,
565	530	* later it's set to 1(masked) automatically by hardware. So we
566		− * have the software workaround here to unmaksed it in order to let
567		− * charger interrutp work.
	531	+ * place the software workaround here to unmask it again in order
	532	+ * to re-enable the charger interrupt.
568	533	*/
569		− regmap_update_bits(pmic->regmap, BXTWC_MIRQLVL1,
570		− BXTWC_MIRQLVL1_MCHGR, 0);
571		−
572		− return 0;
573		−}
574		−
575		−static int bxtwc_remove(struct platform_device *pdev)
576		−{
577		− sysfs_remove_group(&pdev->dev.kobj, &bxtwc_group);
	534	+ regmap_update_bits(pmic->regmap, BXTWC_MIRQLVL1, BXTWC_MIRQLVL1_MCHGR, 0);
578	535
579	536	return 0;
580	537	}
581	538
582	539	static void bxtwc_shutdown(struct platform_device *pdev)
583	540	{
584		− struct intel_soc_pmic *pmic = dev_get_drvdata(&pdev->dev);
	541	+ struct intel_soc_pmic *pmic = platform_get_drvdata(pdev);
585	542
586	543	disable_irq(pmic->irq);
587	544	}
588	545
589		−#ifdef CONFIG_PM_SLEEP
590	546	static int bxtwc_suspend(struct device *dev)
591	547	{
592	548	struct intel_soc_pmic *pmic = dev_get_drvdata(dev);
@@ -603,8 +559,8 @@ static int bxtwc_resume(struct device *dev) · 10 unmodified lines
603	559	enable_irq(pmic->irq);
604	560	return 0;
605	561	}
606		−#endif
607		−static SIMPLE_DEV_PM_OPS(bxtwc_pm_ops, bxtwc_suspend, bxtwc_resume);
	562	+
	563	+static DEFINE_SIMPLE_DEV_PM_OPS(bxtwc_pm_ops, bxtwc_suspend, bxtwc_resume);
608	564
609	565	static const struct acpi_device_id bxtwc_acpi_ids[] = {
610	566	{ "INT34D3", },
@@ -614,16 +570,16 @@ MODULE_DEVICE_TABLE(acpi, bxtwc_acpi_ids); · 3 unmodified lines
614	570
615	571	static struct platform_driver bxtwc_driver = {
616	572	.probe = bxtwc_probe,
617		− .remove = bxtwc_remove,
618	573	.shutdown = bxtwc_shutdown,
619	574	.driver = {
620	575	.name = "BXTWC PMIC",
621		− .pm = &bxtwc_pm_ops,
622		− .acpi_match_table = ACPI_PTR(bxtwc_acpi_ids),
	576	+ .pm = pm_sleep_ptr(&bxtwc_pm_ops),
	577	+ .acpi_match_table = bxtwc_acpi_ids,
	578	+ .dev_groups = bxtwc_groups,
623	579	},
624	580	};
625	581
626	582	module_platform_driver(bxtwc_driver);
627	583
628	584	MODULE_LICENSE("GPL v2");
629		−MODULE_AUTHOR("Qipeng Zha<qipeng.zha@intel.com>");
	585	+MODULE_AUTHOR("Qipeng Zha <qipeng.zha@intel.com>");

drivers/mfd/intel_soc_pmic_chtwc.c+11−16

@@ -179,18 +179,13 @@ static int cht_wc_probe(struct i2c_client *client) · 178 unmodified lines
179	179	int ret;
180	180
181	181	status = acpi_evaluate_integer(ACPI_HANDLE(dev), "_HRV", NULL, &hrv);
182		− if (ACPI_FAILURE(status)) {
183		− dev_err(dev, "Failed to get PMIC hardware revision\n");
184		− return -ENODEV;
185		− }
186		− if (hrv != CHT_WC_HRV) {
187		− dev_err(dev, "Invalid PMIC hardware revision: %llu\n", hrv);
188		− return -ENODEV;
189		− }
190		− if (client->irq < 0) {
191		− dev_err(dev, "Invalid IRQ\n");
192		− return -EINVAL;
193		− }
	182	+ if (ACPI_FAILURE(status))
	183	+ return dev_err_probe(dev, -ENODEV, "Failed to get PMIC hardware revision\n");
	184	+ if (hrv != CHT_WC_HRV)
	185	+ return dev_err_probe(dev, -ENODEV, "Invalid PMIC hardware revision: %llu\n", hrv);
	186	+
	187	+ if (client->irq < 0)
	188	+ return dev_err_probe(dev, -EINVAL, "Invalid IRQ\n");
194	189
195	190	pmic = devm_kzalloc(dev, sizeof(*pmic), GFP_KERNEL);
196	191	if (!pmic)
@@ -227,7 +222,7 @@ static void cht_wc_shutdown(struct i2c_client *client) · 30 unmodified lines
227	222	disable_irq(pmic->irq);
228	223	}
229	224
230		−static int __maybe_unused cht_wc_suspend(struct device *dev)
	225	+static int cht_wc_suspend(struct device *dev)
231	226	{
232	227	struct intel_soc_pmic *pmic = dev_get_drvdata(dev);
233	228
@@ -236,7 +231,7 @@ static int __maybe_unused cht_wc_suspend(struct device *dev) · 2 unmodified lines
236	231	return 0;
237	232	}
238	233
239		−static int __maybe_unused cht_wc_resume(struct device *dev)
	234	+static int cht_wc_resume(struct device *dev)
240	235	{
241	236	struct intel_soc_pmic *pmic = dev_get_drvdata(dev);
242	237
@@ -244,7 +239,7 @@ static int __maybe_unused cht_wc_resume(struct device *dev) · 1 unmodified line
244	239
245	240	return 0;
246	241	}
247		−static SIMPLE_DEV_PM_OPS(cht_wc_pm_ops, cht_wc_suspend, cht_wc_resume);
	242	+static DEFINE_SIMPLE_DEV_PM_OPS(cht_wc_pm_ops, cht_wc_suspend, cht_wc_resume);
248	243
249	244	static const struct i2c_device_id cht_wc_i2c_id[] = {
250	245	{ }
@@ -258,7 +253,7 @@ static const struct acpi_device_id cht_wc_acpi_ids[] = { · 7 unmodified lines
258	253	static struct i2c_driver cht_wc_driver = {
259	254	.driver = {
260	255	.name = "CHT Whiskey Cove PMIC",
261		− .pm = &cht_wc_pm_ops,
	256	+ .pm = pm_sleep_ptr(&cht_wc_pm_ops),
262	257	.acpi_match_table = cht_wc_acpi_ids,
263	258	},
264	259	.probe_new = cht_wc_probe,

drivers/mfd/max77620.c+2−0

@@ -419,9 +419,11 @@ static int max77620_initialise_fps(struct max77620_chip *chip) · 418 unmodified lines
419	419	ret = max77620_config_fps(chip, fps_child);
420	420	if (ret < 0) {
421	421	of_node_put(fps_child);
	422	+ of_node_put(fps_np);
422	423	return ret;
423	424	}
424	425	}
	426	+ of_node_put(fps_np);
425	427
426	428	config = chip->enable_global_lpm ? MAX77620_ONOFFCNFG2_SLP_LPM_MSK : 0;
427	429	ret = regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG2,

drivers/mfd/max77714.c+2−2

@@ -3,7 +3,7 @@ · 2 unmodified lines
3	3	* Maxim MAX77714 Core Driver
4	4	*
5	5	* Copyright (C) 2022 Luca Ceresoli
6		− * Author: Luca Ceresoli <luca@lucaceresoli.net>
	6	+ * Author: Luca Ceresoli <luca.ceresoli@bootlin.com>
7	7	*/
8	8
9	9	#include <linux/i2c.h>
@@ -148,5 +148,5 @@ static struct i2c_driver max77714_driver = { · 138 unmodified lines
148	148	module_i2c_driver(max77714_driver);
149	149
150	150	MODULE_DESCRIPTION("Maxim MAX77714 MFD core driver");
151		−MODULE_AUTHOR("Luca Ceresoli <luca@lucaceresoli.net>");
	151	+MODULE_AUTHOR("Luca Ceresoli <luca.ceresoli@bootlin.com>");
152	152	MODULE_LICENSE("GPL");

drivers/mfd/mt6358-irq.c+24−0

@@ -3,6 +3,8 @@ · 2 unmodified lines
3	3	// Copyright (c) 2020 MediaTek Inc.
4	4
5	5	#include <linux/interrupt.h>
	6	+#include <linux/mfd/mt6357/core.h>
	7	+#include <linux/mfd/mt6357/registers.h>
6	8	#include <linux/mfd/mt6358/core.h>
7	9	#include <linux/mfd/mt6358/registers.h>
8	10	#include <linux/mfd/mt6359/core.h>
@@ -17,6 +19,17 @@ · 8 unmodified lines
17	19
18	20	#define MTK_PMIC_REG_WIDTH 16
19	21
	22	+static const struct irq_top_t mt6357_ints[] = {
	23	+ MT6357_TOP_GEN(BUCK),
	24	+ MT6357_TOP_GEN(LDO),
	25	+ MT6357_TOP_GEN(PSC),
	26	+ MT6357_TOP_GEN(SCK),
	27	+ MT6357_TOP_GEN(BM),
	28	+ MT6357_TOP_GEN(HK),
	29	+ MT6357_TOP_GEN(AUD),
	30	+ MT6357_TOP_GEN(MISC),
	31	+};
	32	+
20	33	static const struct irq_top_t mt6358_ints[] = {
21	34	MT6358_TOP_GEN(BUCK),
22	35	MT6358_TOP_GEN(LDO),
@@ -39,6 +52,13 @@ static const struct irq_top_t mt6359_ints[] = { · 16 unmodified lines
39	52	MT6359_TOP_GEN(MISC),
40	53	};
41	54
	55	+static struct pmic_irq_data mt6357_irqd = {
	56	+ .num_top = ARRAY_SIZE(mt6357_ints),
	57	+ .num_pmic_irqs = MT6357_IRQ_NR,
	58	+ .top_int_status_reg = MT6357_TOP_INT_STATUS0,
	59	+ .pmic_ints = mt6357_ints,
	60	+};
	61	+
42	62	static struct pmic_irq_data mt6358_irqd = {
43	63	.num_top = ARRAY_SIZE(mt6358_ints),
44	64	.num_pmic_irqs = MT6358_IRQ_NR,
@@ -211,6 +231,10 @@ int mt6358_irq_init(struct mt6397_chip *chip) · 166 unmodified lines
211	231	struct pmic_irq_data *irqd;
212	232
213	233	switch (chip->chip_id) {
	234	+ case MT6357_CHIP_ID:
	235	+ chip->irq_data = &mt6357_irqd;
	236	+ break;
	237	+
214	238	case MT6358_CHIP_ID:
215	239	case MT6366_CHIP_ID:
216	240	chip->irq_data = &mt6358_irqd;

drivers/mfd/mt6397-core.c+91−0

@@ -12,10 +12,14 @@ · 11 unmodified lines
12	12	#include <linux/regmap.h>
13	13	#include <linux/mfd/core.h>
14	14	#include <linux/mfd/mt6323/core.h>
	15	+#include <linux/mfd/mt6331/core.h>
	16	+#include <linux/mfd/mt6357/core.h>
15	17	#include <linux/mfd/mt6358/core.h>
16	18	#include <linux/mfd/mt6359/core.h>
17	19	#include <linux/mfd/mt6397/core.h>
18	20	#include <linux/mfd/mt6323/registers.h>
	21	+#include <linux/mfd/mt6331/registers.h>
	22	+#include <linux/mfd/mt6357/registers.h>
19	23	#include <linux/mfd/mt6358/registers.h>
20	24	#include <linux/mfd/mt6359/registers.h>
21	25	#include <linux/mfd/mt6397/registers.h>
@@ -23,6 +27,12 @@ · 1 unmodified line
23	27	#define MT6323_RTC_BASE 0x8000
24	28	#define MT6323_RTC_SIZE 0x40
25	29
	30	+#define MT6357_RTC_BASE 0x0588
	31	+#define MT6357_RTC_SIZE 0x3c
	32	+
	33	+#define MT6331_RTC_BASE 0x4000
	34	+#define MT6331_RTC_SIZE 0x40
	35	+
26	36	#define MT6358_RTC_BASE 0x0588
27	37	#define MT6358_RTC_SIZE 0x3c
28	38
@@ -37,6 +47,16 @@ static const struct resource mt6323_rtc_resources[] = { · 8 unmodified lines
37	47	DEFINE_RES_IRQ(MT6323_IRQ_STATUS_RTC),
38	48	};
39	49
	50	+static const struct resource mt6357_rtc_resources[] = {
	51	+ DEFINE_RES_MEM(MT6357_RTC_BASE, MT6357_RTC_SIZE),
	52	+ DEFINE_RES_IRQ(MT6357_IRQ_RTC),
	53	+};
	54	+
	55	+static const struct resource mt6331_rtc_resources[] = {
	56	+ DEFINE_RES_MEM(MT6331_RTC_BASE, MT6331_RTC_SIZE),
	57	+ DEFINE_RES_IRQ(MT6331_IRQ_STATUS_RTC),
	58	+};
	59	+
40	60	static const struct resource mt6358_rtc_resources[] = {
41	61	DEFINE_RES_MEM(MT6358_RTC_BASE, MT6358_RTC_SIZE),
42	62	DEFINE_RES_IRQ(MT6358_IRQ_RTC),
@@ -66,6 +86,18 @@ static const struct resource mt6323_keys_resources[] = { · 23 unmodified lines
66	86	DEFINE_RES_IRQ_NAMED(MT6323_IRQ_STATUS_FCHRKEY, "homekey"),
67	87	};
68	88
	89	+static const struct resource mt6357_keys_resources[] = {
	90	+ DEFINE_RES_IRQ_NAMED(MT6357_IRQ_PWRKEY, "powerkey"),
	91	+ DEFINE_RES_IRQ_NAMED(MT6357_IRQ_HOMEKEY, "homekey"),
	92	+ DEFINE_RES_IRQ_NAMED(MT6357_IRQ_PWRKEY_R, "powerkey_r"),
	93	+ DEFINE_RES_IRQ_NAMED(MT6357_IRQ_HOMEKEY_R, "homekey_r"),
	94	+};
	95	+
	96	+static const struct resource mt6331_keys_resources[] = {
	97	+ DEFINE_RES_IRQ_NAMED(MT6331_IRQ_STATUS_PWRKEY, "powerkey"),
	98	+ DEFINE_RES_IRQ_NAMED(MT6331_IRQ_STATUS_HOMEKEY, "homekey"),
	99	+};
	100	+
69	101	static const struct resource mt6397_keys_resources[] = {
70	102	DEFINE_RES_IRQ_NAMED(MT6397_IRQ_PWRKEY, "powerkey"),
71	103	DEFINE_RES_IRQ_NAMED(MT6397_IRQ_HOMEKEY, "homekey"),
@@ -100,6 +132,43 @@ static const struct mfd_cell mt6323_devs[] = { · 28 unmodified lines
100	132	},
101	133	};
102	134
	135	+static const struct mfd_cell mt6357_devs[] = {
	136	+ {
	137	+ .name = "mt6357-regulator",
	138	+ }, {
	139	+ .name = "mt6357-rtc",
	140	+ .num_resources = ARRAY_SIZE(mt6357_rtc_resources),
	141	+ .resources = mt6357_rtc_resources,
	142	+ .of_compatible = "mediatek,mt6357-rtc",
	143	+ }, {
	144	+ .name = "mtk-pmic-keys",
	145	+ .num_resources = ARRAY_SIZE(mt6357_keys_resources),
	146	+ .resources = mt6357_keys_resources,
	147	+ .of_compatible = "mediatek,mt6357-keys"
	148	+ },
	149	+};
	150	+
	151	+/* MT6331 is always used in combination with MT6332 */
	152	+static const struct mfd_cell mt6331_mt6332_devs[] = {
	153	+ {
	154	+ .name = "mt6331-rtc",
	155	+ .num_resources = ARRAY_SIZE(mt6331_rtc_resources),
	156	+ .resources = mt6331_rtc_resources,
	157	+ .of_compatible = "mediatek,mt6331-rtc",
	158	+ }, {
	159	+ .name = "mt6331-regulator",
	160	+ .of_compatible = "mediatek,mt6331-regulator"
	161	+ }, {
	162	+ .name = "mt6332-regulator",
	163	+ .of_compatible = "mediatek,mt6332-regulator"
	164	+ }, {
	165	+ .name = "mtk-pmic-keys",
	166	+ .num_resources = ARRAY_SIZE(mt6331_keys_resources),
	167	+ .resources = mt6331_keys_resources,
	168	+ .of_compatible = "mediatek,mt6331-keys"
	169	+ },
	170	+};
	171	+
103	172	static const struct mfd_cell mt6358_devs[] = {
104	173	{
105	174	.name = "mt6358-regulator",
@@ -179,6 +248,22 @@ static const struct chip_data mt6323_core = { · 73 unmodified lines
179	248	.irq_init = mt6397_irq_init,
180	249	};
181	250
	251	+static const struct chip_data mt6357_core = {
	252	+ .cid_addr = MT6357_SWCID,
	253	+ .cid_shift = 8,
	254	+ .cells = mt6357_devs,
	255	+ .cell_size = ARRAY_SIZE(mt6357_devs),
	256	+ .irq_init = mt6358_irq_init,
	257	+};
	258	+
	259	+static const struct chip_data mt6331_mt6332_core = {
	260	+ .cid_addr = MT6331_HWCID,
	261	+ .cid_shift = 0,
	262	+ .cells = mt6331_mt6332_devs,
	263	+ .cell_size = ARRAY_SIZE(mt6331_mt6332_devs),
	264	+ .irq_init = mt6397_irq_init,
	265	+};
	266	+
182	267	static const struct chip_data mt6358_core = {
183	268	.cid_addr = MT6358_SWCID,
184	269	.cid_shift = 8,
@@ -261,6 +346,12 @@ static const struct of_device_id mt6397_of_match[] = { · 76 unmodified lines
261	346	{
262	347	.compatible = "mediatek,mt6323",
263	348	.data = &mt6323_core,
	349	+ }, {
	350	+ .compatible = "mediatek,mt6331",
	351	+ .data = &mt6331_mt6332_core,
	352	+ }, {
	353	+ .compatible = "mediatek,mt6357",
	354	+ .data = &mt6357_core,
264	355	}, {
265	356	.compatible = "mediatek,mt6358",
266	357	.data = &mt6358_core,

drivers/mfd/mt6397-irq.c+8−1

@@ -12,6 +12,8 @@ · 11 unmodified lines
12	12	#include <linux/suspend.h>
13	13	#include <linux/mfd/mt6323/core.h>
14	14	#include <linux/mfd/mt6323/registers.h>
	15	+#include <linux/mfd/mt6331/core.h>
	16	+#include <linux/mfd/mt6331/registers.h>
15	17	#include <linux/mfd/mt6397/core.h>
16	18	#include <linux/mfd/mt6397/registers.h>
17	19
@@ -172,7 +174,12 @@ int mt6397_irq_init(struct mt6397_chip *chip) · 154 unmodified lines
172	174	chip->int_status[0] = MT6323_INT_STATUS0;
173	175	chip->int_status[1] = MT6323_INT_STATUS1;
174	176	break;
175		−
	177	+ case MT6331_CHIP_ID:
	178	+ chip->int_con[0] = MT6331_INT_CON0;
	179	+ chip->int_con[1] = MT6331_INT_CON1;
	180	+ chip->int_status[0] = MT6331_INT_STATUS_CON0;
	181	+ chip->int_status[1] = MT6331_INT_STATUS_CON1;
	182	+ break;
176	183	case MT6391_CHIP_ID:
177	184	case MT6397_CHIP_ID:
178	185	chip->int_con[0] = MT6397_INT_CON0;

drivers/mfd/qcom-pm8008.c+20−33

@@ -54,13 +54,6 @@ enum { · 53 unmodified lines
54	54
55	55	#define PM8008_PERIPH_OFFSET(paddr) (paddr - PM8008_PERIPH_0_BASE)
56	56
57		−struct pm8008_data {
58		− struct device *dev;
59		− struct regmap *regmap;
60		− int irq;
61		− struct regmap_irq_chip_data *irq_data;
62		−};
63		−
64	57	static unsigned int p0_offs[] = {PM8008_PERIPH_OFFSET(PM8008_PERIPH_0_BASE)};
65	58	static unsigned int p1_offs[] = {PM8008_PERIPH_OFFSET(PM8008_PERIPH_1_BASE)};
66	59	static unsigned int p2_offs[] = {PM8008_PERIPH_OFFSET(PM8008_PERIPH_2_BASE)};
@@ -150,7 +143,7 @@ static struct regmap_config qcom_mfd_regmap_cfg = { · 83 unmodified lines
150	143	.max_register = 0xFFFF,
151	144	};
152	145
153		−static int pm8008_init(struct pm8008_data *chip)
	146	+static int pm8008_init(struct regmap *regmap)
154	147	{
155	148	int rc;
156	149
@@ -160,34 +153,31 @@ static int pm8008_init(struct pm8008_data *chip) · 3 unmodified lines
160	153	* This is required to enable the writing of TYPE registers in
161	154	* regmap_irq_sync_unlock().
162	155	*/
163		− rc = regmap_write(chip->regmap,
164		− (PM8008_TEMP_ALARM_ADDR \| INT_SET_TYPE_OFFSET),
165		− BIT(0));
	156	+ rc = regmap_write(regmap, (PM8008_TEMP_ALARM_ADDR \| INT_SET_TYPE_OFFSET), BIT(0));
166	157	if (rc)
167	158	return rc;
168	159
169	160	/* Do the same for GPIO1 and GPIO2 peripherals */
170		− rc = regmap_write(chip->regmap,
171		− (PM8008_GPIO1_ADDR \| INT_SET_TYPE_OFFSET), BIT(0));
	161	+ rc = regmap_write(regmap, (PM8008_GPIO1_ADDR \| INT_SET_TYPE_OFFSET), BIT(0));
172	162	if (rc)
173	163	return rc;
174	164
175		− rc = regmap_write(chip->regmap,
176		− (PM8008_GPIO2_ADDR \| INT_SET_TYPE_OFFSET), BIT(0));
	165	+ rc = regmap_write(regmap, (PM8008_GPIO2_ADDR \| INT_SET_TYPE_OFFSET), BIT(0));
177	166
178	167	return rc;
179	168	}
180	169
181		−static int pm8008_probe_irq_peripherals(struct pm8008_data *chip,
	170	+static int pm8008_probe_irq_peripherals(struct device *dev,
	171	+ struct regmap *regmap,
182	172	int client_irq)
183	173	{
184	174	int rc, i;
185	175	struct regmap_irq_type *type;
186	176	struct regmap_irq_chip_data *irq_data;
187	177
188		− rc = pm8008_init(chip);
	178	+ rc = pm8008_init(regmap);
189	179	if (rc) {
190		− dev_err(chip->dev, "Init failed: %d\n", rc);
	180	+ dev_err(dev, "Init failed: %d\n", rc);
191	181	return rc;
192	182	}
193	183
@@ -207,10 +197,10 @@ static int pm8008_probe_irq_peripherals(struct pm8008_data *chip, · 13 unmodified lines
207	197	IRQ_TYPE_LEVEL_HIGH \| IRQ_TYPE_LEVEL_LOW);
208	198	}
209	199
210		− rc = devm_regmap_add_irq_chip(chip->dev, chip->regmap, client_irq,
	200	+ rc = devm_regmap_add_irq_chip(dev, regmap, client_irq,
211	201	IRQF_SHARED, 0, &pm8008_irq_chip, &irq_data);
212	202	if (rc) {
213		− dev_err(chip->dev, "Failed to add IRQ chip: %d\n", rc);
	203	+ dev_err(dev, "Failed to add IRQ chip: %d\n", rc);
214	204	return rc;
215	205	}
216	206
@@ -220,26 +210,23 @@ static int pm8008_probe_irq_peripherals(struct pm8008_data *chip, · 3 unmodified lines
220	210	static int pm8008_probe(struct i2c_client *client)
221	211	{
222	212	int rc;
223		− struct pm8008_data *chip;
224		−
225		− chip = devm_kzalloc(&client->dev, sizeof(*chip), GFP_KERNEL);
226		− if (!chip)
227		− return -ENOMEM;
	213	+ struct device *dev;
	214	+ struct regmap *regmap;
228	215
229		− chip->dev = &client->dev;
230		− chip->regmap = devm_regmap_init_i2c(client, &qcom_mfd_regmap_cfg);
231		− if (!chip->regmap)
	216	+ dev = &client->dev;
	217	+ regmap = devm_regmap_init_i2c(client, &qcom_mfd_regmap_cfg);
	218	+ if (!regmap)
232	219	return -ENODEV;
233	220
234		− i2c_set_clientdata(client, chip);
	221	+ i2c_set_clientdata(client, regmap);
235	222
236		− if (of_property_read_bool(chip->dev->of_node, "interrupt-controller")) {
237		− rc = pm8008_probe_irq_peripherals(chip, client->irq);
	223	+ if (of_property_read_bool(dev->of_node, "interrupt-controller")) {
	224	+ rc = pm8008_probe_irq_peripherals(dev, regmap, client->irq);
238	225	if (rc)
239		− dev_err(chip->dev, "Failed to probe irq periphs: %d\n", rc);
	226	+ dev_err(dev, "Failed to probe irq periphs: %d\n", rc);
240	227	}
241	228
242		− return devm_of_platform_populate(chip->dev);
	229	+ return devm_of_platform_populate(dev);
243	230	}
244	231
245	232	static const struct of_device_id pm8008_match[] = {

drivers/mfd/syscon.c+1−2

@@ -101,8 +101,7 @@ static struct syscon of_syscon_register(struct device_node np, bool check_clk) · 100 unmodified lines
101	101	}
102	102	}
103	103
104		− syscon_config.name = kasprintf(GFP_KERNEL, "%pOFn@%llx", np,
105		− (u64)res.start);
	104	+ syscon_config.name = kasprintf(GFP_KERNEL, "%pOFn@%pa", np, &res.start);
106	105	syscon_config.reg_stride = reg_io_width;
107	106	syscon_config.val_bits = reg_io_width * 8;
108	107	syscon_config.max_register = resource_size(&res) - reg_io_width;

drivers/mfd/t7l66xb.c+1−5

@@ -397,11 +397,8 @@ err_noirq: · 396 unmodified lines
397	397
398	398	static int t7l66xb_remove(struct platform_device *dev)
399	399	{
400		− struct t7l66xb_platform_data *pdata = dev_get_platdata(&dev->dev);
401	400	struct t7l66xb *t7l66xb = platform_get_drvdata(dev);
402		− int ret;
403	401
404		− ret = pdata->disable(dev);
405	402	clk_disable_unprepare(t7l66xb->clk48m);
406	403	clk_put(t7l66xb->clk48m);
407	404	clk_disable_unprepare(t7l66xb->clk32k);
@@ -412,8 +409,7 @@ static int t7l66xb_remove(struct platform_device *dev) · 4 unmodified lines
412	409	mfd_remove_devices(&dev->dev);
413	410	kfree(t7l66xb);
414	411
415		− return ret;
416		−
	412	+ return 0;
417	413	}
418	414
419	415	static struct platform_driver t7l66xb_platform_driver = {

drivers/mfd/tc6393xb.c+2−3

@@ -798,20 +798,19 @@ static int tc6393xb_remove(struct platform_device *dev) · 797 unmodified lines
798	798	{
799	799	struct tc6393xb_platform_data *tcpd = dev_get_platdata(&dev->dev);
800	800	struct tc6393xb *tc6393xb = platform_get_drvdata(dev);
801		− int ret;
802	801
803	802	mfd_remove_devices(&dev->dev);
804	803
805	804	tc6393xb_detach_irq(dev);
806	805
807		− ret = tcpd->disable(dev);
	806	+ tcpd->disable(dev);
808	807	clk_disable_unprepare(tc6393xb->clk);
809	808	iounmap(tc6393xb->scr);
810	809	release_resource(&tc6393xb->rscr);
811	810	clk_put(tc6393xb->clk);
812	811	kfree(tc6393xb);
813	812
814		− return ret;
	813	+ return 0;
815	814	}
816	815
817	816	#ifdef CONFIG_PM

drivers/mfd/twl-core.c+5−318

@@ -656,309 +656,6 @@ static inline struct device add_child(unsigned mod_no, const char name, · 655 unmodified lines
656	656	can_wakeup, irq0, irq1);
657	657	}
658	658
659		−static struct device *
660		−add_regulator_linked(int num, struct regulator_init_data *pdata,
661		− struct regulator_consumer_supply *consumers,
662		− unsigned num_consumers, unsigned long features)
663		−{
664		− struct twl_regulator_driver_data drv_data;
665		−
666		− /* regulator framework demands init_data ... */
667		− if (!pdata)
668		− return NULL;
669		−
670		− if (consumers) {
671		− pdata->consumer_supplies = consumers;
672		− pdata->num_consumer_supplies = num_consumers;
673		− }
674		−
675		− if (pdata->driver_data) {
676		− /* If we have existing drv_data, just add the flags */
677		− struct twl_regulator_driver_data *tmp;
678		− tmp = pdata->driver_data;
679		− tmp->features \|= features;
680		− } else {
681		− /* add new driver data struct, used only during init */
682		− drv_data.features = features;
683		− drv_data.set_voltage = NULL;
684		− drv_data.get_voltage = NULL;
685		− drv_data.data = NULL;
686		− pdata->driver_data = &drv_data;
687		− }
688		−
689		− /* NOTE: we currently ignore regulator IRQs, e.g. for short circuits */
690		− return add_numbered_child(TWL_MODULE_PM_MASTER, "twl_reg", num,
691		− pdata, sizeof(*pdata), false, 0, 0);
692		−}
693		−
694		−static struct device *
695		−add_regulator(int num, struct regulator_init_data *pdata,
696		− unsigned long features)
697		−{
698		− return add_regulator_linked(num, pdata, NULL, 0, features);
699		−}
700		−
701		−/*
702		− * NOTE: We know the first 8 IRQs after pdata->base_irq are
703		− * for the PIH, and the next are for the PWR_INT SIH, since
704		− * that's how twl_init_irq() sets things up.
705		− */
706		−
707		−static int
708		−add_children(struct twl4030_platform_data *pdata, unsigned irq_base,
709		− unsigned long features)
710		−{
711		− struct device *child;
712		−
713		− if (IS_ENABLED(CONFIG_GPIO_TWL4030) && pdata->gpio) {
714		− child = add_child(TWL4030_MODULE_GPIO, "twl4030_gpio",
715		− pdata->gpio, sizeof(*pdata->gpio),
716		− false, irq_base + GPIO_INTR_OFFSET, 0);
717		− if (IS_ERR(child))
718		− return PTR_ERR(child);
719		− }
720		−
721		− if (IS_ENABLED(CONFIG_KEYBOARD_TWL4030) && pdata->keypad) {
722		− child = add_child(TWL4030_MODULE_KEYPAD, "twl4030_keypad",
723		− pdata->keypad, sizeof(*pdata->keypad),
724		− true, irq_base + KEYPAD_INTR_OFFSET, 0);
725		− if (IS_ERR(child))
726		− return PTR_ERR(child);
727		− }
728		−
729		− if (IS_ENABLED(CONFIG_TWL4030_MADC) && pdata->madc &&
730		− twl_class_is_4030()) {
731		− child = add_child(TWL4030_MODULE_MADC, "twl4030_madc",
732		− pdata->madc, sizeof(*pdata->madc),
733		− true, irq_base + MADC_INTR_OFFSET, 0);
734		− if (IS_ERR(child))
735		− return PTR_ERR(child);
736		− }
737		−
738		− if (IS_ENABLED(CONFIG_RTC_DRV_TWL4030)) {
739		− /*
740		− * REVISIT platform_data here currently might expose the
741		− * "msecure" line ... but for now we just expect board
742		− * setup to tell the chip "it's always ok to SET_TIME".
743		− * Eventually, Linux might become more aware of such
744		− * HW security concerns, and "least privilege".
745		− */
746		− child = add_child(TWL_MODULE_RTC, "twl_rtc", NULL, 0,
747		− true, irq_base + RTC_INTR_OFFSET, 0);
748		− if (IS_ERR(child))
749		− return PTR_ERR(child);
750		− }
751		−
752		− if (IS_ENABLED(CONFIG_PWM_TWL)) {
753		− child = add_child(TWL_MODULE_PWM, "twl-pwm", NULL, 0,
754		− false, 0, 0);
755		− if (IS_ERR(child))
756		− return PTR_ERR(child);
757		− }
758		−
759		− if (IS_ENABLED(CONFIG_PWM_TWL_LED)) {
760		− child = add_child(TWL_MODULE_LED, "twl-pwmled", NULL, 0,
761		− false, 0, 0);
762		− if (IS_ERR(child))
763		− return PTR_ERR(child);
764		− }
765		−
766		− if (IS_ENABLED(CONFIG_TWL4030_USB) && pdata->usb &&
767		− twl_class_is_4030()) {
768		−
769		− static struct regulator_consumer_supply usb1v5 = {
770		− .supply = "usb1v5",
771		− };
772		− static struct regulator_consumer_supply usb1v8 = {
773		− .supply = "usb1v8",
774		− };
775		− static struct regulator_consumer_supply usb3v1 = {
776		− .supply = "usb3v1",
777		− };
778		−
779		− /* First add the regulators so that they can be used by transceiver */
780		− if (IS_ENABLED(CONFIG_REGULATOR_TWL4030)) {
781		− /* this is a template that gets copied */
782		− struct regulator_init_data usb_fixed = {
783		− .constraints.valid_modes_mask =
784		− REGULATOR_MODE_NORMAL
785		− \| REGULATOR_MODE_STANDBY,
786		− .constraints.valid_ops_mask =
787		− REGULATOR_CHANGE_MODE
788		− \| REGULATOR_CHANGE_STATUS,
789		− };
790		−
791		− child = add_regulator_linked(TWL4030_REG_VUSB1V5,
792		− &usb_fixed, &usb1v5, 1,
793		− features);
794		− if (IS_ERR(child))
795		− return PTR_ERR(child);
796		−
797		− child = add_regulator_linked(TWL4030_REG_VUSB1V8,
798		− &usb_fixed, &usb1v8, 1,
799		− features);
800		− if (IS_ERR(child))
801		− return PTR_ERR(child);
802		−
803		− child = add_regulator_linked(TWL4030_REG_VUSB3V1,
804		− &usb_fixed, &usb3v1, 1,
805		− features);
806		− if (IS_ERR(child))
807		− return PTR_ERR(child);
808		−
809		− }
810		−
811		− child = add_child(TWL_MODULE_USB, "twl4030_usb",
812		− pdata->usb, sizeof(*pdata->usb), true,
813		− /* irq0 = USB_PRES, irq1 = USB */
814		− irq_base + USB_PRES_INTR_OFFSET,
815		− irq_base + USB_INTR_OFFSET);
816		−
817		− if (IS_ERR(child))
818		− return PTR_ERR(child);
819		−
820		− /* we need to connect regulators to this transceiver */
821		− if (IS_ENABLED(CONFIG_REGULATOR_TWL4030) && child) {
822		− usb1v5.dev_name = dev_name(child);
823		− usb1v8.dev_name = dev_name(child);
824		− usb3v1.dev_name = dev_name(child);
825		− }
826		− }
827		−
828		− if (IS_ENABLED(CONFIG_TWL4030_WATCHDOG) && twl_class_is_4030()) {
829		− child = add_child(TWL_MODULE_PM_RECEIVER, "twl4030_wdt", NULL,
830		− 0, false, 0, 0);
831		− if (IS_ERR(child))
832		− return PTR_ERR(child);
833		− }
834		−
835		− if (IS_ENABLED(CONFIG_INPUT_TWL4030_PWRBUTTON) && twl_class_is_4030()) {
836		− child = add_child(TWL_MODULE_PM_MASTER, "twl4030_pwrbutton",
837		− NULL, 0, true, irq_base + 8 + 0, 0);
838		− if (IS_ERR(child))
839		− return PTR_ERR(child);
840		− }
841		−
842		− if (IS_ENABLED(CONFIG_MFD_TWL4030_AUDIO) && pdata->audio &&
843		− twl_class_is_4030()) {
844		− child = add_child(TWL4030_MODULE_AUDIO_VOICE, "twl4030-audio",
845		− pdata->audio, sizeof(*pdata->audio),
846		− false, 0, 0);
847		− if (IS_ERR(child))
848		− return PTR_ERR(child);
849		− }
850		−
851		− /* twl4030 regulators */
852		− if (IS_ENABLED(CONFIG_REGULATOR_TWL4030) && twl_class_is_4030()) {
853		− child = add_regulator(TWL4030_REG_VPLL1, pdata->vpll1,
854		− features);
855		− if (IS_ERR(child))
856		− return PTR_ERR(child);
857		−
858		− child = add_regulator(TWL4030_REG_VIO, pdata->vio,
859		− features);
860		− if (IS_ERR(child))
861		− return PTR_ERR(child);
862		−
863		− child = add_regulator(TWL4030_REG_VDD1, pdata->vdd1,
864		− features);
865		− if (IS_ERR(child))
866		− return PTR_ERR(child);
867		−
868		− child = add_regulator(TWL4030_REG_VDD2, pdata->vdd2,
869		− features);
870		− if (IS_ERR(child))
871		− return PTR_ERR(child);
872		−
873		− child = add_regulator(TWL4030_REG_VMMC1, pdata->vmmc1,
874		− features);
875		− if (IS_ERR(child))
876		− return PTR_ERR(child);
877		−
878		− child = add_regulator(TWL4030_REG_VDAC, pdata->vdac,
879		− features);
880		− if (IS_ERR(child))
881		− return PTR_ERR(child);
882		−
883		− child = add_regulator((features & TWL4030_VAUX2)
884		− ? TWL4030_REG_VAUX2_4030
885		− : TWL4030_REG_VAUX2,
886		− pdata->vaux2, features);
887		− if (IS_ERR(child))
888		− return PTR_ERR(child);
889		−
890		− child = add_regulator(TWL4030_REG_VINTANA1, pdata->vintana1,
891		− features);
892		− if (IS_ERR(child))
893		− return PTR_ERR(child);
894		−
895		− child = add_regulator(TWL4030_REG_VINTANA2, pdata->vintana2,
896		− features);
897		− if (IS_ERR(child))
898		− return PTR_ERR(child);
899		−
900		− child = add_regulator(TWL4030_REG_VINTDIG, pdata->vintdig,
901		− features);
902		− if (IS_ERR(child))
903		− return PTR_ERR(child);
904		− }
905		−
906		− /* maybe add LDOs that are omitted on cost-reduced parts */
907		− if (IS_ENABLED(CONFIG_REGULATOR_TWL4030) && !(features & TPS_SUBSET)
908		− && twl_class_is_4030()) {
909		− child = add_regulator(TWL4030_REG_VPLL2, pdata->vpll2,
910		− features);
911		− if (IS_ERR(child))
912		− return PTR_ERR(child);
913		−
914		− child = add_regulator(TWL4030_REG_VMMC2, pdata->vmmc2,
915		− features);
916		− if (IS_ERR(child))
917		− return PTR_ERR(child);
918		−
919		− child = add_regulator(TWL4030_REG_VSIM, pdata->vsim,
920		− features);
921		− if (IS_ERR(child))
922		− return PTR_ERR(child);
923		−
924		− child = add_regulator(TWL4030_REG_VAUX1, pdata->vaux1,
925		− features);
926		− if (IS_ERR(child))
927		− return PTR_ERR(child);
928		−
929		− child = add_regulator(TWL4030_REG_VAUX3, pdata->vaux3,
930		− features);
931		− if (IS_ERR(child))
932		− return PTR_ERR(child);
933		−
934		− child = add_regulator(TWL4030_REG_VAUX4, pdata->vaux4,
935		− features);
936		− if (IS_ERR(child))
937		− return PTR_ERR(child);
938		− }
939		−
940		− if (IS_ENABLED(CONFIG_CHARGER_TWL4030) && pdata->bci &&
941		− !(features & (TPS_SUBSET \| TWL5031))) {
942		− child = add_child(TWL_MODULE_MAIN_CHARGE, "twl4030_bci",
943		− pdata->bci, sizeof(*pdata->bci), false,
944		− /* irq0 = CHG_PRES, irq1 = BCI */
945		− irq_base + BCI_PRES_INTR_OFFSET,
946		− irq_base + BCI_INTR_OFFSET);
947		− if (IS_ERR(child))
948		− return PTR_ERR(child);
949		− }
950		−
951		− if (IS_ENABLED(CONFIG_TWL4030_POWER) && pdata->power) {
952		− child = add_child(TWL_MODULE_PM_MASTER, "twl4030_power",
953		− pdata->power, sizeof(*pdata->power), false,
954		− 0, 0);
955		− if (IS_ERR(child))
956		− return PTR_ERR(child);
957		− }
958		−
959		− return 0;
960		−}
961		−
962	659	/----------------------------------------------------------------------/
963	660
964	661	/*
@@ -987,8 +684,7 @@ static inline int unprotect_pm_master(void) · 22 unmodified lines
987	684	return e;
988	685	}
989	686
990		−static void clocks_init(struct device *dev,
991		− struct twl4030_clock_init_data *clock)
	687	+static void clocks_init(struct device *dev)
992	688	{
993	689	int e = 0;
994	690	struct clk *osc;
@@ -1018,8 +714,6 @@ static void clocks_init(struct device *dev, · 23 unmodified lines
1018	714	}
1019	715
1020	716	ctrl \|= HIGH_PERF_SQ;
1021		− if (clock && clock->ck32k_lowpwr_enable)
1022		− ctrl \|= CK32K_LOWPWR_EN;
1023	717
1024	718	e \|= unprotect_pm_master();
1025	719	/* effect->MADC+USB ck en */
@@ -1063,7 +757,6 @@ static struct of_dev_auxdata twl_auxdata_lookup[] = { · 37 unmodified lines
1063	757	static int
1064	758	twl_probe(struct i2c_client client, const struct i2c_device_id id)
1065	759	{
1066		− struct twl4030_platform_data *pdata = dev_get_platdata(&client->dev);
1067	760	struct device_node *node = client->dev.of_node;
1068	761	struct platform_device *pdev;
1069	762	const struct regmap_config *twl_regmap_config;
@@ -1071,7 +764,7 @@ twl_probe(struct i2c_client client, const struct i2c_device_id id) · 1 unmodified line
1071	764	int status;
1072	765	unsigned i, num_slaves;
1073	766
1074		− if (!node && !pdata) {
	767	+ if (!node) {
1075	768	dev_err(&client->dev, "no platform data\n");
1076	769	return -EINVAL;
1077	770	}
@@ -1161,7 +854,7 @@ twl_probe(struct i2c_client client, const struct i2c_device_id id) · 83 unmodified lines
1161	854	twl_priv->ready = true;
1162	855
1163	856	/* setup clock framework */
1164		− clocks_init(&client->dev, pdata ? pdata->clock : NULL);
	857	+ clocks_init(&client->dev);
1165	858
1166	859	/* read TWL IDCODE Register */
1167	860	if (twl_class_is_4030()) {
@@ -1209,14 +902,8 @@ twl_probe(struct i2c_client client, const struct i2c_device_id id) · 41 unmodified lines
1209	902	TWL4030_DCDC_GLOBAL_CFG);
1210	903	}
1211	904
1212		− if (node) {
1213		− if (pdata)
1214		− twl_auxdata_lookup[0].platform_data = pdata->gpio;
1215		− status = of_platform_populate(node, NULL, twl_auxdata_lookup,
1216		− &client->dev);
1217		− } else {
1218		− status = add_children(pdata, irq_base, id->driver_data);
1219		− }
	905	+ status = of_platform_populate(node, NULL, twl_auxdata_lookup,
	906	+ &client->dev);
1220	907
1221	908	fail:
1222	909	if (status < 0)

include/linux/mfd/ipaq-micro.h+2−2

@@ -75,8 +75,8 @@ struct ipaq_micro_rxdev { · 74 unmodified lines
75	75	* @id: 4-bit ID of the message
76	76	* @tx_len: length of TX data
77	77	* @tx_data: TX data to send
78		− * @rx_len: length of receieved RX data
79		− * @rx_data: RX data to recieve
	78	+ * @rx_len: length of received RX data
	79	+ * @rx_data: RX data to receive
80	80	* @ack: a completion that will be completed when RX is complete
81	81	* @node: list node if message gets queued
82	82	*/

include/linux/mfd/max77714.h+1−1

@@ -3,7 +3,7 @@ · 2 unmodified lines
3	3	* Maxim MAX77714 Register and data structures definition.
4	4	*
5	5	* Copyright (C) 2022 Luca Ceresoli
6		− * Author: Luca Ceresoli <luca@lucaceresoli.net>
	6	+ * Author: Luca Ceresoli <luca.ceresoli@bootlin.com>
7	7	*/
8	8
9	9	#ifndef __LINUX_MFD_MAX77714_H_

include/linux/mfd/mt6331/core.h+40−0

@@ -0,0 +1,40 @@
	1	+/* SPDX-License-Identifier: GPL-2.0-only */
	2	+/*
	3	+ * Copyright (c) 2022 AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
	4	+ */
	5	+
	6	+#ifndef __MFD_MT6331_CORE_H__
	7	+#define __MFD_MT6331_CORE_H__
	8	+
	9	+enum mt6331_irq_status_numbers {
	10	+ MT6331_IRQ_STATUS_PWRKEY = 0,
	11	+ MT6331_IRQ_STATUS_HOMEKEY,
	12	+ MT6331_IRQ_STATUS_CHRDET,
	13	+ MT6331_IRQ_STATUS_THR_H,
	14	+ MT6331_IRQ_STATUS_THR_L,
	15	+ MT6331_IRQ_STATUS_BAT_H,
	16	+ MT6331_IRQ_STATUS_BAT_L,
	17	+ MT6331_IRQ_STATUS_RTC,
	18	+ MT6331_IRQ_STATUS_AUDIO,
	19	+ MT6331_IRQ_STATUS_MAD,
	20	+ MT6331_IRQ_STATUS_ACCDET,
	21	+ MT6331_IRQ_STATUS_ACCDET_EINT,
	22	+ MT6331_IRQ_STATUS_ACCDET_NEGV = 12,
	23	+ MT6331_IRQ_STATUS_VDVFS11_OC = 16,
	24	+ MT6331_IRQ_STATUS_VDVFS12_OC,
	25	+ MT6331_IRQ_STATUS_VDVFS13_OC,
	26	+ MT6331_IRQ_STATUS_VDVFS14_OC,
	27	+ MT6331_IRQ_STATUS_GPU_OC,
	28	+ MT6331_IRQ_STATUS_VCORE1_OC,
	29	+ MT6331_IRQ_STATUS_VCORE2_OC,
	30	+ MT6331_IRQ_STATUS_VIO18_OC,
	31	+ MT6331_IRQ_STATUS_LDO_OC,
	32	+ MT6331_IRQ_STATUS_NR,
	33	+};
	34	+
	35	+#define MT6331_IRQ_CON0_BASE MT6331_IRQ_STATUS_PWRKEY
	36	+#define MT6331_IRQ_CON0_BITS (MT6331_IRQ_STATUS_ACCDET_NEGV + 1)
	37	+#define MT6331_IRQ_CON1_BASE MT6331_IRQ_STATUS_VDVFS11_OC
	38	+#define MT6331_IRQ_CON1_BITS (MT6331_IRQ_STATUS_LDO_OC - MT6331_IRQ_STATUS_VDFS11_OC + 1)
	39	+
	40	+#endif /* __MFD_MT6331_CORE_H__ */

include/linux/mfd/mt6331/registers.h+584−0

@@ -0,0 +1,584 @@
	1	+/* SPDX-License-Identifier: GPL-2.0-only */
	2	+/*
	3	+ * Copyright (c) 2022 AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
	4	+ */
	5	+
	6	+#ifndef __MFD_MT6331_REGISTERS_H__
	7	+#define __MFD_MT6331_REGISTERS_H__
	8	+
	9	+/* PMIC Registers */
	10	+#define MT6331_STRUP_CON0 0x0
	11	+#define MT6331_STRUP_CON2 0x2
	12	+#define MT6331_STRUP_CON3 0x4
	13	+#define MT6331_STRUP_CON4 0x6
	14	+#define MT6331_STRUP_CON5 0x8
	15	+#define MT6331_STRUP_CON6 0xA
	16	+#define MT6331_STRUP_CON7 0xC
	17	+#define MT6331_STRUP_CON8 0xE
	18	+#define MT6331_STRUP_CON9 0x10
	19	+#define MT6331_STRUP_CON10 0x12
	20	+#define MT6331_STRUP_CON11 0x14
	21	+#define MT6331_STRUP_CON12 0x16
	22	+#define MT6331_STRUP_CON13 0x18
	23	+#define MT6331_STRUP_CON14 0x1A
	24	+#define MT6331_STRUP_CON15 0x1C
	25	+#define MT6331_STRUP_CON16 0x1E
	26	+#define MT6331_STRUP_CON17 0x20
	27	+#define MT6331_STRUP_CON18 0x22
	28	+#define MT6331_HWCID 0x100
	29	+#define MT6331_SWCID 0x102
	30	+#define MT6331_EXT_PMIC_STATUS 0x104
	31	+#define MT6331_TOP_CON 0x106
	32	+#define MT6331_TEST_OUT 0x108
	33	+#define MT6331_TEST_CON0 0x10A
	34	+#define MT6331_TEST_CON1 0x10C
	35	+#define MT6331_TESTMODE_SW 0x10E
	36	+#define MT6331_EN_STATUS0 0x110
	37	+#define MT6331_EN_STATUS1 0x112
	38	+#define MT6331_EN_STATUS2 0x114
	39	+#define MT6331_OCSTATUS0 0x116
	40	+#define MT6331_OCSTATUS1 0x118
	41	+#define MT6331_OCSTATUS2 0x11A
	42	+#define MT6331_PGSTATUS 0x11C
	43	+#define MT6331_TOPSTATUS 0x11E
	44	+#define MT6331_TDSEL_CON 0x120
	45	+#define MT6331_RDSEL_CON 0x122
	46	+#define MT6331_SMT_CON0 0x124
	47	+#define MT6331_SMT_CON1 0x126
	48	+#define MT6331_SMT_CON2 0x128
	49	+#define MT6331_DRV_CON0 0x12A
	50	+#define MT6331_DRV_CON1 0x12C
	51	+#define MT6331_DRV_CON2 0x12E
	52	+#define MT6331_DRV_CON3 0x130
	53	+#define MT6331_TOP_STATUS 0x132
	54	+#define MT6331_TOP_STATUS_SET 0x134
	55	+#define MT6331_TOP_STATUS_CLR 0x136
	56	+#define MT6331_TOP_CKPDN_CON0 0x138
	57	+#define MT6331_TOP_CKPDN_CON0_SET 0x13A
	58	+#define MT6331_TOP_CKPDN_CON0_CLR 0x13C
	59	+#define MT6331_TOP_CKPDN_CON1 0x13E
	60	+#define MT6331_TOP_CKPDN_CON1_SET 0x140
	61	+#define MT6331_TOP_CKPDN_CON1_CLR 0x142
	62	+#define MT6331_TOP_CKPDN_CON2 0x144
	63	+#define MT6331_TOP_CKPDN_CON2_SET 0x146
	64	+#define MT6331_TOP_CKPDN_CON2_CLR 0x148
	65	+#define MT6331_TOP_CKSEL_CON 0x14A
	66	+#define MT6331_TOP_CKSEL_CON_SET 0x14C
	67	+#define MT6331_TOP_CKSEL_CON_CLR 0x14E
	68	+#define MT6331_TOP_CKHWEN_CON 0x150
	69	+#define MT6331_TOP_CKHWEN_CON_SET 0x152
	70	+#define MT6331_TOP_CKHWEN_CON_CLR 0x154
	71	+#define MT6331_TOP_CKTST_CON0 0x156
	72	+#define MT6331_TOP_CKTST_CON1 0x158
	73	+#define MT6331_TOP_CLKSQ 0x15A
	74	+#define MT6331_TOP_CLKSQ_SET 0x15C
	75	+#define MT6331_TOP_CLKSQ_CLR 0x15E
	76	+#define MT6331_TOP_RST_CON 0x160
	77	+#define MT6331_TOP_RST_CON_SET 0x162
	78	+#define MT6331_TOP_RST_CON_CLR 0x164
	79	+#define MT6331_TOP_RST_MISC 0x166
	80	+#define MT6331_TOP_RST_MISC_SET 0x168
	81	+#define MT6331_TOP_RST_MISC_CLR 0x16A
	82	+#define MT6331_INT_CON0 0x16C
	83	+#define MT6331_INT_CON0_SET 0x16E
	84	+#define MT6331_INT_CON0_CLR 0x170
	85	+#define MT6331_INT_CON1 0x172
	86	+#define MT6331_INT_CON1_SET 0x174
	87	+#define MT6331_INT_CON1_CLR 0x176
	88	+#define MT6331_INT_MISC_CON 0x178
	89	+#define MT6331_INT_MISC_CON_SET 0x17A
	90	+#define MT6331_INT_MISC_CON_CLR 0x17C
	91	+#define MT6331_INT_STATUS_CON0 0x17E
	92	+#define MT6331_INT_STATUS_CON1 0x180
	93	+#define MT6331_OC_GEAR_0 0x182
	94	+#define MT6331_FQMTR_CON0 0x184
	95	+#define MT6331_FQMTR_CON1 0x186
	96	+#define MT6331_FQMTR_CON2 0x188
	97	+#define MT6331_RG_SPI_CON 0x18A
	98	+#define MT6331_DEW_DIO_EN 0x18C
	99	+#define MT6331_DEW_READ_TEST 0x18E
	100	+#define MT6331_DEW_WRITE_TEST 0x190
	101	+#define MT6331_DEW_CRC_SWRST 0x192
	102	+#define MT6331_DEW_CRC_EN 0x194
	103	+#define MT6331_DEW_CRC_VAL 0x196
	104	+#define MT6331_DEW_DBG_MON_SEL 0x198
	105	+#define MT6331_DEW_CIPHER_KEY_SEL 0x19A
	106	+#define MT6331_DEW_CIPHER_IV_SEL 0x19C
	107	+#define MT6331_DEW_CIPHER_EN 0x19E
	108	+#define MT6331_DEW_CIPHER_RDY 0x1A0
	109	+#define MT6331_DEW_CIPHER_MODE 0x1A2
	110	+#define MT6331_DEW_CIPHER_SWRST 0x1A4
	111	+#define MT6331_DEW_RDDMY_NO 0x1A6
	112	+#define MT6331_INT_TYPE_CON0 0x1A8
	113	+#define MT6331_INT_TYPE_CON0_SET 0x1AA
	114	+#define MT6331_INT_TYPE_CON0_CLR 0x1AC
	115	+#define MT6331_INT_TYPE_CON1 0x1AE
	116	+#define MT6331_INT_TYPE_CON1_SET 0x1B0
	117	+#define MT6331_INT_TYPE_CON1_CLR 0x1B2
	118	+#define MT6331_INT_STA 0x1B4
	119	+#define MT6331_BUCK_ALL_CON0 0x200
	120	+#define MT6331_BUCK_ALL_CON1 0x202
	121	+#define MT6331_BUCK_ALL_CON2 0x204
	122	+#define MT6331_BUCK_ALL_CON3 0x206
	123	+#define MT6331_BUCK_ALL_CON4 0x208
	124	+#define MT6331_BUCK_ALL_CON5 0x20A
	125	+#define MT6331_BUCK_ALL_CON6 0x20C
	126	+#define MT6331_BUCK_ALL_CON7 0x20E
	127	+#define MT6331_BUCK_ALL_CON8 0x210
	128	+#define MT6331_BUCK_ALL_CON9 0x212
	129	+#define MT6331_BUCK_ALL_CON10 0x214
	130	+#define MT6331_BUCK_ALL_CON11 0x216
	131	+#define MT6331_BUCK_ALL_CON12 0x218
	132	+#define MT6331_BUCK_ALL_CON13 0x21A
	133	+#define MT6331_BUCK_ALL_CON14 0x21C
	134	+#define MT6331_BUCK_ALL_CON15 0x21E
	135	+#define MT6331_BUCK_ALL_CON16 0x220
	136	+#define MT6331_BUCK_ALL_CON17 0x222
	137	+#define MT6331_BUCK_ALL_CON18 0x224
	138	+#define MT6331_BUCK_ALL_CON19 0x226
	139	+#define MT6331_BUCK_ALL_CON20 0x228
	140	+#define MT6331_BUCK_ALL_CON21 0x22A
	141	+#define MT6331_BUCK_ALL_CON22 0x22C
	142	+#define MT6331_BUCK_ALL_CON23 0x22E
	143	+#define MT6331_BUCK_ALL_CON24 0x230
	144	+#define MT6331_BUCK_ALL_CON25 0x232
	145	+#define MT6331_BUCK_ALL_CON26 0x234
	146	+#define MT6331_VDVFS11_CON0 0x236
	147	+#define MT6331_VDVFS11_CON1 0x238
	148	+#define MT6331_VDVFS11_CON2 0x23A
	149	+#define MT6331_VDVFS11_CON3 0x23C
	150	+#define MT6331_VDVFS11_CON4 0x23E
	151	+#define MT6331_VDVFS11_CON5 0x240
	152	+#define MT6331_VDVFS11_CON6 0x242
	153	+#define MT6331_VDVFS11_CON7 0x244
	154	+#define MT6331_VDVFS11_CON8 0x246
	155	+#define MT6331_VDVFS11_CON9 0x248
	156	+#define MT6331_VDVFS11_CON10 0x24A
	157	+#define MT6331_VDVFS11_CON11 0x24C
	158	+#define MT6331_VDVFS11_CON12 0x24E
	159	+#define MT6331_VDVFS11_CON13 0x250
	160	+#define MT6331_VDVFS11_CON14 0x252
	161	+#define MT6331_VDVFS11_CON18 0x25A
	162	+#define MT6331_VDVFS11_CON19 0x25C
	163	+#define MT6331_VDVFS11_CON20 0x25E
	164	+#define MT6331_VDVFS11_CON21 0x260
	165	+#define MT6331_VDVFS11_CON22 0x262
	166	+#define MT6331_VDVFS11_CON23 0x264
	167	+#define MT6331_VDVFS11_CON24 0x266
	168	+#define MT6331_VDVFS11_CON25 0x268
	169	+#define MT6331_VDVFS11_CON26 0x26A
	170	+#define MT6331_VDVFS11_CON27 0x26C
	171	+#define MT6331_VDVFS12_CON0 0x26E
	172	+#define MT6331_VDVFS12_CON1 0x270
	173	+#define MT6331_VDVFS12_CON2 0x272
	174	+#define MT6331_VDVFS12_CON3 0x274
	175	+#define MT6331_VDVFS12_CON4 0x276
	176	+#define MT6331_VDVFS12_CON5 0x278
	177	+#define MT6331_VDVFS12_CON6 0x27A
	178	+#define MT6331_VDVFS12_CON7 0x27C
	179	+#define MT6331_VDVFS12_CON8 0x27E
	180	+#define MT6331_VDVFS12_CON9 0x280
	181	+#define MT6331_VDVFS12_CON10 0x282
	182	+#define MT6331_VDVFS12_CON11 0x284
	183	+#define MT6331_VDVFS12_CON12 0x286
	184	+#define MT6331_VDVFS12_CON13 0x288
	185	+#define MT6331_VDVFS12_CON14 0x28A
	186	+#define MT6331_VDVFS12_CON18 0x292
	187	+#define MT6331_VDVFS12_CON19 0x294
	188	+#define MT6331_VDVFS12_CON20 0x296
	189	+#define MT6331_VDVFS13_CON0 0x298
	190	+#define MT6331_VDVFS13_CON1 0x29A
	191	+#define MT6331_VDVFS13_CON2 0x29C
	192	+#define MT6331_VDVFS13_CON3 0x29E
	193	+#define MT6331_VDVFS13_CON4 0x2A0
	194	+#define MT6331_VDVFS13_CON5 0x2A2
	195	+#define MT6331_VDVFS13_CON6 0x2A4
	196	+#define MT6331_VDVFS13_CON7 0x2A6
	197	+#define MT6331_VDVFS13_CON8 0x2A8
	198	+#define MT6331_VDVFS13_CON9 0x2AA
	199	+#define MT6331_VDVFS13_CON10 0x2AC
	200	+#define MT6331_VDVFS13_CON11 0x2AE
	201	+#define MT6331_VDVFS13_CON12 0x2B0
	202	+#define MT6331_VDVFS13_CON13 0x2B2
	203	+#define MT6331_VDVFS13_CON14 0x2B4
	204	+#define MT6331_VDVFS13_CON18 0x2BC
	205	+#define MT6331_VDVFS13_CON19 0x2BE
	206	+#define MT6331_VDVFS13_CON20 0x2C0
	207	+#define MT6331_VDVFS14_CON0 0x2C2
	208	+#define MT6331_VDVFS14_CON1 0x2C4
	209	+#define MT6331_VDVFS14_CON2 0x2C6
	210	+#define MT6331_VDVFS14_CON3 0x2C8
	211	+#define MT6331_VDVFS14_CON4 0x2CA
	212	+#define MT6331_VDVFS14_CON5 0x2CC
	213	+#define MT6331_VDVFS14_CON6 0x2CE
	214	+#define MT6331_VDVFS14_CON7 0x2D0
	215	+#define MT6331_VDVFS14_CON8 0x2D2
	216	+#define MT6331_VDVFS14_CON9 0x2D4
	217	+#define MT6331_VDVFS14_CON10 0x2D6
	218	+#define MT6331_VDVFS14_CON11 0x2D8
	219	+#define MT6331_VDVFS14_CON12 0x2DA
	220	+#define MT6331_VDVFS14_CON13 0x2DC
	221	+#define MT6331_VDVFS14_CON14 0x2DE
	222	+#define MT6331_VDVFS14_CON18 0x2E6
	223	+#define MT6331_VDVFS14_CON19 0x2E8
	224	+#define MT6331_VDVFS14_CON20 0x2EA
	225	+#define MT6331_VGPU_CON0 0x300
	226	+#define MT6331_VGPU_CON1 0x302
	227	+#define MT6331_VGPU_CON2 0x304
	228	+#define MT6331_VGPU_CON3 0x306
	229	+#define MT6331_VGPU_CON4 0x308
	230	+#define MT6331_VGPU_CON5 0x30A
	231	+#define MT6331_VGPU_CON6 0x30C
	232	+#define MT6331_VGPU_CON7 0x30E
	233	+#define MT6331_VGPU_CON8 0x310
	234	+#define MT6331_VGPU_CON9 0x312
	235	+#define MT6331_VGPU_CON10 0x314
	236	+#define MT6331_VGPU_CON11 0x316
	237	+#define MT6331_VGPU_CON12 0x318
	238	+#define MT6331_VGPU_CON13 0x31A
	239	+#define MT6331_VGPU_CON14 0x31C
	240	+#define MT6331_VGPU_CON15 0x31E
	241	+#define MT6331_VGPU_CON16 0x320
	242	+#define MT6331_VGPU_CON17 0x322
	243	+#define MT6331_VGPU_CON18 0x324
	244	+#define MT6331_VGPU_CON19 0x326
	245	+#define MT6331_VGPU_CON20 0x328
	246	+#define MT6331_VCORE1_CON0 0x32A
	247	+#define MT6331_VCORE1_CON1 0x32C
	248	+#define MT6331_VCORE1_CON2 0x32E
	249	+#define MT6331_VCORE1_CON3 0x330
	250	+#define MT6331_VCORE1_CON4 0x332
	251	+#define MT6331_VCORE1_CON5 0x334
	252	+#define MT6331_VCORE1_CON6 0x336
	253	+#define MT6331_VCORE1_CON7 0x338
	254	+#define MT6331_VCORE1_CON8 0x33A
	255	+#define MT6331_VCORE1_CON9 0x33C
	256	+#define MT6331_VCORE1_CON10 0x33E
	257	+#define MT6331_VCORE1_CON11 0x340
	258	+#define MT6331_VCORE1_CON12 0x342
	259	+#define MT6331_VCORE1_CON13 0x344
	260	+#define MT6331_VCORE1_CON14 0x346
	261	+#define MT6331_VCORE1_CON15 0x348
	262	+#define MT6331_VCORE1_CON16 0x34A
	263	+#define MT6331_VCORE1_CON17 0x34C
	264	+#define MT6331_VCORE1_CON18 0x34E
	265	+#define MT6331_VCORE1_CON19 0x350
	266	+#define MT6331_VCORE1_CON20 0x352
	267	+#define MT6331_VCORE2_CON0 0x354
	268	+#define MT6331_VCORE2_CON1 0x356
	269	+#define MT6331_VCORE2_CON2 0x358
	270	+#define MT6331_VCORE2_CON3 0x35A
	271	+#define MT6331_VCORE2_CON4 0x35C
	272	+#define MT6331_VCORE2_CON5 0x35E
	273	+#define MT6331_VCORE2_CON6 0x360
	274	+#define MT6331_VCORE2_CON7 0x362
	275	+#define MT6331_VCORE2_CON8 0x364
	276	+#define MT6331_VCORE2_CON9 0x366
	277	+#define MT6331_VCORE2_CON10 0x368
	278	+#define MT6331_VCORE2_CON11 0x36A
	279	+#define MT6331_VCORE2_CON12 0x36C
	280	+#define MT6331_VCORE2_CON13 0x36E
	281	+#define MT6331_VCORE2_CON14 0x370
	282	+#define MT6331_VCORE2_CON15 0x372
	283	+#define MT6331_VCORE2_CON16 0x374
	284	+#define MT6331_VCORE2_CON17 0x376
	285	+#define MT6331_VCORE2_CON18 0x378
	286	+#define MT6331_VCORE2_CON19 0x37A
	287	+#define MT6331_VCORE2_CON20 0x37C
	288	+#define MT6331_VCORE2_CON21 0x37E
	289	+#define MT6331_VIO18_CON0 0x380
	290	+#define MT6331_VIO18_CON1 0x382
	291	+#define MT6331_VIO18_CON2 0x384
	292	+#define MT6331_VIO18_CON3 0x386
	293	+#define MT6331_VIO18_CON4 0x388
	294	+#define MT6331_VIO18_CON5 0x38A
	295	+#define MT6331_VIO18_CON6 0x38C
	296	+#define MT6331_VIO18_CON7 0x38E
	297	+#define MT6331_VIO18_CON8 0x390
	298	+#define MT6331_VIO18_CON9 0x392
	299	+#define MT6331_VIO18_CON10 0x394
	300	+#define MT6331_VIO18_CON11 0x396
	301	+#define MT6331_VIO18_CON12 0x398
	302	+#define MT6331_VIO18_CON13 0x39A
	303	+#define MT6331_VIO18_CON14 0x39C
	304	+#define MT6331_VIO18_CON15 0x39E
	305	+#define MT6331_VIO18_CON16 0x3A0
	306	+#define MT6331_VIO18_CON17 0x3A2
	307	+#define MT6331_VIO18_CON18 0x3A4
	308	+#define MT6331_VIO18_CON19 0x3A6
	309	+#define MT6331_VIO18_CON20 0x3A8
	310	+#define MT6331_BUCK_K_CON0 0x3AA
	311	+#define MT6331_BUCK_K_CON1 0x3AC
	312	+#define MT6331_BUCK_K_CON2 0x3AE
	313	+#define MT6331_BUCK_K_CON3 0x3B0
	314	+#define MT6331_ZCD_CON0 0x400
	315	+#define MT6331_ZCD_CON1 0x402
	316	+#define MT6331_ZCD_CON2 0x404
	317	+#define MT6331_ZCD_CON3 0x406
	318	+#define MT6331_ZCD_CON4 0x408
	319	+#define MT6331_ZCD_CON5 0x40A
	320	+#define MT6331_ISINK0_CON0 0x40C
	321	+#define MT6331_ISINK0_CON1 0x40E
	322	+#define MT6331_ISINK0_CON2 0x410
	323	+#define MT6331_ISINK0_CON3 0x412
	324	+#define MT6331_ISINK0_CON4 0x414
	325	+#define MT6331_ISINK1_CON0 0x416
	326	+#define MT6331_ISINK1_CON1 0x418
	327	+#define MT6331_ISINK1_CON2 0x41A
	328	+#define MT6331_ISINK1_CON3 0x41C
	329	+#define MT6331_ISINK1_CON4 0x41E
	330	+#define MT6331_ISINK2_CON0 0x420
	331	+#define MT6331_ISINK2_CON1 0x422
	332	+#define MT6331_ISINK2_CON2 0x424
	333	+#define MT6331_ISINK2_CON3 0x426
	334	+#define MT6331_ISINK2_CON4 0x428
	335	+#define MT6331_ISINK3_CON0 0x42A
	336	+#define MT6331_ISINK3_CON1 0x42C
	337	+#define MT6331_ISINK3_CON2 0x42E
	338	+#define MT6331_ISINK3_CON3 0x430
	339	+#define MT6331_ISINK3_CON4 0x432
	340	+#define MT6331_ISINK_ANA0 0x434
	341	+#define MT6331_ISINK_ANA1 0x436
	342	+#define MT6331_ISINK_PHASE_DLY 0x438
	343	+#define MT6331_ISINK_EN_CTRL 0x43A
	344	+#define MT6331_ANALDO_CON0 0x500
	345	+#define MT6331_ANALDO_CON1 0x502
	346	+#define MT6331_ANALDO_CON2 0x504
	347	+#define MT6331_ANALDO_CON3 0x506
	348	+#define MT6331_ANALDO_CON4 0x508
	349	+#define MT6331_ANALDO_CON5 0x50A
	350	+#define MT6331_ANALDO_CON6 0x50C
	351	+#define MT6331_ANALDO_CON7 0x50E
	352	+#define MT6331_ANALDO_CON8 0x510
	353	+#define MT6331_ANALDO_CON9 0x512
	354	+#define MT6331_ANALDO_CON10 0x514
	355	+#define MT6331_ANALDO_CON11 0x516
	356	+#define MT6331_ANALDO_CON12 0x518
	357	+#define MT6331_ANALDO_CON13 0x51A
	358	+#define MT6331_SYSLDO_CON0 0x51C
	359	+#define MT6331_SYSLDO_CON1 0x51E
	360	+#define MT6331_SYSLDO_CON2 0x520
	361	+#define MT6331_SYSLDO_CON3 0x522
	362	+#define MT6331_SYSLDO_CON4 0x524
	363	+#define MT6331_SYSLDO_CON5 0x526
	364	+#define MT6331_SYSLDO_CON6 0x528
	365	+#define MT6331_SYSLDO_CON7 0x52A
	366	+#define MT6331_SYSLDO_CON8 0x52C
	367	+#define MT6331_SYSLDO_CON9 0x52E
	368	+#define MT6331_SYSLDO_CON10 0x530
	369	+#define MT6331_SYSLDO_CON11 0x532
	370	+#define MT6331_SYSLDO_CON12 0x534
	371	+#define MT6331_SYSLDO_CON13 0x536
	372	+#define MT6331_SYSLDO_CON14 0x538
	373	+#define MT6331_SYSLDO_CON15 0x53A
	374	+#define MT6331_SYSLDO_CON16 0x53C
	375	+#define MT6331_SYSLDO_CON17 0x53E
	376	+#define MT6331_SYSLDO_CON18 0x540
	377	+#define MT6331_SYSLDO_CON19 0x542
	378	+#define MT6331_SYSLDO_CON20 0x544
	379	+#define MT6331_SYSLDO_CON21 0x546
	380	+#define MT6331_DIGLDO_CON0 0x548
	381	+#define MT6331_DIGLDO_CON1 0x54A
	382	+#define MT6331_DIGLDO_CON2 0x54C
	383	+#define MT6331_DIGLDO_CON3 0x54E
	384	+#define MT6331_DIGLDO_CON4 0x550
	385	+#define MT6331_DIGLDO_CON5 0x552
	386	+#define MT6331_DIGLDO_CON6 0x554
	387	+#define MT6331_DIGLDO_CON7 0x556
	388	+#define MT6331_DIGLDO_CON8 0x558
	389	+#define MT6331_DIGLDO_CON9 0x55A
	390	+#define MT6331_DIGLDO_CON10 0x55C
	391	+#define MT6331_DIGLDO_CON11 0x55E
	392	+#define MT6331_DIGLDO_CON12 0x560
	393	+#define MT6331_DIGLDO_CON13 0x562
	394	+#define MT6331_DIGLDO_CON14 0x564
	395	+#define MT6331_DIGLDO_CON15 0x566
	396	+#define MT6331_DIGLDO_CON16 0x568
	397	+#define MT6331_DIGLDO_CON17 0x56A
	398	+#define MT6331_DIGLDO_CON18 0x56C
	399	+#define MT6331_DIGLDO_CON19 0x56E
	400	+#define MT6331_DIGLDO_CON20 0x570
	401	+#define MT6331_DIGLDO_CON21 0x572
	402	+#define MT6331_DIGLDO_CON22 0x574
	403	+#define MT6331_DIGLDO_CON23 0x576
	404	+#define MT6331_DIGLDO_CON24 0x578
	405	+#define MT6331_DIGLDO_CON25 0x57A
	406	+#define MT6331_DIGLDO_CON26 0x57C
	407	+#define MT6331_DIGLDO_CON27 0x57E
	408	+#define MT6331_DIGLDO_CON28 0x580
	409	+#define MT6331_OTP_CON0 0x600
	410	+#define MT6331_OTP_CON1 0x602
	411	+#define MT6331_OTP_CON2 0x604
	412	+#define MT6331_OTP_CON3 0x606
	413	+#define MT6331_OTP_CON4 0x608
	414	+#define MT6331_OTP_CON5 0x60A
	415	+#define MT6331_OTP_CON6 0x60C
	416	+#define MT6331_OTP_CON7 0x60E
	417	+#define MT6331_OTP_CON8 0x610
	418	+#define MT6331_OTP_CON9 0x612
	419	+#define MT6331_OTP_CON10 0x614
	420	+#define MT6331_OTP_CON11 0x616
	421	+#define MT6331_OTP_CON12 0x618
	422	+#define MT6331_OTP_CON13 0x61A
	423	+#define MT6331_OTP_CON14 0x61C
	424	+#define MT6331_OTP_DOUT_0_15 0x61E
	425	+#define MT6331_OTP_DOUT_16_31 0x620
	426	+#define MT6331_OTP_DOUT_32_47 0x622
	427	+#define MT6331_OTP_DOUT_48_63 0x624
	428	+#define MT6331_OTP_DOUT_64_79 0x626
	429	+#define MT6331_OTP_DOUT_80_95 0x628
	430	+#define MT6331_OTP_DOUT_96_111 0x62A
	431	+#define MT6331_OTP_DOUT_112_127 0x62C
	432	+#define MT6331_OTP_DOUT_128_143 0x62E
	433	+#define MT6331_OTP_DOUT_144_159 0x630
	434	+#define MT6331_OTP_DOUT_160_175 0x632
	435	+#define MT6331_OTP_DOUT_176_191 0x634
	436	+#define MT6331_OTP_DOUT_192_207 0x636
	437	+#define MT6331_OTP_DOUT_208_223 0x638
	438	+#define MT6331_OTP_DOUT_224_239 0x63A
	439	+#define MT6331_OTP_DOUT_240_255 0x63C
	440	+#define MT6331_OTP_VAL_0_15 0x63E
	441	+#define MT6331_OTP_VAL_16_31 0x640
	442	+#define MT6331_OTP_VAL_32_47 0x642
	443	+#define MT6331_OTP_VAL_48_63 0x644
	444	+#define MT6331_OTP_VAL_64_79 0x646
	445	+#define MT6331_OTP_VAL_80_95 0x648
	446	+#define MT6331_OTP_VAL_96_111 0x64A
	447	+#define MT6331_OTP_VAL_112_127 0x64C
	448	+#define MT6331_OTP_VAL_128_143 0x64E
	449	+#define MT6331_OTP_VAL_144_159 0x650
	450	+#define MT6331_OTP_VAL_160_175 0x652
	451	+#define MT6331_OTP_VAL_176_191 0x654
	452	+#define MT6331_OTP_VAL_192_207 0x656
	453	+#define MT6331_OTP_VAL_208_223 0x658
	454	+#define MT6331_OTP_VAL_224_239 0x65A
	455	+#define MT6331_OTP_VAL_240_255 0x65C
	456	+#define MT6331_RTC_MIX_CON0 0x65E
	457	+#define MT6331_RTC_MIX_CON1 0x660
	458	+#define MT6331_AUDDAC_CFG0 0x662
	459	+#define MT6331_AUDBUF_CFG0 0x664
	460	+#define MT6331_AUDBUF_CFG1 0x666
	461	+#define MT6331_AUDBUF_CFG2 0x668
	462	+#define MT6331_AUDBUF_CFG3 0x66A
	463	+#define MT6331_AUDBUF_CFG4 0x66C
	464	+#define MT6331_AUDBUF_CFG5 0x66E
	465	+#define MT6331_AUDBUF_CFG6 0x670
	466	+#define MT6331_AUDBUF_CFG7 0x672
	467	+#define MT6331_AUDBUF_CFG8 0x674
	468	+#define MT6331_IBIASDIST_CFG0 0x676
	469	+#define MT6331_AUDCLKGEN_CFG0 0x678
	470	+#define MT6331_AUDLDO_CFG0 0x67A
	471	+#define MT6331_AUDDCDC_CFG0 0x67C
	472	+#define MT6331_AUDDCDC_CFG1 0x67E
	473	+#define MT6331_AUDNVREGGLB_CFG0 0x680
	474	+#define MT6331_AUD_NCP0 0x682
	475	+#define MT6331_AUD_ZCD_CFG0 0x684
	476	+#define MT6331_AUDPREAMP_CFG0 0x686
	477	+#define MT6331_AUDPREAMP_CFG1 0x688
	478	+#define MT6331_AUDPREAMP_CFG2 0x68A
	479	+#define MT6331_AUDADC_CFG0 0x68C
	480	+#define MT6331_AUDADC_CFG1 0x68E
	481	+#define MT6331_AUDADC_CFG2 0x690
	482	+#define MT6331_AUDADC_CFG3 0x692
	483	+#define MT6331_AUDADC_CFG4 0x694
	484	+#define MT6331_AUDADC_CFG5 0x696
	485	+#define MT6331_AUDDIGMI_CFG0 0x698
	486	+#define MT6331_AUDDIGMI_CFG1 0x69A
	487	+#define MT6331_AUDMICBIAS_CFG0 0x69C
	488	+#define MT6331_AUDMICBIAS_CFG1 0x69E
	489	+#define MT6331_AUDENCSPARE_CFG0 0x6A0
	490	+#define MT6331_AUDPREAMPGAIN_CFG0 0x6A2
	491	+#define MT6331_AUDMADPLL_CFG0 0x6A4
	492	+#define MT6331_AUDMADPLL_CFG1 0x6A6
	493	+#define MT6331_AUDMADPLL_CFG2 0x6A8
	494	+#define MT6331_AUDLDO_NVREG_CFG0 0x6AA
	495	+#define MT6331_AUDLDO_NVREG_CFG1 0x6AC
	496	+#define MT6331_AUDLDO_NVREG_CFG2 0x6AE
	497	+#define MT6331_AUXADC_ADC0 0x700
	498	+#define MT6331_AUXADC_ADC1 0x702
	499	+#define MT6331_AUXADC_ADC2 0x704
	500	+#define MT6331_AUXADC_ADC3 0x706
	501	+#define MT6331_AUXADC_ADC4 0x708
	502	+#define MT6331_AUXADC_ADC5 0x70A
	503	+#define MT6331_AUXADC_ADC6 0x70C
	504	+#define MT6331_AUXADC_ADC7 0x70E
	505	+#define MT6331_AUXADC_ADC8 0x710
	506	+#define MT6331_AUXADC_ADC9 0x712
	507	+#define MT6331_AUXADC_ADC10 0x714
	508	+#define MT6331_AUXADC_ADC11 0x716
	509	+#define MT6331_AUXADC_ADC12 0x718
	510	+#define MT6331_AUXADC_ADC13 0x71A
	511	+#define MT6331_AUXADC_ADC14 0x71C
	512	+#define MT6331_AUXADC_ADC15 0x71E
	513	+#define MT6331_AUXADC_ADC16 0x720
	514	+#define MT6331_AUXADC_ADC17 0x722
	515	+#define MT6331_AUXADC_ADC18 0x724
	516	+#define MT6331_AUXADC_ADC19 0x726
	517	+#define MT6331_AUXADC_STA0 0x728
	518	+#define MT6331_AUXADC_STA1 0x72A
	519	+#define MT6331_AUXADC_RQST0 0x72C
	520	+#define MT6331_AUXADC_RQST0_SET 0x72E
	521	+#define MT6331_AUXADC_RQST0_CLR 0x730
	522	+#define MT6331_AUXADC_RQST1 0x732
	523	+#define MT6331_AUXADC_RQST1_SET 0x734
	524	+#define MT6331_AUXADC_RQST1_CLR 0x736
	525	+#define MT6331_AUXADC_CON0 0x738
	526	+#define MT6331_AUXADC_CON1 0x73A
	527	+#define MT6331_AUXADC_CON2 0x73C
	528	+#define MT6331_AUXADC_CON3 0x73E
	529	+#define MT6331_AUXADC_CON4 0x740
	530	+#define MT6331_AUXADC_CON5 0x742
	531	+#define MT6331_AUXADC_CON6 0x744
	532	+#define MT6331_AUXADC_CON7 0x746
	533	+#define MT6331_AUXADC_CON8 0x748
	534	+#define MT6331_AUXADC_CON9 0x74A
	535	+#define MT6331_AUXADC_CON10 0x74C
	536	+#define MT6331_AUXADC_CON11 0x74E
	537	+#define MT6331_AUXADC_CON12 0x750
	538	+#define MT6331_AUXADC_CON13 0x752
	539	+#define MT6331_AUXADC_CON14 0x754
	540	+#define MT6331_AUXADC_CON15 0x756
	541	+#define MT6331_AUXADC_CON16 0x758
	542	+#define MT6331_AUXADC_CON17 0x75A
	543	+#define MT6331_AUXADC_CON18 0x75C
	544	+#define MT6331_AUXADC_CON19 0x75E
	545	+#define MT6331_AUXADC_CON20 0x760
	546	+#define MT6331_AUXADC_CON21 0x762
	547	+#define MT6331_AUXADC_CON22 0x764
	548	+#define MT6331_AUXADC_CON23 0x766
	549	+#define MT6331_AUXADC_CON24 0x768
	550	+#define MT6331_AUXADC_CON25 0x76A
	551	+#define MT6331_AUXADC_CON26 0x76C
	552	+#define MT6331_AUXADC_CON27 0x76E
	553	+#define MT6331_AUXADC_CON28 0x770
	554	+#define MT6331_AUXADC_CON29 0x772
	555	+#define MT6331_AUXADC_CON30 0x774
	556	+#define MT6331_AUXADC_CON31 0x776
	557	+#define MT6331_AUXADC_CON32 0x778
	558	+#define MT6331_ACCDET_CON0 0x77A
	559	+#define MT6331_ACCDET_CON1 0x77C
	560	+#define MT6331_ACCDET_CON2 0x77E
	561	+#define MT6331_ACCDET_CON3 0x780
	562	+#define MT6331_ACCDET_CON4 0x782
	563	+#define MT6331_ACCDET_CON5 0x784
	564	+#define MT6331_ACCDET_CON6 0x786
	565	+#define MT6331_ACCDET_CON7 0x788
	566	+#define MT6331_ACCDET_CON8 0x78A
	567	+#define MT6331_ACCDET_CON9 0x78C
	568	+#define MT6331_ACCDET_CON10 0x78E
	569	+#define MT6331_ACCDET_CON11 0x790
	570	+#define MT6331_ACCDET_CON12 0x792
	571	+#define MT6331_ACCDET_CON13 0x794
	572	+#define MT6331_ACCDET_CON14 0x796
	573	+#define MT6331_ACCDET_CON15 0x798
	574	+#define MT6331_ACCDET_CON16 0x79A
	575	+#define MT6331_ACCDET_CON17 0x79C
	576	+#define MT6331_ACCDET_CON18 0x79E
	577	+#define MT6331_ACCDET_CON19 0x7A0
	578	+#define MT6331_ACCDET_CON20 0x7A2
	579	+#define MT6331_ACCDET_CON21 0x7A4
	580	+#define MT6331_ACCDET_CON22 0x7A6
	581	+#define MT6331_ACCDET_CON23 0x7A8
	582	+#define MT6331_ACCDET_CON24 0x7AA
	583	+
	584	+#endif /* __MFD_MT6331_REGISTERS_H__ */

include/linux/mfd/mt6332/core.h+65−0

@@ -0,0 +1,65 @@
	1	+/* SPDX-License-Identifier: GPL-2.0-only */
	2	+/*
	3	+ * Copyright (c) 2022 AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
	4	+ */
	5	+
	6	+#ifndef __MFD_MT6332_CORE_H__
	7	+#define __MFD_MT6332_CORE_H__
	8	+
	9	+enum mt6332_irq_status_numbers {
	10	+ MT6332_IRQ_STATUS_CHR_COMPLETE = 0,
	11	+ MT6332_IRQ_STATUS_THERMAL_SD,
	12	+ MT6332_IRQ_STATUS_THERMAL_REG_IN,
	13	+ MT6332_IRQ_STATUS_THERMAL_REG_OUT,
	14	+ MT6332_IRQ_STATUS_OTG_OC,
	15	+ MT6332_IRQ_STATUS_CHR_OC,
	16	+ MT6332_IRQ_STATUS_OTG_THERMAL,
	17	+ MT6332_IRQ_STATUS_CHRIN_SHORT,
	18	+ MT6332_IRQ_STATUS_DRVCDT_SHORT,
	19	+ MT6332_IRQ_STATUS_PLUG_IN_FLASH,
	20	+ MT6332_IRQ_STATUS_CHRWDT_FLAG,
	21	+ MT6332_IRQ_STATUS_FLASH_EN_TIMEOUT,
	22	+ MT6332_IRQ_STATUS_FLASH_VLED1_SHORT,
	23	+ MT6332_IRQ_STATUS_FLASH_VLED1_OPEN = 13,
	24	+ MT6332_IRQ_STATUS_OV = 16,
	25	+ MT6332_IRQ_STATUS_BVALID_DET,
	26	+ MT6332_IRQ_STATUS_VBATON_UNDET,
	27	+ MT6332_IRQ_STATUS_CHR_PLUG_IN,
	28	+ MT6332_IRQ_STATUS_CHR_PLUG_OUT,
	29	+ MT6332_IRQ_STATUS_BC11_TIMEOUT,
	30	+ MT6332_IRQ_STATUS_FLASH_VLED2_SHORT,
	31	+ MT6332_IRQ_STATUS_FLASH_VLED2_OPEN = 23,
	32	+ MT6332_IRQ_STATUS_THR_H = 32,
	33	+ MT6332_IRQ_STATUS_THR_L,
	34	+ MT6332_IRQ_STATUS_BAT_H,
	35	+ MT6332_IRQ_STATUS_BAT_L,
	36	+ MT6332_IRQ_STATUS_M3_H,
	37	+ MT6332_IRQ_STATUS_M3_L,
	38	+ MT6332_IRQ_STATUS_FG_BAT_H,
	39	+ MT6332_IRQ_STATUS_FG_BAT_L,
	40	+ MT6332_IRQ_STATUS_FG_CUR_H,
	41	+ MT6332_IRQ_STATUS_FG_CUR_L,
	42	+ MT6332_IRQ_STATUS_SPKL_D,
	43	+ MT6332_IRQ_STATUS_SPKL_AB,
	44	+ MT6332_IRQ_STATUS_BIF,
	45	+ MT6332_IRQ_STATUS_VWLED_OC = 45,
	46	+ MT6332_IRQ_STATUS_VDRAM_OC = 48,
	47	+ MT6332_IRQ_STATUS_VDVFS2_OC,
	48	+ MT6332_IRQ_STATUS_VRF1_OC,
	49	+ MT6332_IRQ_STATUS_VRF2_OC,
	50	+ MT6332_IRQ_STATUS_VPA_OC,
	51	+ MT6332_IRQ_STATUS_VSBST_OC,
	52	+ MT6332_IRQ_STATUS_LDO_OC,
	53	+ MT6332_IRQ_STATUS_NR,
	54	+};
	55	+
	56	+#define MT6332_IRQ_CON0_BASE MT6332_IRQ_STATUS_CHR_COMPLETE
	57	+#define MT6332_IRQ_CON0_BITS (MT6332_IRQ_STATUS_FLASH_VLED1_OPEN + 1)
	58	+#define MT6332_IRQ_CON1_BASE MT6332_IRQ_STATUS_OV
	59	+#define MT6332_IRQ_CON1_BITS (MT6332_IRQ_STATUS_FLASH_VLED2_OPEN - MT6332_IRQ_STATUS_OV + 1)
	60	+#define MT6332_IRQ_CON2_BASE MT6332_IRQ_STATUS_THR_H
	61	+#define MT6332_IRQ_CON2_BITS (MT6332_IRQ_STATUS_VWLED_OC - MT6332_IRQ_STATUS_THR_H + 1)
	62	+#define MT6332_IRQ_CON3_BASE MT6332_IRQ_STATUS_VDRAM_OC
	63	+#define MT6332_IRQ_CON3_BITS (MT6332_IRQ_STATUS_LDO_OC - MT6332_IRQ_STATUS_VDRAM_OC + 1)
	64	+
	65	+#endif /* __MFD_MT6332_CORE_H__ */

include/linux/mfd/mt6332/registers.h+642−0

@@ -0,0 +1,642 @@
	1	+/* SPDX-License-Identifier: GPL-2.0-only */
	2	+/*
	3	+ * Copyright (c) 2022 AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
	4	+ */
	5	+
	6	+#ifndef __MFD_MT6332_REGISTERS_H__
	7	+#define __MFD_MT6332_REGISTERS_H__
	8	+
	9	+/* PMIC Registers */
	10	+#define MT6332_HWCID 0x8000
	11	+#define MT6332_SWCID 0x8002
	12	+#define MT6332_TOP_CON 0x8004
	13	+#define MT6332_DDR_VREF_AP_CON 0x8006
	14	+#define MT6332_DDR_VREF_DQ_CON 0x8008
	15	+#define MT6332_DDR_VREF_CA_CON 0x800A
	16	+#define MT6332_TEST_OUT 0x800C
	17	+#define MT6332_TEST_CON0 0x800E
	18	+#define MT6332_TEST_CON1 0x8010
	19	+#define MT6332_TESTMODE_SW 0x8012
	20	+#define MT6332_TESTMODE_ANA 0x8014
	21	+#define MT6332_TDSEL_CON 0x8016
	22	+#define MT6332_RDSEL_CON 0x8018
	23	+#define MT6332_SMT_CON0 0x801A
	24	+#define MT6332_SMT_CON1 0x801C
	25	+#define MT6332_DRV_CON0 0x801E
	26	+#define MT6332_DRV_CON1 0x8020
	27	+#define MT6332_DRV_CON2 0x8022
	28	+#define MT6332_EN_STATUS0 0x8024
	29	+#define MT6332_OCSTATUS0 0x8026
	30	+#define MT6332_TOP_STATUS 0x8028
	31	+#define MT6332_TOP_STATUS_SET 0x802A
	32	+#define MT6332_TOP_STATUS_CLR 0x802C
	33	+#define MT6332_FLASH_CON0 0x802E
	34	+#define MT6332_FLASH_CON1 0x8030
	35	+#define MT6332_FLASH_CON2 0x8032
	36	+#define MT6332_CORE_CON0 0x8034
	37	+#define MT6332_CORE_CON1 0x8036
	38	+#define MT6332_CORE_CON2 0x8038
	39	+#define MT6332_CORE_CON3 0x803A
	40	+#define MT6332_CORE_CON4 0x803C
	41	+#define MT6332_CORE_CON5 0x803E
	42	+#define MT6332_CORE_CON6 0x8040
	43	+#define MT6332_CORE_CON7 0x8042
	44	+#define MT6332_CORE_CON8 0x8044
	45	+#define MT6332_CORE_CON9 0x8046
	46	+#define MT6332_CORE_CON10 0x8048
	47	+#define MT6332_CORE_CON11 0x804A
	48	+#define MT6332_CORE_CON12 0x804C
	49	+#define MT6332_CORE_CON13 0x804E
	50	+#define MT6332_CORE_CON14 0x8050
	51	+#define MT6332_CORE_CON15 0x8052
	52	+#define MT6332_STA_CON0 0x8054
	53	+#define MT6332_STA_CON1 0x8056
	54	+#define MT6332_STA_CON2 0x8058
	55	+#define MT6332_STA_CON3 0x805A
	56	+#define MT6332_STA_CON4 0x805C
	57	+#define MT6332_STA_CON5 0x805E
	58	+#define MT6332_STA_CON6 0x8060
	59	+#define MT6332_STA_CON7 0x8062
	60	+#define MT6332_CHR_CON0 0x8064
	61	+#define MT6332_CHR_CON1 0x8066
	62	+#define MT6332_CHR_CON2 0x8068
	63	+#define MT6332_CHR_CON3 0x806A
	64	+#define MT6332_CHR_CON4 0x806C
	65	+#define MT6332_CHR_CON5 0x806E
	66	+#define MT6332_CHR_CON6 0x8070
	67	+#define MT6332_CHR_CON7 0x8072
	68	+#define MT6332_CHR_CON8 0x8074
	69	+#define MT6332_CHR_CON9 0x8076
	70	+#define MT6332_CHR_CON10 0x8078
	71	+#define MT6332_CHR_CON11 0x807A
	72	+#define MT6332_CHR_CON12 0x807C
	73	+#define MT6332_CHR_CON13 0x807E
	74	+#define MT6332_CHR_CON14 0x8080
	75	+#define MT6332_CHR_CON15 0x8082
	76	+#define MT6332_BOOST_CON0 0x8084
	77	+#define MT6332_BOOST_CON1 0x8086
	78	+#define MT6332_BOOST_CON2 0x8088
	79	+#define MT6332_BOOST_CON3 0x808A
	80	+#define MT6332_BOOST_CON4 0x808C
	81	+#define MT6332_BOOST_CON5 0x808E
	82	+#define MT6332_BOOST_CON6 0x8090
	83	+#define MT6332_BOOST_CON7 0x8092
	84	+#define MT6332_TOP_CKPDN_CON0 0x8094
	85	+#define MT6332_TOP_CKPDN_CON0_SET 0x8096
	86	+#define MT6332_TOP_CKPDN_CON0_CLR 0x8098
	87	+#define MT6332_TOP_CKPDN_CON1 0x809A
	88	+#define MT6332_TOP_CKPDN_CON1_SET 0x809C
	89	+#define MT6332_TOP_CKPDN_CON1_CLR 0x809E
	90	+#define MT6332_TOP_CKPDN_CON2 0x80A0
	91	+#define MT6332_TOP_CKPDN_CON2_SET 0x80A2
	92	+#define MT6332_TOP_CKPDN_CON2_CLR 0x80A4
	93	+#define MT6332_TOP_CKSEL_CON0 0x80A6
	94	+#define MT6332_TOP_CKSEL_CON0_SET 0x80A8
	95	+#define MT6332_TOP_CKSEL_CON0_CLR 0x80AA
	96	+#define MT6332_TOP_CKSEL_CON1 0x80AC
	97	+#define MT6332_TOP_CKSEL_CON1_SET 0x80AE
	98	+#define MT6332_TOP_CKSEL_CON1_CLR 0x80B0
	99	+#define MT6332_TOP_CKHWEN_CON 0x80B2
	100	+#define MT6332_TOP_CKHWEN_CON_SET 0x80B4
	101	+#define MT6332_TOP_CKHWEN_CON_CLR 0x80B6
	102	+#define MT6332_TOP_CKTST_CON0 0x80B8
	103	+#define MT6332_TOP_CKTST_CON1 0x80BA
	104	+#define MT6332_TOP_RST_CON 0x80BC
	105	+#define MT6332_TOP_RST_CON_SET 0x80BE
	106	+#define MT6332_TOP_RST_CON_CLR 0x80C0
	107	+#define MT6332_TOP_RST_MISC 0x80C2
	108	+#define MT6332_TOP_RST_MISC_SET 0x80C4
	109	+#define MT6332_TOP_RST_MISC_CLR 0x80C6
	110	+#define MT6332_INT_CON0 0x80C8
	111	+#define MT6332_INT_CON0_SET 0x80CA
	112	+#define MT6332_INT_CON0_CLR 0x80CC
	113	+#define MT6332_INT_CON1 0x80CE
	114	+#define MT6332_INT_CON1_SET 0x80D0
	115	+#define MT6332_INT_CON1_CLR 0x80D2
	116	+#define MT6332_INT_CON2 0x80D4
	117	+#define MT6332_INT_CON2_SET 0x80D6
	118	+#define MT6332_INT_CON2_CLR 0x80D8
	119	+#define MT6332_INT_CON3 0x80DA
	120	+#define MT6332_INT_CON3_SET 0x80DC
	121	+#define MT6332_INT_CON3_CLR 0x80DE
	122	+#define MT6332_CHRWDT_CON0 0x80E0
	123	+#define MT6332_CHRWDT_STATUS0 0x80E2
	124	+#define MT6332_INT_STATUS0 0x80E4
	125	+#define MT6332_INT_STATUS1 0x80E6
	126	+#define MT6332_INT_STATUS2 0x80E8
	127	+#define MT6332_INT_STATUS3 0x80EA
	128	+#define MT6332_OC_GEAR_0 0x80EC
	129	+#define MT6332_OC_GEAR_1 0x80EE
	130	+#define MT6332_OC_GEAR_2 0x80F0
	131	+#define MT6332_INT_MISC_CON 0x80F2
	132	+#define MT6332_RG_SPI_CON 0x80F4
	133	+#define MT6332_DEW_DIO_EN 0x80F6
	134	+#define MT6332_DEW_READ_TEST 0x80F8
	135	+#define MT6332_DEW_WRITE_TEST 0x80FA
	136	+#define MT6332_DEW_CRC_SWRST 0x80FC
	137	+#define MT6332_DEW_CRC_EN 0x80FE
	138	+#define MT6332_DEW_CRC_VAL 0x8100
	139	+#define MT6332_DEW_DBG_MON_SEL 0x8102
	140	+#define MT6332_DEW_CIPHER_KEY_SEL 0x8104
	141	+#define MT6332_DEW_CIPHER_IV_SEL 0x8106
	142	+#define MT6332_DEW_CIPHER_EN 0x8108
	143	+#define MT6332_DEW_CIPHER_RDY 0x810A
	144	+#define MT6332_DEW_CIPHER_MODE 0x810C
	145	+#define MT6332_DEW_CIPHER_SWRST 0x810E
	146	+#define MT6332_DEW_RDDMY_NO 0x8110
	147	+#define MT6332_INT_STA 0x8112
	148	+#define MT6332_BIF_CON0 0x8114
	149	+#define MT6332_BIF_CON1 0x8116
	150	+#define MT6332_BIF_CON2 0x8118
	151	+#define MT6332_BIF_CON3 0x811A
	152	+#define MT6332_BIF_CON4 0x811C
	153	+#define MT6332_BIF_CON5 0x811E
	154	+#define MT6332_BIF_CON6 0x8120
	155	+#define MT6332_BIF_CON7 0x8122
	156	+#define MT6332_BIF_CON8 0x8124
	157	+#define MT6332_BIF_CON9 0x8126
	158	+#define MT6332_BIF_CON10 0x8128
	159	+#define MT6332_BIF_CON11 0x812A
	160	+#define MT6332_BIF_CON12 0x812C
	161	+#define MT6332_BIF_CON13 0x812E
	162	+#define MT6332_BIF_CON14 0x8130
	163	+#define MT6332_BIF_CON15 0x8132
	164	+#define MT6332_BIF_CON16 0x8134
	165	+#define MT6332_BIF_CON17 0x8136
	166	+#define MT6332_BIF_CON18 0x8138
	167	+#define MT6332_BIF_CON19 0x813A
	168	+#define MT6332_BIF_CON20 0x813C
	169	+#define MT6332_BIF_CON21 0x813E
	170	+#define MT6332_BIF_CON22 0x8140
	171	+#define MT6332_BIF_CON23 0x8142
	172	+#define MT6332_BIF_CON24 0x8144
	173	+#define MT6332_BIF_CON25 0x8146
	174	+#define MT6332_BIF_CON26 0x8148
	175	+#define MT6332_BIF_CON27 0x814A
	176	+#define MT6332_BIF_CON28 0x814C
	177	+#define MT6332_BIF_CON29 0x814E
	178	+#define MT6332_BIF_CON30 0x8150
	179	+#define MT6332_BIF_CON31 0x8152
	180	+#define MT6332_BIF_CON32 0x8154
	181	+#define MT6332_BIF_CON33 0x8156
	182	+#define MT6332_BIF_CON34 0x8158
	183	+#define MT6332_BIF_CON35 0x815A
	184	+#define MT6332_BIF_CON36 0x815C
	185	+#define MT6332_BATON_CON0 0x815E
	186	+#define MT6332_BIF_CON37 0x8160
	187	+#define MT6332_BIF_CON38 0x8162
	188	+#define MT6332_CHR_CON16 0x8164
	189	+#define MT6332_CHR_CON17 0x8166
	190	+#define MT6332_CHR_CON18 0x8168
	191	+#define MT6332_CHR_CON19 0x816A
	192	+#define MT6332_CHR_CON20 0x816C
	193	+#define MT6332_CHR_CON21 0x816E
	194	+#define MT6332_CHR_CON22 0x8170
	195	+#define MT6332_CHR_CON23 0x8172
	196	+#define MT6332_CHR_CON24 0x8174
	197	+#define MT6332_CHR_CON25 0x8176
	198	+#define MT6332_STA_CON8 0x8178
	199	+#define MT6332_BUCK_ALL_CON0 0x8400
	200	+#define MT6332_BUCK_ALL_CON1 0x8402
	201	+#define MT6332_BUCK_ALL_CON2 0x8404
	202	+#define MT6332_BUCK_ALL_CON3 0x8406
	203	+#define MT6332_BUCK_ALL_CON4 0x8408
	204	+#define MT6332_BUCK_ALL_CON5 0x840A
	205	+#define MT6332_BUCK_ALL_CON6 0x840C
	206	+#define MT6332_BUCK_ALL_CON7 0x840E
	207	+#define MT6332_BUCK_ALL_CON8 0x8410
	208	+#define MT6332_BUCK_ALL_CON9 0x8412
	209	+#define MT6332_BUCK_ALL_CON10 0x8414
	210	+#define MT6332_BUCK_ALL_CON11 0x8416
	211	+#define MT6332_BUCK_ALL_CON12 0x8418
	212	+#define MT6332_BUCK_ALL_CON13 0x841A
	213	+#define MT6332_BUCK_ALL_CON14 0x841C
	214	+#define MT6332_BUCK_ALL_CON15 0x841E
	215	+#define MT6332_BUCK_ALL_CON16 0x8420
	216	+#define MT6332_BUCK_ALL_CON17 0x8422
	217	+#define MT6332_BUCK_ALL_CON18 0x8424
	218	+#define MT6332_BUCK_ALL_CON19 0x8426
	219	+#define MT6332_BUCK_ALL_CON20 0x8428
	220	+#define MT6332_BUCK_ALL_CON21 0x842A
	221	+#define MT6332_BUCK_ALL_CON22 0x842C
	222	+#define MT6332_BUCK_ALL_CON23 0x842E
	223	+#define MT6332_BUCK_ALL_CON24 0x8430
	224	+#define MT6332_BUCK_ALL_CON25 0x8432
	225	+#define MT6332_BUCK_ALL_CON26 0x8434
	226	+#define MT6332_BUCK_ALL_CON27 0x8436
	227	+#define MT6332_VDRAM_CON0 0x8438
	228	+#define MT6332_VDRAM_CON1 0x843A
	229	+#define MT6332_VDRAM_CON2 0x843C
	230	+#define MT6332_VDRAM_CON3 0x843E
	231	+#define MT6332_VDRAM_CON4 0x8440
	232	+#define MT6332_VDRAM_CON5 0x8442
	233	+#define MT6332_VDRAM_CON6 0x8444
	234	+#define MT6332_VDRAM_CON7 0x8446
	235	+#define MT6332_VDRAM_CON8 0x8448
	236	+#define MT6332_VDRAM_CON9 0x844A
	237	+#define MT6332_VDRAM_CON10 0x844C
	238	+#define MT6332_VDRAM_CON11 0x844E
	239	+#define MT6332_VDRAM_CON12 0x8450
	240	+#define MT6332_VDRAM_CON13 0x8452
	241	+#define MT6332_VDRAM_CON14 0x8454
	242	+#define MT6332_VDRAM_CON15 0x8456
	243	+#define MT6332_VDRAM_CON16 0x8458
	244	+#define MT6332_VDRAM_CON17 0x845A
	245	+#define MT6332_VDRAM_CON18 0x845C
	246	+#define MT6332_VDRAM_CON19 0x845E
	247	+#define MT6332_VDRAM_CON20 0x8460
	248	+#define MT6332_VDRAM_CON21 0x8462
	249	+#define MT6332_VDVFS2_CON0 0x8464
	250	+#define MT6332_VDVFS2_CON1 0x8466
	251	+#define MT6332_VDVFS2_CON2 0x8468
	252	+#define MT6332_VDVFS2_CON3 0x846A
	253	+#define MT6332_VDVFS2_CON4 0x846C
	254	+#define MT6332_VDVFS2_CON5 0x846E
	255	+#define MT6332_VDVFS2_CON6 0x8470
	256	+#define MT6332_VDVFS2_CON7 0x8472
	257	+#define MT6332_VDVFS2_CON8 0x8474
	258	+#define MT6332_VDVFS2_CON9 0x8476
	259	+#define MT6332_VDVFS2_CON10 0x8478
	260	+#define MT6332_VDVFS2_CON11 0x847A
	261	+#define MT6332_VDVFS2_CON12 0x847C
	262	+#define MT6332_VDVFS2_CON13 0x847E
	263	+#define MT6332_VDVFS2_CON14 0x8480
	264	+#define MT6332_VDVFS2_CON15 0x8482
	265	+#define MT6332_VDVFS2_CON16 0x8484
	266	+#define MT6332_VDVFS2_CON17 0x8486
	267	+#define MT6332_VDVFS2_CON18 0x8488
	268	+#define MT6332_VDVFS2_CON19 0x848A
	269	+#define MT6332_VDVFS2_CON20 0x848C
	270	+#define MT6332_VDVFS2_CON21 0x848E
	271	+#define MT6332_VDVFS2_CON22 0x8490
	272	+#define MT6332_VDVFS2_CON23 0x8492
	273	+#define MT6332_VDVFS2_CON24 0x8494
	274	+#define MT6332_VDVFS2_CON25 0x8496
	275	+#define MT6332_VDVFS2_CON26 0x8498
	276	+#define MT6332_VDVFS2_CON27 0x849A
	277	+#define MT6332_VRF1_CON0 0x849C
	278	+#define MT6332_VRF1_CON1 0x849E
	279	+#define MT6332_VRF1_CON2 0x84A0
	280	+#define MT6332_VRF1_CON3 0x84A2
	281	+#define MT6332_VRF1_CON4 0x84A4
	282	+#define MT6332_VRF1_CON5 0x84A6
	283	+#define MT6332_VRF1_CON6 0x84A8
	284	+#define MT6332_VRF1_CON7 0x84AA
	285	+#define MT6332_VRF1_CON8 0x84AC
	286	+#define MT6332_VRF1_CON9 0x84AE
	287	+#define MT6332_VRF1_CON10 0x84B0
	288	+#define MT6332_VRF1_CON11 0x84B2
	289	+#define MT6332_VRF1_CON12 0x84B4
	290	+#define MT6332_VRF1_CON13 0x84B6
	291	+#define MT6332_VRF1_CON14 0x84B8
	292	+#define MT6332_VRF1_CON15 0x84BA
	293	+#define MT6332_VRF1_CON16 0x84BC
	294	+#define MT6332_VRF1_CON17 0x84BE
	295	+#define MT6332_VRF1_CON18 0x84C0
	296	+#define MT6332_VRF1_CON19 0x84C2
	297	+#define MT6332_VRF1_CON20 0x84C4
	298	+#define MT6332_VRF1_CON21 0x84C6
	299	+#define MT6332_VRF2_CON0 0x84C8
	300	+#define MT6332_VRF2_CON1 0x84CA
	301	+#define MT6332_VRF2_CON2 0x84CC
	302	+#define MT6332_VRF2_CON3 0x84CE
	303	+#define MT6332_VRF2_CON4 0x84D0
	304	+#define MT6332_VRF2_CON5 0x84D2
	305	+#define MT6332_VRF2_CON6 0x84D4
	306	+#define MT6332_VRF2_CON7 0x84D6
	307	+#define MT6332_VRF2_CON8 0x84D8
	308	+#define MT6332_VRF2_CON9 0x84DA
	309	+#define MT6332_VRF2_CON10 0x84DC
	310	+#define MT6332_VRF2_CON11 0x84DE
	311	+#define MT6332_VRF2_CON12 0x84E0
	312	+#define MT6332_VRF2_CON13 0x84E2
	313	+#define MT6332_VRF2_CON14 0x84E4
	314	+#define MT6332_VRF2_CON15 0x84E6
	315	+#define MT6332_VRF2_CON16 0x84E8
	316	+#define MT6332_VRF2_CON17 0x84EA
	317	+#define MT6332_VRF2_CON18 0x84EC
	318	+#define MT6332_VRF2_CON19 0x84EE
	319	+#define MT6332_VRF2_CON20 0x84F0
	320	+#define MT6332_VRF2_CON21 0x84F2
	321	+#define MT6332_VPA_CON0 0x84F4
	322	+#define MT6332_VPA_CON1 0x84F6
	323	+#define MT6332_VPA_CON2 0x84F8
	324	+#define MT6332_VPA_CON3 0x84FC
	325	+#define MT6332_VPA_CON4 0x84FE
	326	+#define MT6332_VPA_CON5 0x8500
	327	+#define MT6332_VPA_CON6 0x8502
	328	+#define MT6332_VPA_CON7 0x8504
	329	+#define MT6332_VPA_CON8 0x8506
	330	+#define MT6332_VPA_CON9 0x8508
	331	+#define MT6332_VPA_CON10 0x850A
	332	+#define MT6332_VPA_CON11 0x850C
	333	+#define MT6332_VPA_CON12 0x850E
	334	+#define MT6332_VPA_CON13 0x8510
	335	+#define MT6332_VPA_CON14 0x8512
	336	+#define MT6332_VPA_CON15 0x8514
	337	+#define MT6332_VPA_CON16 0x8516
	338	+#define MT6332_VPA_CON17 0x8518
	339	+#define MT6332_VPA_CON18 0x851A
	340	+#define MT6332_VPA_CON19 0x851C
	341	+#define MT6332_VPA_CON20 0x851E
	342	+#define MT6332_VPA_CON21 0x8520
	343	+#define MT6332_VPA_CON22 0x8522
	344	+#define MT6332_VPA_CON23 0x8524
	345	+#define MT6332_VPA_CON24 0x8526
	346	+#define MT6332_VPA_CON25 0x8528
	347	+#define MT6332_VSBST_CON0 0x852A
	348	+#define MT6332_VSBST_CON1 0x852C
	349	+#define MT6332_VSBST_CON2 0x852E
	350	+#define MT6332_VSBST_CON3 0x8530
	351	+#define MT6332_VSBST_CON4 0x8532
	352	+#define MT6332_VSBST_CON5 0x8534
	353	+#define MT6332_VSBST_CON6 0x8536
	354	+#define MT6332_VSBST_CON7 0x8538
	355	+#define MT6332_VSBST_CON8 0x853A
	356	+#define MT6332_VSBST_CON9 0x853C
	357	+#define MT6332_VSBST_CON10 0x853E
	358	+#define MT6332_VSBST_CON11 0x8540
	359	+#define MT6332_VSBST_CON12 0x8542
	360	+#define MT6332_VSBST_CON13 0x8544
	361	+#define MT6332_VSBST_CON14 0x8546
	362	+#define MT6332_VSBST_CON15 0x8548
	363	+#define MT6332_VSBST_CON16 0x854A
	364	+#define MT6332_VSBST_CON17 0x854C
	365	+#define MT6332_VSBST_CON18 0x854E
	366	+#define MT6332_VSBST_CON19 0x8550
	367	+#define MT6332_VSBST_CON20 0x8552
	368	+#define MT6332_VSBST_CON21 0x8554
	369	+#define MT6332_BUCK_K_CON0 0x8556
	370	+#define MT6332_BUCK_K_CON1 0x8558
	371	+#define MT6332_BUCK_K_CON2 0x855A
	372	+#define MT6332_BUCK_K_CON3 0x855C
	373	+#define MT6332_BUCK_K_CON4 0x855E
	374	+#define MT6332_BUCK_K_CON5 0x8560
	375	+#define MT6332_AUXADC_ADC0 0x8800
	376	+#define MT6332_AUXADC_ADC1 0x8802
	377	+#define MT6332_AUXADC_ADC2 0x8804
	378	+#define MT6332_AUXADC_ADC3 0x8806
	379	+#define MT6332_AUXADC_ADC4 0x8808
	380	+#define MT6332_AUXADC_ADC5 0x880A
	381	+#define MT6332_AUXADC_ADC6 0x880C
	382	+#define MT6332_AUXADC_ADC7 0x880E
	383	+#define MT6332_AUXADC_ADC8 0x8810
	384	+#define MT6332_AUXADC_ADC9 0x8812
	385	+#define MT6332_AUXADC_ADC10 0x8814
	386	+#define MT6332_AUXADC_ADC11 0x8816
	387	+#define MT6332_AUXADC_ADC12 0x8818
	388	+#define MT6332_AUXADC_ADC13 0x881A
	389	+#define MT6332_AUXADC_ADC14 0x881C
	390	+#define MT6332_AUXADC_ADC15 0x881E
	391	+#define MT6332_AUXADC_ADC16 0x8820
	392	+#define MT6332_AUXADC_ADC17 0x8822
	393	+#define MT6332_AUXADC_ADC18 0x8824
	394	+#define MT6332_AUXADC_ADC19 0x8826
	395	+#define MT6332_AUXADC_ADC20 0x8828
	396	+#define MT6332_AUXADC_ADC21 0x882A
	397	+#define MT6332_AUXADC_ADC22 0x882C
	398	+#define MT6332_AUXADC_ADC23 0x882E
	399	+#define MT6332_AUXADC_ADC24 0x8830
	400	+#define MT6332_AUXADC_ADC25 0x8832
	401	+#define MT6332_AUXADC_ADC26 0x8834
	402	+#define MT6332_AUXADC_ADC27 0x8836
	403	+#define MT6332_AUXADC_ADC28 0x8838
	404	+#define MT6332_AUXADC_ADC29 0x883A
	405	+#define MT6332_AUXADC_ADC30 0x883C
	406	+#define MT6332_AUXADC_ADC31 0x883E
	407	+#define MT6332_AUXADC_ADC32 0x8840
	408	+#define MT6332_AUXADC_ADC33 0x8842
	409	+#define MT6332_AUXADC_ADC34 0x8844
	410	+#define MT6332_AUXADC_ADC35 0x8846
	411	+#define MT6332_AUXADC_ADC36 0x8848
	412	+#define MT6332_AUXADC_ADC37 0x884A
	413	+#define MT6332_AUXADC_ADC38 0x884C
	414	+#define MT6332_AUXADC_ADC39 0x884E
	415	+#define MT6332_AUXADC_ADC40 0x8850
	416	+#define MT6332_AUXADC_ADC41 0x8852
	417	+#define MT6332_AUXADC_ADC42 0x8854
	418	+#define MT6332_AUXADC_ADC43 0x8856
	419	+#define MT6332_AUXADC_STA0 0x8858
	420	+#define MT6332_AUXADC_STA1 0x885A
	421	+#define MT6332_AUXADC_RQST0 0x885C
	422	+#define MT6332_AUXADC_RQST0_SET 0x885E
	423	+#define MT6332_AUXADC_RQST0_CLR 0x8860
	424	+#define MT6332_AUXADC_RQST1 0x8862
	425	+#define MT6332_AUXADC_RQST1_SET 0x8864
	426	+#define MT6332_AUXADC_RQST1_CLR 0x8866
	427	+#define MT6332_AUXADC_CON0 0x8868
	428	+#define MT6332_AUXADC_CON1 0x886A
	429	+#define MT6332_AUXADC_CON2 0x886C
	430	+#define MT6332_AUXADC_CON3 0x886E
	431	+#define MT6332_AUXADC_CON4 0x8870
	432	+#define MT6332_AUXADC_CON5 0x8872
	433	+#define MT6332_AUXADC_CON6 0x8874
	434	+#define MT6332_AUXADC_CON7 0x8876
	435	+#define MT6332_AUXADC_CON8 0x8878
	436	+#define MT6332_AUXADC_CON9 0x887A
	437	+#define MT6332_AUXADC_CON10 0x887C
	438	+#define MT6332_AUXADC_CON11 0x887E
	439	+#define MT6332_AUXADC_CON12 0x8880
	440	+#define MT6332_AUXADC_CON13 0x8882
	441	+#define MT6332_AUXADC_CON14 0x8884
	442	+#define MT6332_AUXADC_CON15 0x8886
	443	+#define MT6332_AUXADC_CON16 0x8888
	444	+#define MT6332_AUXADC_CON17 0x888A
	445	+#define MT6332_AUXADC_CON18 0x888C
	446	+#define MT6332_AUXADC_CON19 0x888E
	447	+#define MT6332_AUXADC_CON20 0x8890
	448	+#define MT6332_AUXADC_CON21 0x8892
	449	+#define MT6332_AUXADC_CON22 0x8894
	450	+#define MT6332_AUXADC_CON23 0x8896
	451	+#define MT6332_AUXADC_CON24 0x8898
	452	+#define MT6332_AUXADC_CON25 0x889A
	453	+#define MT6332_AUXADC_CON26 0x889C
	454	+#define MT6332_AUXADC_CON27 0x889E
	455	+#define MT6332_AUXADC_CON28 0x88A0
	456	+#define MT6332_AUXADC_CON29 0x88A2
	457	+#define MT6332_AUXADC_CON30 0x88A4
	458	+#define MT6332_AUXADC_CON31 0x88A6
	459	+#define MT6332_AUXADC_CON32 0x88A8
	460	+#define MT6332_AUXADC_CON33 0x88AA
	461	+#define MT6332_AUXADC_CON34 0x88AC
	462	+#define MT6332_AUXADC_CON35 0x88AE
	463	+#define MT6332_AUXADC_CON36 0x88B0
	464	+#define MT6332_AUXADC_CON37 0x88B2
	465	+#define MT6332_AUXADC_CON38 0x88B4
	466	+#define MT6332_AUXADC_CON39 0x88B6
	467	+#define MT6332_AUXADC_CON40 0x88B8
	468	+#define MT6332_AUXADC_CON41 0x88BA
	469	+#define MT6332_AUXADC_CON42 0x88BC
	470	+#define MT6332_AUXADC_CON43 0x88BE
	471	+#define MT6332_AUXADC_CON44 0x88C0
	472	+#define MT6332_AUXADC_CON45 0x88C2
	473	+#define MT6332_AUXADC_CON46 0x88C4
	474	+#define MT6332_AUXADC_CON47 0x88C6
	475	+#define MT6332_STRUP_CONA0 0x8C00
	476	+#define MT6332_STRUP_CONA1 0x8C02
	477	+#define MT6332_STRUP_CONA2 0x8C04
	478	+#define MT6332_STRUP_CON0 0x8C06
	479	+#define MT6332_STRUP_CON2 0x8C08
	480	+#define MT6332_STRUP_CON3 0x8C0A
	481	+#define MT6332_STRUP_CON4 0x8C0C
	482	+#define MT6332_STRUP_CON5 0x8C0E
	483	+#define MT6332_STRUP_CON6 0x8C10
	484	+#define MT6332_STRUP_CON7 0x8C12
	485	+#define MT6332_STRUP_CON8 0x8C14
	486	+#define MT6332_STRUP_CON9 0x8C16
	487	+#define MT6332_STRUP_CON10 0x8C18
	488	+#define MT6332_STRUP_CON11 0x8C1A
	489	+#define MT6332_STRUP_CON12 0x8C1C
	490	+#define MT6332_STRUP_CON13 0x8C1E
	491	+#define MT6332_STRUP_CON14 0x8C20
	492	+#define MT6332_STRUP_CON15 0x8C22
	493	+#define MT6332_STRUP_CON16 0x8C24
	494	+#define MT6332_STRUP_CON17 0x8C26
	495	+#define MT6332_FGADC_CON0 0x8C28
	496	+#define MT6332_FGADC_CON1 0x8C2A
	497	+#define MT6332_FGADC_CON2 0x8C2C
	498	+#define MT6332_FGADC_CON3 0x8C2E
	499	+#define MT6332_FGADC_CON4 0x8C30
	500	+#define MT6332_FGADC_CON5 0x8C32
	501	+#define MT6332_FGADC_CON6 0x8C34
	502	+#define MT6332_FGADC_CON7 0x8C36
	503	+#define MT6332_FGADC_CON8 0x8C38
	504	+#define MT6332_FGADC_CON9 0x8C3A
	505	+#define MT6332_FGADC_CON10 0x8C3C
	506	+#define MT6332_FGADC_CON11 0x8C3E
	507	+#define MT6332_FGADC_CON12 0x8C40
	508	+#define MT6332_FGADC_CON13 0x8C42
	509	+#define MT6332_FGADC_CON14 0x8C44
	510	+#define MT6332_FGADC_CON15 0x8C46
	511	+#define MT6332_FGADC_CON16 0x8C48
	512	+#define MT6332_FGADC_CON17 0x8C4A
	513	+#define MT6332_FGADC_CON18 0x8C4C
	514	+#define MT6332_FGADC_CON19 0x8C4E
	515	+#define MT6332_FGADC_CON20 0x8C50
	516	+#define MT6332_FGADC_CON21 0x8C52
	517	+#define MT6332_FGADC_CON22 0x8C54
	518	+#define MT6332_OTP_CON0 0x8C56
	519	+#define MT6332_OTP_CON1 0x8C58
	520	+#define MT6332_OTP_CON2 0x8C5A
	521	+#define MT6332_OTP_CON3 0x8C5C
	522	+#define MT6332_OTP_CON4 0x8C5E
	523	+#define MT6332_OTP_CON5 0x8C60
	524	+#define MT6332_OTP_CON6 0x8C62
	525	+#define MT6332_OTP_CON7 0x8C64
	526	+#define MT6332_OTP_CON8 0x8C66
	527	+#define MT6332_OTP_CON9 0x8C68
	528	+#define MT6332_OTP_CON10 0x8C6A
	529	+#define MT6332_OTP_CON11 0x8C6C
	530	+#define MT6332_OTP_CON12 0x8C6E
	531	+#define MT6332_OTP_CON13 0x8C70
	532	+#define MT6332_OTP_CON14 0x8C72
	533	+#define MT6332_OTP_DOUT_0_15 0x8C74
	534	+#define MT6332_OTP_DOUT_16_31 0x8C76
	535	+#define MT6332_OTP_DOUT_32_47 0x8C78
	536	+#define MT6332_OTP_DOUT_48_63 0x8C7A
	537	+#define MT6332_OTP_DOUT_64_79 0x8C7C
	538	+#define MT6332_OTP_DOUT_80_95 0x8C7E
	539	+#define MT6332_OTP_DOUT_96_111 0x8C80
	540	+#define MT6332_OTP_DOUT_112_127 0x8C82
	541	+#define MT6332_OTP_DOUT_128_143 0x8C84
	542	+#define MT6332_OTP_DOUT_144_159 0x8C86
	543	+#define MT6332_OTP_DOUT_160_175 0x8C88
	544	+#define MT6332_OTP_DOUT_176_191 0x8C8A
	545	+#define MT6332_OTP_DOUT_192_207 0x8C8C
	546	+#define MT6332_OTP_DOUT_208_223 0x8C8E
	547	+#define MT6332_OTP_DOUT_224_239 0x8C90
	548	+#define MT6332_OTP_DOUT_240_255 0x8C92
	549	+#define MT6332_OTP_VAL_0_15 0x8C94
	550	+#define MT6332_OTP_VAL_16_31 0x8C96
	551	+#define MT6332_OTP_VAL_32_47 0x8C98
	552	+#define MT6332_OTP_VAL_48_63 0x8C9A
	553	+#define MT6332_OTP_VAL_64_79 0x8C9C
	554	+#define MT6332_OTP_VAL_80_95 0x8C9E
	555	+#define MT6332_OTP_VAL_96_111 0x8CA0
	556	+#define MT6332_OTP_VAL_112_127 0x8CA2
	557	+#define MT6332_OTP_VAL_128_143 0x8CA4
	558	+#define MT6332_OTP_VAL_144_159 0x8CA6
	559	+#define MT6332_OTP_VAL_160_175 0x8CA8
	560	+#define MT6332_OTP_VAL_176_191 0x8CAA
	561	+#define MT6332_OTP_VAL_192_207 0x8CAC
	562	+#define MT6332_OTP_VAL_208_223 0x8CAE
	563	+#define MT6332_OTP_VAL_224_239 0x8CB0
	564	+#define MT6332_OTP_VAL_240_255 0x8CB2
	565	+#define MT6332_LDO_CON0 0x8CB4
	566	+#define MT6332_LDO_CON1 0x8CB6
	567	+#define MT6332_LDO_CON2 0x8CB8
	568	+#define MT6332_LDO_CON3 0x8CBA
	569	+#define MT6332_LDO_CON5 0x8CBC
	570	+#define MT6332_LDO_CON6 0x8CBE
	571	+#define MT6332_LDO_CON7 0x8CC0
	572	+#define MT6332_LDO_CON8 0x8CC2
	573	+#define MT6332_LDO_CON9 0x8CC4
	574	+#define MT6332_LDO_CON10 0x8CC6
	575	+#define MT6332_LDO_CON11 0x8CC8
	576	+#define MT6332_LDO_CON12 0x8CCA
	577	+#define MT6332_LDO_CON13 0x8CCC
	578	+#define MT6332_FQMTR_CON0 0x8CCE
	579	+#define MT6332_FQMTR_CON1 0x8CD0
	580	+#define MT6332_FQMTR_CON2 0x8CD2
	581	+#define MT6332_IWLED_CON0 0x8CD4
	582	+#define MT6332_IWLED_DEG 0x8CD6
	583	+#define MT6332_IWLED_STATUS 0x8CD8
	584	+#define MT6332_IWLED_EN_CTRL 0x8CDA
	585	+#define MT6332_IWLED_CON1 0x8CDC
	586	+#define MT6332_IWLED_CON2 0x8CDE
	587	+#define MT6332_IWLED_TRIM0 0x8CE0
	588	+#define MT6332_IWLED_TRIM1 0x8CE2
	589	+#define MT6332_IWLED_CON3 0x8CE4
	590	+#define MT6332_IWLED_CON4 0x8CE6
	591	+#define MT6332_IWLED_CON5 0x8CE8
	592	+#define MT6332_IWLED_CON6 0x8CEA
	593	+#define MT6332_IWLED_CON7 0x8CEC
	594	+#define MT6332_IWLED_CON8 0x8CEE
	595	+#define MT6332_IWLED_CON9 0x8CF0
	596	+#define MT6332_SPK_CON0 0x8CF2
	597	+#define MT6332_SPK_CON1 0x8CF4
	598	+#define MT6332_SPK_CON2 0x8CF6
	599	+#define MT6332_SPK_CON3 0x8CF8
	600	+#define MT6332_SPK_CON4 0x8CFA
	601	+#define MT6332_SPK_CON5 0x8CFC
	602	+#define MT6332_SPK_CON6 0x8CFE
	603	+#define MT6332_SPK_CON7 0x8D00
	604	+#define MT6332_SPK_CON8 0x8D02
	605	+#define MT6332_SPK_CON9 0x8D04
	606	+#define MT6332_SPK_CON10 0x8D06
	607	+#define MT6332_SPK_CON11 0x8D08
	608	+#define MT6332_SPK_CON12 0x8D0A
	609	+#define MT6332_SPK_CON13 0x8D0C
	610	+#define MT6332_SPK_CON14 0x8D0E
	611	+#define MT6332_SPK_CON15 0x8D10
	612	+#define MT6332_SPK_CON16 0x8D12
	613	+#define MT6332_TESTI_CON0 0x8D14
	614	+#define MT6332_TESTI_CON1 0x8D16
	615	+#define MT6332_TESTI_CON2 0x8D18
	616	+#define MT6332_TESTI_CON3 0x8D1A
	617	+#define MT6332_TESTI_CON4 0x8D1C
	618	+#define MT6332_TESTI_CON5 0x8D1E
	619	+#define MT6332_TESTI_CON6 0x8D20
	620	+#define MT6332_TESTI_MUX_CON0 0x8D22
	621	+#define MT6332_TESTI_MUX_CON1 0x8D24
	622	+#define MT6332_TESTI_MUX_CON2 0x8D26
	623	+#define MT6332_TESTI_MUX_CON3 0x8D28
	624	+#define MT6332_TESTI_MUX_CON4 0x8D2A
	625	+#define MT6332_TESTI_MUX_CON5 0x8D2C
	626	+#define MT6332_TESTI_MUX_CON6 0x8D2E
	627	+#define MT6332_TESTO_CON0 0x8D30
	628	+#define MT6332_TESTO_CON1 0x8D32
	629	+#define MT6332_TEST_OMUX_CON0 0x8D34
	630	+#define MT6332_TEST_OMUX_CON1 0x8D36
	631	+#define MT6332_DEBUG_CON0 0x8D38
	632	+#define MT6332_DEBUG_CON1 0x8D3A
	633	+#define MT6332_DEBUG_CON2 0x8D3C
	634	+#define MT6332_FGADC_CON23 0x8D3E
	635	+#define MT6332_FGADC_CON24 0x8D40
	636	+#define MT6332_FGADC_CON25 0x8D42
	637	+#define MT6332_TOP_RST_STATUS 0x8D44
	638	+#define MT6332_TOP_RST_STATUS_SET 0x8D46
	639	+#define MT6332_TOP_RST_STATUS_CLR 0x8D48
	640	+#define MT6332_VDVFS2_CON28 0x8D4A
	641	+
	642	+#endif /* __MFD_MT6332_REGISTERS_H__ */

include/linux/mfd/mt6357/core.h+119−0

@@ -0,0 +1,119 @@
	1	+/* SPDX-License-Identifier: GPL-2.0-only */
	2	+/*
	3	+ * Copyright (c) 2022 BayLibre, SAS
	4	+ * Author: Fabien Parent <fparent@baylibre.com>
	5	+ */
	6	+
	7	+#ifndef __MFD_MT6357_CORE_H__
	8	+#define __MFD_MT6357_CORE_H__
	9	+
	10	+enum mt6357_irq_top_status_shift {
	11	+ MT6357_BUCK_TOP = 0,
	12	+ MT6357_LDO_TOP,
	13	+ MT6357_PSC_TOP,
	14	+ MT6357_SCK_TOP,
	15	+ MT6357_BM_TOP,
	16	+ MT6357_HK_TOP,
	17	+ MT6357_XPP_TOP,
	18	+ MT6357_AUD_TOP,
	19	+ MT6357_MISC_TOP,
	20	+};
	21	+
	22	+enum mt6357_irq_numbers {
	23	+ MT6357_IRQ_VPROC_OC = 0,
	24	+ MT6357_IRQ_VCORE_OC,
	25	+ MT6357_IRQ_VMODEM_OC,
	26	+ MT6357_IRQ_VS1_OC,
	27	+ MT6357_IRQ_VPA_OC,
	28	+ MT6357_IRQ_VCORE_PREOC,
	29	+ MT6357_IRQ_VFE28_OC = 16,
	30	+ MT6357_IRQ_VXO22_OC,
	31	+ MT6357_IRQ_VRF18_OC,
	32	+ MT6357_IRQ_VRF12_OC,
	33	+ MT6357_IRQ_VEFUSE_OC,
	34	+ MT6357_IRQ_VCN33_OC,
	35	+ MT6357_IRQ_VCN28_OC,
	36	+ MT6357_IRQ_VCN18_OC,
	37	+ MT6357_IRQ_VCAMA_OC,
	38	+ MT6357_IRQ_VCAMD_OC,
	39	+ MT6357_IRQ_VCAMIO_OC,
	40	+ MT6357_IRQ_VLDO28_OC,
	41	+ MT6357_IRQ_VUSB33_OC,
	42	+ MT6357_IRQ_VAUX18_OC,
	43	+ MT6357_IRQ_VAUD28_OC,
	44	+ MT6357_IRQ_VIO28_OC,
	45	+ MT6357_IRQ_VIO18_OC,
	46	+ MT6357_IRQ_VSRAM_PROC_OC,
	47	+ MT6357_IRQ_VSRAM_OTHERS_OC,
	48	+ MT6357_IRQ_VIBR_OC,
	49	+ MT6357_IRQ_VDRAM_OC,
	50	+ MT6357_IRQ_VMC_OC,
	51	+ MT6357_IRQ_VMCH_OC,
	52	+ MT6357_IRQ_VEMC_OC,
	53	+ MT6357_IRQ_VSIM1_OC,
	54	+ MT6357_IRQ_VSIM2_OC,
	55	+ MT6357_IRQ_PWRKEY = 48,
	56	+ MT6357_IRQ_HOMEKEY,
	57	+ MT6357_IRQ_PWRKEY_R,
	58	+ MT6357_IRQ_HOMEKEY_R,
	59	+ MT6357_IRQ_NI_LBAT_INT,
	60	+ MT6357_IRQ_CHRDET,
	61	+ MT6357_IRQ_CHRDET_EDGE,
	62	+ MT6357_IRQ_VCDT_HV_DET,
	63	+ MT6357_IRQ_WATCHDOG,
	64	+ MT6357_IRQ_VBATON_UNDET,
	65	+ MT6357_IRQ_BVALID_DET,
	66	+ MT6357_IRQ_OV,
	67	+ MT6357_IRQ_RTC = 64,
	68	+ MT6357_IRQ_FG_BAT0_H = 80,
	69	+ MT6357_IRQ_FG_BAT0_L,
	70	+ MT6357_IRQ_FG_CUR_H,
	71	+ MT6357_IRQ_FG_CUR_L,
	72	+ MT6357_IRQ_FG_ZCV,
	73	+ MT6357_IRQ_BATON_LV = 96,
	74	+ MT6357_IRQ_BATON_HT,
	75	+ MT6357_IRQ_BAT_H = 112,
	76	+ MT6357_IRQ_BAT_L,
	77	+ MT6357_IRQ_AUXADC_IMP,
	78	+ MT6357_IRQ_NAG_C_DLTV,
	79	+ MT6357_IRQ_AUDIO = 128,
	80	+ MT6357_IRQ_ACCDET = 133,
	81	+ MT6357_IRQ_ACCDET_EINT0,
	82	+ MT6357_IRQ_ACCDET_EINT1,
	83	+ MT6357_IRQ_SPI_CMD_ALERT = 144,
	84	+ MT6357_IRQ_NR,
	85	+};
	86	+
	87	+#define MT6357_IRQ_BUCK_BASE MT6357_IRQ_VPROC_OC
	88	+#define MT6357_IRQ_LDO_BASE MT6357_IRQ_VFE28_OC
	89	+#define MT6357_IRQ_PSC_BASE MT6357_IRQ_PWRKEY
	90	+#define MT6357_IRQ_SCK_BASE MT6357_IRQ_RTC
	91	+#define MT6357_IRQ_BM_BASE MT6357_IRQ_FG_BAT0_H
	92	+#define MT6357_IRQ_HK_BASE MT6357_IRQ_BAT_H
	93	+#define MT6357_IRQ_AUD_BASE MT6357_IRQ_AUDIO
	94	+#define MT6357_IRQ_MISC_BASE MT6357_IRQ_SPI_CMD_ALERT
	95	+
	96	+#define MT6357_IRQ_BUCK_BITS (MT6357_IRQ_VCORE_PREOC - MT6357_IRQ_BUCK_BASE + 1)
	97	+#define MT6357_IRQ_LDO_BITS (MT6357_IRQ_VSIM2_OC - MT6357_IRQ_LDO_BASE + 1)
	98	+#define MT6357_IRQ_PSC_BITS (MT6357_IRQ_VCDT_HV_DET - MT6357_IRQ_PSC_BASE + 1)
	99	+#define MT6357_IRQ_SCK_BITS (MT6357_IRQ_RTC - MT6357_IRQ_SCK_BASE + 1)
	100	+#define MT6357_IRQ_BM_BITS (MT6357_IRQ_BATON_HT - MT6357_IRQ_BM_BASE + 1)
	101	+#define MT6357_IRQ_HK_BITS (MT6357_IRQ_NAG_C_DLTV - MT6357_IRQ_HK_BASE + 1)
	102	+#define MT6357_IRQ_AUD_BITS (MT6357_IRQ_ACCDET_EINT1 - MT6357_IRQ_AUD_BASE + 1)
	103	+#define MT6357_IRQ_MISC_BITS \
	104	+ (MT6357_IRQ_SPI_CMD_ALERT - MT6357_IRQ_MISC_BASE + 1)
	105	+
	106	+#define MT6357_TOP_GEN(sp) \
	107	+{ \
	108	+ .hwirq_base = MT6357_IRQ_##sp##_BASE, \
	109	+ .num_int_regs = \
	110	+ ((MT6357_IRQ_##sp##_BITS - 1) / \
	111	+ MTK_PMIC_REG_WIDTH) + 1, \
	112	+ .en_reg = MT6357_##sp##_TOP_INT_CON0, \
	113	+ .en_reg_shift = 0x6, \
	114	+ .sta_reg = MT6357_##sp##_TOP_INT_STATUS0, \
	115	+ .sta_reg_shift = 0x2, \
	116	+ .top_offset = MT6357_##sp##_TOP, \
	117	+}
	118	+
	119	+#endif /* __MFD_MT6357_CORE_H__ */

include/linux/mfd/mt6357/registers.h+1574−0

@@ -0,0 +1,1574 @@
	1	+/* SPDX-License-Identifier: GPL-2.0 */
	2	+/*
	3	+ * Copyright (c) 2022 MediaTek Inc.
	4	+ */
	5	+
	6	+#ifndef __MFD_MT6357_REGISTERS_H__
	7	+#define __MFD_MT6357_REGISTERS_H__
	8	+
	9	+/* PMIC Registers */
	10	+#define MT6357_TOP0_ID 0x0
	11	+#define MT6357_TOP0_REV0 0x2
	12	+#define MT6357_TOP0_DSN_DBI 0x4
	13	+#define MT6357_TOP0_DSN_DXI 0x6
	14	+#define MT6357_HWCID 0x8
	15	+#define MT6357_SWCID 0xa
	16	+#define MT6357_PONSTS 0xc
	17	+#define MT6357_POFFSTS 0xe
	18	+#define MT6357_PSTSCTL 0x10
	19	+#define MT6357_PG_DEB_STS0 0x12
	20	+#define MT6357_PG_SDN_STS0 0x14
	21	+#define MT6357_OC_SDN_STS0 0x16
	22	+#define MT6357_THERMALSTATUS 0x18
	23	+#define MT6357_TOP_CON 0x1a
	24	+#define MT6357_TEST_OUT 0x1c
	25	+#define MT6357_TEST_CON0 0x1e
	26	+#define MT6357_TEST_CON1 0x20
	27	+#define MT6357_TESTMODE_SW 0x22
	28	+#define MT6357_TOPSTATUS 0x24
	29	+#define MT6357_TDSEL_CON 0x26
	30	+#define MT6357_RDSEL_CON 0x28
	31	+#define MT6357_SMT_CON0 0x2a
	32	+#define MT6357_SMT_CON1 0x2c
	33	+#define MT6357_TOP_RSV0 0x2e
	34	+#define MT6357_TOP_RSV1 0x30
	35	+#define MT6357_DRV_CON0 0x32
	36	+#define MT6357_DRV_CON1 0x34
	37	+#define MT6357_DRV_CON2 0x36
	38	+#define MT6357_DRV_CON3 0x38
	39	+#define MT6357_FILTER_CON0 0x3a
	40	+#define MT6357_FILTER_CON1 0x3c
	41	+#define MT6357_FILTER_CON2 0x3e
	42	+#define MT6357_FILTER_CON3 0x40
	43	+#define MT6357_TOP_STATUS 0x42
	44	+#define MT6357_TOP_STATUS_SET 0x44
	45	+#define MT6357_TOP_STATUS_CLR 0x46
	46	+#define MT6357_TOP_TRAP 0x48
	47	+#define MT6357_TOP1_ID 0x80
	48	+#define MT6357_TOP1_REV0 0x82
	49	+#define MT6357_TOP1_DSN_DBI 0x84
	50	+#define MT6357_TOP1_DSN_DXI 0x86
	51	+#define MT6357_GPIO_DIR0 0x88
	52	+#define MT6357_GPIO_DIR0_SET 0x8a
	53	+#define MT6357_GPIO_DIR0_CLR 0x8c
	54	+#define MT6357_GPIO_PULLEN0 0x8e
	55	+#define MT6357_GPIO_PULLEN0_SET 0x90
	56	+#define MT6357_GPIO_PULLEN0_CLR 0x92
	57	+#define MT6357_GPIO_PULLSEL0 0x94
	58	+#define MT6357_GPIO_PULLSEL0_SET 0x96
	59	+#define MT6357_GPIO_PULLSEL0_CLR 0x98
	60	+#define MT6357_GPIO_DINV0 0x9a
	61	+#define MT6357_GPIO_DINV0_SET 0x9c
	62	+#define MT6357_GPIO_DINV0_CLR 0x9e
	63	+#define MT6357_GPIO_DOUT0 0xa0
	64	+#define MT6357_GPIO_DOUT0_SET 0xa2
	65	+#define MT6357_GPIO_DOUT0_CLR 0xa4
	66	+#define MT6357_GPIO_PI0 0xa6
	67	+#define MT6357_GPIO_POE0 0xa8
	68	+#define MT6357_GPIO_MODE0 0xaa
	69	+#define MT6357_GPIO_MODE0_SET 0xac
	70	+#define MT6357_GPIO_MODE0_CLR 0xae
	71	+#define MT6357_GPIO_MODE1 0xb0
	72	+#define MT6357_GPIO_MODE1_SET 0xb2
	73	+#define MT6357_GPIO_MODE1_CLR 0xb4
	74	+#define MT6357_GPIO_MODE2 0xb6
	75	+#define MT6357_GPIO_MODE2_SET 0xb8
	76	+#define MT6357_GPIO_MODE2_CLR 0xba
	77	+#define MT6357_GPIO_MODE3 0xbc
	78	+#define MT6357_GPIO_MODE3_SET 0xbe
	79	+#define MT6357_GPIO_MODE3_CLR 0xc0
	80	+#define MT6357_GPIO_RSV 0xc2
	81	+#define MT6357_TOP2_ID 0x100
	82	+#define MT6357_TOP2_REV0 0x102
	83	+#define MT6357_TOP2_DSN_DBI 0x104
	84	+#define MT6357_TOP2_DSN_DXI 0x106
	85	+#define MT6357_TOP_PAM0 0x108
	86	+#define MT6357_TOP_PAM1 0x10a
	87	+#define MT6357_TOP_CKPDN_CON0 0x10c
	88	+#define MT6357_TOP_CKPDN_CON0_SET 0x10e
	89	+#define MT6357_TOP_CKPDN_CON0_CLR 0x110
	90	+#define MT6357_TOP_CKPDN_CON1 0x112
	91	+#define MT6357_TOP_CKPDN_CON1_SET 0x114
	92	+#define MT6357_TOP_CKPDN_CON1_CLR 0x116
	93	+#define MT6357_TOP_CKSEL_CON0 0x118
	94	+#define MT6357_TOP_CKSEL_CON0_SET 0x11a
	95	+#define MT6357_TOP_CKSEL_CON0_CLR 0x11c
	96	+#define MT6357_TOP_CKSEL_CON1 0x11e
	97	+#define MT6357_TOP_CKSEL_CON1_SET 0x120
	98	+#define MT6357_TOP_CKSEL_CON1_CLR 0x122
	99	+#define MT6357_TOP_CKDIVSEL_CON0 0x124
	100	+#define MT6357_TOP_CKDIVSEL_CON0_SET 0x126
	101	+#define MT6357_TOP_CKDIVSEL_CON0_CLR 0x128
	102	+#define MT6357_TOP_CKHWEN_CON0 0x12a
	103	+#define MT6357_TOP_CKHWEN_CON0_SET 0x12c
	104	+#define MT6357_TOP_CKHWEN_CON0_CLR 0x12e
	105	+#define MT6357_TOP_CKTST_CON0 0x130
	106	+#define MT6357_TOP_CKTST_CON1 0x132
	107	+#define MT6357_TOP_CLK_CON0 0x134
	108	+#define MT6357_TOP_CLK_CON0_SET 0x136
	109	+#define MT6357_TOP_CLK_CON0_CLR 0x138
	110	+#define MT6357_TOP_DCM_CON0 0x13a
	111	+#define MT6357_TOP_HANDOVER_DEBUG0 0x13c
	112	+#define MT6357_TOP_RST_CON0 0x13e
	113	+#define MT6357_TOP_RST_CON0_SET 0x140
	114	+#define MT6357_TOP_RST_CON0_CLR 0x142
	115	+#define MT6357_TOP_RST_CON1 0x144
	116	+#define MT6357_TOP_RST_CON1_SET 0x146
	117	+#define MT6357_TOP_RST_CON1_CLR 0x148
	118	+#define MT6357_TOP_RST_CON2 0x14a
	119	+#define MT6357_TOP_RST_MISC 0x14c
	120	+#define MT6357_TOP_RST_MISC_SET 0x14e
	121	+#define MT6357_TOP_RST_MISC_CLR 0x150
	122	+#define MT6357_TOP_RST_STATUS 0x152
	123	+#define MT6357_TOP_RST_STATUS_SET 0x154
	124	+#define MT6357_TOP_RST_STATUS_CLR 0x156
	125	+#define MT6357_TOP2_ELR_NUM 0x158
	126	+#define MT6357_TOP2_ELR0 0x15a
	127	+#define MT6357_TOP2_ELR1 0x15c
	128	+#define MT6357_TOP3_ID 0x180
	129	+#define MT6357_TOP3_REV0 0x182
	130	+#define MT6357_TOP3_DSN_DBI 0x184
	131	+#define MT6357_TOP3_DSN_DXI 0x186
	132	+#define MT6357_MISC_TOP_INT_CON0 0x188
	133	+#define MT6357_MISC_TOP_INT_CON0_SET 0x18a
	134	+#define MT6357_MISC_TOP_INT_CON0_CLR 0x18c
	135	+#define MT6357_MISC_TOP_INT_MASK_CON0 0x18e
	136	+#define MT6357_MISC_TOP_INT_MASK_CON0_SET 0x190
	137	+#define MT6357_MISC_TOP_INT_MASK_CON0_CLR 0x192
	138	+#define MT6357_MISC_TOP_INT_STATUS0 0x194
	139	+#define MT6357_MISC_TOP_INT_RAW_STATUS0 0x196
	140	+#define MT6357_TOP_INT_MASK_CON0 0x198
	141	+#define MT6357_TOP_INT_MASK_CON0_SET 0x19a
	142	+#define MT6357_TOP_INT_MASK_CON0_CLR 0x19c
	143	+#define MT6357_TOP_INT_STATUS0 0x19e
	144	+#define MT6357_TOP_INT_RAW_STATUS0 0x1a0
	145	+#define MT6357_TOP_INT_CON0 0x1a2
	146	+#define MT6357_PLT0_ID 0x380
	147	+#define MT6357_PLT0_REV0 0x382
	148	+#define MT6357_PLT0_REV1 0x384
	149	+#define MT6357_PLT0_DSN_DXI 0x386
	150	+#define MT6357_FQMTR_CON0 0x388
	151	+#define MT6357_FQMTR_CON1 0x38a
	152	+#define MT6357_FQMTR_CON2 0x38c
	153	+#define MT6357_TOP_CLK_TRIM 0x38e
	154	+#define MT6357_OTP_CON0 0x390
	155	+#define MT6357_OTP_CON1 0x392
	156	+#define MT6357_OTP_CON2 0x394
	157	+#define MT6357_OTP_CON3 0x396
	158	+#define MT6357_OTP_CON4 0x398
	159	+#define MT6357_OTP_CON5 0x39a
	160	+#define MT6357_OTP_CON6 0x39c
	161	+#define MT6357_OTP_CON7 0x39e
	162	+#define MT6357_OTP_CON8 0x3a0
	163	+#define MT6357_OTP_CON9 0x3a2
	164	+#define MT6357_OTP_CON10 0x3a4
	165	+#define MT6357_OTP_CON11 0x3a6
	166	+#define MT6357_OTP_CON12 0x3a8
	167	+#define MT6357_OTP_CON13 0x3aa
	168	+#define MT6357_OTP_CON14 0x3ac
	169	+#define MT6357_TOP_TMA_KEY 0x3ae
	170	+#define MT6357_TOP_MDB_CONF0 0x3b0
	171	+#define MT6357_TOP_MDB_CONF1 0x3b2
	172	+#define MT6357_TOP_MDB_CONF2 0x3b4
	173	+#define MT6357_PLT0_ELR_NUM 0x3b6
	174	+#define MT6357_PLT0_ELR0 0x3b8
	175	+#define MT6357_PLT0_ELR1 0x3ba
	176	+#define MT6357_SPISLV_ID 0x400
	177	+#define MT6357_SPISLV_REV0 0x402
	178	+#define MT6357_SPISLV_REV1 0x404
	179	+#define MT6357_SPISLV_DSN_DXI 0x406
	180	+#define MT6357_RG_SPI_CON0 0x408
	181	+#define MT6357_DEW_DIO_EN 0x40a
	182	+#define MT6357_DEW_READ_TEST 0x40c
	183	+#define MT6357_DEW_WRITE_TEST 0x40e
	184	+#define MT6357_DEW_CRC_SWRST 0x410
	185	+#define MT6357_DEW_CRC_EN 0x412
	186	+#define MT6357_DEW_CRC_VAL 0x414
	187	+#define MT6357_DEW_DBG_MON_SEL 0x416
	188	+#define MT6357_DEW_CIPHER_KEY_SEL 0x418
	189	+#define MT6357_DEW_CIPHER_IV_SEL 0x41a
	190	+#define MT6357_DEW_CIPHER_EN 0x41c
	191	+#define MT6357_DEW_CIPHER_RDY 0x41e
	192	+#define MT6357_DEW_CIPHER_MODE 0x420
	193	+#define MT6357_DEW_CIPHER_SWRST 0x422
	194	+#define MT6357_DEW_RDDMY_NO 0x424
	195	+#define MT6357_INT_TYPE_CON0 0x426
	196	+#define MT6357_INT_TYPE_CON0_SET 0x428
	197	+#define MT6357_INT_TYPE_CON0_CLR 0x42a
	198	+#define MT6357_INT_STA 0x42c
	199	+#define MT6357_RG_SPI_CON1 0x42e
	200	+#define MT6357_RG_SPI_CON2 0x430
	201	+#define MT6357_RG_SPI_CON3 0x432
	202	+#define MT6357_RG_SPI_CON4 0x434
	203	+#define MT6357_RG_SPI_CON5 0x436
	204	+#define MT6357_RG_SPI_CON6 0x438
	205	+#define MT6357_RG_SPI_CON7 0x43a
	206	+#define MT6357_RG_SPI_CON8 0x43c
	207	+#define MT6357_RG_SPI_CON9 0x43e
	208	+#define MT6357_RG_SPI_CON10 0x440
	209	+#define MT6357_RG_SPI_CON11 0x442
	210	+#define MT6357_RG_SPI_CON12 0x444
	211	+#define MT6357_RG_SPI_CON13 0x446
	212	+#define MT6357_TOP_SPI_CON0 0x448
	213	+#define MT6357_TOP_SPI_CON1 0x44a
	214	+#define MT6357_SCK_TOP_DSN_ID 0x500
	215	+#define MT6357_SCK_TOP_DSN_REV0 0x502
	216	+#define MT6357_SCK_TOP_DBI 0x504
	217	+#define MT6357_SCK_TOP_DXI 0x506
	218	+#define MT6357_SCK_TOP_TPM0 0x508
	219	+#define MT6357_SCK_TOP_TPM1 0x50a
	220	+#define MT6357_SCK_TOP_CON0 0x50c
	221	+#define MT6357_SCK_TOP_CON1 0x50e
	222	+#define MT6357_SCK_TOP_TEST_OUT 0x510
	223	+#define MT6357_SCK_TOP_TEST_CON0 0x512
	224	+#define MT6357_SCK_TOP_CKPDN_CON0 0x514
	225	+#define MT6357_SCK_TOP_CKPDN_CON0_SET 0x516
	226	+#define MT6357_SCK_TOP_CKPDN_CON0_CLR 0x518
	227	+#define MT6357_SCK_TOP_CKHWEN_CON0 0x51a
	228	+#define MT6357_SCK_TOP_CKHWEN_CON0_SET 0x51c
	229	+#define MT6357_SCK_TOP_CKHWEN_CON0_CLR 0x51e
	230	+#define MT6357_SCK_TOP_CKTST_CON 0x520
	231	+#define MT6357_SCK_TOP_RST_CON0 0x522
	232	+#define MT6357_SCK_TOP_RST_CON0_SET 0x524
	233	+#define MT6357_SCK_TOP_RST_CON0_CLR 0x526
	234	+#define MT6357_SCK_TOP_INT_CON0 0x528
	235	+#define MT6357_SCK_TOP_INT_CON0_SET 0x52a
	236	+#define MT6357_SCK_TOP_INT_CON0_CLR 0x52c
	237	+#define MT6357_SCK_TOP_INT_MASK_CON0 0x52e
	238	+#define MT6357_SCK_TOP_INT_MASK_CON0_SET 0x530
	239	+#define MT6357_SCK_TOP_INT_MASK_CON0_CLR 0x532
	240	+#define MT6357_SCK_TOP_INT_STATUS0 0x534
	241	+#define MT6357_SCK_TOP_INT_RAW_STATUS0 0x536
	242	+#define MT6357_SCK_TOP_INT_MISC_CON 0x538
	243	+#define MT6357_EOSC_CALI_CON0 0x53a
	244	+#define MT6357_EOSC_CALI_CON1 0x53c
	245	+#define MT6357_RTC_MIX_CON0 0x53e
	246	+#define MT6357_RTC_MIX_CON1 0x540
	247	+#define MT6357_RTC_MIX_CON2 0x542
	248	+#define MT6357_RTC_DSN_ID 0x580
	249	+#define MT6357_RTC_DSN_REV0 0x582
	250	+#define MT6357_RTC_DBI 0x584
	251	+#define MT6357_RTC_DXI 0x586
	252	+#define MT6357_RTC_BBPU 0x588
	253	+#define MT6357_RTC_IRQ_STA 0x58a
	254	+#define MT6357_RTC_IRQ_EN 0x58c
	255	+#define MT6357_RTC_CII_EN 0x58e
	256	+#define MT6357_RTC_AL_MASK 0x590
	257	+#define MT6357_RTC_TC_SEC 0x592
	258	+#define MT6357_RTC_TC_MIN 0x594
	259	+#define MT6357_RTC_TC_HOU 0x596
	260	+#define MT6357_RTC_TC_DOM 0x598
	261	+#define MT6357_RTC_TC_DOW 0x59a
	262	+#define MT6357_RTC_TC_MTH 0x59c
	263	+#define MT6357_RTC_TC_YEA 0x59e
	264	+#define MT6357_RTC_AL_SEC 0x5a0
	265	+#define MT6357_RTC_AL_MIN 0x5a2
	266	+#define MT6357_RTC_AL_HOU 0x5a4
	267	+#define MT6357_RTC_AL_DOM 0x5a6
	268	+#define MT6357_RTC_AL_DOW 0x5a8
	269	+#define MT6357_RTC_AL_MTH 0x5aa
	270	+#define MT6357_RTC_AL_YEA 0x5ac
	271	+#define MT6357_RTC_OSC32CON 0x5ae
	272	+#define MT6357_RTC_POWERKEY1 0x5b0
	273	+#define MT6357_RTC_POWERKEY2 0x5b2
	274	+#define MT6357_RTC_PDN1 0x5b4
	275	+#define MT6357_RTC_PDN2 0x5b6
	276	+#define MT6357_RTC_SPAR0 0x5b8
	277	+#define MT6357_RTC_SPAR1 0x5ba
	278	+#define MT6357_RTC_PROT 0x5bc
	279	+#define MT6357_RTC_DIFF 0x5be
	280	+#define MT6357_RTC_CALI 0x5c0
	281	+#define MT6357_RTC_WRTGR 0x5c2
	282	+#define MT6357_RTC_CON 0x5c4
	283	+#define MT6357_RTC_SEC_CTRL 0x5c6
	284	+#define MT6357_RTC_INT_CNT 0x5c8
	285	+#define MT6357_RTC_SEC_DAT0 0x5ca
	286	+#define MT6357_RTC_SEC_DAT1 0x5cc
	287	+#define MT6357_RTC_SEC_DAT2 0x5ce
	288	+#define MT6357_RTC_SEC_DSN_ID 0x600
	289	+#define MT6357_RTC_SEC_DSN_REV0 0x602
	290	+#define MT6357_RTC_SEC_DBI 0x604
	291	+#define MT6357_RTC_SEC_DXI 0x606
	292	+#define MT6357_RTC_TC_SEC_SEC 0x608
	293	+#define MT6357_RTC_TC_MIN_SEC 0x60a
	294	+#define MT6357_RTC_TC_HOU_SEC 0x60c
	295	+#define MT6357_RTC_TC_DOM_SEC 0x60e
	296	+#define MT6357_RTC_TC_DOW_SEC 0x610
	297	+#define MT6357_RTC_TC_MTH_SEC 0x612
	298	+#define MT6357_RTC_TC_YEA_SEC 0x614
	299	+#define MT6357_RTC_SEC_CK_PDN 0x616
	300	+#define MT6357_RTC_SEC_WRTGR 0x618
	301	+#define MT6357_DCXO_DSN_ID 0x780
	302	+#define MT6357_DCXO_DSN_REV0 0x782
	303	+#define MT6357_DCXO_DSN_DBI 0x784
	304	+#define MT6357_DCXO_DSN_DXI 0x786
	305	+#define MT6357_DCXO_CW00 0x788
	306	+#define MT6357_DCXO_CW00_SET 0x78a
	307	+#define MT6357_DCXO_CW00_CLR 0x78c
	308	+#define MT6357_DCXO_CW01 0x78e
	309	+#define MT6357_DCXO_CW02 0x790
	310	+#define MT6357_DCXO_CW03 0x792
	311	+#define MT6357_DCXO_CW04 0x794
	312	+#define MT6357_DCXO_CW05 0x796
	313	+#define MT6357_DCXO_CW06 0x798
	314	+#define MT6357_DCXO_CW07 0x79a
	315	+#define MT6357_DCXO_CW08 0x79c
	316	+#define MT6357_DCXO_CW09 0x79e
	317	+#define MT6357_DCXO_CW10 0x7a0
	318	+#define MT6357_DCXO_CW11 0x7a2
	319	+#define MT6357_DCXO_CW11_SET 0x7a4
	320	+#define MT6357_DCXO_CW11_CLR 0x7a6
	321	+#define MT6357_DCXO_CW12 0x7a8
	322	+#define MT6357_DCXO_CW13 0x7aa
	323	+#define MT6357_DCXO_CW14 0x7ac
	324	+#define MT6357_DCXO_CW15 0x7ae
	325	+#define MT6357_DCXO_CW16 0x7b0
	326	+#define MT6357_DCXO_CW17 0x7b2
	327	+#define MT6357_DCXO_CW18 0x7b4
	328	+#define MT6357_DCXO_CW19 0x7b6
	329	+#define MT6357_DCXO_CW20 0x7b8
	330	+#define MT6357_DCXO_CW21 0x7ba
	331	+#define MT6357_DCXO_CW22 0x7bc
	332	+#define MT6357_DCXO_ELR_NUM 0x7be
	333	+#define MT6357_DCXO_ELR0 0x7c0
	334	+#define MT6357_PSC_TOP_ID 0x900
	335	+#define MT6357_PSC_TOP_REV0 0x902
	336	+#define MT6357_PSC_TOP_DBI 0x904
	337	+#define MT6357_PSC_TOP_DXI 0x906
	338	+#define MT6357_PSC_TPM0 0x908
	339	+#define MT6357_PSC_TPM1 0x90a
	340	+#define MT6357_PSC_TOP_RSTCTL_0 0x90c
	341	+#define MT6357_PSC_TOP_INT_CON0 0x90e
	342	+#define MT6357_PSC_TOP_INT_CON0_SET 0x910
	343	+#define MT6357_PSC_TOP_INT_CON0_CLR 0x912
	344	+#define MT6357_PSC_TOP_INT_MASK_CON0 0x914
	345	+#define MT6357_PSC_TOP_INT_MASK_CON0_SET 0x916
	346	+#define MT6357_PSC_TOP_INT_MASK_CON0_CLR 0x918
	347	+#define MT6357_PSC_TOP_INT_STATUS0 0x91a
	348	+#define MT6357_PSC_TOP_INT_RAW_STATUS0 0x91c
	349	+#define MT6357_PSC_TOP_INT_MISC_CON 0x91e
	350	+#define MT6357_PSC_TOP_INT_MISC_CON_SET 0x920
	351	+#define MT6357_PSC_TOP_INT_MISC_CON_CLR 0x922
	352	+#define MT6357_PSC_TOP_MON_CTL 0x924
	353	+#define MT6357_STRUP_ID 0x980
	354	+#define MT6357_STRUP_REV0 0x982
	355	+#define MT6357_STRUP_DBI 0x984
	356	+#define MT6357_STRUP_DXI 0x986
	357	+#define MT6357_STRUP_ANA_CON0 0x988
	358	+#define MT6357_STRUP_ANA_CON1 0x98a
	359	+#define MT6357_STRUP_ANA_CON2 0x98c
	360	+#define MT6357_STRUP_ELR_NUM 0x98e
	361	+#define MT6357_STRUP_ELR_0 0x990
	362	+#define MT6357_PSEQ_ID 0xa00
	363	+#define MT6357_PSEQ_REV0 0xa02
	364	+#define MT6357_PSEQ_DBI 0xa04
	365	+#define MT6357_PSEQ_DXI 0xa06
	366	+#define MT6357_PPCCTL0 0xa08
	367	+#define MT6357_PPCCTL1 0xa0a
	368	+#define MT6357_PPCCTL2 0xa0c
	369	+#define MT6357_PPCCFG0 0xa0e
	370	+#define MT6357_PPCTST0 0xa10
	371	+#define MT6357_PORFLAG 0xa12
	372	+#define MT6357_STRUP_CON0 0xa14
	373	+#define MT6357_STRUP_CON1 0xa16
	374	+#define MT6357_STRUP_CON2 0xa18
	375	+#define MT6357_STRUP_CON3 0xa1a
	376	+#define MT6357_STRUP_CON4 0xa1c
	377	+#define MT6357_STRUP_CON5 0xa1e
	378	+#define MT6357_STRUP_CON6 0xa20
	379	+#define MT6357_STRUP_CON7 0xa22
	380	+#define MT6357_CPSCFG0 0xa24
	381	+#define MT6357_STRUP_CON9 0xa26
	382	+#define MT6357_STRUP_CON10 0xa28
	383	+#define MT6357_STRUP_CON11 0xa2a
	384	+#define MT6357_STRUP_CON12 0xa2c
	385	+#define MT6357_STRUP_CON13 0xa2e
	386	+#define MT6357_STRUP_CON14 0xa30
	387	+#define MT6357_STRUP_CON15 0xa32
	388	+#define MT6357_STRUP_CON16 0xa34
	389	+#define MT6357_STRUP_CON19 0xa36
	390	+#define MT6357_PSEQ_ELR_NUM 0xa38
	391	+#define MT6357_PSEQ_ELR7 0xa3a
	392	+#define MT6357_PSEQ_ELR8 0xa3c
	393	+#define MT6357_PCHR_DIG_DSN_ID 0xa80
	394	+#define MT6357_PCHR_DIG_DSN_REV0 0xa82
	395	+#define MT6357_PCHR_DIG_DSN_DBI 0xa84
	396	+#define MT6357_PCHR_DIG_DSN_DXI 0xa86
	397	+#define MT6357_CHR_TOP_CON0 0xa88
	398	+#define MT6357_CHR_TOP_CON1 0xa8a
	399	+#define MT6357_CHR_TOP_CON2 0xa8c
	400	+#define MT6357_CHR_TOP_CON3 0xa8e
	401	+#define MT6357_CHR_TOP_CON4 0xa90
	402	+#define MT6357_CHR_TOP_CON5 0xa92
	403	+#define MT6357_CHR_TOP_CON6 0xa94
	404	+#define MT6357_PCHR_DIG_ELR_NUM 0xa96
	405	+#define MT6357_PCHR_ELR0 0xa98
	406	+#define MT6357_PCHR_ELR1 0xa9a
	407	+#define MT6357_PCHR_MACRO_DSN_ID 0xb80
	408	+#define MT6357_PCHR_MACRO_DSN_REV0 0xb82
	409	+#define MT6357_PCHR_MACRO_DSN_DBI 0xb84
	410	+#define MT6357_PCHR_MACRO_DSN_DXI 0xb86
	411	+#define MT6357_CHR_CON0 0xb88
	412	+#define MT6357_CHR_CON1 0xb8a
	413	+#define MT6357_CHR_CON2 0xb8c
	414	+#define MT6357_CHR_CON3 0xb8e
	415	+#define MT6357_CHR_CON4 0xb90
	416	+#define MT6357_CHR_CON5 0xb92
	417	+#define MT6357_CHR_CON6 0xb94
	418	+#define MT6357_CHR_CON7 0xb96
	419	+#define MT6357_CHR_CON8 0xb98
	420	+#define MT6357_CHR_CON9 0xb9a
	421	+#define MT6357_BM_TOP_DSN_ID 0xc00
	422	+#define MT6357_BM_TOP_DSN_REV0 0xc02
	423	+#define MT6357_BM_TOP_DBI 0xc04
	424	+#define MT6357_BM_TOP_DXI 0xc06
	425	+#define MT6357_BM_TPM0 0xc08
	426	+#define MT6357_BM_TPM1 0xc0a
	427	+#define MT6357_BM_TOP_CKPDN_CON0 0xc0c
	428	+#define MT6357_BM_TOP_CKPDN_CON0_SET 0xc0e
	429	+#define MT6357_BM_TOP_CKPDN_CON0_CLR 0xc10
	430	+#define MT6357_BM_TOP_CKSEL_CON0 0xc12
	431	+#define MT6357_BM_TOP_CKSEL_CON0_SET 0xc14
	432	+#define MT6357_BM_TOP_CKSEL_CON0_CLR 0xc16
	433	+#define MT6357_BM_TOP_CKTST_CON0 0xc18
	434	+#define MT6357_BM_TOP_RST_CON0 0xc1a
	435	+#define MT6357_BM_TOP_RST_CON0_SET 0xc1c
	436	+#define MT6357_BM_TOP_RST_CON0_CLR 0xc1e
	437	+#define MT6357_BM_TOP_INT_CON0 0xc20
	438	+#define MT6357_BM_TOP_INT_CON0_SET 0xc22
	439	+#define MT6357_BM_TOP_INT_CON0_CLR 0xc24
	440	+#define MT6357_BM_TOP_INT_CON1 0xc26
	441	+#define MT6357_BM_TOP_INT_CON1_SET 0xc28
	442	+#define MT6357_BM_TOP_INT_CON1_CLR 0xc2a
	443	+#define MT6357_BM_TOP_INT_MASK_CON0 0xc2c
	444	+#define MT6357_BM_TOP_INT_MASK_CON0_SET 0xc2e
	445	+#define MT6357_BM_TOP_INT_MASK_CON0_CLR 0xc30
	446	+#define MT6357_BM_TOP_INT_MASK_CON1 0xc32
	447	+#define MT6357_BM_TOP_INT_MASK_CON1_SET 0xc34
	448	+#define MT6357_BM_TOP_INT_MASK_CON1_CLR 0xc36
	449	+#define MT6357_BM_TOP_INT_STATUS0 0xc38
	450	+#define MT6357_BM_TOP_INT_STATUS1 0xc3a
	451	+#define MT6357_BM_TOP_INT_RAW_STATUS0 0xc3c
	452	+#define MT6357_BM_TOP_INT_RAW_STATUS1 0xc3e
	453	+#define MT6357_BM_TOP_INT_MISC_CON 0xc40
	454	+#define MT6357_BM_TOP_DBG_CON 0xc42
	455	+#define MT6357_BM_TOP_RSV0 0xc44
	456	+#define MT6357_FGADC_ANA_DSN_ID 0xc80
	457	+#define MT6357_FGADC_ANA_DSN_REV0 0xc82
	458	+#define MT6357_FGADC_ANA_DSN_DBI 0xc84
	459	+#define MT6357_FGADC_ANA_DSN_DXI 0xc86
	460	+#define MT6357_FGADC_ANA_CON0 0xc88
	461	+#define MT6357_FGADC_ANA_TEST_CON0 0xc8a
	462	+#define MT6357_FGADC_ANA_ELR_NUM 0xc8c
	463	+#define MT6357_FGADC_ANA_ELR0 0xc8e
	464	+#define MT6357_FGADC_ANA_ELR1 0xc90
	465	+#define MT6357_FGADC0_DSN_ID 0xd00
	466	+#define MT6357_FGADC0_DSN_REV0 0xd02
	467	+#define MT6357_FGADC0_DSN_DBI 0xd04
	468	+#define MT6357_FGADC0_DSN_DXI 0xd06
	469	+#define MT6357_FGADC_CON0 0xd08
	470	+#define MT6357_FGADC_CON1 0xd0a
	471	+#define MT6357_FGADC_CON2 0xd0c
	472	+#define MT6357_FGADC_CON3 0xd0e
	473	+#define MT6357_FGADC_CON4 0xd10
	474	+#define MT6357_FGADC_CAR_CON0 0xd12
	475	+#define MT6357_FGADC_CAR_CON1 0xd14
	476	+#define MT6357_FGADC_CAR_CON2 0xd16
	477	+#define MT6357_FGADC_CARTH_CON0 0xd18
	478	+#define MT6357_FGADC_CARTH_CON1 0xd1a
	479	+#define MT6357_FGADC_CARTH_CON2 0xd1c
	480	+#define MT6357_FGADC_CARTH_CON3 0xd1e
	481	+#define MT6357_FGADC_NTER_CON0 0xd20
	482	+#define MT6357_FGADC_NTER_CON1 0xd22
	483	+#define MT6357_FGADC_NTER_CON2 0xd24
	484	+#define MT6357_FGADC_SON_CON0 0xd26
	485	+#define MT6357_FGADC_SON_CON1 0xd28
	486	+#define MT6357_FGADC_SON_CON2 0xd2a
	487	+#define MT6357_FGADC_SON_CON3 0xd2c
	488	+#define MT6357_FGADC_ZCV_CON0 0xd2e
	489	+#define MT6357_FGADC_ZCV_CON1 0xd30
	490	+#define MT6357_FGADC_ZCV_CON2 0xd32
	491	+#define MT6357_FGADC_ZCV_CON3 0xd34
	492	+#define MT6357_FGADC_ZCV_CON4 0xd36
	493	+#define MT6357_FGADC_ZCVTH_CON0 0xd38
	494	+#define MT6357_FGADC_ZCVTH_CON1 0xd3a
	495	+#define MT6357_FGADC_ZCVTH_CON2 0xd3c
	496	+#define MT6357_FGADC1_DSN_ID 0xd80
	497	+#define MT6357_FGADC1_DSN_REV0 0xd82
	498	+#define MT6357_FGADC1_DSN_DBI 0xd84
	499	+#define MT6357_FGADC1_DSN_DXI 0xd86
	500	+#define MT6357_FGADC_R_CON0 0xd88
	501	+#define MT6357_FGADC_CUR_CON0 0xd8a
	502	+#define MT6357_FGADC_CUR_CON1 0xd8c
	503	+#define MT6357_FGADC_CUR_CON2 0xd8e
	504	+#define MT6357_FGADC_CUR_CON3 0xd90
	505	+#define MT6357_FGADC_OFFSET_CON0 0xd92
	506	+#define MT6357_FGADC_OFFSET_CON1 0xd94
	507	+#define MT6357_FGADC_GAIN_CON0 0xd96
	508	+#define MT6357_FGADC_TEST_CON0 0xd98
	509	+#define MT6357_SYSTEM_INFO_CON0 0xd9a
	510	+#define MT6357_SYSTEM_INFO_CON1 0xd9c
	511	+#define MT6357_SYSTEM_INFO_CON2 0xd9e
	512	+#define MT6357_SYSTEM_INFO_CON3 0xda0
	513	+#define MT6357_SYSTEM_INFO_CON4 0xda2
	514	+#define MT6357_BATON_ANA_DSN_ID 0xe00
	515	+#define MT6357_BATON_ANA_DSN_REV0 0xe02
	516	+#define MT6357_BATON_ANA_DSN_DBI 0xe04
	517	+#define MT6357_BATON_ANA_DSN_DXI 0xe06
	518	+#define MT6357_BATON_ANA_CON0 0xe08
	519	+#define MT6357_BATON_ANA_ELR_NUM 0xe0a
	520	+#define MT6357_BATON_ANA_ELR0 0xe0c
	521	+#define MT6357_HK_TOP_ID 0xf80
	522	+#define MT6357_HK_TOP_REV0 0xf82
	523	+#define MT6357_HK_TOP_DBI 0xf84
	524	+#define MT6357_HK_TOP_DXI 0xf86
	525	+#define MT6357_HK_TPM0 0xf88
	526	+#define MT6357_HK_TPM1 0xf8a
	527	+#define MT6357_HK_TOP_CLK_CON0 0xf8c
	528	+#define MT6357_HK_TOP_CLK_CON1 0xf8e
	529	+#define MT6357_HK_TOP_RST_CON0 0xf90
	530	+#define MT6357_HK_TOP_INT_CON0 0xf92
	531	+#define MT6357_HK_TOP_INT_CON0_SET 0xf94
	532	+#define MT6357_HK_TOP_INT_CON0_CLR 0xf96
	533	+#define MT6357_HK_TOP_INT_MASK_CON0 0xf98
	534	+#define MT6357_HK_TOP_INT_MASK_CON0_SET 0xf9a
	535	+#define MT6357_HK_TOP_INT_MASK_CON0_CLR 0xf9c
	536	+#define MT6357_HK_TOP_INT_STATUS0 0xf9e
	537	+#define MT6357_HK_TOP_INT_RAW_STATUS0 0xfa0
	538	+#define MT6357_HK_TOP_MON_CON0 0xfa2
	539	+#define MT6357_HK_TOP_MON_CON1 0xfa4
	540	+#define MT6357_HK_TOP_MON_CON2 0xfa6
	541	+#define MT6357_AUXADC_DSN_ID 0x1000
	542	+#define MT6357_AUXADC_DSN_REV0 0x1002
	543	+#define MT6357_AUXADC_DSN_DBI 0x1004
	544	+#define MT6357_AUXADC_DSN_DXI 0x1006
	545	+#define MT6357_AUXADC_ANA_CON0 0x1008
	546	+#define MT6357_AUXADC_DIG_1_DSN_ID 0x1080
	547	+#define MT6357_AUXADC_DIG_1_DSN_REV0 0x1082
	548	+#define MT6357_AUXADC_DIG_1_DSN_DBI 0x1084
	549	+#define MT6357_AUXADC_DIG_1_DSN_DXI 0x1086
	550	+#define MT6357_AUXADC_ADC0 0x1088
	551	+#define MT6357_AUXADC_ADC1 0x108a
	552	+#define MT6357_AUXADC_ADC2 0x108c
	553	+#define MT6357_AUXADC_ADC3 0x108e
	554	+#define MT6357_AUXADC_ADC4 0x1090
	555	+#define MT6357_AUXADC_ADC5 0x1092
	556	+#define MT6357_AUXADC_ADC6 0x1094
	557	+#define MT6357_AUXADC_ADC7 0x1096
	558	+#define MT6357_AUXADC_ADC8 0x1098
	559	+#define MT6357_AUXADC_ADC9 0x109a
	560	+#define MT6357_AUXADC_ADC10 0x109c
	561	+#define MT6357_AUXADC_ADC11 0x109e
	562	+#define MT6357_AUXADC_ADC12 0x10a0
	563	+#define MT6357_AUXADC_ADC14 0x10a2
	564	+#define MT6357_AUXADC_ADC16 0x10a4
	565	+#define MT6357_AUXADC_ADC17 0x10a6
	566	+#define MT6357_AUXADC_ADC18 0x10a8
	567	+#define MT6357_AUXADC_ADC19 0x10aa
	568	+#define MT6357_AUXADC_ADC20 0x10ac
	569	+#define MT6357_AUXADC_ADC21 0x10ae
	570	+#define MT6357_AUXADC_ADC22 0x10b0
	571	+#define MT6357_AUXADC_ADC23 0x10b2
	572	+#define MT6357_AUXADC_ADC24 0x10b4
	573	+#define MT6357_AUXADC_ADC25 0x10b6
	574	+#define MT6357_AUXADC_ADC26 0x10b8
	575	+#define MT6357_AUXADC_ADC27 0x10ba
	576	+#define MT6357_AUXADC_ADC29 0x10bc
	577	+#define MT6357_AUXADC_ADC30 0x10be
	578	+#define MT6357_AUXADC_ADC31 0x10c0
	579	+#define MT6357_AUXADC_ADC32 0x10c2
	580	+#define MT6357_AUXADC_ADC33 0x10c4
	581	+#define MT6357_AUXADC_ADC34 0x10c6
	582	+#define MT6357_AUXADC_ADC35 0x10c8
	583	+#define MT6357_AUXADC_ADC36 0x10ca
	584	+#define MT6357_AUXADC_ADC38 0x10cc
	585	+#define MT6357_AUXADC_ADC39 0x10ce
	586	+#define MT6357_AUXADC_ADC40 0x10d0
	587	+#define MT6357_AUXADC_ADC41 0x10d2
	588	+#define MT6357_AUXADC_ADC42 0x10d4
	589	+#define MT6357_AUXADC_ADC43 0x10d6
	590	+#define MT6357_AUXADC_ADC46 0x10d8
	591	+#define MT6357_AUXADC_ADC47 0x10da
	592	+#define MT6357_AUXADC_DIG_1_ELR_NUM 0x10dc
	593	+#define MT6357_AUXADC_DIG_1_ELR0 0x10de
	594	+#define MT6357_AUXADC_DIG_1_ELR1 0x10e0
	595	+#define MT6357_AUXADC_DIG_2_DSN_ID 0x1100
	596	+#define MT6357_AUXADC_DIG_2_DSN_REV0 0x1102
	597	+#define MT6357_AUXADC_DIG_2_DSN_DBI 0x1104
	598	+#define MT6357_AUXADC_DIG_2_DSN_DXI 0x1106
	599	+#define MT6357_AUXADC_STA0 0x1108
	600	+#define MT6357_AUXADC_STA1 0x110a
	601	+#define MT6357_AUXADC_STA2 0x110c
	602	+#define MT6357_AUXADC_RQST0 0x110e
	603	+#define MT6357_AUXADC_RQST0_SET 0x1110
	604	+#define MT6357_AUXADC_RQST0_CLR 0x1112
	605	+#define MT6357_AUXADC_RQST2 0x1114
	606	+#define MT6357_AUXADC_RQST2_SET 0x1116
	607	+#define MT6357_AUXADC_RQST2_CLR 0x1118
	608	+#define MT6357_AUXADC_RQST1 0x111a
	609	+#define MT6357_AUXADC_RQST1_SET 0x111c
	610	+#define MT6357_AUXADC_RQST1_CLR 0x111e
	611	+#define MT6357_AUXADC_CON0 0x1120
	612	+#define MT6357_AUXADC_CON0_SET 0x1122
	613	+#define MT6357_AUXADC_CON0_CLR 0x1124
	614	+#define MT6357_AUXADC_CON1 0x1126
	615	+#define MT6357_AUXADC_CON2 0x1128
	616	+#define MT6357_AUXADC_CON3 0x112a
	617	+#define MT6357_AUXADC_CON4 0x112c
	618	+#define MT6357_AUXADC_CON5 0x112e
	619	+#define MT6357_AUXADC_CON6 0x1130
	620	+#define MT6357_AUXADC_CON7 0x1132
	621	+#define MT6357_AUXADC_CON8 0x1134
	622	+#define MT6357_AUXADC_CON9 0x1136
	623	+#define MT6357_AUXADC_CON10 0x1138
	624	+#define MT6357_AUXADC_CON11 0x113a
	625	+#define MT6357_AUXADC_CON12 0x113c
	626	+#define MT6357_AUXADC_CON13 0x113e
	627	+#define MT6357_AUXADC_CON14 0x1140
	628	+#define MT6357_AUXADC_CON15 0x1142
	629	+#define MT6357_AUXADC_CON16 0x1144
	630	+#define MT6357_AUXADC_CON17 0x1146
	631	+#define MT6357_AUXADC_CON18 0x1148
	632	+#define MT6357_AUXADC_CON19 0x114a
	633	+#define MT6357_AUXADC_CON20 0x114c
	634	+#define MT6357_AUXADC_DIG_3_DSN_ID 0x1180
	635	+#define MT6357_AUXADC_DIG_3_DSN_REV0 0x1182
	636	+#define MT6357_AUXADC_DIG_3_DSN_DBI 0x1184
	637	+#define MT6357_AUXADC_DIG_3_DSN_DXI 0x1186
	638	+#define MT6357_AUXADC_AUTORPT0 0x1188
	639	+#define MT6357_AUXADC_LBAT0 0x118a
	640	+#define MT6357_AUXADC_LBAT1 0x118c
	641	+#define MT6357_AUXADC_LBAT2 0x118e
	642	+#define MT6357_AUXADC_LBAT3 0x1190
	643	+#define MT6357_AUXADC_LBAT4 0x1192
	644	+#define MT6357_AUXADC_LBAT5 0x1194
	645	+#define MT6357_AUXADC_LBAT6 0x1196
	646	+#define MT6357_AUXADC_ACCDET 0x1198
	647	+#define MT6357_AUXADC_DBG0 0x119a
	648	+#define MT6357_AUXADC_IMP0 0x119c
	649	+#define MT6357_AUXADC_IMP1 0x119e
	650	+#define MT6357_AUXADC_DIG_3_ELR_NUM 0x11a0
	651	+#define MT6357_AUXADC_DIG_3_ELR0 0x11a2
	652	+#define MT6357_AUXADC_DIG_3_ELR1 0x11a4
	653	+#define MT6357_AUXADC_DIG_3_ELR2 0x11a6
	654	+#define MT6357_AUXADC_DIG_3_ELR3 0x11a8
	655	+#define MT6357_AUXADC_DIG_3_ELR4 0x11aa
	656	+#define MT6357_AUXADC_DIG_3_ELR5 0x11ac
	657	+#define MT6357_AUXADC_DIG_3_ELR6 0x11ae
	658	+#define MT6357_AUXADC_DIG_3_ELR7 0x11b0
	659	+#define MT6357_AUXADC_DIG_3_ELR8 0x11b2
	660	+#define MT6357_AUXADC_DIG_3_ELR9 0x11b4
	661	+#define MT6357_AUXADC_DIG_3_ELR10 0x11b6
	662	+#define MT6357_AUXADC_DIG_3_ELR11 0x11b8
	663	+#define MT6357_AUXADC_DIG_4_DSN_ID 0x1200
	664	+#define MT6357_AUXADC_DIG_4_DSN_REV0 0x1202
	665	+#define MT6357_AUXADC_DIG_4_DSN_DBI 0x1204
	666	+#define MT6357_AUXADC_DIG_4_DSN_DXI 0x1206
	667	+#define MT6357_AUXADC_MDRT_0 0x1208
	668	+#define MT6357_AUXADC_MDRT_1 0x120a
	669	+#define MT6357_AUXADC_MDRT_2 0x120c
	670	+#define MT6357_AUXADC_MDRT_3 0x120e
	671	+#define MT6357_AUXADC_MDRT_4 0x1210
	672	+#define MT6357_AUXADC_DCXO_MDRT_0 0x1212
	673	+#define MT6357_AUXADC_DCXO_MDRT_1 0x1214
	674	+#define MT6357_AUXADC_DCXO_MDRT_2 0x1216
	675	+#define MT6357_AUXADC_NAG_0 0x1218
	676	+#define MT6357_AUXADC_NAG_1 0x121a
	677	+#define MT6357_AUXADC_NAG_2 0x121c
	678	+#define MT6357_AUXADC_NAG_3 0x121e
	679	+#define MT6357_AUXADC_NAG_4 0x1220
	680	+#define MT6357_AUXADC_NAG_5 0x1222
	681	+#define MT6357_AUXADC_NAG_6 0x1224
	682	+#define MT6357_AUXADC_NAG_7 0x1226
	683	+#define MT6357_AUXADC_NAG_8 0x1228
	684	+#define MT6357_AUXADC_RSV_1 0x122a
	685	+#define MT6357_AUXADC_ANA_0 0x122c
	686	+#define MT6357_AUXADC_IMP_CG0 0x122e
	687	+#define MT6357_AUXADC_LBAT_CG0 0x1230
	688	+#define MT6357_AUXADC_NAG_CG0 0x1232
	689	+#define MT6357_AUXADC_PRI_NEW 0x1234
	690	+#define MT6357_AUXADC_CHR_TOP_CON2 0x1236
	691	+#define MT6357_BUCK_TOP_DSN_ID 0x1400
	692	+#define MT6357_BUCK_TOP_DSN_REV0 0x1402
	693	+#define MT6357_BUCK_TOP_DBI 0x1404
	694	+#define MT6357_BUCK_TOP_DXI 0x1406
	695	+#define MT6357_BUCK_TOP_PAM0 0x1408
	696	+#define MT6357_BUCK_TOP_PAM1 0x140a
	697	+#define MT6357_BUCK_TOP_CLK_CON0 0x140c
	698	+#define MT6357_BUCK_TOP_CLK_CON0_SET 0x140e
	699	+#define MT6357_BUCK_TOP_CLK_CON0_CLR 0x1410
	700	+#define MT6357_BUCK_TOP_CLK_HWEN_CON0 0x1412
	701	+#define MT6357_BUCK_TOP_CLK_HWEN_CON0_SET 0x1414
	702	+#define MT6357_BUCK_TOP_CLK_HWEN_CON0_CLR 0x1416
	703	+#define MT6357_BUCK_TOP_CLK_MISC_CON0 0x1418
	704	+#define MT6357_BUCK_TOP_INT_CON0 0x141a
	705	+#define MT6357_BUCK_TOP_INT_CON0_SET 0x141c
	706	+#define MT6357_BUCK_TOP_INT_CON0_CLR 0x141e
	707	+#define MT6357_BUCK_TOP_INT_MASK_CON0 0x1420
	708	+#define MT6357_BUCK_TOP_INT_MASK_CON0_SET 0x1422
	709	+#define MT6357_BUCK_TOP_INT_MASK_CON0_CLR 0x1424
	710	+#define MT6357_BUCK_TOP_INT_STATUS0 0x1426
	711	+#define MT6357_BUCK_TOP_INT_RAW_STATUS0 0x1428
	712	+#define MT6357_BUCK_TOP_STB_CON 0x142a
	713	+#define MT6357_BUCK_TOP_SLP_CON0 0x142c
	714	+#define MT6357_BUCK_TOP_SLP_CON1 0x142e
	715	+#define MT6357_BUCK_TOP_SLP_CON2 0x1430
	716	+#define MT6357_BUCK_TOP_MINFREQ_CON 0x1432
	717	+#define MT6357_BUCK_TOP_OC_CON0 0x1434
	718	+#define MT6357_BUCK_TOP_K_CON0 0x1436
	719	+#define MT6357_BUCK_TOP_K_CON1 0x1438
	720	+#define MT6357_BUCK_TOP_K_CON2 0x143a
	721	+#define MT6357_BUCK_TOP_WDTDBG0 0x143c
	722	+#define MT6357_BUCK_TOP_WDTDBG1 0x143e
	723	+#define MT6357_BUCK_TOP_WDTDBG2 0x1440
	724	+#define MT6357_BUCK_TOP_ELR_NUM 0x1442
	725	+#define MT6357_BUCK_TOP_ELR0 0x1444
	726	+#define MT6357_BUCK_TOP_ELR1 0x1446
	727	+#define MT6357_BUCK_VPROC_DSN_ID 0x1480
	728	+#define MT6357_BUCK_VPROC_DSN_REV0 0x1482
	729	+#define MT6357_BUCK_VPROC_DSN_DBI 0x1484
	730	+#define MT6357_BUCK_VPROC_DSN_DXI 0x1486
	731	+#define MT6357_BUCK_VPROC_CON0 0x1488
	732	+#define MT6357_BUCK_VPROC_CON1 0x148a
	733	+#define MT6357_BUCK_VPROC_CFG0 0x148c
	734	+#define MT6357_BUCK_VPROC_CFG1 0x148e
	735	+#define MT6357_BUCK_VPROC_OP_EN 0x1490
	736	+#define MT6357_BUCK_VPROC_OP_EN_SET 0x1492
	737	+#define MT6357_BUCK_VPROC_OP_EN_CLR 0x1494
	738	+#define MT6357_BUCK_VPROC_OP_CFG 0x1496
	739	+#define MT6357_BUCK_VPROC_OP_CFG_SET 0x1498
	740	+#define MT6357_BUCK_VPROC_OP_CFG_CLR 0x149a
	741	+#define MT6357_BUCK_VPROC_SP_CON 0x149c
	742	+#define MT6357_BUCK_VPROC_SP_CFG 0x149e
	743	+#define MT6357_BUCK_VPROC_OC_CFG 0x14a0
	744	+#define MT6357_BUCK_VPROC_DBG0 0x14a2
	745	+#define MT6357_BUCK_VPROC_DBG1 0x14a4
	746	+#define MT6357_BUCK_VPROC_DBG2 0x14a6
	747	+#define MT6357_BUCK_VPROC_ELR_NUM 0x14a8
	748	+#define MT6357_BUCK_VPROC_ELR0 0x14aa
	749	+#define MT6357_BUCK_VCORE_DSN_ID 0x1500
	750	+#define MT6357_BUCK_VCORE_DSN_REV0 0x1502
	751	+#define MT6357_BUCK_VCORE_DSN_DBI 0x1504
	752	+#define MT6357_BUCK_VCORE_DSN_DXI 0x1506
	753	+#define MT6357_BUCK_VCORE_CON0 0x1508
	754	+#define MT6357_BUCK_VCORE_CON1 0x150a
	755	+#define MT6357_BUCK_VCORE_CFG0 0x150c
	756	+#define MT6357_BUCK_VCORE_CFG1 0x150e
	757	+#define MT6357_BUCK_VCORE_OP_EN 0x1510
	758	+#define MT6357_BUCK_VCORE_OP_EN_SET 0x1512
	759	+#define MT6357_BUCK_VCORE_OP_EN_CLR 0x1514
	760	+#define MT6357_BUCK_VCORE_OP_CFG 0x1516
	761	+#define MT6357_BUCK_VCORE_OP_CFG_SET 0x1518
	762	+#define MT6357_BUCK_VCORE_OP_CFG_CLR 0x151a
	763	+#define MT6357_BUCK_VCORE_SP_CON 0x151c
	764	+#define MT6357_BUCK_VCORE_SP_CFG 0x151e
	765	+#define MT6357_BUCK_VCORE_OC_CFG 0x1520
	766	+#define MT6357_BUCK_VCORE_DBG0 0x1522
	767	+#define MT6357_BUCK_VCORE_DBG1 0x1524
	768	+#define MT6357_BUCK_VCORE_DBG2 0x1526
	769	+#define MT6357_BUCK_VCORE_ELR_NUM 0x1528
	770	+#define MT6357_BUCK_VCORE_ELR0 0x152a
	771	+#define MT6357_BUCK_VMODEM_DSN_ID 0x1580
	772	+#define MT6357_BUCK_VMODEM_DSN_REV0 0x1582
	773	+#define MT6357_BUCK_VMODEM_DSN_DBI 0x1584
	774	+#define MT6357_BUCK_VMODEM_DSN_DXI 0x1586
	775	+#define MT6357_BUCK_VMODEM_CON0 0x1588
	776	+#define MT6357_BUCK_VMODEM_CON1 0x158a
	777	+#define MT6357_BUCK_VMODEM_CFG0 0x158c
	778	+#define MT6357_BUCK_VMODEM_CFG1 0x158e
	779	+#define MT6357_BUCK_VMODEM_OP_EN 0x1590
	780	+#define MT6357_BUCK_VMODEM_OP_EN_SET 0x1592
	781	+#define MT6357_BUCK_VMODEM_OP_EN_CLR 0x1594
	782	+#define MT6357_BUCK_VMODEM_OP_CFG 0x1596
	783	+#define MT6357_BUCK_VMODEM_OP_CFG_SET 0x1598
	784	+#define MT6357_BUCK_VMODEM_OP_CFG_CLR 0x159a
	785	+#define MT6357_BUCK_VMODEM_SP_CON 0x159c
	786	+#define MT6357_BUCK_VMODEM_SP_CFG 0x159e
	787	+#define MT6357_BUCK_VMODEM_OC_CFG 0x15a0
	788	+#define MT6357_BUCK_VMODEM_DBG0 0x15a2
	789	+#define MT6357_BUCK_VMODEM_DBG1 0x15a4
	790	+#define MT6357_BUCK_VMODEM_DBG2 0x15a6
	791	+#define MT6357_BUCK_VMODEM_ELR_NUM 0x15a8
	792	+#define MT6357_BUCK_VMODEM_ELR0 0x15aa
	793	+#define MT6357_BUCK_VS1_DSN_ID 0x1600
	794	+#define MT6357_BUCK_VS1_DSN_REV0 0x1602
	795	+#define MT6357_BUCK_VS1_DSN_DBI 0x1604
	796	+#define MT6357_BUCK_VS1_DSN_DXI 0x1606
	797	+#define MT6357_BUCK_VS1_CON0 0x1608
	798	+#define MT6357_BUCK_VS1_CON1 0x160a
	799	+#define MT6357_BUCK_VS1_CFG0 0x160c
	800	+#define MT6357_BUCK_VS1_CFG1 0x160e
	801	+#define MT6357_BUCK_VS1_OP_EN 0x1610
	802	+#define MT6357_BUCK_VS1_OP_EN_SET 0x1612
	803	+#define MT6357_BUCK_VS1_OP_EN_CLR 0x1614
	804	+#define MT6357_BUCK_VS1_OP_CFG 0x1616
	805	+#define MT6357_BUCK_VS1_OP_CFG_SET 0x1618
	806	+#define MT6357_BUCK_VS1_OP_CFG_CLR 0x161a
	807	+#define MT6357_BUCK_VS1_SP_CON 0x161c
	808	+#define MT6357_BUCK_VS1_SP_CFG 0x161e
	809	+#define MT6357_BUCK_VS1_OC_CFG 0x1620
	810	+#define MT6357_BUCK_VS1_DBG0 0x1622
	811	+#define MT6357_BUCK_VS1_DBG1 0x1624
	812	+#define MT6357_BUCK_VS1_DBG2 0x1626
	813	+#define MT6357_BUCK_VS1_VOTER 0x1628
	814	+#define MT6357_BUCK_VS1_VOTER_SET 0x162a
	815	+#define MT6357_BUCK_VS1_VOTER_CLR 0x162c
	816	+#define MT6357_BUCK_VS1_VOTER_CFG 0x162e
	817	+#define MT6357_BUCK_VS1_ELR_NUM 0x1630
	818	+#define MT6357_BUCK_VS1_ELR0 0x1632
	819	+#define MT6357_BUCK_VPA_DSN_ID 0x1680
	820	+#define MT6357_BUCK_VPA_DSN_REV0 0x1682
	821	+#define MT6357_BUCK_VPA_DSN_DBI 0x1684
	822	+#define MT6357_BUCK_VPA_DSN_DXI 0x1686
	823	+#define MT6357_BUCK_VPA_CON0 0x1688
	824	+#define MT6357_BUCK_VPA_CON1 0x168a
	825	+#define MT6357_BUCK_VPA_CFG0 0x168c
	826	+#define MT6357_BUCK_VPA_CFG1 0x168e
	827	+#define MT6357_BUCK_VPA_OC_CFG 0x1690
	828	+#define MT6357_BUCK_VPA_DBG0 0x1692
	829	+#define MT6357_BUCK_VPA_DBG1 0x1694
	830	+#define MT6357_BUCK_VPA_DBG2 0x1696
	831	+#define MT6357_BUCK_VPA_DLC_CON0 0x1698
	832	+#define MT6357_BUCK_VPA_DLC_CON1 0x169a
	833	+#define MT6357_BUCK_VPA_DLC_CON2 0x169c
	834	+#define MT6357_BUCK_VPA_MSFG_CON0 0x169e
	835	+#define MT6357_BUCK_VPA_MSFG_CON1 0x16a0
	836	+#define MT6357_BUCK_VPA_MSFG_RRATE0 0x16a2
	837	+#define MT6357_BUCK_VPA_MSFG_RRATE1 0x16a4
	838	+#define MT6357_BUCK_VPA_MSFG_RRATE2 0x16a6
	839	+#define MT6357_BUCK_VPA_MSFG_RTHD0 0x16a8
	840	+#define MT6357_BUCK_VPA_MSFG_RTHD1 0x16aa
	841	+#define MT6357_BUCK_VPA_MSFG_RTHD2 0x16ac
	842	+#define MT6357_BUCK_VPA_MSFG_FRATE0 0x16ae
	843	+#define MT6357_BUCK_VPA_MSFG_FRATE1 0x16b0
	844	+#define MT6357_BUCK_VPA_MSFG_FRATE2 0x16b2
	845	+#define MT6357_BUCK_VPA_MSFG_FTHD0 0x16b4
	846	+#define MT6357_BUCK_VPA_MSFG_FTHD1 0x16b6
	847	+#define MT6357_BUCK_VPA_MSFG_FTHD2 0x16b8
	848	+#define MT6357_BUCK_ANA_DSN_ID 0x1700
	849	+#define MT6357_BUCK_ANA_DSN_REV0 0x1702
	850	+#define MT6357_BUCK_ANA_DSN_DBI 0x1704
	851	+#define MT6357_BUCK_ANA_DSN_FPI 0x1706
	852	+#define MT6357_SMPS_ANA_CON0 0x1708
	853	+#define MT6357_SMPS_ANA_CON1 0x170a
	854	+#define MT6357_SMPS_ANA_CON2 0x170c
	855	+#define MT6357_VCORE_VPROC_ANA_CON0 0x170e
	856	+#define MT6357_VCORE_VPROC_ANA_CON1 0x1710
	857	+#define MT6357_VCORE_VPROC_ANA_CON2 0x1712
	858	+#define MT6357_VCORE_VPROC_ANA_CON3 0x1714
	859	+#define MT6357_VCORE_VPROC_ANA_CON4 0x1716
	860	+#define MT6357_VCORE_VPROC_ANA_CON5 0x1718
	861	+#define MT6357_VCORE_VPROC_ANA_CON6 0x171a
	862	+#define MT6357_VCORE_VPROC_ANA_CON7 0x171c
	863	+#define MT6357_VCORE_VPROC_ANA_CON8 0x171e
	864	+#define MT6357_VCORE_VPROC_ANA_CON9 0x1720
	865	+#define MT6357_VCORE_VPROC_ANA_CON10 0x1722
	866	+#define MT6357_VCORE_VPROC_ANA_CON11 0x1724
	867	+#define MT6357_VMODEM_ANA_CON0 0x1726
	868	+#define MT6357_VMODEM_ANA_CON1 0x1728
	869	+#define MT6357_VMODEM_ANA_CON2 0x172a
	870	+#define MT6357_VMODEM_ANA_CON3 0x172c
	871	+#define MT6357_VMODEM_ANA_CON4 0x172e
	872	+#define MT6357_VMODEM_ANA_CON5 0x1730
	873	+#define MT6357_VS1_ANA_CON0 0x1732
	874	+#define MT6357_VS1_ANA_CON1 0x1734
	875	+#define MT6357_VS1_ANA_CON2 0x1736
	876	+#define MT6357_VS1_ANA_CON3 0x1738
	877	+#define MT6357_VS1_ANA_CON4 0x173a
	878	+#define MT6357_VS1_ANA_CON5 0x173c
	879	+#define MT6357_VPA_ANA_CON0 0x173e
	880	+#define MT6357_VPA_ANA_CON1 0x1740
	881	+#define MT6357_VPA_ANA_CON2 0x1742
	882	+#define MT6357_VPA_ANA_CON3 0x1744
	883	+#define MT6357_VPA_ANA_CON4 0x1746
	884	+#define MT6357_VPA_ANA_CON5 0x1748
	885	+#define MT6357_BUCK_ANA_ELR_NUM 0x174a
	886	+#define MT6357_SMPS_ELR_0 0x174c
	887	+#define MT6357_SMPS_ELR_1 0x174e
	888	+#define MT6357_SMPS_ELR_2 0x1750
	889	+#define MT6357_SMPS_ELR_3 0x1752
	890	+#define MT6357_SMPS_ELR_4 0x1754
	891	+#define MT6357_SMPS_ELR_5 0x1756
	892	+#define MT6357_VCORE_VPROC_ELR_0 0x1758
	893	+#define MT6357_VCORE_VPROC_ELR_1 0x175a
	894	+#define MT6357_VCORE_VPROC_ELR_2 0x175c
	895	+#define MT6357_VCORE_VPROC_ELR_3 0x175e
	896	+#define MT6357_VCORE_VPROC_ELR_4 0x1760
	897	+#define MT6357_VMODEM_ELR_0 0x1762
	898	+#define MT6357_VMODEM_ELR_1 0x1764
	899	+#define MT6357_VMODEM_ELR_2 0x1766
	900	+#define MT6357_VS1_ELR_0 0x1768
	901	+#define MT6357_VS1_ELR_1 0x176a
	902	+#define MT6357_VPA_ELR_0 0x176c
	903	+#define MT6357_LDO_TOP_ID 0x1880
	904	+#define MT6357_LDO_TOP_REV0 0x1882
	905	+#define MT6357_LDO_TOP_DBI 0x1884
	906	+#define MT6357_LDO_TOP_DXI 0x1886
	907	+#define MT6357_LDO_TPM0 0x1888
	908	+#define MT6357_LDO_TPM1 0x188a
	909	+#define MT6357_LDO_TOP_CLK_DCM_CON0 0x188c
	910	+#define MT6357_LDO_TOP_CLK_VIO28_CON0 0x188e
	911	+#define MT6357_LDO_TOP_CLK_VIO18_CON0 0x1890
	912	+#define MT6357_LDO_TOP_CLK_VAUD28_CON0 0x1892
	913	+#define MT6357_LDO_TOP_CLK_VDRAM_CON0 0x1894
	914	+#define MT6357_LDO_TOP_CLK_VSRAM_PROC_CON0 0x1896
	915	+#define MT6357_LDO_TOP_CLK_VSRAM_OTHERS_CON0 0x1898
	916	+#define MT6357_LDO_TOP_CLK_VAUX18_CON0 0x189a
	917	+#define MT6357_LDO_TOP_CLK_VUSB33_CON0 0x189c
	918	+#define MT6357_LDO_TOP_CLK_VEMC_CON0 0x189e
	919	+#define MT6357_LDO_TOP_CLK_VXO22_CON0 0x18a0
	920	+#define MT6357_LDO_TOP_CLK_VSIM1_CON0 0x18a2
	921	+#define MT6357_LDO_TOP_CLK_VSIM2_CON0 0x18a4
	922	+#define MT6357_LDO_TOP_CLK_VCAMD_CON0 0x18a6
	923	+#define MT6357_LDO_TOP_CLK_VCAMIO_CON0 0x18a8
	924	+#define MT6357_LDO_TOP_CLK_VEFUSE_CON0 0x18aa
	925	+#define MT6357_LDO_TOP_CLK_VCN33_CON0 0x18ac
	926	+#define MT6357_LDO_TOP_CLK_VCN18_CON0 0x18ae
	927	+#define MT6357_LDO_TOP_CLK_VCN28_CON0 0x18b0
	928	+#define MT6357_LDO_TOP_CLK_VIBR_CON0 0x18b2
	929	+#define MT6357_LDO_TOP_CLK_VFE28_CON0 0x18b4
	930	+#define MT6357_LDO_TOP_CLK_VMCH_CON0 0x18b6
	931	+#define MT6357_LDO_TOP_CLK_VMC_CON0 0x18b8
	932	+#define MT6357_LDO_TOP_CLK_VRF18_CON0 0x18ba
	933	+#define MT6357_LDO_TOP_CLK_VLDO28_CON0 0x18bc
	934	+#define MT6357_LDO_TOP_CLK_VRF12_CON0 0x18be
	935	+#define MT6357_LDO_TOP_CLK_VCAMA_CON0 0x18c0
	936	+#define MT6357_LDO_TOP_CLK_TREF_CON0 0x18c2
	937	+#define MT6357_LDO_TOP_INT_CON0 0x18c4
	938	+#define MT6357_LDO_TOP_INT_CON0_SET 0x18c6
	939	+#define MT6357_LDO_TOP_INT_CON0_CLR 0x18c8
	940	+#define MT6357_LDO_TOP_INT_CON1 0x18ca
	941	+#define MT6357_LDO_TOP_INT_CON1_SET 0x18cc
	942	+#define MT6357_LDO_TOP_INT_CON1_CLR 0x18ce
	943	+#define MT6357_LDO_TOP_INT_MASK_CON0 0x18d0
	944	+#define MT6357_LDO_TOP_INT_MASK_CON0_SET 0x18d2
	945	+#define MT6357_LDO_TOP_INT_MASK_CON0_CLR 0x18d4
	946	+#define MT6357_LDO_TOP_INT_MASK_CON1 0x18d6
	947	+#define MT6357_LDO_TOP_INT_MASK_CON1_SET 0x18d8
	948	+#define MT6357_LDO_TOP_INT_MASK_CON1_CLR 0x18da
	949	+#define MT6357_LDO_TOP_INT_STATUS0 0x18dc
	950	+#define MT6357_LDO_TOP_INT_STATUS1 0x18de
	951	+#define MT6357_LDO_TOP_INT_RAW_STATUS0 0x18e0
	952	+#define MT6357_LDO_TOP_INT_RAW_STATUS1 0x18e2
	953	+#define MT6357_LDO_TEST_CON0 0x18e4
	954	+#define MT6357_LDO_TOP_WDT_CON0 0x18e6
	955	+#define MT6357_LDO_TOP_RSV_CON0 0x18e8
	956	+#define MT6357_LDO_TOP_RSV_CON1 0x18ea
	957	+#define MT6357_LDO_OCFB0 0x18ec
	958	+#define MT6357_LDO_LP_PROTECTION 0x18ee
	959	+#define MT6357_LDO_DUMMY_LOAD_GATED 0x18f0
	960	+#define MT6357_LDO_GON0_DSN_ID 0x1900
	961	+#define MT6357_LDO_GON0_DSN_REV0 0x1902
	962	+#define MT6357_LDO_GON0_DSN_DBI 0x1904
	963	+#define MT6357_LDO_GON0_DSN_DXI 0x1906
	964	+#define MT6357_LDO_VXO22_CON0 0x1908
	965	+#define MT6357_LDO_VXO22_OP_EN 0x190a
	966	+#define MT6357_LDO_VXO22_OP_EN_SET 0x190c
	967	+#define MT6357_LDO_VXO22_OP_EN_CLR 0x190e
	968	+#define MT6357_LDO_VXO22_OP_CFG 0x1910
	969	+#define MT6357_LDO_VXO22_OP_CFG_SET 0x1912
	970	+#define MT6357_LDO_VXO22_OP_CFG_CLR 0x1914
	971	+#define MT6357_LDO_VXO22_CON1 0x1916
	972	+#define MT6357_LDO_VXO22_CON2 0x1918
	973	+#define MT6357_LDO_VXO22_CON3 0x191a
	974	+#define MT6357_LDO_VAUX18_CON0 0x191c
	975	+#define MT6357_LDO_VAUX18_OP_EN 0x191e
	976	+#define MT6357_LDO_VAUX18_OP_EN_SET 0x1920
	977	+#define MT6357_LDO_VAUX18_OP_EN_CLR 0x1922
	978	+#define MT6357_LDO_VAUX18_OP_CFG 0x1924
	979	+#define MT6357_LDO_VAUX18_OP_CFG_SET 0x1926
	980	+#define MT6357_LDO_VAUX18_OP_CFG_CLR 0x1928
	981	+#define MT6357_LDO_VAUX18_CON1 0x192a
	982	+#define MT6357_LDO_VAUX18_CON2 0x192c
	983	+#define MT6357_LDO_VAUX18_CON3 0x192e
	984	+#define MT6357_LDO_VAUD28_CON0 0x1930
	985	+#define MT6357_LDO_VAUD28_OP_EN 0x1932
	986	+#define MT6357_LDO_VAUD28_OP_EN_SET 0x1934
	987	+#define MT6357_LDO_VAUD28_OP_EN_CLR 0x1936
	988	+#define MT6357_LDO_VAUD28_OP_CFG 0x1938
	989	+#define MT6357_LDO_VAUD28_OP_CFG_SET 0x193a
	990	+#define MT6357_LDO_VAUD28_OP_CFG_CLR 0x193c
	991	+#define MT6357_LDO_VAUD28_CON1 0x193e
	992	+#define MT6357_LDO_VAUD28_CON2 0x1940
	993	+#define MT6357_LDO_VAUD28_CON3 0x1942
	994	+#define MT6357_LDO_VIO28_CON0 0x1944
	995	+#define MT6357_LDO_VIO28_OP_EN 0x1946
	996	+#define MT6357_LDO_VIO28_OP_EN_SET 0x1948
	997	+#define MT6357_LDO_VIO28_OP_EN_CLR 0x194a
	998	+#define MT6357_LDO_VIO28_OP_CFG 0x194c
	999	+#define MT6357_LDO_VIO28_OP_CFG_SET 0x194e
	1000	+#define MT6357_LDO_VIO28_OP_CFG_CLR 0x1950
	1001	+#define MT6357_LDO_VIO28_CON1 0x1952
	1002	+#define MT6357_LDO_VIO28_CON2 0x1954
	1003	+#define MT6357_LDO_VIO28_CON3 0x1956
	1004	+#define MT6357_LDO_VIO18_CON0 0x1958
	1005	+#define MT6357_LDO_VIO18_OP_EN 0x195a
	1006	+#define MT6357_LDO_VIO18_OP_EN_SET 0x195c
	1007	+#define MT6357_LDO_VIO18_OP_EN_CLR 0x195e
	1008	+#define MT6357_LDO_VIO18_OP_CFG 0x1960
	1009	+#define MT6357_LDO_VIO18_OP_CFG_SET 0x1962
	1010	+#define MT6357_LDO_VIO18_OP_CFG_CLR 0x1964
	1011	+#define MT6357_LDO_VIO18_CON1 0x1966
	1012	+#define MT6357_LDO_VIO18_CON2 0x1968
	1013	+#define MT6357_LDO_VIO18_CON3 0x196a
	1014	+#define MT6357_LDO_VDRAM_CON0 0x196c
	1015	+#define MT6357_LDO_VDRAM_OP_EN 0x196e
	1016	+#define MT6357_LDO_VDRAM_OP_EN_SET 0x1970
	1017	+#define MT6357_LDO_VDRAM_OP_EN_CLR 0x1972
	1018	+#define MT6357_LDO_VDRAM_OP_CFG 0x1974
	1019	+#define MT6357_LDO_VDRAM_OP_CFG_SET 0x1976
	1020	+#define MT6357_LDO_VDRAM_OP_CFG_CLR 0x1978
	1021	+#define MT6357_LDO_VDRAM_CON1 0x197a
	1022	+#define MT6357_LDO_VDRAM_CON2 0x197c
	1023	+#define MT6357_LDO_VDRAM_CON3 0x197e
	1024	+#define MT6357_LDO_GON1_DSN_ID 0x1980
	1025	+#define MT6357_LDO_GON1_DSN_REV0 0x1982
	1026	+#define MT6357_LDO_GON1_DSN_DBI 0x1984
	1027	+#define MT6357_LDO_GON1_DSN_DXI 0x1986
	1028	+#define MT6357_LDO_VEMC_CON0 0x1988
	1029	+#define MT6357_LDO_VEMC_OP_EN 0x198a
	1030	+#define MT6357_LDO_VEMC_OP_EN_SET 0x198c
	1031	+#define MT6357_LDO_VEMC_OP_EN_CLR 0x198e
	1032	+#define MT6357_LDO_VEMC_OP_CFG 0x1990
	1033	+#define MT6357_LDO_VEMC_OP_CFG_SET 0x1992
	1034	+#define MT6357_LDO_VEMC_OP_CFG_CLR 0x1994
	1035	+#define MT6357_LDO_VEMC_CON1 0x1996
	1036	+#define MT6357_LDO_VEMC_CON2 0x1998
	1037	+#define MT6357_LDO_VEMC_CON3 0x199a
	1038	+#define MT6357_LDO_VUSB33_CON0_0 0x199c
	1039	+#define MT6357_LDO_VUSB33_OP_EN 0x199e
	1040	+#define MT6357_LDO_VUSB33_OP_EN_SET 0x19a0
	1041	+#define MT6357_LDO_VUSB33_OP_EN_CLR 0x19a2
	1042	+#define MT6357_LDO_VUSB33_OP_CFG 0x19a4
	1043	+#define MT6357_LDO_VUSB33_OP_CFG_SET 0x19a6
	1044	+#define MT6357_LDO_VUSB33_OP_CFG_CLR 0x19a8
	1045	+#define MT6357_LDO_VUSB33_CON0_1 0x19aa
	1046	+#define MT6357_LDO_VUSB33_CON1 0x19ac
	1047	+#define MT6357_LDO_VUSB33_CON2 0x19ae
	1048	+#define MT6357_LDO_VUSB33_CON3 0x19b0
	1049	+#define MT6357_LDO_VSRAM_PROC_CON0 0x19b2
	1050	+#define MT6357_LDO_VSRAM_PROC_CON2 0x19b4
	1051	+#define MT6357_LDO_VSRAM_PROC_CFG0 0x19b6
	1052	+#define MT6357_LDO_VSRAM_PROC_CFG1 0x19b8
	1053	+#define MT6357_LDO_VSRAM_PROC_OP_EN 0x19ba
	1054	+#define MT6357_LDO_VSRAM_PROC_OP_EN_SET 0x19bc
	1055	+#define MT6357_LDO_VSRAM_PROC_OP_EN_CLR 0x19be
	1056	+#define MT6357_LDO_VSRAM_PROC_OP_CFG 0x19c0
	1057	+#define MT6357_LDO_VSRAM_PROC_OP_CFG_SET 0x19c2
	1058	+#define MT6357_LDO_VSRAM_PROC_OP_CFG_CLR 0x19c4
	1059	+#define MT6357_LDO_VSRAM_PROC_CON3 0x19c6
	1060	+#define MT6357_LDO_VSRAM_PROC_CON4 0x19c8
	1061	+#define MT6357_LDO_VSRAM_PROC_CON5 0x19ca
	1062	+#define MT6357_LDO_VSRAM_PROC_DBG0 0x19cc
	1063	+#define MT6357_LDO_VSRAM_PROC_DBG1 0x19ce
	1064	+#define MT6357_LDO_VSRAM_OTHERS_CON0 0x19d0
	1065	+#define MT6357_LDO_VSRAM_OTHERS_CON2 0x19d2
	1066	+#define MT6357_LDO_VSRAM_OTHERS_CFG0 0x19d4
	1067	+#define MT6357_LDO_VSRAM_OTHERS_CFG1 0x19d6
	1068	+#define MT6357_LDO_VSRAM_OTHERS_OP_EN 0x19d8
	1069	+#define MT6357_LDO_VSRAM_OTHERS_OP_EN_SET 0x19da
	1070	+#define MT6357_LDO_VSRAM_OTHERS_OP_EN_CLR 0x19dc
	1071	+#define MT6357_LDO_VSRAM_OTHERS_OP_CFG 0x19de
	1072	+#define MT6357_LDO_VSRAM_OTHERS_OP_CFG_SET 0x19e0
	1073	+#define MT6357_LDO_VSRAM_OTHERS_OP_CFG_CLR 0x19e2
	1074	+#define MT6357_LDO_VSRAM_OTHERS_CON3 0x19e4
	1075	+#define MT6357_LDO_VSRAM_OTHERS_CON4 0x19e6
	1076	+#define MT6357_LDO_VSRAM_OTHERS_CON5 0x19e8
	1077	+#define MT6357_LDO_VSRAM_OTHERS_DBG0 0x19ea
	1078	+#define MT6357_LDO_VSRAM_OTHERS_DBG1 0x19ec
	1079	+#define MT6357_LDO_VSRAM_PROC_SP 0x19ee
	1080	+#define MT6357_LDO_VSRAM_OTHERS_SP 0x19f0
	1081	+#define MT6357_LDO_VSRAM_PROC_R2R_PDN_DIS 0x19f2
	1082	+#define MT6357_LDO_VSRAM_OTHERS_R2R_PDN_DIS 0x19f4
	1083	+#define MT6357_LDO_VSRAM_WDT_DBG0 0x19f6
	1084	+#define MT6357_LDO_GON1_ELR_NUM 0x19f8
	1085	+#define MT6357_LDO_VSRAM_CON0 0x19fa
	1086	+#define MT6357_LDO_VSRAM_CON1 0x19fc
	1087	+#define MT6357_LDO_VSRAM_CON2 0x19fe
	1088	+#define MT6357_LDO_GOFF0_DSN_ID 0x1a00
	1089	+#define MT6357_LDO_GOFF0_DSN_REV0 0x1a02
	1090	+#define MT6357_LDO_GOFF0_DSN_DBI 0x1a04
	1091	+#define MT6357_LDO_GOFF0_DSN_DXI 0x1a06
	1092	+#define MT6357_LDO_VFE28_CON0 0x1a08
	1093	+#define MT6357_LDO_VFE28_OP_EN 0x1a0a
	1094	+#define MT6357_LDO_VFE28_OP_EN_SET 0x1a0c
	1095	+#define MT6357_LDO_VFE28_OP_EN_CLR 0x1a0e
	1096	+#define MT6357_LDO_VFE28_OP_CFG 0x1a10
	1097	+#define MT6357_LDO_VFE28_OP_CFG_SET 0x1a12
	1098	+#define MT6357_LDO_VFE28_OP_CFG_CLR 0x1a14
	1099	+#define MT6357_LDO_VFE28_CON1 0x1a16
	1100	+#define MT6357_LDO_VFE28_CON2 0x1a18
	1101	+#define MT6357_LDO_VFE28_CON3 0x1a1a
	1102	+#define MT6357_LDO_VRF18_CON0 0x1a1c
	1103	+#define MT6357_LDO_VRF18_OP_EN 0x1a1e
	1104	+#define MT6357_LDO_VRF18_OP_EN_SET 0x1a20
	1105	+#define MT6357_LDO_VRF18_OP_EN_CLR 0x1a22
	1106	+#define MT6357_LDO_VRF18_OP_CFG 0x1a24
	1107	+#define MT6357_LDO_VRF18_OP_CFG_SET 0x1a26
	1108	+#define MT6357_LDO_VRF18_OP_CFG_CLR 0x1a28
	1109	+#define MT6357_LDO_VRF18_CON1 0x1a2a
	1110	+#define MT6357_LDO_VRF18_CON2 0x1a2c
	1111	+#define MT6357_LDO_VRF18_CON3 0x1a2e
	1112	+#define MT6357_LDO_VRF12_CON0 0x1a30
	1113	+#define MT6357_LDO_VRF12_OP_EN 0x1a32
	1114	+#define MT6357_LDO_VRF12_OP_EN_SET 0x1a34
	1115	+#define MT6357_LDO_VRF12_OP_EN_CLR 0x1a36
	1116	+#define MT6357_LDO_VRF12_OP_CFG 0x1a38
	1117	+#define MT6357_LDO_VRF12_OP_CFG_SET 0x1a3a
	1118	+#define MT6357_LDO_VRF12_OP_CFG_CLR 0x1a3c
	1119	+#define MT6357_LDO_VRF12_CON1 0x1a3e
	1120	+#define MT6357_LDO_VRF12_CON2 0x1a40
	1121	+#define MT6357_LDO_VRF12_CON3 0x1a42
	1122	+#define MT6357_LDO_VEFUSE_CON0 0x1a44
	1123	+#define MT6357_LDO_VEFUSE_OP_EN 0x1a46
	1124	+#define MT6357_LDO_VEFUSE_OP_EN_SET 0x1a48
	1125	+#define MT6357_LDO_VEFUSE_OP_EN_CLR 0x1a4a
	1126	+#define MT6357_LDO_VEFUSE_OP_CFG 0x1a4c
	1127	+#define MT6357_LDO_VEFUSE_OP_CFG_SET 0x1a4e
	1128	+#define MT6357_LDO_VEFUSE_OP_CFG_CLR 0x1a50
	1129	+#define MT6357_LDO_VEFUSE_CON1 0x1a52
	1130	+#define MT6357_LDO_VEFUSE_CON2 0x1a54
	1131	+#define MT6357_LDO_VEFUSE_CON3 0x1a56
	1132	+#define MT6357_LDO_VCN18_CON0 0x1a58
	1133	+#define MT6357_LDO_VCN18_OP_EN 0x1a5a
	1134	+#define MT6357_LDO_VCN18_OP_EN_SET 0x1a5c
	1135	+#define MT6357_LDO_VCN18_OP_EN_CLR 0x1a5e
	1136	+#define MT6357_LDO_VCN18_OP_CFG 0x1a60
	1137	+#define MT6357_LDO_VCN18_OP_CFG_SET 0x1a62
	1138	+#define MT6357_LDO_VCN18_OP_CFG_CLR 0x1a64
	1139	+#define MT6357_LDO_VCN18_CON1 0x1a66
	1140	+#define MT6357_LDO_VCN18_CON2 0x1a68
	1141	+#define MT6357_LDO_VCN18_CON3 0x1a6a
	1142	+#define MT6357_LDO_VCAMA_CON0 0x1a6c
	1143	+#define MT6357_LDO_VCAMA_OP_EN 0x1a6e
	1144	+#define MT6357_LDO_VCAMA_OP_EN_SET 0x1a70
	1145	+#define MT6357_LDO_VCAMA_OP_EN_CLR 0x1a72
	1146	+#define MT6357_LDO_VCAMA_OP_CFG 0x1a74
	1147	+#define MT6357_LDO_VCAMA_OP_CFG_SET 0x1a76
	1148	+#define MT6357_LDO_VCAMA_OP_CFG_CLR 0x1a78
	1149	+#define MT6357_LDO_VCAMA_CON1 0x1a7a
	1150	+#define MT6357_LDO_VCAMA_CON2 0x1a7c
	1151	+#define MT6357_LDO_VCAMA_CON3 0x1a7e
	1152	+#define MT6357_LDO_GOFF1_DSN_ID 0x1a80
	1153	+#define MT6357_LDO_GOFF1_DSN_REV0 0x1a82
	1154	+#define MT6357_LDO_GOFF1_DSN_DBI 0x1a84
	1155	+#define MT6357_LDO_GOFF1_DSN_DXI 0x1a86
	1156	+#define MT6357_LDO_VCAMD_CON0 0x1a88
	1157	+#define MT6357_LDO_VCAMD_OP_EN 0x1a8a
	1158	+#define MT6357_LDO_VCAMD_OP_EN_SET 0x1a8c
	1159	+#define MT6357_LDO_VCAMD_OP_EN_CLR 0x1a8e
	1160	+#define MT6357_LDO_VCAMD_OP_CFG 0x1a90
	1161	+#define MT6357_LDO_VCAMD_OP_CFG_SET 0x1a92
	1162	+#define MT6357_LDO_VCAMD_OP_CFG_CLR 0x1a94
	1163	+#define MT6357_LDO_VCAMD_CON1 0x1a96
	1164	+#define MT6357_LDO_VCAMD_CON2 0x1a98
	1165	+#define MT6357_LDO_VCAMD_CON3 0x1a9a
	1166	+#define MT6357_LDO_VCAMIO_CON0 0x1a9c
	1167	+#define MT6357_LDO_VCAMIO_OP_EN 0x1a9e
	1168	+#define MT6357_LDO_VCAMIO_OP_EN_SET 0x1aa0
	1169	+#define MT6357_LDO_VCAMIO_OP_EN_CLR 0x1aa2
	1170	+#define MT6357_LDO_VCAMIO_OP_CFG 0x1aa4
	1171	+#define MT6357_LDO_VCAMIO_OP_CFG_SET 0x1aa6
	1172	+#define MT6357_LDO_VCAMIO_OP_CFG_CLR 0x1aa8
	1173	+#define MT6357_LDO_VCAMIO_CON1 0x1aaa
	1174	+#define MT6357_LDO_VCAMIO_CON2 0x1aac
	1175	+#define MT6357_LDO_VCAMIO_CON3 0x1aae
	1176	+#define MT6357_LDO_VMC_CON0 0x1ab0
	1177	+#define MT6357_LDO_VMC_OP_EN 0x1ab2
	1178	+#define MT6357_LDO_VMC_OP_EN_SET 0x1ab4
	1179	+#define MT6357_LDO_VMC_OP_EN_CLR 0x1ab6
	1180	+#define MT6357_LDO_VMC_OP_CFG 0x1ab8
	1181	+#define MT6357_LDO_VMC_OP_CFG_SET 0x1aba
	1182	+#define MT6357_LDO_VMC_OP_CFG_CLR 0x1abc
	1183	+#define MT6357_LDO_VMC_CON1 0x1abe
	1184	+#define MT6357_LDO_VMC_CON2 0x1ac0
	1185	+#define MT6357_LDO_VMC_CON3 0x1ac2
	1186	+#define MT6357_LDO_VMCH_CON0 0x1ac4
	1187	+#define MT6357_LDO_VMCH_OP_EN 0x1ac6
	1188	+#define MT6357_LDO_VMCH_OP_EN_SET 0x1ac8
	1189	+#define MT6357_LDO_VMCH_OP_EN_CLR 0x1aca
	1190	+#define MT6357_LDO_VMCH_OP_CFG 0x1acc
	1191	+#define MT6357_LDO_VMCH_OP_CFG_SET 0x1ace
	1192	+#define MT6357_LDO_VMCH_OP_CFG_CLR 0x1ad0
	1193	+#define MT6357_LDO_VMCH_CON1 0x1ad2
	1194	+#define MT6357_LDO_VMCH_CON2 0x1ad4
	1195	+#define MT6357_LDO_VMCH_CON3 0x1ad6
	1196	+#define MT6357_LDO_VSIM1_CON0 0x1ad8
	1197	+#define MT6357_LDO_VSIM1_OP_EN 0x1ada
	1198	+#define MT6357_LDO_VSIM1_OP_EN_SET 0x1adc
	1199	+#define MT6357_LDO_VSIM1_OP_EN_CLR 0x1ade
	1200	+#define MT6357_LDO_VSIM1_OP_CFG 0x1ae0
	1201	+#define MT6357_LDO_VSIM1_OP_CFG_SET 0x1ae2
	1202	+#define MT6357_LDO_VSIM1_OP_CFG_CLR 0x1ae4
	1203	+#define MT6357_LDO_VSIM1_CON1 0x1ae6
	1204	+#define MT6357_LDO_VSIM1_CON2 0x1ae8
	1205	+#define MT6357_LDO_VSIM1_CON3 0x1aea
	1206	+#define MT6357_LDO_VSIM2_CON0 0x1aec
	1207	+#define MT6357_LDO_VSIM2_OP_EN 0x1aee
	1208	+#define MT6357_LDO_VSIM2_OP_EN_SET 0x1af0
	1209	+#define MT6357_LDO_VSIM2_OP_EN_CLR 0x1af2
	1210	+#define MT6357_LDO_VSIM2_OP_CFG 0x1af4
	1211	+#define MT6357_LDO_VSIM2_OP_CFG_SET 0x1af6
	1212	+#define MT6357_LDO_VSIM2_OP_CFG_CLR 0x1af8
	1213	+#define MT6357_LDO_VSIM2_CON1 0x1afa
	1214	+#define MT6357_LDO_VSIM2_CON2 0x1afc
	1215	+#define MT6357_LDO_VSIM2_CON3 0x1afe
	1216	+#define MT6357_LDO_GOFF2_DSN_ID 0x1b00
	1217	+#define MT6357_LDO_GOFF2_DSN_REV0 0x1b02
	1218	+#define MT6357_LDO_GOFF2_DSN_DBI 0x1b04
	1219	+#define MT6357_LDO_GOFF2_DSN_DXI 0x1b06
	1220	+#define MT6357_LDO_VIBR_CON0 0x1b08
	1221	+#define MT6357_LDO_VIBR_OP_EN 0x1b0a
	1222	+#define MT6357_LDO_VIBR_OP_EN_SET 0x1b0c
	1223	+#define MT6357_LDO_VIBR_OP_EN_CLR 0x1b0e
	1224	+#define MT6357_LDO_VIBR_OP_CFG 0x1b10
	1225	+#define MT6357_LDO_VIBR_OP_CFG_SET 0x1b12
	1226	+#define MT6357_LDO_VIBR_OP_CFG_CLR 0x1b14
	1227	+#define MT6357_LDO_VIBR_CON1 0x1b16
	1228	+#define MT6357_LDO_VIBR_CON2 0x1b18
	1229	+#define MT6357_LDO_VIBR_CON3 0x1b1a
	1230	+#define MT6357_LDO_VCN33_CON0_0 0x1b1c
	1231	+#define MT6357_LDO_VCN33_OP_EN 0x1b1e
	1232	+#define MT6357_LDO_VCN33_OP_EN_SET 0x1b20
	1233	+#define MT6357_LDO_VCN33_OP_EN_CLR 0x1b22
	1234	+#define MT6357_LDO_VCN33_OP_CFG 0x1b24
	1235	+#define MT6357_LDO_VCN33_OP_CFG_SET 0x1b26
	1236	+#define MT6357_LDO_VCN33_OP_CFG_CLR 0x1b28
	1237	+#define MT6357_LDO_VCN33_CON0_1 0x1b2a
	1238	+#define MT6357_LDO_VCN33_CON1 0x1b2c
	1239	+#define MT6357_LDO_VCN33_CON2 0x1b2e
	1240	+#define MT6357_LDO_VCN33_CON3 0x1b30
	1241	+#define MT6357_LDO_VLDO28_CON0_0 0x1b32
	1242	+#define MT6357_LDO_VLDO28_OP_EN 0x1b34
	1243	+#define MT6357_LDO_VLDO28_OP_EN_SET 0x1b36
	1244	+#define MT6357_LDO_VLDO28_OP_EN_CLR 0x1b38
	1245	+#define MT6357_LDO_VLDO28_OP_CFG 0x1b3a
	1246	+#define MT6357_LDO_VLDO28_OP_CFG_SET 0x1b3c
	1247	+#define MT6357_LDO_VLDO28_OP_CFG_CLR 0x1b3e
	1248	+#define MT6357_LDO_VLDO28_CON0_1 0x1b40
	1249	+#define MT6357_LDO_VLDO28_CON1 0x1b42
	1250	+#define MT6357_LDO_VLDO28_CON2 0x1b44
	1251	+#define MT6357_LDO_VLDO28_CON3 0x1b46
	1252	+#define MT6357_LDO_GOFF2_RSV_CON0 0x1b48
	1253	+#define MT6357_LDO_GOFF2_RSV_CON1 0x1b4a
	1254	+#define MT6357_LDO_GOFF3_DSN_ID 0x1b80
	1255	+#define MT6357_LDO_GOFF3_DSN_REV0 0x1b82
	1256	+#define MT6357_LDO_GOFF3_DSN_DBI 0x1b84
	1257	+#define MT6357_LDO_GOFF3_DSN_DXI 0x1b86
	1258	+#define MT6357_LDO_VCN28_CON0 0x1b88
	1259	+#define MT6357_LDO_VCN28_OP_EN 0x1b8a
	1260	+#define MT6357_LDO_VCN28_OP_EN_SET 0x1b8c
	1261	+#define MT6357_LDO_VCN28_OP_EN_CLR 0x1b8e
	1262	+#define MT6357_LDO_VCN28_OP_CFG 0x1b90
	1263	+#define MT6357_LDO_VCN28_OP_CFG_SET 0x1b92
	1264	+#define MT6357_LDO_VCN28_OP_CFG_CLR 0x1b94
	1265	+#define MT6357_LDO_VCN28_CON1 0x1b96
	1266	+#define MT6357_LDO_VCN28_CON2 0x1b98
	1267	+#define MT6357_LDO_VCN28_CON3 0x1b9a
	1268	+#define MT6357_VRTC_CON0 0x1b9c
	1269	+#define MT6357_LDO_TREF_CON0 0x1b9e
	1270	+#define MT6357_LDO_TREF_OP_EN 0x1ba0
	1271	+#define MT6357_LDO_TREF_OP_EN_SET 0x1ba2
	1272	+#define MT6357_LDO_TREF_OP_EN_CLR 0x1ba4
	1273	+#define MT6357_LDO_TREF_OP_CFG 0x1ba6
	1274	+#define MT6357_LDO_TREF_OP_CFG_SET 0x1ba8
	1275	+#define MT6357_LDO_TREF_OP_CFG_CLR 0x1baa
	1276	+#define MT6357_LDO_TREF_CON1 0x1bac
	1277	+#define MT6357_LDO_GOFF3_RSV_CON0 0x1bae
	1278	+#define MT6357_LDO_GOFF3_RSV_CON1 0x1bb0
	1279	+#define MT6357_LDO_ANA0_DSN_ID 0x1c00
	1280	+#define MT6357_LDO_ANA0_DSN_REV0 0x1c02
	1281	+#define MT6357_LDO_ANA0_DSN_DBI 0x1c04
	1282	+#define MT6357_LDO_ANA0_DSN_DXI 0x1c06
	1283	+#define MT6357_VFE28_ANA_CON0 0x1c08
	1284	+#define MT6357_VFE28_ANA_CON1 0x1c0a
	1285	+#define MT6357_VCN28_ANA_CON0 0x1c0c
	1286	+#define MT6357_VCN28_ANA_CON1 0x1c0e
	1287	+#define MT6357_VAUD28_ANA_CON0 0x1c10
	1288	+#define MT6357_VAUD28_ANA_CON1 0x1c12
	1289	+#define MT6357_VAUX18_ANA_CON0 0x1c14
	1290	+#define MT6357_VAUX18_ANA_CON1 0x1c16
	1291	+#define MT6357_VXO22_ANA_CON0 0x1c18
	1292	+#define MT6357_VXO22_ANA_CON1 0x1c1a
	1293	+#define MT6357_VCN33_ANA_CON0 0x1c1c
	1294	+#define MT6357_VCN33_ANA_CON1 0x1c1e
	1295	+#define MT6357_VEMC_ANA_CON0 0x1c20
	1296	+#define MT6357_VEMC_ANA_CON1 0x1c22
	1297	+#define MT6357_VLDO28_ANA_CON0 0x1c24
	1298	+#define MT6357_VLDO28_ANA_CON1 0x1c26
	1299	+#define MT6357_VIO28_ANA_CON0 0x1c28
	1300	+#define MT6357_VIO28_ANA_CON1 0x1c2a
	1301	+#define MT6357_VIBR_ANA_CON0 0x1c2c
	1302	+#define MT6357_VIBR_ANA_CON1 0x1c2e
	1303	+#define MT6357_VSIM1_ANA_CON0 0x1c30
	1304	+#define MT6357_VSIM1_ANA_CON1 0x1c32
	1305	+#define MT6357_VSIM2_ANA_CON0 0x1c34
	1306	+#define MT6357_VSIM2_ANA_CON1 0x1c36
	1307	+#define MT6357_VMCH_ANA_CON0 0x1c38
	1308	+#define MT6357_VMCH_ANA_CON1 0x1c3a
	1309	+#define MT6357_VMC_ANA_CON0 0x1c3c
	1310	+#define MT6357_VMC_ANA_CON1 0x1c3e
	1311	+#define MT6357_VCAMIO_ANA_CON0 0x1c40
	1312	+#define MT6357_VCAMIO_ANA_CON1 0x1c42
	1313	+#define MT6357_VCN18_ANA_CON0 0x1c44
	1314	+#define MT6357_VCN18_ANA_CON1 0x1c46
	1315	+#define MT6357_VRF18_ANA_CON0 0x1c48
	1316	+#define MT6357_VRF18_ANA_CON1 0x1c4a
	1317	+#define MT6357_VIO18_ANA_CON0 0x1c4c
	1318	+#define MT6357_VIO18_ANA_CON1 0x1c4e
	1319	+#define MT6357_VDRAM_ANA_CON1 0x1c50
	1320	+#define MT6357_VRF12_ANA_CON0 0x1c52
	1321	+#define MT6357_VRF12_ANA_CON1 0x1c54
	1322	+#define MT6357_VSRAM_PROC_ANA_CON0 0x1c56
	1323	+#define MT6357_VSRAM_OTHERS_ANA_CON0 0x1c58
	1324	+#define MT6357_LDO_ANA0_ELR_NUM 0x1c5a
	1325	+#define MT6357_VFE28_ELR_0 0x1c5c
	1326	+#define MT6357_VCN28_ELR_0 0x1c5e
	1327	+#define MT6357_VAUD28_ELR_0 0x1c60
	1328	+#define MT6357_VAUX18_ELR_0 0x1c62
	1329	+#define MT6357_VXO22_ELR_0 0x1c64
	1330	+#define MT6357_VCN33_ELR_0 0x1c66
	1331	+#define MT6357_VEMC_ELR_0 0x1c68
	1332	+#define MT6357_VLDO28_ELR_0 0x1c6a
	1333	+#define MT6357_VIO28_ELR_0 0x1c6c
	1334	+#define MT6357_VIBR_ELR_0 0x1c6e
	1335	+#define MT6357_VSIM1_ELR_0 0x1c70
	1336	+#define MT6357_VSIM2_ELR_0 0x1c72
	1337	+#define MT6357_VMCH_ELR_0 0x1c74
	1338	+#define MT6357_VMC_ELR_0 0x1c76
	1339	+#define MT6357_VCAMIO_ELR_0 0x1c78
	1340	+#define MT6357_VCN18_ELR_0 0x1c7a
	1341	+#define MT6357_VRF18_ELR_0 0x1c7c
	1342	+#define MT6357_LDO_ANA1_DSN_ID 0x1c80
	1343	+#define MT6357_LDO_ANA1_DSN_REV0 0x1c82
	1344	+#define MT6357_LDO_ANA1_DSN_DBI 0x1c84
	1345	+#define MT6357_LDO_ANA1_DSN_DXI 0x1c86
	1346	+#define MT6357_VUSB33_ANA_CON0 0x1c88
	1347	+#define MT6357_VUSB33_ANA_CON1 0x1c8a
	1348	+#define MT6357_VCAMA_ANA_CON0 0x1c8c
	1349	+#define MT6357_VCAMA_ANA_CON1 0x1c8e
	1350	+#define MT6357_VEFUSE_ANA_CON0 0x1c90
	1351	+#define MT6357_VEFUSE_ANA_CON1 0x1c92
	1352	+#define MT6357_VCAMD_ANA_CON0 0x1c94
	1353	+#define MT6357_VCAMD_ANA_CON1 0x1c96
	1354	+#define MT6357_LDO_ANA1_ELR_NUM 0x1c98
	1355	+#define MT6357_VUSB33_ELR_0 0x1c9a
	1356	+#define MT6357_VCAMA_ELR_0 0x1c9c
	1357	+#define MT6357_VEFUSE_ELR_0 0x1c9e
	1358	+#define MT6357_VCAMD_ELR_0 0x1ca0
	1359	+#define MT6357_VIO18_ELR_0 0x1ca2
	1360	+#define MT6357_VDRAM_ELR_0 0x1ca4
	1361	+#define MT6357_VRF12_ELR_0 0x1ca6
	1362	+#define MT6357_VRTC_ELR_0 0x1ca8
	1363	+#define MT6357_VDRAM_ELR_1 0x1caa
	1364	+#define MT6357_VDRAM_ELR_2 0x1cac
	1365	+#define MT6357_XPP_TOP_ID 0x1e00
	1366	+#define MT6357_XPP_TOP_REV0 0x1e02
	1367	+#define MT6357_XPP_TOP_DBI 0x1e04
	1368	+#define MT6357_XPP_TOP_DXI 0x1e06
	1369	+#define MT6357_XPP_TPM0 0x1e08
	1370	+#define MT6357_XPP_TPM1 0x1e0a
	1371	+#define MT6357_XPP_TOP_TEST_OUT 0x1e0c
	1372	+#define MT6357_XPP_TOP_TEST_CON0 0x1e0e
	1373	+#define MT6357_XPP_TOP_CKPDN_CON0 0x1e10
	1374	+#define MT6357_XPP_TOP_CKPDN_CON0_SET 0x1e12
	1375	+#define MT6357_XPP_TOP_CKPDN_CON0_CLR 0x1e14
	1376	+#define MT6357_XPP_TOP_CKSEL_CON0 0x1e16
	1377	+#define MT6357_XPP_TOP_CKSEL_CON0_SET 0x1e18
	1378	+#define MT6357_XPP_TOP_CKSEL_CON0_CLR 0x1e1a
	1379	+#define MT6357_XPP_TOP_RST_CON0 0x1e1c
	1380	+#define MT6357_XPP_TOP_RST_CON0_SET 0x1e1e
	1381	+#define MT6357_XPP_TOP_RST_CON0_CLR 0x1e20
	1382	+#define MT6357_XPP_TOP_RST_BANK_CON0 0x1e22
	1383	+#define MT6357_XPP_TOP_RST_BANK_CON0_SET 0x1e24
	1384	+#define MT6357_XPP_TOP_RST_BANK_CON0_CLR 0x1e26
	1385	+#define MT6357_DRIVER_BL_DSN_ID 0x1e80
	1386	+#define MT6357_DRIVER_BL_DSN_REV0 0x1e82
	1387	+#define MT6357_DRIVER_BL_DSN_DBI 0x1e84
	1388	+#define MT6357_DRIVER_BL_DSN_DXI 0x1e86
	1389	+#define MT6357_ISINK1_CON0 0x1e88
	1390	+#define MT6357_ISINK1_CON1 0x1e8a
	1391	+#define MT6357_ISINK1_CON2 0x1e8c
	1392	+#define MT6357_ISINK1_CON3 0x1e8e
	1393	+#define MT6357_ISINK_ANA1 0x1e90
	1394	+#define MT6357_ISINK_PHASE_DLY 0x1e92
	1395	+#define MT6357_ISINK_SFSTR 0x1e94
	1396	+#define MT6357_ISINK_EN_CTRL 0x1e96
	1397	+#define MT6357_ISINK_MODE_CTRL 0x1e98
	1398	+#define MT6357_DRIVER_ANA_CON0 0x1e9a
	1399	+#define MT6357_ISINK_ANA_CON0 0x1e9c
	1400	+#define MT6357_ISINK_ANA_CON1 0x1e9e
	1401	+#define MT6357_DRIVER_BL_ELR_NUM 0x1ea0
	1402	+#define MT6357_DRIVER_BL_ELR_0 0x1ea2
	1403	+#define MT6357_DRIVER_CI_DSN_ID 0x1f00
	1404	+#define MT6357_DRIVER_CI_DSN_REV0 0x1f02
	1405	+#define MT6357_DRIVER_CI_DSN_DBI 0x1f04
	1406	+#define MT6357_DRIVER_CI_DSN_DXI 0x1f06
	1407	+#define MT6357_CHRIND_CON0 0x1f08
	1408	+#define MT6357_CHRIND_CON1 0x1f0a
	1409	+#define MT6357_CHRIND_CON2 0x1f0c
	1410	+#define MT6357_CHRIND_CON3 0x1f0e
	1411	+#define MT6357_CHRIND_CON4 0x1f10
	1412	+#define MT6357_CHRIND_EN_CTRL 0x1f12
	1413	+#define MT6357_CHRIND_ANA_CON0 0x1f14
	1414	+#define MT6357_DRIVER_DL_DSN_ID 0x1f80
	1415	+#define MT6357_DRIVER_DL_DSN_REV0 0x1f82
	1416	+#define MT6357_DRIVER_DL_DSN_DBI 0x1f84
	1417	+#define MT6357_DRIVER_DL_DSN_DXI 0x1f86
	1418	+#define MT6357_ISINK2_CON0 0x1f88
	1419	+#define MT6357_ISINK3_CON0 0x1f8a
	1420	+#define MT6357_ISINK_EN_CTRL_SMPL 0x1f8c
	1421	+#define MT6357_AUD_TOP_ID 0x2080
	1422	+#define MT6357_AUD_TOP_REV0 0x2082
	1423	+#define MT6357_AUD_TOP_DBI 0x2084
	1424	+#define MT6357_AUD_TOP_DXI 0x2086
	1425	+#define MT6357_AUD_TOP_CKPDN_TPM0 0x2088
	1426	+#define MT6357_AUD_TOP_CKPDN_TPM1 0x208a
	1427	+#define MT6357_AUD_TOP_CKPDN_CON0 0x208c
	1428	+#define MT6357_AUD_TOP_CKPDN_CON0_SET 0x208e
	1429	+#define MT6357_AUD_TOP_CKPDN_CON0_CLR 0x2090
	1430	+#define MT6357_AUD_TOP_CKSEL_CON0 0x2092
	1431	+#define MT6357_AUD_TOP_CKSEL_CON0_SET 0x2094
	1432	+#define MT6357_AUD_TOP_CKSEL_CON0_CLR 0x2096
	1433	+#define MT6357_AUD_TOP_CKTST_CON0 0x2098
	1434	+#define MT6357_AUD_TOP_RST_CON0 0x209a
	1435	+#define MT6357_AUD_TOP_RST_CON0_SET 0x209c
	1436	+#define MT6357_AUD_TOP_RST_CON0_CLR 0x209e
	1437	+#define MT6357_AUD_TOP_RST_BANK_CON0 0x20a0
	1438	+#define MT6357_AUD_TOP_INT_CON0 0x20a2
	1439	+#define MT6357_AUD_TOP_INT_CON0_SET 0x20a4
	1440	+#define MT6357_AUD_TOP_INT_CON0_CLR 0x20a6
	1441	+#define MT6357_AUD_TOP_INT_MASK_CON0 0x20a8
	1442	+#define MT6357_AUD_TOP_INT_MASK_CON0_SET 0x20aa
	1443	+#define MT6357_AUD_TOP_INT_MASK_CON0_CLR 0x20ac
	1444	+#define MT6357_AUD_TOP_INT_STATUS0 0x20ae
	1445	+#define MT6357_AUD_TOP_INT_RAW_STATUS0 0x20b0
	1446	+#define MT6357_AUD_TOP_INT_MISC_CON0 0x20b2
	1447	+#define MT6357_AUDNCP_CLKDIV_CON0 0x20b4
	1448	+#define MT6357_AUDNCP_CLKDIV_CON1 0x20b6
	1449	+#define MT6357_AUDNCP_CLKDIV_CON2 0x20b8
	1450	+#define MT6357_AUDNCP_CLKDIV_CON3 0x20ba
	1451	+#define MT6357_AUDNCP_CLKDIV_CON4 0x20bc
	1452	+#define MT6357_AUD_TOP_MON_CON0 0x20be
	1453	+#define MT6357_AUDIO_DIG_DSN_ID 0x2100
	1454	+#define MT6357_AUDIO_DIG_DSN_REV0 0x2102
	1455	+#define MT6357_AUDIO_DIG_DSN_DBI 0x2104
	1456	+#define MT6357_AUDIO_DIG_DSN_DXI 0x2106
	1457	+#define MT6357_AFE_UL_DL_CON0 0x2108
	1458	+#define MT6357_AFE_DL_SRC2_CON0_L 0x210a
	1459	+#define MT6357_AFE_UL_SRC_CON0_H 0x210c
	1460	+#define MT6357_AFE_UL_SRC_CON0_L 0x210e
	1461	+#define MT6357_AFE_TOP_CON0 0x2110
	1462	+#define MT6357_AUDIO_TOP_CON0 0x2112
	1463	+#define MT6357_AFE_MON_DEBUG0 0x2114
	1464	+#define MT6357_AFUNC_AUD_CON0 0x2116
	1465	+#define MT6357_AFUNC_AUD_CON1 0x2118
	1466	+#define MT6357_AFUNC_AUD_CON2 0x211a
	1467	+#define MT6357_AFUNC_AUD_CON3 0x211c
	1468	+#define MT6357_AFUNC_AUD_CON4 0x211e
	1469	+#define MT6357_AFUNC_AUD_CON5 0x2120
	1470	+#define MT6357_AFUNC_AUD_CON6 0x2122
	1471	+#define MT6357_AFUNC_AUD_MON0 0x2124
	1472	+#define MT6357_AUDRC_TUNE_MON0 0x2126
	1473	+#define MT6357_AFE_ADDA_MTKAIF_FIFO_CFG0 0x2128
	1474	+#define MT6357_AFE_ADDA_MTKAIF_FIFO_LOG_MON1 0x212a
	1475	+#define MT6357_AFE_ADDA_MTKAIF_MON0 0x212c
	1476	+#define MT6357_AFE_ADDA_MTKAIF_MON1 0x212e
	1477	+#define MT6357_AFE_ADDA_MTKAIF_MON2 0x2130
	1478	+#define MT6357_AFE_ADDA_MTKAIF_MON3 0x2132
	1479	+#define MT6357_AFE_ADDA_MTKAIF_CFG0 0x2134
	1480	+#define MT6357_AFE_ADDA_MTKAIF_RX_CFG0 0x2136
	1481	+#define MT6357_AFE_ADDA_MTKAIF_RX_CFG1 0x2138
	1482	+#define MT6357_AFE_ADDA_MTKAIF_RX_CFG2 0x213a
	1483	+#define MT6357_AFE_ADDA_MTKAIF_RX_CFG3 0x213c
	1484	+#define MT6357_AFE_ADDA_MTKAIF_TX_CFG1 0x213e
	1485	+#define MT6357_AFE_SGEN_CFG0 0x2140
	1486	+#define MT6357_AFE_SGEN_CFG1 0x2142
	1487	+#define MT6357_AFE_ADC_ASYNC_FIFO_CFG 0x2144
	1488	+#define MT6357_AFE_DCCLK_CFG0 0x2146
	1489	+#define MT6357_AFE_DCCLK_CFG1 0x2148
	1490	+#define MT6357_AUDIO_DIG_CFG 0x214a
	1491	+#define MT6357_AFE_AUD_PAD_TOP 0x214c
	1492	+#define MT6357_AFE_AUD_PAD_TOP_MON 0x214e
	1493	+#define MT6357_AFE_AUD_PAD_TOP_MON1 0x2150
	1494	+#define MT6357_AUDENC_DSN_ID 0x2180
	1495	+#define MT6357_AUDENC_DSN_REV0 0x2182
	1496	+#define MT6357_AUDENC_DSN_DBI 0x2184
	1497	+#define MT6357_AUDENC_DSN_FPI 0x2186
	1498	+#define MT6357_AUDENC_ANA_CON0 0x2188
	1499	+#define MT6357_AUDENC_ANA_CON1 0x218a
	1500	+#define MT6357_AUDENC_ANA_CON2 0x218c
	1501	+#define MT6357_AUDENC_ANA_CON3 0x218e
	1502	+#define MT6357_AUDENC_ANA_CON4 0x2190
	1503	+#define MT6357_AUDENC_ANA_CON5 0x2192
	1504	+#define MT6357_AUDENC_ANA_CON6 0x2194
	1505	+#define MT6357_AUDENC_ANA_CON7 0x2196
	1506	+#define MT6357_AUDENC_ANA_CON8 0x2198
	1507	+#define MT6357_AUDENC_ANA_CON9 0x219a
	1508	+#define MT6357_AUDENC_ANA_CON10 0x219c
	1509	+#define MT6357_AUDENC_ANA_CON11 0x219e
	1510	+#define MT6357_AUDDEC_DSN_ID 0x2200
	1511	+#define MT6357_AUDDEC_DSN_REV0 0x2202
	1512	+#define MT6357_AUDDEC_DSN_DBI 0x2204
	1513	+#define MT6357_AUDDEC_DSN_FPI 0x2206
	1514	+#define MT6357_AUDDEC_ANA_CON0 0x2208
	1515	+#define MT6357_AUDDEC_ANA_CON1 0x220a
	1516	+#define MT6357_AUDDEC_ANA_CON2 0x220c
	1517	+#define MT6357_AUDDEC_ANA_CON3 0x220e
	1518	+#define MT6357_AUDDEC_ANA_CON4 0x2210
	1519	+#define MT6357_AUDDEC_ANA_CON5 0x2212
	1520	+#define MT6357_AUDDEC_ANA_CON6 0x2214
	1521	+#define MT6357_AUDDEC_ANA_CON7 0x2216
	1522	+#define MT6357_AUDDEC_ANA_CON8 0x2218
	1523	+#define MT6357_AUDDEC_ANA_CON9 0x221a
	1524	+#define MT6357_AUDDEC_ANA_CON10 0x221c
	1525	+#define MT6357_AUDDEC_ANA_CON11 0x221e
	1526	+#define MT6357_AUDDEC_ANA_CON12 0x2220
	1527	+#define MT6357_AUDDEC_ANA_CON13 0x2222
	1528	+#define MT6357_AUDDEC_ELR_NUM 0x2224
	1529	+#define MT6357_AUDDEC_ELR_0 0x2226
	1530	+#define MT6357_AUDZCD_DSN_ID 0x2280
	1531	+#define MT6357_AUDZCD_DSN_REV0 0x2282
	1532	+#define MT6357_AUDZCD_DSN_DBI 0x2284
	1533	+#define MT6357_AUDZCD_DSN_FPI 0x2286
	1534	+#define MT6357_ZCD_CON0 0x2288
	1535	+#define MT6357_ZCD_CON1 0x228a
	1536	+#define MT6357_ZCD_CON2 0x228c
	1537	+#define MT6357_ZCD_CON3 0x228e
	1538	+#define MT6357_ZCD_CON4 0x2290
	1539	+#define MT6357_ZCD_CON5 0x2292
	1540	+#define MT6357_ACCDET_DSN_DIG_ID 0x2300
	1541	+#define MT6357_ACCDET_DSN_DIG_REV0 0x2302
	1542	+#define MT6357_ACCDET_DSN_DBI 0x2304
	1543	+#define MT6357_ACCDET_DSN_FPI 0x2306
	1544	+#define MT6357_ACCDET_CON0 0x2308
	1545	+#define MT6357_ACCDET_CON1 0x230a
	1546	+#define MT6357_ACCDET_CON2 0x230c
	1547	+#define MT6357_ACCDET_CON3 0x230e
	1548	+#define MT6357_ACCDET_CON4 0x2310
	1549	+#define MT6357_ACCDET_CON5 0x2312
	1550	+#define MT6357_ACCDET_CON6 0x2314
	1551	+#define MT6357_ACCDET_CON7 0x2316
	1552	+#define MT6357_ACCDET_CON8 0x2318
	1553	+#define MT6357_ACCDET_CON9 0x231a
	1554	+#define MT6357_ACCDET_CON10 0x231c
	1555	+#define MT6357_ACCDET_CON11 0x231e
	1556	+#define MT6357_ACCDET_CON12 0x2320
	1557	+#define MT6357_ACCDET_CON13 0x2322
	1558	+#define MT6357_ACCDET_CON14 0x2324
	1559	+#define MT6357_ACCDET_CON15 0x2326
	1560	+#define MT6357_ACCDET_CON16 0x2328
	1561	+#define MT6357_ACCDET_CON17 0x232a
	1562	+#define MT6357_ACCDET_CON18 0x232c
	1563	+#define MT6357_ACCDET_CON19 0x232e
	1564	+#define MT6357_ACCDET_CON20 0x2330
	1565	+#define MT6357_ACCDET_CON21 0x2332
	1566	+#define MT6357_ACCDET_CON22 0x2334
	1567	+#define MT6357_ACCDET_CON23 0x2336
	1568	+#define MT6357_ACCDET_CON24 0x2338
	1569	+#define MT6357_ACCDET_CON25 0x233a
	1570	+#define MT6357_ACCDET_CON26 0x233c
	1571	+#define MT6357_ACCDET_CON27 0x233e
	1572	+#define MT6357_ACCDET_CON28 0x2340
	1573	+
	1574	+#endif /* __MFD_MT6357_REGISTERS_H__ */

include/linux/mfd/mt6397/core.h+3−0

@@ -12,6 +12,9 @@ · 11 unmodified lines
12	12
13	13	enum chip_id {
14	14	MT6323_CHIP_ID = 0x23,
	15	+ MT6331_CHIP_ID = 0x20,
	16	+ MT6332_CHIP_ID = 0x20,
	17	+ MT6357_CHIP_ID = 0x57,
15	18	MT6358_CHIP_ID = 0x58,
16	19	MT6359_CHIP_ID = 0x59,
17	20	MT6366_CHIP_ID = 0x66,

include/linux/mfd/t7l66xb.h+0−1

@@ -12,7 +12,6 @@ · 11 unmodified lines
12	12
13	13	struct t7l66xb_platform_data {
14	14	int (enable)(struct platform_device dev);
15		− int (disable)(struct platform_device dev);
16	15	int (suspend)(struct platform_device dev);
17	16	int (resume)(struct platform_device dev);
18	17

include/linux/mfd/tc6387xb.h+0−1

@@ -12,7 +12,6 @@ · 11 unmodified lines
12	12
13	13	struct tc6387xb_platform_data {
14	14	int (enable)(struct platform_device dev);
15		− int (disable)(struct platform_device dev);
16	15	int (suspend)(struct platform_device dev);
17	16	int (resume)(struct platform_device dev);
18	17	};

include/linux/mfd/tc6393xb.h+1−1

@@ -22,7 +22,7 @@ struct tc6393xb_platform_data { · 21 unmodified lines
22	22	u16 scr_gper; /* GP Enable */
23	23
24	24	int (enable)(struct platform_device dev);
25		− int (disable)(struct platform_device dev);
	25	+ void (disable)(struct platform_device dev);
26	26	int (suspend)(struct platform_device dev);
27	27	int (resume)(struct platform_device dev);
28	28

include/linux/mfd/twl.h+0−55

@@ -692,61 +692,6 @@ struct twl4030_audio_data { · 691 unmodified lines
692	692	unsigned int irq_base;
693	693	};
694	694
695		−struct twl4030_platform_data {
696		− struct twl4030_clock_init_data *clock;
697		− struct twl4030_bci_platform_data *bci;
698		− struct twl4030_gpio_platform_data *gpio;
699		− struct twl4030_madc_platform_data *madc;
700		− struct twl4030_keypad_data *keypad;
701		− struct twl4030_usb_data *usb;
702		− struct twl4030_power_data *power;
703		− struct twl4030_audio_data *audio;
704		−
705		− /* Common LDO regulators for TWL4030/TWL6030 */
706		− struct regulator_init_data *vdac;
707		− struct regulator_init_data *vaux1;
708		− struct regulator_init_data *vaux2;
709		− struct regulator_init_data *vaux3;
710		− struct regulator_init_data *vdd1;
711		− struct regulator_init_data *vdd2;
712		− struct regulator_init_data *vdd3;
713		− /* TWL4030 LDO regulators */
714		− struct regulator_init_data *vpll1;
715		− struct regulator_init_data *vpll2;
716		− struct regulator_init_data *vmmc1;
717		− struct regulator_init_data *vmmc2;
718		− struct regulator_init_data *vsim;
719		− struct regulator_init_data *vaux4;
720		− struct regulator_init_data *vio;
721		− struct regulator_init_data *vintana1;
722		− struct regulator_init_data *vintana2;
723		− struct regulator_init_data *vintdig;
724		− /* TWL6030 LDO regulators */
725		− struct regulator_init_data *vmmc;
726		− struct regulator_init_data *vpp;
727		− struct regulator_init_data *vusim;
728		− struct regulator_init_data *vana;
729		− struct regulator_init_data *vcxio;
730		− struct regulator_init_data *vusb;
731		− struct regulator_init_data *clk32kg;
732		− struct regulator_init_data *v1v8;
733		− struct regulator_init_data *v2v1;
734		− /* TWL6032 LDO regulators */
735		− struct regulator_init_data *ldo1;
736		− struct regulator_init_data *ldo2;
737		− struct regulator_init_data *ldo3;
738		− struct regulator_init_data *ldo4;
739		− struct regulator_init_data *ldo5;
740		− struct regulator_init_data *ldo6;
741		− struct regulator_init_data *ldo7;
742		− struct regulator_init_data *ldoln;
743		− struct regulator_init_data *ldousb;
744		− /* TWL6032 DCDC regulators */
745		− struct regulator_init_data *smps3;
746		− struct regulator_init_data *smps4;
747		− struct regulator_init_data *vio6025;
748		−};
749		−
750	695	struct twl_regulator_driver_data {
751	696	int (set_voltage)(void data, int target_uV);
752	697	int (get_voltage)(void data);

include/linux/platform_data/cros_ec_commands.h+2−0

@@ -1300,6 +1300,8 @@ enum ec_feature_code { · 1299 unmodified lines
1300	1300	* mux.
1301	1301	*/
1302	1302	EC_FEATURE_TYPEC_MUX_REQUIRE_AP_ACK = 43,
	1303	+ /* The MCU is a System Companion Processor (SCP) 2nd Core. */
	1304	+ EC_FEATURE_SCP_C1 = 45,
1303	1305	};
1304	1306
1305	1307	#define EC_FEATURE_MASK_0(event_code) BIT(event_code % 32)

include/linux/platform_data/cros_ec_proto.h+1−0

@@ -19,6 +19,7 @@ · 18 unmodified lines
19	19	#define CROS_EC_DEV_ISH_NAME "cros_ish"
20	20	#define CROS_EC_DEV_PD_NAME "cros_pd"
21	21	#define CROS_EC_DEV_SCP_NAME "cros_scp"
	22	+#define CROS_EC_DEV_SCP_C1_NAME "cros_scp_c1"
22	23	#define CROS_EC_DEV_TP_NAME "cros_tp"
23	24
24	25	#define CROS_EC_DEV_EC_INDEX 0

Merge tag 'mfd-next-5.20' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd

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