We no longer use the semaphore sync registers on gen6/7, so including them in the GPU error state is mere noise.
Unified · Split
| @@ -502,13 +502,6 @@ static void error_print_engine(struct drm_i915_error_state_buf *m, · 501 unmodified lines | ||
| 502 | 502 | if (INTEL_GEN(m->i915) >= 6) { |
| 503 | 503 | err_printf(m, " RC PSMI: 0x%08x\n", ee->rc_psmi); |
| 504 | 504 | err_printf(m, " FAULT_REG: 0x%08x\n", ee->fault_reg); |
| 505 | − err_printf(m, " SYNC_0: 0x%08x\n", | |
| 506 | − ee->semaphore_mboxes[0]); | |
| 507 | − err_printf(m, " SYNC_1: 0x%08x\n", | |
| 508 | − ee->semaphore_mboxes[1]); | |
| 509 | − if (HAS_VEBOX(m->i915)) | |
| 510 | − err_printf(m, " SYNC_2: 0x%08x\n", | |
| 511 | − ee->semaphore_mboxes[2]); | |
| 512 | 505 | } |
| 513 | 506 | if (HAS_PPGTT(m->i915)) { |
| 514 | 507 | err_printf(m, " GFX_MODE: 0x%08x\n", ee->vm_info.gfx_mode); |
| @@ -1138,18 +1131,6 @@ static void gem_record_fences(struct i915_gpu_state *error) · 623 unmodified lines | ||
| 1138 | 1131 | error->nfence = i; |
| 1139 | 1132 | } |
| 1140 | 1133 | |
| 1141 | −static void gen6_record_semaphore_state(struct intel_engine_cs *engine, | |
| 1142 | − struct drm_i915_error_engine *ee) | |
| 1143 | −{ | |
| 1144 | − struct drm_i915_private *dev_priv = engine->i915; | |
| 1145 | − | |
| 1146 | − ee->semaphore_mboxes[0] = I915_READ(RING_SYNC_0(engine->mmio_base)); | |
| 1147 | − ee->semaphore_mboxes[1] = I915_READ(RING_SYNC_1(engine->mmio_base)); | |
| 1148 | − if (HAS_VEBOX(dev_priv)) | |
| 1149 | − ee->semaphore_mboxes[2] = | |
| 1150 | − I915_READ(RING_SYNC_2(engine->mmio_base)); | |
| 1151 | −} | |
| 1152 | − | |
| 1153 | 1134 | static void error_record_engine_registers(struct i915_gpu_state *error, |
| 1154 | 1135 | struct intel_engine_cs *engine, |
| 1155 | 1136 | struct drm_i915_error_engine *ee) |
| @@ -1158,12 +1139,10 @@ static void error_record_engine_registers(struct i915_gpu_state *error, · 2 unmodified lines | ||
| 1158 | 1139 | |
| 1159 | 1140 | if (INTEL_GEN(dev_priv) >= 6) { |
| 1160 | 1141 | ee->rc_psmi = I915_READ(RING_PSMI_CTL(engine->mmio_base)); |
| 1161 | − if (INTEL_GEN(dev_priv) >= 8) { | |
| 1142 | + if (INTEL_GEN(dev_priv) >= 8) | |
| 1162 | 1143 | ee->fault_reg = I915_READ(GEN8_RING_FAULT_REG); |
| 1163 | − } else { | |
| 1164 | − gen6_record_semaphore_state(engine, ee); | |
| 1144 | + else | |
| 1165 | 1145 | ee->fault_reg = I915_READ(RING_FAULT_REG(engine)); |
| 1166 | − } | |
| 1167 | 1146 | } |
| 1168 | 1147 | |
| 1169 | 1148 | if (INTEL_GEN(dev_priv) >= 4) { |
| @@ -111,7 +111,6 @@ struct i915_gpu_state { · 110 unmodified lines | ||
| 111 | 111 | u32 fault_reg; |
| 112 | 112 | u64 faddr; |
| 113 | 113 | u32 rc_psmi; /* sleep state */ |
| 114 | − u32 semaphore_mboxes[I915_NUM_ENGINES - 1]; | |
| 115 | 114 | struct intel_instdone instdone; |
| 116 | 115 | |
| 117 | 116 | struct drm_i915_error_context { |