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virtio-gpu: add 3d/virgl support

Add the bits needed for opengl rendering support: query capabilities, new virtio commands, drm ioctls.

Gerd Hoffmann committed 12 years ago

Commit 62fb7a51 parent 7552ed811 files · +1368 −3Browse files

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3 files
  1. include/uapi/drm/Kbuild +1 −0
  2. include/uapi/drm/virtgpu_drm.h +167 −0
  3. include/uapi/linux/virtio_gpu.h +111 −1
include/uapi/drm/Kbuild+1−0
@@ -17,3 +17,4 @@ header-y += tegra_drm.h · 16 unmodified lines
1717 header-y += via_drm.h
1818 header-y += vmwgfx_drm.h
1919 header-y += msm_drm.h
20+header-y += virtgpu_drm.h
include/uapi/drm/virtgpu_drm.h+167−0
@@ -0,0 +1,167 @@
1+/*
2+ * Copyright 2013 Red Hat
3+ * All Rights Reserved.
4+ *
5+ * Permission is hereby granted, free of charge, to any person obtaining a
6+ * copy of this software and associated documentation files (the "Software"),
7+ * to deal in the Software without restriction, including without limitation
8+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9+ * and/or sell copies of the Software, and to permit persons to whom the
10+ * Software is furnished to do so, subject to the following conditions:
11+ *
12+ * The above copyright notice and this permission notice (including the next
13+ * paragraph) shall be included in all copies or substantial portions of the
14+ * Software.
15+ *
16+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19+ * THE AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22+ * OTHER DEALINGS IN THE SOFTWARE.
23+ */
24+#ifndef VIRTGPU_DRM_H
25+#define VIRTGPU_DRM_H
26+
27+#include <stddef.h>
28+#include "drm/drm.h"
29+
30+/* Please note that modifications to all structs defined here are
31+ * subject to backwards-compatibility constraints.
32+ *
33+ * Do not use pointers, use uint64_t instead for 32 bit / 64 bit user/kernel
34+ * compatibility Keep fields aligned to their size
35+ */
36+
37+#define DRM_VIRTGPU_MAP 0x01
38+#define DRM_VIRTGPU_EXECBUFFER 0x02
39+#define DRM_VIRTGPU_GETPARAM 0x03
40+#define DRM_VIRTGPU_RESOURCE_CREATE 0x04
41+#define DRM_VIRTGPU_RESOURCE_INFO 0x05
42+#define DRM_VIRTGPU_TRANSFER_FROM_HOST 0x06
43+#define DRM_VIRTGPU_TRANSFER_TO_HOST 0x07
44+#define DRM_VIRTGPU_WAIT 0x08
45+#define DRM_VIRTGPU_GET_CAPS 0x09
46+
47+struct drm_virtgpu_map {
48+ uint64_t offset; /* use for mmap system call */
49+ uint32_t handle;
50+ uint32_t pad;
51+};
52+
53+struct drm_virtgpu_execbuffer {
54+ uint32_t flags; /* for future use */
55+ uint32_t size;
56+ uint64_t command; /* void* */
57+ uint64_t bo_handles;
58+ uint32_t num_bo_handles;
59+ uint32_t pad;
60+};
61+
62+#define VIRTGPU_PARAM_3D_FEATURES 1 /* do we have 3D features in the hw */
63+
64+struct drm_virtgpu_getparam {
65+ uint64_t param;
66+ uint64_t value;
67+};
68+
69+/* NO_BO flags? NO resource flag? */
70+/* resource flag for y_0_top */
71+struct drm_virtgpu_resource_create {
72+ uint32_t target;
73+ uint32_t format;
74+ uint32_t bind;
75+ uint32_t width;
76+ uint32_t height;
77+ uint32_t depth;
78+ uint32_t array_size;
79+ uint32_t last_level;
80+ uint32_t nr_samples;
81+ uint32_t flags;
82+ uint32_t bo_handle; /* if this is set - recreate a new resource attached to this bo ? */
83+ uint32_t res_handle; /* returned by kernel */
84+ uint32_t size; /* validate transfer in the host */
85+ uint32_t stride; /* validate transfer in the host */
86+};
87+
88+struct drm_virtgpu_resource_info {
89+ uint32_t bo_handle;
90+ uint32_t res_handle;
91+ uint32_t size;
92+ uint32_t stride;
93+};
94+
95+struct drm_virtgpu_3d_box {
96+ uint32_t x;
97+ uint32_t y;
98+ uint32_t z;
99+ uint32_t w;
100+ uint32_t h;
101+ uint32_t d;
102+};
103+
104+struct drm_virtgpu_3d_transfer_to_host {
105+ uint32_t bo_handle;
106+ struct drm_virtgpu_3d_box box;
107+ uint32_t level;
108+ uint32_t offset;
109+};
110+
111+struct drm_virtgpu_3d_transfer_from_host {
112+ uint32_t bo_handle;
113+ struct drm_virtgpu_3d_box box;
114+ uint32_t level;
115+ uint32_t offset;
116+};
117+
118+#define VIRTGPU_WAIT_NOWAIT 1 /* like it */
119+struct drm_virtgpu_3d_wait {
120+ uint32_t handle; /* 0 is an invalid handle */
121+ uint32_t flags;
122+};
123+
124+struct drm_virtgpu_get_caps {
125+ uint32_t cap_set_id;
126+ uint32_t cap_set_ver;
127+ uint64_t addr;
128+ uint32_t size;
129+ uint32_t pad;
130+};
131+
132+#define DRM_IOCTL_VIRTGPU_MAP \
133+ DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_MAP, struct drm_virtgpu_map)
134+
135+#define DRM_IOCTL_VIRTGPU_EXECBUFFER \
136+ DRM_IOW(DRM_COMMAND_BASE + DRM_VIRTGPU_EXECBUFFER,\
137+ struct drm_virtgpu_execbuffer)
138+
139+#define DRM_IOCTL_VIRTGPU_GETPARAM \
140+ DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_GETPARAM,\
141+ struct drm_virtgpu_getparam)
142+
143+#define DRM_IOCTL_VIRTGPU_RESOURCE_CREATE \
144+ DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_RESOURCE_CREATE, \
145+ struct drm_virtgpu_resource_create)
146+
147+#define DRM_IOCTL_VIRTGPU_RESOURCE_INFO \
148+ DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_RESOURCE_INFO, \
149+ struct drm_virtgpu_resource_info)
150+
151+#define DRM_IOCTL_VIRTGPU_TRANSFER_FROM_HOST \
152+ DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_TRANSFER_FROM_HOST, \
153+ struct drm_virtgpu_3d_transfer_from_host)
154+
155+#define DRM_IOCTL_VIRTGPU_TRANSFER_TO_HOST \
156+ DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_TRANSFER_TO_HOST, \
157+ struct drm_virtgpu_3d_transfer_to_host)
158+
159+#define DRM_IOCTL_VIRTGPU_WAIT \
160+ DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_WAIT, \
161+ struct drm_virtgpu_3d_wait)
162+
163+#define DRM_IOCTL_VIRTGPU_GET_CAPS \
164+ DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_GET_CAPS, \
165+ struct drm_virtgpu_get_caps)
166+
167+#endif
include/uapi/linux/virtio_gpu.h+111−1
@@ -40,6 +40,8 @@ · 39 unmodified lines
4040
4141 #include <linux/types.h>
4242
43+#define VIRTIO_GPU_F_VIRGL 0
44+
4345 enum virtio_gpu_ctrl_type {
4446 VIRTIO_GPU_UNDEFINED = 0,
4547
@@ -52,6 +54,18 @@ enum virtio_gpu_ctrl_type { · 6 unmodified lines
5254 VIRTIO_GPU_CMD_TRANSFER_TO_HOST_2D,
5355 VIRTIO_GPU_CMD_RESOURCE_ATTACH_BACKING,
5456 VIRTIO_GPU_CMD_RESOURCE_DETACH_BACKING,
57+ VIRTIO_GPU_CMD_GET_CAPSET_INFO,
58+ VIRTIO_GPU_CMD_GET_CAPSET,
59+
60+ /* 3d commands */
61+ VIRTIO_GPU_CMD_CTX_CREATE = 0x0200,
62+ VIRTIO_GPU_CMD_CTX_DESTROY,
63+ VIRTIO_GPU_CMD_CTX_ATTACH_RESOURCE,
64+ VIRTIO_GPU_CMD_CTX_DETACH_RESOURCE,
65+ VIRTIO_GPU_CMD_RESOURCE_CREATE_3D,
66+ VIRTIO_GPU_CMD_TRANSFER_TO_HOST_3D,
67+ VIRTIO_GPU_CMD_TRANSFER_FROM_HOST_3D,
68+ VIRTIO_GPU_CMD_SUBMIT_3D,
5569
5670 /* cursor commands */
5771 VIRTIO_GPU_CMD_UPDATE_CURSOR = 0x0300,
@@ -60,6 +74,8 @@ enum virtio_gpu_ctrl_type { · 2 unmodified lines
6074 /* success responses */
6175 VIRTIO_GPU_RESP_OK_NODATA = 0x1100,
6276 VIRTIO_GPU_RESP_OK_DISPLAY_INFO,
77+ VIRTIO_GPU_RESP_OK_CAPSET_INFO,
78+ VIRTIO_GPU_RESP_OK_CAPSET,
6379
6480 /* error responses */
6581 VIRTIO_GPU_RESP_ERR_UNSPEC = 0x1200,
@@ -180,13 +196,107 @@ struct virtio_gpu_resp_display_info { · 114 unmodified lines
180196 } pmodes[VIRTIO_GPU_MAX_SCANOUTS];
181197 };
182198
199+/* data passed in the control vq, 3d related */
200+
201+struct virtio_gpu_box {
202+ __le32 x, y, z;
203+ __le32 w, h, d;
204+};
205+
206+/* VIRTIO_GPU_CMD_TRANSFER_TO_HOST_3D, VIRTIO_GPU_CMD_TRANSFER_FROM_HOST_3D */
207+struct virtio_gpu_transfer_host_3d {
208+ struct virtio_gpu_ctrl_hdr hdr;
209+ struct virtio_gpu_box box;
210+ __le64 offset;
211+ __le32 resource_id;
212+ __le32 level;
213+ __le32 stride;
214+ __le32 layer_stride;
215+};
216+
217+/* VIRTIO_GPU_CMD_RESOURCE_CREATE_3D */
218+#define VIRTIO_GPU_RESOURCE_FLAG_Y_0_TOP (1 << 0)
219+struct virtio_gpu_resource_create_3d {
220+ struct virtio_gpu_ctrl_hdr hdr;
221+ __le32 resource_id;
222+ __le32 target;
223+ __le32 format;
224+ __le32 bind;
225+ __le32 width;
226+ __le32 height;
227+ __le32 depth;
228+ __le32 array_size;
229+ __le32 last_level;
230+ __le32 nr_samples;
231+ __le32 flags;
232+ __le32 padding;
233+};
234+
235+/* VIRTIO_GPU_CMD_CTX_CREATE */
236+struct virtio_gpu_ctx_create {
237+ struct virtio_gpu_ctrl_hdr hdr;
238+ __le32 nlen;
239+ __le32 padding;
240+ char debug_name[64];
241+};
242+
243+/* VIRTIO_GPU_CMD_CTX_DESTROY */
244+struct virtio_gpu_ctx_destroy {
245+ struct virtio_gpu_ctrl_hdr hdr;
246+};
247+
248+/* VIRTIO_GPU_CMD_CTX_ATTACH_RESOURCE, VIRTIO_GPU_CMD_CTX_DETACH_RESOURCE */
249+struct virtio_gpu_ctx_resource {
250+ struct virtio_gpu_ctrl_hdr hdr;
251+ __le32 resource_id;
252+ __le32 padding;
253+};
254+
255+/* VIRTIO_GPU_CMD_SUBMIT_3D */
256+struct virtio_gpu_cmd_submit {
257+ struct virtio_gpu_ctrl_hdr hdr;
258+ __le32 size;
259+ __le32 padding;
260+};
261+
262+#define VIRTIO_GPU_CAPSET_VIRGL 1
263+
264+/* VIRTIO_GPU_CMD_GET_CAPSET_INFO */
265+struct virtio_gpu_get_capset_info {
266+ struct virtio_gpu_ctrl_hdr hdr;
267+ __le32 capset_index;
268+ __le32 padding;
269+};
270+
271+/* VIRTIO_GPU_RESP_OK_CAPSET_INFO */
272+struct virtio_gpu_resp_capset_info {
273+ struct virtio_gpu_ctrl_hdr hdr;
274+ __le32 capset_id;
275+ __le32 capset_max_version;
276+ __le32 capset_max_size;
277+ __le32 padding;
278+};
279+
280+/* VIRTIO_GPU_CMD_GET_CAPSET */
281+struct virtio_gpu_get_capset {
282+ struct virtio_gpu_ctrl_hdr hdr;
283+ __le32 capset_id;
284+ __le32 capset_version;
285+};
286+
287+/* VIRTIO_GPU_RESP_OK_CAPSET */
288+struct virtio_gpu_resp_capset {
289+ struct virtio_gpu_ctrl_hdr hdr;
290+ uint8_t capset_data[];
291+};
292+
183293 #define VIRTIO_GPU_EVENT_DISPLAY (1 << 0)
184294
185295 struct virtio_gpu_config {
186296 __u32 events_read;
187297 __u32 events_clear;
188298 __u32 num_scanouts;
189− __u32 reserved;
299+ __u32 num_capsets;
190300 };
191301
192302 /* simple formats for fbcon/X use */