Pull arm-soc bug fixes from Olof Johansson: "A couple of samsung clock locking fixes, at91 device tree gpio configuration fix and a couple more for shmobile and i.MX. All small targeted fixes." * tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: ARM i.MX25: Make timer irq work again ARM: imx: armadillo5x0: Fix illegal register access ARM: shmobile: kzm9g: bugfix: correct mmcif interrupt settings ARM: SAMSUNG: Use spin_lock_{irqsave,irqrestore} in clk_set_rate ARM: at91: fix missing #interrupt-cells on gpio-controller ARM: SAMSUNG: use spin_lock_irqsave() in clk_set_parent
Unified · Split
| @@ -104,6 +104,7 @@ · 103 unmodified lines | ||
| 104 | 104 | #gpio-cells = <2>; |
| 105 | 105 | gpio-controller; |
| 106 | 106 | interrupt-controller; |
| 107 | + #interrupt-cells = <2>; | |
| 107 | 108 | }; |
| 108 | 109 | |
| 109 | 110 | pioB: gpio@fffff600 { |
| @@ -113,6 +114,7 @@ · 3 unmodified lines | ||
| 113 | 114 | #gpio-cells = <2>; |
| 114 | 115 | gpio-controller; |
| 115 | 116 | interrupt-controller; |
| 117 | + #interrupt-cells = <2>; | |
| 116 | 118 | }; |
| 117 | 119 | |
| 118 | 120 | pioC: gpio@fffff800 { |
| @@ -122,6 +124,7 @@ · 3 unmodified lines | ||
| 122 | 124 | #gpio-cells = <2>; |
| 123 | 125 | gpio-controller; |
| 124 | 126 | interrupt-controller; |
| 127 | + #interrupt-cells = <2>; | |
| 125 | 128 | }; |
| 126 | 129 | |
| 127 | 130 | dbgu: serial@fffff200 { |
| @@ -95,6 +95,7 @@ · 94 unmodified lines | ||
| 95 | 95 | #gpio-cells = <2>; |
| 96 | 96 | gpio-controller; |
| 97 | 97 | interrupt-controller; |
| 98 | + #interrupt-cells = <2>; | |
| 98 | 99 | }; |
| 99 | 100 | |
| 100 | 101 | pioB: gpio@fffff400 { |
| @@ -104,6 +105,7 @@ · 3 unmodified lines | ||
| 104 | 105 | #gpio-cells = <2>; |
| 105 | 106 | gpio-controller; |
| 106 | 107 | interrupt-controller; |
| 108 | + #interrupt-cells = <2>; | |
| 107 | 109 | }; |
| 108 | 110 | |
| 109 | 111 | pioC: gpio@fffff600 { |
| @@ -113,6 +115,7 @@ · 3 unmodified lines | ||
| 113 | 115 | #gpio-cells = <2>; |
| 114 | 116 | gpio-controller; |
| 115 | 117 | interrupt-controller; |
| 118 | + #interrupt-cells = <2>; | |
| 116 | 119 | }; |
| 117 | 120 | |
| 118 | 121 | pioD: gpio@fffff800 { |
| @@ -122,6 +125,7 @@ · 3 unmodified lines | ||
| 122 | 125 | #gpio-cells = <2>; |
| 123 | 126 | gpio-controller; |
| 124 | 127 | interrupt-controller; |
| 128 | + #interrupt-cells = <2>; | |
| 125 | 129 | }; |
| 126 | 130 | |
| 127 | 131 | pioE: gpio@fffffa00 { |
| @@ -131,6 +135,7 @@ · 3 unmodified lines | ||
| 131 | 135 | #gpio-cells = <2>; |
| 132 | 136 | gpio-controller; |
| 133 | 137 | interrupt-controller; |
| 138 | + #interrupt-cells = <2>; | |
| 134 | 139 | }; |
| 135 | 140 | |
| 136 | 141 | dbgu: serial@ffffee00 { |
| @@ -113,6 +113,7 @@ · 112 unmodified lines | ||
| 113 | 113 | #gpio-cells = <2>; |
| 114 | 114 | gpio-controller; |
| 115 | 115 | interrupt-controller; |
| 116 | + #interrupt-cells = <2>; | |
| 116 | 117 | }; |
| 117 | 118 | |
| 118 | 119 | pioB: gpio@fffff400 { |
| @@ -122,6 +123,7 @@ · 3 unmodified lines | ||
| 122 | 123 | #gpio-cells = <2>; |
| 123 | 124 | gpio-controller; |
| 124 | 125 | interrupt-controller; |
| 126 | + #interrupt-cells = <2>; | |
| 125 | 127 | }; |
| 126 | 128 | |
| 127 | 129 | pioC: gpio@fffff600 { |
| @@ -131,6 +133,7 @@ · 3 unmodified lines | ||
| 131 | 133 | #gpio-cells = <2>; |
| 132 | 134 | gpio-controller; |
| 133 | 135 | interrupt-controller; |
| 136 | + #interrupt-cells = <2>; | |
| 134 | 137 | }; |
| 135 | 138 | |
| 136 | 139 | pioD: gpio@fffff800 { |
| @@ -140,6 +143,7 @@ · 3 unmodified lines | ||
| 140 | 143 | #gpio-cells = <2>; |
| 141 | 144 | gpio-controller; |
| 142 | 145 | interrupt-controller; |
| 146 | + #interrupt-cells = <2>; | |
| 143 | 147 | }; |
| 144 | 148 | |
| 145 | 149 | pioE: gpio@fffffa00 { |
| @@ -149,6 +153,7 @@ · 3 unmodified lines | ||
| 149 | 153 | #gpio-cells = <2>; |
| 150 | 154 | gpio-controller; |
| 151 | 155 | interrupt-controller; |
| 156 | + #interrupt-cells = <2>; | |
| 152 | 157 | }; |
| 153 | 158 | |
| 154 | 159 | dbgu: serial@ffffee00 { |
| @@ -107,6 +107,7 @@ · 106 unmodified lines | ||
| 107 | 107 | #gpio-cells = <2>; |
| 108 | 108 | gpio-controller; |
| 109 | 109 | interrupt-controller; |
| 110 | + #interrupt-cells = <2>; | |
| 110 | 111 | }; |
| 111 | 112 | |
| 112 | 113 | pioB: gpio@fffff600 { |
| @@ -116,6 +117,7 @@ · 3 unmodified lines | ||
| 116 | 117 | #gpio-cells = <2>; |
| 117 | 118 | gpio-controller; |
| 118 | 119 | interrupt-controller; |
| 120 | + #interrupt-cells = <2>; | |
| 119 | 121 | }; |
| 120 | 122 | |
| 121 | 123 | pioC: gpio@fffff800 { |
| @@ -125,6 +127,7 @@ · 3 unmodified lines | ||
| 125 | 127 | #gpio-cells = <2>; |
| 126 | 128 | gpio-controller; |
| 127 | 129 | interrupt-controller; |
| 130 | + #interrupt-cells = <2>; | |
| 128 | 131 | }; |
| 129 | 132 | |
| 130 | 133 | pioD: gpio@fffffa00 { |
| @@ -134,6 +137,7 @@ · 3 unmodified lines | ||
| 134 | 137 | #gpio-cells = <2>; |
| 135 | 138 | gpio-controller; |
| 136 | 139 | interrupt-controller; |
| 140 | + #interrupt-cells = <2>; | |
| 137 | 141 | }; |
| 138 | 142 | |
| 139 | 143 | dbgu: serial@fffff200 { |
| @@ -115,6 +115,7 @@ · 114 unmodified lines | ||
| 115 | 115 | #gpio-cells = <2>; |
| 116 | 116 | gpio-controller; |
| 117 | 117 | interrupt-controller; |
| 118 | + #interrupt-cells = <2>; | |
| 118 | 119 | }; |
| 119 | 120 | |
| 120 | 121 | pioB: gpio@fffff600 { |
| @@ -124,6 +125,7 @@ · 3 unmodified lines | ||
| 124 | 125 | #gpio-cells = <2>; |
| 125 | 126 | gpio-controller; |
| 126 | 127 | interrupt-controller; |
| 128 | + #interrupt-cells = <2>; | |
| 127 | 129 | }; |
| 128 | 130 | |
| 129 | 131 | pioC: gpio@fffff800 { |
| @@ -133,6 +135,7 @@ · 3 unmodified lines | ||
| 133 | 135 | #gpio-cells = <2>; |
| 134 | 136 | gpio-controller; |
| 135 | 137 | interrupt-controller; |
| 138 | + #interrupt-cells = <2>; | |
| 136 | 139 | }; |
| 137 | 140 | |
| 138 | 141 | pioD: gpio@fffffa00 { |
| @@ -142,6 +145,7 @@ · 3 unmodified lines | ||
| 142 | 145 | #gpio-cells = <2>; |
| 143 | 146 | gpio-controller; |
| 144 | 147 | interrupt-controller; |
| 148 | + #interrupt-cells = <2>; | |
| 145 | 149 | }; |
| 146 | 150 | |
| 147 | 151 | dbgu: serial@fffff200 { |
| @@ -241,6 +241,6 @@ int __init mx25_clocks_init(void) · 240 unmodified lines | ||
| 241 | 241 | clk_register_clkdev(clk[sdma_ahb], "ahb", "imx35-sdma"); |
| 242 | 242 | clk_register_clkdev(clk[iim_ipg], "iim", NULL); |
| 243 | 243 | |
| 244 | − mxc_timer_init(MX25_IO_ADDRESS(MX25_GPT1_BASE_ADDR), 54); | |
| 244 | + mxc_timer_init(MX25_IO_ADDRESS(MX25_GPT1_BASE_ADDR), MX25_INT_GPT1); | |
| 245 | 245 | return 0; |
| 246 | 246 | } |
| @@ -526,7 +526,8 @@ static void __init armadillo5x0_init(void) · 525 unmodified lines | ||
| 526 | 526 | imx31_add_mxc_nand(&armadillo5x0_nand_board_info); |
| 527 | 527 | |
| 528 | 528 | /* set NAND page size to 2k if not configured via boot mode pins */ |
| 529 | − __raw_writel(__raw_readl(MXC_CCM_RCSR) | (1 << 30), MXC_CCM_RCSR); | |
| 529 | + __raw_writel(__raw_readl(mx3_ccm_base + MXC_CCM_RCSR) | | |
| 530 | + (1 << 30), mx3_ccm_base + MXC_CCM_RCSR); | |
| 530 | 531 | |
| 531 | 532 | /* RTC */ |
| 532 | 533 | /* Get RTC IRQ and register the chip */ |
| @@ -346,11 +346,11 @@ static struct resource sh_mmcif_resources[] = { · 345 unmodified lines | ||
| 346 | 346 | .flags = IORESOURCE_MEM, |
| 347 | 347 | }, |
| 348 | 348 | [1] = { |
| 349 | − .start = gic_spi(141), | |
| 349 | + .start = gic_spi(140), | |
| 350 | 350 | .flags = IORESOURCE_IRQ, |
| 351 | 351 | }, |
| 352 | 352 | [2] = { |
| 353 | − .start = gic_spi(140), | |
| 353 | + .start = gic_spi(141), | |
| 354 | 354 | .flags = IORESOURCE_IRQ, |
| 355 | 355 | }, |
| 356 | 356 | }; |
| @@ -98,6 +98,7 @@ · 97 unmodified lines | ||
| 98 | 98 | #define MX25_INT_UART1 (NR_IRQS_LEGACY + 45) |
| 99 | 99 | #define MX25_INT_GPIO2 (NR_IRQS_LEGACY + 51) |
| 100 | 100 | #define MX25_INT_GPIO1 (NR_IRQS_LEGACY + 52) |
| 101 | +#define MX25_INT_GPT1 (NR_IRQS_LEGACY + 54) | |
| 101 | 102 | #define MX25_INT_FEC (NR_IRQS_LEGACY + 57) |
| 102 | 103 | |
| 103 | 104 | #define MX25_DMA_REQ_SSI2_RX1 22 |
| @@ -144,6 +144,7 @@ long clk_round_rate(struct clk *clk, unsigned long rate) · 143 unmodified lines | ||
| 144 | 144 | |
| 145 | 145 | int clk_set_rate(struct clk *clk, unsigned long rate) |
| 146 | 146 | { |
| 147 | + unsigned long flags; | |
| 147 | 148 | int ret; |
| 148 | 149 | |
| 149 | 150 | if (IS_ERR(clk)) |
| @@ -159,9 +160,9 @@ int clk_set_rate(struct clk *clk, unsigned long rate) · 9 unmodified lines | ||
| 159 | 160 | if (clk->ops == NULL || clk->ops->set_rate == NULL) |
| 160 | 161 | return -EINVAL; |
| 161 | 162 | |
| 162 | − spin_lock(&clocks_lock); | |
| 163 | + spin_lock_irqsave(&clocks_lock, flags); | |
| 163 | 164 | ret = (clk->ops->set_rate)(clk, rate); |
| 164 | − spin_unlock(&clocks_lock); | |
| 165 | + spin_unlock_irqrestore(&clocks_lock, flags); | |
| 165 | 166 | |
| 166 | 167 | return ret; |
| 167 | 168 | } |
| @@ -173,17 +174,18 @@ struct clk *clk_get_parent(struct clk *clk) · 5 unmodified lines | ||
| 173 | 174 | |
| 174 | 175 | int clk_set_parent(struct clk *clk, struct clk *parent) |
| 175 | 176 | { |
| 177 | + unsigned long flags; | |
| 176 | 178 | int ret = 0; |
| 177 | 179 | |
| 178 | 180 | if (IS_ERR(clk)) |
| 179 | 181 | return -EINVAL; |
| 180 | 182 | |
| 181 | − spin_lock(&clocks_lock); | |
| 183 | + spin_lock_irqsave(&clocks_lock, flags); | |
| 182 | 184 | |
| 183 | 185 | if (clk->ops && clk->ops->set_parent) |
| 184 | 186 | ret = (clk->ops->set_parent)(clk, parent); |
| 185 | 187 | |
| 186 | − spin_unlock(&clocks_lock); | |
| 188 | + spin_unlock_irqrestore(&clocks_lock, flags); | |
| 187 | 189 | |
| 188 | 190 | return ret; |
| 189 | 191 | } |