History

Merge branch 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc

* 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc: [POWERPC] Fix G5 DART (IOMMU) race causing occasional data corruption [POWERPC] Fix MMIO ops to provide expected barrier behaviour [POWERPC] Fix interrupt clearing in kdump shutdown sequence [POWERPC] update prep_defconfig [POWERPC] kdump: Support kernels having 64k page size. [POWERPC] Implement PowerPC futex_atomic_cmpxchg_inatomic(). [POWERPC] Add new, missing argument to of_irq_map_raw() for 86xx. [POWERPC] Update defconfigs

Linus Torvalds committed 20 years ago

Commit 63b98082 parents 1883c5a eeac5c126 files · +1102 −524Browse files

Showing the changes to include (7 of 26 files). Show all

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7 files
  1. include/asm-powerpc/eeh.h +3 −0
  2. include/asm-powerpc/futex.h +27 −1
  3. include/asm-powerpc/io.h +28 −15
  4. include/asm-powerpc/kdump.h +1 −1
  5. include/asm-powerpc/paca.h +1 −0
  6. include/asm-powerpc/spinlock.h +17 −0
  7. include/asm-ppc/io.h +11 −9
include/asm-powerpc/eeh.h+3−0
@@ -205,6 +205,7 @@ static inline void eeh_memset_io(volatile void __iomem *addr, int c, · 204 unmodified lines
205205 lc |= lc << 8;
206206 lc |= lc << 16;
207207
208+ __asm__ __volatile__ ("sync" : : : "memory");
208209 while(n && !EEH_CHECK_ALIGN(p, 4)) {
209210 *((volatile u8 *)p) = c;
210211 p++;
@@ -229,6 +230,7 @@ static inline void eeh_memcpy_fromio(void *dest, const volatile void __iomem *sr · 18 unmodified lines
229230 void *destsave = dest;
230231 unsigned long nsave = n;
231232
233+ __asm__ __volatile__ ("sync" : : : "memory");
232234 while(n && (!EEH_CHECK_ALIGN(vsrc, 4) || !EEH_CHECK_ALIGN(dest, 4))) {
233235 *((u8 *)dest) = *((volatile u8 *)vsrc);
234236 __asm__ __volatile__ ("eieio" : : : "memory");
@@ -266,6 +268,7 @@ static inline void eeh_memcpy_toio(volatile void __iomem *dest, const void *src, · 31 unmodified lines
266268 {
267269 void *vdest = (void __force *) dest;
268270
271+ __asm__ __volatile__ ("sync" : : : "memory");
269272 while(n && (!EEH_CHECK_ALIGN(vdest, 4) || !EEH_CHECK_ALIGN(src, 4))) {
270273 *((volatile u8 *)vdest) = *((u8 *)src);
271274 src++;
include/asm-powerpc/futex.h+27−1
@@ -84,7 +84,33 @@ static inline int futex_atomic_op_inuser (int encoded_op, int __user *uaddr) · 83 unmodified lines
8484 static inline int
8585 futex_atomic_cmpxchg_inatomic(int __user *uaddr, int oldval, int newval)
8686 {
87− return -ENOSYS;
87+ int prev;
88+
89+ if (!access_ok(VERIFY_WRITE, uaddr, sizeof(int)))
90+ return -EFAULT;
91+
92+ __asm__ __volatile__ (
93+ LWSYNC_ON_SMP
94+"1: lwarx %0,0,%2 # futex_atomic_cmpxchg_inatomic\n\
95+ cmpw 0,%0,%3\n\
96+ bne- 3f\n"
97+ PPC405_ERR77(0,%2)
98+"2: stwcx. %4,0,%2\n\
99+ bne- 1b\n"
100+ ISYNC_ON_SMP
101+"3: .section .fixup,\"ax\"\n\
102+4: li %0,%5\n\
103+ b 3b\n\
104+ .previous\n\
105+ .section __ex_table,\"a\"\n\
106+ .align 3\n\
107+ " PPC_LONG "1b,4b,2b,4b\n\
108+ .previous" \
109+ : "=&r" (prev), "+m" (*uaddr)
110+ : "r" (uaddr), "r" (oldval), "r" (newval), "i" (-EFAULT)
111+ : "cc", "memory");
112+
113+ return prev;
88114 }
89115
90116 #endif /* __KERNEL__ */
include/asm-powerpc/io.h+28−15
@@ -19,6 +19,7 @@ extern int check_legacy_ioport(unsigned long base_port); · 18 unmodified lines
1919 #include <linux/compiler.h>
2020 #include <asm/page.h>
2121 #include <asm/byteorder.h>
22+#include <asm/paca.h>
2223 #ifdef CONFIG_PPC_ISERIES
2324 #include <asm/iseries/iseries_io.h>
2425 #endif
@@ -162,7 +163,11 @@ extern void _outsw_ns(volatile u16 __iomem *port, const void *buf, int ns); · 137 unmodified lines
162163 extern void _insl_ns(volatile u32 __iomem *port, void *buf, int nl);
163164 extern void _outsl_ns(volatile u32 __iomem *port, const void *buf, int nl);
164165
165−#define mmiowb()
166+static inline void mmiowb(void)
167+{
168+ __asm__ __volatile__ ("sync" : : : "memory");
169+ get_paca()->io_sync = 0;
170+}
166171
167172 /*
168173 * output pause versions need a delay at least for the
@@ -278,22 +283,23 @@ static inline int in_8(const volatile unsigned char __iomem *addr) · 109 unmodified lines
278283 {
279284 int ret;
280285
281− __asm__ __volatile__("lbz%U1%X1 %0,%1; twi 0,%0,0; isync"
286+ __asm__ __volatile__("sync; lbz%U1%X1 %0,%1; twi 0,%0,0; isync"
282287 : "=r" (ret) : "m" (*addr));
283288 return ret;
284289 }
285290
286291 static inline void out_8(volatile unsigned char __iomem *addr, int val)
287292 {
288− __asm__ __volatile__("stb%U0%X0 %1,%0; sync"
293+ __asm__ __volatile__("sync; stb%U0%X0 %1,%0"
289294 : "=m" (*addr) : "r" (val));
295+ get_paca()->io_sync = 1;
290296 }
291297
292298 static inline int in_le16(const volatile unsigned short __iomem *addr)
293299 {
294300 int ret;
295301
296− __asm__ __volatile__("lhbrx %0,0,%1; twi 0,%0,0; isync"
302+ __asm__ __volatile__("sync; lhbrx %0,0,%1; twi 0,%0,0; isync"
297303 : "=r" (ret) : "r" (addr), "m" (*addr));
298304 return ret;
299305 }
@@ -302,28 +308,30 @@ static inline int in_be16(const volatile unsigned short __iomem *addr) · 2 unmodified lines
302308 {
303309 int ret;
304310
305− __asm__ __volatile__("lhz%U1%X1 %0,%1; twi 0,%0,0; isync"
311+ __asm__ __volatile__("sync; lhz%U1%X1 %0,%1; twi 0,%0,0; isync"
306312 : "=r" (ret) : "m" (*addr));
307313 return ret;
308314 }
309315
310316 static inline void out_le16(volatile unsigned short __iomem *addr, int val)
311317 {
312− __asm__ __volatile__("sthbrx %1,0,%2; sync"
318+ __asm__ __volatile__("sync; sthbrx %1,0,%2"
313319 : "=m" (*addr) : "r" (val), "r" (addr));
320+ get_paca()->io_sync = 1;
314321 }
315322
316323 static inline void out_be16(volatile unsigned short __iomem *addr, int val)
317324 {
318− __asm__ __volatile__("sth%U0%X0 %1,%0; sync"
325+ __asm__ __volatile__("sync; sth%U0%X0 %1,%0"
319326 : "=m" (*addr) : "r" (val));
327+ get_paca()->io_sync = 1;
320328 }
321329
322330 static inline unsigned in_le32(const volatile unsigned __iomem *addr)
323331 {
324332 unsigned ret;
325333
326− __asm__ __volatile__("lwbrx %0,0,%1; twi 0,%0,0; isync"
334+ __asm__ __volatile__("sync; lwbrx %0,0,%1; twi 0,%0,0; isync"
327335 : "=r" (ret) : "r" (addr), "m" (*addr));
328336 return ret;
329337 }
@@ -332,21 +340,23 @@ static inline unsigned in_be32(const volatile unsigned __iomem *addr) · 2 unmodified lines
332340 {
333341 unsigned ret;
334342
335− __asm__ __volatile__("lwz%U1%X1 %0,%1; twi 0,%0,0; isync"
343+ __asm__ __volatile__("sync; lwz%U1%X1 %0,%1; twi 0,%0,0; isync"
336344 : "=r" (ret) : "m" (*addr));
337345 return ret;
338346 }
339347
340348 static inline void out_le32(volatile unsigned __iomem *addr, int val)
341349 {
342− __asm__ __volatile__("stwbrx %1,0,%2; sync" : "=m" (*addr)
350+ __asm__ __volatile__("sync; stwbrx %1,0,%2" : "=m" (*addr)
343351 : "r" (val), "r" (addr));
352+ get_paca()->io_sync = 1;
344353 }
345354
346355 static inline void out_be32(volatile unsigned __iomem *addr, int val)
347356 {
348− __asm__ __volatile__("stw%U0%X0 %1,%0; sync"
357+ __asm__ __volatile__("sync; stw%U0%X0 %1,%0"
349358 : "=m" (*addr) : "r" (val));
359+ get_paca()->io_sync = 1;
350360 }
351361
352362 static inline unsigned long in_le64(const volatile unsigned long __iomem *addr)
@@ -354,6 +364,7 @@ static inline unsigned long in_le64(const volatile unsigned long __iomem *addr) · 1 unmodified line
354364 unsigned long tmp, ret;
355365
356366 __asm__ __volatile__(
367+ "sync\n"
357368 "ld %1,0(%2)\n"
358369 "twi 0,%1,0\n"
359370 "isync\n"
@@ -372,7 +383,7 @@ static inline unsigned long in_be64(const volatile unsigned long __iomem *addr) · 12 unmodified lines
372383 {
373384 unsigned long ret;
374385
375− __asm__ __volatile__("ld%U1%X1 %0,%1; twi 0,%0,0; isync"
386+ __asm__ __volatile__("sync; ld%U1%X1 %0,%1; twi 0,%0,0; isync"
376387 : "=r" (ret) : "m" (*addr));
377388 return ret;
378389 }
@@ -389,14 +400,16 @@ static inline void out_le64(volatile unsigned long __iomem *addr, unsigned long · 10 unmodified lines
389400 "rldicl %1,%1,32,0\n"
390401 "rlwimi %0,%1,8,8,31\n"
391402 "rlwimi %0,%1,24,16,23\n"
392− "std %0,0(%3)\n"
393− "sync"
403+ "sync\n"
404+ "std %0,0(%3)"
394405 : "=&r" (tmp) , "=&r" (val) : "1" (val) , "b" (addr) , "m" (*addr));
406+ get_paca()->io_sync = 1;
395407 }
396408
397409 static inline void out_be64(volatile unsigned long __iomem *addr, unsigned long val)
398410 {
399− __asm__ __volatile__("std%U0%X0 %1,%0; sync" : "=m" (*addr) : "r" (val));
411+ __asm__ __volatile__("sync; std%U0%X0 %1,%0" : "=m" (*addr) : "r" (val));
412+ get_paca()->io_sync = 1;
400413 }
401414
402415 #ifndef CONFIG_PPC_ISERIES
include/asm-powerpc/kdump.h+1−1
@@ -7,7 +7,7 @@ · 6 unmodified lines
77 /* How many bytes to reserve at zero for kdump. The reserve limit should
88 * be greater or equal to the trampoline's end address.
99 * Reserve to the end of the FWNMI area, see head_64.S */
10−#define KDUMP_RESERVE_LIMIT 0x8000
10+#define KDUMP_RESERVE_LIMIT 0x10000 /* 64K */
1111
1212 #ifdef CONFIG_CRASH_DUMP
1313
include/asm-powerpc/paca.h+1−0
@@ -93,6 +93,7 @@ struct paca_struct { · 92 unmodified lines
9393 u64 saved_r1; /* r1 save for RTAS calls */
9494 u64 saved_msr; /* MSR saved here by enter_rtas */
9595 u8 proc_enabled; /* irq soft-enable flag */
96+ u8 io_sync; /* writel() needs spin_unlock sync */
9697
9798 /* Stuff for accurate time accounting */
9899 u64 user_time; /* accumulated usermode TB ticks */
include/asm-powerpc/spinlock.h+17−0
@@ -36,6 +36,19 @@ · 35 unmodified lines
3636 #define LOCK_TOKEN 1
3737 #endif
3838
39+#if defined(CONFIG_PPC64) && defined(CONFIG_SMP)
40+#define CLEAR_IO_SYNC (get_paca()->io_sync = 0)
41+#define SYNC_IO do { \
42+ if (unlikely(get_paca()->io_sync)) { \
43+ mb(); \
44+ get_paca()->io_sync = 0; \
45+ } \
46+ } while (0)
47+#else
48+#define CLEAR_IO_SYNC
49+#define SYNC_IO
50+#endif
51+
3952 /*
4053 * This returns the old value in the lock, so we succeeded
4154 * in getting the lock if the return value is 0.
@@ -61,6 +74,7 @@ static __inline__ unsigned long __spin_trylock(raw_spinlock_t *lock) · 19 unmodified lines
6174
6275 static int __inline__ __raw_spin_trylock(raw_spinlock_t *lock)
6376 {
77+ CLEAR_IO_SYNC;
6478 return __spin_trylock(lock) == 0;
6579 }
6680
@@ -91,6 +105,7 @@ extern void __rw_yield(raw_rwlock_t *lock); · 24 unmodified lines
91105
92106 static void __inline__ __raw_spin_lock(raw_spinlock_t *lock)
93107 {
108+ CLEAR_IO_SYNC;
94109 while (1) {
95110 if (likely(__spin_trylock(lock) == 0))
96111 break;
@@ -107,6 +122,7 @@ static void __inline__ __raw_spin_lock_flags(raw_spinlock_t *lock, unsigned long · 10 unmodified lines
107122 {
108123 unsigned long flags_dis;
109124
125+ CLEAR_IO_SYNC;
110126 while (1) {
111127 if (likely(__spin_trylock(lock) == 0))
112128 break;
@@ -124,6 +140,7 @@ static void __inline__ __raw_spin_lock_flags(raw_spinlock_t *lock, unsigned long · 11 unmodified lines
124140
125141 static __inline__ void __raw_spin_unlock(raw_spinlock_t *lock)
126142 {
143+ SYNC_IO;
127144 __asm__ __volatile__("# __raw_spin_unlock\n\t"
128145 LWSYNC_ON_SMP: : :"memory");
129146 lock->slock = 0;
include/asm-ppc/io.h+11−9
@@ -63,7 +63,7 @@ extern inline int in_8(const volatile unsigned char __iomem *addr) · 62 unmodified lines
6363 int ret;
6464
6565 __asm__ __volatile__(
66− "lbz%U1%X1 %0,%1;\n"
66+ "sync; lbz%U1%X1 %0,%1;\n"
6767 "twi 0,%0,0;\n"
6868 "isync" : "=r" (ret) : "m" (*addr));
6969 return ret;
@@ -78,7 +78,7 @@ extern inline int in_le16(const volatile unsigned short __iomem *addr) · 8 unmodified lines
7878 {
7979 int ret;
8080
81− __asm__ __volatile__("lhbrx %0,0,%1;\n"
81+ __asm__ __volatile__("sync; lhbrx %0,0,%1;\n"
8282 "twi 0,%0,0;\n"
8383 "isync" : "=r" (ret) :
8484 "r" (addr), "m" (*addr));
@@ -89,7 +89,7 @@ extern inline int in_be16(const volatile unsigned short __iomem *addr) · 4 unmodified lines
8989 {
9090 int ret;
9191
92− __asm__ __volatile__("lhz%U1%X1 %0,%1;\n"
92+ __asm__ __volatile__("sync; lhz%U1%X1 %0,%1;\n"
9393 "twi 0,%0,0;\n"
9494 "isync" : "=r" (ret) : "m" (*addr));
9595 return ret;
@@ -97,20 +97,20 @@ extern inline int in_be16(const volatile unsigned short __iomem *addr) · 1 unmodified line
9797
9898 extern inline void out_le16(volatile unsigned short __iomem *addr, int val)
9999 {
100− __asm__ __volatile__("sthbrx %1,0,%2; eieio" : "=m" (*addr) :
100+ __asm__ __volatile__("sync; sthbrx %1,0,%2" : "=m" (*addr) :
101101 "r" (val), "r" (addr));
102102 }
103103
104104 extern inline void out_be16(volatile unsigned short __iomem *addr, int val)
105105 {
106− __asm__ __volatile__("sth%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val));
106+ __asm__ __volatile__("sync; sth%U0%X0 %1,%0" : "=m" (*addr) : "r" (val));
107107 }
108108
109109 extern inline unsigned in_le32(const volatile unsigned __iomem *addr)
110110 {
111111 unsigned ret;
112112
113− __asm__ __volatile__("lwbrx %0,0,%1;\n"
113+ __asm__ __volatile__("sync; lwbrx %0,0,%1;\n"
114114 "twi 0,%0,0;\n"
115115 "isync" : "=r" (ret) :
116116 "r" (addr), "m" (*addr));
@@ -121,7 +121,7 @@ extern inline unsigned in_be32(const volatile unsigned __iomem *addr) · 4 unmodified lines
121121 {
122122 unsigned ret;
123123
124− __asm__ __volatile__("lwz%U1%X1 %0,%1;\n"
124+ __asm__ __volatile__("sync; lwz%U1%X1 %0,%1;\n"
125125 "twi 0,%0,0;\n"
126126 "isync" : "=r" (ret) : "m" (*addr));
127127 return ret;
@@ -129,13 +129,13 @@ extern inline unsigned in_be32(const volatile unsigned __iomem *addr) · 1 unmodified line
129129
130130 extern inline void out_le32(volatile unsigned __iomem *addr, int val)
131131 {
132− __asm__ __volatile__("stwbrx %1,0,%2; eieio" : "=m" (*addr) :
132+ __asm__ __volatile__("sync; stwbrx %1,0,%2" : "=m" (*addr) :
133133 "r" (val), "r" (addr));
134134 }
135135
136136 extern inline void out_be32(volatile unsigned __iomem *addr, int val)
137137 {
138− __asm__ __volatile__("stw%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val));
138+ __asm__ __volatile__("sync; stw%U0%X0 %1,%0" : "=m" (*addr) : "r" (val));
139139 }
140140 #if defined (CONFIG_8260_PCI9)
141141 #define readb(addr) in_8((volatile u8 *)(addr))
@@ -259,6 +259,7 @@ extern __inline__ unsigned int name(unsigned int port) \ · 117 unmodified lines
259259 { \
260260 unsigned int x; \
261261 __asm__ __volatile__( \
262+ "sync\n" \
262263 "0:" op " %0,0,%1\n" \
263264 "1: twi 0,%0,0\n" \
264265 "2: isync\n" \
@@ -284,6 +285,7 @@ extern __inline__ unsigned int name(unsigned int port) \ · 19 unmodified lines
284285 extern __inline__ void name(unsigned int val, unsigned int port) \
285286 { \
286287 __asm__ __volatile__( \
288+ "sync\n" \
287289 "0:" op " %0,0,%1\n" \
288290 "1: sync\n" \
289291 "2:\n" \