It used to be a gap in port definitions after PORT_MAX_8250. Since the new drivers are coming the gap become shorter and shorter until the commit a2d6a987bfe4 ("serial: 8250: Add new port type for TI DA8xx/66AK2x") completely removed it. So, while type here is just a formality, make things a little bit more explicit for this driver and move port types to UAPI header. Note, it uses two types for now.
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| @@ -57,7 +57,6 @@ · 56 unmodified lines | |||
| 57 | #define PORT_RT2880 29 /* Ralink RT2880 internal UART */ | 57 | #define PORT_RT2880 29 /* Ralink RT2880 internal UART */ |
| 58 | #define PORT_16550A_FSL64 30 /* Freescale 16550 UART with 64 FIFOs */ | 58 | #define PORT_16550A_FSL64 30 /* Freescale 16550 UART with 64 FIFOs */ |
| 59 | #define PORT_DA830 31 /* TI DA8xx/66AK2x */ | 59 | #define PORT_DA830 31 /* TI DA8xx/66AK2x */ |
| 60 | #define PORT_MAX_8250 31 /* max port ID */ | ||
| 61 | 60 | ||
| 62 | /* | 61 | /* |
| 63 | * ARM specific type numbers. These are not currently guaranteed | 62 | * ARM specific type numbers. These are not currently guaranteed |
| @@ -77,6 +76,10 @@ · 13 unmodified lines | |||
| 77 | #define PORT_SUNZILOG 38 | 76 | #define PORT_SUNZILOG 38 |
| 78 | #define PORT_SUNSAB 39 | 77 | #define PORT_SUNSAB 39 |
| 79 | 78 | ||
| 79 | /* Intel EG20 */ | ||
| 80 | #define PORT_PCH_8LINE 44 | ||
| 81 | #define PORT_PCH_2LINE 45 | ||
| 82 | |||
| 80 | /* DEC */ | 83 | /* DEC */ |
| 81 | #define PORT_DZ 46 | 84 | #define PORT_DZ 46 |
| 82 | #define PORT_ZS 47 | 85 | #define PORT_ZS 47 |