drm/tegra: Changes for v4.12-rc1 This contains various fixes to the host1x driver as well as a plug for a leak of kernel pointers to userspace. A fairly big addition this time around is the Video Image Composer (VIC) support that can be used to accelerate some 2D and image compositing operations. Furthermore the driver now supports FB modifiers, so we no longer rely on a custom IOCTL to set those. Finally this contains a few preparatory patches for Tegra186 support which unfortunately didn't quite make it this time, but will hopefully be ready for v4.13. * tag 'drm/tegra/for-4.12-rc1' of git://anongit.freedesktop.org/tegra/linux: gpu: host1x: Fix host1x driver shutdown gpu: host1x: Support module reset gpu: host1x: Sort includes alphabetically drm/tegra: Add VIC support dt-bindings: Add bindings for the Tegra VIC drm/tegra: Add falcon helper library drm/tegra: Add Tegra DRM allocation API drm/tegra: Add tiling FB modifiers drm/tegra: Don't leak kernel pointer to userspace drm/tegra: Protect IOMMU operations by mutex drm/tegra: Enable IOVA API when IOMMU support is enabled gpu: host1x: Add IOMMU support gpu: host1x: Fix potential out-of-bounds access iommu/iova: Fix compile error with CONFIG_IOMMU_IOVA=m iommu: Add dummy implementations for !IOMMU_IOVA MAINTAINERS: Add related headers to IOMMU section iommu/iova: Consolidate code for adding new node to iovad domain rbtree
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| @@ -306,6 +306,51 @@ extern "C" { · 305 unmodified lines | ||
| 306 | 306 | */ |
| 307 | 307 | #define DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED fourcc_mod_code(VIVANTE, 4) |
| 308 | 308 | |
| 309 | + | |
| 310 | +/* NVIDIA Tegra frame buffer modifiers */ | |
| 311 | + | |
| 312 | +/* | |
| 313 | + * Some modifiers take parameters, for example the number of vertical GOBs in | |
| 314 | + * a block. Reserve the lower 32 bits for parameters | |
| 315 | + */ | |
| 316 | +#define __fourcc_mod_tegra_mode_shift 32 | |
| 317 | +#define fourcc_mod_tegra_code(val, params) \ | |
| 318 | + fourcc_mod_code(NV, ((((__u64)val) << __fourcc_mod_tegra_mode_shift) | params)) | |
| 319 | +#define fourcc_mod_tegra_mod(m) \ | |
| 320 | + (m & ~((1ULL << __fourcc_mod_tegra_mode_shift) - 1)) | |
| 321 | +#define fourcc_mod_tegra_param(m) \ | |
| 322 | + (m & ((1ULL << __fourcc_mod_tegra_mode_shift) - 1)) | |
| 323 | + | |
| 324 | +/* | |
| 325 | + * Tegra Tiled Layout, used by Tegra 2, 3 and 4. | |
| 326 | + * | |
| 327 | + * Pixels are arranged in simple tiles of 16 x 16 bytes. | |
| 328 | + */ | |
| 329 | +#define NV_FORMAT_MOD_TEGRA_TILED fourcc_mod_tegra_code(1, 0) | |
| 330 | + | |
| 331 | +/* | |
| 332 | + * Tegra 16Bx2 Block Linear layout, used by TK1/TX1 | |
| 333 | + * | |
| 334 | + * Pixels are arranged in 64x8 Groups Of Bytes (GOBs). GOBs are then stacked | |
| 335 | + * vertically by a power of 2 (1 to 32 GOBs) to form a block. | |
| 336 | + * | |
| 337 | + * Within a GOB, data is ordered as 16B x 2 lines sectors laid in Z-shape. | |
| 338 | + * | |
| 339 | + * Parameter 'v' is the log2 encoding of the number of GOBs stacked vertically. | |
| 340 | + * Valid values are: | |
| 341 | + * | |
| 342 | + * 0 == ONE_GOB | |
| 343 | + * 1 == TWO_GOBS | |
| 344 | + * 2 == FOUR_GOBS | |
| 345 | + * 3 == EIGHT_GOBS | |
| 346 | + * 4 == SIXTEEN_GOBS | |
| 347 | + * 5 == THIRTYTWO_GOBS | |
| 348 | + * | |
| 349 | + * Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format | |
| 350 | + * in full detail. | |
| 351 | + */ | |
| 352 | +#define NV_FORMAT_MOD_TEGRA_16BX2_BLOCK(v) fourcc_mod_tegra_code(2, v) | |
| 353 | + | |
| 309 | 354 | #if defined(__cplusplus) |
| 310 | 355 | } |
| 311 | 356 | #endif |