AQE (Applicaton Qrisc Engine) is required to support VK ray-pipeline. Two conditions should be met to use this HW: 1. AQE firmware should be loaded and programmed 2. Preemption support Expose a new MSM_PARAM to allow userspace to query its support.
Unified · Split
| @@ -2604,6 +2604,17 @@ static int a6xx_set_supported_hw(struct device *dev, struct a6xx_gpu *a6xx_gpu, · 2603 unmodified lines | |||
| 2604 | return 0; | 2604 | return 0; |
| 2605 | } | 2605 | } |
| 2606 | 2606 | ||
| 2607 | static bool a6xx_aqe_is_enabled(struct adreno_gpu *adreno_gpu) | ||
| 2608 | { | ||
| 2609 | struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); | ||
| 2610 | |||
| 2611 | /* | ||
| 2612 | * AQE uses preemption context record as scratch pad, so check if | ||
| 2613 | * preemption is enabled | ||
| 2614 | */ | ||
| 2615 | return (adreno_gpu->base.nr_rings > 1) && !!a6xx_gpu->aqe_bo; | ||
| 2616 | } | ||
| 2617 | |||
| 2607 | static struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) | 2618 | static struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) |
| 2608 | { | 2619 | { |
| 2609 | struct msm_drm_private *priv = dev->dev_private; | 2620 | struct msm_drm_private *priv = dev->dev_private; |
| @@ -2803,6 +2814,7 @@ const struct adreno_gpu_funcs a7xx_gpu_funcs = { · 193 unmodified lines | |||
| 2803 | .bus_halt = a6xx_bus_clear_pending_transactions, | 2814 | .bus_halt = a6xx_bus_clear_pending_transactions, |
| 2804 | .mmu_fault_handler = a6xx_fault_handler, | 2815 | .mmu_fault_handler = a6xx_fault_handler, |
| 2805 | .gx_is_on = a7xx_gmu_gx_is_on, | 2816 | .gx_is_on = a7xx_gmu_gx_is_on, |
| 2817 | .aqe_is_enabled = a6xx_aqe_is_enabled, | ||
| 2806 | }; | 2818 | }; |
| 2807 | 2819 | ||
| 2808 | const struct adreno_gpu_funcs a8xx_gpu_funcs = { | 2820 | const struct adreno_gpu_funcs a8xx_gpu_funcs = { |
| @@ -2831,4 +2843,5 @@ const struct adreno_gpu_funcs a8xx_gpu_funcs = { · 22 unmodified lines | |||
| 2831 | .bus_halt = a8xx_bus_clear_pending_transactions, | 2843 | .bus_halt = a8xx_bus_clear_pending_transactions, |
| 2832 | .mmu_fault_handler = a8xx_fault_handler, | 2844 | .mmu_fault_handler = a8xx_fault_handler, |
| 2833 | .gx_is_on = a8xx_gmu_gx_is_on, | 2845 | .gx_is_on = a8xx_gmu_gx_is_on, |
| 2846 | .aqe_is_enabled = a6xx_aqe_is_enabled, | ||
| 2834 | }; | 2847 | }; |
| @@ -441,6 +441,10 @@ int adreno_get_param(struct msm_gpu *gpu, struct msm_context *ctx, · 440 unmodified lines | |||
| 441 | case MSM_PARAM_HAS_PRR: | 441 | case MSM_PARAM_HAS_PRR: |
| 442 | *value = adreno_smmu_has_prr(gpu); | 442 | *value = adreno_smmu_has_prr(gpu); |
| 443 | return 0; | 443 | return 0; |
| 444 | case MSM_PARAM_AQE: | ||
| 445 | *value = !!(adreno_gpu->funcs->aqe_is_enabled && | ||
| 446 | adreno_gpu->funcs->aqe_is_enabled(adreno_gpu)); | ||
| 447 | return 0; | ||
| 444 | default: | 448 | default: |
| 445 | return UERR(EINVAL, drm, "%s: invalid param: %u", gpu->name, param); | 449 | return UERR(EINVAL, drm, "%s: invalid param: %u", gpu->name, param); |
| 446 | } | 450 | } |
| @@ -80,6 +80,7 @@ struct adreno_gpu_funcs { · 79 unmodified lines | |||
| 80 | void (*bus_halt)(struct adreno_gpu *adreno_gpu, bool gx_off); | 80 | void (*bus_halt)(struct adreno_gpu *adreno_gpu, bool gx_off); |
| 81 | int (*mmu_fault_handler)(void *arg, unsigned long iova, int flags, void *data); | 81 | int (*mmu_fault_handler)(void *arg, unsigned long iova, int flags, void *data); |
| 82 | bool (*gx_is_on)(struct adreno_gpu *adreno_gpu); | 82 | bool (*gx_is_on)(struct adreno_gpu *adreno_gpu); |
| 83 | bool (*aqe_is_enabled)(struct adreno_gpu *adreno_gpu); | ||
| 83 | }; | 84 | }; |
| 84 | 85 | ||
| 85 | struct adreno_reglist { | 86 | struct adreno_reglist { |
| @@ -117,6 +117,7 @@ struct drm_msm_timespec { · 116 unmodified lines | |||
| 117 | * ioctl will throw -EPIPE. | 117 | * ioctl will throw -EPIPE. |
| 118 | */ | 118 | */ |
| 119 | #define MSM_PARAM_EN_VM_BIND 0x16 /* WO, once */ | 119 | #define MSM_PARAM_EN_VM_BIND 0x16 /* WO, once */ |
| 120 | #define MSM_PARAM_AQE 0x17 /* RO */ | ||
| 120 | 121 | ||
| 121 | /* For backwards compat. The original support for preemption was based on | 122 | /* For backwards compat. The original support for preemption was based on |
| 122 | * a single ring per priority level so # of priority levels equals the # | 123 | * a single ring per priority level so # of priority levels equals the # |