The V3D engine has various hardware counters which might be interesting to userspace performance analysis tools. Expose new ioctls to create/destroy a performance monitor object and query the counter values of this perfmance monitor. Note that a perfomance monitor is given an ID that is only valid on the file descriptor it has been allocated from. A performance monitor can be attached to a CL submission and the driver will enable HW counters for this request and update the performance monitor values at the end of the job.
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| @@ -42,6 +42,9 @@ extern "C" { · 41 unmodified lines | ||
| 42 | 42 | #define DRM_VC4_GET_TILING 0x09 |
| 43 | 43 | #define DRM_VC4_LABEL_BO 0x0a |
| 44 | 44 | #define DRM_VC4_GEM_MADVISE 0x0b |
| 45 | +#define DRM_VC4_PERFMON_CREATE 0x0c | |
| 46 | +#define DRM_VC4_PERFMON_DESTROY 0x0d | |
| 47 | +#define DRM_VC4_PERFMON_GET_VALUES 0x0e | |
| 45 | 48 | |
| 46 | 49 | #define DRM_IOCTL_VC4_SUBMIT_CL DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_SUBMIT_CL, struct drm_vc4_submit_cl) |
| 47 | 50 | #define DRM_IOCTL_VC4_WAIT_SEQNO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_WAIT_SEQNO, struct drm_vc4_wait_seqno) |
| @@ -55,6 +58,9 @@ extern "C" { · 7 unmodified lines | ||
| 55 | 58 | #define DRM_IOCTL_VC4_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_TILING, struct drm_vc4_get_tiling) |
| 56 | 59 | #define DRM_IOCTL_VC4_LABEL_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_LABEL_BO, struct drm_vc4_label_bo) |
| 57 | 60 | #define DRM_IOCTL_VC4_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GEM_MADVISE, struct drm_vc4_gem_madvise) |
| 61 | +#define DRM_IOCTL_VC4_PERFMON_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_PERFMON_CREATE, struct drm_vc4_perfmon_create) | |
| 62 | +#define DRM_IOCTL_VC4_PERFMON_DESTROY DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_PERFMON_DESTROY, struct drm_vc4_perfmon_destroy) | |
| 63 | +#define DRM_IOCTL_VC4_PERFMON_GET_VALUES DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_PERFMON_GET_VALUES, struct drm_vc4_perfmon_get_values) | |
| 58 | 64 | |
| 59 | 65 | struct drm_vc4_submit_rcl_surface { |
| 60 | 66 | __u32 hindex; /* Handle index, or ~0 if not present. */ |
| @@ -173,6 +179,15 @@ struct drm_vc4_submit_cl { · 112 unmodified lines | ||
| 173 | 179 | * wait ioctl). |
| 174 | 180 | */ |
| 175 | 181 | __u64 seqno; |
| 182 | + | |
| 183 | + /* ID of the perfmon to attach to this job. 0 means no perfmon. */ | |
| 184 | + __u32 perfmonid; | |
| 185 | + | |
| 186 | + /* Unused field to align this struct on 64 bits. Must be set to 0. | |
| 187 | + * If one ever needs to add an u32 field to this struct, this field | |
| 188 | + * can be used. | |
| 189 | + */ | |
| 190 | + __u32 pad2; | |
| 176 | 191 | }; |
| 177 | 192 | |
| 178 | 193 | /** |
| @@ -308,6 +323,7 @@ struct drm_vc4_get_hang_state { · 129 unmodified lines | ||
| 308 | 323 | #define DRM_VC4_PARAM_SUPPORTS_THREADED_FS 5 |
| 309 | 324 | #define DRM_VC4_PARAM_SUPPORTS_FIXED_RCL_ORDER 6 |
| 310 | 325 | #define DRM_VC4_PARAM_SUPPORTS_MADVISE 7 |
| 326 | +#define DRM_VC4_PARAM_SUPPORTS_PERFMON 8 | |
| 311 | 327 | |
| 312 | 328 | struct drm_vc4_get_param { |
| 313 | 329 | __u32 param; |
| @@ -352,6 +368,66 @@ struct drm_vc4_gem_madvise { · 38 unmodified lines | ||
| 352 | 368 | __u32 pad; |
| 353 | 369 | }; |
| 354 | 370 | |
| 371 | +enum { | |
| 372 | + VC4_PERFCNT_FEP_VALID_PRIMS_NO_RENDER, | |
| 373 | + VC4_PERFCNT_FEP_VALID_PRIMS_RENDER, | |
| 374 | + VC4_PERFCNT_FEP_CLIPPED_QUADS, | |
| 375 | + VC4_PERFCNT_FEP_VALID_QUADS, | |
| 376 | + VC4_PERFCNT_TLB_QUADS_NOT_PASSING_STENCIL, | |
| 377 | + VC4_PERFCNT_TLB_QUADS_NOT_PASSING_Z_AND_STENCIL, | |
| 378 | + VC4_PERFCNT_TLB_QUADS_PASSING_Z_AND_STENCIL, | |
| 379 | + VC4_PERFCNT_TLB_QUADS_ZERO_COVERAGE, | |
| 380 | + VC4_PERFCNT_TLB_QUADS_NON_ZERO_COVERAGE, | |
| 381 | + VC4_PERFCNT_TLB_QUADS_WRITTEN_TO_COLOR_BUF, | |
| 382 | + VC4_PERFCNT_PLB_PRIMS_OUTSIDE_VIEWPORT, | |
| 383 | + VC4_PERFCNT_PLB_PRIMS_NEED_CLIPPING, | |
| 384 | + VC4_PERFCNT_PSE_PRIMS_REVERSED, | |
| 385 | + VC4_PERFCNT_QPU_TOTAL_IDLE_CYCLES, | |
| 386 | + VC4_PERFCNT_QPU_TOTAL_CLK_CYCLES_VERTEX_COORD_SHADING, | |
| 387 | + VC4_PERFCNT_QPU_TOTAL_CLK_CYCLES_FRAGMENT_SHADING, | |
| 388 | + VC4_PERFCNT_QPU_TOTAL_CLK_CYCLES_EXEC_VALID_INST, | |
| 389 | + VC4_PERFCNT_QPU_TOTAL_CLK_CYCLES_WAITING_TMUS, | |
| 390 | + VC4_PERFCNT_QPU_TOTAL_CLK_CYCLES_WAITING_SCOREBOARD, | |
| 391 | + VC4_PERFCNT_QPU_TOTAL_CLK_CYCLES_WAITING_VARYINGS, | |
| 392 | + VC4_PERFCNT_QPU_TOTAL_INST_CACHE_HIT, | |
| 393 | + VC4_PERFCNT_QPU_TOTAL_INST_CACHE_MISS, | |
| 394 | + VC4_PERFCNT_QPU_TOTAL_UNIFORM_CACHE_HIT, | |
| 395 | + VC4_PERFCNT_QPU_TOTAL_UNIFORM_CACHE_MISS, | |
| 396 | + VC4_PERFCNT_TMU_TOTAL_TEXT_QUADS_PROCESSED, | |
| 397 | + VC4_PERFCNT_TMU_TOTAL_TEXT_CACHE_MISS, | |
| 398 | + VC4_PERFCNT_VPM_TOTAL_CLK_CYCLES_VDW_STALLED, | |
| 399 | + VC4_PERFCNT_VPM_TOTAL_CLK_CYCLES_VCD_STALLED, | |
| 400 | + VC4_PERFCNT_L2C_TOTAL_L2_CACHE_HIT, | |
| 401 | + VC4_PERFCNT_L2C_TOTAL_L2_CACHE_MISS, | |
| 402 | + VC4_PERFCNT_NUM_EVENTS, | |
| 403 | +}; | |
| 404 | + | |
| 405 | +#define DRM_VC4_MAX_PERF_COUNTERS 16 | |
| 406 | + | |
| 407 | +struct drm_vc4_perfmon_create { | |
| 408 | + __u32 id; | |
| 409 | + __u32 ncounters; | |
| 410 | + __u8 events[DRM_VC4_MAX_PERF_COUNTERS]; | |
| 411 | +}; | |
| 412 | + | |
| 413 | +struct drm_vc4_perfmon_destroy { | |
| 414 | + __u32 id; | |
| 415 | +}; | |
| 416 | + | |
| 417 | +/* | |
| 418 | + * Returns the values of the performance counters tracked by this | |
| 419 | + * perfmon (as an array of ncounters u64 values). | |
| 420 | + * | |
| 421 | + * No implicit synchronization is performed, so the user has to | |
| 422 | + * guarantee that any jobs using this perfmon have already been | |
| 423 | + * completed (probably by blocking on the seqno returned by the | |
| 424 | + * last exec that used the perfmon). | |
| 425 | + */ | |
| 426 | +struct drm_vc4_perfmon_get_values { | |
| 427 | + __u32 id; | |
| 428 | + __u64 values_ptr; | |
| 429 | +}; | |
| 430 | + | |
| 355 | 431 | #if defined(__cplusplus) |
| 356 | 432 | } |
| 357 | 433 | #endif |