Merge tag 'drm-fixes-for-v4.16-rc5' of git://people.freedesktop.org/~airlied/linux

Pull drm fixes from Dave Airlie: "There are a small set of sun4i and i915 fixes, and many more amdgpu fixes: sun4i: - divide by zero fix - clock and LVDS fixes i915: - fix for perf - race fix amdgpu: - a bit more than we are normally comfortable with at this point, however it does fix a lot of display issues with the new DC code which result in black screens in various configurations along with some run of the mill gpu configuration fixes. I'm happy enough that the fixes are limited to the DC code and should fix a bunch of issues on the new raven ridge APUs that we are seeing shipped now" * tag 'drm-fixes-for-v4.16-rc5' of git://people.freedesktop.org/~airlied/linux: (42 commits) drm/amd/display: validate plane format on primary plane drm/amdgpu:Always save uvd vcpu_bo in VM Mode drm/amdgpu:Correct max uvd handles drm/amd/display: early return if not in vga mode in disable_vga drm/amd/display: Fix takover from VGA mode drm/amd/display: Fix memleaks when atomic check fails. drm/amd/display: Return success when enabling interrupt drm/amd/display: Use crtc enable/disable_vblank hooks drm/amd/display: update infoframe after dig fe is turned on drm/amd/display: fix boot-up on vega10 drm/amd/display: fix cursor related Pstate hang drm/amd/display: Set irq state only on existing crtcs drm/amd/display: Fixed non-native modes not lighting up drm/amd/display: Call update_stream_signal directly from amdgpu_dm drm/amd/display: Make create_stream_for_sink more consistent drm/amd/display: Don't block dual-link DVI modes drm/amd/display: Don't allow dual-link DVI on all ASICs. drm/amd/display: Pass signal directly to enable_tmds_output drm/amd/display: Remove unnecessary fail labels in create_stream_for_sink drm/amd/display: Move MAX_TMDS_CLOCK define to header ...

Linus Torvalds committed 8 years ago

Commit 65307f22 parents dfbab3f b0655d641 files · +464 −366Browse files

Unified · Split

41 files

drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c +3 −0
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c +1 −1
drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c +8 −5
drivers/gpu/drm/amd/amdgpu/dce_v6_0.c +1 −1
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c +2 −28
drivers/gpu/drm/amd/amdgpu/si.c +10 −12
drivers/gpu/drm/amd/amdgpu/si_dpm.c +13 −37
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +117 −48
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c +2 −4
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +6 −0
drivers/gpu/drm/amd/display/dc/core/dc.c +3 −3
drivers/gpu/drm/amd/display/dc/core/dc_link.c +1 −2
drivers/gpu/drm/amd/display/dc/core/dc_resource.c +0 −3
drivers/gpu/drm/amd/display/dc/core/dc_stream.c +8 −68
drivers/gpu/drm/amd/display/dc/dc.h +2 −1
drivers/gpu/drm/amd/display/dc/dc_stream.h +2 −0
drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h +9 −1
drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c +18 −20
drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h +1 −2
drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c +1 −0
drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +77 −14
drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c +18 −0
drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c +2 −0
drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c +2 −0
drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c +1 −0
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +60 −5
drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h +1 −2
drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h +3 −0
drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c +1 −1
drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.c +1 −2
drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h +0 −5
drivers/gpu/drm/amd/display/include/signal_types.h +5 −0
drivers/gpu/drm/i915/i915_gem.c +5 −1
drivers/gpu/drm/i915/i915_perf.c +13 −27
drivers/gpu/drm/i915/intel_lrc.c +5 −0
drivers/gpu/drm/radeon/cik.c +2 −29
drivers/gpu/drm/sun4i/sun4i_crtc.c +4 −0
drivers/gpu/drm/sun4i/sun4i_dotclock.c +4 −1
drivers/gpu/drm/sun4i/sun4i_rgb.c +2 −0
drivers/gpu/drm/sun4i/sun4i_tcon.c +49 −43
drivers/gpu/drm/sun4i/sun4i_tcon.h +1 −0

drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c+3−0

@@ -540,6 +540,9 @@ int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, · 539 unmodified lines
540	540	size_t size;
541	541	u32 retry = 3;
542	542
	543	+ if (amdgpu_acpi_pcie_notify_device_ready(adev))
	544	+ return -EINVAL;
	545	+
543	546	/* Get the device handle */
544	547	handle = ACPI_HANDLE(&adev->pdev->dev);
545	548	if (!handle)

drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c+1−1

@@ -481,7 +481,7 @@ static ssize_t amdgpu_debugfs_ring_read(struct file f, char __user buf, · 480 unmodified lines
481	481	result = 0;
482	482
483	483	if (*pos < 12) {
484		− early[0] = amdgpu_ring_get_rptr(ring);
	484	+ early[0] = amdgpu_ring_get_rptr(ring) & ring->buf_mask;
485	485	early[1] = amdgpu_ring_get_wptr(ring) & ring->buf_mask;
486	486	early[2] = ring->wptr & ring->buf_mask;
487	487	for (i = *pos / 4; i < 3 && size; i++) {

drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c+8−5

@@ -299,12 +299,15 @@ int amdgpu_uvd_suspend(struct amdgpu_device *adev) · 298 unmodified lines
299	299
300	300	cancel_delayed_work_sync(&adev->uvd.idle_work);
301	301
302		− for (i = 0; i < adev->uvd.max_handles; ++i)
303		− if (atomic_read(&adev->uvd.handles[i]))
304		− break;
	302	+ /* only valid for physical mode */
	303	+ if (adev->asic_type < CHIP_POLARIS10) {
	304	+ for (i = 0; i < adev->uvd.max_handles; ++i)
	305	+ if (atomic_read(&adev->uvd.handles[i]))
	306	+ break;
305	307
306		− if (i == AMDGPU_MAX_UVD_HANDLES)
307		− return 0;
	308	+ if (i == adev->uvd.max_handles)
	309	+ return 0;
	310	+ }
308	311
309	312	size = amdgpu_bo_size(adev->uvd.vcpu_bo);
310	313	ptr = adev->uvd.cpu_addr;

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c+1−1

@@ -3093,7 +3093,7 @@ static int dce_v6_0_hpd_irq(struct amdgpu_device *adev, · 3092 unmodified lines
3093	3093	tmp \|= DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK;
3094	3094	WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp);
3095	3095	schedule_work(&adev->hotplug_work);
3096		− DRM_INFO("IH: HPD%d\n", hpd + 1);
	3096	+ DRM_DEBUG("IH: HPD%d\n", hpd + 1);
3097	3097	}
3098	3098
3099	3099	return 0;

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c+2−28

@@ -4384,34 +4384,8 @@ static void gfx_v7_0_gpu_early_init(struct amdgpu_device *adev) · 4383 unmodified lines
4384	4384	case CHIP_KAVERI:
4385	4385	adev->gfx.config.max_shader_engines = 1;
4386	4386	adev->gfx.config.max_tile_pipes = 4;
4387		− if ((adev->pdev->device == 0x1304) \|\|
4388		− (adev->pdev->device == 0x1305) \|\|
4389		− (adev->pdev->device == 0x130C) \|\|
4390		− (adev->pdev->device == 0x130F) \|\|
4391		− (adev->pdev->device == 0x1310) \|\|
4392		− (adev->pdev->device == 0x1311) \|\|
4393		− (adev->pdev->device == 0x131C)) {
4394		− adev->gfx.config.max_cu_per_sh = 8;
4395		− adev->gfx.config.max_backends_per_se = 2;
4396		− } else if ((adev->pdev->device == 0x1309) \|\|
4397		− (adev->pdev->device == 0x130A) \|\|
4398		− (adev->pdev->device == 0x130D) \|\|
4399		− (adev->pdev->device == 0x1313) \|\|
4400		− (adev->pdev->device == 0x131D)) {
4401		− adev->gfx.config.max_cu_per_sh = 6;
4402		− adev->gfx.config.max_backends_per_se = 2;
4403		− } else if ((adev->pdev->device == 0x1306) \|\|
4404		− (adev->pdev->device == 0x1307) \|\|
4405		− (adev->pdev->device == 0x130B) \|\|
4406		− (adev->pdev->device == 0x130E) \|\|
4407		− (adev->pdev->device == 0x1315) \|\|
4408		− (adev->pdev->device == 0x131B)) {
4409		− adev->gfx.config.max_cu_per_sh = 4;
4410		− adev->gfx.config.max_backends_per_se = 1;
4411		− } else {
4412		− adev->gfx.config.max_cu_per_sh = 3;
4413		− adev->gfx.config.max_backends_per_se = 1;
4414		− }
	4387	+ adev->gfx.config.max_cu_per_sh = 8;
	4388	+ adev->gfx.config.max_backends_per_se = 2;
4415	4389	adev->gfx.config.max_sh_per_se = 1;
4416	4390	adev->gfx.config.max_texture_channel_caches = 4;
4417	4391	adev->gfx.config.max_gprs = 256;

drivers/gpu/drm/amd/amdgpu/si.c+10−12

@@ -31,6 +31,7 @@ · 30 unmodified lines
31	31	#include "amdgpu_uvd.h"
32	32	#include "amdgpu_vce.h"
33	33	#include "atom.h"
	34	+#include "amd_pcie.h"
34	35	#include "amdgpu_powerplay.h"
35	36	#include "sid.h"
36	37	#include "si_ih.h"
@@ -1461,8 +1462,8 @@ static void si_pcie_gen3_enable(struct amdgpu_device *adev) · 1424 unmodified lines
1461	1462	{
1462	1463	struct pci_dev *root = adev->pdev->bus->self;
1463	1464	int bridge_pos, gpu_pos;
1464		− u32 speed_cntl, mask, current_data_rate;
1465		− int ret, i;
	1465	+ u32 speed_cntl, current_data_rate;
	1466	+ int i;
1466	1467	u16 tmp16;
1467	1468
1468	1469	if (pci_is_root_bus(adev->pdev->bus))
@@ -1474,23 +1475,20 @@ static void si_pcie_gen3_enable(struct amdgpu_device *adev) · 5 unmodified lines
1474	1475	if (adev->flags & AMD_IS_APU)
1475	1476	return;
1476	1477
1477		− ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask);
1478		− if (ret != 0)
1479		− return;
1480		−
1481		− if (!(mask & (DRM_PCIE_SPEED_50 \| DRM_PCIE_SPEED_80)))
	1478	+ if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 \|
	1479	+ CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
1482	1480	return;
1483	1481
1484	1482	speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
1485	1483	current_data_rate = (speed_cntl & LC_CURRENT_DATA_RATE_MASK) >>
1486	1484	LC_CURRENT_DATA_RATE_SHIFT;
1487		− if (mask & DRM_PCIE_SPEED_80) {
	1485	+ if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) {
1488	1486	if (current_data_rate == 2) {
1489	1487	DRM_INFO("PCIE gen 3 link speeds already enabled\n");
1490	1488	return;
1491	1489	}
1492	1490	DRM_INFO("enabling PCIE gen 3 link speeds, disable with amdgpu.pcie_gen2=0\n");
1493		− } else if (mask & DRM_PCIE_SPEED_50) {
	1491	+ } else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) {
1494	1492	if (current_data_rate == 1) {
1495	1493	DRM_INFO("PCIE gen 2 link speeds already enabled\n");
1496	1494	return;
@@ -1506,7 +1504,7 @@ static void si_pcie_gen3_enable(struct amdgpu_device *adev) · 9 unmodified lines
1506	1504	if (!gpu_pos)
1507	1505	return;
1508	1506
1509		− if (mask & DRM_PCIE_SPEED_80) {
	1507	+ if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) {
1510	1508	if (current_data_rate != 2) {
1511	1509	u16 bridge_cfg, gpu_cfg;
1512	1510	u16 bridge_cfg2, gpu_cfg2;
@@ -1589,9 +1587,9 @@ static void si_pcie_gen3_enable(struct amdgpu_device *adev) · 76 unmodified lines
1589	1587
1590	1588	pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
1591	1589	tmp16 &= ~0xf;
1592		− if (mask & DRM_PCIE_SPEED_80)
	1590	+ if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
1593	1591	tmp16 \|= 3;
1594		− else if (mask & DRM_PCIE_SPEED_50)
	1592	+ else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
1595	1593	tmp16 \|= 2;
1596	1594	else
1597	1595	tmp16 \|= 1;

drivers/gpu/drm/amd/amdgpu/si_dpm.c+13−37

@@ -26,6 +26,7 @@ · 25 unmodified lines
26	26	#include "amdgpu_pm.h"
27	27	#include "amdgpu_dpm.h"
28	28	#include "amdgpu_atombios.h"
	29	+#include "amd_pcie.h"
29	30	#include "sid.h"
30	31	#include "r600_dpm.h"
31	32	#include "si_dpm.h"
@@ -3331,29 +3332,6 @@ static void btc_apply_voltage_delta_rules(struct amdgpu_device *adev, · 3299 unmodified lines
3331	3332	}
3332	3333	}
3333	3334
3334		−static enum amdgpu_pcie_gen r600_get_pcie_gen_support(struct amdgpu_device *adev,
3335		− u32 sys_mask,
3336		− enum amdgpu_pcie_gen asic_gen,
3337		− enum amdgpu_pcie_gen default_gen)
3338		−{
3339		− switch (asic_gen) {
3340		− case AMDGPU_PCIE_GEN1:
3341		− return AMDGPU_PCIE_GEN1;
3342		− case AMDGPU_PCIE_GEN2:
3343		− return AMDGPU_PCIE_GEN2;
3344		− case AMDGPU_PCIE_GEN3:
3345		− return AMDGPU_PCIE_GEN3;
3346		− default:
3347		− if ((sys_mask & DRM_PCIE_SPEED_80) && (default_gen == AMDGPU_PCIE_GEN3))
3348		− return AMDGPU_PCIE_GEN3;
3349		− else if ((sys_mask & DRM_PCIE_SPEED_50) && (default_gen == AMDGPU_PCIE_GEN2))
3350		− return AMDGPU_PCIE_GEN2;
3351		− else
3352		− return AMDGPU_PCIE_GEN1;
3353		− }
3354		− return AMDGPU_PCIE_GEN1;
3355		−}
3356		−
3357	3335	static void r600_calculate_u_and_p(u32 i, u32 r_c, u32 p_b,
3358	3336	u32 p, u32 u)
3359	3337	{
@@ -5028,10 +5006,11 @@ static int si_populate_smc_acpi_state(struct amdgpu_device *adev, · 1668 unmodified lines
5028	5006	table->ACPIState.levels[0].vddc.index,
5029	5007	&table->ACPIState.levels[0].std_vddc);
5030	5008	}
5031		− table->ACPIState.levels[0].gen2PCIE = (u8)r600_get_pcie_gen_support(adev,
5032		− si_pi->sys_pcie_mask,
5033		− si_pi->boot_pcie_gen,
5034		− AMDGPU_PCIE_GEN1);
	5009	+ table->ACPIState.levels[0].gen2PCIE =
	5010	+ (u8)amdgpu_get_pcie_gen_support(adev,
	5011	+ si_pi->sys_pcie_mask,
	5012	+ si_pi->boot_pcie_gen,
	5013	+ AMDGPU_PCIE_GEN1);
5035	5014
5036	5015	if (si_pi->vddc_phase_shed_control)
5037	5016	si_populate_phase_shedding_value(adev,
@@ -7168,10 +7147,10 @@ static void si_parse_pplib_clock_info(struct amdgpu_device *adev, · 2130 unmodified lines
7168	7147	pl->vddc = le16_to_cpu(clock_info->si.usVDDC);
7169	7148	pl->vddci = le16_to_cpu(clock_info->si.usVDDCI);
7170	7149	pl->flags = le32_to_cpu(clock_info->si.ulFlags);
7171		− pl->pcie_gen = r600_get_pcie_gen_support(adev,
7172		− si_pi->sys_pcie_mask,
7173		− si_pi->boot_pcie_gen,
7174		− clock_info->si.ucPCIEGen);
	7150	+ pl->pcie_gen = amdgpu_get_pcie_gen_support(adev,
	7151	+ si_pi->sys_pcie_mask,
	7152	+ si_pi->boot_pcie_gen,
	7153	+ clock_info->si.ucPCIEGen);
7175	7154
7176	7155	/* patch up vddc if necessary */
7177	7156	ret = si_get_leakage_voltage_from_leakage_index(adev, pl->vddc,
@@ -7326,7 +7305,6 @@ static int si_dpm_init(struct amdgpu_device *adev) · 148 unmodified lines
7326	7305	struct si_power_info *si_pi;
7327	7306	struct atom_clock_dividers dividers;
7328	7307	int ret;
7329		− u32 mask;
7330	7308
7331	7309	si_pi = kzalloc(sizeof(struct si_power_info), GFP_KERNEL);
7332	7310	if (si_pi == NULL)
@@ -7336,11 +7314,9 @@ static int si_dpm_init(struct amdgpu_device *adev) · 3 unmodified lines
7336	7314	eg_pi = &ni_pi->eg;
7337	7315	pi = &eg_pi->rv7xx;
7338	7316
7339		− ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask);
7340		− if (ret)
7341		− si_pi->sys_pcie_mask = 0;
7342		− else
7343		− si_pi->sys_pcie_mask = mask;
	7317	+ si_pi->sys_pcie_mask =
	7318	+ (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_MASK) >>
	7319	+ CAIL_PCIE_LINK_SPEED_SUPPORT_SHIFT;
7344	7320	si_pi->force_pcie_gen = AMDGPU_PCIE_GEN_INVALID;
7345	7321	si_pi->boot_pcie_gen = si_get_current_pcie_speed(adev);
7346	7322

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c+117−48

@@ -1037,6 +1037,10 @@ static void handle_hpd_rx_irq(void *param) · 1036 unmodified lines
1037	1037	!is_mst_root_connector) {
1038	1038	/* Downstream Port status changed. */
1039	1039	if (dc_link_detect(dc_link, DETECT_REASON_HPDRX)) {
	1040	+
	1041	+ if (aconnector->fake_enable)
	1042	+ aconnector->fake_enable = false;
	1043	+
1040	1044	amdgpu_dm_update_connector_after_detect(aconnector);
1041	1045
1042	1046
@@ -2012,30 +2016,32 @@ static void update_stream_scaling_settings(const struct drm_display_mode *mode, · 969 unmodified lines
2012	2016	dst.width = stream->timing.h_addressable;
2013	2017	dst.height = stream->timing.v_addressable;
2014	2018
2015		− rmx_type = dm_state->scaling;
2016		− if (rmx_type == RMX_ASPECT \|\| rmx_type == RMX_OFF) {
2017		− if (src.width * dst.height <
2018		− src.height * dst.width) {
2019		− /* height needs less upscaling/more downscaling */
2020		− dst.width = src.width *
2021		− dst.height / src.height;
2022		− } else {
2023		− /* width needs less upscaling/more downscaling */
2024		− dst.height = src.height *
2025		− dst.width / src.width;
	2019	+ if (dm_state) {
	2020	+ rmx_type = dm_state->scaling;
	2021	+ if (rmx_type == RMX_ASPECT \|\| rmx_type == RMX_OFF) {
	2022	+ if (src.width * dst.height <
	2023	+ src.height * dst.width) {
	2024	+ /* height needs less upscaling/more downscaling */
	2025	+ dst.width = src.width *
	2026	+ dst.height / src.height;
	2027	+ } else {
	2028	+ /* width needs less upscaling/more downscaling */
	2029	+ dst.height = src.height *
	2030	+ dst.width / src.width;
	2031	+ }
	2032	+ } else if (rmx_type == RMX_CENTER) {
	2033	+ dst = src;
2026	2034	}
2027		− } else if (rmx_type == RMX_CENTER) {
2028		− dst = src;
2029		− }
2030	2035
2031		− dst.x = (stream->timing.h_addressable - dst.width) / 2;
2032		− dst.y = (stream->timing.v_addressable - dst.height) / 2;
	2036	+ dst.x = (stream->timing.h_addressable - dst.width) / 2;
	2037	+ dst.y = (stream->timing.v_addressable - dst.height) / 2;
2033	2038
2034		− if (dm_state->underscan_enable) {
2035		− dst.x += dm_state->underscan_hborder / 2;
2036		− dst.y += dm_state->underscan_vborder / 2;
2037		− dst.width -= dm_state->underscan_hborder;
2038		− dst.height -= dm_state->underscan_vborder;
	2039	+ if (dm_state->underscan_enable) {
	2040	+ dst.x += dm_state->underscan_hborder / 2;
	2041	+ dst.y += dm_state->underscan_vborder / 2;
	2042	+ dst.width -= dm_state->underscan_hborder;
	2043	+ dst.height -= dm_state->underscan_vborder;
	2044	+ }
2039	2045	}
2040	2046
2041	2047	stream->src = src;
@@ -2360,12 +2366,7 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector, · 318 unmodified lines
2360	2366
2361	2367	if (aconnector == NULL) {
2362	2368	DRM_ERROR("aconnector is NULL!\n");
2363		− goto drm_connector_null;
2364		− }
2365		−
2366		− if (dm_state == NULL) {
2367		− DRM_ERROR("dm_state is NULL!\n");
2368		− goto dm_state_null;
	2369	+ return stream;
2369	2370	}
2370	2371
2371	2372	drm_connector = &aconnector->base;
@@ -2377,18 +2378,18 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector, · 5 unmodified lines
2377	2378	*/
2378	2379	if (aconnector->mst_port) {
2379	2380	dm_dp_mst_dc_sink_create(drm_connector);
2380		− goto mst_dc_sink_create_done;
	2381	+ return stream;
2381	2382	}
2382	2383
2383	2384	if (create_fake_sink(aconnector))
2384		− goto stream_create_fail;
	2385	+ return stream;
2385	2386	}
2386	2387
2387	2388	stream = dc_create_stream_for_sink(aconnector->dc_sink);
2388	2389
2389	2390	if (stream == NULL) {
2390	2391	DRM_ERROR("Failed to create stream for sink!\n");
2391		− goto stream_create_fail;
	2392	+ return stream;
2392	2393	}
2393	2394
2394	2395	list_for_each_entry(preferred_mode, &aconnector->base.modes, head) {
@@ -2414,9 +2415,12 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector, · 19 unmodified lines
2414	2415	} else {
2415	2416	decide_crtc_timing_for_drm_display_mode(
2416	2417	&mode, preferred_mode,
2417		− dm_state->scaling != RMX_OFF);
	2418	+ dm_state ? (dm_state->scaling != RMX_OFF) : false);
2418	2419	}
2419	2420
	2421	+ if (!dm_state)
	2422	+ drm_mode_set_crtcinfo(&mode, 0);
	2423	+
2420	2424	fill_stream_properties_from_drm_display_mode(stream,
2421	2425	&mode, &aconnector->base);
2422	2426	update_stream_scaling_settings(&mode, dm_state, stream);
@@ -2426,10 +2430,8 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector, · 3 unmodified lines
2426	2430	drm_connector,
2427	2431	aconnector->dc_sink);
2428	2432
2429		−stream_create_fail:
2430		−dm_state_null:
2431		−drm_connector_null:
2432		−mst_dc_sink_create_done:
	2433	+ update_stream_signal(stream);
	2434	+
2433	2435	return stream;
2434	2436	}
2435	2437
@@ -2497,6 +2499,27 @@ dm_crtc_duplicate_state(struct drm_crtc *crtc) · 61 unmodified lines
2497	2499	return &state->base;
2498	2500	}
2499	2501
	2502	+
	2503	+static inline int dm_set_vblank(struct drm_crtc *crtc, bool enable)
	2504	+{
	2505	+ enum dc_irq_source irq_source;
	2506	+ struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
	2507	+ struct amdgpu_device *adev = crtc->dev->dev_private;
	2508	+
	2509	+ irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst;
	2510	+ return dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;
	2511	+}
	2512	+
	2513	+static int dm_enable_vblank(struct drm_crtc *crtc)
	2514	+{
	2515	+ return dm_set_vblank(crtc, true);
	2516	+}
	2517	+
	2518	+static void dm_disable_vblank(struct drm_crtc *crtc)
	2519	+{
	2520	+ dm_set_vblank(crtc, false);
	2521	+}
	2522	+
2500	2523	/* Implemented only the options currently availible for the driver */
2501	2524	static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = {
2502	2525	.reset = dm_crtc_reset_state,
@@ -2506,6 +2529,8 @@ static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = { · 3 unmodified lines
2506	2529	.page_flip = drm_atomic_helper_page_flip,
2507	2530	.atomic_duplicate_state = dm_crtc_duplicate_state,
2508	2531	.atomic_destroy_state = dm_crtc_destroy_state,
	2532	+ .enable_vblank = dm_enable_vblank,
	2533	+ .disable_vblank = dm_disable_vblank,
2509	2534	};
2510	2535
2511	2536	static enum drm_connector_status
@@ -2800,7 +2825,7 @@ int amdgpu_dm_connector_mode_valid(struct drm_connector *connector, · 288 unmodified lines
2800	2825	goto fail;
2801	2826	}
2802	2827
2803		− stream = dc_create_stream_for_sink(dc_sink);
	2828	+ stream = create_stream_for_sink(aconnector, mode, NULL);
2804	2829	if (stream == NULL) {
2805	2830	DRM_ERROR("Failed to create stream for sink!\n");
2806	2831	goto fail;
@@ -3060,6 +3085,9 @@ static int dm_plane_atomic_check(struct drm_plane *plane, · 253 unmodified lines
3060	3085	if (!dm_plane_state->dc_state)
3061	3086	return 0;
3062	3087
	3088	+ if (!fill_rects_from_plane_state(state, dm_plane_state->dc_state))
	3089	+ return -EINVAL;
	3090	+
3063	3091	if (dc_validate_plane(dc, dm_plane_state->dc_state) == DC_OK)
3064	3092	return 0;
3065	3093
@@ -4632,8 +4660,6 @@ static int dm_update_planes_state(struct dc *dc, · 1566 unmodified lines
4632	4660	bool pflip_needed = !state->allow_modeset;
4633	4661	int ret = 0;
4634	4662
4635		− if (pflip_needed)
4636		− return ret;
4637	4663
4638	4664	/* Add new planes */
4639	4665	for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
@@ -4648,6 +4674,8 @@ static int dm_update_planes_state(struct dc *dc, · 8 unmodified lines
4648	4674
4649	4675	/* Remove any changed/removed planes */
4650	4676	if (!enable) {
	4677	+ if (pflip_needed)
	4678	+ continue;
4651	4679
4652	4680	if (!old_plane_crtc)
4653	4681	continue;
@@ -4679,6 +4707,7 @@ static int dm_update_planes_state(struct dc *dc, · 25 unmodified lines
4679	4707	*lock_and_validation_needed = true;
4680	4708
4681	4709	} else { /* Add new planes */
	4710	+ struct dc_plane_state *dc_new_plane_state;
4682	4711
4683	4712	if (drm_atomic_plane_disabling(plane->state, new_plane_state))
4684	4713	continue;
@@ -4692,38 +4721,50 @@ static int dm_update_planes_state(struct dc *dc, · 7 unmodified lines
4692	4721	if (!dm_new_crtc_state->stream)
4693	4722	continue;
4694	4723
	4724	+ if (pflip_needed)
	4725	+ continue;
4695	4726
4696	4727	WARN_ON(dm_new_plane_state->dc_state);
4697	4728
4698		− dm_new_plane_state->dc_state = dc_create_plane_state(dc);
4699		−
4700		− DRM_DEBUG_DRIVER("Enabling DRM plane: %d on DRM crtc %d\n",
4701		− plane->base.id, new_plane_crtc->base.id);
4702		−
4703		− if (!dm_new_plane_state->dc_state) {
	4729	+ dc_new_plane_state = dc_create_plane_state(dc);
	4730	+ if (!dc_new_plane_state) {
4704	4731	ret = -EINVAL;
4705	4732	return ret;
4706	4733	}
4707	4734
	4735	+ DRM_DEBUG_DRIVER("Enabling DRM plane: %d on DRM crtc %d\n",
	4736	+ plane->base.id, new_plane_crtc->base.id);
	4737	+
4708	4738	ret = fill_plane_attributes(
4709	4739	new_plane_crtc->dev->dev_private,
4710		− dm_new_plane_state->dc_state,
	4740	+ dc_new_plane_state,
4711	4741	new_plane_state,
4712	4742	new_crtc_state);
4713		− if (ret)
	4743	+ if (ret) {
	4744	+ dc_plane_state_release(dc_new_plane_state);
4714	4745	return ret;
	4746	+ }
4715	4747
4716		−
	4748	+ /*
	4749	+ * Any atomic check errors that occur after this will
	4750	+ * not need a release. The plane state will be attached
	4751	+ * to the stream, and therefore part of the atomic
	4752	+ * state. It'll be released when the atomic state is
	4753	+ * cleaned.
	4754	+ */
4717	4755	if (!dc_add_plane_to_context(
4718	4756	dc,
4719	4757	dm_new_crtc_state->stream,
4720		− dm_new_plane_state->dc_state,
	4758	+ dc_new_plane_state,
4721	4759	dm_state->context)) {
4722	4760
	4761	+ dc_plane_state_release(dc_new_plane_state);
4723	4762	ret = -EINVAL;
4724	4763	return ret;
4725	4764	}
4726	4765
	4766	+ dm_new_plane_state->dc_state = dc_new_plane_state;
	4767	+
4727	4768	/* Tell DC to do a full surface update every time there
4728	4769	* is a plane change. Inefficient, but works for now.
4729	4770	*/
@@ -4737,6 +4778,30 @@ static int dm_update_planes_state(struct dc *dc, · 7 unmodified lines
4737	4778	return ret;
4738	4779	}
4739	4780
	4781	+static int dm_atomic_check_plane_state_fb(struct drm_atomic_state *state,
	4782	+ struct drm_crtc *crtc)
	4783	+{
	4784	+ struct drm_plane *plane;
	4785	+ struct drm_crtc_state *crtc_state;
	4786	+
	4787	+ WARN_ON(!drm_atomic_get_new_crtc_state(state, crtc));
	4788	+
	4789	+ drm_for_each_plane_mask(plane, state->dev, crtc->state->plane_mask) {
	4790	+ struct drm_plane_state *plane_state =
	4791	+ drm_atomic_get_plane_state(state, plane);
	4792	+
	4793	+ if (IS_ERR(plane_state))
	4794	+ return -EDEADLK;
	4795	+
	4796	+ crtc_state = drm_atomic_get_crtc_state(plane_state->state, crtc);
	4797	+ if (crtc->primary == plane && crtc_state->active) {
	4798	+ if (!plane_state->fb)
	4799	+ return -EINVAL;
	4800	+ }
	4801	+ }
	4802	+ return 0;
	4803	+}
	4804	+
4740	4805	static int amdgpu_dm_atomic_check(struct drm_device *dev,
4741	4806	struct drm_atomic_state *state)
4742	4807	{
@@ -4760,6 +4825,10 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, · 17 unmodified lines
4760	4825	goto fail;
4761	4826
4762	4827	for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
	4828	+ ret = dm_atomic_check_plane_state_fb(state, crtc);
	4829	+ if (ret)
	4830	+ goto fail;
	4831	+
4763	4832	if (!drm_atomic_crtc_needs_modeset(new_crtc_state) &&
4764	4833	!new_crtc_state->color_mgmt_changed)
4765	4834	continue;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c+2−4

@@ -683,10 +683,8 @@ static const struct amdgpu_irq_src_funcs dm_hpd_irq_funcs = { · 682 unmodified lines
683	683
684	684	void amdgpu_dm_set_irq_funcs(struct amdgpu_device *adev)
685	685	{
686		− if (adev->mode_info.num_crtc > 0)
687		− adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_VLINE1 + adev->mode_info.num_crtc;
688		− else
689		− adev->crtc_irq.num_types = 0;
	686	+
	687	+ adev->crtc_irq.num_types = adev->mode_info.num_crtc;
690	688	adev->crtc_irq.funcs = &dm_crtc_irq_funcs;
691	689
692	690	adev->pageflip_irq.num_types = adev->mode_info.num_crtc;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c+6−0

@@ -189,6 +189,12 @@ void dm_dp_mst_dc_sink_create(struct drm_connector *connector) · 188 unmodified lines
189	189	.link = aconnector->dc_link,
190	190	.sink_signal = SIGNAL_TYPE_DISPLAY_PORT_MST };
191	191
	192	+ /*
	193	+ * TODO: Need to further figure out why ddc.algo is NULL while MST port exists
	194	+ */
	195	+ if (!aconnector->port \|\| !aconnector->port->aux.ddc.algo)
	196	+ return;
	197	+
192	198	edid = drm_dp_mst_get_edid(connector, &aconnector->mst_port->mst_mgr, aconnector->port);
193	199
194	200	if (!edid) {

drivers/gpu/drm/amd/display/dc/core/dc.c+3−3

@@ -1358,13 +1358,13 @@ enum dc_irq_source dc_interrupt_to_irq_source( · 1357 unmodified lines
1358	1358	return dal_irq_service_to_irq_source(dc->res_pool->irqs, src_id, ext_id);
1359	1359	}
1360	1360
1361		−void dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable)
	1361	+bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable)
1362	1362	{
1363	1363
1364	1364	if (dc == NULL)
1365		− return;
	1365	+ return false;
1366	1366
1367		− dal_irq_service_set(dc->res_pool->irqs, src, enable);
	1367	+ return dal_irq_service_set(dc->res_pool->irqs, src, enable);
1368	1368	}
1369	1369
1370	1370	void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src)

drivers/gpu/drm/amd/display/dc/core/dc_link.c+1−2

@@ -1749,8 +1749,7 @@ static void enable_link_hdmi(struct pipe_ctx *pipe_ctx) · 1748 unmodified lines
1749	1749	link->link_enc,
1750	1750	pipe_ctx->clock_source->id,
1751	1751	display_color_depth,
1752		− pipe_ctx->stream->signal == SIGNAL_TYPE_HDMI_TYPE_A,
1753		− pipe_ctx->stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK,
	1752	+ pipe_ctx->stream->signal,
1754	1753	stream->phy_pix_clk);
1755	1754
1756	1755	if (pipe_ctx->stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c+0−3

@@ -1360,9 +1360,6 @@ bool dc_is_stream_scaling_unchanged( · 1359 unmodified lines
1360	1360	return true;
1361	1361	}
1362	1362
1363		−/* Maximum TMDS single link pixel clock 165MHz */
1364		−#define TMDS_MAX_PIXEL_CLOCK_IN_KHZ 165000
1365		−
1366	1363	static void update_stream_engine_usage(
1367	1364	struct resource_context *res_ctx,
1368	1365	const struct resource_pool *pool,

drivers/gpu/drm/amd/display/dc/core/dc_stream.c+8−68

@@ -33,8 +33,7 @@ · 32 unmodified lines
33	33	/*******************************************************************************
34	34	* Private functions
35	35	******************************************************************************/
36		−#define TMDS_MAX_PIXEL_CLOCK_IN_KHZ_UPMOST 297000
37		−static void update_stream_signal(struct dc_stream_state *stream)
	36	+void update_stream_signal(struct dc_stream_state *stream)
38	37	{
39	38
40	39	struct dc_sink *dc_sink = stream->sink;
@@ -45,8 +44,9 @@ static void update_stream_signal(struct dc_stream_state *stream) · 4 unmodified lines
45	44	stream->signal = dc_sink->sink_signal;
46	45
47	46	if (dc_is_dvi_signal(stream->signal)) {
48		− if (stream->timing.pix_clk_khz > TMDS_MAX_PIXEL_CLOCK_IN_KHZ_UPMOST &&
49		− stream->sink->sink_signal != SIGNAL_TYPE_DVI_SINGLE_LINK)
	47	+ if (stream->ctx->dc->caps.dual_link_dvi &&
	48	+ stream->timing.pix_clk_khz > TMDS_MAX_PIXEL_CLOCK &&
	49	+ stream->sink->sink_signal != SIGNAL_TYPE_DVI_SINGLE_LINK)
50	50	stream->signal = SIGNAL_TYPE_DVI_DUAL_LINK;
51	51	else
52	52	stream->signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
@@ -193,6 +193,7 @@ bool dc_stream_set_cursor_attributes( · 140 unmodified lines
193	193
194	194	core_dc = stream->ctx->dc;
195	195	res_ctx = &core_dc->current_state->res_ctx;
	196	+ stream->cursor_attributes = *attributes;
196	197
197	198	for (i = 0; i < MAX_PIPES; i++) {
198	199	struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
@@ -204,34 +205,8 @@ bool dc_stream_set_cursor_attributes( · 5 unmodified lines
204	205	continue;
205	206
206	207
207		− if (pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes != NULL)
208		− pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes(
209		− pipe_ctx->plane_res.ipp, attributes);
210		−
211		− if (pipe_ctx->plane_res.hubp != NULL &&
212		− pipe_ctx->plane_res.hubp->funcs->set_cursor_attributes != NULL)
213		− pipe_ctx->plane_res.hubp->funcs->set_cursor_attributes(
214		− pipe_ctx->plane_res.hubp, attributes);
215		−
216		− if (pipe_ctx->plane_res.mi != NULL &&
217		− pipe_ctx->plane_res.mi->funcs->set_cursor_attributes != NULL)
218		− pipe_ctx->plane_res.mi->funcs->set_cursor_attributes(
219		− pipe_ctx->plane_res.mi, attributes);
220		−
221		−
222		− if (pipe_ctx->plane_res.xfm != NULL &&
223		− pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes != NULL)
224		− pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes(
225		− pipe_ctx->plane_res.xfm, attributes);
226		−
227		− if (pipe_ctx->plane_res.dpp != NULL &&
228		− pipe_ctx->plane_res.dpp->funcs->set_cursor_attributes != NULL)
229		− pipe_ctx->plane_res.dpp->funcs->set_cursor_attributes(
230		− pipe_ctx->plane_res.dpp, attributes->color_format);
	208	+ core_dc->hwss.set_cursor_attribute(pipe_ctx);
231	209	}
232		−
233		− stream->cursor_attributes = *attributes;
234		−
235	210	return true;
236	211	}
237	212
@@ -255,21 +230,10 @@ bool dc_stream_set_cursor_position( · 17 unmodified lines
255	230
256	231	core_dc = stream->ctx->dc;
257	232	res_ctx = &core_dc->current_state->res_ctx;
	233	+ stream->cursor_position = *position;
258	234
259	235	for (i = 0; i < MAX_PIPES; i++) {
260	236	struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
261		− struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp;
262		− struct mem_input *mi = pipe_ctx->plane_res.mi;
263		− struct hubp *hubp = pipe_ctx->plane_res.hubp;
264		− struct dpp *dpp = pipe_ctx->plane_res.dpp;
265		− struct dc_cursor_position pos_cpy = *position;
266		− struct dc_cursor_mi_param param = {
267		− .pixel_clk_khz = stream->timing.pix_clk_khz,
268		− .ref_clk_khz = core_dc->res_pool->ref_clock_inKhz,
269		− .viewport_x_start = pipe_ctx->plane_res.scl_data.viewport.x,
270		− .viewport_width = pipe_ctx->plane_res.scl_data.viewport.width,
271		− .h_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.horz
272		− };
273	237
274	238	if (pipe_ctx->stream != stream \|\|
275	239	(!pipe_ctx->plane_res.mi && !pipe_ctx->plane_res.hubp) \|\|
@@ -278,33 +242,9 @@ bool dc_stream_set_cursor_position( · 2 unmodified lines
278	242	!pipe_ctx->plane_res.ipp)
279	243	continue;
280	244
281		− if (pipe_ctx->plane_state->address.type
282		− == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE)
283		− pos_cpy.enable = false;
284		−
285		− if (pipe_ctx->top_pipe && pipe_ctx->plane_state != pipe_ctx->top_pipe->plane_state)
286		− pos_cpy.enable = false;
287		−
288		−
289		− if (ipp != NULL && ipp->funcs->ipp_cursor_set_position != NULL)
290		− ipp->funcs->ipp_cursor_set_position(ipp, &pos_cpy, &param);
291		−
292		− if (mi != NULL && mi->funcs->set_cursor_position != NULL)
293		− mi->funcs->set_cursor_position(mi, &pos_cpy, &param);
294		−
295		− if (!hubp)
296		− continue;
297		−
298		− if (hubp->funcs->set_cursor_position != NULL)
299		− hubp->funcs->set_cursor_position(hubp, &pos_cpy, &param);
300		−
301		− if (dpp != NULL && dpp->funcs->set_cursor_position != NULL)
302		− dpp->funcs->set_cursor_position(dpp, &pos_cpy, &param, hubp->curs_attr.width);
303		−
	245	+ core_dc->hwss.set_cursor_position(pipe_ctx);
304	246	}
305	247
306		− stream->cursor_position = *position;
307		−
308	248	return true;
309	249	}
310	250

drivers/gpu/drm/amd/display/dc/dc.h+2−1

@@ -62,6 +62,7 @@ struct dc_caps { · 61 unmodified lines
62	62	bool dcc_const_color;
63	63	bool dynamic_audio;
64	64	bool is_apu;
	65	+ bool dual_link_dvi;
65	66	};
66	67
67	68	struct dc_dcc_surface_param {
@@ -672,7 +673,7 @@ enum dc_irq_source dc_interrupt_to_irq_source( · 604 unmodified lines
672	673	struct dc *dc,
673	674	uint32_t src_id,
674	675	uint32_t ext_id);
675		−void dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable);
	676	+bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable);
676	677	void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src);
677	678	enum dc_irq_source dc_get_hpd_irq_source_at_index(
678	679	struct dc *dc, uint32_t link_index);

drivers/gpu/drm/amd/display/dc/dc_stream.h+2−0

@@ -237,6 +237,8 @@ enum surface_update_type dc_check_update_surfaces_for_stream( · 236 unmodified lines
237	237	*/
238	238	struct dc_stream_state dc_create_stream_for_sink(struct dc_sink dc_sink);
239	239
	240	+void update_stream_signal(struct dc_stream_state *stream);
	241	+
240	242	void dc_stream_retain(struct dc_stream_state *dc_stream);
241	243	void dc_stream_release(struct dc_stream_state *dc_stream);
242	244

drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h+9−1

@@ -236,6 +236,7 @@ · 235 unmodified lines
236	236	SR(D2VGA_CONTROL), \
237	237	SR(D3VGA_CONTROL), \
238	238	SR(D4VGA_CONTROL), \
	239	+ SR(VGA_TEST_CONTROL), \
239	240	SR(DC_IP_REQUEST_CNTL), \
240	241	BL_REG_LIST()
241	242
@@ -337,6 +338,7 @@ struct dce_hwseq_registers { · 95 unmodified lines
337	338	uint32_t D2VGA_CONTROL;
338	339	uint32_t D3VGA_CONTROL;
339	340	uint32_t D4VGA_CONTROL;
	341	+ uint32_t VGA_TEST_CONTROL;
340	342	/* MMHUB registers. read only. temporary hack */
341	343	uint32_t VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32;
342	344	uint32_t VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32;
@@ -493,6 +495,9 @@ struct dce_hwseq_registers { · 150 unmodified lines
493	495	HWS_SF(, DOMAIN6_PG_STATUS, DOMAIN6_PGFSM_PWR_STATUS, mask_sh), \
494	496	HWS_SF(, DOMAIN7_PG_STATUS, DOMAIN7_PGFSM_PWR_STATUS, mask_sh), \
495	497	HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
	498	+ HWS_SF(, D1VGA_CONTROL, D1VGA_MODE_ENABLE, mask_sh),\
	499	+ HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_ENABLE, mask_sh),\
	500	+ HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_RENDER_START, mask_sh),\
496	501	HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \
497	502	HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh)
498	503
@@ -583,7 +588,10 @@ struct dce_hwseq_registers { · 84 unmodified lines
583	588	type DCFCLK_GATE_DIS; \
584	589	type DCHUBBUB_GLOBAL_TIMER_REFDIV; \
585	590	type DENTIST_DPPCLK_WDIVIDER; \
586		− type DENTIST_DISPCLK_WDIVIDER;
	591	+ type DENTIST_DISPCLK_WDIVIDER; \
	592	+ type VGA_TEST_ENABLE; \
	593	+ type VGA_TEST_RENDER_START; \
	594	+ type D1VGA_MODE_ENABLE;
587	595
588	596	struct dce_hwseq_shift {
589	597	HWSEQ_REG_FIELD_LIST(uint8_t)

drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c+18−20

@@ -82,13 +82,6 @@ · 81 unmodified lines
82	82	#define DCE110_DIG_FE_SOURCE_SELECT_DIGF 0x20
83	83	#define DCE110_DIG_FE_SOURCE_SELECT_DIGG 0x40
84	84
85		−/* Minimum pixel clock, in KHz. For TMDS signal is 25.00 MHz */
86		−#define TMDS_MIN_PIXEL_CLOCK 25000
87		−/* Maximum pixel clock, in KHz. For TMDS signal is 165.00 MHz */
88		−#define TMDS_MAX_PIXEL_CLOCK 165000
89		−/* For current ASICs pixel clock - 600MHz */
90		−#define MAX_ENCODER_CLOCK 600000
91		−
92	85	enum {
93	86	DP_MST_UPDATE_MAX_RETRY = 50
94	87	};
@@ -683,6 +676,7 @@ void dce110_link_encoder_construct( · 588 unmodified lines
683	676	{
684	677	struct bp_encoder_cap_info bp_cap_info = {0};
685	678	const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs;
	679	+ enum bp_result result = BP_RESULT_OK;
686	680
687	681	enc110->base.funcs = &dce110_lnk_enc_funcs;
688	682	enc110->base.ctx = init_data->ctx;
@@ -757,15 +751,24 @@ void dce110_link_encoder_construct( · 68 unmodified lines
757	751	enc110->base.preferred_engine = ENGINE_ID_UNKNOWN;
758	752	}
759	753
	754	+ /* default to one to mirror Windows behavior */
	755	+ enc110->base.features.flags.bits.HDMI_6GB_EN = 1;
	756	+
	757	+ result = bp_funcs->get_encoder_cap_info(enc110->base.ctx->dc_bios,
	758	+ enc110->base.id, &bp_cap_info);
	759	+
760	760	/* Override features with DCE-specific values */
761		− if (BP_RESULT_OK == bp_funcs->get_encoder_cap_info(
762		− enc110->base.ctx->dc_bios, enc110->base.id,
763		− &bp_cap_info)) {
	761	+ if (BP_RESULT_OK == result) {
764	762	enc110->base.features.flags.bits.IS_HBR2_CAPABLE =
765	763	bp_cap_info.DP_HBR2_EN;
766	764	enc110->base.features.flags.bits.IS_HBR3_CAPABLE =
767	765	bp_cap_info.DP_HBR3_EN;
768	766	enc110->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN;
	767	+ } else {
	768	+ dm_logger_write(enc110->base.ctx->logger, LOG_WARNING,
	769	+ "%s: Failed to get encoder_cap_info from VBIOS with error code %d!\n",
	770	+ __func__,
	771	+ result);
769	772	}
770	773	}
771	774
@@ -904,8 +907,7 @@ void dce110_link_encoder_enable_tmds_output( · 132 unmodified lines
904	907	struct link_encoder *enc,
905	908	enum clock_source_id clock_source,
906	909	enum dc_color_depth color_depth,
907		− bool hdmi,
908		− bool dual_link,
	910	+ enum signal_type signal,
909	911	uint32_t pixel_clock)
910	912	{
911	913	struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
@@ -919,16 +921,12 @@ void dce110_link_encoder_enable_tmds_output( · 7 unmodified lines
919	921	cntl.engine_id = enc->preferred_engine;
920	922	cntl.transmitter = enc110->base.transmitter;
921	923	cntl.pll_id = clock_source;
922		− if (hdmi) {
923		− cntl.signal = SIGNAL_TYPE_HDMI_TYPE_A;
924		− cntl.lanes_number = 4;
925		− } else if (dual_link) {
926		− cntl.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
	924	+ cntl.signal = signal;
	925	+ if (cntl.signal == SIGNAL_TYPE_DVI_DUAL_LINK)
927	926	cntl.lanes_number = 8;
928		− } else {
929		− cntl.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
	927	+ else
930	928	cntl.lanes_number = 4;
931		− }
	929	+
932	930	cntl.hpd_sel = enc110->base.hpd_source;
933	931
934	932	cntl.pixel_clock = pixel_clock;

drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h+1−2

@@ -210,8 +210,7 @@ void dce110_link_encoder_enable_tmds_output( · 209 unmodified lines
210	210	struct link_encoder *enc,
211	211	enum clock_source_id clock_source,
212	212	enum dc_color_depth color_depth,
213		− bool hdmi,
214		− bool dual_link,
	213	+ enum signal_type signal,
215	214	uint32_t pixel_clock);
216	215
217	216	/* enables DP PHY output */

drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c+1−0

@@ -852,6 +852,7 @@ static bool construct( · 851 unmodified lines
852	852	dc->caps.max_downscale_ratio = 200;
853	853	dc->caps.i2c_speed_in_khz = 40;
854	854	dc->caps.max_cursor_size = 128;
	855	+ dc->caps.dual_link_dvi = true;
855	856
856	857	for (i = 0; i < pool->base.pipe_count; i++) {
857	858	pool->base.timing_generators[i] =

drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c+77−14

@@ -688,15 +688,22 @@ void dce110_enable_stream(struct pipe_ctx *pipe_ctx) · 687 unmodified lines
688	688	struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;
689	689	struct dc_link *link = pipe_ctx->stream->sink->link;
690	690
691		− /* 1. update AVI info frame (HDMI, DP)
692		− * we always need to update info frame
693		− */
	691	+
694	692	uint32_t active_total_with_borders;
695	693	uint32_t early_control = 0;
696	694	struct timing_generator *tg = pipe_ctx->stream_res.tg;
697	695
698		− /* TODOFPGA may change to hwss.update_info_frame */
	696	+ /* For MST, there are multiply stream go to only one link.
	697	+ * connect DIG back_end to front_end while enable_stream and
	698	+ * disconnect them during disable_stream
	699	+ * BY this, it is logic clean to separate stream and link */
	700	+ link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc,
	701	+ pipe_ctx->stream_res.stream_enc->id, true);
	702	+
	703	+ /* update AVI info frame (HDMI, DP)*/
	704	+ /* TODO: FPGA may change to hwss.update_info_frame */
699	705	dce110_update_info_frame(pipe_ctx);
	706	+
700	707	/* enable early control to avoid corruption on DP monitor*/
701	708	active_total_with_borders =
702	709	timing->h_addressable
@@ -717,12 +724,8 @@ void dce110_enable_stream(struct pipe_ctx *pipe_ctx) · 14 unmodified lines
717	724	pipe_ctx->stream_res.stream_enc->funcs->dp_audio_enable(pipe_ctx->stream_res.stream_enc);
718	725	}
719	726
720		− /* For MST, there are multiply stream go to only one link.
721		− * connect DIG back_end to front_end while enable_stream and
722		− * disconnect them during disable_stream
723		− * BY this, it is logic clean to separate stream and link */
724		− link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc,
725		− pipe_ctx->stream_res.stream_enc->id, true);
	727	+
	728	+
726	729
727	730	}
728	731
@@ -1690,9 +1693,13 @@ static void apply_min_clocks( · 961 unmodified lines
1690	1693	* Check if FBC can be enabled
1691	1694	*/
1692	1695	static bool should_enable_fbc(struct dc *dc,
1693		− struct dc_state *context)
	1696	+ struct dc_state *context,
	1697	+ uint32_t *pipe_idx)
1694	1698	{
1695		− struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[0];
	1699	+ uint32_t i;
	1700	+ struct pipe_ctx *pipe_ctx = NULL;
	1701	+ struct resource_context *res_ctx = &context->res_ctx;
	1702	+
1696	1703
1697	1704	ASSERT(dc->fbc_compressor);
1698	1705
@@ -1704,6 +1711,14 @@ static bool should_enable_fbc(struct dc *dc, · 5 unmodified lines
1704	1711	if (context->stream_count != 1)
1705	1712	return false;
1706	1713
	1714	+ for (i = 0; i < dc->res_pool->pipe_count; i++) {
	1715	+ if (res_ctx->pipe_ctx[i].stream) {
	1716	+ pipe_ctx = &res_ctx->pipe_ctx[i];
	1717	+ *pipe_idx = i;
	1718	+ break;
	1719	+ }
	1720	+ }
	1721	+
1707	1722	/* Only supports eDP */
1708	1723	if (pipe_ctx->stream->sink->link->connector_signal != SIGNAL_TYPE_EDP)
1709	1724	return false;
@@ -1729,11 +1744,14 @@ static bool should_enable_fbc(struct dc *dc, · 19 unmodified lines
1729	1744	static void enable_fbc(struct dc *dc,
1730	1745	struct dc_state *context)
1731	1746	{
1732		− if (should_enable_fbc(dc, context)) {
	1747	+ uint32_t pipe_idx = 0;
	1748	+
	1749	+ if (should_enable_fbc(dc, context, &pipe_idx)) {
1733	1750	/* Program GRPH COMPRESSED ADDRESS and PITCH */
1734	1751	struct compr_addr_and_pitch_params params = {0, 0, 0};
1735	1752	struct compressor *compr = dc->fbc_compressor;
1736		− struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[0];
	1753	+ struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx];
	1754	+
1737	1755
1738	1756	params.source_view_width = pipe_ctx->stream->timing.h_addressable;
1739	1757	params.source_view_height = pipe_ctx->stream->timing.v_addressable;
@@ -2915,6 +2933,49 @@ static void program_csc_matrix(struct pipe_ctx *pipe_ctx, · 1175 unmodified lines
2915	2933	}
2916	2934	}
2917	2935
	2936	+void dce110_set_cursor_position(struct pipe_ctx *pipe_ctx)
	2937	+{
	2938	+ struct dc_cursor_position pos_cpy = pipe_ctx->stream->cursor_position;
	2939	+ struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp;
	2940	+ struct mem_input *mi = pipe_ctx->plane_res.mi;
	2941	+ struct dc_cursor_mi_param param = {
	2942	+ .pixel_clk_khz = pipe_ctx->stream->timing.pix_clk_khz,
	2943	+ .ref_clk_khz = pipe_ctx->stream->ctx->dc->res_pool->ref_clock_inKhz,
	2944	+ .viewport_x_start = pipe_ctx->plane_res.scl_data.viewport.x,
	2945	+ .viewport_width = pipe_ctx->plane_res.scl_data.viewport.width,
	2946	+ .h_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.horz
	2947	+ };
	2948	+
	2949	+ if (pipe_ctx->plane_state->address.type
	2950	+ == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE)
	2951	+ pos_cpy.enable = false;
	2952	+
	2953	+ if (pipe_ctx->top_pipe && pipe_ctx->plane_state != pipe_ctx->top_pipe->plane_state)
	2954	+ pos_cpy.enable = false;
	2955	+
	2956	+ if (ipp->funcs->ipp_cursor_set_position)
	2957	+ ipp->funcs->ipp_cursor_set_position(ipp, &pos_cpy, &param);
	2958	+ if (mi->funcs->set_cursor_position)
	2959	+ mi->funcs->set_cursor_position(mi, &pos_cpy, &param);
	2960	+}
	2961	+
	2962	+void dce110_set_cursor_attribute(struct pipe_ctx *pipe_ctx)
	2963	+{
	2964	+ struct dc_cursor_attributes *attributes = &pipe_ctx->stream->cursor_attributes;
	2965	+
	2966	+ if (pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes)
	2967	+ pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes(
	2968	+ pipe_ctx->plane_res.ipp, attributes);
	2969	+
	2970	+ if (pipe_ctx->plane_res.mi->funcs->set_cursor_attributes)
	2971	+ pipe_ctx->plane_res.mi->funcs->set_cursor_attributes(
	2972	+ pipe_ctx->plane_res.mi, attributes);
	2973	+
	2974	+ if (pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes)
	2975	+ pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes(
	2976	+ pipe_ctx->plane_res.xfm, attributes);
	2977	+}
	2978	+
2918	2979	static void ready_shared_resources(struct dc dc, struct dc_state context) {}
2919	2980
2920	2981	static void optimize_shared_resources(struct dc *dc) {}
@@ -2957,6 +3018,8 @@ static const struct hw_sequencer_funcs dce110_funcs = { · 36 unmodified lines
2957	3018	.edp_backlight_control = hwss_edp_backlight_control,
2958	3019	.edp_power_control = hwss_edp_power_control,
2959	3020	.edp_wait_for_hpd_ready = hwss_edp_wait_for_hpd_ready,
	3021	+ .set_cursor_position = dce110_set_cursor_position,
	3022	+ .set_cursor_attribute = dce110_set_cursor_attribute
2960	3023	};
2961	3024
2962	3025	void dce110_hw_sequencer_construct(struct dc *dc)

drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c+18−0

@@ -846,6 +846,16 @@ static bool dce110_validate_bandwidth( · 845 unmodified lines
846	846	return result;
847	847	}
848	848
	849	+enum dc_status dce110_validate_plane(const struct dc_plane_state *plane_state,
	850	+ struct dc_caps *caps)
	851	+{
	852	+ if (((plane_state->dst_rect.width * 2) < plane_state->src_rect.width) \|\|
	853	+ ((plane_state->dst_rect.height * 2) < plane_state->src_rect.height))
	854	+ return DC_FAIL_SURFACE_VALIDATE;
	855	+
	856	+ return DC_OK;
	857	+}
	858	+
849	859	static bool dce110_validate_surface_sets(
850	860	struct dc_state *context)
851	861	{
@@ -869,6 +879,13 @@ static bool dce110_validate_surface_sets( · 17 unmodified lines
869	879	plane->src_rect.height > 1080))
870	880	return false;
871	881
	882	+ /* we don't have the logic to support underlay
	883	+ * only yet so block the use case where we get
	884	+ * NV12 plane as top layer
	885	+ */
	886	+ if (j == 0)
	887	+ return false;
	888	+
872	889	/* irrespective of plane format,
873	890	* stream should be RGB encoded
874	891	*/
@@ -1021,6 +1038,7 @@ static const struct resource_funcs dce110_res_pool_funcs = { · 146 unmodified lines
1021	1038	.link_enc_create = dce110_link_encoder_create,
1022	1039	.validate_guaranteed = dce110_validate_guaranteed,
1023	1040	.validate_bandwidth = dce110_validate_bandwidth,
	1041	+ .validate_plane = dce110_validate_plane,
1024	1042	.acquire_idle_pipe_for_layer = dce110_acquire_underlay,
1025	1043	.add_stream_to_ctx = dce110_add_stream_to_ctx,
1026	1044	.validate_global = dce110_validate_global

drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c+2−0

@@ -1103,6 +1103,8 @@ static bool construct( · 1102 unmodified lines
1103	1103	dc->caps.max_downscale_ratio = 200;
1104	1104	dc->caps.i2c_speed_in_khz = 100;
1105	1105	dc->caps.max_cursor_size = 128;
	1106	+ dc->caps.dual_link_dvi = true;
	1107	+
1106	1108
1107	1109	/*************************************************
1108	1110	* Create resources *

drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c+2−0

@@ -835,6 +835,8 @@ static bool construct( · 834 unmodified lines
835	835	dc->caps.max_downscale_ratio = 200;
836	836	dc->caps.i2c_speed_in_khz = 100;
837	837	dc->caps.max_cursor_size = 128;
	838	+ dc->caps.dual_link_dvi = true;
	839	+
838	840	dc->debug = debug_defaults;
839	841
840	842	/*************************************************

drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c+1−0

@@ -793,6 +793,7 @@ static bool dce80_construct( · 792 unmodified lines
793	793	dc->caps.max_downscale_ratio = 200;
794	794	dc->caps.i2c_speed_in_khz = 40;
795	795	dc->caps.max_cursor_size = 128;
	796	+ dc->caps.dual_link_dvi = true;
796	797
797	798	/*************************************************
798	799	* Create resources *

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c+60−5

@@ -238,10 +238,24 @@ static void enable_power_gating_plane( · 237 unmodified lines
238	238	static void disable_vga(
239	239	struct dce_hwseq *hws)
240	240	{
	241	+ unsigned int in_vga_mode = 0;
	242	+
	243	+ REG_GET(D1VGA_CONTROL, D1VGA_MODE_ENABLE, &in_vga_mode);
	244	+
	245	+ if (in_vga_mode == 0)
	246	+ return;
	247	+
241	248	REG_WRITE(D1VGA_CONTROL, 0);
242		− REG_WRITE(D2VGA_CONTROL, 0);
243		− REG_WRITE(D3VGA_CONTROL, 0);
244		− REG_WRITE(D4VGA_CONTROL, 0);
	249	+
	250	+ /* HW Engineer's Notes:
	251	+ * During switch from vga->extended, if we set the VGA_TEST_ENABLE and
	252	+ * then hit the VGA_TEST_RENDER_START, then the DCHUBP timing gets updated correctly.
	253	+ *
	254	+ * Then vBIOS will have it poll for the VGA_TEST_RENDER_DONE and unset
	255	+ * VGA_TEST_ENABLE, to leave it in the same state as before.
	256	+ */
	257	+ REG_UPDATE(VGA_TEST_CONTROL, VGA_TEST_ENABLE, 1);
	258	+ REG_UPDATE(VGA_TEST_CONTROL, VGA_TEST_RENDER_START, 1);
245	259	}
246	260
247	261	static void dpp_pg_control(
@@ -1761,6 +1775,11 @@ static void update_dchubp_dpp( · 1513 unmodified lines
1761	1775	&pipe_ctx->plane_res.scl_data.viewport_c);
1762	1776	}
1763	1777
	1778	+ if (pipe_ctx->stream->cursor_attributes.address.quad_part != 0) {
	1779	+ dc->hwss.set_cursor_position(pipe_ctx);
	1780	+ dc->hwss.set_cursor_attribute(pipe_ctx);
	1781	+ }
	1782	+
1764	1783	if (plane_state->update_flags.bits.full_update) {
1765	1784	/gamut remap/
1766	1785	program_gamut_remap(pipe_ctx);
@@ -2296,7 +2315,7 @@ static bool dcn10_dummy_display_power_gating( · 529 unmodified lines
2296	2315	return true;
2297	2316	}
2298	2317
2299		−void dcn10_update_pending_status(struct pipe_ctx *pipe_ctx)
	2318	+static void dcn10_update_pending_status(struct pipe_ctx *pipe_ctx)
2300	2319	{
2301	2320	struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2302	2321	struct timing_generator *tg = pipe_ctx->stream_res.tg;
@@ -2316,12 +2335,46 @@ void dcn10_update_pending_status(struct pipe_ctx *pipe_ctx) · 13 unmodified lines
2316	2335	}
2317	2336	}
2318	2337
2319		−void dcn10_update_dchub(struct dce_hwseq hws, struct dchub_init_data dh_data)
	2338	+static void dcn10_update_dchub(struct dce_hwseq hws, struct dchub_init_data dh_data)
2320	2339	{
2321	2340	if (hws->ctx->dc->res_pool->hubbub != NULL)
2322	2341	hubbub1_update_dchub(hws->ctx->dc->res_pool->hubbub, dh_data);
2323	2342	}
2324	2343
	2344	+static void dcn10_set_cursor_position(struct pipe_ctx *pipe_ctx)
	2345	+{
	2346	+ struct dc_cursor_position pos_cpy = pipe_ctx->stream->cursor_position;
	2347	+ struct hubp *hubp = pipe_ctx->plane_res.hubp;
	2348	+ struct dpp *dpp = pipe_ctx->plane_res.dpp;
	2349	+ struct dc_cursor_mi_param param = {
	2350	+ .pixel_clk_khz = pipe_ctx->stream->timing.pix_clk_khz,
	2351	+ .ref_clk_khz = pipe_ctx->stream->ctx->dc->res_pool->ref_clock_inKhz,
	2352	+ .viewport_x_start = pipe_ctx->plane_res.scl_data.viewport.x,
	2353	+ .viewport_width = pipe_ctx->plane_res.scl_data.viewport.width,
	2354	+ .h_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.horz
	2355	+ };
	2356	+
	2357	+ if (pipe_ctx->plane_state->address.type
	2358	+ == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE)
	2359	+ pos_cpy.enable = false;
	2360	+
	2361	+ if (pipe_ctx->top_pipe && pipe_ctx->plane_state != pipe_ctx->top_pipe->plane_state)
	2362	+ pos_cpy.enable = false;
	2363	+
	2364	+ hubp->funcs->set_cursor_position(hubp, &pos_cpy, &param);
	2365	+ dpp->funcs->set_cursor_position(dpp, &pos_cpy, &param, hubp->curs_attr.width);
	2366	+}
	2367	+
	2368	+static void dcn10_set_cursor_attribute(struct pipe_ctx *pipe_ctx)
	2369	+{
	2370	+ struct dc_cursor_attributes *attributes = &pipe_ctx->stream->cursor_attributes;
	2371	+
	2372	+ pipe_ctx->plane_res.hubp->funcs->set_cursor_attributes(
	2373	+ pipe_ctx->plane_res.hubp, attributes);
	2374	+ pipe_ctx->plane_res.dpp->funcs->set_cursor_attributes(
	2375	+ pipe_ctx->plane_res.dpp, attributes->color_format);
	2376	+}
	2377	+
2325	2378	static const struct hw_sequencer_funcs dcn10_funcs = {
2326	2379	.program_gamut_remap = program_gamut_remap,
2327	2380	.program_csc_matrix = program_csc_matrix,
@@ -2362,6 +2415,8 @@ static const struct hw_sequencer_funcs dcn10_funcs = { · 34 unmodified lines
2362	2415	.edp_backlight_control = hwss_edp_backlight_control,
2363	2416	.edp_power_control = hwss_edp_power_control,
2364	2417	.edp_wait_for_hpd_ready = hwss_edp_wait_for_hpd_ready,
	2418	+ .set_cursor_position = dcn10_set_cursor_position,
	2419	+ .set_cursor_attribute = dcn10_set_cursor_attribute
2365	2420	};
2366	2421
2367	2422

drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h+1−2

@@ -123,8 +123,7 @@ struct link_encoder_funcs { · 122 unmodified lines
123	123	void (enable_tmds_output)(struct link_encoder enc,
124	124	enum clock_source_id clock_source,
125	125	enum dc_color_depth color_depth,
126		− bool hdmi,
127		− bool dual_link,
	126	+ enum signal_type signal,
128	127	uint32_t pixel_clock);
129	128	void (enable_dp_output)(struct link_encoder enc,
130	129	const struct dc_link_settings *link_settings,

drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h+3−0

@@ -198,6 +198,9 @@ struct hw_sequencer_funcs { · 197 unmodified lines
198	198	bool enable);
199	199	void (edp_wait_for_hpd_ready)(struct dc_link link, bool power_up);
200	200
	201	+ void (set_cursor_position)(struct pipe_ctx pipe);
	202	+ void (set_cursor_attribute)(struct pipe_ctx pipe);
	203	+
201	204	};
202	205
203	206	void color_space_to_black_color(

drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c+1−1

@@ -217,7 +217,7 @@ bool dce110_vblank_set( · 216 unmodified lines
217	217	core_dc->current_state->res_ctx.pipe_ctx[pipe_offset].stream_res.tg;
218	218
219	219	if (enable) {
220		− if (!tg->funcs->arm_vert_intr(tg, 2)) {
	220	+ if (!tg \|\| !tg->funcs->arm_vert_intr(tg, 2)) {
221	221	DC_ERROR("Failed to get VBLANK!\n");
222	222	return false;
223	223	}

drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.c+1−2

@@ -42,8 +42,7 @@ static void virtual_link_encoder_enable_tmds_output( · 41 unmodified lines
42	42	struct link_encoder *enc,
43	43	enum clock_source_id clock_source,
44	44	enum dc_color_depth color_depth,
45		− bool hdmi,
46		− bool dual_link,
	45	+ enum signal_type signal,
47	46	uint32_t pixel_clock) {}
48	47
49	48	static void virtual_link_encoder_enable_dp_output(

drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h+0−5

@@ -419,11 +419,6 @@ struct bios_event_info { · 418 unmodified lines
419	419	bool backlight_changed;
420	420	};
421	421
422		−enum {
423		− HDMI_PIXEL_CLOCK_IN_KHZ_297 = 297000,
424		− TMDS_PIXEL_CLOCK_IN_KHZ_165 = 165000
425		−};
426		−
427	422	/*
428	423	* DFS-bypass flag
429	424	*/

drivers/gpu/drm/amd/display/include/signal_types.h+5−0

@@ -26,6 +26,11 @@ · 25 unmodified lines
26	26	#ifndef __DC_SIGNAL_TYPES_H__
27	27	#define __DC_SIGNAL_TYPES_H__
28	28
	29	+/* Minimum pixel clock, in KHz. For TMDS signal is 25.00 MHz */
	30	+#define TMDS_MIN_PIXEL_CLOCK 25000
	31	+/* Maximum pixel clock, in KHz. For TMDS signal is 165.00 MHz */
	32	+#define TMDS_MAX_PIXEL_CLOCK 165000
	33	+
29	34	enum signal_type {
30	35	SIGNAL_TYPE_NONE = 0L, /* no signal */
31	36	SIGNAL_TYPE_DVI_SINGLE_LINK = (1 << 0),

drivers/gpu/drm/i915/i915_gem.c+5−1

@@ -3205,8 +3205,10 @@ void i915_gem_set_wedged(struct drm_i915_private *i915) · 3204 unmodified lines
3205	3205	* rolling the global seqno forward (since this would complete requests
3206	3206	* for which we haven't set the fence error to EIO yet).
3207	3207	*/
3208		− for_each_engine(engine, i915, id)
	3208	+ for_each_engine(engine, i915, id) {
	3209	+ i915_gem_reset_prepare_engine(engine);
3209	3210	engine->submit_request = nop_submit_request;
	3211	+ }
3210	3212
3211	3213	/*
3212	3214	* Make sure no one is running the old callback before we proceed with
@@ -3244,6 +3246,8 @@ void i915_gem_set_wedged(struct drm_i915_private *i915) · 31 unmodified lines
3244	3246	intel_engine_init_global_seqno(engine,
3245	3247	intel_engine_last_submit(engine));
3246	3248	spin_unlock_irqrestore(&engine->timeline->lock, flags);
	3249	+
	3250	+ i915_gem_reset_finish_engine(engine);
3247	3251	}
3248	3252
3249	3253	set_bit(I915_WEDGED, &i915->gpu_error.flags);

drivers/gpu/drm/i915/i915_perf.c+13−27

@@ -1303,9 +1303,8 @@ static void i915_oa_stream_destroy(struct i915_perf_stream *stream) · 1302 unmodified lines
1303	1303	*/
1304	1304	mutex_lock(&dev_priv->drm.struct_mutex);
1305	1305	dev_priv->perf.oa.exclusive_stream = NULL;
1306		− mutex_unlock(&dev_priv->drm.struct_mutex);
1307		−
1308	1306	dev_priv->perf.oa.ops.disable_metric_set(dev_priv);
	1307	+ mutex_unlock(&dev_priv->drm.struct_mutex);
1309	1308
1310	1309	free_oa_buffer(dev_priv);
1311	1310
@@ -1756,22 +1755,13 @@ static int gen8_switch_to_updated_kernel_context(struct drm_i915_private *dev_pr · 444 unmodified lines
1756	1755	* Note: it's only the RCS/Render context that has any OA state.
1757	1756	*/
1758	1757	static int gen8_configure_all_contexts(struct drm_i915_private *dev_priv,
1759		− const struct i915_oa_config *oa_config,
1760		− bool interruptible)
	1758	+ const struct i915_oa_config *oa_config)
1761	1759	{
1762	1760	struct i915_gem_context *ctx;
1763	1761	int ret;
1764	1762	unsigned int wait_flags = I915_WAIT_LOCKED;
1765	1763
1766		− if (interruptible) {
1767		− ret = i915_mutex_lock_interruptible(&dev_priv->drm);
1768		− if (ret)
1769		− return ret;
1770		−
1771		− wait_flags \|= I915_WAIT_INTERRUPTIBLE;
1772		− } else {
1773		− mutex_lock(&dev_priv->drm.struct_mutex);
1774		− }
	1764	+ lockdep_assert_held(&dev_priv->drm.struct_mutex);
1775	1765
1776	1766	/* Switch away from any user context. */
1777	1767	ret = gen8_switch_to_updated_kernel_context(dev_priv, oa_config);
@@ -1819,8 +1809,6 @@ static int gen8_configure_all_contexts(struct drm_i915_private *dev_priv, · 41 unmodified lines
1819	1809	}
1820	1810
1821	1811	out:
1822		− mutex_unlock(&dev_priv->drm.struct_mutex);
1823		−
1824	1812	return ret;
1825	1813	}
1826	1814
@@ -1863,7 +1851,7 @@ static int gen8_enable_metric_set(struct drm_i915_private *dev_priv, · 36 unmodified lines
1863	1851	* to make sure all slices/subslices are ON before writing to NOA
1864	1852	* registers.
1865	1853	*/
1866		− ret = gen8_configure_all_contexts(dev_priv, oa_config, true);
	1854	+ ret = gen8_configure_all_contexts(dev_priv, oa_config);
1867	1855	if (ret)
1868	1856	return ret;
1869	1857
@@ -1878,7 +1866,7 @@ static int gen8_enable_metric_set(struct drm_i915_private *dev_priv, · 8 unmodified lines
1878	1866	static void gen8_disable_metric_set(struct drm_i915_private *dev_priv)
1879	1867	{
1880	1868	/* Reset all contexts' slices/subslices configurations. */
1881		− gen8_configure_all_contexts(dev_priv, NULL, false);
	1869	+ gen8_configure_all_contexts(dev_priv, NULL);
1882	1870
1883	1871	I915_WRITE(GDT_CHICKEN_BITS, (I915_READ(GDT_CHICKEN_BITS) &
1884	1872	~GT_NOA_ENABLE));
@@ -1888,7 +1876,7 @@ static void gen8_disable_metric_set(struct drm_i915_private *dev_priv) · 3 unmodified lines
1888	1876	static void gen10_disable_metric_set(struct drm_i915_private *dev_priv)
1889	1877	{
1890	1878	/* Reset all contexts' slices/subslices configurations. */
1891		− gen8_configure_all_contexts(dev_priv, NULL, false);
	1879	+ gen8_configure_all_contexts(dev_priv, NULL);
1892	1880
1893	1881	/* Make sure we disable noa to save power. */
1894	1882	I915_WRITE(RPM_CONFIG1,
@@ -2138,6 +2126,10 @@ static int i915_oa_stream_init(struct i915_perf_stream *stream, · 243 unmodified lines
2138	2126	if (ret)
2139	2127	goto err_oa_buf_alloc;
2140	2128
	2129	+ ret = i915_mutex_lock_interruptible(&dev_priv->drm);
	2130	+ if (ret)
	2131	+ goto err_lock;
	2132	+
2141	2133	ret = dev_priv->perf.oa.ops.enable_metric_set(dev_priv,
2142	2134	stream->oa_config);
2143	2135	if (ret)
@@ -2145,23 +2137,17 @@ static int i915_oa_stream_init(struct i915_perf_stream *stream, · 1 unmodified line
2145	2137
2146	2138	stream->ops = &i915_oa_stream_ops;
2147	2139
2148		− /* Lock device for exclusive_stream access late because
2149		− * enable_metric_set() might lock as well on gen8+.
2150		− */
2151		− ret = i915_mutex_lock_interruptible(&dev_priv->drm);
2152		− if (ret)
2153		− goto err_lock;
2154		−
2155	2140	dev_priv->perf.oa.exclusive_stream = stream;
2156	2141
2157	2142	mutex_unlock(&dev_priv->drm.struct_mutex);
2158	2143
2159	2144	return 0;
2160	2145
2161		−err_lock:
	2146	+err_enable:
2162	2147	dev_priv->perf.oa.ops.disable_metric_set(dev_priv);
	2148	+ mutex_unlock(&dev_priv->drm.struct_mutex);
2163	2149
2164		−err_enable:
	2150	+err_lock:
2165	2151	free_oa_buffer(dev_priv);
2166	2152
2167	2153	err_oa_buf_alloc:

drivers/gpu/drm/i915/intel_lrc.c+5−0

@@ -719,6 +719,8 @@ static void execlists_cancel_requests(struct intel_engine_cs *engine) · 718 unmodified lines
719	719	struct rb_node *rb;
720	720	unsigned long flags;
721	721
	722	+ GEM_TRACE("%s\n", engine->name);
	723	+
722	724	spin_lock_irqsave(&engine->timeline->lock, flags);
723	725
724	726	/* Cancel the requests on the HW and clear the ELSP tracker. */
@@ -765,6 +767,9 @@ static void execlists_cancel_requests(struct intel_engine_cs *engine) · 40 unmodified lines
765	767	*/
766	768	clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted);
767	769
	770	+ /* Mark all CS interrupts as complete */
	771	+ execlists->active = 0;
	772	+
768	773	spin_unlock_irqrestore(&engine->timeline->lock, flags);
769	774	}
770	775

drivers/gpu/drm/radeon/cik.c+2−29

@@ -3221,35 +3221,8 @@ static void cik_gpu_init(struct radeon_device *rdev) · 3220 unmodified lines
3221	3221	case CHIP_KAVERI:
3222	3222	rdev->config.cik.max_shader_engines = 1;
3223	3223	rdev->config.cik.max_tile_pipes = 4;
3224		− if ((rdev->pdev->device == 0x1304) \|\|
3225		− (rdev->pdev->device == 0x1305) \|\|
3226		− (rdev->pdev->device == 0x130C) \|\|
3227		− (rdev->pdev->device == 0x130F) \|\|
3228		− (rdev->pdev->device == 0x1310) \|\|
3229		− (rdev->pdev->device == 0x1311) \|\|
3230		− (rdev->pdev->device == 0x131C)) {
3231		− rdev->config.cik.max_cu_per_sh = 8;
3232		− rdev->config.cik.max_backends_per_se = 2;
3233		− } else if ((rdev->pdev->device == 0x1309) \|\|
3234		− (rdev->pdev->device == 0x130A) \|\|
3235		− (rdev->pdev->device == 0x130D) \|\|
3236		− (rdev->pdev->device == 0x1313) \|\|
3237		− (rdev->pdev->device == 0x131D)) {
3238		− rdev->config.cik.max_cu_per_sh = 6;
3239		− rdev->config.cik.max_backends_per_se = 2;
3240		− } else if ((rdev->pdev->device == 0x1306) \|\|
3241		− (rdev->pdev->device == 0x1307) \|\|
3242		− (rdev->pdev->device == 0x130B) \|\|
3243		− (rdev->pdev->device == 0x130E) \|\|
3244		− (rdev->pdev->device == 0x1315) \|\|
3245		− (rdev->pdev->device == 0x1318) \|\|
3246		− (rdev->pdev->device == 0x131B)) {
3247		− rdev->config.cik.max_cu_per_sh = 4;
3248		− rdev->config.cik.max_backends_per_se = 1;
3249		− } else {
3250		− rdev->config.cik.max_cu_per_sh = 3;
3251		− rdev->config.cik.max_backends_per_se = 1;
3252		− }
	3224	+ rdev->config.cik.max_cu_per_sh = 8;
	3225	+ rdev->config.cik.max_backends_per_se = 2;
3253	3226	rdev->config.cik.max_sh_per_se = 1;
3254	3227	rdev->config.cik.max_texture_channel_caches = 4;
3255	3228	rdev->config.cik.max_gprs = 256;

drivers/gpu/drm/sun4i/sun4i_crtc.c+4−0

@@ -93,6 +93,8 @@ static void sun4i_crtc_atomic_disable(struct drm_crtc *crtc, · 92 unmodified lines
93	93
94	94	DRM_DEBUG_DRIVER("Disabling the CRTC\n");
95	95
	96	+ drm_crtc_vblank_off(crtc);
	97	+
96	98	sun4i_tcon_set_status(scrtc->tcon, encoder, false);
97	99
98	100	if (crtc->state->event && !crtc->state->active) {
@@ -113,6 +115,8 @@ static void sun4i_crtc_atomic_enable(struct drm_crtc *crtc, · 14 unmodified lines
113	115	DRM_DEBUG_DRIVER("Enabling the CRTC\n");
114	116
115	117	sun4i_tcon_set_status(scrtc->tcon, encoder, true);
	118	+
	119	+ drm_crtc_vblank_on(crtc);
116	120	}
117	121
118	122	static void sun4i_crtc_mode_set_nofb(struct drm_crtc *crtc)

drivers/gpu/drm/sun4i/sun4i_dotclock.c+4−1

@@ -132,10 +132,13 @@ static int sun4i_dclk_get_phase(struct clk_hw *hw) · 131 unmodified lines
132	132	static int sun4i_dclk_set_phase(struct clk_hw *hw, int degrees)
133	133	{
134	134	struct sun4i_dclk *dclk = hw_to_dclk(hw);
	135	+ u32 val = degrees / 120;
	136	+
	137	+ val <<= 28;
135	138
136	139	regmap_update_bits(dclk->regmap, SUN4I_TCON0_IO_POL_REG,
137	140	GENMASK(29, 28),
138		− degrees / 120);
	141	+ val);
139	142
140	143	return 0;
141	144	}

drivers/gpu/drm/sun4i/sun4i_rgb.c+2−0

@@ -92,6 +92,8 @@ static int sun4i_rgb_mode_valid(struct drm_connector *connector, · 91 unmodified lines
92	92
93	93	DRM_DEBUG_DRIVER("Vertical parameters OK\n");
94	94
	95	+ tcon->dclk_min_div = 6;
	96	+ tcon->dclk_max_div = 127;
95	97	rounded_rate = clk_round_rate(tcon->dclk, rate);
96	98	if (rounded_rate < rate)
97	99	return MODE_CLOCK_LOW;

drivers/gpu/drm/sun4i/sun4i_tcon.c+49−43

@@ -101,10 +101,12 @@ static void sun4i_tcon_channel_set_status(struct sun4i_tcon *tcon, int channel, · 100 unmodified lines
101	101	return;
102	102	}
103	103
104		− if (enabled)
	104	+ if (enabled) {
105	105	clk_prepare_enable(clk);
106		− else
	106	+ } else {
	107	+ clk_rate_exclusive_put(clk);
107	108	clk_disable_unprepare(clk);
	109	+ }
108	110	}
109	111
110	112	static void sun4i_tcon_lvds_set_status(struct sun4i_tcon *tcon,
@@ -873,52 +875,56 @@ static int sun4i_tcon_bind(struct device dev, struct device master, · 762 unmodified lines
873	875	return ret;
874	876	}
875	877
876		− /*
877		− * This can only be made optional since we've had DT nodes
878		− * without the LVDS reset properties.
879		− *
880		− * If the property is missing, just disable LVDS, and print a
881		− * warning.
882		− */
883		− tcon->lvds_rst = devm_reset_control_get_optional(dev, "lvds");
884		− if (IS_ERR(tcon->lvds_rst)) {
885		− dev_err(dev, "Couldn't get our reset line\n");
886		− return PTR_ERR(tcon->lvds_rst);
887		− } else if (tcon->lvds_rst) {
888		− has_lvds_rst = true;
889		− reset_control_reset(tcon->lvds_rst);
890		− } else {
891		− has_lvds_rst = false;
892		− }
	878	+ if (tcon->quirks->supports_lvds) {
	879	+ /*
	880	+ * This can only be made optional since we've had DT
	881	+ * nodes without the LVDS reset properties.
	882	+ *
	883	+ * If the property is missing, just disable LVDS, and
	884	+ * print a warning.
	885	+ */
	886	+ tcon->lvds_rst = devm_reset_control_get_optional(dev, "lvds");
	887	+ if (IS_ERR(tcon->lvds_rst)) {
	888	+ dev_err(dev, "Couldn't get our reset line\n");
	889	+ return PTR_ERR(tcon->lvds_rst);
	890	+ } else if (tcon->lvds_rst) {
	891	+ has_lvds_rst = true;
	892	+ reset_control_reset(tcon->lvds_rst);
	893	+ } else {
	894	+ has_lvds_rst = false;
	895	+ }
893	896
894		− /*
895		− * This can only be made optional since we've had DT nodes
896		− * without the LVDS reset properties.
897		− *
898		− * If the property is missing, just disable LVDS, and print a
899		− * warning.
900		− */
901		− if (tcon->quirks->has_lvds_alt) {
902		− tcon->lvds_pll = devm_clk_get(dev, "lvds-alt");
903		− if (IS_ERR(tcon->lvds_pll)) {
904		− if (PTR_ERR(tcon->lvds_pll) == -ENOENT) {
905		− has_lvds_alt = false;
	897	+ /*
	898	+ * This can only be made optional since we've had DT
	899	+ * nodes without the LVDS reset properties.
	900	+ *
	901	+ * If the property is missing, just disable LVDS, and
	902	+ * print a warning.
	903	+ */
	904	+ if (tcon->quirks->has_lvds_alt) {
	905	+ tcon->lvds_pll = devm_clk_get(dev, "lvds-alt");
	906	+ if (IS_ERR(tcon->lvds_pll)) {
	907	+ if (PTR_ERR(tcon->lvds_pll) == -ENOENT) {
	908	+ has_lvds_alt = false;
	909	+ } else {
	910	+ dev_err(dev, "Couldn't get the LVDS PLL\n");
	911	+ return PTR_ERR(tcon->lvds_pll);
	912	+ }
906	913	} else {
907		− dev_err(dev, "Couldn't get the LVDS PLL\n");
908		− return PTR_ERR(tcon->lvds_pll);
	914	+ has_lvds_alt = true;
909	915	}
910		− } else {
911		− has_lvds_alt = true;
912	916	}
913		− }
914	917
915		− if (!has_lvds_rst \|\| (tcon->quirks->has_lvds_alt && !has_lvds_alt)) {
916		− dev_warn(dev,
917		− "Missing LVDS properties, Please upgrade your DT\n");
918		− dev_warn(dev, "LVDS output disabled\n");
919		− can_lvds = false;
	918	+ if (!has_lvds_rst \|\|
	919	+ (tcon->quirks->has_lvds_alt && !has_lvds_alt)) {
	920	+ dev_warn(dev, "Missing LVDS properties, Please upgrade your DT\n");
	921	+ dev_warn(dev, "LVDS output disabled\n");
	922	+ can_lvds = false;
	923	+ } else {
	924	+ can_lvds = true;
	925	+ }
920	926	} else {
921		− can_lvds = true;
	927	+ can_lvds = false;
922	928	}
923	929
924	930	ret = sun4i_tcon_init_clocks(dev, tcon);
@@ -1137,7 +1143,7 @@ static const struct sun4i_tcon_quirks sun8i_a33_quirks = { · 212 unmodified lines
1137	1143	};
1138	1144
1139	1145	static const struct sun4i_tcon_quirks sun8i_a83t_lcd_quirks = {
1140		− /* nothing is supported */
	1146	+ .supports_lvds = true,
1141	1147	};
1142	1148
1143	1149	static const struct sun4i_tcon_quirks sun8i_v3s_quirks = {

drivers/gpu/drm/sun4i/sun4i_tcon.h+1−0

@@ -175,6 +175,7 @@ struct sun4i_tcon_quirks { · 174 unmodified lines
175	175	bool has_channel_1; /* a33 does not have channel 1 */
176	176	bool has_lvds_alt; /* Does the LVDS clock have a parent other than the TCON clock? */
177	177	bool needs_de_be_mux; /* sun6i needs mux to select backend */
	178	+ bool supports_lvds; /* Does the TCON support an LVDS output? */
178	179
179	180	/* callback to handle tcon muxing options */
180	181	int (set_mux)(struct sun4i_tcon , const struct drm_encoder *);

Merge tag 'drm-fixes-for-v4.16-rc5' of git://people.freedesktop.org/~airlied/linux

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