When a dual-port VHCA sends a RoCE packet on its non-native port, and the packet arrives to its affiliated vport FDB, a mismatch might occur on the rules that match the packet source vport. So we replace the match on source port with the match on metadata that was configured in ingress ACL, and that metadata will be passed further also to the NIC RX table of the eswitch manager. Introduce vport metadata matching bits and enum constants as a pre-step towards metadata matching. o metadata type C registers in the misc parameters 2 fields. o esw_uplink_ingress_acl bit in esw cap. If it set, the device supports ingress ACL for the uplink vport. o fdb_to_vport_reg_* bits in flow table cap and esw vport context, to support propagating the metadata to the nic rx through the loopback path. o flow_source in flow context, to indicate the known origin of packets. o enum constants, to support the above bits.
Unified · Split
| @@ -528,7 +528,21 @@ struct mlx5_ifc_fte_match_set_misc2_bits { · 527 unmodified lines | ||
| 528 | 528 | |
| 529 | 529 | struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp; |
| 530 | 530 | |
| 531 | − u8 reserved_at_80[0x100]; | |
| 531 | + u8 metadata_reg_c_7[0x20]; | |
| 532 | + | |
| 533 | + u8 metadata_reg_c_6[0x20]; | |
| 534 | + | |
| 535 | + u8 metadata_reg_c_5[0x20]; | |
| 536 | + | |
| 537 | + u8 metadata_reg_c_4[0x20]; | |
| 538 | + | |
| 539 | + u8 metadata_reg_c_3[0x20]; | |
| 540 | + | |
| 541 | + u8 metadata_reg_c_2[0x20]; | |
| 542 | + | |
| 543 | + u8 metadata_reg_c_1[0x20]; | |
| 544 | + | |
| 545 | + u8 metadata_reg_c_0[0x20]; | |
| 532 | 546 | |
| 533 | 547 | u8 metadata_reg_a[0x20]; |
| 534 | 548 | |
| @@ -636,8 +650,22 @@ struct mlx5_ifc_flow_table_nic_cap_bits { · 101 unmodified lines | ||
| 636 | 650 | u8 reserved_at_e00[0x7200]; |
| 637 | 651 | }; |
| 638 | 652 | |
| 653 | +enum { | |
| 654 | + MLX5_FDB_TO_VPORT_REG_C_0 = 0x01, | |
| 655 | + MLX5_FDB_TO_VPORT_REG_C_1 = 0x02, | |
| 656 | + MLX5_FDB_TO_VPORT_REG_C_2 = 0x04, | |
| 657 | + MLX5_FDB_TO_VPORT_REG_C_3 = 0x08, | |
| 658 | + MLX5_FDB_TO_VPORT_REG_C_4 = 0x10, | |
| 659 | + MLX5_FDB_TO_VPORT_REG_C_5 = 0x20, | |
| 660 | + MLX5_FDB_TO_VPORT_REG_C_6 = 0x40, | |
| 661 | + MLX5_FDB_TO_VPORT_REG_C_7 = 0x80, | |
| 662 | +}; | |
| 663 | + | |
| 639 | 664 | struct mlx5_ifc_flow_table_eswitch_cap_bits { |
| 640 | − u8 reserved_at_0[0x1a]; | |
| 665 | + u8 fdb_to_vport_reg_c_id[0x8]; | |
| 666 | + u8 reserved_at_8[0xf]; | |
| 667 | + u8 flow_source[0x1]; | |
| 668 | + u8 reserved_at_18[0x2]; | |
| 641 | 669 | u8 multi_fdb_encap[0x1]; |
| 642 | 670 | u8 reserved_at_1b[0x1]; |
| 643 | 671 | u8 fdb_multi_path_to_table[0x1]; |
| @@ -665,7 +693,9 @@ struct mlx5_ifc_e_switch_cap_bits { · 21 unmodified lines | ||
| 665 | 693 | u8 vport_svlan_insert[0x1]; |
| 666 | 694 | u8 vport_cvlan_insert_if_not_exist[0x1]; |
| 667 | 695 | u8 vport_cvlan_insert_overwrite[0x1]; |
| 668 | − u8 reserved_at_5[0x14]; | |
| 696 | + u8 reserved_at_5[0x3]; | |
| 697 | + u8 esw_uplink_ingress_acl[0x1]; | |
| 698 | + u8 reserved_at_9[0x10]; | |
| 669 | 699 | u8 esw_functions_changed[0x1]; |
| 670 | 700 | u8 reserved_at_1a[0x1]; |
| 671 | 701 | u8 ecpf_vport_exists[0x1]; |
| @@ -2555,6 +2585,12 @@ enum { · 1883 unmodified lines | ||
| 2555 | 2585 | MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800, |
| 2556 | 2586 | }; |
| 2557 | 2587 | |
| 2588 | +enum { | |
| 2589 | + MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT = 0x0, | |
| 2590 | + MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK = 0x1, | |
| 2591 | + MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT = 0x2, | |
| 2592 | +}; | |
| 2593 | + | |
| 2558 | 2594 | struct mlx5_ifc_vlan_bits { |
| 2559 | 2595 | u8 ethtype[0x10]; |
| 2560 | 2596 | u8 prio[0x3]; |
| @@ -2574,7 +2610,9 @@ struct mlx5_ifc_flow_context_bits { · 13 unmodified lines | ||
| 2574 | 2610 | u8 action[0x10]; |
| 2575 | 2611 | |
| 2576 | 2612 | u8 extended_destination[0x1]; |
| 2577 | − u8 reserved_at_80[0x7]; | |
| 2613 | + u8 reserved_at_81[0x1]; | |
| 2614 | + u8 flow_source[0x2]; | |
| 2615 | + u8 reserved_at_84[0x4]; | |
| 2578 | 2616 | u8 destination_list_size[0x18]; |
| 2579 | 2617 | |
| 2580 | 2618 | u8 reserved_at_a0[0x8]; |
| @@ -3099,12 +3137,14 @@ struct mlx5_ifc_hca_vport_context_bits { · 518 unmodified lines | ||
| 3099 | 3137 | }; |
| 3100 | 3138 | |
| 3101 | 3139 | struct mlx5_ifc_esw_vport_context_bits { |
| 3102 | − u8 reserved_at_0[0x3]; | |
| 3140 | + u8 fdb_to_vport_reg_c[0x1]; | |
| 3141 | + u8 reserved_at_1[0x2]; | |
| 3103 | 3142 | u8 vport_svlan_strip[0x1]; |
| 3104 | 3143 | u8 vport_cvlan_strip[0x1]; |
| 3105 | 3144 | u8 vport_svlan_insert[0x1]; |
| 3106 | 3145 | u8 vport_cvlan_insert[0x2]; |
| 3107 | − u8 reserved_at_8[0x18]; | |
| 3146 | + u8 fdb_to_vport_reg_c_id[0x8]; | |
| 3147 | + u8 reserved_at_10[0x10]; | |
| 3108 | 3148 | |
| 3109 | 3149 | u8 reserved_at_20[0x20]; |
| 3110 | 3150 | |
| @@ -4985,7 +5025,8 @@ struct mlx5_ifc_modify_esw_vport_context_out_bits { · 1874 unmodified lines | ||
| 4985 | 5025 | }; |
| 4986 | 5026 | |
| 4987 | 5027 | struct mlx5_ifc_esw_vport_context_fields_select_bits { |
| 4988 | − u8 reserved_at_0[0x1c]; | |
| 5028 | + u8 reserved_at_0[0x1b]; | |
| 5029 | + u8 fdb_to_vport_reg_c_id[0x1]; | |
| 4989 | 5030 | u8 vport_cvlan_insert[0x1]; |
| 4990 | 5031 | u8 vport_svlan_insert[0x1]; |
| 4991 | 5032 | u8 vport_cvlan_strip[0x1]; |
| @@ -5182,6 +5223,7 @@ enum { · 190 unmodified lines | ||
| 5182 | 5223 | MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16, |
| 5183 | 5224 | MLX5_ACTION_IN_FIELD_OUT_FIRST_VID = 0x17, |
| 5184 | 5225 | MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47, |
| 5226 | + MLX5_ACTION_IN_FIELD_METADATA_REG_C_0 = 0x51, | |
| 5185 | 5227 | }; |
| 5186 | 5228 | |
| 5187 | 5229 | struct mlx5_ifc_alloc_modify_header_context_out_bits { |