Pull irq core updates from Thomas Gleixner: "A rather large update for the interrupt core code and the irq chip drivers: - Add a new bitmap matrix allocator and supporting changes, which is used to replace the x86 vector allocator which comes with separate pull request. This allows to replace the convoluted nested loop allocation function in x86 with a facility which supports the recently added property of managed interrupts proper and allows to switch to a best effort vector reservation scheme, which addresses problems with vector exhaustion. - A large update to the ARM GIC-V3-ITS driver adding support for range selectors. - New interrupt controllers: - Meson and Meson8 GPIO - BCM7271 L2 - Socionext EXIU If you expected that this will stop at some point, I have to disappoint you. There are new ones posted already. Sigh! - STM32 interrupt controller support for new platforms. - A pile of fixes, cleanups and updates to the MIPS GIC driver - The usual small fixes, cleanups and updates all over the place. Most visible one is to move the irq chip drivers Kconfig switches into a separate Kconfig menu" * 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (70 commits) genirq: Fix type of shifting literal 1 in __setup_irq() irqdomain: Drop pointless NULL check in virq_debug_show_one genirq/proc: Return proper error code when irq_set_affinity() fails irq/work: Use llist_for_each_entry_safe irqchip: mips-gic: Print warning if inherited GIC base is used irqchip/mips-gic: Add pr_fmt and reword pr_* messages irqchip/stm32: Move the wakeup on interrupt mask irqchip/stm32: Fix initial values irqchip/stm32: Add stm32h7 support dt-bindings/interrupt-controllers: Add compatible string for stm32h7 irqchip/stm32: Add multi-bank management irqchip/stm32: Select GENERIC_IRQ_CHIP irqchip/exiu: Add support for Socionext Synquacer EXIU controller dt-bindings: Add description of Socionext EXIU interrupt controller irqchip/gic-v3-its: Fix VPE activate callback return value irqchip: mips-gic: Make IPI bitmaps static irqchip: mips-gic: Share register writes in gic_set_type() irqchip: mips-gic: Remove gic_vpes variable irqchip: mips-gic: Use num_possible_cpus() to reserve IPIs irqchip: mips-gic: Configure EIC when CPUs come online ...
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| 1 | #undef TRACE_SYSTEM | ||
| 2 | #define TRACE_SYSTEM irq_matrix | ||
| 3 | |||
| 4 | #if !defined(_TRACE_IRQ_MATRIX_H) || defined(TRACE_HEADER_MULTI_READ) | ||
| 5 | #define _TRACE_IRQ_MATRIX_H | ||
| 6 | |||
| 7 | #include <linux/tracepoint.h> | ||
| 8 | |||
| 9 | struct irq_matrix; | ||
| 10 | struct cpumap; | ||
| 11 | |||
| 12 | DECLARE_EVENT_CLASS(irq_matrix_global, | ||
| 13 | |||
| 14 | TP_PROTO(struct irq_matrix *matrix), | ||
| 15 | |||
| 16 | TP_ARGS(matrix), | ||
| 17 | |||
| 18 | TP_STRUCT__entry( | ||
| 19 | __field( unsigned int, online_maps ) | ||
| 20 | __field( unsigned int, global_available ) | ||
| 21 | __field( unsigned int, global_reserved ) | ||
| 22 | __field( unsigned int, total_allocated ) | ||
| 23 | ), | ||
| 24 | |||
| 25 | TP_fast_assign( | ||
| 26 | __entry->online_maps = matrix->online_maps; | ||
| 27 | __entry->global_available = matrix->global_available; | ||
| 28 | __entry->global_reserved = matrix->global_reserved; | ||
| 29 | __entry->total_allocated = matrix->total_allocated; | ||
| 30 | ), | ||
| 31 | |||
| 32 | TP_printk("online_maps=%d global_avl=%u, global_rsvd=%u, total_alloc=%u", | ||
| 33 | __entry->online_maps, __entry->global_available, | ||
| 34 | __entry->global_reserved, __entry->total_allocated) | ||
| 35 | ); | ||
| 36 | |||
| 37 | DECLARE_EVENT_CLASS(irq_matrix_global_update, | ||
| 38 | |||
| 39 | TP_PROTO(int bit, struct irq_matrix *matrix), | ||
| 40 | |||
| 41 | TP_ARGS(bit, matrix), | ||
| 42 | |||
| 43 | TP_STRUCT__entry( | ||
| 44 | __field( int, bit ) | ||
| 45 | __field( unsigned int, online_maps ) | ||
| 46 | __field( unsigned int, global_available ) | ||
| 47 | __field( unsigned int, global_reserved ) | ||
| 48 | __field( unsigned int, total_allocated ) | ||
| 49 | ), | ||
| 50 | |||
| 51 | TP_fast_assign( | ||
| 52 | __entry->bit = bit; | ||
| 53 | __entry->online_maps = matrix->online_maps; | ||
| 54 | __entry->global_available = matrix->global_available; | ||
| 55 | __entry->global_reserved = matrix->global_reserved; | ||
| 56 | __entry->total_allocated = matrix->total_allocated; | ||
| 57 | ), | ||
| 58 | |||
| 59 | TP_printk("bit=%d online_maps=%d global_avl=%u, global_rsvd=%u, total_alloc=%u", | ||
| 60 | __entry->bit, __entry->online_maps, | ||
| 61 | __entry->global_available, __entry->global_reserved, | ||
| 62 | __entry->total_allocated) | ||
| 63 | ); | ||
| 64 | |||
| 65 | DECLARE_EVENT_CLASS(irq_matrix_cpu, | ||
| 66 | |||
| 67 | TP_PROTO(int bit, unsigned int cpu, struct irq_matrix *matrix, | ||
| 68 | struct cpumap *cmap), | ||
| 69 | |||
| 70 | TP_ARGS(bit, cpu, matrix, cmap), | ||
| 71 | |||
| 72 | TP_STRUCT__entry( | ||
| 73 | __field( int, bit ) | ||
| 74 | __field( unsigned int, cpu ) | ||
| 75 | __field( bool, online ) | ||
| 76 | __field( unsigned int, available ) | ||
| 77 | __field( unsigned int, allocated ) | ||
| 78 | __field( unsigned int, managed ) | ||
| 79 | __field( unsigned int, online_maps ) | ||
| 80 | __field( unsigned int, global_available ) | ||
| 81 | __field( unsigned int, global_reserved ) | ||
| 82 | __field( unsigned int, total_allocated ) | ||
| 83 | ), | ||
| 84 | |||
| 85 | TP_fast_assign( | ||
| 86 | __entry->bit = bit; | ||
| 87 | __entry->cpu = cpu; | ||
| 88 | __entry->online = cmap->online; | ||
| 89 | __entry->available = cmap->available; | ||
| 90 | __entry->allocated = cmap->allocated; | ||
| 91 | __entry->managed = cmap->managed; | ||
| 92 | __entry->online_maps = matrix->online_maps; | ||
| 93 | __entry->global_available = matrix->global_available; | ||
| 94 | __entry->global_reserved = matrix->global_reserved; | ||
| 95 | __entry->total_allocated = matrix->total_allocated; | ||
| 96 | ), | ||
| 97 | |||
| 98 | TP_printk("bit=%d cpu=%u online=%d avl=%u alloc=%u managed=%u online_maps=%u global_avl=%u, global_rsvd=%u, total_alloc=%u", | ||
| 99 | __entry->bit, __entry->cpu, __entry->online, | ||
| 100 | __entry->available, __entry->allocated, | ||
| 101 | __entry->managed, __entry->online_maps, | ||
| 102 | __entry->global_available, __entry->global_reserved, | ||
| 103 | __entry->total_allocated) | ||
| 104 | ); | ||
| 105 | |||
| 106 | DEFINE_EVENT(irq_matrix_global, irq_matrix_online, | ||
| 107 | |||
| 108 | TP_PROTO(struct irq_matrix *matrix), | ||
| 109 | |||
| 110 | TP_ARGS(matrix) | ||
| 111 | ); | ||
| 112 | |||
| 113 | DEFINE_EVENT(irq_matrix_global, irq_matrix_offline, | ||
| 114 | |||
| 115 | TP_PROTO(struct irq_matrix *matrix), | ||
| 116 | |||
| 117 | TP_ARGS(matrix) | ||
| 118 | ); | ||
| 119 | |||
| 120 | DEFINE_EVENT(irq_matrix_global, irq_matrix_reserve, | ||
| 121 | |||
| 122 | TP_PROTO(struct irq_matrix *matrix), | ||
| 123 | |||
| 124 | TP_ARGS(matrix) | ||
| 125 | ); | ||
| 126 | |||
| 127 | DEFINE_EVENT(irq_matrix_global, irq_matrix_remove_reserved, | ||
| 128 | |||
| 129 | TP_PROTO(struct irq_matrix *matrix), | ||
| 130 | |||
| 131 | TP_ARGS(matrix) | ||
| 132 | ); | ||
| 133 | |||
| 134 | DEFINE_EVENT(irq_matrix_global_update, irq_matrix_assign_system, | ||
| 135 | |||
| 136 | TP_PROTO(int bit, struct irq_matrix *matrix), | ||
| 137 | |||
| 138 | TP_ARGS(bit, matrix) | ||
| 139 | ); | ||
| 140 | |||
| 141 | DEFINE_EVENT(irq_matrix_cpu, irq_matrix_alloc_reserved, | ||
| 142 | |||
| 143 | TP_PROTO(int bit, unsigned int cpu, | ||
| 144 | struct irq_matrix *matrix, struct cpumap *cmap), | ||
| 145 | |||
| 146 | TP_ARGS(bit, cpu, matrix, cmap) | ||
| 147 | ); | ||
| 148 | |||
| 149 | DEFINE_EVENT(irq_matrix_cpu, irq_matrix_reserve_managed, | ||
| 150 | |||
| 151 | TP_PROTO(int bit, unsigned int cpu, | ||
| 152 | struct irq_matrix *matrix, struct cpumap *cmap), | ||
| 153 | |||
| 154 | TP_ARGS(bit, cpu, matrix, cmap) | ||
| 155 | ); | ||
| 156 | |||
| 157 | DEFINE_EVENT(irq_matrix_cpu, irq_matrix_remove_managed, | ||
| 158 | |||
| 159 | TP_PROTO(int bit, unsigned int cpu, | ||
| 160 | struct irq_matrix *matrix, struct cpumap *cmap), | ||
| 161 | |||
| 162 | TP_ARGS(bit, cpu, matrix, cmap) | ||
| 163 | ); | ||
| 164 | |||
| 165 | DEFINE_EVENT(irq_matrix_cpu, irq_matrix_alloc_managed, | ||
| 166 | |||
| 167 | TP_PROTO(int bit, unsigned int cpu, | ||
| 168 | struct irq_matrix *matrix, struct cpumap *cmap), | ||
| 169 | |||
| 170 | TP_ARGS(bit, cpu, matrix, cmap) | ||
| 171 | ); | ||
| 172 | |||
| 173 | DEFINE_EVENT(irq_matrix_cpu, irq_matrix_assign, | ||
| 174 | |||
| 175 | TP_PROTO(int bit, unsigned int cpu, | ||
| 176 | struct irq_matrix *matrix, struct cpumap *cmap), | ||
| 177 | |||
| 178 | TP_ARGS(bit, cpu, matrix, cmap) | ||
| 179 | ); | ||
| 180 | |||
| 181 | DEFINE_EVENT(irq_matrix_cpu, irq_matrix_alloc, | ||
| 182 | |||
| 183 | TP_PROTO(int bit, unsigned int cpu, | ||
| 184 | struct irq_matrix *matrix, struct cpumap *cmap), | ||
| 185 | |||
| 186 | TP_ARGS(bit, cpu, matrix, cmap) | ||
| 187 | ); | ||
| 188 | |||
| 189 | DEFINE_EVENT(irq_matrix_cpu, irq_matrix_free, | ||
| 190 | |||
| 191 | TP_PROTO(int bit, unsigned int cpu, | ||
| 192 | struct irq_matrix *matrix, struct cpumap *cmap), | ||
| 193 | |||
| 194 | TP_ARGS(bit, cpu, matrix, cmap) | ||
| 195 | ); | ||
| 196 | |||
| 197 | |||
| 198 | #endif /* _TRACE_IRQ_H */ | ||
| 199 | |||
| 200 | /* This part must be outside protection */ | ||
| 201 | #include <trace/define_trace.h> | ||