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drm/amdgpu: cleanup UAPI comments

No functional change.

Christian König committed 11 years ago

Commit 675da0d1 parent 692a59e1 file · +78 −41Browse files

Showing the changes to include/uapi (1 of 1 file). Show all

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include/uapi/drm/amdgpu_drm.h+78−41
@@ -141,12 +141,17 @@ union drm_amdgpu_bo_list { · 140 unmodified lines
141141
142142 /* GPU reset status */
143143 #define AMDGPU_CTX_NO_RESET 0
144−#define AMDGPU_CTX_GUILTY_RESET 1 /* this the context caused it */
145−#define AMDGPU_CTX_INNOCENT_RESET 2 /* some other context caused it */
146−#define AMDGPU_CTX_UNKNOWN_RESET 3 /* unknown cause */
144+/* this the context caused it */
145+#define AMDGPU_CTX_GUILTY_RESET 1
146+/* some other context caused it */
147+#define AMDGPU_CTX_INNOCENT_RESET 2
148+/* unknown cause */
149+#define AMDGPU_CTX_UNKNOWN_RESET 3
147150
148151 struct drm_amdgpu_ctx_in {
152+ /** AMDGPU_CTX_OP_* */
149153 uint32_t op;
154+ /** For future use, no flags defined so far */
150155 uint32_t flags;
151156 uint32_t ctx_id;
152157 uint32_t _pad;
@@ -159,6 +164,7 @@ union drm_amdgpu_ctx_out { · 6 unmodified lines
159164 } alloc;
160165
161166 struct {
167+ /** For future use, no flags defined so far */
162168 uint64_t flags;
163169 /** Number of resets caused by this context so far. */
164170 uint32_t hangs;
@@ -185,7 +191,9 @@ union drm_amdgpu_ctx { · 20 unmodified lines
185191 struct drm_amdgpu_gem_userptr {
186192 uint64_t addr;
187193 uint64_t size;
194+ /* AMDGPU_GEM_USERPTR_* */
188195 uint32_t flags;
196+ /* Resulting GEM handle */
189197 uint32_t handle;
190198 };
191199
@@ -217,23 +225,29 @@ struct drm_amdgpu_gem_userptr { · 25 unmodified lines
217225
218226 /** The same structure is shared for input/output */
219227 struct drm_amdgpu_gem_metadata {
220− uint32_t handle; /* GEM Object handle */
221− uint32_t op; /** Do we want get or set metadata */
228+ /** GEM Object handle */
229+ uint32_t handle;
230+ /** Do we want get or set metadata */
231+ uint32_t op;
222232 struct {
233+ /** For future use, no flags defined so far */
223234 uint64_t flags;
224− uint64_t tiling_info; /* family specific tiling info */
235+ /** family specific tiling info */
236+ uint64_t tiling_info;
225237 uint32_t data_size_bytes;
226238 uint32_t data[64];
227239 } data;
228240 };
229241
230242 struct drm_amdgpu_gem_mmap_in {
231− uint32_t handle; /** the GEM object handle */
243+ /** the GEM object handle */
244+ uint32_t handle;
232245 uint32_t _pad;
233246 };
234247
235248 struct drm_amdgpu_gem_mmap_out {
236− uint64_t addr_ptr; /** mmap offset from the vma offset manager */
249+ /** mmap offset from the vma offset manager */
250+ uint64_t addr_ptr;
237251 };
238252
239253 union drm_amdgpu_gem_mmap {
@@ -242,14 +256,19 @@ union drm_amdgpu_gem_mmap { · 2 unmodified lines
242256 };
243257
244258 struct drm_amdgpu_gem_wait_idle_in {
245− uint32_t handle; /* GEM object handle */
259+ /** GEM object handle */
260+ uint32_t handle;
261+ /** For future use, no flags defined so far */
246262 uint32_t flags;
247− uint64_t timeout; /* Timeout to wait. If 0 then returned immediately with the status */
263+ /** Absolute timeout to wait */
264+ uint64_t timeout;
248265 };
249266
250267 struct drm_amdgpu_gem_wait_idle_out {
251− uint32_t status; /* BO status: 0 - BO is idle, 1 - BO is busy */
252− uint32_t domain; /* Returned current memory domain */
268+ /** BO status: 0 - BO is idle, 1 - BO is busy */
269+ uint32_t status;
270+ /** Returned current memory domain */
271+ uint32_t domain;
253272 };
254273
255274 union drm_amdgpu_gem_wait_idle {
@@ -258,7 +277,9 @@ union drm_amdgpu_gem_wait_idle { · 2 unmodified lines
258277 };
259278
260279 struct drm_amdgpu_wait_cs_in {
280+ /** Command submission handle */
261281 uint64_t handle;
282+ /** Absolute timeout to wait */
262283 uint64_t timeout;
263284 uint32_t ip_type;
264285 uint32_t ip_instance;
@@ -267,6 +288,7 @@ struct drm_amdgpu_wait_cs_in { · 2 unmodified lines
267288 };
268289
269290 struct drm_amdgpu_wait_cs_out {
291+ /** CS status: 0 - CS completed, 1 - CS still busy */
270292 uint64_t status;
271293 };
272294
@@ -275,16 +297,19 @@ union drm_amdgpu_wait_cs { · 2 unmodified lines
275297 struct drm_amdgpu_wait_cs_out out;
276298 };
277299
300+#define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0
301+#define AMDGPU_GEM_OP_SET_PLACEMENT 1
302+
278303 /* Sets or returns a value associated with a buffer. */
279304 struct drm_amdgpu_gem_op {
280− uint32_t handle; /* buffer */
281− uint32_t op; /* AMDGPU_GEM_OP_* */
282− uint64_t value; /* input or return value */
305+ /** GEM object handle */
306+ uint32_t handle;
307+ /** AMDGPU_GEM_OP_* */
308+ uint32_t op;
309+ /** Input or return value */
310+ uint64_t value;
283311 };
284312
285−#define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0
286−#define AMDGPU_GEM_OP_SET_PLACEMENT 1
287−
288313 #define AMDGPU_VA_OP_MAP 1
289314 #define AMDGPU_VA_OP_UNMAP 2
290315
@@ -297,19 +322,18 @@ struct drm_amdgpu_gem_op { · 6 unmodified lines
297322 #define AMDGPU_VM_PAGE_EXECUTABLE (1 << 3)
298323
299324 struct drm_amdgpu_gem_va {
300− /* GEM object handle */
325+ /** GEM object handle */
301326 uint32_t handle;
302327 uint32_t _pad;
303− /* map or unmap*/
328+ /** AMDGPU_VA_OP_* */
304329 uint32_t operation;
305− /* specify mapping flags */
330+ /** AMDGPU_VM_PAGE_* */
306331 uint32_t flags;
307− /* va address to assign . Must be correctly aligned.*/
332+ /** va address to assign . Must be correctly aligned.*/
308333 uint64_t va_address;
309− /* Specify offset inside of BO to assign. Must be correctly aligned.*/
334+ /** Specify offset inside of BO to assign. Must be correctly aligned.*/
310335 uint64_t offset_in_bo;
311− /* Specify mapping size. If 0 and offset is 0 then map the whole BO.*/
312− /* Must be correctly aligned. */
336+ /** Specify mapping size. Must be correctly aligned. */
313337 uint64_t map_size;
314338 };
315339
@@ -324,6 +348,7 @@ struct drm_amdgpu_gem_va { · 8 unmodified lines
324348
325349 #define AMDGPU_CHUNK_ID_IB 0x01
326350 #define AMDGPU_CHUNK_ID_FENCE 0x02
351+
327352 struct drm_amdgpu_cs_chunk {
328353 uint32_t chunk_id;
329354 uint32_t length_dw;
@@ -337,7 +362,7 @@ struct drm_amdgpu_cs_in { · 7 unmodified lines
337362 uint32_t bo_list_handle;
338363 uint32_t num_chunks;
339364 uint32_t _pad;
340− /* this points to uint64_t * which point to cs chunks */
365+ /** this points to uint64_t * which point to cs chunks */
341366 uint64_t chunks;
342367 };
343368
@@ -346,8 +371,8 @@ struct drm_amdgpu_cs_out { · 2 unmodified lines
346371 };
347372
348373 union drm_amdgpu_cs {
349− struct drm_amdgpu_cs_in in;
350− struct drm_amdgpu_cs_out out;
374+ struct drm_amdgpu_cs_in in;
375+ struct drm_amdgpu_cs_out out;
351376 };
352377
353378 /* Specify flags to be used for IB */
@@ -360,12 +385,18 @@ union drm_amdgpu_cs { · 6 unmodified lines
360385
361386 struct drm_amdgpu_cs_chunk_ib {
362387 uint32_t _pad;
363− uint32_t flags; /* IB Flags */
364− uint64_t va_start; /* Virtual address to begin IB execution */
365− uint32_t ib_bytes; /* Size of submission */
366− uint32_t ip_type; /* HW IP to submit to */
367− uint32_t ip_instance; /* HW IP index of the same type to submit to */
368− uint32_t ring; /* Ring index to submit to */
388+ /** AMDGPU_IB_FLAG_* */
389+ uint32_t flags;
390+ /** Virtual address to begin IB execution */
391+ uint64_t va_start;
392+ /** Size of submission */
393+ uint32_t ib_bytes;
394+ /** HW IP to submit to */
395+ uint32_t ip_type;
396+ /** HW IP index of the same type to submit to */
397+ uint32_t ip_instance;
398+ /** Ring index to submit to */
399+ uint32_t ring;
369400 };
370401
371402 struct drm_amdgpu_cs_chunk_fence {
@@ -460,23 +491,28 @@ struct drm_amdgpu_info { · 88 unmodified lines
460491 /** AMDGPU_HW_IP_* */
461492 uint32_t type;
462493 /**
463− * Index of the IP if there are more IPs of the same type.
464− * Ignored by AMDGPU_INFO_HW_IP_COUNT.
494+ * Index of the IP if there are more IPs of the same
495+ * type. Ignored by AMDGPU_INFO_HW_IP_COUNT.
465496 */
466497 uint32_t ip_instance;
467498 } query_hw_ip;
468499
469500 struct {
470501 uint32_t dword_offset;
471− uint32_t count; /* number of registers to read */
502+ /** number of registers to read */
503+ uint32_t count;
472504 uint32_t instance;
505+ /** For future use, no flags defined so far */
473506 uint32_t flags;
474507 } read_mmr_reg;
475508
476509 struct {
477510 /** AMDGPU_INFO_FW_* */
478511 uint32_t fw_type;
479− /** Index of the IP if there are more IPs of the same type. */
512+ /**
513+ * Index of the IP if there are more IPs of
514+ * the same type.
515+ */
480516 uint32_t ip_instance;
481517 /**
482518 * Index of the engine. Whether this is used depends
@@ -537,9 +573,10 @@ struct drm_amdgpu_info_device { · 54 unmodified lines
537573 uint32_t family;
538574 uint32_t num_shader_engines;
539575 uint32_t num_shader_arrays_per_engine;
540− uint32_t gpu_counter_freq; /* in KHz */
541− uint64_t max_engine_clock; /* in KHz */
542− uint64_t max_memory_clock; /* in KHz */
576+ /* in KHz */
577+ uint32_t gpu_counter_freq;
578+ uint64_t max_engine_clock;
579+ uint64_t max_memory_clock;
543580 /* cu information */
544581 uint32_t cu_active_number;
545582 uint32_t cu_ao_mask;