New chunk for dependency on start of job's execution instead on the end. This is used for GPU deadlock prevention when userspace uses mid-IB fences to wait for mid-IB work on other rings. v2: Fix typo in AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES v3: Bump KMS version v4: put old fence AFTER acquiring the scheduled fence.
Unified · Split
| @@ -214,6 +214,7 @@ static int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, union drm_amdgpu_cs · 213 unmodified lines | |||
| 214 | case AMDGPU_CHUNK_ID_DEPENDENCIES: | 214 | case AMDGPU_CHUNK_ID_DEPENDENCIES: |
| 215 | case AMDGPU_CHUNK_ID_SYNCOBJ_IN: | 215 | case AMDGPU_CHUNK_ID_SYNCOBJ_IN: |
| 216 | case AMDGPU_CHUNK_ID_SYNCOBJ_OUT: | 216 | case AMDGPU_CHUNK_ID_SYNCOBJ_OUT: |
| 217 | case AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES: | ||
| 217 | break; | 218 | break; |
| 218 | 219 | ||
| 219 | default: | 220 | default: |
| @@ -1090,6 +1091,15 @@ static int amdgpu_cs_process_fence_dep(struct amdgpu_cs_parser *p, · 870 unmodified lines | |||
| 1090 | 1091 | ||
| 1091 | fence = amdgpu_ctx_get_fence(ctx, entity, | 1092 | fence = amdgpu_ctx_get_fence(ctx, entity, |
| 1092 | deps[i].handle); | 1093 | deps[i].handle); |
| 1094 | |||
| 1095 | if (chunk->chunk_id == AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES) { | ||
| 1096 | struct drm_sched_fence *s_fence = to_drm_sched_fence(fence); | ||
| 1097 | struct dma_fence *old = fence; | ||
| 1098 | |||
| 1099 | fence = dma_fence_get(&s_fence->scheduled); | ||
| 1100 | dma_fence_put(old); | ||
| 1101 | } | ||
| 1102 | |||
| 1093 | if (IS_ERR(fence)) { | 1103 | if (IS_ERR(fence)) { |
| 1094 | r = PTR_ERR(fence); | 1104 | r = PTR_ERR(fence); |
| 1095 | amdgpu_ctx_put(ctx); | 1105 | amdgpu_ctx_put(ctx); |
| @@ -1177,7 +1187,8 @@ static int amdgpu_cs_dependencies(struct amdgpu_device *adev, · 81 unmodified lines | |||
| 1177 | 1187 | ||
| 1178 | chunk = &p->chunks[i]; | 1188 | chunk = &p->chunks[i]; |
| 1179 | 1189 | ||
| 1180 | if (chunk->chunk_id == AMDGPU_CHUNK_ID_DEPENDENCIES) { | 1190 | if (chunk->chunk_id == AMDGPU_CHUNK_ID_DEPENDENCIES || |
| 1191 | chunk->chunk_id == AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES) { | ||
| 1181 | r = amdgpu_cs_process_fence_dep(p, chunk); | 1192 | r = amdgpu_cs_process_fence_dep(p, chunk); |
| 1182 | if (r) | 1193 | if (r) |
| 1183 | return r; | 1194 | return r; |
| @@ -71,9 +71,10 @@ · 70 unmodified lines | |||
| 71 | * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk). | 71 | * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk). |
| 72 | * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE. | 72 | * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE. |
| 73 | * - 3.27.0 - Add new chunk to to AMDGPU_CS to enable BO_LIST creation. | 73 | * - 3.27.0 - Add new chunk to to AMDGPU_CS to enable BO_LIST creation. |
| 74 | * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES | ||
| 74 | */ | 75 | */ |
| 75 | #define KMS_DRIVER_MAJOR 3 | 76 | #define KMS_DRIVER_MAJOR 3 |
| 76 | #define KMS_DRIVER_MINOR 27 | 77 | #define KMS_DRIVER_MINOR 28 |
| 77 | #define KMS_DRIVER_PATCHLEVEL 0 | 78 | #define KMS_DRIVER_PATCHLEVEL 0 |
| 78 | 79 | ||
| 79 | int amdgpu_vram_limit = 0; | 80 | int amdgpu_vram_limit = 0; |
| @@ -523,6 +523,7 @@ struct drm_amdgpu_gem_va { · 522 unmodified lines | |||
| 523 | #define AMDGPU_CHUNK_ID_SYNCOBJ_IN 0x04 | 523 | #define AMDGPU_CHUNK_ID_SYNCOBJ_IN 0x04 |
| 524 | #define AMDGPU_CHUNK_ID_SYNCOBJ_OUT 0x05 | 524 | #define AMDGPU_CHUNK_ID_SYNCOBJ_OUT 0x05 |
| 525 | #define AMDGPU_CHUNK_ID_BO_HANDLES 0x06 | 525 | #define AMDGPU_CHUNK_ID_BO_HANDLES 0x06 |
| 526 | #define AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 0x07 | ||
| 526 | 527 | ||
| 527 | struct drm_amdgpu_cs_chunk { | 528 | struct drm_amdgpu_cs_chunk { |
| 528 | __u32 chunk_id; | 529 | __u32 chunk_id; |